{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1639713018149 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.0 Build 156 04/24/2013 SJ Full Version " "Version 13.0.0 Build 156 04/24/2013 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1639713018149 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Dec 17 11:50:18 2021 " "Processing started: Fri Dec 17 11:50:18 2021" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1639713018149 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1639713018149 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off eda2 -c eda2 " "Command: quartus_map --read_settings_files=on --write_settings_files=off eda2 -c eda2" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1639713018150 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS_MORE_LOGICAL" "6 6 12 " "Parallel Compilation has detected 12 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 6 of the 6 physical processors detected instead." {  } {  } 0 11104 "Parallel Compilation has detected %3!i! hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use %1!i! of the %2!i! physical processors detected instead." 0 0 "Quartus II" 0 -1 1639713018427 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "IN_5c in_5c eda2.v(362) " "Verilog HDL Declaration information at eda2.v(362): object \"IN_5c\" differs only in case from object \"in_5c\" in the same scope" {  } { { "eda2.v" "" { Text "C:/Users/Xsu1023/Desktop/eda2_/eda2.v" 362 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Quartus II" 0 -1 1639713018463 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "IN_10c in_10c eda2.v(362) " "Verilog HDL Declaration information at eda2.v(362): object \"IN_10c\" differs only in case from object \"in_10c\" in the same scope" {  } { { "eda2.v" "" { Text "C:/Users/Xsu1023/Desktop/eda2_/eda2.v" 362 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Quartus II" 0 -1 1639713018464 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "IN_50c in_50c eda2.v(362) " "Verilog HDL Declaration information at eda2.v(362): object \"IN_50c\" differs only in case from object \"in_50c\" in the same scope" {  } { { "eda2.v" "" { Text "C:/Users/Xsu1023/Desktop/eda2_/eda2.v" 362 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Quartus II" 0 -1 1639713018464 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "OUT_15c out_15c eda2.v(362) " "Verilog HDL Declaration information at eda2.v(362): object \"OUT_15c\" differs only in case from object \"out_15c\" in the same scope" {  } { { "eda2.v" "" { Text "C:/Users/Xsu1023/Desktop/eda2_/eda2.v" 362 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Quartus II" 0 -1 1639713018464 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "OUT_25c out_25c eda2.v(362) " "Verilog HDL Declaration information at eda2.v(362): object \"OUT_25c\" differs only in case from object \"out_25c\" in the same scope" {  } { { "eda2.v" "" { Text "C:/Users/Xsu1023/Desktop/eda2_/eda2.v" 362 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Quartus II" 0 -1 1639713018464 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "eda2.v 9 9 " "Found 9 design units, including 9 entities, in source file eda2.v" { { "Info" "ISGN_ENTITY_NAME" "1 debounce " "Found entity 1: debounce" {  } { { "eda2.v" "" { Text "C:/Users/Xsu1023/Desktop/eda2_/eda2.v" 14 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1639713018465 ""} { "Info" "ISGN_ENTITY_NAME" "2 clock " "Found entity 2: clock" {  } { { "eda2.v" "" { Text "C:/Users/Xsu1023/Desktop/eda2_/eda2.v" 52 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1639713018465 ""} { "Info" "ISGN_ENTITY_NAME" "3 numbertranslator " "Found entity 3: numbertranslator" {  } { { "eda2.v" "" { Text "C:/Users/Xsu1023/Desktop/eda2_/eda2.v" 72 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1639713018465 ""} { "Info" "ISGN_ENTITY_NAME" "4 gettempnumber " "Found entity 4: gettempnumber" {  } { { "eda2.v" "" { Text "C:/Users/Xsu1023/Desktop/eda2_/eda2.v" 101 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1639713018465 ""} { "Info" "ISGN_ENTITY_NAME" "5 segtranslator " "Found entity 5: segtranslator" {  } { { "eda2.v" "" { Text "C:/Users/Xsu1023/Desktop/eda2_/eda2.v" 123 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1639713018465 ""} { "Info" "ISGN_ENTITY_NAME" "6 counter " "Found entity 6: counter" {  } { { "eda2.v" "" { Text "C:/Users/Xsu1023/Desktop/eda2_/eda2.v" 145 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1639713018465 ""} { "Info" "ISGN_ENTITY_NAME" "7 FSM " "Found entity 7: FSM" {  } { { "eda2.v" "" { Text "C:/Users/Xsu1023/Desktop/eda2_/eda2.v" 172 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1639713018465 ""} { "Info" "ISGN_ENTITY_NAME" "8 calculator " "Found entity 8: calculator" {  } { { "eda2.v" "" { Text "C:/Users/Xsu1023/Desktop/eda2_/eda2.v" 266 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1639713018465 ""} { "Info" "ISGN_ENTITY_NAME" "9 eda2 " "Found entity 9: eda2" {  } { { "eda2.v" "" { Text "C:/Users/Xsu1023/Desktop/eda2_/eda2.v" 350 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1639713018465 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1639713018465 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "eda2 " "Elaborating entity \"eda2\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1639713018522 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "debounce debounce:in_5c " "Elaborating entity \"debounce\" for hierarchy \"debounce:in_5c\"" {  } { { "eda2.v" "in_5c" { Text "C:/Users/Xsu1023/Desktop/eda2_/eda2.v" 365 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1639713018525 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 eda2.v(40) " "Verilog HDL assignment warning at eda2.v(40): truncated value with size 32 to match size of target (8)" {  } { { "eda2.v" "" { Text "C:/Users/Xsu1023/Desktop/eda2_/eda2.v" 40 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1639713018525 "|eda2|debounce:in_5c"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clock clock:my_clock " "Elaborating entity \"clock\" for hierarchy \"clock:my_clock\"" {  } { { "eda2.v" "my_clock" { Text "C:/Users/Xsu1023/Desktop/eda2_/eda2.v" 372 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1639713018529 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 31 eda2.v(58) " "Verilog HDL assignment warning at eda2.v(58): truncated value with size 32 to match size of target (31)" {  } { { "eda2.v" "" { Text "C:/Users/Xsu1023/Desktop/eda2_/eda2.v" 58 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1639713018530 "|eda2|clock:my_clock"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "FSM FSM:my_FSM " "Elaborating entity \"FSM\" for hierarchy \"FSM:my_FSM\"" {  } { { "eda2.v" "my_FSM" { Text "C:/Users/Xsu1023/Desktop/eda2_/eda2.v" 375 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1639713018531 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "calculator calculator:my_calculator " "Elaborating entity \"calculator\" for hierarchy \"calculator:my_calculator\"" {  } { { "eda2.v" "my_calculator" { Text "C:/Users/Xsu1023/Desktop/eda2_/eda2.v" 376 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1639713018533 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 eda2.v(301) " "Verilog HDL assignment warning at eda2.v(301): truncated value with size 32 to match size of target (10)" {  } { { "eda2.v" "" { Text "C:/Users/Xsu1023/Desktop/eda2_/eda2.v" 301 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1639713018535 "|eda2|calculator:my_calculator"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 eda2.v(306) " "Verilog HDL assignment warning at eda2.v(306): truncated value with size 32 to match size of target (10)" {  } { { "eda2.v" "" { Text "C:/Users/Xsu1023/Desktop/eda2_/eda2.v" 306 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1639713018535 "|eda2|calculator:my_calculator"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 eda2.v(311) " "Verilog HDL assignment warning at eda2.v(311): truncated value with size 32 to match size of target (10)" {  } { { "eda2.v" "" { Text "C:/Users/Xsu1023/Desktop/eda2_/eda2.v" 311 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1639713018535 "|eda2|calculator:my_calculator"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 eda2.v(317) " "Verilog HDL assignment warning at eda2.v(317): truncated value with size 32 to match size of target (10)" {  } { { "eda2.v" "" { Text "C:/Users/Xsu1023/Desktop/eda2_/eda2.v" 317 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1639713018535 "|eda2|calculator:my_calculator"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 eda2.v(326) " "Verilog HDL assignment warning at eda2.v(326): truncated value with size 32 to match size of target (10)" {  } { { "eda2.v" "" { Text "C:/Users/Xsu1023/Desktop/eda2_/eda2.v" 326 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1639713018535 "|eda2|calculator:my_calculator"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 9 eda2.v(333) " "Verilog HDL assignment warning at eda2.v(333): truncated value with size 32 to match size of target (9)" {  } { { "eda2.v" "" { Text "C:/Users/Xsu1023/Desktop/eda2_/eda2.v" 333 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1639713018535 "|eda2|calculator:my_calculator"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "counter counter:my_counter " "Elaborating entity \"counter\" for hierarchy \"counter:my_counter\"" {  } { { "eda2.v" "my_counter" { Text "C:/Users/Xsu1023/Desktop/eda2_/eda2.v" 379 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1639713018536 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 eda2.v(150) " "Verilog HDL assignment warning at eda2.v(150): truncated value with size 32 to match size of target (2)" {  } { { "eda2.v" "" { Text "C:/Users/Xsu1023/Desktop/eda2_/eda2.v" 150 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1639713018537 "|eda2|counter:my_counter"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "segtranslator segtranslator:my_segtranslator " "Elaborating entity \"segtranslator\" for hierarchy \"segtranslator:my_segtranslator\"" {  } { { "eda2.v" "my_segtranslator" { Text "C:/Users/Xsu1023/Desktop/eda2_/eda2.v" 380 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1639713018538 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "gettempnumber gettempnumber:my_gettempnumber " "Elaborating entity \"gettempnumber\" for hierarchy \"gettempnumber:my_gettempnumber\"" {  } { { "eda2.v" "my_gettempnumber" { Text "C:/Users/Xsu1023/Desktop/eda2_/eda2.v" 381 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1639713018540 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 eda2.v(108) " "Verilog HDL assignment warning at eda2.v(108): truncated value with size 32 to match size of target (5)" {  } { { "eda2.v" "" { Text "C:/Users/Xsu1023/Desktop/eda2_/eda2.v" 108 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1639713018541 "|eda2|gettempnumber:my_gettempnumber"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 eda2.v(109) " "Verilog HDL assignment warning at eda2.v(109): truncated value with size 32 to match size of target (5)" {  } { { "eda2.v" "" { Text "C:/Users/Xsu1023/Desktop/eda2_/eda2.v" 109 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1639713018541 "|eda2|gettempnumber:my_gettempnumber"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 eda2.v(110) " "Verilog HDL assignment warning at eda2.v(110): truncated value with size 32 to match size of target (5)" {  } { { "eda2.v" "" { Text "C:/Users/Xsu1023/Desktop/eda2_/eda2.v" 110 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1639713018541 "|eda2|gettempnumber:my_gettempnumber"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "numbertranslator numbertranslator:my_numbertranslator " "Elaborating entity \"numbertranslator\" for hierarchy \"numbertranslator:my_numbertranslator\"" {  } { { "eda2.v" "my_numbertranslator" { Text "C:/Users/Xsu1023/Desktop/eda2_/eda2.v" 382 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1639713018542 ""}
{ "Info" "ILPMS_INFERENCING_SUMMARY" "5 " "Inferred 5 megafunctions from design logic" { { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "gettempnumber:my_gettempnumber\|Div0 lpm_divide " "Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"gettempnumber:my_gettempnumber\|Div0\"" {  } { { "eda2.v" "Div0" { Text "C:/Users/Xsu1023/Desktop/eda2_/eda2.v" 108 -1 0 } }  } 0 278004 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1639713018792 ""} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "gettempnumber:my_gettempnumber\|Mod0 lpm_divide " "Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"gettempnumber:my_gettempnumber\|Mod0\"" {  } { { "eda2.v" "Mod0" { Text "C:/Users/Xsu1023/Desktop/eda2_/eda2.v" 108 -1 0 } }  } 0 278004 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1639713018792 ""} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "gettempnumber:my_gettempnumber\|Div1 lpm_divide " "Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"gettempnumber:my_gettempnumber\|Div1\"" {  } { { "eda2.v" "Div1" { Text "C:/Users/Xsu1023/Desktop/eda2_/eda2.v" 109 -1 0 } }  } 0 278004 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1639713018792 ""} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "gettempnumber:my_gettempnumber\|Mod1 lpm_divide " "Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"gettempnumber:my_gettempnumber\|Mod1\"" {  } { { "eda2.v" "Mod1" { Text "C:/Users/Xsu1023/Desktop/eda2_/eda2.v" 109 -1 0 } }  } 0 278004 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1639713018792 ""} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "gettempnumber:my_gettempnumber\|Mod2 lpm_divide " "Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"gettempnumber:my_gettempnumber\|Mod2\"" {  } { { "eda2.v" "Mod2" { Text "C:/Users/Xsu1023/Desktop/eda2_/eda2.v" 110 -1 0 } }  } 0 278004 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1639713018792 ""}  } {  } 0 278001 "Inferred %1!llu! megafunctions from design logic" 0 0 "Quartus II" 0 -1 1639713018792 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "gettempnumber:my_gettempnumber\|lpm_divide:Div0 " "Elaborated megafunction instantiation \"gettempnumber:my_gettempnumber\|lpm_divide:Div0\"" {  } { { "eda2.v" "" { Text "C:/Users/Xsu1023/Desktop/eda2_/eda2.v" 108 -1 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1639713018824 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "gettempnumber:my_gettempnumber\|lpm_divide:Div0 " "Instantiated megafunction \"gettempnumber:my_gettempnumber\|lpm_divide:Div0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHN 10 " "Parameter \"LPM_WIDTHN\" = \"10\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1639713018825 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHD 7 " "Parameter \"LPM_WIDTHD\" = \"7\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1639713018825 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_NREPRESENTATION UNSIGNED " "Parameter \"LPM_NREPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1639713018825 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DREPRESENTATION UNSIGNED " "Parameter \"LPM_DREPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1639713018825 ""}  } { { "eda2.v" "" { Text "C:/Users/Xsu1023/Desktop/eda2_/eda2.v" 108 -1 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1639713018825 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_mhm.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/lpm_divide_mhm.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_mhm " "Found entity 1: lpm_divide_mhm" {  } { { "db/lpm_divide_mhm.tdf" "" { Text "C:/Users/Xsu1023/Desktop/eda2_/db/lpm_divide_mhm.tdf" 24 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1639713018876 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1639713018876 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/sign_div_unsign_nlh.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/sign_div_unsign_nlh.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 sign_div_unsign_nlh " "Found entity 1: sign_div_unsign_nlh" {  } { { "db/sign_div_unsign_nlh.tdf" "" { Text "C:/Users/Xsu1023/Desktop/eda2_/db/sign_div_unsign_nlh.tdf" 24 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1639713018889 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1639713018889 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/alt_u_div_p5f.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/alt_u_div_p5f.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_u_div_p5f " "Found entity 1: alt_u_div_p5f" {  } { { "db/alt_u_div_p5f.tdf" "" { Text "C:/Users/Xsu1023/Desktop/eda2_/db/alt_u_div_p5f.tdf" 26 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1639713018909 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1639713018909 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_unc.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/add_sub_unc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_unc " "Found entity 1: add_sub_unc" {  } { { "db/add_sub_unc.tdf" "" { Text "C:/Users/Xsu1023/Desktop/eda2_/db/add_sub_unc.tdf" 22 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1639713018965 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1639713018965 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_vnc.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/add_sub_vnc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_vnc " "Found entity 1: add_sub_vnc" {  } { { "db/add_sub_vnc.tdf" "" { Text "C:/Users/Xsu1023/Desktop/eda2_/db/add_sub_vnc.tdf" 22 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1639713019017 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1639713019017 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "gettempnumber:my_gettempnumber\|lpm_divide:Mod0 " "Elaborated megafunction instantiation \"gettempnumber:my_gettempnumber\|lpm_divide:Mod0\"" {  } { { "eda2.v" "" { Text "C:/Users/Xsu1023/Desktop/eda2_/eda2.v" 108 -1 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1639713019024 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "gettempnumber:my_gettempnumber\|lpm_divide:Mod0 " "Instantiated megafunction \"gettempnumber:my_gettempnumber\|lpm_divide:Mod0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHN 10 " "Parameter \"LPM_WIDTHN\" = \"10\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1639713019024 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHD 4 " "Parameter \"LPM_WIDTHD\" = \"4\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1639713019024 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_NREPRESENTATION UNSIGNED " "Parameter \"LPM_NREPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1639713019024 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DREPRESENTATION UNSIGNED " "Parameter \"LPM_DREPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1639713019024 ""}  } { { "eda2.v" "" { Text "C:/Users/Xsu1023/Desktop/eda2_/eda2.v" 108 -1 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1639713019024 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_m9m.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/lpm_divide_m9m.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_m9m " "Found entity 1: lpm_divide_m9m" {  } { { "db/lpm_divide_m9m.tdf" "" { Text "C:/Users/Xsu1023/Desktop/eda2_/db/lpm_divide_m9m.tdf" 24 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1639713019075 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1639713019075 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/sign_div_unsign_klh.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/sign_div_unsign_klh.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 sign_div_unsign_klh " "Found entity 1: sign_div_unsign_klh" {  } { { "db/sign_div_unsign_klh.tdf" "" { Text "C:/Users/Xsu1023/Desktop/eda2_/db/sign_div_unsign_klh.tdf" 24 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1639713019091 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1639713019091 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/alt_u_div_j5f.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/alt_u_div_j5f.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_u_div_j5f " "Found entity 1: alt_u_div_j5f" {  } { { "db/alt_u_div_j5f.tdf" "" { Text "C:/Users/Xsu1023/Desktop/eda2_/db/alt_u_div_j5f.tdf" 26 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1639713019109 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1639713019109 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "gettempnumber:my_gettempnumber\|lpm_divide:Div1 " "Elaborated megafunction instantiation \"gettempnumber:my_gettempnumber\|lpm_divide:Div1\"" {  } { { "eda2.v" "" { Text "C:/Users/Xsu1023/Desktop/eda2_/eda2.v" 109 -1 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1639713019119 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "gettempnumber:my_gettempnumber\|lpm_divide:Div1 " "Instantiated megafunction \"gettempnumber:my_gettempnumber\|lpm_divide:Div1\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHN 10 " "Parameter \"LPM_WIDTHN\" = \"10\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1639713019119 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHD 4 " "Parameter \"LPM_WIDTHD\" = \"4\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1639713019119 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_NREPRESENTATION UNSIGNED " "Parameter \"LPM_NREPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1639713019119 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DREPRESENTATION UNSIGNED " "Parameter \"LPM_DREPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1639713019119 ""}  } { { "eda2.v" "" { Text "C:/Users/Xsu1023/Desktop/eda2_/eda2.v" 109 -1 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1639713019119 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_jhm.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/lpm_divide_jhm.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_jhm " "Found entity 1: lpm_divide_jhm" {  } { { "db/lpm_divide_jhm.tdf" "" { Text "C:/Users/Xsu1023/Desktop/eda2_/db/lpm_divide_jhm.tdf" 24 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1639713019168 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1639713019168 ""}
{ "Warning" "WSGN_CONNECTIVITY_WARNINGS" "1 " "1 hierarchies have connectivity warnings - see the Connectivity Checks report folder" {  } {  } 0 12241 "%1!d! hierarchies have connectivity warnings - see the Connectivity Checks report folder" 0 0 "Quartus II" 0 -1 1639713019361 ""}
{ "Info" "IMLS_MLS_PRESET_POWER_UP" "" "Registers with preset signals will power-up high" {  } { { "eda2.v" "" { Text "C:/Users/Xsu1023/Desktop/eda2_/eda2.v" 282 -1 0 } }  } 0 13000 "Registers with preset signals will power-up high" 0 0 "Quartus II" 0 -1 1639713019380 ""}
{ "Info" "IMLS_MLS_DEV_CLRN_SETS_REGISTERS" "" "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" {  } {  } 0 13003 "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" 0 0 "Quartus II" 0 -1 1639713019380 ""}
{ "Warning" "WMLS_MLS_CREATED_ALOAD_CCT" "" "Presettable and clearable registers converted to equivalent circuits with latches. Registers power-up to an undefined state, and DEVCLRn places the registers in an undefined state." { { "Warning" "WMLS_MLS_CREATED_ALOAD_CCT_SUB" "debounce:in_10c\|out debounce:in_10c\|out~_emulated debounce:in_10c\|out~1 " "Register \"debounce:in_10c\|out\" is converted into an equivalent circuit using register \"debounce:in_10c\|out~_emulated\" and latch \"debounce:in_10c\|out~1\"" {  } { { "eda2.v" "" { Text "C:/Users/Xsu1023/Desktop/eda2_/eda2.v" 17 -1 0 } }  } 0 13310 "Register \"%1!s!\" is converted into an equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0 "Quartus II" 0 -1 1639713019381 "|eda2|debounce:in_10c|out"} { "Warning" "WMLS_MLS_CREATED_ALOAD_CCT_SUB" "debounce:in_5c\|out debounce:in_5c\|out~_emulated debounce:in_5c\|out~1 " "Register \"debounce:in_5c\|out\" is converted into an equivalent circuit using register \"debounce:in_5c\|out~_emulated\" and latch \"debounce:in_5c\|out~1\"" {  } { { "eda2.v" "" { Text "C:/Users/Xsu1023/Desktop/eda2_/eda2.v" 17 -1 0 } }  } 0 13310 "Register \"%1!s!\" is converted into an equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0 "Quartus II" 0 -1 1639713019381 "|eda2|debounce:in_5c|out"} { "Warning" "WMLS_MLS_CREATED_ALOAD_CCT_SUB" "debounce:in_50c\|out debounce:in_50c\|out~_emulated debounce:in_50c\|out~1 " "Register \"debounce:in_50c\|out\" is converted into an equivalent circuit using register \"debounce:in_50c\|out~_emulated\" and latch \"debounce:in_50c\|out~1\"" {  } { { "eda2.v" "" { Text "C:/Users/Xsu1023/Desktop/eda2_/eda2.v" 17 -1 0 } }  } 0 13310 "Register \"%1!s!\" is converted into an equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0 "Quartus II" 0 -1 1639713019381 "|eda2|debounce:in_50c|out"} { "Warning" "WMLS_MLS_CREATED_ALOAD_CCT_SUB" "debounce:out_15c\|out debounce:out_15c\|out~_emulated debounce:out_15c\|out~1 " "Register \"debounce:out_15c\|out\" is converted into an equivalent circuit using register \"debounce:out_15c\|out~_emulated\" and latch \"debounce:out_15c\|out~1\"" {  } { { "eda2.v" "" { Text "C:/Users/Xsu1023/Desktop/eda2_/eda2.v" 17 -1 0 } }  } 0 13310 "Register \"%1!s!\" is converted into an equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0 "Quartus II" 0 -1 1639713019381 "|eda2|debounce:out_15c|out"} { "Warning" "WMLS_MLS_CREATED_ALOAD_CCT_SUB" "debounce:out_25c\|out debounce:out_25c\|out~_emulated debounce:out_25c\|out~1 " "Register \"debounce:out_25c\|out\" is converted into an equivalent circuit using register \"debounce:out_25c\|out~_emulated\" and latch \"debounce:out_25c\|out~1\"" {  } { { "eda2.v" "" { Text "C:/Users/Xsu1023/Desktop/eda2_/eda2.v" 17 -1 0 } }  } 0 13310 "Register \"%1!s!\" is converted into an equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0 "Quartus II" 0 -1 1639713019381 "|eda2|debounce:out_25c|out"} { "Warning" "WMLS_MLS_CREATED_ALOAD_CCT_SUB" "debounce:in_10c\|last debounce:in_10c\|last~_emulated debounce:in_10c\|out~1 " "Register \"debounce:in_10c\|last\" is converted into an equivalent circuit using register \"debounce:in_10c\|last~_emulated\" and latch \"debounce:in_10c\|out~1\"" {  } { { "eda2.v" "" { Text "C:/Users/Xsu1023/Desktop/eda2_/eda2.v" 21 -1 0 } }  } 0 13310 "Register \"%1!s!\" is converted into an equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0 "Quartus II" 0 -1 1639713019381 "|eda2|debounce:in_10c|last"} { "Warning" "WMLS_MLS_CREATED_ALOAD_CCT_SUB" "debounce:in_5c\|last debounce:in_5c\|last~_emulated debounce:in_5c\|out~1 " "Register \"debounce:in_5c\|last\" is converted into an equivalent circuit using register \"debounce:in_5c\|last~_emulated\" and latch \"debounce:in_5c\|out~1\"" {  } { { "eda2.v" "" { Text "C:/Users/Xsu1023/Desktop/eda2_/eda2.v" 21 -1 0 } }  } 0 13310 "Register \"%1!s!\" is converted into an equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0 "Quartus II" 0 -1 1639713019381 "|eda2|debounce:in_5c|last"} { "Warning" "WMLS_MLS_CREATED_ALOAD_CCT_SUB" "debounce:in_50c\|last debounce:in_50c\|last~_emulated debounce:in_50c\|out~1 " "Register \"debounce:in_50c\|last\" is converted into an equivalent circuit using register \"debounce:in_50c\|last~_emulated\" and latch \"debounce:in_50c\|out~1\"" {  } { { "eda2.v" "" { Text "C:/Users/Xsu1023/Desktop/eda2_/eda2.v" 21 -1 0 } }  } 0 13310 "Register \"%1!s!\" is converted into an equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0 "Quartus II" 0 -1 1639713019381 "|eda2|debounce:in_50c|last"} { "Warning" "WMLS_MLS_CREATED_ALOAD_CCT_SUB" "debounce:out_15c\|last debounce:out_15c\|last~_emulated debounce:out_15c\|out~1 " "Register \"debounce:out_15c\|last\" is converted into an equivalent circuit using register \"debounce:out_15c\|last~_emulated\" and latch \"debounce:out_15c\|out~1\"" {  } { { "eda2.v" "" { Text "C:/Users/Xsu1023/Desktop/eda2_/eda2.v" 21 -1 0 } }  } 0 13310 "Register \"%1!s!\" is converted into an equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0 "Quartus II" 0 -1 1639713019381 "|eda2|debounce:out_15c|last"} { "Warning" "WMLS_MLS_CREATED_ALOAD_CCT_SUB" "debounce:out_25c\|last debounce:out_25c\|last~_emulated debounce:out_25c\|out~1 " "Register \"debounce:out_25c\|last\" is converted into an equivalent circuit using register \"debounce:out_25c\|last~_emulated\" and latch \"debounce:out_25c\|out~1\"" {  } { { "eda2.v" "" { Text "C:/Users/Xsu1023/Desktop/eda2_/eda2.v" 21 -1 0 } }  } 0 13310 "Register \"%1!s!\" is converted into an equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0 "Quartus II" 0 -1 1639713019381 "|eda2|debounce:out_25c|last"}  } {  } 0 13004 "Presettable and clearable registers converted to equivalent circuits with latches. Registers power-up to an undefined state, and DEVCLRn places the registers in an undefined state." 0 0 "Quartus II" 0 -1 1639713019381 ""}
{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "segout\[0\] VCC " "Pin \"segout\[0\]\" is stuck at VCC" {  } { { "eda2.v" "" { Text "C:/Users/Xsu1023/Desktop/eda2_/eda2.v" 353 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1639713019519 "|eda2|segout[0]"} { "Warning" "WMLS_MLS_STUCK_PIN" "segout\[1\] VCC " "Pin \"segout\[1\]\" is stuck at VCC" {  } { { "eda2.v" "" { Text "C:/Users/Xsu1023/Desktop/eda2_/eda2.v" 353 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1639713019519 "|eda2|segout[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "segout\[2\] VCC " "Pin \"segout\[2\]\" is stuck at VCC" {  } { { "eda2.v" "" { Text "C:/Users/Xsu1023/Desktop/eda2_/eda2.v" 353 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1639713019519 "|eda2|segout[2]"}  } {  } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Quartus II" 0 -1 1639713019519 ""}
{ "Critical Warning" "WFTM_FTM_POWER_UP_HIGH_IGNORED_GROUP" "" "Ignored Power-Up Level option on the following registers" { { "Critical Warning" "WFTM_FTM_CORE_REG_POWER_UP_HIGH_IGNORED" "calculator:my_calculator\|clear High " "Register calculator:my_calculator\|clear will power up to High" {  } { { "eda2.v" "" { Text "C:/Users/Xsu1023/Desktop/eda2_/eda2.v" 282 -1 0 } }  } 1 18010 "Register %1!s! will power up to %2!s!" 0 0 "Quartus II" 0 -1 1639713019523 ""}  } {  } 1 18061 "Ignored Power-Up Level option on the following registers" 0 0 "Quartus II" 0 -1 1639713019523 ""}
{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" {  } {  } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Quartus II" 0 -1 1639713019629 ""}
{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "18 " "18 registers lost all their fanouts during netlist optimizations." {  } {  } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Quartus II" 0 -1 1639713019944 ""}
{ "Info" "ISCL_SCL_WANNA_REM_USR_WIRE" "" "Found the following redundant logic cells in design" { { "Info" "ISCL_SCL_CELL_NAME" "gettempnumber:my_gettempnumber\|lpm_divide:Mod1\|lpm_divide_m9m:auto_generated\|sign_div_unsign_klh:divider\|alt_u_div_j5f:divider\|add_sub_6_result_int\[0\]~10 " "Logic cell \"gettempnumber:my_gettempnumber\|lpm_divide:Mod1\|lpm_divide_m9m:auto_generated\|sign_div_unsign_klh:divider\|alt_u_div_j5f:divider\|add_sub_6_result_int\[0\]~10\"" {  } { { "db/alt_u_div_j5f.tdf" "add_sub_6_result_int\[0\]~10" { Text "C:/Users/Xsu1023/Desktop/eda2_/db/alt_u_div_j5f.tdf" 56 22 0 } }  } 0 17048 "Logic cell \"%1!s!\"" 0 0 "Quartus II" 0 -1 1639713019948 ""} { "Info" "ISCL_SCL_CELL_NAME" "gettempnumber:my_gettempnumber\|lpm_divide:Mod1\|lpm_divide_m9m:auto_generated\|sign_div_unsign_klh:divider\|alt_u_div_j5f:divider\|add_sub_7_result_int\[0\]~10 " "Logic cell \"gettempnumber:my_gettempnumber\|lpm_divide:Mod1\|lpm_divide_m9m:auto_generated\|sign_div_unsign_klh:divider\|alt_u_div_j5f:divider\|add_sub_7_result_int\[0\]~10\"" {  } { { "db/alt_u_div_j5f.tdf" "add_sub_7_result_int\[0\]~10" { Text "C:/Users/Xsu1023/Desktop/eda2_/db/alt_u_div_j5f.tdf" 61 22 0 } }  } 0 17048 "Logic cell \"%1!s!\"" 0 0 "Quartus II" 0 -1 1639713019948 ""} { "Info" "ISCL_SCL_CELL_NAME" "gettempnumber:my_gettempnumber\|lpm_divide:Mod1\|lpm_divide_m9m:auto_generated\|sign_div_unsign_klh:divider\|alt_u_div_j5f:divider\|add_sub_8_result_int\[0\]~10 " "Logic cell \"gettempnumber:my_gettempnumber\|lpm_divide:Mod1\|lpm_divide_m9m:auto_generated\|sign_div_unsign_klh:divider\|alt_u_div_j5f:divider\|add_sub_8_result_int\[0\]~10\"" {  } { { "db/alt_u_div_j5f.tdf" "add_sub_8_result_int\[0\]~10" { Text "C:/Users/Xsu1023/Desktop/eda2_/db/alt_u_div_j5f.tdf" 66 22 0 } }  } 0 17048 "Logic cell \"%1!s!\"" 0 0 "Quartus II" 0 -1 1639713019948 ""} { "Info" "ISCL_SCL_CELL_NAME" "gettempnumber:my_gettempnumber\|lpm_divide:Mod0\|lpm_divide_m9m:auto_generated\|sign_div_unsign_klh:divider\|alt_u_div_j5f:divider\|add_sub_9_result_int\[0\]~0 " "Logic cell \"gettempnumber:my_gettempnumber\|lpm_divide:Mod0\|lpm_divide_m9m:auto_generated\|sign_div_unsign_klh:divider\|alt_u_div_j5f:divider\|add_sub_9_result_int\[0\]~0\"" {  } { { "db/alt_u_div_j5f.tdf" "add_sub_9_result_int\[0\]~0" { Text "C:/Users/Xsu1023/Desktop/eda2_/db/alt_u_div_j5f.tdf" 71 22 0 } }  } 0 17048 "Logic cell \"%1!s!\"" 0 0 "Quartus II" 0 -1 1639713019948 ""} { "Info" "ISCL_SCL_CELL_NAME" "gettempnumber:my_gettempnumber\|lpm_divide:Mod1\|lpm_divide_m9m:auto_generated\|sign_div_unsign_klh:divider\|alt_u_div_j5f:divider\|add_sub_9_result_int\[0\]~10 " "Logic cell \"gettempnumber:my_gettempnumber\|lpm_divide:Mod1\|lpm_divide_m9m:auto_generated\|sign_div_unsign_klh:divider\|alt_u_div_j5f:divider\|add_sub_9_result_int\[0\]~10\"" {  } { { "db/alt_u_div_j5f.tdf" "add_sub_9_result_int\[0\]~10" { Text "C:/Users/Xsu1023/Desktop/eda2_/db/alt_u_div_j5f.tdf" 71 22 0 } }  } 0 17048 "Logic cell \"%1!s!\"" 0 0 "Quartus II" 0 -1 1639713019948 ""}  } {  } 0 17016 "Found the following redundant logic cells in design" 0 0 "Quartus II" 0 -1 1639713019948 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/Xsu1023/Desktop/eda2_/output_files/eda2.map.smsg " "Generated suppressed messages file C:/Users/Xsu1023/Desktop/eda2_/output_files/eda2.map.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1639713020003 ""}
{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Quartus II" 0 -1 1639713020093 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1639713020093 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "600 " "Implemented 600 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "7 " "Implemented 7 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1639713020143 ""} { "Info" "ICUT_CUT_TM_OPINS" "16 " "Implemented 16 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1639713020143 ""} { "Info" "ICUT_CUT_TM_LCELLS" "577 " "Implemented 577 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1639713020143 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1639713020143 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 30 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 30 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4630 " "Peak virtual memory: 4630 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1639713020161 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Dec 17 11:50:20 2021 " "Processing ended: Fri Dec 17 11:50:20 2021" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1639713020161 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1639713020161 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1639713020161 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1639713020161 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1639713021103 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II 64-Bit " "Running Quartus II 64-Bit Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.0 Build 156 04/24/2013 SJ Full Version " "Version 13.0.0 Build 156 04/24/2013 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1639713021103 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Dec 17 11:50:20 2021 " "Processing started: Fri Dec 17 11:50:20 2021" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1639713021103 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1639713021103 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off eda2 -c eda2 " "Command: quartus_fit --read_settings_files=off --write_settings_files=off eda2 -c eda2" {  } {  } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1639713021103 ""}
{ "Info" "0" "" "qfit2_default_script.tcl version: #3" {  } {  } 0 0 "qfit2_default_script.tcl version: #3" 0 0 "Fitter" 0 0 1639713021181 ""}
{ "Info" "0" "" "Project  = eda2" {  } {  } 0 0 "Project  = eda2" 0 0 "Fitter" 0 0 1639713021182 ""}
{ "Info" "0" "" "Revision = eda2" {  } {  } 0 0 "Revision = eda2" 0 0 "Fitter" 0 0 1639713021182 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS_MORE_LOGICAL" "6 6 12 " "Parallel Compilation has detected 12 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 6 of the 6 physical processors detected instead." {  } {  } 0 11104 "Parallel Compilation has detected %3!i! hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use %1!i! of the %2!i! physical processors detected instead." 0 0 "Fitter" 0 -1 1639713021225 ""}
{ "Info" "IMPP_MPP_USER_DEVICE" "eda2 EP3C16Q240C8 " "Selected device EP3C16Q240C8 for design \"eda2\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1639713021239 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1639713021271 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1639713021271 ""}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1639713021334 ""}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C25Q240C8 " "Device EP3C25Q240C8 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1639713021529 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C40Q240C8 " "Device EP3C40Q240C8 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1639713021529 ""}  } {  } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1639713021529 ""}
{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ 12 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location 12" {  } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_ASDO_DATA1~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Xsu1023/Desktop/eda2_/" { { 0 { 0 ""} 0 1321 9224 9983 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1639713021531 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ 14 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location 14" {  } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_FLASH_nCE_nCSO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Xsu1023/Desktop/eda2_/" { { 0 { 0 ""} 0 1323 9224 9983 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1639713021531 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ 23 " "Pin ~ALTERA_DCLK~ is reserved at location 23" {  } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DCLK~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Xsu1023/Desktop/eda2_/" { { 0 { 0 ""} 0 1325 9224 9983 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1639713021531 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ 24 " "Pin ~ALTERA_DATA0~ is reserved at location 24" {  } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DATA0~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Xsu1023/Desktop/eda2_/" { { 0 { 0 ""} 0 1327 9224 9983 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1639713021531 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ 162 " "Pin ~ALTERA_nCEO~ is reserved at location 162" {  } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_nCEO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Xsu1023/Desktop/eda2_/" { { 0 { 0 ""} 0 1329 9224 9983 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1639713021531 ""}  } {  } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1639713021531 ""}
{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1639713021532 ""}
{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "5 " "TimeQuest Timing Analyzer is analyzing 5 combinational loops as latches." {  } {  } 0 335093 "TimeQuest Timing Analyzer is analyzing %1!d! combinational loops as latches." 0 0 "Fitter" 0 -1 1639713022042 ""}
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "eda2.sdc " "Synopsys Design Constraints File file not found: 'eda2.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1639713022043 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" {  } {  } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1639713022044 ""}
{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1639713022049 ""}
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "Fitter" 0 -1 1639713022049 ""}
{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." {  } {  } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1639713022050 ""}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "clk~input (placed in PIN 152 (CLK4, DIFFCLK_2p)) " "Automatically promoted node clk~input (placed in PIN 152 (CLK4, DIFFCLK_2p))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G9 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G9" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1639713022071 ""}  } { { "eda2.v" "" { Text "C:/Users/Xsu1023/Desktop/eda2_/eda2.v" 351 0 0 } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { clk~input } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Xsu1023/Desktop/eda2_/" { { 0 { 0 ""} 0 1311 9224 9983 0}  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1639713022071 ""}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "reset~input (placed in PIN 176 (DIFFIO_R2n, PADD20, DQS2R/CQ3R,CDPCLK5)) " "Automatically promoted node reset~input (placed in PIN 176 (DIFFIO_R2n, PADD20, DQS2R/CQ3R,CDPCLK5))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G7 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G7" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1639713022071 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "calculator:my_calculator\|count\[0\]~14 " "Destination node calculator:my_calculator\|count\[0\]~14" {  } { { "eda2.v" "" { Text "C:/Users/Xsu1023/Desktop/eda2_/eda2.v" 295 -1 0 } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { calculator:my_calculator|count[0]~14 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Xsu1023/Desktop/eda2_/" { { 0 { 0 ""} 0 1097 9224 9983 0}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1639713022071 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "debounce:in_10c\|out~2 " "Destination node debounce:in_10c\|out~2" {  } { { "eda2.v" "" { Text "C:/Users/Xsu1023/Desktop/eda2_/eda2.v" 17 -1 0 } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { debounce:in_10c|out~2 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Xsu1023/Desktop/eda2_/" { { 0 { 0 ""} 0 471 9224 9983 0}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1639713022071 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "debounce:in_5c\|out~2 " "Destination node debounce:in_5c\|out~2" {  } { { "eda2.v" "" { Text "C:/Users/Xsu1023/Desktop/eda2_/eda2.v" 17 -1 0 } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { debounce:in_5c|out~2 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Xsu1023/Desktop/eda2_/" { { 0 { 0 ""} 0 475 9224 9983 0}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1639713022071 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "debounce:in_50c\|out~2 " "Destination node debounce:in_50c\|out~2" {  } { { "eda2.v" "" { Text "C:/Users/Xsu1023/Desktop/eda2_/eda2.v" 17 -1 0 } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { debounce:in_50c|out~2 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Xsu1023/Desktop/eda2_/" { { 0 { 0 ""} 0 479 9224 9983 0}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1639713022071 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "debounce:out_25c\|out~2 " "Destination node debounce:out_25c\|out~2" {  } { { "eda2.v" "" { Text "C:/Users/Xsu1023/Desktop/eda2_/eda2.v" 17 -1 0 } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { debounce:out_25c|out~2 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Xsu1023/Desktop/eda2_/" { { 0 { 0 ""} 0 487 9224 9983 0}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1639713022071 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "debounce:out_15c\|out~2 " "Destination node debounce:out_15c\|out~2" {  } { { "eda2.v" "" { Text "C:/Users/Xsu1023/Desktop/eda2_/eda2.v" 17 -1 0 } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { debounce:out_15c|out~2 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Xsu1023/Desktop/eda2_/" { { 0 { 0 ""} 0 483 9224 9983 0}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1639713022071 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "debounce:in_10c\|last~0 " "Destination node debounce:in_10c\|last~0" {  } { { "eda2.v" "" { Text "C:/Users/Xsu1023/Desktop/eda2_/eda2.v" 21 -1 0 } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { debounce:in_10c|last~0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Xsu1023/Desktop/eda2_/" { { 0 { 0 ""} 0 490 9224 9983 0}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1639713022071 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "debounce:in_5c\|last~0 " "Destination node debounce:in_5c\|last~0" {  } { { "eda2.v" "" { Text "C:/Users/Xsu1023/Desktop/eda2_/eda2.v" 21 -1 0 } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { debounce:in_5c|last~0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Xsu1023/Desktop/eda2_/" { { 0 { 0 ""} 0 493 9224 9983 0}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1639713022071 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "debounce:in_50c\|last~0 " "Destination node debounce:in_50c\|last~0" {  } { { "eda2.v" "" { Text "C:/Users/Xsu1023/Desktop/eda2_/eda2.v" 21 -1 0 } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { debounce:in_50c|last~0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Xsu1023/Desktop/eda2_/" { { 0 { 0 ""} 0 496 9224 9983 0}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1639713022071 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "debounce:out_25c\|last~0 " "Destination node debounce:out_25c\|last~0" {  } { { "eda2.v" "" { Text "C:/Users/Xsu1023/Desktop/eda2_/eda2.v" 21 -1 0 } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { debounce:out_25c|last~0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Xsu1023/Desktop/eda2_/" { { 0 { 0 ""} 0 502 9224 9983 0}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1639713022071 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_LIMITED_TO_SUB" "10 " "Non-global destination nodes limited to 10 nodes" {  } {  } 0 176358 "Non-global destination nodes limited to %1!d! nodes" 0 0 "Quartus II" 0 -1 1639713022071 ""}  } {  } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Quartus II" 0 -1 1639713022071 ""}  } { { "eda2.v" "" { Text "C:/Users/Xsu1023/Desktop/eda2_/eda2.v" 351 0 0 } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { reset~input } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Xsu1023/Desktop/eda2_/" { { 0 { 0 ""} 0 1310 9224 9983 0}  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1639713022071 ""}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "clock:my_clock\|count\[15\]  " "Automatically promoted node clock:my_clock\|count\[15\] " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1639713022072 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "clock:my_clock\|count\[15\]~43 " "Destination node clock:my_clock\|count\[15\]~43" {  } { { "eda2.v" "" { Text "C:/Users/Xsu1023/Desktop/eda2_/eda2.v" 56 -1 0 } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { clock:my_clock|count[15]~43 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Xsu1023/Desktop/eda2_/" { { 0 { 0 ""} 0 1142 9224 9983 0}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1639713022072 ""}  } {  } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Quartus II" 0 -1 1639713022072 ""}  } { { "eda2.v" "" { Text "C:/Users/Xsu1023/Desktop/eda2_/eda2.v" 56 -1 0 } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { clock:my_clock|count[15] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Xsu1023/Desktop/eda2_/" { { 0 { 0 ""} 0 166 9224 9983 0}  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1639713022072 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" {  } {  } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1639713022227 ""}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1639713022228 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1639713022228 ""}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" {  } {  } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1639713022229 ""}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" {  } {  } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1639713022229 ""}
{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" {  } {  } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1639713022230 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" {  } {  } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1639713022230 ""}
{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" {  } {  } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1639713022230 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" {  } {  } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1639713022231 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" {  } {  } 1 176219 "No registers were packed into other blocks" 0 0 "Quartus II" 0 -1 1639713022231 ""}  } {  } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1639713022231 ""}
{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" {  } {  } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1639713022246 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" {  } {  } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1639713022670 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1639713022878 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" {  } {  } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1639713022888 ""}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1639713023400 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1639713023401 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1639713023603 ""}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "3 X21_Y10 X30_Y19 " "Router estimated peak interconnect usage is 3% of the available device resources in the region that extends from location X21_Y10 to location X30_Y19" {  } { { "loc" "" { Generic "C:/Users/Xsu1023/Desktop/eda2_/" { { 1 { 0 "Router estimated peak interconnect usage is 3% of the available device resources in the region that extends from location X21_Y10 to location X30_Y19"} { { 11 { 0 "Router estimated peak interconnect usage is 3% of the available device resources in the region that extends from location X21_Y10 to location X30_Y19"} 21 10 10 10 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1639713024459 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1639713024459 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:02 " "Fitter routing operations ending: elapsed time is 00:00:02" {  } {  } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1639713025463 ""}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" {  } {  } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Quartus II" 0 -1 1639713025464 ""}  } {  } 0 170199 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1639713025464 ""}
{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.50 " "Total time spent on timing analysis during the Fitter is 0.50 seconds." {  } {  } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1639713025474 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1639713025499 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1639713025720 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1639713025745 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1639713025843 ""}
{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:01 " "Fitter post-fit operations ending: elapsed time is 00:00:01" {  } {  } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1639713026345 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/Xsu1023/Desktop/eda2_/output_files/eda2.fit.smsg " "Generated suppressed messages file C:/Users/Xsu1023/Desktop/eda2_/output_files/eda2.fit.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1639713026766 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 3 s Quartus II 64-Bit " "Quartus II 64-Bit Fitter was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "5443 " "Peak virtual memory: 5443 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1639713026999 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Dec 17 11:50:26 2021 " "Processing ended: Fri Dec 17 11:50:26 2021" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1639713026999 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1639713026999 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:08 " "Total CPU time (on all processors): 00:00:08" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1639713026999 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1639713026999 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1639713027797 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 64-Bit " "Running Quartus II 64-Bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.0 Build 156 04/24/2013 SJ Full Version " "Version 13.0.0 Build 156 04/24/2013 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1639713027797 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Dec 17 11:50:27 2021 " "Processing started: Fri Dec 17 11:50:27 2021" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1639713027797 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1639713027797 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off eda2 -c eda2 " "Command: quartus_asm --read_settings_files=off --write_settings_files=off eda2 -c eda2" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1639713027797 ""}
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" {  } {  } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1639713028405 ""}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1639713028422 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4549 " "Peak virtual memory: 4549 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1639713028692 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Dec 17 11:50:28 2021 " "Processing ended: Fri Dec 17 11:50:28 2021" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1639713028692 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1639713028692 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1639713028692 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1639713028692 ""}
{ "Info" "IFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" {  } {  } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1639713029273 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1639713029643 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 64-Bit " "Running Quartus II 64-Bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.0 Build 156 04/24/2013 SJ Full Version " "Version 13.0.0 Build 156 04/24/2013 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1639713029644 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Dec 17 11:50:29 2021 " "Processing started: Fri Dec 17 11:50:29 2021" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1639713029644 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1639713029644 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta eda2 -c eda2 " "Command: quartus_sta eda2 -c eda2" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1639713029644 ""}
{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1639713029729 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS_MORE_LOGICAL" "6 6 12 " "Parallel Compilation has detected 12 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 6 of the 6 physical processors detected instead." {  } {  } 0 11104 "Parallel Compilation has detected %3!i! hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use %1!i! of the %2!i! physical processors detected instead." 0 0 "Quartus II" 0 -1 1639713029856 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1639713029899 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1639713029899 ""}
{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "5 " "TimeQuest Timing Analyzer is analyzing 5 combinational loops as latches." {  } {  } 0 335093 "TimeQuest Timing Analyzer is analyzing %1!d! combinational loops as latches." 0 0 "Quartus II" 0 -1 1639713030004 ""}
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "eda2.sdc " "Synopsys Design Constraints File file not found: 'eda2.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1639713030040 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1639713030040 ""}
{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name clock:my_clock\|count\[15\] clock:my_clock\|count\[15\] " "create_clock -period 1.000 -name clock:my_clock\|count\[15\] clock:my_clock\|count\[15\]" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1639713030042 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name reset reset " "create_clock -period 1.000 -name reset reset" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1639713030042 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name clk clk " "create_clock -period 1.000 -name clk clk" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1639713030042 ""}  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1639713030042 ""}
{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Quartus II" 0 -1 1639713030131 ""}
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1639713030132 ""}
{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1639713030133 ""}
{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" {  } {  } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Quartus II" 0 0 1639713030139 ""}
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1639713030160 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1639713030160 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -5.016 " "Worst-case setup slack is -5.016" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1639713030162 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1639713030162 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -5.016      -254.327 clock:my_clock\|count\[15\]  " "   -5.016      -254.327 clock:my_clock\|count\[15\] " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1639713030162 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.014       -21.856 clk  " "   -2.014       -21.856 clk " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1639713030162 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1639713030162 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.204 " "Worst-case hold slack is 0.204" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1639713030165 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1639713030165 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.204         0.000 clk  " "    0.204         0.000 clk " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1639713030165 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.455         0.000 clock:my_clock\|count\[15\]  " "    0.455         0.000 clock:my_clock\|count\[15\] " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1639713030165 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1639713030165 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "recovery -0.244 " "Worst-case recovery slack is -0.244" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1639713030167 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1639713030167 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.244       -16.742 clock:my_clock\|count\[15\]  " "   -0.244       -16.742 clock:my_clock\|count\[15\] " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1639713030167 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1639713030167 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "removal 0.187 " "Worst-case removal slack is 0.187" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1639713030169 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1639713030169 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.187         0.000 clock:my_clock\|count\[15\]  " "    0.187         0.000 clock:my_clock\|count\[15\] " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1639713030169 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1639713030169 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1639713030171 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1639713030171 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.000       -26.792 clk  " "   -3.000       -26.792 clk " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1639713030171 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.000        -3.000 reset  " "   -3.000        -3.000 reset " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1639713030171 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.487      -118.960 clock:my_clock\|count\[15\]  " "   -1.487      -118.960 clock:my_clock\|count\[15\] " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1639713030171 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1639713030171 ""}
{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" {  } {  } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Quartus II" 0 0 1639713030232 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1639713030249 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1639713030572 ""}
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1639713030612 ""}
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1639713030620 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1639713030620 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -4.741 " "Worst-case setup slack is -4.741" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1639713030623 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1639713030623 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -4.741      -238.577 clock:my_clock\|count\[15\]  " "   -4.741      -238.577 clock:my_clock\|count\[15\] " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1639713030623 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.723       -18.612 clk  " "   -1.723       -18.612 clk " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1639713030623 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1639713030623 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.274 " "Worst-case hold slack is 0.274" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1639713030628 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1639713030628 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.274         0.000 clk  " "    0.274         0.000 clk " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1639713030628 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.403         0.000 clock:my_clock\|count\[15\]  " "    0.403         0.000 clock:my_clock\|count\[15\] " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1639713030628 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1639713030628 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "recovery -0.214 " "Worst-case recovery slack is -0.214" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1639713030631 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1639713030631 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.214       -14.661 clock:my_clock\|count\[15\]  " "   -0.214       -14.661 clock:my_clock\|count\[15\] " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1639713030631 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1639713030631 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "removal 0.190 " "Worst-case removal slack is 0.190" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1639713030635 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1639713030635 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.190         0.000 clock:my_clock\|count\[15\]  " "    0.190         0.000 clock:my_clock\|count\[15\] " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1639713030635 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1639713030635 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1639713030637 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1639713030637 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.000       -26.792 clk  " "   -3.000       -26.792 clk " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1639713030637 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.000        -3.000 reset  " "   -3.000        -3.000 reset " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1639713030637 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.487      -118.960 clock:my_clock\|count\[15\]  " "   -1.487      -118.960 clock:my_clock\|count\[15\] " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1639713030637 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1639713030637 ""}
{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" {  } {  } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Quartus II" 0 0 1639713030724 ""}
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1639713030795 ""}
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1639713030797 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1639713030797 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -2.278 " "Worst-case setup slack is -2.278" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1639713030802 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1639713030802 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.278      -121.288 clock:my_clock\|count\[15\]  " "   -2.278      -121.288 clock:my_clock\|count\[15\] " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1639713030802 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.322        -1.305 clk  " "   -0.322        -1.305 clk " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1639713030802 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1639713030802 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold -0.106 " "Worst-case hold slack is -0.106" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1639713030809 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1639713030809 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.106        -0.106 clk  " "   -0.106        -0.106 clk " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1639713030809 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.187         0.000 clock:my_clock\|count\[15\]  " "    0.187         0.000 clock:my_clock\|count\[15\] " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1639713030809 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1639713030809 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "recovery -0.298 " "Worst-case recovery slack is -0.298" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1639713030815 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1639713030815 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.298       -20.505 clock:my_clock\|count\[15\]  " "   -0.298       -20.505 clock:my_clock\|count\[15\] " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1639713030815 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1639713030815 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "removal 0.163 " "Worst-case removal slack is 0.163" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1639713030820 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1639713030820 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.163         0.000 clock:my_clock\|count\[15\]  " "    0.163         0.000 clock:my_clock\|count\[15\] " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1639713030820 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1639713030820 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1639713030826 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1639713030826 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.000       -19.954 clk  " "   -3.000       -19.954 clk " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1639713030826 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.000        -3.000 reset  " "   -3.000        -3.000 reset " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1639713030826 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000       -80.000 clock:my_clock\|count\[15\]  " "   -1.000       -80.000 clock:my_clock\|count\[15\] " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1639713030826 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1639713030826 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1639713031043 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1639713031044 ""}
{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 5 s Quartus II 64-Bit " "Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4657 " "Peak virtual memory: 4657 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1639713031124 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Dec 17 11:50:31 2021 " "Processing ended: Fri Dec 17 11:50:31 2021" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1639713031124 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1639713031124 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1639713031124 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1639713031124 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1639713031969 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus II 64-Bit " "Running Quartus II 64-Bit EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.0 Build 156 04/24/2013 SJ Full Version " "Version 13.0.0 Build 156 04/24/2013 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1639713031970 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Dec 17 11:50:31 2021 " "Processing started: Fri Dec 17 11:50:31 2021" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1639713031970 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1639713031970 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off eda2 -c eda2 " "Command: quartus_eda --read_settings_files=off --write_settings_files=off eda2 -c eda2" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1639713031970 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "eda2_8_1200mv_85c_slow.vo C:/Users/Xsu1023/Desktop/eda2_/simulation/modelsim/ simulation " "Generated file eda2_8_1200mv_85c_slow.vo in folder \"C:/Users/Xsu1023/Desktop/eda2_/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1639713032368 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "eda2_8_1200mv_0c_slow.vo C:/Users/Xsu1023/Desktop/eda2_/simulation/modelsim/ simulation " "Generated file eda2_8_1200mv_0c_slow.vo in folder \"C:/Users/Xsu1023/Desktop/eda2_/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1639713032437 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "eda2_min_1200mv_0c_fast.vo C:/Users/Xsu1023/Desktop/eda2_/simulation/modelsim/ simulation " "Generated file eda2_min_1200mv_0c_fast.vo in folder \"C:/Users/Xsu1023/Desktop/eda2_/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1639713032507 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "eda2.vo C:/Users/Xsu1023/Desktop/eda2_/simulation/modelsim/ simulation " "Generated file eda2.vo in folder \"C:/Users/Xsu1023/Desktop/eda2_/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1639713032580 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "eda2_8_1200mv_85c_v_slow.sdo C:/Users/Xsu1023/Desktop/eda2_/simulation/modelsim/ simulation " "Generated file eda2_8_1200mv_85c_v_slow.sdo in folder \"C:/Users/Xsu1023/Desktop/eda2_/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1639713032637 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "eda2_8_1200mv_0c_v_slow.sdo C:/Users/Xsu1023/Desktop/eda2_/simulation/modelsim/ simulation " "Generated file eda2_8_1200mv_0c_v_slow.sdo in folder \"C:/Users/Xsu1023/Desktop/eda2_/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1639713032697 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "eda2_min_1200mv_0c_v_fast.sdo C:/Users/Xsu1023/Desktop/eda2_/simulation/modelsim/ simulation " "Generated file eda2_min_1200mv_0c_v_fast.sdo in folder \"C:/Users/Xsu1023/Desktop/eda2_/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1639713032763 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "eda2_v.sdo C:/Users/Xsu1023/Desktop/eda2_/simulation/modelsim/ simulation " "Generated file eda2_v.sdo in folder \"C:/Users/Xsu1023/Desktop/eda2_/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1639713032820 ""}
{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit EDA Netlist Writer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4537 " "Peak virtual memory: 4537 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1639713032852 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Dec 17 11:50:32 2021 " "Processing ended: Fri Dec 17 11:50:32 2021" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1639713032852 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1639713032852 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1639713032852 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1639713032852 ""}
{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 38 s " "Quartus II Full Compilation was successful. 0 errors, 38 warnings" {  } {  } 0 293000 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1639713033427 ""}