--- drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c 2019-10-21 14:23:50.032830050 -0400 +++ drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c 2019-10-21 14:54:39.000000000 -0400 @@ -151,6 +151,7 @@ #define SFP_EEPROM_CON_TYPE_ADDR 0x2 #define SFP_EEPROM_CON_TYPE_VAL_UNKNOWN 0x0 + #define SFP_EEPROM_CON_TYPE_VAL_SC 0x1 #define SFP_EEPROM_CON_TYPE_VAL_LC 0x7 #define SFP_EEPROM_CON_TYPE_VAL_COPPER 0x21 #define SFP_EEPROM_CON_TYPE_VAL_RJ45 0x22 @@ -4206,6 +4207,16 @@ 0x1000); DP(NETIF_MSG_LINK, "set SGMII AUTONEG\n"); } else { + /* Note that 2.5G works only when used with 1G advertisment */ + if (fiber_mode && (phy->req_line_speed == SPEED_2500) && + (phy->speed_cap_mask & + (PORT_HW_CFG_SPEED_CAPABILITY_D0_1G | + PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))) { + bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, + MDIO_WC_REG_SERDESDIGITAL_MISC1, + 0x6010); + } + bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16); val16 &= 0xcebf; @@ -4216,6 +4227,7 @@ val16 |= 0x2000; break; case SPEED_1000: + case SPEED_2500: val16 |= 0x0040; break; default: @@ -8169,6 +8181,7 @@ break; } case SFP_EEPROM_CON_TYPE_VAL_UNKNOWN: + case SFP_EEPROM_CON_TYPE_VAL_SC: case SFP_EEPROM_CON_TYPE_VAL_LC: case SFP_EEPROM_CON_TYPE_VAL_RJ45: check_limiting_mode = 1; @@ -8179,7 +8192,8 @@ (val[SFP_EEPROM_1G_COMP_CODE_ADDR] != 0)) { DP(NETIF_MSG_LINK, "1G SFP module detected\n"); phy->media_type = ETH_PHY_SFP_1G_FIBER; - if (phy->req_line_speed != SPEED_1000) { + if ((phy->req_line_speed != SPEED_1000) && + (phy->req_line_speed != SPEED_2500)) { u8 gport = params->port; phy->req_line_speed = SPEED_1000; if (!CHIP_IS_E1x(bp)) { @@ -9238,6 +9252,7 @@ u16 tmp1, val; /* Set option 1G speed */ if ((phy->req_line_speed == SPEED_1000) || + (phy->req_line_speed == SPEED_2500) || (phy->media_type == ETH_PHY_SFP_1G_FIBER)) { DP(NETIF_MSG_LINK, "Setting 1G force\n"); bnx2x_cl45_write(bp, phy, @@ -9247,6 +9262,22 @@ bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, &tmp1); DP(NETIF_MSG_LINK, "1.7 = 0x%x\n", tmp1); + if ((phy->req_line_speed == SPEED_2500) && + (phy->speed_cap_mask & + (PORT_HW_CFG_SPEED_CAPABILITY_D0_1G | + PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))) { + bnx2x_cl45_read_and_write(bp, phy, + MDIO_AN_DEVAD, + MDIO_AN_REG_8727_MISC_CTRL2, + ~(1<<5)); + bnx2x_cl45_write(bp, phy, + MDIO_AN_DEVAD, + MDIO_AN_REG_8727_MISC_CTRL1, 0x0010); + } else { + bnx2x_cl45_write(bp, phy, + MDIO_AN_DEVAD, + MDIO_AN_REG_8727_MISC_CTRL1, 0x001C); + } /* Power down the XAUI until link is up in case of dual-media * and 1G */ @@ -9268,7 +9299,7 @@ DP(NETIF_MSG_LINK, "Setting 1G clause37\n"); bnx2x_cl45_write(bp, phy, - MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL, 0); + MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL2, 0); bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1300); } else { @@ -9276,9 +9307,12 @@ * registers although it is default */ bnx2x_cl45_write(bp, phy, - MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL, + MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL2, 0x0020); bnx2x_cl45_write(bp, phy, + MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL1, + 0x001C); + bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x0100); bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040); @@ -9569,6 +9603,11 @@ vars->line_speed = SPEED_10000; DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n", params->port); + } else if ((link_status & (1<<1)) && (!(link_status & (1<<14)))) { + link_up = 1; + vars->line_speed = SPEED_2500; + DP(NETIF_MSG_LINK, "port %x: External link up in 2.5G\n", + params->port); } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) { link_up = 1; vars->line_speed = SPEED_1000; @@ -9600,7 +9639,8 @@ } if ((DUAL_MEDIA(params)) && - (phy->req_line_speed == SPEED_1000)) { + ((phy->req_line_speed == SPEED_1000) || + (phy->req_line_speed == SPEED_2500))) { bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_GP, &val1); @@ -11730,6 +11770,7 @@ SUPPORTED_100baseT_Full | SUPPORTED_1000baseT_Full | SUPPORTED_1000baseKX_Full | + SUPPORTED_2500baseX_Full | SUPPORTED_10000baseT_Full | SUPPORTED_10000baseKR_Full | SUPPORTED_20000baseKR2_Full | @@ -11916,6 +11957,7 @@ .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, .mdio_ctrl = 0, .supported = (SUPPORTED_10000baseT_Full | + SUPPORTED_2500baseX_Full | SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE | SUPPORTED_Pause | @@ -12263,6 +12305,7 @@ break; case PORT_HW_CFG_NET_SERDES_IF_SFI: phy->supported &= (SUPPORTED_1000baseT_Full | + SUPPORTED_2500baseX_Full | SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE | SUPPORTED_Pause | --- drivers/net/ethernet/broadcom/bnx2x/bnx2x_reg.h 2019-10-21 14:23:50.032830050 -0400 +++ drivers/net/ethernet/broadcom/bnx2x/bnx2x_reg.h 2019-10-21 14:25:37.955753876 -0400 @@ -7169,7 +7169,8 @@ #define MDIO_PMA_REG_8727_PCS_GP 0xc842 #define MDIO_PMA_REG_8727_OPT_CFG_REG 0xc8e4 -#define MDIO_AN_REG_8727_MISC_CTRL 0x8309 +#define MDIO_AN_REG_8727_MISC_CTRL1 0x8308 +#define MDIO_AN_REG_8727_MISC_CTRL2 0x8309 #define MDIO_PMA_REG_8073_CHIP_REV 0xc801 #define MDIO_PMA_REG_8073_SPEED_LINK_STATUS 0xc820