Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page: 1
Conditional Compiles. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page: 2
UPT Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page: 4
Register Usage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page: 6
CROM Field Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page: 7
CROM Field - ALU. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page: 8
CROM Field - ALU, Subfield - ALU SP FUN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page: 10
CROM Field - ALU, Subfield - ALU OP 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page: 11
CROM Field - ALU, Subfield - ALU SHIFT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page: 12
CROM Field - ALU, Subfield - ALU OP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page: 14
CROM Field - ALU, Subfield - ALU 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page: 15
CROM Field - R SEL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page: 16
CROM Field - R SEL, Subfield - R SEL TYP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page: 18
CROM Field - B SEL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page: 19
CROM Field - B SEL, Subfield - B SEL TYP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page: 21
CROM Field - CARRY OP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page: 23
CROM Field - STATUS OP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page: 25
CROM Field - U STATUS ENAB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page: 28
CROM Field - M STATUS ENAB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page: 29
CROM Field - ALU_Y. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page: 30
CROM Field - U PROG OP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page: 31
CROM Field - TEST SEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page: 33
CROM Field - J. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page: 35
CROM Field - MAP SEL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page: 41
CROM Field - MEM OP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page: 42
CROM Field - Y SEL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page: 43
Instruction Macros. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page: 45
Console Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page: 57
A - Console Address Break Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page: 70
B - Console Bootstrap Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page: 72
C - Console Continue Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page: 73
D - Console Deposit Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page: 74
E - Console Examine Memory Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page: 76
DI - Console Deposit I/O Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page: 78
EI - Console Examine IO Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page: 79
DR - Console Deposit Ramfi1e Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page: 80
ER - Console Examine Ramfile Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page: 81
DV - Console Deposit Virtual Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page: 82
EV - Console Examine Virtual Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page: 84
H - Console Halt Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page: 85
I - Console Initialize Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page: 86
R - Console Repeat Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page: 88
S - Console Start Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page: 89
SH - Console Shut Down Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page: 90
SI - Console Single Instruction Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page: 91
SM - Console Start u-code Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page: 93
T - Console Self Test Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page: 94
ZM - Console Zero memory Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page: 96
Write Halt Status Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page: 98
Instruction fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page: 100
Effective Address Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page: 103
Operand Fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page: 105
User Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page: 109
Byte Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page: 113
Floating Point Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page: 117
Full Word Data Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page: 119
Fixed Point Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page: 121
Double Precision Fixed Point Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page: 124
Shift and Rotate Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page: 126
Program Control Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page: 130
Stack Operation Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page: 135
Arithmetic Testing Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page: 140
Boolean Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page: 143
Half Word Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page: 145
Logical Testing and Modification Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page: 148
Extend Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page: 150
CIS Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page: 151
IO Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page: 156
Executive Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page: 157
Arithmetic Processor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page: 158
APRID - APR Identification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page: 159
WRAPR - Write APR Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page: 161
RDAPR - Read APR Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page: 164
SZAPR (CONSZ APR) - Skip on masked APR conditions all zero. . . . . . . . . . . . . . . . . . . . . . . . . . Page: 165
SNAPR (CONSO APR) - Skip on any masked APR conditions non-zero. . . . . . . . . . . . . . . . . . . . . . . . Page: 166
PI System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page: 168
WRPI - Write PI Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page: 169
RDPI - Read PI Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page: 172
SZPI - Skip on masked PI conditions all zero. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page: 174
SNPI - Skip on any masked PI conditions non-zero. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page: 175
Pager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page: 176
WREBR - Write Executive Base Address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page: 177
RDEBR - Read the Executive Base Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page: 179
WRUBR (DATAO PAG) - Write User Base Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page: 181
RDUBR - Read User Base Address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page: 183
WRSPB - Write the SPT base address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page: 184
RDSPB - Read SPT base address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page: 185
WRCSTM - Write CST Mask register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page: 186
RDCSTM - Read CST Mask register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page: 188
WRPUR - Write process use register (CSTDATA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page: 189
RDPUR - Read process use register (CSTDATA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page: 190
WRCSB - Write Core status table base address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page: 191
RDCSB - Read Core status table base address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page: 192
CLRPT - Clear Page Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page: 193
Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page: 194
RDTIM - Read time base register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page: 195
WRTIM - Write time base register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page: 197
RDINT - Read Interval Timer register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page: 198
WRINT - Write Interval Timer register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page: 199
Halt Status Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page: 200
WRHSB - Write Halt Status Block Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page: 201
RDHSB - Read Halt Status Block Address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page: 203
PCI Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page: 204
RDTTY - Read TTY Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page: 205
External IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page: 216
Trap Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page: 219
Interrupt Handling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page: 221
Memory Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page: 226
Store Instruction Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page: 227
TOPS20 Page Refill. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page: 231
TOPS10 Page Refill. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page: 234
Unmapped Memory Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page: 236
Memory Read Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page: 239
Unmapped Memory Write Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page: 241
Memory Write Routine. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page: 243
Page Fail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page: 245
Dispatch Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page: 248
Dispatch Table Field Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page: 249
Dispatch Table Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page: 250
Opcodes 000 - 037 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page: 252
Opcodes 040 - 077 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page: 253
Opcodes 100 - 137 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page: 255
Opcodes 140 - 177 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page: 257
Opcodes 200 - 237 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page: 259
Opcodes 240 - 277 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page: 261
Opcodes 300 - 337 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page: 262
Opcodes 340 - 377 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page: 264
Opcodes 400 - 437 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page: 265
Opcodes 440 - 477 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page: 267
Opcodes 500 - 537 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page: 269
Opcodes 540 - 577 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page: 270
Opcodes 600 - 637 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page: 272
Opcodes 640 - 677 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page: 274
Opcodes 700 - 737 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page: 275
Opcodes 740 - 777 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page: 277
| -1|1|//
| -1|2|// KT-20 Microcode originally created by Digital Equipment Corporation (DEC).
| -1|3|// This code was archived (with no copyright notice attached) on:
| -1|4|// <http://bitsavers.org/pdf/dec/pdp10/KT20_Minnow/minnow_uCodeSrc.pdf>
| -1|5|//
| -1|6|// Microcode changes to the original are Copyright 2009 by Rob Doyle
| -1|7|//
| -1|8|
| -1|9|.DEBUG/0
| -1|10|
| -1|11|.TITLE "KT-20 MICROCODE"
| -1|12|.TOC "Conditional Compiles"
| -1|13|
| -1|14|;
| -1|15|; DEBUG2 - UCODE ERR
| -1|16|; DEBUG3 - POOP FLAG
| -1|17|; DEBUGPF - Debug Page Faults
| -1|18|; DEBUGTTY - Replaces RDIOB instruction with RDTTY instruction (73510)
| -1|19|; FAST -
| -1|20|; FTADRB - installs address breakpoint
| -1|21|; FTAGEPF - Page Fault Aging?
| -1|22|; FTBB -
| -1|23|; FTCKBP - Check Bus Parity
| -1|24|; FTCRC - Adds CRC Calculation
| -1|25|; FTCTLR - Adds ^R Console Command
| -1|26|; FTDDTM - DDT Mode
| -1|27|; FTFCSL - Engineering Console Commands
| -1|28|; FTFP - Adds Floating Point
| -1|29|; FTDIAG - Diagnostics
| -1|30|; FTLDIAG - Long Diagnosics
| -1|31|; FTMBZ - Enforces "Must be zero" in instructions.
| -1|32|; FTPFRMER - Something to do with page fail and memory errors
| -1|33|; FTTTYF -
| -1|34|; FTTTYR - TTY Line Reset when ??? occurs
| -1|35|; FTTTYSB - TTY Something about stop on buffer
| -1|36|; FTSM - Add SM Engineering Console Command
| -1|37|; FTSMER - Something to do with Memory Errors
| -1|38|; FTZM - Add ZM Engineering Console Command
| -1|39|; FT7PI - MUUO if try to set PI to 1
| -1|40|; SILLY -
| -1|41|; SH_N_TL - Show and Tell
| -1|42|;
| -1|43|; Instruction Set Options
| -1|44|; FT10PAG - Include TOP10 Instructions
| -1|45|; FT20PAG - Include TOP20 Instructions
| -1|46|; FTEXTEND - Include Extend Instructions
| -1|47|; FTBYTE - Include Byte Instructions
| -1|48|; FTCIS - Include CIS Instructions
| -1|49|;
| -1|50|
| -1|51|.SET/DEBUG2 = 1
| -1|52|.SET/DEBUG3 = 1
| -1|53|.SET/DEBUGPF = 1
| -1|54|.SET/DEBUGTTY = 1
| -1|55|.SET/FAST = 1
| -1|56|.SET/FTADRB = 1
| -1|57|.SET/FTAGEPF = 1
| -1|58|.SET/FTBB = 1
| -1|59|.SET/FTCKBP = 1
| -1|60|.SET/FTCRC = 0
| -1|61|.SET/FTCTLR = 1
| -1|62|.SET/FTDDTM = 1
| -1|63|.SET/FTFCSL = 1
| -1|64|.SET/FTFP = 1
| -1|65|.SET/FTDIAG = 1
| -1|66|.SET/FTLDIAG = 1
| -1|67|.SET/FTMBZ = 1
| -1|68|.SET/FTPFRMER = 1
| -1|69|.SET/FTTTYF = 1
| -1|70|.SET/FTTTYR = 1
| -1|71|.SET/FTTTYSB = 1
| -1|72|.SET/FTSM = 1
| -1|73|.SET/FTSMER = 1
| -1|74|.SET/FTZM = 1
| -1|75|.SET/FT7PI = 1
| -1|76|.SET/SILLY = 1
| -1|77|.SET/SH_N_TL = 1
| -1|78|.SET/FT10PAG = 1
| -1|79|.SET/FT20PAG = 1
| -1|80|.SET/FTEXTEND = 1
| -1|81|.SET/FTBYTE = 1
| -1|82|.SET/FTCIS = 1
| -1|83|
| -1|84|.TOC "UPT Format"
| -1|85|
| -1|86|; TOPS10 TOPS20
| -1|87|; +-----------------------------------+ +-----------------------------------+
| -1|88|; 0 | Reserved | | User pg 0,,User pg 1 |
| -1|89|; 377 | | | User pg 776,,User pg 777 |
| -1|90|; +-----------------------------------+ +-----------------------------------+
| -1|91|; 400 | Reserved | | Exec pg 340,,Exec pg 341 |
| -1|92|; 417 | | | Exec pg 376,,Exec pg 377 |
| -1|93|; +-----------------------------------+ +-----------------------------------+
| -1|94|; 420 | Adr of LUUO block |
| -1|95|; +-----------------------------------+
| -1|96|; 421 | User arith overflow trap ins |
| -1|97|; +-----------------------------------+
| -1|98|; 422 | User stack overflow trap ins |
| -1|99|; +-----------------------------------+
| -1|100|; 423 | User trap 3 ins |
| -1|101|; +--------------------+--------------+
| -1|102|; 424 | MUUO flags | MUUO op code |
| -1|103|; +--------------------+--------------+
| -1|104|; 425 | MUUO old PC |
| -1|105|; +-----------------------------------+
| -1|106|; 426 | E of MUUO |
| -1|107|; +-----------------------------------+
| -1|108|; 427 | MUUO process context word |
| -1|109|; +-----------------------------------+
| -1|110|; 430 | Exec no trap MUUO new PC |
| -1|111|; +-----------------------------------+
| -1|112|; 430 | Reserved |
| -1|113|; 433 | |
| -1|114|; +-----------------------------------+
| -1|115|; 434 | User no trap MUUO new PC |
| -1|116|; +-----------------------------------+
| -1|117|; 435 | Reserved |
| -1|118|; 477 | |
| -1|119|; +-----------------------------------+
| -1|120|; 500 | Page fail word |
| -1|121|; +-----------------------------------+ +-----------------------------------+
| -1|122|; 501 | Page fail flags | | Page fail old flags,,PC |
| -1|123|; +-----------------------------------+ +-----------------------------------+
| -1|124|; 502 | Page fail old PC | | Page fail new PC |
| -1|125|; +-----------------------------------+ +-----------------------------------+
| -1|126|; 503 | Page fail new PC | | Reserved |
| -1|127|; +-----------------------------------+ +-----------------------------------+
| -1|128|; 504 | Reserved |
| -1|129|; 537 | |
| -1|130|; +-----------------------------------+
| -1|131|; 540 | User section 0 |
| -1|132|; 500 | ... |
| -1|133|; 577 | User section 37 |
| -1|134|; +-----------------------------------+
| -1|135|; 600 | Reserved |
| -1|136|; 777 | |
| -1|137|; +-----------------------------------+
| -1|138|
| -1|139|.TOC "Register Usage"
| -1|140|
| -1|141|; EXT INT
| -1|142|; Reg 0 W1 PC FLAGS
| -1|143|; Reg 1 W2 AC-OP+1
| -1|144|; Reg 2 W3 MEM-OP+1
| -1|145|; Reg 3 W4 EPT
| -1|146|; Reg 4 W5 UPT
| -1|147|; Reg 5 W6 SPT
| -1|148|; Reg 6 IR PMA
| -1|149|; Reg 7 PC TIME
| -1|150|; Reg 10 E PI REG(loads 2914 status reg)
| -1|151|; Reg 11 MB BIT4(first part done)
| -1|152|; Reg 12 AC-OP BIT12
| -1|153|; Reg 13 MEM-OP BIT17
| -1|154|; Reg 14 PXCT CO!C1
| -1|155|; Reg 15 K 77 K 7777.-1
| -1|156|; Reg 16 K 777 K 407777.0
| -1|157|; Reg 17 K -1.0 K -1
| -1|158|
| -1|159|.UCODE
| -1|160|.LTOR ;Assume MIN6 CRM 00 to be leftmost bit.
| -1|161|
| -1|162|.TOC 1, "CROM Field Definitions"
| -1|163|.TOC 2, "CROM Field - ALU"
| -1|164|
| -1|165|;
| -1|166|; ALU Functons
| -1|167|;
| -1|168|
| -1|169|ALU/=<0:8> ;AM2903 OP[8:0]
| -1|170|
| -1|171|;
| -1|172|; ALU Special Functions
| -1|173|;
| -1|174|
| -1|175|.TOC 3, "CROM Field - ALU, Subfield - ALU SP FUN"
| -1|176|ALU SP FUN/=<0:8> ;AM2903 OP[8:0]
| -1|177| MUL=0000 ;or 040, unsigned multiply
| -1|178| TCM=0100 ;or 140, Twos complement multiply
| -1|179| S+1+C_B=0200 ;increment by one or two
| -1|180| SM=0240 ;sign/magnitude twos complement
| -1|181| TCM COR=0300 ;or 340, twos complement multiply correction
| -1|182| SLN=0400 ;or 440, single length normalize
| -1|183| DLN=0500 ;or 540, double length normalize and first divide op
| -1|184| TCDIV=0600 ;or 640, twos complement divide
| -1|185| TCDIV COR=0700 ;or 740, twos complement divide correction and remainder
| -1|186|
| -1|187|;
| -1|188|; ALU OP 0
| -1|189|;
| -1|190|
| -1|191|.TOC 3, "CROM Field - ALU, Subfield - ALU OP 0"
| -1|192|ALU OP 0/=<0> ;AM2903 OP[8]
| -1|193|
| -1|194|;
| -1|195|; ALU Shift (and Destination) Functions
| -1|196|;
| -1|197|
| -1|198|.TOC 3, "CROM Field - ALU, Subfield - ALU SHIFT"
| -1|199|ALU SHIFT/=<0:3>,.DEFAULT=014 ;AM2903 OP[8:5] - This controls the destination (w/shift)
| -1|200| ASR F_B "ALU SHIFT/000,ALU_Y/YES" ;ASR F_Y Q_Q WRITE=0
| -1|201| LRS F_B "ALU SHIFT/001,ALU_Y/YES" ;LRS R_Y Q_Q WRITE=1
| -1|202| F_LRS Y_B "ALU SHIFT/001,ALU_Y/NO" ;LRS R_Y Q_Q WRITE=1
| -1|203| (MC F)RS_[] "MC_SION SIO0_QION,LRS F_B,B SEL/@1" ;
| -1|204| (MN F)RS_[] "MN_SION SIO0_QION,LRS F_B,B SEL/@1" ;
| -1|205| ASRC_B "ALU SHIFT/002,ALU_Y/YES" ;F3_Y3;Y2 FQ/2_BQ
| -1|206| LSRC_B "ALU SHIFT/003,ALU_Y/YES" ;LRS F_Y LRS Q_Q WRITE=3
| -1|207| Y_[] QRS_Q "ALU SHIFT/003,ALU_Y/NO,B SEL/@1" ;LRS F_LRS Q_Q WRITE=3
| -1|208| F_B "ALU SHIFT/004,ALU_Y/YES" ;F_Y Q_Q WRITE=4
| -1|209| Y_B "ALU SHIFT/004,ALU_Y/NO" ;F_Y Q_Q WRITE=4
| -1|210| F_Y QRS_Q "ALU SHIFT/005,ALU_Y/YES" ;F_Y LRS Q_Q=5
| -1|211| F_Q "ALU SHIFT/006,ALU_Y/NO" ;F_Y F_Q=6
| -1|212| F_Q_Y "ALU SHIFT/006,ALU_Y/YES" ;F_Y F_Q=6
| -1|213| F_Q_B "ALU SHIFT/007,ALU_Y/YES" ;F_Y F_Q WRITE=7
| -1|214| Y_B F_Q "ALU SHIFT/007,ALU_Y/NO" ;F_Y F_Q WRITE=7
| -1|215| ALS F_[] "ALU SHIFT/010,ALU_Y/YES,#0_SIO0 #0_QIO0,B SEL/@1" ;ALS F_Y
| -1|216| LLS F_B "ALU SHIFT/011,ALU_Y/YES" ;
| -1|217| F_LSZ Y_[] "ALU SHIFT/011,ALU_Y/NO,#0_SIO0 #0_QIO0,B SEL/@1" ;LLS F_Y
| -1|218| ALSC_B "ALU SHIFT/012,ALU_Y/YES" ;ALS F_Y LLS Q_Q WRITE=012
| -1|219| LLSC_B "ALU SHIFT/013,ALU_Y/YES" ;LLS F_Y LLS Q_Q WRITE=013
| -1|220| Y_[] QLS_Q "ALU SHIFT/013,ALU_Y/NO,B SEL/@1" ;LLS F_Y LLS Q_Q WRITE=013
| -1|221| F_Y "ALU SHIFT/014,ALU_Y/YES" ;F_Y Q_Q=014
| -1|222| QLS_Q "ALU SHIFT/015" ;F_Y LLS Q_Q=015
| -1|223| F_Y QLS_Q "ALU SHIFT/015,ALU_Y/YES" ;F_Y LLS Q_Q=015
| -1|224| ;SIO0_Y Q_Q WRITE=016
| -1|225| ;F_Y Q_Q WRITE=017
| -1|226|;
| -1|227|; ALU Operations
| -1|228|;
| -1|229|
| -1|230|
| -1|231|.TOC 3, "CROM Field - ALU, Subfield - ALU OP"
| -1|232|ALU OP/=<4:7>,.DEFAULT=010 ;AM2903 OP[4:1]
| -1|233| S-R-1+C=001
| -1|234| R-S-1+C=002
| -1|235| R+S+C=003
| -1|236| S+C=004
| -1|237| SBAR+C=005
| -1|238| R+C=006
| -1|239| RBAR+C=007
| -1|240| LOW=010
| -1|241| RBAR.AND.S=011
| -1|242| R.XNOR.S=012
| -1|243| R.XOR.S=013
| -1|244| R.AND.S=014
| -1|245| R.NOR.S=015
| -1|246| R.NAND.S=016
| -1|247| R.OR.S=017
| -1|248|
| -1|249|;.TOC 3, "CROM Field - ALU, Subfield - ALU OP"
| -1|250|;ALU OP/=<4:8>,.DEFAULT=020 ;AM2903 OP[4:1]
| -1|251|; HIGH=001
| -1|252|; S-R-1+C=002
| -1|253|; R-S-1+C=004
| -1|254|; R+S+C=006
| -1|255|; S+C=010
| -1|256|; SBAR+C=012
| -1|257|; R+C=015
| -1|258|; RBAR+C=017
| -1|259|; LOW=021
| -1|260|; RBAR.AND.S=022
| -1|261|; R.XNOR.S=024
| -1|262|; R.XOR.S=026
| -1|263|; R.AND.S=030
| -1|264|; R.NOR.S=032
| -1|265|; R.NAND.S=034
| -1|266|; R.OR.S=036
| -1|267|
| -1|268|.TOC 3, "CROM Field - ALU, Subfield - ALU 10"
| -1|269|
| -1|270|;
| -1|271|; ALU OP LSB. Shared with AM2904 OP[10]
| -1|272|; This selects either B RAM or Q Reg as the S input to the ALU.
| -1|273|;
| -1|274|
| -1|275|ALU 10/=<8:8>,.DEFAULT=<B_S> ;AM2903 OP[0]
| -1|276| B_S=0 ;S source is B RAM
| -1|277| Q_S=1 ;S source is Q reg
| -1|278|
| -1|279|.TOC 2, "CROM Field - R SEL"
| -1|280|R SEL/=<9:14>,.DEFAULT=00
| -1|281| REG-EXT=002
| -1|282| W1=002
| -1|283| W2=006
| -1|284| W3=012
| -1|285| W4=016
| -1|286| W5=022
| -1|287| W6=026
| -1|288| IR=032
| -1|289| PC=036
| -1|290| E=042
| -1|291| MB=046
| -1|292| AC-OP=052
| -1|293| MEM-OP=056
| -1|294| PXCT=062
| -1|295| K 77=066
| -1|296| K 777=072
| -1|297| K -1.0=076
| -1|298| REG-INT=003
| -1|299| PC FLAGS=003
| -1|300| AC-OP+1=007
| -1|301| MEM-OP+1=013
| -1|302| EPT=017
| -1|303| UPT=023
| -1|304| SPT=027
| -1|305| PMA=033
| -1|306| TIME=037
| -1|307| PI REG=043
| -1|308| BIT4=047
| -1|309| BIT12=053
| -1|310| BIT17=057
| -1|311| C0!C1=063
| -1|312| K 7777.-1=067
| -1|313| K 407777.0=073
| -1|314| K -1=077
| -1|315|
| -1|316|.TOC 3, "CROM Field - R SEL, Subfield - R SEL TYP"
| -1|317|
| -1|318|R SEL TYP/=<13:14> ;R_SEL[4:5]
| -1|319| RESERVED=00
| -1|320| LINE=01
| -1|321| REG EXT=02
| -1|322| REG INT=03
| -1|323| LINE #_[] "R SEL TYP/LINE,ALU OP/R+C,ALU 10/Q_S,#0_CO,F_[@1]"
| -1|324|
| -1|325|.TOC 2, "CROM Field - B SEL"
| -1|326|B SEL/=<15:20>,.DEFAULT=00
| -1|327| REG-EXT=00
| -1|328| W1=000
| -1|329| W2=004
| -1|330| W3=010
| -1|331| W4=014
| -1|332| W5=020
| -1|333| W6=024
| -1|334| IR=030
| -1|335| PC=034
| -1|336| E=040
| -1|337| MB=044
| -1|338| AC-OP=050
| -1|339| MEM-OP=054
| -1|340| PXCT=060
| -1|341| K 77=064
| -1|342| K 777=070
| -1|343| K -1.0=074
| -1|344| REG-EXT-LH=01
| -1|345| W1 LH=001
| -1|346| W2 LH=005
| -1|347| W3 LH=011
| -1|348| W4 LH=015
| -1|349| W5 LH=021
| -1|350| W6 LH=025
| -1|351| IR LH=031
| -1|352| PC LH=035
| -1|353| E LH=041
| -1|354| MB LH=045
| -1|355| AC-OP LH=051
| -1|356| MEM-OP LH=055
| -1|357| PXCT LH=061
| -1|358| K 77 LH=065
| -1|359| K 777 LH=071
| -1|360| K -1.0 LH=075
| -1|361| REG-EXT-RH=02
| -1|362| W1 RH=002
| -1|363| W2 RH=006
| -1|364| W3 RH=012
| -1|365| W4 RH=016
| -1|366| W5 RH=022
| -1|367| W6 RH=026
| -1|368| IR RH=032
| -1|369| PC RH=036
| -1|370| E RH=042
| -1|371| MB RH=046
| -1|372| AC-OP RH=052
| -1|373| MEM-OP RH=056
| -1|374| PXCT RH=062
| -1|375| K 77 RH=066
| -1|376| K 777 RH=072
| -1|377| K -1.0 RH=076
| -1|378| REG-INT=03
| -1|379| PC FLAGS=003
| -1|380| AC-OP+1=007
| -1|381| MEM-OP+1=013
| -1|382| EPT=017
| -1|383| UPT=023
| -1|384| SPT=027
| -1|385| PMA=033
| -1|386| TIME=037
| -1|387| PI REG=043
| -1|388| BIT4=047
| -1|389| BIT12=053
| -1|390| BIT17=057
| -1|391| C0!C1=063
| -1|392| K 7777.-1=067
| -1|393| K 407777.0=073
| -1|394| K -1=077
| -1|395|
| -1|396|.TOC 3, "CROM Field - B SEL, Subfield - B SEL TYP"
| -1|397|
| -1|398|B SEL TYP/=<19:20> ;B_SEL[4:5]
| -1|399| REG EXT=00
| -1|400| REG EXT LH=01
| -1|401| REG EXT RH=02
| -1|402| REG INT=03
| -1|403|
| -1|404| S SEL[] "B SEL/@1,ALU 10/B_S"
| -1|405|
| -1|406|.TOC 2, "CROM Field - CARRY OP"
| -1|407|
| -1|408|CARRY OP/=<21:22>,.DEFAULT=0 ;AM2904 OP[12:11]
| -1|409| #0_CO "CARRY OP/00"
| -1|410| #1_CO "CARRY OP/01"
| -1|411| CX_CO "CARRY OP/02" ;This is Z for ALU SP FUN stuff
| -1|412|
| -1|413|SHARED OP/=<23:28>,.DEFAULT=00
| -1|414|SET FLAG/=<23:28> ;with shared op4.5=00
| -1|415| CLEAR LOCAL "SET FLAG/010"
| -1|416| SET GLOBAL "CLEAR LOCAL"
| -1|417| SET LOCAL "SET FLAG/014"
| -1|418| CLEAR USER "SET FLAG/020"
| -1|419| SET EXEC "CLEAR USER"
| -1|420| SET USER "SET FLAG/024"
| -1|421| CLEAR PAGED "SET FLAG/030"
| -1|422| SET PAGED "SET FLAG/034"
| -1|423| CLEAR RUN "SET FLAG/040"
| -1|424| SET RUN "SET FLAG/044"
| -1|425| CLEAR TOPS20 "SET FLAG/050"
| -1|426| SET TOPS20 "SET FLAG/054"
| -1|427| CLEAR PXCT "SET FLAG/060"
| -1|428| SET PXCT "SET FLAG/064"
| -1|429| CLEAR TRAP "SET FLAG/070"
| -1|430| SET TRAP "SET FLAG/074"
| -1|431|
| -1|432|SHIFT OP/=<23:28> ;with shared op4,5=01
| -1|433| ;AM2904 OP[9:6] Shift linkage mux
| -1|434| ;AM2904 OP[10] comes from AM2903 OP[8]
| -1|435| #0_SION #0_QION "SHIFT OP/001,ALU OP 0/0"
| -1|436| #1_SION #1_QION "SHIFT OP/005,ALU OP 0/0"
| -1|437| #0_SION SIO0_MC MN_QION "SHIFT OP/011,ALU OP 0/0"
| -1|438| #1_SION SIO0_QION "SHIFT OP/015,ALU OP 0/0"
| -1|439| MC_SION SIO0_QION "SHIFT OP/021,ALU OP 0/0"
| -1|440| MN_SION SIO0_QION "SHIFT OP/025,ALU OP 0/0"
| -1|441| #0_SION SIO0_QION "SHIFT OP/031,ALU OP 0/0"
| -1|442| SIO0_SION QIO0_QION "SHIFT OP/051,ALU OP 0/0"
| -1|443| QIO0_SION SIO0_QION "SHIFT OP/075,ALU OP 0/0"
| -1|444|
| -1|445| SION_MC #0_SIO0 #0_QIO0 "SHIFT OP/001,ALU OP 0/1"
| -1|446| #0_SIO0 #0_QIO0 "SHIFT OP/011,ALU OP 0/1"
| -1|447| #1_SIO0 #1_QIO0 "SHIFT OP/015,ALU OP 0/1"
| -1|448| SION_MC QION_SIO0 #0_QIO0 "SHIFT OP/021,ALU OP 0/1"
| -1|449| QION_SIO0 #0_QIO0 "SHIFT OP/031,ALU OP 0/1"
| -1|450| SION_SIO0 QION_QIO0 "SHIFT OP/051,ALU OP 0/1"
| -1|451| SION_QIO0 QION_SIO0 "SHIFT OP/075,ALU OP 0/1"
| -1|452|
| -1|453|
| -1|454|INT OP/=<23:28> ;with shared opt4,5=10 2904 Instruction
| -1|455| MASTER CLEAR=002
| -1|456| CLEAR ALL INTS=006
| -1|457| CLEAR INTS FROM Y-BUS=012
| -1|458| CLEAR INTS FROM MASK REGISTER=016
| -1|459| CLEAR INT LAST VECTOR READ=022
| -1|460| GRANT INTERRUPT "INT OP/026"
| -1|461| #2914 STATUS_Y "INT OP/032"
| -1|462| #2914 MASK_Y "INT OP/036"
| -1|463| #377_2914 MASK "INT OP/042"
| -1|464| Y_2914 STATUS "INT OP/046"
| -1|465| ;BIT CLEAR MASK REG=052
| -1|466| ;BIT SET MASK REG=056
| -1|467| #000_2914 MASK "INT OP/062"
| -1|468| ;DISABLE INT REQ=066
| -1|469| Y_2914 MASK "INT OP/072"
| -1|470| ;ENABLE INT REQ=076
| -1|471|
| -1|472|SPEC SEL/=<23:28> ;with shared op4,5=11 Load Ram/PCI adr
| -1|473| Y=003 ;Low order 12 bits of Y bus are Ramfile adr
| -1|474| ; If this is an I/O adr = PCI
| -1|475| ; Y31 is 2651 A1
| -1|476| ; Y32 is 2651 A0
| -1|477| ; Y33-35 are line number
| -1|478|
| -1|479| VMA=023 ;Uses low order bits from previous spec sel/page table entry
| -1|480| AC+N=027
| -1|481| XR=033
| -1|482| PAGE TABLE ENTRY=077
| -1|483| IW=053 ; If bits 0,1 = 11 set ILLEGAL IW else clear ILLEGAL IW.
| -1|484| ; If section 0 or if bits 0,1=10 set NOT GLOBAL, else CLEAR LOCAL.
| -1|485| ; If GLOBAL load I and index reg from 1-5, else load from 13-17.
| -1|486| SEL AC+[] "SPEC SEL/027,J.AC/@1"
| -1|487| Y_RAMFILE ADR "SPEC SEL/Y"
| -1|488| Y_TTY ADR "Y_RAMFILE ADR"
| -1|489|
| -1|490|AMD2904 I5-I4/=<29:30> ;AM2904 OP[5:4]
| -1|491| MX_Y "AMD2904 I5-I4/2,STATUS_Y,ALU_Y/NO"
| -1|492| MX_[] "MX_Y,Y_[@1]"
| -1|493| F_Q MX_[] "AMD2904 I5-I4/2,STATUS_Y,F_Q Y_[@1]"
| -1|494| UX_[] "STATUS OP/001,STATUS_Y,Y_[@1]"
| -1|495|
| -1|496|.TOC 2, "CROM Field - STATUS OP"
| -1|497|STATUS OP/=<29:34>,.DEFAULT=020 ;AM2904 OP[5:0]
| -1|498| Y_MX "STATUS OP/000,M STATUS ENAB/YES" ; YX -> MX
| -1|499| #1_UX "STATUS OP/001,U STATUS ENAB/YES" ; 1 -> UX
| -1|500| #1_MX "STATUS OP/001,M STATUS ENAB/YES" ; 1 -> MX
| -1|501| MX_UX "STATUS OP/002,U STATUS ENAB/YES" ; MX -> UX
| -1|502| UX_MX "STATUS OP/002,M STATUS ENAB/YES" ; UX -> MX
| -1|503| MX_UX UX_MX "STATUS OP/002,M STATUS ENAB/YES,U STATUS ENAB/YES" ; MX <-> UX
| -1|504| #0_UX "STATUS OP/003,U STATUS ENAB/YES" ; 0 -> UX
| -1|505| #0_MX "STATUS OP/003,M STATUS ENAB/YES" ; 0 -> MX
| -1|506| IX!UOVR_UX "STATUS OP/006,U STATUS ENAB/YES" ;
| -1|507| IX!MOVR_MX "STATUS OP/006,M STATUS ENAB/YES" ;
| -1|508|
| -1|509| #0_UZ "STATUS OP/010,U STATUS ENAB/YES" ;Reset zero bit
| -1|510| #1_UZ "STATUS OP/011,U STATUS ENAB/YES" ;Set zero bit
| -1|511| #0_UC "STATUS OP/012,U STATUS ENAB/YES" ;Reset carry bit
| -1|512| #1_UC "STATUS OP/013,U STATUS ENAB/YES" ;Set carry bit
| -1|513| #0_UN "STATUS OP/014,U STATUS ENAB/YES" ;Reset sign bit
| -1|514| #1_UN "STATUS OP/015,U STATUS ENAB/YES" ;Set sign bit
| -1|515| #0_UOVR "STATUS OP/016,U STATUS ENAB/YES" ;Reset overflow bit
| -1|516| #1_UOVR "STATUS OP/017,U STATUS ENAB/YES" ;Set overflow bit
| -1|517|
| -1|518|
| -1|519| IX_UX "STATUS OP/020,U STATUS ENAB/YES" ;
| -1|520| IX_MX "STATUS OP/020,M STATUS ENAB/YES" ;
| -1|521| IX ICBAR_UX "STATUS OP/030,U STATUS ENAB/YES" ;
| -1|522| IX ICBAR_MX "STATUS OP/030,M STATUS ENAB/YES" ;
| -1|523|
| -1|524| MX_UX Y_MX "Y_MX,U STATUS ENAB/YES" ;
| -1|525| #0_UC IX_MX "#0_UC,M STATUS ENAB/YES" ;
| -1|526| #1_UC IX_MX "#1_UC,M STATUS ENAB/YES" ;
| -1|527|
| -1|528|;Carry operation
| -1|529| MC_C "CARRY OP/003,STATUS OP/047"
| -1|530| UC_C "CARRY OP/003,STATUS OP/000"
| -1|531|
| -1|532|;Test conditions
| -1|533|; U - micro status
| -1|534|; M - macros tatus
| -1|535|; I - current status (I bus)
| -1|536|; Z - zero;
| -1|537|; N - negative;
| -1|538|; OVR - overflow
| -1|539|; C - carry
| -1|540|; ! - inclusive or
| -1|541|; X - xor
| -1|542|; & - and
| -1|543|; E - xnor = equivalence
| -1|544|
| -1|545| UZ "STATUS OP/024" ; Micro Zero
| -1|546| MZ "STATUS OP/044" ; Macro Zero
| -1|547| IZ "STATUS OP/064" ; I-bus Zero
| -1|548| NOT UZ "STATUS OP/025" ; Micro Not-Zero
| -1|549| NOT MZ "STATUS OP/045" ; Macro Not-Zero
| -1|550| NOT IZ "STATUS OP/065" ; I-bus Not-Zero
| -1|551| UOVR "STATUS OP/026" ; Micro Overflow
| -1|552| MOVR "STATUS OP/046" ; Macro Overflow
| -1|553| IOVR "STATUS OP/066" ; I-bus Overflow
| -1|554| NOT UOVR "STATUS OP/027" ; Micro Not-Overflow
| -1|555| NOT MOVR "STATUS OP/047" ; Macro Not-Overflow
| -1|556| NOT IOVR "STATUS OP/067" ; I-bus Not-Overflow
| -1|557| UC "STATUS OP/032" ; Micro Carry
| -1|558| MC "STATUS OP/052" ; Macro Carry
| -1|559| IC "STATUS OP/072" ; I-bus Carry
| -1|560| NOT UC "STATUS OP/033" ; Micro Not-Carry
| -1|561| NOT MC "STATUS OP/053" ; Macro Not-Carry
| -1|562| NOT IC "STATUS OP/073" ; I-bus Not-Carry
| -1|563| UN "STATUS OP/036" ; Micro Negative
| -1|564| MN "STATUS OP/056" ; Macro Negative
| -1|565| IN "STATUS OP/076" ; I-bus Negative
| -1|566| NOT UN "STATUS OP/037" ; Micro Not-Negative
| -1|567| NOT MN "STATUS OP/057" ; Macro Not-Negative
| -1|568| NOT IN "STATUS OP/077" ; I-bus Not-Negative
| -1|569| (UNxUOVR)!UZ "STATUS OP/020" ; (UNxUOVR)!UZ
| -1|570| (MNxMOVR)!MZ "STATUS OP/040" ; (MNxMOVR)!MZ
| -1|571| (INxIOVR)!IZ "STATUS OP/060" ; (INxIOVR)!IZ
| -1|572|
| -1|573| INxorMN "STATUS OP/016" ; INxorMN
| -1|574| MNxMOVR "STATUS OP/042" ; MNxMOVR
| -1|575|
| -1|576|
| -1|577| MC_C IX_MX "MC,M STATUS ENAB/YES"
| -1|578| MC_C IX_UX "MC,U STATUS ENAB/YES"
| -1|579| UZ IX_MX "UZ,M STATUS ENAB/YES"
| -1|580| UZ UX_MX "UZ,U STATUS ENAB/YES"
| -1|581| MZ IX_MX "MZ,M STATUS ENAB/YES"
| -1|582| MZ IX_UX "MZ,U STATUS ENAB/YES"
| -1|583| IZ IX_UX "IZ,M STATUS ENAB/YES"
| -1|584| IZ IX_MX "IZ,U STATUS ENAB/YES"
| -1|585| UOVR IX_MX "UOVR,M STATUS ENAB/YES"
| -1|586| IOVR IX_MX "IOVR,M STATUS ENAB/YES"
| -1|587| NOT IOVR IX_MX "NOT IOVR,M STATUS ENAB/YES"
| -1|588| UN IX_MX "UN,M STATUS ENAB/YES"
| -1|589| UN IX_UX "UN,U STATUS ENAB/YES"
| -1|590| MN IX_MX "MN,M STATUS ENAB/YES"
| -1|591| MN IX_UX "MN,U STATUS ENAB/YES"
| -1|592| IN IX_MX "IN,M STATUS ENAB/YES"
| -1|593| IN IX_UX "IN,U STATUS ENAB/YES"
| -1|594| (MNxMOVR)!MZ IX_MX "(MNxMOVR)!MZ,M STATUS ENAB/YES"
| -1|595| (MNxMOVR)!MZ IX_UX "(MNxMOVR)!MZ,U STATUS ENAB/YES"
| -1|596|
| -1|597|.TOC 2, "CROM Field - U STATUS ENAB"
| -1|598|U STATUS ENAB/=<35:35>,.DEFAULT=<NO>
| -1|599| YES=0
| -1|600| NO=1
| -1|601|
| -1|602|.TOC 2, "CROM Field - M STATUS ENAB"
| -1|603|M STATUS ENAB/=<36:36>,.DEFAULT=<NO>
| -1|604| YES=0
| -1|605| NO=1
| -1|606|
| -1|607|.TOC 2, "CROM Field - ALU_Y"
| -1|608|ALU_Y/=<37:37>,.DEFAULT=<NO> ;2903
| -1|609| NO=0
| -1|610| YES=1
| -1|611|
| -1|612|;
| -1|613|; This field controls the AM2910 controller op code.
| -1|614|;
| -1|615|
| -1|616|.TOC 2, "CROM Field - U PROG OP"
| -1|617|U PROG OP/=<38:41>,.DEFAULT=<CONT> ;AM2910 OP[3:0]
| -1|618| JZ=000 ; Jump to address zero (not used)
| -1|619| CJS=001 ; Conditional Jump Subroutine (address from Pipeline)
| -1|620| JMAP=002 ; Jump MAP (not used)
| -1|621| CJP=003 ; Conditional Jump to address from Pipeline
| -1|622| PUSH=004 ; Push /Conditional Load Register
| -1|623| JSRP=005 ; Conditional Jump Subroutine to Register address or Pipeline address
| -1|624| CJV=006 ; Conditional Jump to address from Vector (Dispatch ROMS)
| -1|625| JRP=007 ; Conditional Jump to Register address or Pipeline address (not used)
| -1|626| RFCT=010 ; Repeat Loop until Counter = 0, Start Address is TOS
| -1|627| RPCT=011 ; Repeat Loop until Counter = 0, Start Address is Pipeline
| -1|628| CRTN=012 ; Conditional Return from Subroutine
| -1|629| CJPP=013 ; Conditional Jump to Pipeline and Pop. Exit loop which uses stack.
| -1|630| LDCT=014 ; Load Counter and Continue
| -1|631| TEOL=015 ; Test End-Of-Loop
| -1|632| CONT=016 ; Continue
| -1|633| TWB=017 ; Three Way Branch (not used)
| -1|634|
| -1|635|.TOC 2, "CROM Field - TEST SEL"
| -1|636|TEST SEL/=<42:47>,.DEFAULT=<NEVER>
| -1|637| NEVER=000
| -1|638| ALWAYS=001
| -1|639| CT=002 ;2904 CT =0 MIN1 STATUS TEST
| -1|640| NOT CT=003
| -1|641| NOT INDEXED=004
| -1|642| INDEXED=005
| -1|643| AC.EQ.0=006
| -1|644| AC.NE.0=007
| -1|645| INDIRECT=010
| -1|646| NOT INDIRECT=011
| -1|647| NOT (I OR XR)=012
| -1|648| I OR XR=013
| -1|649| ILLEGAL IW=014 ;Signal from SPEC SEL/IW =<not section 0> and <bit0,bit1=11)
| -1|650| NOT ILLEGAL IW=015
| -1|651| GLOBAL IW=016 ;Signal from SPEC SEL/IW
| -1|652| LOCAL IW=017 ; <not section 0> and <bit0=1>
| -1|653| NO PI REQ=020 ;i.e. something wants to interrupt
| -1|654| PI REQ=021
| -1|655| NOT AC REF=022
| -1|656| AC REF=023
| -1|657| LEGAL SECTION=024
| -1|658| ILLEGAL SECTION=025
| -1|659| NOT SECTION 0=026
| -1|660| SECTION 0=027
| -1|661| CONTEXT MATCH=030 ;i.e. no match, AC ref, or not paged
| -1|662| NOT CONTEXT MATCH=031
| -1|663| NOT MEM FAULT=032
| -1|664| MEM FAULT=033
| -1|665| LOCAL=034
| -1|666| GLOBAL=035
| -1|667| USER=036
| -1|668| EXEC=037 ;Not exec
| -1|669| PAGED=040 ;PAGED and NOT AC REF
| -1|670| NOT PAGED=041 ;AC REF or NOT PAGED
| -1|671| RUN=042
| -1|672| NOT RUN=043
| -1|673| TOPS20=044
| -1|674| TOPS10=045
| -1|675| PXCT=046
| -1|676| NOT PXCT=047
| -1|677| B BIT 3=050 ;i.e. bit 3 on B port register is set
| -1|678| NOT B BIT 3=051
| -1|679| ;B BIT 4=052 ;i.e. bit 4 on B port register is set
| -1|680| ;NOT B BIT 4=053
| -1|681| B BIT 9=054
| -1|682| NOT B BIT 9=055
| -1|683| B BIT 18=056 ;i.e. bit 18 on B port register is set
| -1|684| NOT B BIT 18=057
| -1|685| ANY BUS ERROR=060
| -1|686| NO BUS ERROR=061
| -1|687| NOT AC LOW=062
| -1|688| AC LOW=063
| -1|689| LOCK=064
| -1|690| NOT LOCK=065
| -1|691| TRAP=066
| -1|692| NOT TRAP=067
| -1|693| MEM EXISTS=070
| -1|694| NOT MEM EXISTS=071
| -1|695| UNPAGED OR AC=072
| -1|696| NOT UNPAGED OR AC=073
| -1|697| NOT TIMER FLAG=074
| -1|698| TIMER FLAG=075
| -1|699| SPARE=076
| -1|700| NOT SPARE=077
| -1|701| NOT MF & NOT PXCT=062
| -1|702|
| -1|703|.TOC 2, "CROM Field - J"
| -1|704|J.AC/=<52:55> ;4 bits in J field for AC+[]
| -1|705|J/=<48:59>,.ADDRESS,.DEFAULT=0
| -1|706| U-CODE VERSION=04002 ;Version of u-code
| -1|707| ;EPT offsets
| -1|708| PFW=00500 ;Page fail word
| -1|709| ESECT=00540 ;Section pointers
| -1|710| ;UPT offsets
| -1|711| ;Console error codes
| -1|712| ERR.URC=00001 ;Unrecognized command
| -1|713| ERR.NWR=00002 ;Not while machine is running
| -1|714| ERR.NEA=00003 ;Not enough arguments
| -1|715| ERR.NXA=00004 ;Non existent address
| -1|716| ERR.MER=00005 ;Memory error
| -1|717| ;PCI hdw bits
| -1|718| A0=00010 ;PCI adr for read status or write syn/syn/dle
| -1|719| A1=00020 ;PCI adr for MR1/MR2
| -1|720| A1!A0=00030 ;PCI adr for CR
| -1|721| TXEN=00001 ;Transmitter enable in CR
| -1|722| RXEN=00004 ;Receiver enable in CR
| -1|723|
| -1|724|;Ramfile offsets
| -1|725| BYTE MASK=00000 ;Following are "byte masks"
| -1|726| PAGE # MASK=00011 ;bits 23-35 (9 bits)
| -1|727| #10B MASK=00012 ;10 bits
| -1|728| #12B MASK=00014
| -1|729| SECTION # MASK=00014 ;bits 24-35 (12 bits)
| -1|730| #13E MASK=00015
| -1|731| #22B MASK=00026
| -1|732| #23B MASK=00027
| -1|733| #24B MASK=00030
| -1|734| #27B MASK=00033
| -1|735| #30B MASK=00036
| -1|736| #32B MASK=00040
| -1|737| JFCL MASK=00040 ;bits 4-35
| -1|738| #33B MASK=00041
| -1|739|;locations 45-77 contain -1
| -1|740|
| -1|741|;Set of sliding bits
| -1|742| BIT0=00100
| -1|743| OVERFLOW=00100
| -1|744| BIT1=00101
| -1|745| CARRY 0=00101
| -1|746| BIT2=00102
| -1|747| CARRY 1=00102
| -1|748| BIT3=00103
| -1|749| FLOATING OVERFLOW=00103
| -1|750| BIT4=00104
| -1|751| FIRST PART DONE=00104
| -1|752| BIT5=00105
| -1|753| USER=00105
| -1|754| BIT6=00106
| -1|755| USER IO=00106
| -1|756| PCU=00106 ;Previous context user
| -1|757| BIT7=00107
| -1|758| PUBLIC=00107
| -1|759| BIT8=00110
| -1|760| ADDRESS FAILURE INHIBIT=00110
| -1|761| BIT9=00111
| -1|762| TRAP 2=00111
| -1|763| BIT10=00112
| -1|764| TRAP 1=00112
| -1|765| BIT11=00113
| -1|766| FLOATING UNDERFLOW=00113
| -1|767| BIT12=00114
| -1|768| NO DIVIDE=00114
| -1|769| BIT13=00115
| -1|770| BIT14=00116
| -1|771| BIT15=00117
| -1|772| BIT16=00120
| -1|773| BIT17=00121
| -1|774| BIT18=00122
| -1|775| BIT19=00123
| -1|776| BIT20=00124
| -1|777| BIT21=00125
| -1|778| BIT22=00126
| -1|779| BIT23=00127
| -1|780| BIT24=00130
| -1|781| BIT25=00131
| -1|782| BIT26=00132
| -1|783| BIT27=00133
| -1|784| BIT28=00134
| -1|785| BIT29=00135
| -1|786| BIT30=00136
| -1|787| BIT31=00137
| -1|788| BIT32=00140
| -1|789| BIT33=00141
| -1|790| BIT34=00142
| -1|791| BIT35=00143
| -1|792| BIT36=00144 ;Phoney location
| -1|793| PUSHJ FLAGS=00145 ;Flags to clear on a PUSHJ =021600,,0
| -1|794| ;UNUSED=00146
| -1|795| ;MASK12-22=00147
| -1|796|
| -1|797| ME RCOVR=00150 ;Memory error recovery routine adr
| -1|798| HALT CODE=00151 ;Halt code
| -1|799| ; -1 = do a console command
| -1|800| HALT INS=00001 ; ISP JRST 4,
| -1|801| HALT CONSOLE=00002 ;Console command
| -1|802| HALT SI=00003 ;Single instruction
| -1|803| HALT PFMER=00004 ;Memory errors, while handling page fault
| -1|804| HALT HSBMER=00005 ;Memory error while writing HSB
| -1|805| HALT ADRBRK=00010 ;Address break
| -1|806|
| -1|807| HALT IOPF=00100 ;IO Page failure
| -1|808| HALT III=00101 ;Illegal interrupt instruction
| -1|809| HALT DSP=01000 ;Illegal u-code dispatch
| -1|810| ; Or GLOBAL at IFETCH
| -1|811| HALT HME=01001 ;Hard memory error
| -1|812| HALT SUP=01005 ;Startup check
| -1|813| HME STS=00152 ;Hard memory error status
| -1|814| ; lh 2=Bus fault line,
| -1|815| ; 3-Bus parity error into CPU
| -1|816| ; rh is status from memory
| -1|817| ;Hard memory error address
| -1|818| ;Hard memory error data
| -1|819| NXM STS=00155 ;NXM memory error status
| -1|820| ; lh=.,,rh is status from memory
| -1|821| ;Soft memory error address (ECC correctable)
| -1|822| ;Soft memory error data
| -1|823|
| -1|824| SME STS=00160 ;Soft memory error status
| -1|825| ;lh=2,,rh is status from memory
| -1|826| ;Soft memory error address (ECC correctable)
| -1|827| ;Soft memory error data
| -1|828| INT RCOVR=00163 ;Where to go if interrupted while not running
| -1|829| PF RCOVR=00164 ;Routine to go to if encounter page fail
| -1|830|
| -1|831| TTYRCV BITS=00177 ;Bit for each receiver which has gone off
| -1|832|;Here begins line block for line 0
| -1|833|; See PCI section for pictures
| -1|834|
| -1|835| LNOSW=00200 ;Line 0 status word
| -1|836| LS.PI=07 ;Mask for PI channel
| -1|837| LS.CLS=010 ;Close receive buffer
| -1|838| LS.XOFF=020 ;Xoff flag
| -1|839| LS.XOFF.ENAB=040 ;Xoff enable
| -1|840| LS.RGO=0100 ;Receiver go
| -1|841| LS.RDN=0200 ;Receiver done
| -1|842| LS.REN=0400 ;Receiver enable
| -1|843| ;LS.XGO=01000 ;Transmitter go
| -1|844| LS.XDN=02000 ;Transmitter done
| -1|845| LS.XEN=04000 ;Transmitter enable
| -1|846| LS.RESET=010000 ;Reset line
| -1|847| LS.DSCHG=020000 ;Dataset change
| -1|848| LS.DSENB=040000 ;Dataset enable
| -1|849| LS.RMER=0100000 ;Receiver nxm or memory err
| -1|850| LS.XMER=0200000 ;Transmitter nxm or memory err
| -1|851| LNOMDW=0201 ;Mode word for CTY
| -1|852| LNXMDW=001 ;Offset for mode word
| -1|853| LNXSYN=002 ;Offset for synch word
| -1|854| LNXCRC=003 ;Offset for CRC word
| -1|855| ; 2-17 =0 xmt crc calculation
| -1|856| ; 20-35 =0 rcv crc calculation
| -1|857| LNXXHD=004 ;Offset for adr of transmit header
| -1|858| LNXXCHR=005 ;Offset for (DDT mode) transmit char
| -1|859| ; non DDT mode
| -1|860| ; 0-11 count of bytes left
| -1|861| ; 12-13, byte number in word
| -1|862| ; 14-35 current word physical adr
| -1|863| LNXRHD=006 ;Offset for adr of receive header
| -1|864| LNXRCHR=007 ;Offset for (DDT mode) receive char
| -1|865|;Here begins line block for line 1
| -1|866| LN1SW=00210 ;Line 1 status word
| -1|867|;Here begins line block for line 2
| -1|868| LN2SW=00220 ;Line 2 status word
| -1|869|;Here begins line block for line 3
| -1|870| LN3SW=00230 ;Line 3 status word
| -1|871|;Here begins line block for line 4
| -1|872| LN4SW=00240 ;Line 4 status word
| -1|873|;Here begins line block for line 5
| -1|874| LN5SW=00250 ;Line 5 status word
| -1|875|;Here begins line block for line 6
| -1|876| LN6SW=00260 ;Line 6 status word
| -1|877|;Here begins line block for line 7
| -1|878| LN7SW=00270 ;Line 7 status word
| -1|879| LNZSW=00300 ; End of line block
| -1|880|
| -1|881| CMDFLG=00300 ;Flags for CTY/KLINIK line
| -1|882| F.O=01 ;^O has been typed
| -1|883| F.S=02 ; Xoff has been typed
| -1|884| F.O!F.S=03
| -1|885|
| -1|886| ; F.USR=BIT4 ;
| -1|887| CMDRPT=00301 ; Repeat Counter
| -1|888| CMRPTR=00302 ; Putter for command response buffer
| -1|889| ; Byte pointer format
| -1|890| ; bits 0-17 byte number
| -1|891| ; bits 18-35 ramfile adr
| -1|892| ; ramfile word adr
| -1|893| ; bit 0 unused
| -1|894| ; bits 1-7 1st byte = 4
| -1|895| ; bits 8-14 2nd byte =3
| -1|896| ; bits 15-21 3rd byte = 2
| -1|897| ; bits 22-28 4th byte = 1
| -1|898| ; bits 29-35 5th byte = 0
| -1|899| CMRTKR=00303 ;Taker for command response buffer
| -1|900| ; Format same as C~RPTR
| -1|901| CMRBUF=00304 ;Command response buffer
| -1|902| CMRBUF-1=00303
| -1|903| CMRBUF END=00337 ;End of command response buffer
| -1|904| CMDPTR=00340 ;Pointer to put command characters into buffer
| -1|905| ; Format same as CMRPTR
| -1|906| CMDTKR=00341 ;Pointer to take command characters from buffer
| -1|907| ; Format same as CMRPTR
| -1|908| ; Only nonzero if a break has been typed
| -1|909| CMDBUF=00342 ;Command buffer
| -1|910| CMDBUF-1=00341
| -1|911| CMDBUF END=00407
| -1|912| MB REFIL=00441 ;Save MB here for a page refill
| -1|913|
| -1|914|.IF/FTADRB
| -1|915| AB IF=00442 ;Address break instruction fetch
| -1|916| AB WR=00443 ;Address break write
| -1|917| AB RD=00444 ;Address break read
| -1|918|.ENDIF/FTADRB
| -1|919|
| -1|920| EXM ADR=00445 ;Last memory adr examined or deposited
| -1|921| EIS W1=00446 ;Extend instruction saves W1 here
| -1|922| EIS W2=00447 ;Extend instruction saves W2 here
| -1|923| EIS W3=00450 ;Extend instruction saves W3 here
| -1|924| EIS W4=00451 ;Extend instruction saves W4 here
| -1|925| EIS W5=00452 ;Extend instruction saves W5 here
| -1|926| EIS W6=00453 ;Extend instruction saves W6 here
| -1|927| NBBYTE1=00454 ;Bits 0-8
| -1|928| NBBYTE3=00455 ;Bits 18-26
| -1|929|
| -1|930| X1=00454 ;Temporary location
| -1|931| X2=00455
| -1|932|.IF/DEBUG3
| -1|933| POOP FLAG=00520
| -1|934|.ENDIF/DEBUG3
| -1|935| CLK W2=00535
| -1|936| CLK W3=00536
| -1|937| ME W1=00537 ;Save W1 here on memory error
| -1|938| ME W2=00540 ;Save W2 here on memory error
| -1|939| WRIO TMP=00541 ;Temporary location for WRIO
| -1|940| HSB=00553 ;Address of halt status block
| -1|941| HSB MB=00554 ;Save MB here when writing HSB
| -1|942| HSB PMA=00555 ;Save PMA here when writing HS8
| -1|943| APR FLAGS=00556 ;Bits 6-13 are flags which are enabled
| -1|944| ; bits 24-31 are flags which are set
| -1|945| ; bits 33-35 is APR PI level
| -1|946| PI IN PROG=00557 ;Interrupts in progress in bits 29-35
| -1|947| PI SFT REQ=00560 ;Software PI requests
| -1|948| ; Bits 28-35 are software requests
| -1|949| ; bits 10-17 are tty/apr requests
| -1|950| PI LVL REG=00561 ;bit 0 is PI system on/off flag
| -1|951| ; bits 29-35 are levels on
| -1|952| PROC REG=00562 ;Processor register
| -1|953| ; For picture see SET PROC REG
| -1|954| RF PROC REG=00563 ;Last word we wrote in hdw PROC REG
| -1|955| TIME INTERVAL=00564 ;Time interval
| -1|956| INTERVAL COUNTER=00565 ;Count it here
| -1|957| TIME BASE=00566 ;Two words of time (kept in u-sec)
| -1|958| TIME BASE+1=00567 ;Low order word of time
| -1|959| CST=00571
| -1|960| CSTMASK=00572
| -1|961| CSTDATA=00573
| -1|962| AC BLOCK=00574 ;Current AC block
| -1|963| P AC BLOCK=00575 ;Previous context AC block
| -1|964| PCS=00576 ;Previous context section
| -1|965| AC 0 0=00600
| -1|966| AC 1 0=00620
| -1|967| AC 2 0=00640
| -1|968| AC 3 0=00660
| -1|969| AC 4 0=00700
| -1|970| AC 5 0=00720
| -1|971| AC 6 0=00740
| -1|972| AC 7 0=00760
| -1|973| PAGE TABLE-1=00777
| -1|974| PAGE TABLE=01000
| -1|975|
| -1|976|.TOC 2, "CROM Field - MAP SEL"
| -1|977|MAP SEL/=<48:51>
| -1|978| DISPATCH 1=010
| -1|979| OPERAND FETCH=010
| -1|980| DISPATCH 2=011
| -1|981| INST EXCT=011
| -1|982| DISPATCH 3=012
| -1|983| OPERAND STORE=012
| -1|984| DISPATCH 4=013
| -1|985| ;DISPATCH 5=014
| -1|986| ;DISPATCH 6=015
| -1|987| ;DISPATCH 7=016
| -1|988| IO 0=016
| -1|989| ;DISPATCH 8=017
| -1|990| MISC=017
| -1|991|
| -1|992|.TOC 2, "CROM Field - MEM OP"
| -1|993|MEM OP/=<60:62>,.DEFAULT=07
| -1|994| MEM HOLD "MEM OP/00" ;Do not release memory
| -1|995| MEM START READ "MEM OP/01,XFER MEM,#1_SION #1_QION,ALU_Y/YES" ;Start memory with from ...
| -1|996| MEM START WRITE "MEM OP/02,XFER MEM,#1_SION #1_QION,ALU_Y/YES" ;Start memory with adr from...
| -1|997| START IO READ "MEM OP/03,XFER MEM,#1_SION #1_QION,ALU_Y/YES" ;Start IO read with adr from...
| -1|998| START IO WRITE "MEM OP/04,XFER MEM,#1_SION #1_QION,ALU_Y/YES" ;Start IO write with adr from...
| -1|999| IO TRANSFER "MEM OP/05,XFER MEM" ;Transfer IO (on MEM bus)
| -1|1000| IO_[] "Y_[@1],ALU_Y/NO,IO TRANSFER,XFER MEM,IX_MX"
| -1|1001| ALU_IO "ALU_Y/YES,IO TRANSFER,XFER MEM,#1_SION #1_QION,IX_MX"
| -1|1002| MEM TRANSFER "MEM OP/05,XFER MEM" ;Transfer MEM
| -1|1003| ALU_MEM "ALU_Y/YES,MEM TRANSFER,XFER MEM,#1_SION #1_QION,IX_MX"
| -1|1004| []_MEM "[@1]_[@1],ALU_MEM"
| -1|1005| MEM_[] "Y_[@1],ALU_Y/NO,MEM TRANSFER,XFER MEM,IX_MX"
| -1|1006| MEM_IR_[] "Y_[@1],ALU_Y/NO,MEM OP/05,LOAD IR,IX_MX"
| -1|1007| ; "MEM OP/06" ;Reserved
| -1|1008| ALLOW DCH "MEM OP/07" ;Allow data channels
| -1|1009|
| -1|1010|.TOC 2, "CROM Field - Y SEL"
| -1|1011|Y SEL/=<63:66>,.DEFAULT=0
| -1|1012| XFER PIPELINE "Y SEL/01"
| -1|1013| J[]_Y24-Y35 "J/@1,XFER PIPELINE,ALU_Y/NO"
| -1|1014| FJ[]_[] "J[@1]_Y24-Y35,Y_[@2]" ;bits 0-23 from F, bits 24-35 from J
| -1|1015| F_Q FJ[]_[] "J[@1]_Y24-Y35,F_Q Y_[@2]" ;bits 0-23 from F, bits 24-35 from J
| -1|1016| J[]_[] "ZERO_F,FJ[@1]_[@2]"
| -1|1017| JS[]_[] "ZERO_F,J[@1]_Y24-Y35,B SEL/@2,#1_SION #1_QION,F_LRS Y_B" ;Bit 0 or J_[]
| -1|1018| JN[]_[] "ONES_F,FJ[@1]_[@2]" ;bits 0-23 or J[]_[]
| -1|1019| []J[]_[] "[@1]_F,J[@2]_Y24-Y35,Y_[@3]" ;bits 0-23 from R-SEL, bits 24-35
| -1|1020| ALU_CTR "ALU_Y/YES,XFER PIPELINE" ;do not need U PROG OP
| -1|1021| J[]_CTR "J/@1,U PROG OP/LDCT" ;Load 2910 counter from J field
| -1|1022| DISP []_Y "XFER PIPELINE,ALU_Y/NO,MAP SEL/@1,U PROG OP/CJV,TEST SEL/NEVER"
| -1|1023| XFER MEM "Y SEL/02" ;Enable MEM bus transceivers
| -1|1024| ALU_PCI "ALU_Y/YES,Y SEL/03"
| -1|1025| PCI_ALU "ALU_Y/NO,Y SEL/03"
| -1|1026| ALU_RAMFILE "ALU_Y/YES,Y SEL/04"
| -1|1027| []_RAMFILE "[K -1]&[@1]_Y,ALU_RAMFILE"
| -1|1028| RAMFILE_Y "ALU_Y/NO,Y SEL/04"
| -1|1029| RAMFILE_[] "RAMFILE_Y,Y_[@1]"
| -1|1030| ALU_MR2 "Y SEL/05,ALU_Y/YES"
| -1|1031| STATUS_Y "Y SEL/06"
| -1|1032| SWAPPER_Y "R SEL TYP/REG EXT,ALU_Y/NO,Y SEL/07" ;A bus swapped goes to Y
| -1|1033| SWAP []_[] "SWAPPER_Y,R SEL/@1,Y_[@2]"
| -1|1034| SWAP []_[] F_Q "SWAPPER_Y,R SEL/@1,Y_[@2] F_Q"
| -1|1035| ALU_PROC REG "Y SEL/010,ALU_Y/YES"
| -1|1036| LOAD IR "Y SEL/011" ;This implies transfer mem
| -1|1037|
| -1|1038|T/=<67:69>,.DEFAULT=0 ;Time
| -1|1039|MARK1/=<70>,.DEFAULT=0
| -1|1040|MARK2/=<71>,.DEFAULT=0
| -1|1041|
| -1|1042|
| -1|1043|.TOC "Instruction Macros"
| -1|1044|
| -1|1045| NOOP "U PROG OP/CONT"
| -1|1046| J[]_D "J/@1"
| -1|1047| GOTO Y "XFER PIPELINE,ALU_Y/YES,U PROG OP/CJP,TEST SEL/ALWAYS"
| -1|1048| CALL Y "XFER PIPELINE,ALU_Y/YES,U PROG OP/CJS,TEST SEL/ALWAYS"
| -1|1049| GOTO [] "TEST SEL/ALWAYS,U PROG OP/CJP,J[@1]_D"
| -1|1050| GOTOP [] "TEST SEL/ALWAYS,U PROG OP/CJPP,J[@1]_D" ;Goto and pop stack
| -1|1051| POP "TEST SEL/ALWAYS,U PROG OP/TEOL"
| -1|1052|
| -1|1053| CALL [] "TEST SEL/ALWAYS,U PROG OP/CJS,J[@1]_D"
| -1|1054| RETURN "TEST SEL/ALWAYS,U PROG OP/CRTN"
| -1|1055|
| -1|1056| RFCT "U PROG OP/RFCT"
| -1|1057| LOOP [] "J[@1]_D,U PROG OP/RPCT"
| -1|1058| TWB [] [] "@1,J[@2]_D,U PROG OP/TWB"
| -1|1059| PUSH "TEST SEL/NEVER,U PROG OP/PUSH"
| -1|1060| PUSH J[]_CTR "TEST SEL/ALWAYS,U PROG OP/PUSH,J[@1]_D"
| -1|1061|
| -1|1062| IF [] THEN [] "TEST SEL/@1,U PROG OP/CJP,J[@2]_D"
| -1|1063| IF [] THENP [] "TEST SEL/@1,U PROG OP/CJPP,J[@2]_D" ;If branch also pop
| -1|1064| IF [] THEN Y "TEST SEL/@1,U PROG OP/CJP,XFER PIPELINE,ALU_Y/YES"
| -1|1065| IF [] CALL [] "TEST SEL/@1,U PROG OP/CJS,J[@2]_D"
| -1|1066| IF [] JSRP [] "TEST SEL/@1,U PROG OP/JSRP,J[@2]_D"
| -1|1067| IF [] D [] "TEST SEL/@1,DISP [@2]"
| -1|1068| IF [] RETURN "TEST SEL/@1,U PROG OP/CRTN"
| -1|1069|
| -1|1070| IF CT [] THEN [] "TEST SEL/CT,@1,U PROG OP/CJP,J[@2]_D" ;CT is 2904 STATUS TEST
| -1|1071| IF CT [] THENP [] "TEST SEL/CT,@1,U PROG OP/CJPP,J[@2]_D"
| -1|1072| IF CT [] THEN Y "TEST SEL/CT,@1,U PROG OP/CJP,XFER PIPELINE,ALU_Y/YES"
| -1|1073| IF CT [] CALL [] "TEST SEL/CT,@1,U PROG OP/CJS,J[@2]_D"
| -1|1074| IF CT [] JSRP [] "TEST SEL/CT,@1,U PROG OP/JSRP,J[@2]_D"
| -1|1075| IF CT [] RETURN "TEST SEL/CT,@1,U PROG OP/CRTN"
| -1|1076| IF CT [] D [] "TEST SEL/CT,@1,DISP [@2]"
| -1|1077| IF NOT CT [] THEN [] "TEST SEL/NOT CT,@1,U PROG OP/CJP,J[@2]_D"
| -1|1078| IF NOT CT [] THENP [] "TEST SEL/NOT CT,@1,U PROG OP/CJPP,J[@2]_D"
| -1|1079| IF NOT CT [] THEN Y "TEST SEL/NOT CT,@1,U PROG OP/CJP,XFER PIPELINE,ALU_Y/YES"
| -1|1080| IF NOT CT [] CALL [] "TEST SEL/NOT CT,@1,U PROG OP/CJS,J[@2]_D"
| -1|1081| IF NOT CT [] JSRP [] "TEST SEL/NOT CT,@1,U PROG OP/JSRP,J[@2]_D"
| -1|1082| IF NOT CT [] RETURN "TEST SEL/NOT CT,@1,U PROG OP/CRTN"
| -1|1083| IF NOT CT [] D [] "TEST SEL/NOT CT,@1,DISP [@2]"
| -1|1084|
| -1|1085| DISP [] "MAP SEL/@1,U PROG OP/CJV"
| -1|1086| DISPATCH [] "TEST SEL/ALWAYS,DISP [@1]"
| -1|1087|
| -1|1088| J[]_RAMFILE ADR "J[@1]_Y24-Y35,ALU_Y/NO,Y_RAMFILE ADR"
| -1|1089|
| -1|1090| Y_[] "B SEL/@1,Y_B"
| -1|1091| Y_[] F_Q "B SEL/@1,Y_B F_Q"
| -1|1092| F_Q Y_[] "B SEL/@1,Y_B F_Q"
| -1|1093| F_[] "B SEL/@1,F_B"
| -1|1094| F_Q RAMFILE_[] "F_Q Y_[@1],RAMFILE_Y"
| -1|1095| F_Q_[] "B SEL/@1,F_Q_B"
| -1|1096| ROR F_[] "LRS F_B,SIO0_SION QIO0_QION,B SEL/@1" ;ROR F_Q_Q WRITE=01
| -1|1097|
| -1|1098| F_ROR Y_[] "F_LRS Y_B,SIO0_SION QIO0_QION,B SEL/@1" ;ROR F_Q_Q WRITE=01
| -1|1099| F_Y LSRQ_Q "F_Y QRS_Q,#0_SION #0_QION" ;Right shift Q, shift in 0
| -1|1100| F_Y RORQ_Q "F_Y QRS_Q,SIO0_SION QIO0_QION" ;Right shift Q, shift in 0
| -1|1101| LSZ F_B "LLS F_B,#0_SIO0 #0_QIO0"
| -1|1102| LSZ F_[] "LSZ F_B,B SEL/@1"
| -1|1103| ROL F_B "LLS F_B,SION_SIO0 QION_QIO0" ;LLS F_Y Q_Q WRITE=011
| -1|1104| ROL F_[] "ROL F_B,B SEL/@1" ;LLS F_Y Q_Q WRITE=011
| -1|1105|
| -1|1106| ZERO_F "ALU OP/LOW,ALU 10/Q_S"
| -1|1107| ZERO_Y "ZERO_F,F_Y"
| -1|1108| ZERO_[] "ZERO_F,F_[@1]"
| -1|1109|
| -1|1110| ONES_F "ALU OP/0,ALU 10/Q_S"
| -1|1111| ONES_[] "ONES_F,F_[@1]"
| -1|1112|
| -1|1113| BIT0_[] "ZERO_F,LRS F_B,#1_SION #1_QION,B SEL/@1"
| -1|1114|
| -1|1115| Q+C_F "ALU 10/Q_S,ALU OP/R+C"
| -1|1116| Q+1_F "#1_CO,Q+C_F"
| -1|1117| Q_F "Q&[K -1]_F"
| -1|1118| Q_Y "Q_F,F_Y"
| -1|1119| Q_[] "Q_F,F_[@1]"
| -1|1120|
| -1|1121| []+C_F "R SEL/@1,ALU OP/R+C,ALU 10/Q_S"
| -1|1122| []_F "[@1]+C_F,#0_CO"
| -1|1123| []_Y "[@1]+C_F,F_Y"
| -1|1124| []_Q "[@1]+C_F,F_Q"
| -1|1125| []_Q RAMFILE_[] "[@1]+C_F,F_Q Y_[@2],RAMFILE_Y"
| -1|1126| []_[] "[@1]_F,F_[@2]"
| -1|1127| []_Q_[] "[@1]_F,F_Q_[@2]"
| -1|1128|
| -1|1129| B[]_F "S SEL[@1],#0_CO,ALU OP/S+C"
| -1|1130|
| -1|1131| #2*Q_Q "QLS_Q,#0_SIO0 #0_QIO0"
| -1|1132| #2*Q_[] "Q_F,LSZ F_[@1]"
| -1|1133| #2*[]_Q "R SEL/@1,S SEL[@1],#0_CO,ALU OP/R+S+C,F_Q"
| -1|1134| #2*[]_[] "[@1]_F,LSZ F_[@2]"
| -1|1135| #2*([]+[])_B "[@1]+[@2]_F,LSZ F_B"
| -1|1136| #4*[]_B "#2*([@1]+[@1])_B"
| -1|1137|
| -1|1138| COMPLEMENT []_F "R SEL/@1,ALU OP/RBAR+C,#0_CO"
| -1|1139| COMPLEMENT Q_F "ALU 10/Q_S,ALU OP/SBAR+C,#0_CO"
| -1|1140|
| -1|1141| ASR []_[] "[@1]_F,B SEL/@2,LRS F_B,MN_SION SIO0_QION" ;Right shift,
| -1|1142| ASR []_[] MC "[@1]_F,B SEL/@2,LRS F_B,#0_SION SIO0_MC MN_QION" ;Right shift,
| -1|1143| ASRC []_[] "[@1]_F,B SEL/@2,ASRC_B,MN_SION SIO0_QION"
| -1|1144| ROR []_[] "[@1]_F,B SEL/@2,LRS F_B,SIO0_SION QIO0_QION"
| -1|1145| ROR F_B ROR Q_Q "LSRC_B,SIO0_SION QIO0_QION"
| -1|1146| F LRS_[] "B SEL/@1,LRS F_B,#0_SION #0_QION"
| -1|1147| F LRS_[] SIO0_MC "B SEL/@1,LRS F_B,#0_SION SIO0_MC MN_QION"
| -1|1148|
| -1|1149| LRS []_[] "[@1]_F,F LRS_[@2]"
| -1|1150| RORC []_[] "[@1]_F,B SEL/@2,LSRC_B,QIO0_SION SIO0_QION"
| -1|1151| LSRC []_[] "[@1]_F,B SEL/@2,LSRC_B,#0_SION SIO0_QION"
| -1|1152| ROL []_[] "[@1]_F,B SEL/@2,ROL F_B"
| -1|1153|
| -1|1154| ROL []_[] ROL Q_Q "[@1]_F,B SEL/@2,LLSC_B,SION_SIO0 QION_QIO0"
| -1|1155| LLS [] "[@1]_F,LSZ F_[@2]"
| -1|1156| LLS []_[] LLS Q_Q "[@1]_F,B SEL/@2,LLSC_B,#0_SIO0 #0_QIO0"
| -1|1157| ROLC []_[] "[@1]_F,B SEL/@2,LLSC_B,SION_QIO0 QION_SIO0"
| -1|1158| LLSC []_[] "[@1]_F,B SEL/@2,LLSC_B,QION_SIO0 #0_QIO0"
| -1|1159|
| -1|1160| NEGATE Q_F "ALU 10/Q_S,#1_CO,ALU OP/SBAR+C"
| -1|1161|
| -1|1162| []BAR+C_F "R SEL/@1,ALU OP/RBAR+C,ALU 10/Q_S"
| -1|1163| NEGATE []_F "[@1]BAR+C_F,#1_CO"
| -1|1164|
| -1|1165| []+1_F "[@1]+C_F,#1_CO"
| -1|1166| []+1_Y "[@1]+1_F,F_Y"
| -1|1167| []+1_Q "[@1]+1_F,F_Q"
| -1|1168| []+1_Q RAMFILE_[] "[@1]+1_F,Y_B,F_Q,RAMFILE_Y,B SEL/@2"
| -1|1169| []+1_[] "[@1]+1_F,F_[@2]"
| -1|1170| []+1_Q_[] "[@1]+1_F,F_Q_[@2]"
| -1|1171| []+2_B "S SEL[@1],#1_CO,ALU SP FUN/S+1+C_B,ALU_Y/YES"
| -1|1172|
| -1|1173| Q+[]+C_F "R SEL/@1,ALU 10/Q_S,ALU OP/R+S+C"
| -1|1174| Q+[]+1_F "Q+[@1]+C_F,#1_CO"
| -1|1175| Q+[]_F "Q+[@1]+C_F,#0_CO"
| -1|1176| Q+[]_Y "Q+[@1]_F,F_Y"
| -1|1177| Q+[]_Q "Q+[@1]_F,F_Q"
| -1|1178| Q+[]_[] "Q+[@1]_F,F_[@2]"
| -1|1179| []+[]+C_F "R SEL/@1,S SEL[@2],ALU OP/R+S+C"
| -1|1180| []+[]+C_B "[@1]+[@2]+C_F,F_B"
| -1|1181| []+[]_F "[@1]+[@2]+C_F,#0_CO"
| -1|1182| []+[]_Y "[@1]+[@2]_F,F_Y"
| -1|1183| []+[]_Q "[@1]+[@2]_F,F_Q"
| -1|1184| []+[]_B "[@1]+[@2]_F,F_B"
| -1|1185| []+[]+1_F "[@1]+[@2]+C_F,#1_CO"
| -1|1186| []+[]+1_Y "[@1]+[@2]+C_F,F_Y,#1_CO" ; Doyle added this
| -1|1187|
| -1|1188| Q-[]_F "R SEL/@1,ALU 10/Q_S,#1_CO,ALU OP/S-R-1+C"
| -1|1189| Q-[]_Y "Q-[@1]_F,F_Y"
| -1|1190| []-Q_F "R SEL/@1,ALU 10/Q_S,#1_CO,ALU OP/R-S-1+C"
| -1|1191| []-[]-1+C_F "R SEL/@1,S SEL[@2],ALU OP/R-S-1+C"
| -1|1192| []-[]-1_F "[@1]-[@2]-1+C_F,#0_CO"
| -1|1193| []-[]_F "[@1]-[@2]-1+C_F,#1_CO"
| -1|1194| []-[]_Y "[@1]-[@2]-1_F,F_Y"
| -1|1195| []-[]_Q "[@1]-[@2]-1_F,F_Q"
| -1|1196| []-[]_B "[@1]-[@2]-1_F,F_B"
| -1|1197| []-[]-1+C_A "R SEL/@2,S SEL[@1],ALU OP/S-R-1+C,F_B"
| -1|1198| []-[]-1_A "[@1]-[@2]-1+C_A,#0_CO"
| -1|1199| []-[]_A "[@1]-[@2]-1+C_A,#1_CO"
| -1|1200|
| -1|1201| SM []_B "S SEL[@1],CX_CO,ALU SP FUN/SM,ALU_Y/YES" ;Sign/magnitude, twos complement
| -1|1202| MUL [] [] "R SEL/@1,S SEL[@2],#0_CO,ALU SP FUN/MUL,#0_SION SIO0_QION,ALU_Y/YES"
| -1|1203| TCM [] [] "R SEL/@1,S SEL[@2],#0_CO,ALU SP FUN/TCM,#0_SION SIO0_QION,ALU_Y/YES"
| -1|1204| TCM COR [] [] "R SEL/@1,S SEL[@2],CX_CO,ALU SP FUN/TCM COR,#0_SION SIO0_QION,ALU_Y/YES"
| -1|1205| TCDIV [] []_B "R SEL/@1,S SEL[@2],CX_CO,ALU SP FUN/TCDIV,SION_QIO0 QION_SIO0,ALU_Y/YES"
| -1|1206| TCDIV COR [] []_B "R SEL/@1,S SEL[@2],CX_CO,ALU SP FUN/TCDIV COR,#1_SIO0 #1_QIO0,ALU_Y/YES"
| -1|1207|
| -1|1208| Q&[]_F "R SEL/@1,ALU 10/Q_S,ALU OP/R.AND.S"
| -1|1209| Q&[]_Y "Q&[@1]_F,F_Y"
| -1|1210| Q&[]_Q "Q&[@1]_F,F_Q"
| -1|1211| Q&[]_Q RAMFILE_[] "Q&[@1]_F,F_Q,Y_[@2],RAMFILE_Y"
| -1|1212| Q&[]_[] "Q&[@1]_F,F_[@2]"
| -1|1213| []&[]_F "R SEL/@1,S SEL[@2],ALU OP/R.AND.S"
| -1|1214| []&[]_Y "[@1]&[@2]_F,F_Y"
| -1|1215| []&[]_Q "[@1]&[@2]_F,F_Q"
| -1|1216| []&[]_B "[@1]&[@2]_F,F_B"
| -1|1217|
| -1|1218| []BAR&Q_F "R SEL/@1,ALU 10/Q_S,ALU OP/RBAR.AND.S"
| -1|1219| []BAR&Q_Y "[@1]BAR&Q_F,F_Y"
| -1|1220| []BAR&[]_F "R SEL/@1,S SEL[@2],ALU OP/RBAR.AND.S"
| -1|1221| []BAR&[]_Y "[@1]BAR&[@2]_F,F_Y"
| -1|1222| []BAR&[]_Q "[@1]BAR&[@2]_F,F_Q"
| -1|1223| []BAR&[]_B "[@1]BAR&[@2]_F,F_B"
| -1|1224|
| -1|1225|
| -1|1226| Q.OR.[]_F "R SEL/@1,ALU 10/Q_S,ALU OP/R.OR.S"
| -1|1227| Q.OR.[]_Y "Q.OR.[@1]_F,F_Y"
| -1|1228| Q.OR.[]_Q "Q.OR.[@1]_F,F_Q"
| -1|1229| Q.OR.[]_[] "Q.OR.[@1]_F,F_[@2]"
| -1|1230| [].OR.[]_F "R SEL/@1,S SEL[@2],ALU OP/R.OR.S"
| -1|1231| [].OR.[]_Y "[@1].OR.[@2]_F,F_Y"
| -1|1232| [].OR.[]_Q "[@1].OR.[@2]_F,F_Q"
| -1|1233| [].OR.[]_B "[@1].OR.[@2]_F,F_B"
| -1|1234| Q.XOR.[]_F "R SEL/@1,ALU 10/Q_S,ALU OP/R.XOR.S"
| -1|1235| [].XOR.[]_F "R SEL/@1,S SEL[@2],ALU OP/R.XOR.S"
| -1|1236| [].XOR.[]_Y "[@1].XOR.[@2]_F,F_Y"
| -1|1237|
| -1|1238| Q.XNOR.[]_F "R SEL/@1,ALU 10/Q_S,ALU OP/R.XNOR.S"
| -1|1239| [].XNOR.[]_F "R SEL/@1,S SEL[@2],ALU OP/R.XNOR.S"
| -1|1240|
| -1|1241| READ [] "[@1]_Q_[E],SPEC SEL/PAGE TABLE ENTRY,CALL [MEMORY READ]"
| -1|1242| WRITE [] "[@1]_Q_[E],SPEC SEL/PAGE TABLE ENTRY,CALL [MEM WRITE 1]"
| -1|1243|
| -1|1244| CHECK INTERRUPTS "IF [PI REQ] CALL [CHK INT]"
| -1|1245|
| -1|1246| SECTION SELECT "SPEC SEL/PAGE TABLE ENTRY"
| -1|1247|
| -1|1248| LIGHTS [] "J[@1]_[PXCT]" ; Things to fix !!!
| -1|1249|
| -1|1250|;
| -1|1251|; Execution begins here
| -1|1252|;
| -1|1253|; Note:
| -1|1254|; The first few (6) instructions pop am2910 stack to ensure that
| -1|1255|; the stack is empty.
| -1|1256|;
| -1|1257|
000,000,0,04,10,1,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,15,01,00,6000,00,7,01,0,0,0,0000|1258|0:
|0000|1259|BEGIN: J[06000]_[W1],POP ;Will become 30000 next
|0000|1260| ;J[02515]_Y24-Y35,[W1]+[W1]_F, ;300 baud
|0000|1261| ;J[05115]_Y24-Y35,[W1]+[W1]_F, ;2400 baud
000,000,1,11,03,0,02,0,00,0,0,00,00,11,00,00,0,20,1,1,0,15,01,00,7115,00,7,01,0,0,0,0001|1262| J[07115]_Y24-Y35,[W1]+[W1]_F, ;9600 baud
|0001|1263| F_LSZ Y_[W1],POP ; Ext clocks, 300 baud,
|0001|1264| ; 1 stop bit, 8bits, async lx
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,03,0,20,1,1,0,15,01,00,0201,00,7,01,0,0,0,0002|1265| J[LNOMDW]_RAMFILE ADR,POP ;CTY mode word
000,000,0,04,10,0,02,2,00,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,5020,00,7,07,0,0,0,0003|1266| SWAP [W1]_[W1],
|0003|1267| CALL [W1_RAMFILE]
|0003|1268| ; GOTO [TEST]
|0003|1269|
|0003|1270|;Here to check system seems to be ok
|0003|1271|; This clobbers everything in Ramfile except CTY status and mode
|0003|1272|; After checking will initialize Ramfile and 2903 regs
|0003|1273|
|0003|1274|
000,000,0,04,00,1,00,0,77,0,0,00,00,00,00,00,0,20,1,1,1,15,01,00,0000,00,7,00,0,0,0,0004|1275|TEST:
|0004|1276|;Initialize some registers
|0004|1277| ONES_[K -1],POP
000,000,0,04,10,1,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,15,01,00,0001,00,7,01,0,0,0,0005|1278| J[1]_[W1],POP
000,000,0,04,10,0,02,2,57,0,0,00,00,00,00,00,0,20,1,1,0,15,01,00,0000,00,7,07,0,0,0,0006|1279| SWAP [W1]_[BIT17],POP
|0006|1280|
|0006|1281|.IF/FTDIAG
|0006|1282|;First quick check on 2903, 2904, and 2910
|0006|1283| LIGHTS [1] ;1st ALU test
000,000,0,04,10,1,00,0,60,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0001,00,7,01,0,0,0,0007|1284| JN[07776]_[W1] ;-2 to W1
000,000,0,14,06,1,02,0,00,0,0,00,00,00,00,00,0,76,1,1,1,03,03,00,1306,00,7,00,0,0,0,0009|1285| [W1]_Y,
|0009|1286| IF NOT CT [IN] THEN [ALU BROKE]
000,000,0,04,06,1,02,0,00,0,1,00,00,00,00,00,0,64,1,1,1,03,02,00,1306,00,7,00,0,0,0,0010|1287| [W1]+1_[W1],
|0010|1288| IF CT [IZ] THEN [ALU BROKE]
000,000,0,04,06,1,02,0,00,0,1,00,00,00,00,00,0,64,1,1,1,03,03,00,1306,00,7,00,0,0,0,0011|1289| [W1]+1_[W1],
|0011|1290| IF NOT CT [IZ] THEN [ALU BROKE]
|0011|1291|;Right shift a bit through Q register
|0011|1292|;Left rotate a bit through W1
|0011|1293|;Count -36 to zero
|0011|1294| JS[0]_[W1] ;400000,,0_W1
000,000,0,06,06,1,02,0,00,0,0,00,00,00,00,00,0,20,1,1,0,14,00,00,0043,00,7,00,0,0,0,0013|1295| [W1]_Q,J[043]_CTR ;44(8) = 36(10)
|0013|1296| JN[07733]_[W2] ;Number to count up to zero
000,000,0,05,14,1,77,0,00,0,0,00,00,01,00,00,0,64,1,1,1,03,02,00,1306,00,7,00,0,0,0,0015|1297|TALU21: Q_F,F_Y LSRQ_Q, ;Shift Q right
|0015|1298| IF CT [IZ] THEN [ALU BROKE]
000,000,1,11,06,1,02,0,00,0,0,00,00,51,00,00,0,64,1,1,1,03,02,00,1306,00,7,00,0,0,0,0016|1299| ROL [W1]_[W1], ;Put 1 in W1
|0016|1300| IF CT [IZ] THEN [ALU BROKE]
000,000,0,04,06,1,06,0,04,0,1,00,00,00,00,00,0,64,1,1,1,03,02,00,1306,00,7,00,0,0,0,0017|1301| [W2]+1_[W2], ;Check did not go to zero yet
|0017|1302| IF CT [IZ] THEN [ALU BROKE]
|0017|1303| LOOP [TALU21] ;Back for rest of count
000,000,0,05,14,1,77,0,00,0,0,00,00,01,00,00,0,64,1,1,1,03,03,00,1306,00,7,00,0,0,0,0019|1304| Q_F,F_Y LSRQ_Q,
|0019|1305| IF NOT CT [IZ] THEN [ALU BROKE]
000,000,1,11,06,1,02,0,00,0,0,00,00,51,00,00,0,76,1,1,1,03,03,00,1306,00,7,00,0,0,0,0020|1306| ROL [W1]_[W1], ;Rotate one more position
|0020|1307| IF NOT CT [IN] THEN [ALU BROKE]
000,000,0,14,03,0,77,0,00,0,0,00,00,00,00,00,0,64,1,1,1,03,03,00,1306,00,7,00,0,0,0,0021|1308| [K -1]+[W1]_Y,
|0021|1309| IF NOT CT [IZ] THEN [ALU BROKE]
000,000,0,04,06,1,06,0,04,0,1,00,00,00,00,00,0,64,1,1,1,03,03,00,1306,00,7,00,0,0,0,0022|1310| [W2]+1_[W2], ;Final count out
|0022|1311| IF NOT CT [IZ] THEN [ALU BROKE]
|0022|1312|
|0022|1313|;Verify UX and MX in 2904
|0022|1314|;For this test bits 28-31 is UX, 32-35 is MX
|0022|1315|
|0022|1316| LIGHTS [2]
000,000,0,04,10,1,00,0,60,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0002,00,7,01,0,0,0,0023|1317| J[0377]_[W2] ;Start with all flags
000,000,0,04,10,1,00,0,04,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0377,00,7,01,0,0,0,0024|1318|.IF/FTBB
|0024|1319|;Set UX from W2 bits 28-31, set KX from W2 bits 32-35
000,000,0,01,06,1,06,0,00,0,0,00,00,51,00,00,0,20,1,1,1,14,00,00,0002,00,7,00,0,0,0,0025|1320|TUMX12: ROR [W2]_[W1],J[2]_CTR
000,000,0,01,06,1,02,0,00,0,0,00,00,51,00,00,0,00,1,0,1,11,00,00,0032,00,7,00,0,0,0,0026|1321|TUMX13: ROR [W1]_[W1],Y_MX,LOOP [TUMX13] ;Load MA from 32-35
000,000,0,01,06,1,02,0,00,0,0,00,00,51,00,00,0,02,0,1,1,14,00,00,0002,00,7,00,0,0,0,0027|1322| ROR [W1]_[W1],
|0027|1323| J[2]_CTR,MX_UX ;Load UX from 32-35
000,000,0,01,06,1,02,0,00,0,0,00,00,51,00,00,0,00,1,0,1,11,00,00,0034,00,7,00,0,0,0,0028|1324|TUMX14: ROR [W1]_[W1],Y_MX,LOOP [TUMX14] ;Load MX from 28-31
|0028|1325| MX_UX UX_MX ;Exchange MX and Ux
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,02,0,0,0,16,00,00,0000,00,7,00,0,0,0,0029|1326|
|0029|1327|;Verify UX & MX by reading onto Y bus
000,000,0,04,10,0,00,0,00,0,0,00,00,00,00,00,0,01,1,1,0,14,00,00,0003,00,7,06,0,0,0,0030|1328| UX_[W1],J[3]_CTR ;Get micro flags
000,000,1,11,06,1,02,0,00,0,0,00,00,51,00,00,0,20,1,1,1,11,00,00,0037,00,7,00,0,0,0,0031|1329|TUMX15: ROL [W1]_[W1],LOOP [TUMX15] ;Put UX in W1 bits 31-35
|0031|1330| J[017]_[W3] ;Mask for extra Y bus bits
000,000,0,07,14,0,12,0,00,0,0,00,00,00,00,00,2,20,1,1,0,14,00,00,0003,00,7,06,0,0,0,0033|1331| [W3]&[W1]_F,F_Q Y_[W1], ;Mask off extra bits
|0033|1332| MX_Y,J[3]_CTR
000,000,1,13,06,1,02,0,00,0,0,00,00,51,00,00,0,20,1,1,1,11,00,00,0042,00,7,00,0,0,0,0034|1333|TUMX16: ROL [W1]_[W1] ROL Q_Q,LOOP [TUMX16] ;Shift left 4 places
|0034|1334| [W3]&[W1]_B ;Mask off extra bits
000,000,0,04,14,0,12,0,00,0,0,00,00,00,00,00,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,0035|1335| Q.OR.[W1]_[W1]
000,000,0,14,13,0,02,0,04,0,0,00,00,00,00,00,0,64,1,1,1,03,03,00,1306,00,7,00,0,0,0,0037|1336| [W1].XOR.[W2]_Y,
|0037|1337| IF NOT CT [IZ] THEN [ALU BROKE]
|0037|1338|.ENDIF/FTBB
|0037|1339|.IFNOT/FTBB
|0037|1340|;Set UX from W2 bits 28-31, set MX from W2 bits 32-35
|0037|1341|TUMX12: LRS [W2]_[W1],J[2]_CTR
|0037|1342|TUMX13: LRS [W1]_[W1],Y_MX, ;Load MX from 28-31
|0037|1343| LOOP [TUMX13]
|0037|1344| [W2]_Y,Y_MX MX_UX ;Load UX from MX and MX from Y
|0037|1345|
|0037|1346|;Verify UX & MX by reading onto Y bus
|0037|1347| UX_[W1] ;Get micro flags
|0037|1348| J[17]_[W3] ;Mask for extra Y bus bits
|0037|1349| [W3]&[W1]_B,J[1]_CTR ;Mask off extra bits
|0037|1350|TUMX16: #4*[W1]_B,LOOP [TUMX16] ;Put UX in W1 bits 28-31
|0037|1351| MX_[W1],[W3]&[W1]_F,F_Q Y_[W1] ;Mask off extra bits
|0037|1352| Q.OR.[W1]_[W1] ;Combine UX and MX
|0037|1353| [W1].XOR.[W2]_Y,
|0037|1354| IF NOT CT [II] THEN [ALU BROKE]
|0037|1355|.ENDIF/FTBB
|0037|1356|
|0037|1357|;Verify UX & MX with TEST SELECT
000,000,0,04,10,1,00,0,00,0,0,00,00,00,00,00,0,26,1,1,1,01,02,00,1263,00,7,00,0,0,0,0038|1358| ZERO_[W1],IF CT [UOVR] CALL [W1+1_W1]
000,000,0,04,03,0,02,0,00,0,0,00,00,00,00,00,0,32,1,1,1,01,02,00,1263,00,7,00,0,0,0,0039|1359| [W1]+[W1]_B,IF CT [UC] CALL [W1+1_W1]
000,000,0,04,03,0,02,0,00,0,0,00,00,00,00,00,0,36,1,1,1,01,02,00,1263,00,7,00,0,0,0,0040|1360| [W1]+[W1]_B,IF CT [UN] CALL [W1+1_W1]
000,000,0,04,03,0,02,0,00,0,0,00,00,00,00,00,0,24,1,1,1,01,02,00,1263,00,7,00,0,0,0,0041|1361| [W1]+[W1]_B,IF CT [UZ] CALL [W1+1_W1]
000,000,0,04,03,0,02,0,00,0,0,00,00,00,00,00,0,46,1,1,1,01,02,00,1263,00,7,00,0,0,0,0042|1362| [W1]+[W1]_B,IF CT [MOVR] CALL [W1+1_W1]
000,000,0,04,03,0,02,0,00,0,0,00,00,00,00,00,0,52,1,1,1,01,02,00,1263,00,7,00,0,0,0,0043|1363| [W1]+[W1]_B,IF CT [MC] CALL [W1+1_W1]
000,000,0,04,03,0,02,0,00,0,0,00,00,00,00,00,0,56,1,1,1,01,02,00,1263,00,7,00,0,0,0,0044|1364| [W1]+[W1]_B,IF CT [MN] CALL [W1+1_W1]
000,000,0,04,03,0,02,0,00,0,0,00,00,00,00,00,0,44,1,1,1,01,02,00,1263,00,7,00,0,0,0,0045|1365| [W1]+[W1]_B,IF CT [MZ] CALL [W1+1_W1]
000,000,0,14,13,0,02,0,04,0,0,00,00,00,00,00,0,64,1,1,1,03,03,00,1306,00,7,00,0,0,0,0046|1366| [W1].XOR.[W2]_Y,
|0046|1367| IF NOT CT [IZ] THEN [ALU BROKE]
|0046|1368|
000,000,0,04,03,0,77,0,04,0,0,00,00,00,00,00,0,76,1,1,1,03,03,00,0031,00,7,00,0,0,0,0047|1369| [K -1]+[W2]_B,
|0047|1370| IF NOT CT [IN] THEN [TUMX12]
|0047|1371|
|0047|1372|
|0047|1373|;Verify LOCAL, USER, PAGED, RUN, TOPS20, PXCT, and TRAP latches
|0047|1374|
|0047|1375| LIGHTS [3]
000,000,0,04,10,1,00,0,60,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0003,00,7,01,0,0,0,0048|1376| J[0177]_[W2] ;1st check all latches
000,000,0,04,10,1,00,0,04,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0177,00,7,01,0,0,0,0049|1377|
000,000,0,07,06,1,06,0,10,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0100,00,7,01,0,0,0,0050|1378|TLTCH2:
|0050|1379|;Here to set LOCAL, USER, PAGED, RUN, TOPS20, PXCT, & TRAP latches from W2
|0050|1380| J[0100]_Y24-Y35,[W2]_F,Y_[W3] F_Q
000,000,0,15,14,1,12,0,00,0,0,00,10,00,00,00,0,64,1,1,1,01,03,00,1262,00,7,00,0,0,0,0051|1381| Q&[W3]_F,F_Y QLS_Q,CLEAR LOCAL,
|0051|1382| IF NOT CT [IZ] CALL [SET LOCAL LATCH]
000,000,0,15,14,1,12,0,00,0,0,00,20,00,00,00,0,64,1,1,1,01,03,00,2322,00,7,00,0,0,0,0052|1383| Q&[W3]_F,F_Y QLS_Q,CLEAR USER,
|0052|1384| IF NOT CT [IZ] CALL [SET USER LATCH]
000,000,0,15,14,1,12,0,00,0,0,00,30,00,00,00,0,64,1,1,1,01,03,00,3315,00,7,00,0,0,0,0053|1385| Q&[W3]_F,F_Y QLS_Q,CLEAR PAGED,
|0053|1386| IF NOT CT [IZ] CALL [SET PAGED LATCH]
000,000,0,15,14,1,12,0,00,0,0,00,40,00,00,00,0,64,1,1,1,01,03,00,1261,00,7,00,0,0,0,0054|1387| Q&[W3]_F,F_Y QLS_Q,CLEAR RUN,
|0054|1388| IF NOT CT [IZ] CALL [SET RUN LATCH]
000,000,0,15,14,1,12,0,00,0,0,00,50,00,00,00,0,64,1,1,1,01,03,00,1256,00,7,00,0,0,0,0055|1389| Q&[W3]_F,F_Y QLS_Q,CLEAR TOPS20,
|0055|1390| IF NOT CT [IZ] CALL [SET TOPS20 LATCH]
000,000,0,15,14,1,12,0,00,0,0,00,60,00,00,00,0,64,1,1,1,01,03,00,1260,00,7,00,0,0,0,0056|1391| Q&[W3]_F,F_Y QLS_Q,CLEAR PXCT,
|0056|1392| IF NOT CT [IZ] CALL [SET PXCT LATCH]
000,000,0,15,14,1,12,0,00,0,0,00,70,00,00,00,0,64,1,1,1,01,03,00,1257,00,7,00,0,0,0,0057|1393| Q&[W3]_F,F_Y QLS_Q,CLEAR TRAP,
|0057|1394| IF NOT CT [IZ] CALL [SET TRAP LATCH]
|0057|1395|
|0057|1396|;Here to read LOCAL, USER, PAGED, RUN, TOPS20, PXCT, & TRAP latches into W1
000,000,0,04,10,1,00,0,00,0,0,00,00,00,00,00,0,20,1,1,1,01,34,00,1263,00,7,00,0,0,0,0058|1397| ZERO_[W1],IF [LOCAL] CALL [W1+1_W1]
000,000,1,11,06,1,02,0,00,0,0,00,00,11,00,00,0,20,1,1,1,01,36,00,1263,00,7,00,0,0,0,0059|1398| #2*[W1]_[W1],IF [USER] CALL [W1+1_W1]
000,000,1,11,06,1,02,0,00,0,0,00,00,11,00,00,0,20,1,1,1,01,40,00,1263,00,7,00,0,0,0,0060|1399| #2*[W1]_[W1],IF [PAGED] CALL [W1+1_W1]
000,000,1,11,06,1,02,0,00,0,0,00,00,11,00,00,0,20,1,1,1,01,42,00,1263,00,7,00,0,0,0,0061|1400| #2*[W1]_[W1],IF [RUN] CALL [W1+1_W1]
000,000,1,11,06,1,02,0,00,0,0,00,00,11,00,00,0,20,1,1,1,01,44,00,1263,00,7,00,0,0,0,0062|1401| #2*[W1]_[W1],IF [TOPS20] CALL [W1+1_W1]
000,000,1,11,06,1,02,0,00,0,0,00,00,11,00,00,0,20,1,1,1,01,46,00,1263,00,7,00,0,0,0,0063|1402| #2*[W1]_[W1],IF [PXCT] CALL [W1+1_W1]
000,000,1,11,06,1,02,0,00,0,0,00,00,11,00,00,0,20,1,1,1,01,66,00,1263,00,7,00,0,0,0,0064|1403| #2*[W1]_[W1],IF [TRAP] CALL [W1+1_W1]
|0064|1404|
|0064|1405| CALL [TVR XY] ;Be sure W1 and W2 are same
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,1267,00,7,00,0,0,0,0065|1406|
000,000,0,04,03,0,77,0,04,0,0,00,00,00,00,00,0,76,1,1,1,03,03,00,0062,00,7,00,0,0,0,0066|1407| [K -1]+[W2]_B, ;Next combination of latches
|0066|1408| IF NOT CT [IN] THEN [TLTCH2]
|0066|1409|
|0066|1410|;Verify the PI status register may be read and written
|0066|1411| LIGHTS [4]
000,000,0,04,10,1,00,0,04,0,0,00,00,00,46,00,0,20,1,1,0,16,00,00,0007,00,7,01,0,0,0,0068|1412| J[7]_[W2],Y_2914 STATUS ;1st value for reg
|0068|1413| J[7]_[W3] ;Mask for value
000,000,0,04,10,0,00,0,00,0,0,00,00,00,32,00,0,20,1,1,0,16,00,00,0000,00,7,00,0,0,0,0070|1414|TP12: #2914 STATUS_Y,Y_[W1] ;Get value back from reg
000,000,0,04,14,0,12,0,00,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,1267,00,7,00,0,0,0,0071|1415| [W3]&[W1]_B,
|0071|1416| CALL [TVR XY] ; Be sure we got correct value
000,000,0,04,03,0,77,0,04,0,0,00,00,00,46,00,0,76,1,1,1,03,03,00,0106,00,7,00,0,0,0,0072|1417| [K -1]+[W2]_B,Y_2914 STATUS,
|0072|1418| IF NOT CT [IN] THEN [TP12]
|0072|1419|
|0072|1420|;Verify the PI mask register may be read & written
|0072|1421|.IF/FTLDIAG
|0072|1422| LIGHTS [5]
000,000,0,04,10,1,00,0,04,0,0,00,00,00,72,00,0,20,1,1,0,16,00,00,0377,00,7,01,0,0,0,0074|1423| J[0377]_[W2], ;1st value for mask
|0074|1424| Y_2914 MASK
|0074|1425| J[0377]_[W3] ;Mask for mask register
000,000,0,04,10,0,00,0,00,0,0,00,00,00,36,00,0,20,1,1,0,16,00,00,0000,00,7,00,0,0,0,0076|1426|TP13: Y_[W1],#2914 MASK_Y ;Get value back from mask
000,000,0,04,14,0,12,0,00,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,1267,00,7,00,0,0,0,0077|1427| [W3]&[W1]_B, ;Mask off extra bits
|0077|1428| CALL [TVR XY] ;Be sure we got correct value
000,000,0,04,03,0,77,0,04,0,0,00,00,00,72,00,0,76,1,1,1,03,03,00,0114,00,7,00,0,0,0,0078|1429| [K -1]+[W2]_B,
|0078|1430| Y_2914 MASK,
|0078|1431| IF NOT CT [IN] THEN [TP13]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,36,00,0,76,1,1,0,03,03,00,0106,00,7,00,0,0,0,0079|1432| #2914 MASK_Y, ;Next value for register
|0079|1433| IF NOT CT [IN] THEN [TP12]
|0079|1434|.ENDIF/FTLDIAG
|0079|1435|
|0079|1436|;Verify the PI mask register blocks interrupts
|0079|1437| LIGHTS [6]
000,000,0,04,10,1,00,0,60,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0006,00,7,01,0,0,0,0080|1438| J[0377]_[W2] ;1st value for mask
000,000,0,04,10,1,00,0,24,0,0,00,00,00,02,00,0,20,1,1,0,16,00,00,7777,00,7,01,0,0,0,0082|1439|TP14: J[07777]_[W6], ;Stall counter
|0082|1440| INT OP/MASTER CLEAR
000,000,0,14,06,1,06,0,00,0,0,00,00,00,72,00,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,0083|1441| [W2]_Y,Y_2914 MASK ;Inhibit some interrupts
|0083|1442| J[0377]_[W1] ;Chnls where ints did not happen
000,000,0,01,06,1,02,0,10,0,0,00,00,01,00,00,0,20,1,1,1,16,00,00,0000,00,7,10,0,0,0,0085|1443| LRS [W1]_[W3],ALU_PROC REG ;Start ints on all chnls
000,000,0,04,10,1,00,0,14,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0007,00,7,01,0,0,0,0086|1444|TP17: J[7]_[W4] ;Mask for 2914 status
000,000,0,06,06,1,16,0,00,0,0,00,00,00,00,00,0,20,1,1,0,03,20,00,0141,00,7,00,0,0,0,0087|1445| [W4]_Q,
|0087|1446| IF [NO PI REQ] THEN [TP19]
000,000,0,14,06,1,16,0,00,0,1,00,00,00,00,00,0,20,1,1,1,16,00,00,0000,00,7,01,0,0,0,0088|1447| [W4]+1_Y,ALU_CTR ;Load ctr with 010
000,000,0,14,10,0,00,0,00,0,0,00,00,00,26,00,0,20,1,1,0,03,75,00,0134,00,7,00,0,0,0,0089|1448| IF [TIMER FLAG] THEN [TP171],
|0089|1449| GRANT INTERRUPT ; Grant interrupt
000,000,0,04,10,0,00,0,14,0,0,00,00,00,32,00,0,20,1,1,0,16,00,00,0000,00,7,00,0,0,0,0090|1450| #2914 STATUS_Y,Y_[W4]
000,000,0,14,14,1,16,0,00,0,0,00,00,00,00,00,0,20,1,1,1,16,00,00,0000,00,7,01,0,0,0,0091|1451| Q&[W4]_Y,ALU_CTR ;Get interrupting level+1
000,000,0,01,10,1,00,0,14,0,0,00,00,05,00,00,0,20,1,1,1,03,01,00,0136,00,7,00,0,0,0,0092|1452|TP171: BIT0_[W4], ;Bit for interrupt
|0092|1453| GOTO [TP173]
000,000,1,11,06,1,16,0,14,0,0,00,00,51,00,00,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,0093|1454|TP172: ROL [W4]_[W4]
000,000,0,14,10,1,00,0,00,0,0,00,00,00,46,00,0,20,1,1,1,11,00,00,0135,00,7,00,0,0,0,0094|1455|TP173: ZERO_Y,Y_2914 STATUS, ;Allow next interrupt
|0094|1456| LOOP [TP172]
|0094|1457| [W4]BAR&[W1]_B ;Flag we got int
000,000,0,04,11,0,16,0,10,0,0,00,00,00,00,00,0,20,1,1,1,16,00,00,0000,00,7,10,0,0,0,0096|1458| [W4]BAR&[W3]_B,ALU_PROC REG ;Stop trying to make that kind
000,000,0,04,03,0,77,0,24,0,0,00,00,00,00,00,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,0097|1459|TP19: [K -1]+[W6]_B
|0097|1460| IF NOT CT [IN] THEN [TP17]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,76,1,1,0,03,03,00,0126,00,7,00,0,0,0,0098|1461| CALL [TVR XY] ;See if right ints were inhibited
000,000,0,04,03,0,77,0,04,0,0,00,00,00,00,00,0,76,1,1,1,03,03,00,0122,00,7,00,0,0,0,0100|1462| [K -1]+[W2]_B,
|0100|1463| IF NOT CT [IN] THEN [TP14]
|0100|1464|
|0100|1465|;Save CTY registers
|0100|1466| J[LNOMDW]_RAMFILE ADR
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,03,0,20,1,1,0,16,00,00,0201,00,7,01,0,0,0,0101|1467| RAMFILE_[PC] ;Save mode register here
000,000,0,04,10,0,00,0,34,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0000,00,7,04,0,0,0,0102|1468|
|0102|1469|;Ramfile test 1, float a bit through each word in Ramfile
|0102|1470|
000,000,0,04,10,1,00,0,60,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0007,00,7,01,0,0,0,0103|1471|TVR 00: LIGHTS [7.] ;First ramfile test
|0103|1472| CALL [TVR X0] ;Point to highest ramfile adr
000,000,0,04,10,1,00,0,04,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0001,00,7,01,0,0,0,0105|1473|TVR 1: J[1]_[W2] ;Bit to float
000,000,0,14,14,0,77,0,04,0,0,00,00,00,00,00,0,20,1,0,1,01,01,00,1266,00,7,04,0,0,0,0106|1474|TVR 2: [W2]_RAMFILE,IX_MX, ;Write next pattern in ramfile
|0106|1475| CALL [TVR XX] ; Check we could write bit
000,000,1,11,06,1,06,0,04,0,0,00,00,11,00,00,0,44,1,1,1,03,03,00,0152,00,7,00,0,0,0,0107|1476| #2*[W2]_[W2], ;Write next word in ramfile
|0107|1477| IF NOT CT [MZ] THEN [TVR 2]
000,000,0,14,14,1,77,0,00,0,0,00,00,00,00,00,0,20,1,1,1,16,00,00,0000,00,7,04,0,0,0,0108|1478| Q_Y,ALU_RAMFILE ;Write words address in word
000,000,0,06,03,1,77,0,00,0,0,00,00,00,00,03,0,76,1,1,1,03,03,00,0151,00,7,00,0,0,0,0109|1479| Q+[K -1]_F,F_Q_Y,Y_RAMFILE ADR, ;Next ramfile location
|0109|1480| IF NOT CT [IN] THEN [TVR 1]
|0109|1481|
|0109|1482|;Ramfile test 2, verify each word has its address written in it
|0109|1483| LIGHTS [8.] ;Second ramfile test
000,000,0,04,10,1,00,0,60,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0010,00,7,01,0,0,0,0110|1484| CALL [TVR X0] ;Initialize ramfile adr
000,000,0,04,14,1,77,0,04,0,0,00,00,00,00,03,0,20,1,1,1,01,01,00,1266,00,7,00,0,0,0,0112|1485|TVR 3: Q_[W2],Y_RAMFILE ADR, ;Address should equal data
|0112|1486| CALL [TVR XX]
000,000,0,06,03,1,77,0,00,0,0,00,00,00,00,03,0,76,1,1,1,03,03,00,0160,00,7,00,0,0,0,0113|1487| Q+[K -1]_F,F_Q_Y,Y_RAMFILE ADR, ;Next ramfile word
|0113|1488| IF NOT CT [IN] THEN [TVR 3]
|0113|1489|
|0113|1490|;Ramfile test 3, address ramfile with special selects
|0113|1491| LIGHTS [9.] ;Third ramfile test
000,000,0,04,10,1,00,0,04,0,0,00,24,00,00,00,0,20,1,1,0,16,00,00,1477,00,7,01,0,0,0,0115|1492| J[01477]_[W2],SET USER ;Expected page table contents
|0115|1493| J[0000]_[W3] ; Illegal section, sect.NE.0,
000,000,0,04,10,1,00,0,10,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0000,00,7,01,0,0,0,0116|1494| ; not AC ref, no context match
000,000,0,14,00,1,00,0,00,0,0,00,00,00,00,77,0,20,1,1,1,01,01,00,1247,00,7,00,0,0,0,0117|1495| ONES_F,F_Y,
|0117|1496| SPEC SEL/PAGE TABLE ENTRY,
|0117|1497| CALL [RDPG LATCHES]
000,000,0,04,10,1,00,0,04,0,0,00,20,00,00,00,0,20,1,1,0,16,00,00,1000,00,7,01,0,0,0,0118|1498| J[01000]_[W2],SET EXEC ;Correct page table contents
|0118|1499| J[00016]_[W3] ; Legal section, sect.EQ.0
000,000,0,04,10,1,00,0,10,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0016,00,7,01,0,0,0,0119|1500| ; AC ref, no context match
000,000,0,14,10,1,00,0,00,0,0,00,00,00,00,77,0,20,1,1,1,01,01,00,1247,00,7,10,0,0,0,0120|1501| ZERO_Y,ALU_PROC REG, ;Register block 0
|0120|1502| SPEC SEL/PAGE TABLE ENTRY,
|0120|1503| CALL [RDPG LATCHES]
|0120|1504| J[0701]_[W1] ;Will be AC16, XR=1
000,000,0,04,10,1,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0701,00,7,01,0,0,0,0121|1505| SWAP [W1]_[W1]
000,000,0,04,10,0,02,2,00,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0000,00,7,07,0,0,0,0122|1506| J[0601]_[W1]
000,000,0,14,06,1,02,0,00,0,0,00,00,00,00,33,0,20,1,1,1,01,01,00,1266,00,7,11,0,0,0,0124|1507| [W1]_Y,LOAD IR,SPEC SEL/XR, ;Load IR
|0124|1508| CALL [TVR XX]
|0124|1509| J[0600]_[W2] ;What should be in AC0 block 0
000,000,0,14,10,1,00,0,00,0,0,00,00,00,00,23,0,20,1,1,1,01,01,00,1266,00,7,00,0,0,0,0126|1510| ZERO_Y,SPEC SEL/VMA, ;Address AC0
|0126|1511| CALL [TVR XX]
|0126|1512| SEL AC+[2] ;Select AC2 block 0
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,27,0,20,1,1,0,16,00,02,0000,00,7,00,0,0,0,0127|1513| CALL [TVR XX]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,1266,00,7,00,0,0,0,0128|1514| J[0616]_[W2]
000,000,0,04,10,1,00,0,04,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0616,00,7,01,0,0,0,0129|1515| SEL AC+[0]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,27,0,20,1,1,0,16,00,00,0000,00,7,00,0,0,0,0130|1516| CALL [TVR XX]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,1266,00,7,00,0,0,0,0131|1517|
|0131|1518|;Zero entire Ramfile
|0131|1519| CALL [TVR X0] ;Set first adr for ramfile
000,000,0,14,10,1,00,0,00,0,0,00,00,00,00,00,0,20,1,1,1,16,00,00,0000,00,7,04,0,0,0,0133|1520|IRF 2: ZERO_Y,ALU_RAMFILE
000,000,0,06,03,1,77,0,00,0,0,00,00,00,00,03,0,76,1,1,1,03,03,00,0205,00,7,00,0,0,0,0134|1521| Q+[K -1]_F,F_Q_Y,Y_RAMFILE ADR,
|0134|1522| IF NOT CT [IN] THEN [IRF 2]
|0134|1523|
|0134|1524|;Check PCIs are OK
|0134|1525| J[LNOSW]_[W6] ;First line block adr
000,000,0,04,10,1,00,0,24,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0200,00,7,01,0,0,0,0135|1526|
|0135|1527|;Verify we can read/write CR register
000,000,0,04,10,1,00,0,60,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0012,00,7,01,0,0,0,0136|1528|TPC10: LIGHTS [10.]
|0136|1529| [W6]_[PXCT LH]
000,000,0,04,06,1,26,0,61,0,0,00,00,00,00,00,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,0137|1530| J[0357]_[W4] ;Mask for compare
000,000,0,04,10,1,00,0,14,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0357,00,7,01,0,0,0,0138|1531| J[0377]_[W3] ; Initial value
000,000,0,04,10,1,00,0,10,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0377,00,7,01,0,0,0,0139|1532|
000,000,0,04,10,1,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0030,00,7,01,0,0,0,0140|1533|TPC 11: J[A1!A0]_[W1] ;To address CR register
000,000,0,04,06,1,12,0,04,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,3715,00,7,00,0,0,0,0141|1534| [W3]_[W2],CALL [WR PCI] ;Write CR register
|0141|1535| CALL [RD PCI CR] ;Get CR now
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,3711,00,7,00,0,0,0,0142|1536| [W4]&[W2]_B ;Leave only good data
000,000,0,04,14,0,16,0,00,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,1267,00,7,00,0,0,0,0144|1537| [W4]&[W1]_B, ;Leave only read data
|0144|1538| CALL [TVR XY] ; Compare good with bad
000,000,0,04,03,0,77,0,10,0,0,00,00,00,00,00,0,76,1,1,1,03,03,00,0214,00,7,00,0,0,0,0145|1539| [K -1]+[W3]_B, ;Next value for CR
|0145|1540| IF NOT CT [IN] THEN [TPC 11]
|0145|1541|
|0145|1542|;Verify we can read/write MRI/2
|0145|1543| J[021]_[PXCT RH]
000,000,0,04,10,1,00,0,62,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0021,00,7,01,0,0,0,0146|1544|
000,000,0,14,06,1,26,0,00,0,1,00,00,00,00,03,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,0147|1545| [W6]+1_Y,Y_RAMFILE ADR ;Address mode word in ramfile
|0147|1546|.IF/FTLDIAG
|0147|1547| J[06000]_[W1] ;Will become 30000
000,000,1,11,03,0,02,0,00,0,0,00,00,11,00,00,0,20,1,1,0,16,00,00,7777,00,7,01,0,0,0,0149|1548| J[07777]_Y24-Y35,[W1]+[W1]_F, ;Leave 37777 in W1
|0149|1549| F_LSZ Y_[W1]
|0149|1550| SWAP [W1]_[W2] ;Put 37777,,0 in W2
000,000,0,04,10,0,02,2,04,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0000,00,7,07,0,0,0,0150|1551|.ENDIF/FTLDIAG
|0150|1552|.IFNOT/FTLDIAG
|0150|1553| J[4000]_[W1] ;Will become 020000
|0150|1554| #4*[W1]_B ;Makes 020000
|0150|1555| SWAP [W1]_[W2] ;Make 020000,,0
|0150|1556|.ENDIF/FTLDIAG
000,000,0,14,14,0,77,0,04,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,3500,00,7,04,0,0,0,0151|1557|TPC12: [W2]_RAMFILE,
|0151|1558| CALL [SET PCI MODE]
|0151|1559| J[A1]_[W1] ;For PCI adr to read MR1/2
000,000,0,04,10,1,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0020,00,7,01,0,0,0,0152|1560| CALL [RD PCI] ;Get MR1
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,3712,00,7,00,0,0,0,0153|1561| J[0377]_[W3] ;Mask for extra bits
000,000,0,04,10,1,00,0,10,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0377,00,7,01,0,0,0,0154|1562| [W3]&[W1]_Q ;Leave only MR1 in Q
000,000,0,04,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,14,00,00,0003,00,7,03,0,0,0,0156|1563| PCI_ALU,Y_[W1],J[3]_CTR ;Read MR2
|0156|1564| J[077]_[W2] ;Mask for MR25-MR20
000,000,0,04,10,1,00,0,04,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0077,00,7,01,0,0,0,0157|1565| [W2]&[W1]_B
000,000,1,11,03,0,02,0,00,0,0,00,00,11,00,00,0,20,1,1,1,11,00,00,0237,00,7,00,0,0,0,0159|1566|TPC14: #4*[W1]_B,LOOP [TPC14]
|0159|1567| Q+[W1]_[W1] ;Combine W1 and W2
000,000,0,14,06,1,26,0,00,0,1,00,00,00,00,03,0,20,1,1,1,01,01,00,4026,00,7,00,0,0,0,0161|1568| [W6]+1_Y,Y_RAMFILE ADR, ;Address ramfile mode word
|0161|1569| CALL [SWAP W1_W1] ;Position like ramfile
000,000,0,04,10,0,00,0,04,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,1267,00,7,04,0,0,0,0162|1570| RAMFILE_[W2],CALL [TVR XY] ;Get correct answer
|0162|1571|.IF/FTLDIAG
000,000,0,04,01,0,57,0,04,0,1,00,00,00,00,00,0,76,1,1,1,03,03,00,0227,00,7,00,0,0,0,0163|1572| [W2]-[BIT17]_A, ;On to next combination
|0163|1573| IF NOT CT [IN] THEN [TPC12]
|0163|1574|.ENDIF/FTLDIAG
|0163|1575|.IFNOT/FTLDIAG
|0163|1576| ROR [W2]_[W2 LH], ;On to next bit
|0163|1577| IF NOT CT [IZ] THEN [TPC12]
|0163|1578|.ENDIF/FTLDIAG
|0163|1579|
|0163|1580|;Now ready for Next line
|0163|1581| J[010]_[W1] ;Bit to test
000,000,0,04,03,0,57,0,24,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,4026,00,7,00,0,0,0,0165|1582| [BIT17]+[W6]_B, ;Next line number in LH
|0165|1583| CALL [SWAP W1_W1] ;Position to test line number
000,000,0,14,14,0,02,0,24,0,0,00,00,00,00,00,0,64,1,1,1,03,02,00,0210,00,7,00,0,0,0,0166|1584| [W1]&[W6]_Y, ;See if we are done
|0166|1585| IF CT [IZ] THEN [TPC10]
|0166|1586|
|0166|1587|;Restore CTY Ramfile registers
|0166|1588| J[LNOMDW]_RAMFILE ADR
000,000,0,14,14,0,77,0,34,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,0764,00,7,04,0,0,0,0168|1589| [PC]_RAMFILE,
|0168|1590| CALL [CMD&CMR FLUSH] ;Flush CMD and CMR buffers
|0168|1591|
|0168|1592|;Checksum DISPATCH RAM
|0168|1593| LIGHTS [11.] ;Check DISPATCH ROM
000,000,0,07,10,1,00,0,00,0,0,00,00,00,00,00,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,0170|1594| ZERO_F,F_Q_[W1] ;Initialize checksum
|0170|1595| J[0777]_[W2] ;First IR
000,000,0,04,10,0,06,2,10,0,0,00,00,00,00,00,0,20,1,1,0,14,00,00,0003,00,7,07,0,0,0,0172|1596|TDP1: SWAP [W2]_[W3],J[3]_CTR
000,000,1,11,03,0,12,0,10,0,0,00,00,11,00,00,0,20,1,1,1,11,00,00,0255,00,7,00,0,0,0,0173|1597|TDP2: #4*[W3]_B,LOOP [TDP2]
000,000,1,11,06,1,12,0,10,0,0,00,00,11,00,00,0,20,1,1,1,16,00,00,0000,00,7,11,0,0,0,0174|1598| #2*[W3]_[W3],LOAD IR
000,000,0,07,03,1,02,0,00,0,0,00,00,00,00,00,0,20,1,1,0,06,00,00,0000,10,7,01,0,0,0,0175|1599| DISP [010]_Y,Q+[W1]_F,F_Q Y_[W1]
000,000,0,07,03,1,02,0,00,0,0,00,00,00,00,00,0,20,1,1,0,06,00,00,0000,11,7,01,0,0,0,0176|1600| DISP [011]_Y,Q+[W1]_F,F_Q Y_[W1]
000,000,0,07,03,1,02,0,00,0,0,00,00,00,00,00,0,20,1,1,0,06,00,00,0000,12,7,01,0,0,0,0177|1601| DISP [012]_Y,Q+[W1]_F,F_Q Y_[W1]
000,000,0,07,03,1,02,0,00,0,0,00,00,00,00,00,0,20,1,1,0,06,00,00,0000,13,7,01,0,0,0,0178|1602| DISP [013]_Y,Q+[W1]_F,F_Q Y_[W1]
000,000,0,07,03,1,02,0,00,0,0,00,00,00,00,00,0,20,1,1,0,06,00,00,0000,14,7,01,0,0,0,0179|1603| DISP [014]_Y,Q+[W1]_F,F_Q Y_[W1]
000,000,0,07,03,1,02,0,00,0,0,00,00,00,00,00,0,20,1,1,0,06,00,00,0000,15,7,01,0,0,0,0180|1604| DISP [015]_Y,Q+[W1]_F,F_Q Y_[W1]
000,000,0,07,03,1,02,0,00,0,0,00,00,00,00,00,0,20,1,1,0,06,00,00,0000,16,7,01,0,0,0,0181|1605| DISP [016]_Y,Q+[W1]_F,F_Q Y_[W1]
000,000,0,07,03,1,02,0,00,0,0,00,00,00,00,00,0,20,1,1,0,06,00,00,0000,17,7,01,0,0,0,0182|1606| DISP [017]_Y,Q+[W1]_F,F_Q Y_[W1]
000,000,0,04,03,0,77,0,04,0,0,00,00,00,00,00,0,76,1,1,1,03,03,00,0254,00,7,00,0,0,0,0183|1607| [K -1]+[W2]_B, ;Next value for IR
|0183|1608| IF NOT CT [IN] THEN [TDP1]
|0183|1609| Q+[W1]_[W1] ;Make final checksum
000,000,0,04,03,1,02,0,00,0,0,00,00,00,00,00,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,0184|1610| J[07777]_[W3] ;Mask for checksum
000,000,0,04,10,1,00,0,10,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,7777,00,7,01,0,0,0,0185|1611| J[0105]_[W2] ;Known checksum
000,000,0,04,14,0,12,0,00,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,1267,00,7,00,0,0,0,0187|1612| [W3]&[W1]_B, ;Mask result to 12 bits
|0187|1613| CALL [TVR XY] ; Compare two values
|0187|1614|
|0187|1615|;Check memory is OK
|0187|1616| ;GOTO [SYS INIT] ;Initialize everything
|0187|1617|.ENDIF/FTDIAG
|0187|1618|.IFNOT/FTDIAG
|0187|1619| J[LNOMDW]_RAMFILE ADR ;Address tty mode word
|0187|1620| J[02000]_[W1]
|0187|1621| RAMFILE_[W6] ;Save it
|0187|1622| ZERO_[W2],Y_RAMFILE ADR
|0187|1623|IR2: ZERO_Y,ALU_RAMFILE,
|0187|1624| CALL [W2+1_RFA]
|0187|1625| [K -1]+[W1]_B,
|0187|1626| IF NOT CT [IZ] THEN [IR2]
|0187|1627| J[LNOMDW]_RAMFILE ADR ;Address Cty mode word
|0187|1628| [W6]_Y,ALU_RAMFILE,
|0187|1629| CALL [CMD&CMR FLUSH] ;Flush CMD and CMR buffers
|0187|1630|.ENDIF/FTDIAG
|0187|1631|
|0187|1632|;Here after TEST has run, to initialize machine for running
000,000,0,04,10,1,00,0,64,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0077,00,7,01,0,0,0,0188|1633|SYS INIT:
|0188|1634|
|0188|1635|;Setup 2903 registers
|0188|1636| J[0077]_[K 77] ;Initialize register
000,000,0,04,10,1,00,0,70,0,0,00,40,00,00,00,0,20,1,1,0,16,00,00,0777,00,7,01,0,0,0,0189|1637| J[0777]_[K 777], ;Initialize register
|0189|1638| CLEAR RUN
|0189|1639| J[027]_[TIME] ;Initialize register
000,000,0,04,10,1,00,0,37,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0027,00,7,01,0,0,0,0190|1640| ZERO_[K -1.0 RH] ;Clear RH of register
000,000,0,04,10,1,00,0,76,0,0,00,00,00,00,00,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,0191|1641| J[3]_[C0!C1]
000,000,0,04,00,1,00,0,75,0,0,00,00,00,00,00,0,20,1,1,1,04,01,00,0002,00,7,00,0,0,0,0193|1642| ONES_[K -1.0 LH],PUSH J[2]_CTR ;Set LH of register
000,000,0,01,06,1,63,0,63,0,0,00,00,51,00,00,0,20,1,1,1,10,00,00,0000,00,7,00,0,0,0,0194|1643| ROR [C0!C1]_[C0!C1],RFCT ;Load 300000,,0
|0194|1644| J[1]_[W1]
000,000,0,04,10,1,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0001,00,7,01,0,0,0,0195|1645| SWAP [W1]_[BIT17] ;Makes 1,,0
000,000,0,01,06,1,57,0,00,0,0,00,00,51,00,00,0,20,1,1,0,16,00,00,7777,00,7,01,0,0,0,0197|1646| J[07777]_Y24-Y35,[BIT17]_F, ;Makes 0,,4077777
|0197|1647| F_ROR Y_[W1]
|0197|1648| SWAP [W1]_[K 407777.0] ;Initialize register
000,000,0,04,10,0,02,2,73,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0000,00,7,07,0,0,0,0198|1649| J[0040]_[W1]
000,000,0,04,10,1,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0040,00,7,01,0,0,0,0199|1650| SWAP [W1]_[BIT12]
000,000,0,04,10,0,02,2,53,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0000,00,7,07,0,0,0,0200|1651|
|0200|1652|;Setup RAMFILE byte masks
|0200|1653| J[BYTE MASK]_[W1] ;First adr in byte mask area
000,000,0,06,03,0,02,0,77,0,0,00,00,00,00,00,0,20,1,1,0,14,00,00,0077,00,7,00,0,0,0,0202|1654| [W1]+[K -1]_Q, ;First adr in Ramfi1e to set
|0202|1655| J[0077]_CTR ;Number of masks to write
|0202|1656| ZERO_[W1] ;First word is all zeros
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,1246,00,7,00,0,0,0,0204|1657|IRF 10: CALL [RF WRITE]
000,000,1,11,06,1,02,0,00,0,0,00,00,15,00,00,0,20,1,1,1,11,00,00,0314,00,7,00,0,0,0,0205|1658| [W1]_F,LLS F_B,#1_SIO0 #1_QIO0, ;Shift left shifting in ones
|0205|1659| B SEL/W1,LOOP [IRF 10]
|0205|1660|
|0205|1661|
|0205|1662|;Setup RAMFILE bit table
|0205|1663| BIT0_[W1] ;First bit
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,1246,00,7,00,0,0,0,0207|1664|IRF 12: CALL [RF WRITE]
000,000,0,01,06,1,02,0,00,0,0,00,00,01,00,00,0,64,1,1,1,03,03,00,0317,00,7,00,0,0,0,0208|1665| LRS [W1]_[W1],
|0208|1666| IF NOT CT [IZ] THEN [IRF 12]
|0208|1667|
|0208|1668|;Setup other Ramfi1e locations
|0208|1669| J[PUSHJ FLAGS]_RAMFILE ADR
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,03,0,20,1,1,0,16,00,00,0145,00,7,01,0,0,0,0209|1670| J[04340]_[W1] ;Want 021600,,0
000,000,0,04,10,1,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,4340,00,7,01,0,0,0,0210|1671| SWAP [W1]_[W1]
000,000,1,11,03,0,02,0,00,0,0,00,00,11,00,00,0,20,1,1,1,14,00,00,0005,00,7,04,0,0,0,0212|1672| #4*[W1]_B,ALU_RAMFILE,
|0212|1673| J[5]_CTR
|0212|1674|
|0212|1675|;Setup M8628 status register
|0212|1676| J[BIT20]_RAMFILE ADR ;Want 100000
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,03,0,20,1,1,0,16,00,00,0124,00,7,01,0,0,0,0213|1677| J[7]_[W5] ;Highest possible memory
000,000,0,04,10,0,00,0,14,0,0,00,00,00,00,00,0,20,1,1,0,14,00,00,0001,00,7,04,0,0,0,0215|1678| RAMFILE_[W4],J[1]_CTR
|0215|1679| J[06540]_[W1] ;Clear error flags
000,000,1,11,03,0,02,0,00,0,0,00,00,11,00,00,0,20,1,1,1,11,00,00,0331,00,7,00,0,0,0,0217|1680|IM 12: #4*[W1]_B,LOOP [IM 12]
000,000,0,06,03,0,16,0,20,0,0,00,00,05,00,00,0,20,1,1,1,16,00,00,0000,00,4,02,0,0,0,0218|1681|IM 20: [W4]+[W5]_F,F_Q_Y, ;Address memory status reg
|0218|1682| START IO WRITE
000,000,0,04,06,1,02,0,00,0,0,00,00,05,00,00,0,20,1,0,1,16,00,00,0000,00,5,02,0,0,0,0219|1683| [W1]_[W1],ALU_IO ;Write status register
000,000,0,04,03,0,77,0,20,0,0,00,00,00,00,00,0,76,1,1,1,03,03,00,0332,00,7,00,0,0,0,0220|1684| [K -1]+[W5]_B, ;Next memory
|0220|1685| IF NOT CT [IN] THEN [IM 20] ; Loop back for rest of memories
|0220|1686|
|0220|1687|;Setup another 2903 reg
|0220|1688| J[BIT4]_RAMFILE ADR
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,03,0,20,1,1,0,16,00,00,0104,00,7,01,0,0,0,0221|1689| RAMFILE_[BIT4]
000,000,0,04,10,0,00,0,47,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0000,00,7,04,0,0,0,0222|1690| J[#30B MASK]_RAMFILE ADR
000,000,0,04,10,0,00,0,67,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,1174,00,7,04,0,0,0,0224|1691| RAMFILE_[K 7777.-1],
|0224|1692| CALL [SYS RESET] ;Reset a bunch of things
|0224|1693|
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,0567,00,7,00,0,0,0,0225|1694|CONSOLE PROMPT:
|0225|1695| CALL [PUT CMR PROMPT] ;Type prompt
|0225|1696| ;GOTOP [CONSOLE]
|0225|1697|
|0225|1698|.TOC "Console Program"
|0225|1699|
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,13,42,00,0347,00,7,00,0,0,0,0226|1700|CONSOLE:
|0226|1701| IF [RUN] THENP [CSL2]
|0226|1702| CHECK INTERRUPTS
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,01,21,00,4154,00,7,00,0,0,0,0227|1703| J[INT RCOVR]_RAMFILE ADR ;Address recovery routine
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,03,0,20,1,1,0,16,00,00,0163,00,7,01,0,0,0,0228|1704| RAMFILE_[W1]
000,000,0,04,06,1,02,0,00,0,0,00,00,00,00,00,0,64,1,1,1,03,03,00,0000,00,7,01,0,0,0,0230|1705| [W1]_[W1],
|0230|1706| IF NOT CT [IZ] THEN Y
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,03,0,20,1,1,0,16,00,00,0341,00,7,01,0,0,0,0231|1707|CSL2:
|0231|1708|CMD PRSEX:
|0231|1709| J[CMDTKR]_RAMFILE ADR
|0231|1710|.IF/FTCRAM
|0231|1711| RAMFILE_[W1] ;Get break char flag
|0231|1712| [W1]_Y,
|0231|1713| IF CT [IZ] THEN [CSL3]
|0231|1714| J[CMRTKR]_RAMFILE ADR ;Address response putter
|0231|1715| RAMFILE_[W1] ;Get response taker
|0231|1716| [W1]_Y,
|0231|1717| IF CT [IZ] THEN [CMD PRSE]
|0231|1718|.ENDIF/FTCRAM
|0231|1719|.IFNOT/FTCRAM
000,000,0,04,10,0,00,0,00,0,0,00,00,00,00,00,0,64,1,1,0,03,02,00,0353,00,7,04,0,0,0,0232|1720| RAMFILE_[W1], ;Get break char flag
|0232|1721| IF CT [IZ] THEN [CSL3]
|0232|1722| J[CMRTKR]_RAMFILE ADR ;Address response putter
000,000,0,04,10,0,00,0,04,0,0,00,00,00,00,00,0,64,1,1,0,03,02,00,0372,00,7,04,0,0,0,0234|1723| RAMFILE_[W2], ;Get response taker
|0234|1724| IF CT [IZ] THEN [CMD PRSE]
|0234|1725|.ENDIF/FTCRAM
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,13,42,00,1420,00,7,00,0,0,0,0235|1726|CSL3: IF [RUN] THENP [IFETCH]
|0235|1727|.IF/SH_N_TL
|0235|1728| CALL [SHOW&TELL]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,0356,00,7,00,0,0,0,0236|1729|.ENDIF/SH_N_TL
|0236|1730| GOTOP [CONSOLE]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,13,01,00,0342,00,7,00,0,0,0,0237|1731|.IF/SH_N_TL
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,03,0,20,1,1,0,16,00,00,0563,00,7,01,0,0,0,0238|1732|SHOW&TELL:
|0238|1733| J[RF PROC REG]_RAMFILE ADR ;Address ramfile copy of
|0238|1734| RAMFILE_[W1] ; PROC REG
000,000,0,04,10,0,00,0,00,0,0,00,00,00,36,00,0,20,1,1,0,16,00,00,0000,00,7,00,0,0,0,0240|1735| #2914 MASK_Y,Y_[W1]
000,000,0,04,10,0,00,0,00,0,0,00,00,00,32,00,0,20,1,1,0,16,00,00,0000,00,7,00,0,0,0,0241|1736| #2914 STATUS_Y,Y_[W1]
|0241|1737| J[LNOSW]_[W6]
000,000,0,04,10,1,00,0,24,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0200,00,7,01,0,0,0,0242|1738| CALL [RD PCI CR]
000,000,0,04,06,1,02,0,00,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,3707,00,7,00,0,0,0,0244|1739| [W1]_[W1],
|0244|1740| CALL [RD PCI SR]
|0244|1741| [W1]_[W1] ;Display SR
000,000,0,04,06,1,02,0,00,0,0,00,00,00,00,00,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,0245|1742| J[A1]_[W1] ;For PCI adr to read MR1/2
000,000,0,04,10,1,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0020,00,7,01,0,0,0,0246|1743| CALL [RD PCI] ;Get MR1
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,3712,00,7,00,0,0,0,0247|1744| [W1]_[W1] ;Display MR1
000,000,0,04,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,12,01,00,0000,00,7,03,0,0,0,0249|1745| PCI_ALU,Y_[W1], ;Read MR2
|0249|1746| RETURN
|0249|1747|.ENDIF/SH_N_TL
|0249|1748|
|0249|1749|;Here to decode next console command
000,000,0,04,10,1,00,0,20,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,0514,00,7,00,0,0,0,0250|1750|CMD PRSE:
|0250|1751| ZERO_[W5], ;Build command in W5
|0250|1752| CALL [GET CMD CHX] ;Get 1st nonblank char from command
|0250|1753| J[015]_[W2] ;Ascii "<cr>"
000,000,0,14,02,0,02,0,04,0,0,00,00,00,00,00,0,64,1,1,1,03,02,00,0505,00,7,00,0,0,0,0252|1754| [W1]-[W2]_Y, ;If end of line done
|0252|1755| IF CT [IZ] THEN [CMD DONE]
|0252|1756| J[054]_[W2] ;Ascii "."
000,000,0,14,02,0,02,0,04,0,0,00,00,00,00,00,0,64,1,1,1,03,02,00,0511,00,7,00,0,0,0,0254|1757| [W1]-[W2]_Y ,
|0254|1758| IF CT [IZ] THEN [CMD PRSE8] ;Skip command separator
|0254|1759| GOTO [CMDP5]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,03,01,00,0411,00,7,00,0,0,0,0255|1760|
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,1004,00,7,00,0,0,0,0256|1761|CMDP2: CALL [GET CMD CHR] ;Get next command char
|0256|1762| J[040]_[W2] ;Ascii " "
000,000,0,14,02,0,06,0,00,0,0,00,00,00,00,00,0,64,1,1,1,03,02,00,0420,00,7,00,0,0,0,0258|1763| [W2]-[W1]_Y, ;Compare
|0258|1764| IF CT [IZ] THEN [CMDDSP]
|0258|1765| J[015]_[W2] ;Ascii "<cr>"
000,000,0,14,02,0,06,0,00,0,0,00,00,00,00,00,0,64,1,1,1,03,02,00,0420,00,7,00,0,0,0,0260|1766| [W2]-[W1]_Y, ;Compare
|0260|1767| IF CT [IZ] THEN [CMDDSP]
|0260|1768| J[054]_[W2] ;Ascii ","
000,000,0,14,02,0,06,0,00,0,0,00,00,00,00,00,0,64,1,1,1,03,02,00,0420,00,7,00,0,0,0,0262|1769| [W2]-[W1]_Y, ;Compare
|0262|1770| IF CT [IZ] THEN [CMDDSP]
000,000,1,11,06,1,22,0,20,0,0,00,00,11,00,00,0,20,1,1,1,14,00,00,0002,00,7,00,0,0,0,0263|1771| #2*[W5]_[W5],
|0263|1772| J[2]_CTR
000,000,1,11,03,0,22,0,20,0,0,00,00,11,00,00,0,20,1,1,1,11,00,00,0410,00,7,00,0,0,0,0264|1773|CMDP3: #4*[W5]_B,
|0264|1774| LOOP [CMDP3]
000,000,0,04,10,1,00,0,04,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0140,00,7,01,0,0,0,0265|1775|CMDP5: J[0140]_[W2] ;141 - 1ower case "a"
000,000,0,14,02,0,02,0,04,0,0,00,00,00,00,00,0,76,1,1,1,03,02,00,0417,00,7,00,0,0,0,0266|1776| [W1]-[W2]_Y, ;Compare
|0266|1777| IF CT [IN] THEN [CMDP6]
|0266|1778| J[0173]_[W2] ;172 - lower case "z"
000,000,0,14,02,0,02,0,04,0,0,00,00,00,00,00,0,76,1,1,1,03,03,00,0417,00,7,00,0,0,0,0268|1779| [W1]-[W2]_Y, ;Compare
|0268|1780| IF NOT CT [IN] THEN [CMDP6]
|0268|1781| J[040]_[W2] ;Mask for bit
000,000,0,04,13,0,06,0,00,0,0,00,00,00,00,00,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,0270|1782| [W2].XOR.[W1]_F,F_B ;Convert to upper case
000,000,0,04,03,0,02,0,20,0,0,00,00,00,00,00,0,20,1,1,1,03,01,00,0400,00,7,00,0,0,0,0271|1783|CMDP6: [W1]+[W5]_B,
|0271|1784| GOTO [CMDP2]
|0271|1785|
|0271|1786|;Consol commands include:
|0271|1787|;
|0271|1788|; A ;(101) Address Break
|0271|1789|; B ;(102) Bootstrap
|0271|1790|; C ;(103) Continue
|0271|1791|; D #1 #2 ;(104) Deposit #2 in physical memory location #1
|0271|1792|; DI ; Deposit IO
|0271|1793|; DR ; Deposit RAMFILE
|0271|1794|; DV ; Deposit Virtual
|0271|1795|; E # ;(105) Examine physical memory location #
|0271|1796|; EI ; Examine IO
|0271|1797|; ER ; Examine RAMFILE
|0271|1798|; EV ; Examine Virtual
|0271|1799|; H ;(110) Halts the machine and prints out PC
|0271|1800|; I ;(111) Initialize system
|0271|1801|; R ;(122) Repeat
|0271|1802|; S # ;(123) Start at address #
|0271|1803|; SH ; Shutdown
|0271|1804|; SI ; Single Instruction
|0271|1805|; SM ; Start Microcode at uAddr
|0271|1806|; T ;(124) Perform self test
|0271|1807|; ZM ; Zero Memory
|0271|1808|; ^C ;(003) Abort repeat, or current line
|0271|1809|; ^M <cr> ;(015) ends command
|0271|1810|; ^R ;(022) ?????
|0271|1811|; ^U ;(025) deletes current command line
|0271|1812|; ^Z ;(032) ?????
|0271|1813|; ^\ ;(034) Toggles console/user switch for console tty
|0271|1814|; ; ;Separate commands
|0271|1815|; rubout ;(177) deletes previous typed character
|0271|1816|
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,1027,00,7,00,0,0,0,0272|1817|CMDDSP:
|0272|1818| CALL [BKUP CMD TKR] ;Backup over command terminator
000,000,0,04,10,1,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,15,01,00,0477,00,7,01,0,0,0,0273|1819| J[CMDERR MER]_[W1],POP ;Where to go if memory fails
|0273|1820| CALL [SET PF ME RCOVR] ;In case error in command
000,000,0,04,10,1,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,15,01,00,0102,00,7,01,0,0,0,0275|1821| J[0102]_[W1],POP
000,000,0,06,02,0,02,0,20,0,1,00,00,00,00,00,0,64,1,1,1,03,02,00,1046,00,7,00,0,0,0,0276|1822| [W1]-[W5]_F,F_Q_Y,
|0276|1823| IF CT [IZ] THEN [B CMD]
|0276|1824|.IF/FTADRB
000,000,0,14,03,1,77,0,00,0,0,00,00,00,00,00,0,64,1,1,1,03,02,00,1037,00,7,00,0,0,0,0277|1825| Q+[K -1]_F,F_Y,
|0277|1826| IF CT [IZ] THEN [A CMD] ;Ascii "A" = 101
|0277|1827|.ENDIF/FTADRB
000,000,0,06,06,1,00,0,00,0,1,00,00,00,00,00,0,64,1,1,1,03,02,00,1050,00,7,00,0,0,0,0278|1828| Q+1_F,F_Q_Y, ;Ascii "C" = 103
|0278|1829| IF CT [IZ] THEN [C CMD]
000,000,0,06,06,1,00,0,00,0,1,00,00,00,00,00,0,64,1,1,1,03,02,00,1062,00,7,00,0,0,0,0279|1830| Q+1_F,F_Q_Y, ;Ascii "D" = 104
|0279|1831| IF CT [IZ] THEN [D CMD]
000,000,0,06,06,1,00,0,00,0,1,00,00,00,00,00,0,64,1,1,1,03,02,00,1107,00,7,00,0,0,0,0280|1832| Q+1_F,F_Q_Y, ;Ascii "E" = 105
|0280|1833| IF CT [IZ] THEN [E CMD]
|0280|1834| J[0110]_[W1] ;Ascii "H" = 110
000,000,0,06,02,0,02,0,20,0,1,00,00,00,00,00,0,64,1,1,1,03,02,00,1165,00,7,00,0,0,0,0282|1835| [W1]-[W5]_F,F_Q_Y,
|0282|1836| IF CT [IZ] THEN [H CMD]
000,000,0,07,06,1,00,0,00,0,1,00,00,00,00,00,0,64,1,1,1,03,02,00,1171,00,7,00,0,0,0,0283|1837| Q+1_F,F_Q_[W1], ;Ascii "I" = 111
|0283|1838| IF CT [IZ] THEN [I CMD]
|0283|1839|.IF/FTFCSL
000,200,0,14,10,0,00,0,00,0,1,00,00,00,00,00,0,64,1,1,1,03,02,00,1067,00,7,00,0,0,0,0284|1840| [W1]+2_B, ;Ascii "K" = 113
|0284|1841| IF CT [IZ] THEN [JK CMD]
|0284|1842|.ENDIF/FTFCSL
|0284|1843| J[0122]_[W1] ;Ascii "R" = 122
000,000,0,06,02,0,02,0,20,0,1,00,00,00,00,00,0,64,1,1,1,03,02,00,1206,00,7,00,0,0,0,0286|1844| [W1]-[W5]_F,F_Q_Y,
|0286|1845| IF CT [IZ] THEN [REPEAT]
000,000,0,06,06,1,00,0,00,0,1,00,00,00,00,00,0,64,1,1,1,03,02,00,1217,00,7,00,0,0,0,0287|1846| Q+1_F,F_Q_Y, ;Ascii "S" = 123
|0287|1847| IF CT [IZ] THEN [S CMD]
000,000,0,06,06,1,00,0,00,0,1,00,00,00,00,00,0,64,1,1,1,03,02,00,1244,00,7,00,0,0,0,0288|1848| Q+1_F,F_Q_Y, ;Ascii "T" = 124
|0288|1849| IF CT [IZ] THEN [T CMD]
|0288|1850| J[04000]_[W1]
000,000,1,11,03,0,02,0,00,0,0,00,00,11,00,00,0,20,1,1,0,16,00,00,4710,00,7,01,0,0,0,0290|1851| J[04710]_Y24-Y35, ;Ascii "SH" = 24710
|0290|1852| [W1]+[W1]_F,F_LSZ Y_[W1]
000,000,0,06,02,0,02,0,20,0,1,00,00,00,00,00,0,64,1,1,1,03,02,00,1222,00,7,00,0,0,0,0291|1853| [W1]-[W5]_F,F_Q_Y, ;Ascii "SI" = 24711
|0291|1854| IF CT [IZ] THEN [SH CMD]
000,000,0,06,06,1,00,0,00,0,1,00,00,00,00,00,0,64,1,1,1,03,02,00,1225,00,7,00,0,0,0,0292|1855| Q+1_F,F_Q_Y,
|0292|1856| IF CT [IZ] THEN [SI CMD]
|0292|1857|.IF/FTFCSL
|0292|1858| [W1]J[01111]_[W1] ;Ascii "DI" = 21111
000,000,0,14,02,0,02,0,20,0,0,00,00,00,00,00,0,64,1,1,1,03,02,00,1135,00,7,00,0,0,0,0294|1859| [W1]-[W5]_Y,
|0294|1860| IF CT [IZ] THEN [DI CMD]
|0294|1861| [W1]J[01122]_[W1] ;Ascii "DR" = 21122
000,000,0,14,02,0,02,0,20,0,0,00,00,00,00,00,0,64,1,1,1,03,02,00,1146,00,7,00,0,0,0,0296|1862| [W1]-[W5]_Y,
|0296|1863| IF CT [IZ] THEN [DR CMD]
|0296|1864| [W1]J[01126]_[W1] ;Ascii "DV" = 21126
000,000,0,14,02,0,02,0,20,0,0,00,00,00,00,00,0,64,1,1,1,03,02,00,1155,00,7,00,0,0,0,0298|1865| [W1]-[W5]_Y,
|0298|1866| IF CT [IZ] THEN [DV CMD]
|0298|1867| [W1]J[01311]_[W1] ;Ascii "EI" = 21311
000,000,0,14,02,0,02,0,20,0,0,00,00,00,00,00,0,64,1,1,1,03,02,00,1141,00,7,00,0,0,0,0300|1868| [W1]-[W5]_Y,
|0300|1869| IF CT [IZ] THEN [EI CMD]
|0300|1870| [W1]J[01326]_[W1] ;Ascii "EV" = 21326
000,000,0,14,02,0,02,0,20,0,0,00,00,00,00,00,0,64,1,1,1,03,02,00,1161,00,7,00,0,0,0,0302|1871| [W1]-[W5]_Y,
|0302|1872| IF CT [IZ] THEN [EV CMD]
|0302|1873| [W1]J[01322]_[W1] ;Ascii "ER" = 21322
000,000,0,14,02,0,02,0,20,0,0,00,00,00,00,00,0,64,1,1,1,03,02,00,1151,00,7,00,0,0,0,0304|1874| [W1]-[W5]_Y,
|0304|1875| IF CT [IZ] THEN [ER CMD]
|0304|1876|.IF/FTSM
|0304|1877| [W1]J[04715]_[W1] ;Ascii "SM" = 24715
000,000,0,14,02,0,02,0,20,0,0,00,00,00,00,00,0,64,1,1,1,03,02,00,1242,00,7,00,0,0,0,0306|1878| [W1]-[W5]_Y,
|0306|1879| IF CT [IZ] THEN [SM CMD]
|0306|1880|.ENDIF/FTSM
|0306|1881|.IF/FTZM
|0306|1882| [W1]J[06515]_[W1] ;Ascii "ZM" = 26515
000,000,0,14,02,0,02,0,20,0,0,00,00,00,00,00,0,64,1,1,1,03,02,00,1271,00,7,00,0,0,0,0308|1883| [W1]-[W5]_Y,
|0308|1884| IF CT [IZ] THEN [ZM CMD]
|0308|1885|.ENDIF/FTZM
|0308|1886|.ENDIF/FTFCSL
|0308|1887|
|0308|1888|;Here if user typed an invalid command
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,0765,00,7,00,0,0,0,0309|1889|CMDERR URC:
|0309|1890| CALL [CMDBUF FLUSH] ;Done with CMD buffer
|0309|1891| J[ERR.URC]_[W1] ;Unrecognized command
000,000,0,04,10,1,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0001,00,7,01,0,0,0,0310|1892| GOTOP [CMDERR]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,13,01,00,0501,00,7,00,0,0,0,0311|1893|
000,000,0,04,10,1,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0002,00,7,01,0,0,0,0312|1894|CMDERR NWR:
|0312|1895| J[ERR.NWR]_[W1] ;Error code (not while running)
|0312|1896| GOTOP [CMDERR]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,13,01,00,0501,00,7,00,0,0,0,0313|1897|
000,000,0,04,10,1,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0004,00,7,01,0,0,0,0314|1898|CMDERR NXA:
|0314|1899| J[ERR.NXA]_[W1] ;Error code (nonexistent adr)
|0314|1900| GOTOP [CMDERR]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,13,01,00,0501,00,7,00,0,0,0,0315|1901|
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,0533,00,7,00,0,0,0,0316|1902|CMDERR E MER:
|0316|1903| CALL [PUT CMR NUM] ;Type error status
|0316|1904| CALL [PUT CMR SPACE]
000,000,0,04,06,1,46,0,00,0,0,00,00,00,00,00,0,20,1,1,1,03,01,00,0477,00,7,00,0,0,0,0318|1905| [MB]_[W1], ;Type data next
|0318|1906| GOTO [CMDERR MER]
|0318|1907|
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,0533,00,7,00,0,0,0,0319|1908|CMDERR MER:
|0319|1909| CALL [PUT CMR NUM] ;Type error status
|0319|1910| J[ERR.MER]_[W1] ;Error code (memory error)
000,000,0,04,10,1,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0005,00,7,01,0,0,0,0320|1911| ;GOTOP [CMDERR]
|0320|1912|
000,000,0,04,10,1,00,0,24,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0103,00,7,01,0,0,0,0321|1913|CMDERR: J[0103]_[W6] ;Ascii "C"
000,000,0,04,06,1,02,0,20,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,0556,00,7,00,0,0,0,0322|1914| [W1]_[W5], ;Save error code
|0322|1915| CALL [PUT ? W6]
000,000,0,04,10,0,22,2,00,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,0540,00,7,07,0,0,0,0323|1916| SWAP [W5]_[W1],
|0323|1917| CALL [P6DNUM] ;Type (6 digit) error number
|0323|1918| GOTOP [CMD DONE 2]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,13,01,00,0506,00,7,00,0,0,0,0324|1919|
|0324|1920|
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,0765,00,7,00,0,0,0,0325|1921|CMD DONE:
|0325|1922| CALL [CMDBUF FLUSH] ;Done with CMD buffer
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,03,0,20,1,1,0,15,01,00,0300,00,7,01,0,0,0,0326|1923|CMD DONE 2:
|0326|1924| J[CMDFLG]_RAMFILE ADR,POP ;Address command flags
000,000,0,04,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,15,01,00,0000,00,7,04,0,0,0,0327|1925| RAMFILE_[W1],POP ;Get flags
000,000,0,14,14,0,47,0,00,0,0,00,00,00,00,00,0,64,1,1,1,01,02,00,0567,00,7,00,0,0,0,0328|1926| [BIT4]&[W1]_Y, ;(F.USR) Check user mode
|0328|1927| IF CT [IZ] CALL [PUT CMR PROMPT]
000,000,0,04,10,1,00,0,00,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,1240,00,7,00,0,0,0,0329|1928|CMD9:
|0329|1929|
|0329|1930|;Here when command has been executed
|0329|1931|
|0329|1932|CMD PRSE8:
|0329|1933| ZERO_[W1],CALL [SET INT RCOVR] ;Clear interrupt recovery
000,000,0,04,10,1,00,0,00,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,5016,00,7,00,0,0,0,0330|1934| ZERO_[W1], ;Clear page fail
|0330|1935| CALL [SET PF ME RCOVR] ; and mem err recovery
|0330|1936| GOTOP [CONSOLE]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,13,01,00,0342,00,7,00,0,0,0,0331|1937|
|0331|1938|;Here to get a char from a command line, skiping leading blanks
|0331|1939|; Returns with character in W1
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,1004,00,7,00,0,0,0,0332|1940|GET CMD CHX:
|0332|1941| CALL [GET CMD CHR]
|0332|1942| J[040]_[W2]
000,000,0,14,02,0,02,0,04,0,0,00,00,00,00,00,0,64,1,1,1,03,02,00,0514,00,7,00,0,0,0,0334|1943| [W1]-[W2]_Y,
|0334|1944| IF CT [IZ] THEN [GET CMD CHX]
|0334|1945| RETURN
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,12,01,00,0000,00,7,00,0,0,0,0335|1946|
|0335|1947|;Here to get a number from a command line
|0335|1948|; Returns clears UZ if number is found, number in W1
000,000,0,04,10,1,00,0,20,0,0,00,00,00,00,00,0,11,0,1,1,01,01,00,0514,00,7,00,0,0,0,0336|1949|GET CMD NUM:
|0336|1950| ZERO_[W5],#1_UZ, ;Build number here
|0336|1951| CALL [GET CMD CHX] ; Get 1st nonblank char from command
000,000,0,04,10,1,00,0,04,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0067,00,7,01,0,0,0,0337|1952|GCN 2: J[067]_[W2] ; Ascii '7'
000,000,0,14,02,0,06,0,00,0,0,00,00,00,00,00,0,76,1,1,1,03,02,00,0531,00,7,00,0,0,0,0338|1953| [W2]-[W1]_Y,
|0338|1954| IF CT [IN] THEN [GCN 4]
|0338|1955| J[060]_[W2] ;Ascii '0'
000,000,0,04,01,0,06,0,00,0,1,00,00,00,00,00,0,76,1,1,1,03,02,00,0531,00,7,00,0,0,0,0340|1956| [W1]-[W2]_A,
|0340|1957| IF CT [IN] THEN [GCN 4]
000,000,1,11,03,0,22,0,20,0,0,00,00,11,00,00,0,10,0,1,1,16,00,00,0000,00,7,00,0,0,0,0341|1958| #4*[W5]_B,#0_UZ ;Clear UZ (we got a num)
|0341|1959| #2*[W5]_[W5]
000,000,0,04,03,0,02,0,20,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,1004,00,7,00,0,0,0,0343|1960| [W1]+[W5]_B,
|0343|1961| CALL [GET CMD CHR]
|0343|1962| GOTO [GCN 2]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,03,01,00,0521,00,7,00,0,0,0,0344|1963|
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,1027,00,7,00,0,0,0,0345|1964|GCN 4: CALL [BKUP CMD TKR] ;Backup command buffer taker
000,000,0,04,06,1,22,0,00,0,0,00,00,00,00,00,0,20,1,1,1,12,01,00,0000,00,7,00,0,0,0,0346|1965| [W5]_[W1], ;Copy result
|0346|1966| RETURN ; and dismiss
|0346|1967|
|0346|1968|
|0346|1969|;Here to type number on CTY
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,0540,00,7,00,0,0,0,0347|1970|PUT CMR NUM:
|0347|1971| CALL [P6DNUM] ;Type first half
|0347|1972| J[054]_[W1] ;Ascii ","
000,000,0,04,10,1,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0054,00,7,01,0,0,0,0348|1973| CALL [PUT CMR CHR]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,0607,00,7,00,0,0,0,0349|1974| J[X1]_RAMFILE ADR
000,000,0,04,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,03,01,00,0540,00,7,04,0,0,0,0351|1975| RAMFILE_[W1], ;Get rest of number back
|0351|1976| GOTO [P6DNUM] ;Type 2nd half
|0351|1977|
|0351|1978|;Here to type a six digit octal number on CTY
000,000,0,04,10,1,00,0,24,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0006,00,7,01,0,0,0,0352|1979|P6DNUM: J[6]_[W6] ;Keep digit counter in W6
|0352|1980| J[X1]_RAMFILE ADR
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,14,00,00,0002,00,7,00,0,0,0,0354|1981|P6DNM2: J[2]_CTR
000,000,1,11,06,1,02,0,00,0,0,00,00,51,00,00,0,20,1,1,1,11,00,00,0543,00,7,04,0,0,0,0355|1982|P6DNM3: ROL [W1]_[W1],ALU_RAMFILE, ;Rotate left thrice
|0355|1983| LOOP [P6DNM3]
|0355|1984| J[7]_[W2] ;Mask for number
000,000,0,07,14,0,06,0,00,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0060,00,7,01,0,0,0,0357|1985| [W2]&[W1]_F,F_Q FJ[060]_[W1] ;Mask number to 3 bits
000,000,0,04,03,1,02,0,00,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,0607,00,7,00,0,0,0,0358|1986| Q+[W1]_[W1], ;Convert octal to ascii
|0358|1987| CALL [PUT CMR CHR] ; and print
|0358|1988| J[X1]_RAMFILE ADR ; and address word
000,000,0,04,03,0,77,0,24,0,0,00,00,00,00,00,0,20,1,0,1,16,00,00,0000,00,7,00,0,0,0,0360|1989| [K -1]+[W6]_B,IX_MX ;Count digits typed
000,000,0,04,10,0,00,0,00,0,0,00,00,00,00,00,0,44,1,1,0,03,03,00,0542,00,7,04,0,0,0,0361|1990| RAMFILE_[W1], ;Get number back again
|0361|1991| IF NOT CT [MZ] THEN [P6DNM2]
|0361|1992| RETURN
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,12,01,00,0000,00,7,00,0,0,0,0362|1993|
|0362|1994|;Here to type "^X"
|0362|1995|; call with J[x]_[W6]
000,000,0,04,10,1,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0136,00,7,01,0,0,0,0363|1996|PUT CNTRL W6:
|0363|1997| J[0136]_[W1] ;Ascii "^"
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,0607,00,7,00,0,0,0,0364|1998|PUTXW6:
|0364|1999| CALL [PUT CMR CHR]
000,000,0,04,06,1,26,0,00,0,0,00,00,00,00,00,0,20,1,1,1,03,01,00,0607,00,7,00,0,0,0,0365|2000| [W6]_[W1],
|0365|2001| GOTO [PUT CMR CHR]
|0365|2002|
|0365|2003|;Here to type "?x"
|0365|2004|; Call with J[x]_[W6]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,0604,00,7,00,0,0,0,0366|2005|PUT ? W6:
|0366|2006| CALL [PUT CMR CRLF] ;Begin with a flourish
|0366|2007| J[034]_[W1] ;Ascii "^\\"
000,000,0,04,10,1,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0034,00,7,01,0,0,0,0367|2008| CALL [PUT CMR CHR] ;Type it for John Kirchoff
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,0607,00,7,00,0,0,0,0368|2009| J[077]_[W1] ;Ascii "?"
000,000,0,04,10,1,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0077,00,7,01,0,0,0,0369|2010|GOTO [PUTXW6]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,03,01,00,0554,00,7,00,0,0,0,0370|2011|
|0370|2012|;Here to type a "/" followed by a " "
000,000,0,04,10,1,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0057,00,7,01,0,0,0,0371|2013|PUT CMR SLSH:
|0371|2014| J[057]_[W1] ;Ascii "/"
|0371|2015| CALL [PUT CMR CHR]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,0607,00,7,00,0,0,0,0372|2016|
000,000,0,04,10,1,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0040,00,7,01,0,0,0,0373|2017|PUT CMR SPACE:
|0373|2018| J[040]_[W1] ; Ascii " "
|0373|2019| GOTO [PUT CMR CHR]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,03,01,00,0607,00,7,00,0,0,0,0374|2020|
|0374|2021|;Here to type "<CR><LF>KT20>"
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,0604,00,7,00,0,0,0,0375|2022|PUT CMR PROMPT:
|0375|2023| CALL [PUT CMR CRLF] ;Begin with a flourish
|0375|2024| J[CMDTKR]_RAMFILE ADR ;Address command taker
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,03,0,20,1,1,0,16,00,00,0341,00,7,01,0,0,0,0376|2025|.IF/FTCRAM
|0376|2026| RAMFILE_[W1] ;If already have command
|0376|2027| [W1]_[W1], ;Let latches go
|0376|2028| IF NOT CT [IZ] RETURN ; do not prompt
|0376|2029|.ENDIF/FTCRAM
|0376|2030|.IFNOT/FTCRAM
000,000,0,04,10,0,00,0,00,0,0,00,00,00,00,00,0,64,1,1,0,12,03,00,0000,00,7,04,0,0,0,0377|2031| RAMFILE_[W1], ;If already have command
|0377|2032| IF NOT CT [IZ] RETURN ; do not prompt
|0377|2033|.ENDIF/FTCRAM
|0377|2034| J[0113]_[W1] ;Ascii "K"
000,000,0,04,10,1,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0113,00,7,01,0,0,0,0378|2035| CALL [PUT CMR CHR]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,0607,00,7,00,0,0,0,0379|2036| J[0124]_[W1] ;Ascii "T"
000,000,0,04,10,1,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0124,00,7,01,0,0,0,0380|2037| CALL [PUT CMR CHR]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,0607,00,7,00,0,0,0,0381|2038| J[062]_[W1] ;Ascii "2"
000,000,0,04,10,1,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0062,00,7,01,0,0,0,0382|2039| CALL [PUT CMR CHR]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,0607,00,7,00,0,0,0,0383|2040| J[060]_[W1] ;Ascii "0"
000,000,0,04,10,1,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0060,00,7,01,0,0,0,0384|2041| CALL [PUT CMR CHR]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,0607,00,7,00,0,0,0,0385|2042| J[076]_[W1] ;Ascii ">"
000,000,0,04,10,1,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0076,00,7,01,0,0,0,0386|2043| GOTO [PUT CMR CHR]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,03,01,00,0607,00,7,00,0,0,0,0387|2044|
|0387|2045|;Here to type a <CR><LF>
000,000,0,04,10,1,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0015,00,7,01,0,0,0,0388|2046|PUT CMR CRLF:
|0388|2047| J[015]_[W1]
|0388|2048| CALL [PUT CMR CHR]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,0607,00,7,00,0,0,0,0389|2049| J[012]_[W1]
000,000,0,04,10,1,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0012,00,7,01,0,0,0,0390|2050| ;CALL [PUT CMR CHR]
|0390|2051| ;RETURN
|0390|2052|
|0390|2053|;Here to type command responses on CTY
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,03,0,20,1,1,0,16,00,00,0300,00,7,01,0,0,0,0391|2054|PUT CMR CHR:
|0391|2055| J[CMDFLG]_RAMFILE ADR ;Address command flags
|0391|2056| J[F.O]_[W2] ;Flag for we are flushing output
000,000,0,07,06,1,06,0,04,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0000,00,7,04,0,0,0,0393|2057| RAMFILE_Y,[W2]_F,Y_[W2] F_Q ;Get flags
000,000,0,14,14,1,06,0,00,0,0,00,00,00,00,00,0,64,1,1,1,12,03,00,0000,00,7,00,0,0,0,0394|2058| Q&[W2]_Y,IF NOT CT [IZ] RETURN ;If flushing we are done
|0394|2059| J[CMRPTR]_RAMFILE ADR ;Address putter for CMRBUF
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,03,0,20,1,1,0,16,00,00,0302,00,7,01,0,0,0,0395|2060| J[CMRBUF END]_[W2] ;last location in CMRBUF
000,000,0,04,10,1,00,0,04,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0337,00,7,01,0,0,0,0396|2061| RAMFILE_[W3] ;Get putter
000,000,0,14,02,0,06,0,10,0,0,00,00,00,00,00,0,64,1,1,1,12,02,00,0000,00,7,00,0,0,0,0398|2062| [W2]-[W3]_Y, ;If full can not put in
|0398|2063| IF CT [IZ] RETURN
|0398|2064| CALL [CMB NXT] ;Adjust pointer
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,1005,00,7,00,0,0,0,0399|2065| [W2]_RAMFILE ;Write byte into ramfile
000,000,0,14,14,0,77,0,04,0,0,00,00,00,00,00,0,20,1,1,1,16,00,00,0000,00,7,04,0,0,0,0400|2066| J[CMRTKR]_RAMFILE ADR ;Address taker
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,03,0,20,1,1,0,16,00,00,0303,00,7,01,0,0,0,0401|2067|.IF/FTCRAM
|0401|2068| RAMFILE_[W1] ;Get taker
|0401|2069| [W1]_[W1], ;Let latches go
|0401|2070| IF CT [IZ] CALL [CKR PTR RESET]
|0401|2071|.ENDIF/FTCRAM
|0401|2072|.IFNOT/FTCRAM
000,000,0,04,10,0,00,0,00,0,0,00,00,00,00,00,0,64,1,1,0,01,02,00,0777,00,7,04,0,0,0,0402|2073| RAMFILE_[W1], ;Get taker
|0402|2074| IF CT [IZ] CALL [CMR PTR RESET]
|0402|2075|.ENDIF/FTCRAM
000,000,0,04,10,1,00,0,25,0,0,00,00,00,00,00,0,20,1,1,1,03,01,00,3675,00,7,00,0,0,0,0403|2076| ZERO_[W6 LH], ;Cty is line 0
|0403|2077| GOTO [SET PCI TXEN] ;Start transmitter
|0403|2078|
|0403|2079|;Here to put characters in the command buffer
|0403|2080|
|0403|2081|;With 7bit char in Q
000,000,0,04,14,1,77,0,00,0,0,00,00,00,00,00,0,64,1,1,1,13,02,00,3613,00,7,00,0,0,0,0404|2082|CONSOLE CHAR:
|0404|2083| Q_[W1], ; Flush nulls
|0404|2084| IF CT [IZ] THENP [PCI INT CLR]
|0404|2085| J[003]_[W2] ; Ascii "C"
000,000,0,14,01,1,06,0,00,0,1,00,00,00,00,00,0,64,1,1,1,03,02,00,0722,00,7,00,0,0,0,0406|2086| Q-[W2]_Y,
|0406|2087| IF CT [IZ] THEN [CNTRL C U]
|0406|2088| J[017]_[W2] ; Ascii "^0" = 17
000,000,0,04,01,0,02,0,04,0,1,00,00,00,00,00,0,64,1,1,1,03,02,00,0734,00,7,00,0,0,0,0408|2089| [W2]-[W1]_A,
|0408|2090| IF CT [IZ] THEN [CNTRL O]
000,200,0,14,10,0,00,0,04,0,1,00,00,00,00,00,0,64,1,1,1,03,02,00,0760,00,7,00,0,0,0,0409|2091| [W2]+2_B,
|0409|2092| IF CT [IZ] THEN [CNTRL Q] ;Ascii "^Q" = 21 = Xon
000,200,0,14,10,0,00,0,04,0,1,00,00,00,00,00,0,64,1,1,1,03,02,00,0746,00,7,00,0,0,0,0410|2093| [W2]+2_B,
|0410|2094| IF CT [IZ] THEN [CNTRL S] ;Ascii "^S" = 23 = Xoff
|0410|2095| J[CMDTKR]_RAMFILE ADR ;Address command taker
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,03,0,20,1,1,0,16,00,00,0341,00,7,01,0,0,0,0411|2096|.IF/FTCRAM
|0411|2097| RAMFILE_[W3] ;Get taker
|0411|2098| [W3]_[W3], ;Let latches go
|0411|2099| IF NOT CT [IZ] THEN [TYPE AHEAD] ; Ignore type ahead
|0411|2100|.ENDIF/FTCRAM
|0411|2101|.IFNOT/FTCRAM
000,000,0,04,10,0,00,0,10,0,0,00,00,00,00,00,0,64,1,1,0,03,03,00,0667,00,7,04,0,0,0,0412|2102| RAMFILE_[W3], ;Get taker
|0412|2103| IF NOT CT [IZ] THEN [TYPE AHEAD] ; Ignore type ahead
|0412|2104|.ENDIF/FTCRAM
|0412|2105|.IF/FTCTLR
000,000,0,14,03,0,06,0,77,0,0,00,00,00,00,00,0,64,1,1,1,03,02,00,0703,00,7,00,0,0,0,0413|2106| [W2]+[K -1]_Y, ; Ascii "^R" = 22
|0413|2107| IF CT [IZ] THEN [CNTRL R]
|0413|2108|.ENDIF/FTCTLR
000,200,0,14,10,0,00,0,04,0,1,00,00,00,00,00,0,64,1,1,1,03,02,00,0722,00,7,00,0,0,0,0414|2109| [W2]+2_B, ;Ascii "^U" = 25
|0414|2110| IF CT [IZ] THEN [CNTRL C U]
|0414|2111| J[032]_[W2] ;Ascii "^Z"
000,000,0,14,01,1,06,0,00,0,1,00,00,00,00,00,0,64,1,1,1,03,02,00,0754,00,7,00,0,0,0,0416|2112| Q-[W2]_Y,
|0416|2113| IF CT [IZ] THEN [CNTRL Z]
|0416|2114| J[0177]_[W2] ;Ascii "rubout" = 177
000,000,0,14,01,1,06,0,00,0,1,00,00,00,00,00,0,64,1,1,1,03,02,00,0674,00,7,00,0,0,0,0418|2115| Q-[W2]_Y, ;Check for character was a rubout
|0418|2116| IF CT [IZ] THEN [CMD RUBOUT]
|0418|2117| J[CMDPTR]_RAMFILE ADR ;Address CMDBUF putter
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,03,0,20,1,1,0,16,00,00,0340,00,7,01,0,0,0,0419|2118| J[CMDBUF END]_[W2] ;Last location in CMDBUF
000,000,0,04,10,1,00,0,04,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0407,00,7,01,0,0,0,0420|2119| RAMFILE_[W3] ;Get putter
000,000,0,14,02,0,06,0,10,0,0,00,00,00,00,00,0,64,1,1,1,03,02,00,0671,00,7,00,0,0,0,0422|2120| [W2]-[W3]_Y, ;If buffer is full stop
|0422|2121| IF CT [IZ] THEN [REFUSE CHAR] ; accepting chars
|0422|2122| J[015]_[W2] ;Carriage return
000,000,0,14,02,0,02,0,04,0,0,00,00,00,00,00,0,64,1,1,1,03,02,00,0653,00,7,00,0,0,0,0424|2123| [W1]-[W2]_Y,
|0424|2124| IF CT [IZ] THEN [CMDC 2]
|0424|2125| J[012]_[W6] ;Ascii <LF>
000,000,0,14,02,0,26,0,00,0,0,00,00,00,00,00,0,64,1,1,1,03,03,00,0665,00,7,00,0,0,0,0426|2126| [W6]-[W1]_Y,
|0426|2127| IF NOT CT [IZ] THEN [CMDC 3]
|0426|2128|
|0426|2129|;Here when char is <CR> or <LF>
000,000,0,04,06,1,06,0,00,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,1001,00,7,00,0,0,0,0427|2130|CMDC 2: [W2]_[W1], ;Put <CR> in CMD buffer
|0427|2131| CALL [PUT CMDBUF]
|0427|2132| CALL [ENABLE PARSE]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,0663,00,7,00,0,0,0,0428|2133| CALL [PUT CMR CRLF] ;End echo with <CR><LF>
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,0604,00,7,00,0,0,0,0429|2134|
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,13,43,00,3613,00,7,00,0,0,0,0430|2135|CMDC X: IF [NOT RUN] THENP [PCI INT CLR]
|0430|2136|.IF/DEBUG3
|0430|2137| J[POOP FLAG]_RAMFILE ADR
000,000,0,14,10,1,00,0,00,0,0,00,00,00,00,00,0,20,1,1,1,16,00,00,0000,00,7,04,0,0,0,0432|2138| ZERO_Y,ALU_RAMFILE
|0432|2139|.ENDIF/DEBUG3
000,000,0,04,10,1,00,0,00,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,5017,00,7,00,0,0,0,0433|2140| ZERO_[W1],CALL [SET PF RCOVR]
000,000,0,04,06,1,62,0,43,0,0,00,00,00,46,00,0,20,1,1,1,03,01,00,0347,00,7,00,0,0,0,0434|2141| [PXCT]_[PI REG],Y_2914 STATUS, ;Restore previous level
|0434|2142| GOTO [CMD PRSEX] ;This is not really an int
|0434|2143|
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,03,0,20,1,1,0,16,00,00,0341,00,7,01,0,0,0,0435|2144|ENABLE PARSE:
|0435|2145| J[CMDTKR]_RAMFILE ADR ;Point to command taker
|0435|2146| GOTO [CMD PTR RESET] ;We can parse now
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,03,01,00,0772,00,7,00,0,0,0,0436|2147|
000,000,0,04,06,1,02,0,24,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,1001,00,7,00,0,0,0,0437|2148|CMDC 3: [W1]_[W6], ;Save character
|0437|2149| CALL [PUT CMDBUF] ; And put in CMDBUF
000,000,0,04,06,1,26,0,00,0,0,00,00,00,00,00,0,20,1,1,1,13,01,00,0672,00,7,00,0,0,0,0438|2150| [W6]_[W1], ;Then echo the char
|0438|2151| GOTOP [PUT W1&DISMISS] ;Type W1 then dismiss int
|0438|2152|
|0438|2153|;Here for typeahead
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,03,0,20,1,1,0,16,00,00,0301,00,7,01,0,0,0,0439|2154|TYPE AHEAD:
|0439|2155| J[CMDRPT]_RAMFILE ADR ;Address repeat counter
000,000,0,14,00,1,00,0,00,0,0,00,00,00,00,00,0,20,1,1,1,16,00,00,0000,00,7,04,0,0,0,0440|2156| ONES_F,F_Y,ALU_RAMFILE ;typeahead kills repeat
000,000,0,04,10,1,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0007,00,7,01,0,0,0,0441|2157|REFUSE CHAR:
|0441|2158| J[007]_[W1] ;Ascii "^G"
|0441|2159|
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,0607,00,7,00,0,0,0,0442|2160|PUT W1&DISMISS:
|0442|2161| CALL [PUT CMR CHR]
|0442|2162| GOTOP [PCI INT CLR]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,13,01,00,3613,00,7,00,0,0,0,0443|2163|
|0443|2164|;Here to process a rubout
000,000,0,06,06,1,72,0,00,0,0,00,00,00,00,03,0,20,1,1,0,16,00,00,0340,00,7,01,0,0,0,0444|2165|CMD RUBOUT:
|0444|2166| J[CMDPTR]_RAMFILE ADR, ;Address putter
|0444|2167| [K 777]_Q
|0444|2168| RAMFILE_[W1] ;Get command putter
000,000,0,07,14,1,02,0,04,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0341,00,7,01,0,0,0,0446|2169| Q&[W1]_F, ;Leave only ramfile adr in Q
|0446|2170| F_Q FJ[CMDBUF-1]_[W2]
000,000,0,14,02,0,06,0,00,0,0,00,00,00,00,00,0,64,1,1,1,13,02,00,3613,00,7,00,0,0,0,0447|2171| [W2]-[W1]_Y, ;See if any characters to delete
|0447|2172| IF CT [IZ] THENP [PCI INT CLR] ; Nothing does not echo
|0447|2173| CALL [BKUP POINTER] ;Backup pointer
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,1030,00,7,00,0,0,0,0448|2174| J[0134]_[W1] ;Ascii "\"
000,000,0,04,10,1,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0134,00,7,01,0,0,0,0449|2175| GOTOP [PUT W1&DISMISS] ;Type W1 then dismiss int
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,13,01,00,0672,00,7,00,0,0,0,0450|2176|
|0450|2177|.IF/FTCTLR
|0450|2178|;Here for a "R
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,03,0,20,1,1,0,16,00,00,0303,00,7,01,0,0,0,0451|2179|CNTRL R:
|0451|2180| J[CMRTKR]_RAMFILE ADR ;Address response taker
|0451|2181|.IF/FTCRAM
|0451|2182| RAMFILE_[W2] ;When typing ignore
|0451|2183| [W2]_[W2], ;let latches go
|0451|2184| IF NOT CT [IZ] THENP [PCI INT CLR]
|0451|2185|.ENDIF/FTCRAM
|0451|2186|.IFNOT/FTCRAM
000,000,0,04,10,0,00,0,04,0,0,00,00,00,00,00,0,64,1,1,0,13,03,00,3613,00,7,04,0,0,0,0452|2187| RAMFILE_[W2], ;When typing ignore
|0452|2188| IF NOT CT [IZ] THENP [PCI INT CLR]
|0452|2189|.ENDIF/FTCRAM
|0452|2190| J[0122]_[W6] ;Put "R" in W6
000,000,0,04,10,1,00,0,24,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0122,00,7,01,0,0,0,0453|2191| CALL [PUT CNTRL W6] ;Type "^R"
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,0553,00,7,00,0,0,0,0454|2192| CALL [PUT CMR PROMPT] ;Retype prompt
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,0567,00,7,00,0,0,0,0455|2193|;copy CMD buffer to CMR buffer
|0455|2194| CALL [ENABLE PARSE]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,0663,00,7,00,0,0,0,0456|2195| GOTO [CR4] ;Be sure there is anything to do
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,1004,00,7,00,0,0,0,0458|2196|CR2: CALL [GET CMD CHR]
|0458|2197| CALL [PUT CMR CHR] ;Copy byte to CMR buffer
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,03,0,20,1,1,0,16,00,00,0340,00,7,01,0,0,0,0460|2198|CR4: J[CMDPTR]_RAMFILE ADR ;Address putter
|0460|2199| RAMFILE_[W2]
000,000,0,04,10,0,00,0,04,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0000,00,7,04,0,0,0,0461|2200| J[CMDTKR]_RAMFILE ADR ;Address taker
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,03,0,20,1,1,0,16,00,00,0341,00,7,01,0,0,0,0462|2201| RAMFILE_[W1]
000,000,0,14,13,0,02,0,04,0,0,00,00,00,00,00,0,64,1,1,1,03,03,00,0712,00,7,00,0,0,0,0464|2202| [W1].XOR.[W2]_Y,
|0464|2203| IF NOT CT [IZ] THEN [CR2]
000,000,0,14,10,1,00,0,00,0,0,00,00,00,00,00,0,20,1,1,1,13,01,00,3613,00,7,04,0,0,0,0465|2204| ZERO_Y,ALU_RAMFILE, ;Reset CMD taker
|0465|2205| GOTOP [PCI INT CLR]
|0465|2206|.ENDIF/FTCTLR
|0465|2207|
|0465|2208|;Here for a ^\
000,000,0,04,10,1,00,0,24,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0100,00,7,01,0,0,0,0466|2209|CNTRL BKSLSH:
|0466|2210|
|0466|2211|;Here for ^C or ^U
|0466|2212|CNTRL C U:
|0466|2213| J[0100]_[W6] ;To convert "^C" to "C"
000,000,0,04,03,1,26,0,24,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,0764,00,7,00,0,0,0,0467|2214| Q+[W6]_[W6],
|0467|2215| CALL [CMD&CMR FLUSH] ;Flush command buffer
000,000,0,04,06,1,47,0,00,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0003,00,7,01,0,0,0,0468|2216| [BIT4]_F,FJ[F.O!F.S]_[W1] ; (F.USR) Flags to clear
|0468|2217| CALL [CLEAR CMDFLG]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,0743,00,7,00,0,0,0,0469|2218| CALL [PUT CNTRL W6] ;Type ^C or ^U
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,0553,00,7,00,0,0,0,0470|2219| CALL [PUT CMR PROMPT]
000,000,0,04,10,1,00,0,00,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,1240,00,7,00,0,0,0,0472|2220| ZERO_[W1],CALL [SET INT RCOVR] ;Clear interrupt recovery
|0472|2221| GOTOP [PCI INT CLR] ;Dismiss interrupt
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,13,01,00,3613,00,7,00,0,0,0,0473|2222|
|0473|2223|;Here to turn off F.O (the control 0 flag)
|0473|2224|
000,000,0,04,10,1,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0001,00,7,01,0,0,0,0474|2225|F.O CLEAR:
|0474|2226| J[F.O]_[W1] ;Flags to clear for new command
|0474|2227| GOTO [CLEAR CMDFLG]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,03,01,00,0743,00,7,00,0,0,0,0475|2228|
|0475|2229|;Here for ^O
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,0774,00,7,00,0,0,0,0476|2230|CNTRL O:
|0476|2231| CALL [CMRBUF FLUSH] ;Flush command response buffer
|0476|2232| J[0117]_[W6] ;Ascii "O"
000,000,0,04,10,1,00,0,24,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0117,00,7,01,0,0,0,0477|2233| CALL [PUT CNTRL W6] ;Type ^O
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,0553,00,7,00,0,0,0,0478|2234| J[CMDFLG]_RAMFILE ADR ;Address ramfile word
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,03,0,20,1,1,0,16,00,00,0300,00,7,01,0,0,0,0479|2235| J[F.O]_[W1] ;Flag we are flushing output
000,000,0,07,06,1,02,0,00,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0000,00,7,04,0,0,0,0481|2236| RAMFILE_Y,[W1]_F,Y_[W1] F_Q ;Get word from ramfile
000,000,0,14,13,1,02,0,00,0,0,00,00,00,00,00,0,20,1,1,1,13,01,00,3613,00,7,04,0,0,0,0482|2237| Q.XOR.[W1]_F,F_Y,ALU_RAMFILE, ;Set/clear flag
|0482|2238| GOTOP [PCI INT CLR] ;Dismiss interrupt
|0482|2239|
|0482|2240|;Here to clear a flag in the CKDFLG word
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,03,0,20,1,1,0,16,00,00,0300,00,7,01,0,0,0,0483|2241|CLEAR CMDFLG:
|0483|2242| J[CMDFLG]_RAMFILE ADR ;Address ramfile word
000,000,0,07,07,0,02,0,00,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0000,00,7,04,0,0,0,0484|2243| RAMFILE_Y,Y_[W1] F_Q, ;Get old flag word
|0484|2244| COMPLEMENT [W1]_F
000,000,0,14,14,1,02,0,00,0,0,00,00,00,00,00,0,20,1,1,1,12,01,00,0000,00,7,04,0,0,0,0485|2245| Q&[W1]_Y,ALU_RAMFILE, ;Clear flag
|0485|2246| RETURN
|0485|2247|
|0485|2248|;Here for a ^S (Xoff) command
|0485|2249|
000,000,0,04,10,1,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0002,00,7,01,0,0,0,0486|2250|CNTRL S:
|0486|2251| J[F.S]_[W1] ;Flag to set
|0486|2252| CALL [SET CMDFLG] ; Set it
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,0751,00,7,00,0,0,0,0487|2253| GOTOP [PCI INT CLR]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,13,01,00,3613,00,7,00,0,0,0,0488|2254|
|0488|2255|;Here to set a flag in the CMDFLG word
|0488|2256|
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,03,0,20,1,1,0,16,00,00,0300,00,7,01,0,0,0,0489|2257|SET CMDFLG:
|0489|2258| J[CMDFLG]_RAMFILE ADR ;Address ramfile word
000,000,0,07,06,1,02,0,00,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0000,00,7,04,0,0,0,0490|2259| RAMFILE_Y,[W1]_F,Y_[W1] F_Q ;Get old flag word
000,000,0,14,17,1,02,0,00,0,0,00,00,00,00,00,0,20,1,1,1,12,01,00,0000,00,7,04,0,0,0,0491|2260| Q.OR.[W1]_Y,ALU_RAMFILE, ;Set flag
|0491|2261| RETURN
|0491|2262|
|0491|2263|;Here for a ^Z
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,13,43,00,3613,00,7,00,0,0,0,0492|2264|CNTRL Z:
|0492|2265| IF [NOT RUN] THENP [PCI INT CLR] ;No user mode if stopped
|0492|2266| J[0132]_[W6] ;Ascii "Z"
000,000,0,04,10,1,00,0,24,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0132,00,7,01,0,0,0,0493|2267| CALL [PUT CNTRL W6] ;^Z
000,000,0,04,06,1,47,0,00,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,0751,00,7,00,0,0,0,0495|2268| [BIT4]_[W1], ;(F.USR) User mode
|0495|2269| CALL [SET CMDFLG] ; Set flag
|0495|2270| ;GOTO [CNTRL Q] ;Also clear XOF flag
|0495|2271|
|0495|2272|;Here for a ^Q (Xon)
000,000,0,04,10,1,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0002,00,7,01,0,0,0,0496|2273|CNTRL Q:
|0496|2274| J[F.S]_[W1] ;Flag to clear
|0496|2275| CALL [CLEAR CMDFLG]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,0743,00,7,00,0,0,0,0497|2276| CALL [SET PCI TXEN] ;Start transmitter again
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,3675,00,7,00,0,0,0,0498|2277| GOTOP [PCI INT CLR] ;Dismiss interrupt
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,13,01,00,3613,00,7,00,0,0,0,0499|2278|
|0499|2279|
|0499|2280|;Here to flush command and command response buffer
|0499|2281|
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,0774,00,7,00,0,0,0,0500|2282|CMD&CMR FLUSH:
|0500|2283| CALL [CMRBUF FLUSH] ;First flush the response buffer
|0500|2284| ;GOTO [CMDBUF FLUSH]
|0500|2285|
|0500|2286|;Here to flush command buffer
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,03,0,20,1,1,0,16,00,00,0341,00,7,01,0,0,0,0501|2287|CMDBUF FLUSH:
|0501|2288| J[CMDTKR]_RAMFILE ADR
000,000,0,14,10,1,00,0,00,0,0,00,00,00,00,00,0,20,1,1,1,16,00,00,0000,00,7,04,0,0,0,0502|2289| ZERO_Y,ALU_RAMFILE ;Clear taker
|0502|2290| J[CMDRPT]_RAMFILE ADR ;Address repeat counter
000,000,0,14,10,1,00,0,00,0,0,00,00,00,00,00,0,20,1,1,1,16,00,00,0000,00,7,04,0,0,0,0504|2291| ZERO_Y,ALU_RAMFILE ;Clear repeat counter
|0504|2292| J[CMDPTR]_RAMFILE ADR
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,03,0,20,1,1,0,16,00,00,0340,00,7,01,0,0,0,0505|2293|
000,000,0,04,10,1,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0341,00,7,01,0,0,0,0506|2294|CMD PTR RESET:
|0506|2295| J[CMDBUF-1]_[W1] ;Adr of 1st word-1 of buffer
000,000,0,14,14,0,77,0,00,0,0,00,00,00,00,00,0,20,1,1,1,12,01,00,0000,00,7,04,0,0,0,0507|2296| [W1]_RAMFILE, ; Initialize putter
|0507|2297| RETURN
|0507|2298|
|0507|2299|;Here to flush command response buffer
|0507|2300|
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,03,0,20,1,1,0,16,00,00,0303,00,7,01,0,0,0,0508|2301|CMRBUF FLUSH:
|0508|2302| J[CMRTKR]_RAMFILE ADR
000,000,0,14,10,1,00,0,00,0,0,00,00,00,00,00,0,20,1,1,1,16,00,00,0000,00,7,04,0,0,0,0509|2303| ZERO_Y,ALU_RAMFILE ;Clear taker
|0509|2304| J[CMRPTR]_RAMFILE ADR
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,03,0,20,1,1,0,16,00,00,0302,00,7,01,0,0,0,0510|2305|
000,000,0,04,10,1,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0303,00,7,01,0,0,0,0511|2306|CMR PTR RESET:
|0511|2307| J[CMRBUF-1]_[W1] ;Adr of 1st word-1 of buffer
000,000,0,14,14,0,77,0,00,0,0,00,00,00,00,00,0,20,1,1,1,12,01,00,0000,00,7,04,0,0,0,0512|2308| [W1]_RAMFILE, ;Initialize putter
|0512|2309| RETURN
|0512|2310|
|0512|2311|;Routine to put a byte into the ramfile
|0512|2312|
|0512|2313|; Call with [W1] = char to put
|0512|2314|; Will first increment pointer than store indirect it
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,03,0,20,1,1,0,16,00,00,0340,00,7,01,0,0,0,0513|2315|PUT CMDBUF:
|0513|2316| J[CMDPTR]_RAMFILE ADR ;Address putter for command buffer
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,1005,00,7,00,0,0,0,0514|2317|PUT CMB:
|0514|2318| CALL [CMB NXT] ;Put byte in ramfile word
000,000,0,14,14,0,77,0,04,0,0,00,00,00,00,00,0,20,1,1,1,12,01,00,0000,00,7,04,0,0,0,0515|2319| [W2]_RAMFILE, ;Put word back in ramfile
|0515|2320| RETURN
|0515|2321|
|0515|2322|;Here to get a char from a command line
|0515|2323|
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,03,0,20,1,1,0,16,00,00,0341,00,7,01,0,0,0,0516|2324|GET CMD CHR:
|0516|2325| J[CMDTKR]_RAMFILE ADR ;Address command char taker
|0516|2326| ;GOTO [CMS NXT] ;Advance to next byte
|0516|2327|
|0516|2328|;Get or prepare to put next byte in ramfile CMD or CMR buffer
|0516|2329|; Call J[taker or putter]_RAMFILE ADR
|0516|2330|; _[W1] ;Byte to be stored
|0516|2331|; returns
|0516|2332|; [W1] ;byte from ramfile
|0516|2333|; [W2] ;Ramfile word with byte inserted
|0516|2334|
000,000,0,04,10,0,00,0,04,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0000,00,7,04,0,0,0,0517|2335|CMB NXT:
|0517|2336| RAMFILE_[W2] ;Get current pointer
000,000,0,04,03,0,76,0,04,0,0,00,00,00,00,00,0,76,1,1,1,03,03,00,1012,00,7,00,0,0,0,0518|2337| [K -1.0]+[W2]_B, ;Next byte adr
|0518|2338| IF NOT CT [IN] THEN [CMBP4]
|0518|2339| J[4]_[W3] ;First byte is number 4
000,000,0,04,10,1,00,0,10,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0004,00,7,01,0,0,0,0519|2340| SWAP [W3]_[W2 LH] ;Put byte number in LH
000,000,0,04,10,0,12,2,05,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0000,00,7,07,0,0,0,0520|2341| [W2]+1_[W2 RH] ;Next ramfile adr
000,000,0,14,14,0,77,0,04,0,0,00,00,00,00,03,0,20,1,1,1,16,00,00,0000,00,7,04,0,0,0,0522|2342|CMBP4: [W2]_RAMFILE, ;Store updated pointer
|0522|2343| Y_RAMFILE ADR ; and address buffer
|0522|2344| J[0117]_[W3]
000,000,0,07,14,0,12,0,00,0,0,00,00,00,00,00,0,20,1,1,0,03,01,00,1021,00,7,04,0,0,0,0524|2345| [W3]&[W1]_F, Y_[W1] F_Q, ;Get mask for data
|0524|2346| RAMFILE_Y, ;Get word from ramfile
|0524|2347| GOTO [CMBP7]
000,000,0,01,06,1,02,0,00,0,0,00,00,01,00,00,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,0525|2348|CMBP5: LRS [W1]_[W1] ;Shift ramfile word right
000,000,1,13,06,1,12,0,10,0,0,00,00,31,00,00,0,20,1,1,1,14,00,00,0005,00,7,00,0,0,0,0526|2349| LLSC [W3]_[W3], ;Shift mask and byte left
|0526|2350| J[5]_CTR
000,000,0,01,06,1,02,0,00,0,0,00,00,01,00,00,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,0527|2351|CMBP6: LRS [W1]_[W1] ;Shift ramfile word right
000,000,1,13,06,1,12,0,10,0,0,00,00,31,00,00,0,20,1,1,1,11,00,00,1017,00,7,00,0,0,0,0528|2352| LLSC [W3]_[W3], ;Shift mask and byte left
|0528|2353| LOOP [CMBP6]
000,000,0,04,03,0,76,0,04,0,0,00,00,00,00,00,0,76,1,1,1,03,03,00,1015,00,7,00,0,0,0,0529|2354|CMBP7: [K -1.0]+[W2]_B,
|0529|2355| IF NOT CT [IN] THEN [CMBP5]
|0529|2356| J[0117]_[W2] ;Get mask for data
000,000,0,04,10,1,00,0,04,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0117,00,7,01,0,0,0,0530|2357| [W2]&[W1]_B ;Leave only data byte
000,000,0,04,14,0,06,0,00,0,0,00,00,00,00,00,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,0531|2358| RAMFILE_[W2] ;Get ramfile word again
000,000,0,04,10,0,00,0,04,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0000,00,7,04,0,0,0,0532|2359| [W3]BAR&[W2]_B ;Clear slot for byte
000,000,0,04,17,1,06,0,04,0,0,00,00,00,00,00,0,20,1,1,1,12,01,00,0000,00,7,00,0,0,0,0534|2360| Q.OR.[W2]_[W2], ;Add new byte
|0534|2361| RETURN
|0534|2362|
|0534|2363|;Here to backup the command buffer taker
|0534|2364|
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,03,0,20,1,1,0,16,00,00,0341,00,7,01,0,0,0,0535|2365|BKUP CMD TKR:
|0535|2366| J[CMDTKR]_RAMFILE ADR
|0535|2367| ;GOTO [BKUP POINTER]
|0535|2368|
|0535|2369|;Here to backup a pointer
000,000,0,04,10,1,00,0,04,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0004,00,7,01,0,0,0,0536|2370|BKUP POINTER:
|0536|2371| J[4]_[W2]
|0536|2372| RAMFILE_[W1]
000,000,0,07,04,0,02,2,06,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0000,00,7,07,0,0,0,0538|2373| SWAP [W1]_[W2 RH] F_Q,B[W2 RH]_F
000,000,0,14,02,1,06,0,00,0,1,00,00,00,00,00,0,20,1,0,1,16,00,00,0000,00,7,00,0,0,0,0539|2374| [W2]-Q_F,F_Y,IX_MX ;Test for overflow
000,000,0,04,03,0,57,0,00,0,0,00,00,00,00,00,0,44,1,1,1,03,03,00,5020,00,7,00,0,0,0,0540|2375| [BIT17]+[W1]_B, ;Previous byte number
|0540|2376| IF NOT CT [MZ] THEN [W1_RAMFILE]
|0540|2377| ZERO_[W1 LH]
000,000,0,04,03,0,77,0,00,0,0,00,00,00,00,00,0,20,1,1,1,03,01,00,5020,00,7,00,0,0,0,0542|2378| [K -1]+[W1]_B, ;Backup ramfile word
|0542|2379| GOTO [W1_RAMFILE]
|0542|2380|
|0542|2381|.TOC 2, " A - Console Address Break Command"
|0542|2382|
|0542|2383|;Here for a "Address Break" command
|0542|2384|
|0542|2385|.IF/FTADRB
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,0520,00,7,00,0,0,0,0543|2386|A CMD: CALL [GET CMD NUM]
|0543|2387| J[AB IF]_RAMFILE ADR
000,000,0,14,14,0,77,0,00,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,0520,00,7,04,0,0,0,0545|2388| [W1]_RAMFILE,
|0545|2389| CALL [GET CMD NUM]
|0545|2390| J[AB RD]_RAMFILE ADR
000,000,0,14,14,0,77,0,00,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,0520,00,7,04,0,0,0,0547|2391| [W1]_RAMFILE,
|0547|2392| CALL [GET CMD NUM]
|0547|2393| J[AB WR]_RAMFILE ADR
000,000,0,14,14,0,77,0,00,0,0,00,00,00,00,00,0,20,1,1,1,03,01,00,0511,00,7,04,0,0,0,0549|2394| [W1]_RAMFILE,
|0549|2395| GOTO [CMD PRSE8]
|0549|2396|.ENDIF/FTADRB
|0549|2397|
|0549|2398|.TOC 2, " B - Console Bootstrap Command"
|0549|2399|
|0549|2400|;Here for a B "Bootstrap" command
|0549|2401|
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,03,42,00,0470,00,7,00,0,0,0,0550|2402|B CMD: IF [RUN] THEN [CMDERR NWR]
|0550|2403| GOTO [CMD PRSE8]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,03,01,00,0511,00,7,00,0,0,0,0551|2404|
|0551|2405|.TOC 2, " C - Console Continue Command"
|0551|2406|
|0551|2407|;Here for a CONTINUE command
|0551|2408|
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,03,42,00,0470,00,7,00,0,0,0,0552|2409|C CMD: IF [RUN] THEN [CMDERR NWR]
000,000,0,14,10,0,00,0,00,0,0,00,14,00,00,00,0,20,1,1,0,01,01,00,1057,00,7,00,0,0,0,0553|2410| SET LOCAL,CALL [GET CMD PC] ;Try to get a PC from command
000,000,0,04,06,1,47,0,00,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,0751,00,7,00,0,0,0,0554|2411| [BIT4]_[W1], ; (F.USR) Console now in user mode
|0554|2412| CALL [SET CMDFLG]
|0554|2413| CALL [SET PCI TXEN] ;Start transmitter
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,3675,00,7,00,0,0,0,0555|2414| J[HALT CODE]_RAMFILE ADR
000,000,0,14,10,1,00,0,00,0,0,00,44,00,00,00,0,20,1,1,1,01,01,00,3216,00,7,04,0,0,0,0557|2415| ZERO_Y,ALU_RAMFILE,SET RUN, ;We have not halted
|0557|2416| CALL [SET PI MASK] ; Enable interrupts
|0557|2417| GOTO [CMD PRSE8]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,03,01,00,0511,00,7,00,0,0,0,0558|2418|
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,0520,00,7,00,0,0,0,0559|2419|GET CMD PC:
|0559|2420| CALL [GET CMD NUM] ;Get suggested starting address
|0559|2421| IF CT [UZ] RETURN
000,000,0,04,06,1,02,0,34,0,0,00,00,00,00,00,0,20,1,1,1,12,01,00,0000,00,7,00,0,0,0,0561|2422| [W1]_[PC], ;Set new PC
|0561|2423| RETURN
|0561|2424|
|0561|2425|.TOC 2, " D - Console Deposit Command"
|0561|2426|
|0561|2427|;Here for a D "Deposit memory" command
|0561|2428|
000,000,0,04,10,1,00,0,00,0,0,00,00,00,00,00,0,12,0,1,1,01,01,00,1115,00,7,00,0,0,0,0562|2429|D CMD: ZERO_[W1], ;No int recovery routine
|0562|2430| CALL [GET EXM ADR],#0_UC ;Get adr to deposit
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,4704,00,7,00,0,0,0,0563|2431|DN: CALL [UNMAPPED WRITE]
|0563|2432|.IF/FTFCSL
|0563|2433| CALL [GET CMD NUM] ;Get data
000,000,0,04,06,1,02,0,44,0,0,00,00,00,00,00,0,24,1,1,1,03,03,00,1063,00,7,00,0,0,0,0565|2434| [W1]_[MB],
|0565|2435| IF NOT CT [UZ] THEN [DN]
|0565|2436|.ENDIF/FTFCSL
|0565|2437| GOTO [CMD PRSE8]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,03,01,00,0511,00,7,00,0,0,0,0566|2438|
|0566|2439|.IF/FTFCSL
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,1076,00,7,00,0,0,0,0567|2440|JK CMD: CALL [GET JK NUM] ;Get adr to deposit into
000,000,0,04,06,1,46,0,33,0,0,00,00,00,00,00,0,24,1,1,1,03,02,00,1130,00,7,00,0,0,0,0568|2441| [MB]_[PMA],
|0568|2442| IF CT [UZ] THEN [CMDERR NEA] ;Require address
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,1076,00,7,00,0,0,0,0569|2443|JK L: CALL [GET JK NUM] ;Get data to deposit
|0569|2444| IF CT [UZ] THEN [CMD PRSE8]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,24,1,1,0,03,02,00,0511,00,7,00,0,0,0,0570|2445| J[EXM ADR]_RAMFILE ADR
000,000,0,14,06,1,33,0,00,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,4704,00,7,04,0,0,0,0572|2446| [PMA]_Y,ALU_RAMFILE, ;Save last adr deposited
|0572|2447| CALL [UNMAPPED WRITE]
000,000,0,04,06,1,33,0,33,0,1,00,00,00,00,00,0,20,1,1,1,03,01,00,1071,00,7,00,0,0,0,0573|2448| [PMA]+1_[PMA], ;Next adr
|0573|2449| GOTO [JK L]
|0573|2450|
|0573|2451|;Here to get an "Asciized" number
000,000,0,04,10,1,00,0,44,0,0,00,00,00,00,00,0,11,0,1,1,01,01,00,0514,00,7,00,0,0,0,0574|2452|GET JK NUM:
|0574|2453| ZERO_[MB], #1_UZ,
|0574|2454| CALL [GET CMD CHX] ;Get 1st nonblank char from command
000,000,0,04,10,1,00,0,04,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0075,00,7,01,0,0,0,0575|2455|JK 1: J[075]_[W2]
000,000,0,14,02,0,02,0,04,0,0,00,00,00,00,00,0,76,1,1,1,03,02,00,0531,00,7,00,0,0,0,0576|2456| [W1]-[W2]_Y,
|0576|2457| IF CT [IN] THEN [GCN 4]
|0576|2458| J[0175]_[W2]
000,000,0,14,02,0,02,0,04,0,0,00,00,00,00,00,0,76,1,1,1,03,03,00,0531,00,7,00,0,0,0,0578|2459| [W1]-[W2]_Y,
|0578|2460| IF NOT CT [IN] THEN [GCN 4]
000,000,0,04,14,0,66,0,00,0,0,00,00,00,00,00,0,20,1,1,1,14,00,00,0002,00,7,00,0,0,0,0579|2461| [K 77]&[W1]_B, ;Strip extra bits
|0579|2462| J[2]_CTR
000,000,1,11,03,0,46,0,44,0,0,00,00,11,00,00,0,20,1,1,1,11,00,00,1104,00,7,00,0,0,0,0580|2463|JK 2: #4*[MB]_B,LOOP [JK 2]
000,000,0,04,03,0,02,0,44,0,0,00,00,00,00,00,0,10,0,1,1,01,01,00,1004,00,7,00,0,0,0,0581|2464| [W1]+[MB]_B,#0_UZ,
|0581|2465| CALL [GET CMD CHR]
|0581|2466| GOTO [JK 1]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,03,01,00,1077,00,7,00,0,0,0,0582|2467|.ENDIF/FTFCSL
|0582|2468|
|0582|2469|.TOC 2, " E - Console Examine Memory Command"
|0582|2470|
|0582|2471|;Here for a E "Examine memory" command
|0582|2472|
000,000,0,04,10,1,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,1111,00,7,01,0,0,0,0583|2473|E CMD: J[E CMD RCOVR]_[W1] ;Recovery routine for ints
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,13,0,1,0,01,01,00,1115,00,7,00,0,0,0,0584|2474| CALL [GET EXM ADR], #1_UC ;Get memory adr to examine
000,000,0,04,06,1,33,0,33,0,0,00,00,05,00,00,0,20,1,1,1,16,00,00,0000,00,1,02,0,0,0,0585|2475|E CMD RCOVR:
|0585|2476| [PMA]_[PMA],MEM START READ
|0585|2477| CALL [UNMAPPED READ]
000,000,0,04,06,1,46,0,00,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,0533,00,7,00,0,0,0,0587|2478|EC 3: [MB]_[W1],
|0587|2479| CALL [PUT CMR NUM]
|0587|2480| GOTO [CMD PRSE8]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,03,01,00,0511,00,7,00,0,0,0,0588|2481|
|0588|2482|;Here to set an address to examine or deposit
|0588|2483|; Call J[adr]_[W1] ; Interrupt recovery address
|0588|2484|; CALL [GET EXM ADR],#0_UC ;for deposit commands
|0588|2485|; CALL [GET EXM ADR],l_UC ;For examine commands
|0588|2486|; Returns adr in [E] & [PMA], (and for deposits data in MB)
000,000,0,14,06,1,02,0,00,0,0,00,00,00,00,00,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,0589|2487|GET EXM ADR:
|0589|2488| [W1]_Y ;Set recovery routine
|0589|2489| IF NOT CT [IZ] CALL [SET INT RCOVR] ; for interrupts
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,64,1,1,0,01,03,00,1240,00,7,00,0,0,0,0590|2490| J[CMDERR E MER]_[W1] ;Recovery routine for examines
000,000,0,04,10,1,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0474,00,7,01,0,0,0,0591|2491| IF CT [UC] CALL [SET PF ME RCOVR]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,32,1,1,0,01,02,00,5016,00,7,00,0,0,0,0592|2492| CALL [GET CMD NUM] ;Get adr to examine
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,0520,00,7,00,0,0,0,0593|2493| J[EXM ADR]_RAMFILE ADR
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,03,0,20,1,1,0,16,00,00,0445,00,7,01,0,0,0,0594|2494| IF NOT CT [UZ] THEN [GEA2] ;If no adr use last
000,000,0,04,10,0,00,0,00,0,0,00,00,00,00,00,0,32,1,1,0,03,03,00,1130,00,7,04,0,0,0,0596|2495| RAMFILE_[W1], ;Get last adr used
|0596|2496| IF NOT CT [UC] THEN [CMDERR NEA] ;Require address
000,000,0,04,06,1,02,0,40,0,0,00,00,00,00,00,0,32,1,1,1,03,02,00,1132,00,7,04,0,0,0,0597|2497|GEA2: [W1]_[E],ALU_RAMFILE, ;Save address in E and ramfile
|0597|2498| IF CT [UC] THEN [GEA6] ; Branch for examine
000,000,0,04,06,1,42,0,33,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,0520,00,7,00,0,0,0,0598|2499| [E]_[PMA], ;Save adr in PMA also
|0598|2500| CALL [GET CMD NUM] ;Get data
000,000,0,04,06,1,02,0,44,0,0,00,00,00,00,00,0,24,1,1,1,12,03,00,0000,00,7,00,0,0,0,0599|2501| [W1]_[MB],
|0599|2502| IF NOT CT [UZ] RETURN ;Require data
|0599|2503| ;GOTO [CMDERR NEA]
000,000,0,04,10,1,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0003,00,7,01,0,0,0,0600|2504|CMDERR NEA:
|0600|2505| J[ERR.NEA]_[W1] ;Error code (not enough args)
|0600|2506| GOTOP [CMDERR]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,13,01,00,0501,00,7,00,0,0,0,0601|2507|
000,000,0,04,06,1,42,0,33,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,0604,00,7,00,0,0,0,0602|2508|GEA6: [E]_[PMA], ;Save adr in PMA also
|0602|2509| CALL [PUT CMR CRLF] ;Begin with a flourish
000,000,0,04,06,1,33,0,00,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,0533,00,7,00,0,0,0,0603|2510| [PMA]_[W1], ;Now type adr
|0603|2511| CALL [PUT CMR NUM]
|0603|2512| GOTO [PUT CMR SLSH]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,03,01,00,0563,00,7,00,0,0,0,0604|2513|
|0604|2514|.TOC 2, "DI - Console Deposit I/O Command"
|0604|2515|
|0604|2516|;Here for an DI "Deposit I/O" command
|0604|2517|.IF/FTFCSL
000,000,0,04,10,1,00,0,00,0,0,00,00,00,00,00,0,12,0,1,1,01,01,00,1115,00,7,00,0,0,0,0605|2518|DI CMD: ZERO_[W1], ;No int recovery
|0605|2519| CALL [GET EXM ADR],#0_UC ;Get adr to deposit
000,000,0,04,06,1,02,0,54,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,4042,00,7,00,0,0,0,0606|2520| [W1]_[MEM-OP], ;Put data in right register
|0606|2521| CALL [WRIOX] ;Try to do it
|0606|2522| IF CT [UOVR] THEN [CMDERR NXA]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,26,1,1,0,03,02,00,0472,00,7,00,0,0,0,0607|2523| GOTO [CMD PRSE8]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,03,01,00,0511,00,7,00,0,0,0,0608|2524|.ENDIF/FTFCSL
|0608|2525|
|0608|2526|.TOC 2, "EI - Console Examine IO Command"
|0608|2527|
|0608|2528|;Here for an EI "Examine I/O" command
|0608|2529|.IF/FTFCSL
000,000,0,04,10,1,00,0,00,0,0,00,00,00,00,00,0,13,0,1,1,01,01,00,1115,00,7,00,0,0,0,0609|2530|EI CMD: ZERO_[W1], ;No int recovery
|0609|2531| CALL [GET EXM ADR],#1_UC ;Get adr to examine
|0609|2532| CALL [RDIOX] ;Do read like RDIO
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,1540,00,7,00,0,0,0,0610|2533| IF CT [UOVR] THENP [CMDERR NXA]
000,000,0,04,06,1,56,0,00,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,0533,00,7,00,0,0,0,0612|2534| [MEM-OP]_[W1], ;Copy data
|0612|2535| CALL [PUT CMR NUM] ; Display data
|0612|2536| GOTO [CMD PRSE8]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,03,01,00,0511,00,7,00,0,0,0,0613|2537|.ENDIF/FTFCSL
|0613|2538|
|0613|2539|.TOC 2, "DR - Console Deposit Ramfi1e Command"
|0613|2540|
|0613|2541|;Here for an DR "Deposit Ramfile" command
|0613|2542|
|0613|2543|.IF/FTFCSL
000,000,0,04,10,1,00,0,00,0,0,00,00,00,00,00,0,12,0,1,1,01,01,00,1115,00,7,00,0,0,0,0614|2544|DR CMD: ZERO_[W1], ;No int recovery
|0614|2545| CALL [GET EXM ADR],#0_UC ;Get adr to examine
000,000,0,14,06,1,33,0,00,0,0,00,00,00,00,03,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,0615|2546| [PMA]_Y,Y_RAMFILE ADR
000,000,0,14,14,0,77,0,44,0,0,00,00,00,00,00,0,20,1,1,1,03,01,00,0511,00,7,04,0,0,0,0616|2547|DRC 3: [MB]_RAMFILE, ; Deposit ramfile
|0616|2548| GOTO [CMD PRSE8]
|0616|2549|
|0616|2550|.TOC 2, "ER - Console Examine Ramfile Command"
|0616|2551|
|0616|2552|;Here for an ER command
000,000,0,04,10,1,00,0,00,0,0,00,00,00,00,00,0,13,0,1,1,01,01,00,1115,00,7,00,0,0,0,0617|2553|ER CMD: ZERO_[W1], ;No int recovery
|0617|2554| CALL [GET EXM ADR],#1_UC ;Get adr to examine
000,000,0,14,06,1,33,0,00,0,0,00,00,00,00,03,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,0618|2555| [PMA]_Y,Y_RAMFILE ADR ;Address ramfile
000,000,0,04,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,0533,00,7,04,0,0,0,0619|2556| RAMFILE_[W1],
|0619|2557| CALL [PUT CMR NUM]
|0619|2558| GOTO [CMD PRSE8]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,03,01,00,0511,00,7,00,0,0,0,0620|2559|.ENDIF/FTFCSL
|0620|2560|
|0620|2561|.TOC 2, "DV - Console Deposit Virtual Command"
|0620|2562|
|0620|2563|;Here for an DV "Deposit Virtual" command
|0620|2564|.IF/FTFCSL
000,000,0,04,10,1,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,15,01,00,1157,00,7,01,0,0,0,0621|2565|DV CMD: J[DV CMD RCOVR]_[W1],POP ;Recovery routine for ints
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,12,0,1,0,01,01,00,1115,00,7,00,0,0,0,0622|2566| CALL [GET EXM ADR],#0_UC ;Get adr to examine
000,000,0,14,10,0,00,0,00,0,0,00,10,00,00,00,0,20,1,1,0,01,01,00,4711,00,7,00,0,0,0,0623|2567|DV CMD RCOVR:
|0623|2568| SET GLOBAL,CALL [MEMORY WRITE] ;Write virtual
|0623|2569| GOTO [CMD PRSE8]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,03,01,00,0511,00,7,00,0,0,0,0624|2570|
|0624|2571|.TOC 2, "EV - Console Examine Virtual Command"
|0624|2572|
|0624|2573|;Here for an EV command
000,000,0,04,10,1,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,1163,00,7,01,0,0,0,0625|2574|EV CMD: J[EV CMD RCOVR]_[W1] ;Recovery routine for ints
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,13,0,1,0,01,01,00,1115,00,7,00,0,0,0,0626|2575| CALL [GET EXM ADR],#1_UC ;Get adr to examine
000,000,0,14,10,0,00,0,00,0,0,00,10,00,00,00,0,20,1,1,0,01,01,00,4662,00,7,00,0,0,0,0627|2576|EV CMD RCOVR:
|0627|2577| SET GLOBAL,CALL [MEM READ 0] ;Read virtual
|0627|2578| GOTO [EC 3] ;Rest like E cmd
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,03,01,00,1113,00,7,00,0,0,0,0628|2579|.ENDIF/FTFCSL
|0628|2580|
|0628|2581|.TOC 2, " H - Console Halt Command"
|0628|2582|
|0628|2583|;Here for a HALT cOMMand
|0628|2584|
000,000,0,04,10,1,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0002,00,7,01,0,0,0,0629|2585|H CMD: ;IF [NOT RUN] THEN [CMDERR NWR] ;This is silly if not running
|0629|2586| J[HALT CONSOLE]_[W1] ;Stopped because told to
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,03,0,20,1,1,0,16,00,00,0151,00,7,01,0,0,0,0630|2587|SET HALT CODE:
|0630|2588| J[HALT CODE]_RAMFILE ADR
000,000,0,14,06,1,66,0,00,0,0,00,00,00,72,00,0,20,1,1,1,13,43,00,1310,00,7,00,0,0,0,0631|2589| [K 77]_Y,Y_2914 MASK, ;Stop interrupts
|0631|2590| IF [NOT RUN] THENP [WRITE HSB]
000,000,0,14,14,0,77,0,00,0,0,00,40,00,00,00,0,20,1,1,1,13,01,00,1310,00,7,04,0,0,0,0632|2591| [W1]_RAMFILE,CLEAR RUN, ;Save code and go type result
|0632|2592| GOTOP [WRITE HSB]
|0632|2593|
|0632|2594|.TOC 2, " I - Console Initialize Command"
|0632|2595|
|0632|2596|;Here for a Initialize command
|0632|2597|
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,03,42,00,0470,00,7,00,0,0,0,0633|2598|I CMD: IF [RUN] THEN [CMDERR NWR]
|0633|2599| CALL [SYS RESET]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,1174,00,7,00,0,0,0,0634|2600| GOTO [CMD PRSE8]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,03,01,00,0511,00,7,00,0,0,0,0635|2601|
000,000,0,04,10,1,00,0,03,0,0,00,20,00,00,00,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,0636|2602|SYS RESET:
|0636|2603| ZERO_[PC FLAGS],CLEAR USER ;Initialize register
000,000,0,04,10,1,00,0,17,0,0,00,30,00,00,00,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,0637|2604| ZERO_[EPT],CLEAR PAGED ;Initialize register
000,000,0,04,10,1,00,0,23,0,0,00,14,00,00,00,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,0638|2605| ZERO_[UPT],SET LOCAL ;Initialize register
000,000,0,04,10,1,00,0,27,0,0,00,60,00,00,00,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,0639|2606| ZERO_[SPT],CLEAR PXCT ;Initialize register
|0639|2607|
|0639|2608|;Set up PROC REG
|0639|2609| J[#33B MASK]_RAMFILE ADR ;Want high order 3 bits on
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,03,0,20,1,1,0,16,00,00,0041,00,7,01,0,0,0,0640|2610|.IF/FT10PAG
000,000,0,04,10,0,00,0,00,0,0,00,50,00,00,00,0,20,1,1,0,16,00,00,0000,00,7,04,0,0,0,0641|2611| RAMFILE_[W1],CLEAR TOPS20
|0641|2612|.ENDIF/FT10PAG
|0641|2613|.IFNOT/FT10PAG
|0641|2614| RAMILE_[W1],SET TOPS20
|0641|2615|.IFNOT/FT20PAG
|0641|2616|.ERROR 2, "FT10PAG=0 and FT20PAG=0. Need to enable one or the other"
|0641|2617|.ENDIF/FT20PAG
|0641|2618|.ENDIF/FT10PAG
000,000,0,04,07,0,02,0,00,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0200,00,7,01,0,0,0,0642|2619| FJ[0200]_[W1], ; Line PI level
|0642|2620| COMPLEMENT [W1]_F ; 700000,,200
|0642|2621| J[PROC REG]_RAMFILE ADR ;Address ramfile copy of proc reg
000,000,0,14,14,0,77,0,00,0,0,00,70,00,00,00,0,20,1,1,1,01,01,00,3210,00,7,04,0,0,0,0644|2622| [W1]_RAMFILE,CLEAR TRAP,
|0644|2623| CALL [RESET PI]
|0644|2624| GOTO [RESET IO] ;Perform an IO reset
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,03,01,00,3117,00,7,00,0,0,0,0645|2625|
|0645|2626|.TOC 2, " R - Console Repeat Command"
|0645|2627|
|0645|2628|;Here for a REPEAT command
|0645|2629|
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,0520,00,7,00,0,0,0,0646|2630|REPEAT: CALL [GET CMD NUM] ;Get repeat count
|0646|2631| J[CMDRPT]_RAMFILE ADR ;Address repeat counter
000,000,0,06,07,1,02,0,00,0,1,00,00,00,00,00,0,20,1,0,1,01,01,00,1216,00,7,00,0,0,0,0648|2632| NEGATE [W1]_F,F_Q_Y,IX_MX,
|0648|2633| CALL [RAMFILE_W1] ;Get current value for counter
000,000,0,14,06,1,02,0,00,0,1,00,00,00,00,00,0,64,0,1,1,03,02,00,0511,00,7,04,0,0,0,0649|2634| [W1]+1_Y,ALU_RAMFILE, ;Update repeat counter
|0649|2635| IF CT [IZ IX_MX] THEN [CMD PRSE8]
000,000,0,14,06,1,02,0,00,0,0,00,00,00,00,00,0,76,1,1,1,03,02,00,1214,00,7,00,0,0,0,0650|2636| [W1]_Y,
|0650|2637| IF CT [IN] THEN [REPEAT 3]
000,000,0,14,14,1,77,0,00,0,0,00,00,00,00,00,0,20,1,1,1,16,00,00,0000,00,7,04,0,0,0,0651|2638| Q_Y,ALU_RAMFILE ;Reseed repeat counter
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,0663,00,7,00,0,0,0,0652|2639|REPEAT 3:
|0652|2640| CALL [ENABLE PARSE]
|0652|2641| GOTO [CMD PRSE8]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,03,01,00,0511,00,7,00,0,0,0,0653|2642|
000,000,0,04,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,12,01,00,0000,00,7,04,0,0,0,0654|2643|RAMFILE_W1:
|0654|2644| RAMFILE_[W1],
|0654|2645| RETURN
|0654|2646|
|0654|2647|.TOC 2, " S - Console Start Command"
|0654|2648|
|0654|2649|;Here for a START command
|0654|2650|
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,03,42,00,0470,00,7,00,0,0,0,0655|2651|S CMD: IF [RUN] THEN [CMDERR NWR]
|0655|2652| CALL [SYS RESET] ;Reset lots of things
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,1174,00,7,00,0,0,0,0656|2653| GOTO [C CMD] ;Rest is like a C command
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,03,01,00,1050,00,7,00,0,0,0,0657|2654|
|0657|2655|.TOC 2, "SH - Console Shut Down Command"
|0657|2656|
000,000,0,04,10,1,00,0,33,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0030,00,7,01,0,0,0,0658|2657|SH CMD: J[030]_[PMA]
000,000,0,04,00,1,00,0,44,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,4704,00,7,00,0,0,0,0659|2658| ONES_[MB], ;Write -1 in location 30
|0659|2659| CALL [UNMAPPED WRITE]
|0659|2660| GOTO [CMD PRSE8]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,03,01,00,0511,00,7,00,0,0,0,0660|2661|
|0660|2662|.TOC 2, "SI - Console Single Instruction Command"
|0660|2663|
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,03,42,00,0470,00,7,00,0,0,0,0661|2664|SI CMD: IF [RUN] THEN [CMDERR NWR]
000,000,0,14,10,0,00,0,00,0,0,00,14,00,00,00,0,20,1,1,0,01,01,00,1057,00,7,00,0,0,0,0662|2665| SET LOCAL,CALL [GET CMD PC] ;Try to pick up a PC
000,000,0,04,10,1,00,0,00,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,5016,00,7,00,0,0,0,0663|2666| ZERO_[W1], ;Memory errs & page fails
|0663|2667| CALL [SET PF ME RCOVR] ; are usual
|0663|2668| J[HALT CODE]_RAMFILE ADR ;Address halt code
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,03,0,20,1,1,0,16,00,00,0151,00,7,01,0,0,0,0664|2669| J[HALT SI]_[W2] ;Single instruction halt
000,000,0,04,10,1,00,0,04,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0003,00,7,01,0,0,0,0665|2670| J[SI I RCOVR]_[W1]
000,000,0,14,14,0,77,0,04,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,1240,00,7,04,0,0,0,0667|2671| [W2]_RAMFILE, ;Set Halt code
|0667|2672| CALL [SET INT RCOVR]
|0667|2673| CALL [SET PI MASK] ;Allow interrupts
000,000,0,04,10,1,00,0,00,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,5016,00,7,00,0,0,0,0669|2674| ZERO_[W1], ;Normal recovery for
|0669|2675| CALL [SET PF ME RCOVR] ; for mem errs & page fails
000,000,0,07,06,1,36,0,40,0,0,00,00,00,00,77,0,20,1,1,1,13,01,00,1423,00,7,00,0,0,0,0670|2676|SI RCOVR:
|0670|2677| [PC]_Q_[E], ;Put PC in ram address & Q
|0670|2678| SPEC SEL/PAGE TABLE ENTRY,
|0670|2679| GOTOP [IFETCH 0]
|0670|2680|
|0670|2681|;Here if got interrupted out of SI cmd
000,000,0,04,03,0,77,0,36,0,0,00,00,00,00,00,0,20,1,1,1,03,01,00,1236,00,7,00,0,0,0,0671|2682|SI I RCOVR:
|0671|2683| [K -1]+[PC RH]_B, ;Backup PC
|0671|2684| GOTO [SI RCOVR]
|0671|2685|
|0671|2686|;Here to set exit for interrupt service
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,03,0,20,1,1,0,16,00,00,0163,00,7,01,0,0,0,0672|2687|SET INT RCOVR:
|0672|2688| J[INT RCOVR]_RAMFILE ADR ;Address ramfile
000,000,0,14,14,0,77,0,00,0,0,00,00,00,00,00,0,20,1,1,1,12,01,00,0000,00,7,04,0,0,0,0673|2689| [W1]_RAMFILE,RETURN
|0673|2690|
|0673|2691|.TOC 2, "SM - Console Start u-code Command"
|0673|2692|;Here for a START u-CODE command
|0673|2693|
|0673|2694|.IF/FTSM
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,0520,00,7,00,0,0,0,0674|2695|SM CMD: CALL [GET CMD NUM]
000,000,0,14,06,1,02,0,00,0,0,00,00,00,00,00,0,20,1,1,1,03,01,00,0000,00,7,01,0,0,0,0675|2696| [W1]_Y,GOTO Y ;Go whither he asketh
|0675|2697|.ENDIF/FTSH
|0675|2698|
|0675|2699|
|0675|2700|.TOC 2, " T - Console Self Test Command"
|0675|2701|
|0675|2702|;Here for a SELF TEST command
|0675|2703|
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,03,42,00,0470,00,7,00,0,0,0,0676|2704|T CMD: IF [RUN] THEN [CMDERR NWR]
|0676|2705| GOTO [TEST]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,03,01,00,0004,00,7,00,0,0,0,0677|2706|
|0677|2707|;Here to write [W1] into Ramfile location Q+1
000,000,0,06,06,1,00,0,00,0,1,00,00,00,00,03,0,20,1,1,1,03,01,00,5020,00,7,00,0,0,0,0678|2708|RF WRITE:
|0678|2709| Q+1_F,F_Q_Y,Y_RAMFILE ADR, ;Point Ramfile at right location
|0678|2710| GOTO [W1_RAMFILE] ;Write Ramfile
|0678|2711|
|0678|2712|.IF/FTDIAG
|0678|2713|;Here to load LEGAL SECTION, SECTION 0, AC REF, CONTEXT MATCH in W1
|0678|2714|; Call with expected page table data in W2, expected latches in W3
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,1266,00,7,00,0,0,0,0679|2715|RDPG LATCHES:
|0679|2716|
|0679|2717| CALL [TVR XX] ;Check data expected is obtained
000,000,0,04,10,1,00,0,00,0,0,00,00,00,00,00,0,20,1,1,1,01,24,00,1263,00,7,00,0,0,0,0680|2718| ZERO_[W1],
|0680|2719| IF [LEGAL SECTION] CALL [W1+1_W1]
000,000,1,11,06,1,02,0,00,0,0,00,00,11,00,00,0,20,1,1,1,01,27,00,1263,00,7,00,0,0,0,0681|2720| #2*[W1]_[W1],
|0681|2721| IF [SECTION 0] CALL [W1+1_W1]
000,000,1,11,06,1,02,0,00,0,0,00,00,11,00,00,0,20,1,1,1,01,23,00,1263,00,7,00,0,0,0,0682|2722| #2*[W1]_[W1],
|0682|2723| IF [AC REF] CALL [W1+1_W1]
000,000,1,11,06,1,02,0,00,0,0,00,00,11,00,00,0,20,1,1,1,01,30,00,1263,00,7,00,0,0,0,0683|2724| #2*[W1]_[W1],
|0683|2725| IF [CONTEXT MATCH] CALL [W1+1_W1]
000,000,0,14,13,0,02,0,10,0,0,00,00,00,00,00,0,64,1,1,1,12,02,00,0000,00,7,00,0,0,0,0684|2726| [W1].XOR.[W3]_Y,
|0684|2727| IF CT [IZ] RETURN
000,000,0,04,06,1,12,0,04,0,0,00,00,00,00,00,0,20,1,1,1,03,01,00,1306,00,7,00,0,0,0,0685|2728| [W3]_[W2],
|0685|2729| GOTO [ALU BROKE]
|0685|2730|
000,000,0,14,10,0,00,0,00,0,0,00,54,00,00,00,0,20,1,1,0,12,01,00,0000,00,7,00,0,0,0,0686|2731|SET TOPS20 LATCH:
|0686|2732| SET TOPS20,RETURN
000,000,0,14,10,0,00,0,00,0,0,00,74,00,00,00,0,20,1,1,0,12,01,00,0000,00,7,00,0,0,0,0687|2733|SET TRAP LATCH:
|0687|2734| SET TRAP,RETURN
000,000,0,14,10,0,00,0,00,0,0,00,64,00,00,00,0,20,1,1,0,12,01,00,0000,00,7,00,0,0,0,0688|2735|SET PXCT LATCH:
|0688|2736| SET PXCT,RETURN
000,000,0,14,10,0,00,0,00,0,0,00,44,00,00,00,0,20,1,1,0,12,01,00,0000,00,7,00,0,0,0,0689|2737|SET RUN LATCH:
|0689|2738| SET RUN,RETURN
000,000,0,14,10,0,00,0,00,0,0,00,14,00,00,00,0,20,1,1,0,12,01,00,0000,00,7,00,0,0,0,0690|2739|SET LOCAL LATCH:
|0690|2740| SET LOCAL,RETURN
|0690|2741|
000,000,0,04,06,1,02,0,00,0,1,00,00,00,00,00,0,20,1,1,1,12,01,00,0000,00,7,00,0,0,0,0691|2742|W1+1_W1:
|0691|2743| [W1]+1_[W1], ;Flag is set
|0691|2744| RETURN
|0691|2745|
|0691|2746|;Here to initialize Q with first ramfile adr
000,000,0,04,10,1,00,0,00,0,0,00,00,00,00,03,0,20,1,1,0,16,00,00,1777,00,7,01,0,0,0,0692|2747|TVR X0: J[01777]_[W1],Y_RAMFILE ADR ;Highest adr in Ramfile
000,000,0,06,06,1,02,0,00,0,0,00,00,00,00,00,0,20,1,1,0,12,01,00,0000,00,7,00,0,0,0,0693|2748| [W1]_Q,RETURN
|0693|2749|
|0693|2750|;Here to verify ramfile contents are correct
000,000,0,04,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,0,0,16,00,00,0000,00,7,04,0,0,0,0694|2751|TVR XX: RAMFILE_[W1],
|0694|2752| IX_MX
000,000,0,14,13,0,02,0,04,0,0,00,00,00,00,00,0,64,1,1,1,12,02,00,0000,00,7,00,0,0,0,0695|2753|TVR XY: [W1].XOR.[W2]_Y,
|0695|2754| IF CT [IZ] RETURN
|0695|2755| GOTO [RF BROKE]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,03,01,00,1306,00,7,00,0,0,0,0696|2756|.ENDIF/FTDIAG
|0696|2757|
|0696|2758|.TOC 2, "ZM - Console Zero memory Command"
|0696|2759|
|0696|2760|;Here for a Zero Kemory command
|0696|2761|.IF/FTZM
000,000,0,04,10,1,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,1301,00,7,01,0,0,0,0697|2762|ZM CMD: J[ZMC 5]_[W1] ;Routine for memory errors
000,000,0,04,10,1,00,0,44,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,5016,00,7,00,0,0,0,0698|2763| ZERO_[MB],
|0698|2764| CALL [SET PF ME RCOVR]
|0698|2765| [K -1]_[PMA]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,03,0,20,1,1,0,16,00,00,0445,00,7,01,0,0,0,0700|2766|ZM 10: J[EXM ADR]_RAMFILE ADR
000,000,0,04,06,1,33,0,33,0,1,00,00,00,00,00,0,20,1,1,1,01,01,00,4704,00,7,04,0,0,0,0701|2767| [PMA]+1_[PMA],ALU_RAMFILE,
|0701|2768| CALL [UNMAPPED WRITE]
000,000,0,04,06,1,33,0,33,0,0,00,00,05,00,00,0,20,1,1,1,01,01,00,4573,00,1,02,0,0,0,0702|2769| [PMA]_[PMA],MEM START READ,
|0702|2770| CALL [UNMAPPED READ]
000,000,0,14,06,1,46,0,00,0,0,00,00,00,00,00,0,64,1,1,1,03,02,00,1274,00,7,00,0,0,0,0703|2771| [MB]_Y,IF CT [IZ] THEN [ZM 10]
|0703|2772| GOTO [CMDERR MER]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,03,01,00,0477,00,7,00,0,0,0,0704|2773|
000,000,0,06,14,0,76,0,00,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0000,00,7,00,0,0,0,0705|2774|ZMC 5: [K -1.0]&[W1]_Q ;Get only code
000,000,0,14,13,1,57,0,00,0,0,00,00,00,00,00,0,64,1,1,1,03,02,00,0511,00,7,00,0,0,0,0706|2775| Q.XOR.[BIT17]_F,F_Y,
|0706|2776| IF CT [IZ] THEN [CMD PRSE8]
|0706|2777| GOTO [CMDERR MER]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,03,01,00,0477,00,7,00,0,0,0,0707|2778|.ENDIF/FTZM
|0707|2779|
|0707|2780|;Here on incorrect u-code dispatch
000,000,0,04,10,1,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,1000,00,7,01,0,0,0,0708|2781|MCE: ;GOTO [U-CODE ERR]
|0708|2782|
|0708|2783|;Here on a horrible u-code problem
|0708|2784|U-CODE ERR:
|0708|2785| J[HALT DSP]_[W1] ;Illegal u-code dispatch
|0708|2786| GOTOP [SET HALT CODE]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,13,01,00,1166,00,7,00,0,0,0,0709|2787|
|0709|2788|;Here if the ALU is broken
000,000,0,06,06,1,62,0,00,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0000,00,7,00,0,0,0,0710|2789|ALU BROKE:
|0710|2790|;Here if the Ramfile (or addressing logic) is broken
|0710|2791|; Bad data in W1, good data in W2, test I on Y bus
|0710|2792|RF BROKE:
|0710|2793| [PXCT]_Q ;Test code
|0710|2794|
|0710|2795|; W1 on A bus, W2 on B bus, test # on Y bus
000,000,0,14,06,1,02,0,04,0,0,00,00,00,00,00,0,20,1,1,1,03,01,00,1307,00,7,00,0,0,0,0711|2796|BROKE9: R SEL/W1,B SEL/W2,#0_CO,Q+C_F,F_Y,
|0711|2797| GOTO [BROKE9]
|0711|2798|
|0711|2799|
|0711|2800|.TOC "Write Halt Status Block"
|0711|2801|
|0711|2802|;Here when ISP code halts
000,000,0,14,06,1,66,0,00,0,0,00,00,00,72,00,0,20,1,1,1,15,01,00,0000,00,7,00,0,0,0,0712|2803|WRITE HSB:
|0712|2804| [K 77]_Y,Y_2914 MASK,POP ;Disallow interrupts
000,000,0,04,14,0,67,0,34,0,0,00,00,00,00,00,0,20,1,1,1,15,01,00,0000,00,7,00,0,0,0,0713|2805| [K 7777.-1]&[PC]_B,POP ;Mask PC to 30 bits
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,03,0,20,1,1,0,15,01,00,0555,00,7,01,0,0,0,0714|2806| J[HSB PMA]_RAMFILE ADR,POP ;Save PMA here
000,000,0,14,14,0,77,0,33,0,0,00,00,00,00,00,0,20,1,1,1,15,01,00,0000,00,7,04,0,0,0,0715|2807| [PMA]_RAMFILE,POP ;Save PMA
|0715|2808| J[HSB]_RAMFILE ADR ;Get adr of Halt Status Block
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,03,0,20,1,1,0,16,00,00,0553,00,7,01,0,0,0,0716|2809|.IF/FTCRAM
|0716|2810| RAMFILE_[PMA].NRFRD/1
|0716|2811| [PMA]_[PMA], ;Let latches go
|0716|2812| IF CT [IZ] THEN [WHSB2] ;No block = do not write
|0716|2813|.ENDIF/FTCRAM
|0716|2814|.IFNOT/FTCRAM
000,000,0,04,10,0,00,0,33,0,0,00,00,00,00,00,0,64,1,1,0,03,02,00,1401,00,7,04,0,0,0,0717|2815| RAMFILE_[PMA],
|0717|2816| IF CT [IZ] THEN [WHSB2] ;No block = do not write
|0717|2817|.ENDIF/FTCRAM
|0717|2818| J[HSB MB]_RAMFILE ADR ;Save MB here
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,03,0,20,1,1,0,16,00,00,0554,00,7,01,0,0,0,0718|2819| J[HSB MER]_[W1] ;Recovery in case of memory errs
000,000,0,14,14,0,77,0,44,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,5021,00,7,04,0,0,0,0720|2820| [MB]_RAMFILE,
|0720|2821| CALL [SET MER]
000,000,0,04,10,1,00,0,00,0,0,00,00,00,00,00,0,20,1,1,1,01,34,00,1263,00,7,00,0,0,0,0721|2822| ZERO_[W1], IF [LOCAL] CALL [W1+1_W1]
000,000,1,11,06,1,02,0,00,0,0,00,00,11,00,00,0,20,1,1,1,01,36,00,1263,00,7,00,0,0,0,0722|2823| #2*[W1]_[W1],IF [USER] CALL [W1+1_W1]
000,000,1,11,06,1,02,0,00,0,0,00,00,11,00,00,0,20,1,1,1,01,40,00,1263,00,7,00,0,0,0,0723|2824| #2*[W1]_[W1],IF [PAGED] CALL [W1+1_W1]
000,000,1,11,06,1,02,0,00,0,0,00,00,11,00,00,0,20,1,1,1,01,42,00,1263,00,7,00,0,0,0,0724|2825| #2*[W1]_[W1],IF [RUN] CALL [W1+1_W1]
000,000,1,11,06,1,02,0,00,0,0,00,00,11,00,00,0,20,1,1,1,01,44,00,1263,00,7,00,0,0,0,0725|2826| #2*[W1]_[W1],IF [TOPS20] CALL [W1+1_W1]
000,000,1,11,06,1,02,0,00,0,0,00,00,11,00,00,0,20,1,1,1,01,46,00,1263,00,7,00,0,0,0,0726|2827| #2*[W1]_[W1],IF [PXCT] CALL [W1+1_W1]
000,000,1,11,06,1,02,0,00,0,0,00,00,11,00,00,0,20,1,1,1,01,66,00,1263,00,7,00,0,0,0,0727|2828| #2*[W1]_[W1],IF [TRAP] CALL [W1+1_W1]
000,000,0,04,06,1,02,0,44,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,4704,00,7,00,0,0,0,0728|2829| [W1]_[MB],CALL [UNMAPPED WRITE]
000,000,0,04,06,1,06,0,44,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,4703,00,7,00,0,0,0,0729|2830| [W2]_[MB],CALL [UNMAPPED WRITE NEXT]
000,000,0,04,06,1,12,0,44,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,4703,00,7,00,0,0,0,0730|2831| [W3]_[MB],CALL [UNMAPPED WRITE NEXT]
000,000,0,04,06,1,16,0,44,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,4703,00,7,00,0,0,0,0731|2832| [W4]_[MB],CALL [UNMAPPED WRITE NEXT]
000,000,0,04,06,1,22,0,44,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,4703,00,7,00,0,0,0,0732|2833| [W5]_[MB],CALL [UNMAPPED WRITE NEXT]
000,000,0,04,06,1,26,0,44,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,4703,00,7,00,0,0,0,0733|2834| [W6]_[MB],CALL [UNMAPPED WRITE NEXT]
000,000,0,04,06,1,32,0,44,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,4703,00,7,00,0,0,0,0734|2835| [IR]_[MB],CALL [UNMAPPED WRITE NEXT]
000,000,0,04,06,1,36,0,44,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,4703,00,7,00,0,0,0,0735|2836| [PC]_[MB],CALL [UNMAPPED WRITE NEXT]
|0735|2837|
000,000,0,04,06,1,42,0,44,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,4703,00,7,00,0,0,0,0736|2838| [E]_[MB],CALL [UNMAPPED WRITE NEXT]
|0736|2839| J[HSB MB]_RAMFILE ADR ;Get saved MB
000,000,0,04,10,0,00,0,44,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,4703,00,7,04,0,0,0,0738|2840| RAMFILE_[MB],CALL [UNMAPPED WRITE NEXT]
000,000,0,04,06,1,52,0,44,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,4703,00,7,00,0,0,0,0739|2841| [AC-OP]_[MB],CALL [UNMAPPED WRITE NEXT]
000,000,0,04,06,1,56,0,44,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,4703,00,7,00,0,0,0,0740|2842| [MEM-OP]_[MB],CALL [UNMAPPED WRITE NEXT]
000,000,0,04,06,1,62,0,44,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,4703,00,7,00,0,0,0,0741|2843| [PXCT]_[MB],CALL [UNMAPPED WRITE NEXT]
000,000,0,04,06,1,66,0,44,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,4703,00,7,00,0,0,0,0742|2844| [K 77]_[MB],CALL [UNMAPPED WRITE NEXT]
000,000,0,04,06,1,72,0,44,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,4703,00,7,00,0,0,0,0743|2845| [K 777]_[MB],CALL [UNMAPPED WRITE NEXT]
000,000,0,04,06,1,76,0,44,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,4703,00,7,00,0,0,0,0744|2846| [K -1.0]_[MB],CALL [UNMAPPED WRITE NEXT]
000,000,0,04,06,1,03,0,44,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,4703,00,7,00,0,0,0,0745|2847| [PC FLAGS]_[MB],CALL [UNMAPPED WRITE NEXT]
000,000,0,04,06,1,07,0,44,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,4703,00,7,00,0,0,0,0746|2848| [AC-OP+1]_[MB],CALL [UNMAPPED WRITE NEXT]
000,000,0,04,06,1,13,0,44,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,4703,00,7,00,0,0,0,0747|2849| [MEM-OP+1]_[MB],CALL [UNMAPPED WRITE NEXT]
000,000,0,04,06,1,17,0,44,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,4703,00,7,00,0,0,0,0748|2850| [EPT]_[MB],CALL [UNMAPPED WRITE NEXT]
000,000,0,04,06,1,23,0,44,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,4703,00,7,00,0,0,0,0749|2851| [UPT]_[MB],CALL [UNMAPPED WRITE NEXT]
000,000,0,04,06,1,27,0,44,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,4703,00,7,00,0,0,0,0750|2852| [SPT]_[MB],CALL [UNMAPPED WRITE NEXT]
|0750|2853| J[HSB PMA]_RAMFILE ADR ;Get saved PMA
000,000,0,04,10,0,00,0,44,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,4703,00,7,04,0,0,0,0752|2854| RAMFILE_[MB],CALL [UNMAPPED WRITE NEXT]
000,000,0,04,06,1,37,0,44,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,4703,00,7,00,0,0,0,0753|2855| [TIME]_[MB],CALL [UNMAPPED WRITE NEXT]
000,000,0,04,06,1,43,0,44,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,4703,00,7,00,0,0,0,0754|2856| [PI REG]_[MB],CALL [UNMAPPED WRITE NEXT]
000,000,0,04,06,1,47,0,44,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,4703,00,7,00,0,0,0,0755|2857| [BIT4]_[MB],CALL [UNMAPPED WRITE NEXT]
000,000,0,04,06,1,53,0,44,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,4703,00,7,00,0,0,0,0756|2858| [BIT12]_[MB],CALL [UNMAPPED WRITE NEXT]
000,000,0,04,06,1,57,0,44,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,4703,00,7,00,0,0,0,0757|2859| [BIT17]_[MB],CALL [UNMAPPED WRITE NEXT]
000,000,0,04,06,1,63,0,44,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,4703,00,7,00,0,0,0,0758|2860| [C0!C1]_[MB],CALL [UNMAPPED WRITE NEXT]
000,000,0,04,06,1,67,0,44,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,4703,00,7,00,0,0,0,0759|2861| [K 7777.-1]_[MB],CALL [UNMAPPED WRITE NEXT]
000,000,0,04,06,1,73,0,44,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,4703,00,7,00,0,0,0,0760|2862| [K 407777.0]_[MB],CALL [UNMAPPED WRITE NEXT]
000,000,0,04,06,1,77,0,44,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,4703,00,7,00,0,0,0,0761|2863| [K -1]_[MB],CALL [UNMAPPED WRITE NEXT]
000,000,0,04,10,1,00,0,20,0,0,00,00,00,00,03,0,20,1,1,0,16,00,00,0151,00,7,01,0,0,0,0762|2864| J[HALT CODE]_[W5], ;Address halt code in ramfile
|0762|2865| Y_RAMFILE ADR
|0762|2866| J[9.]_[W6] ;Also want 9 more locations
000,000,0,04,10,0,00,0,44,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,4703,00,7,04,0,0,0,0764|2867| RAMFILE_[MB],
|0764|2868| CALL [UNMAPPED WRITE NEXT]
000,000,0,04,06,1,22,0,20,0,1,00,00,00,00,03,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,0765|2869|WHSB1: [W5]+1_[W5],Y_RAMFILE ADR ;Next ramfile location
|0765|2870| RAMFILE_[MB]
000,000,0,14,10,1,00,0,00,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,4703,00,7,04,0,0,0,0767|2871| ZERO_Y,ALU_RAMFILE,
|0767|2872| CALL [UNMAPPED WRITE NEXT]
000,000,0,04,03,0,77,0,24,0,0,00,00,00,00,00,0,64,1,1,1,03,03,00,1375,00,7,00,0,0,0,0768|2873| [K -1]+[W6]_B,
|0768|2874| IF NOT CT [IZ] THEN [WHSB1]
|0768|2875|
|0768|2876|;Type <CR><LF>?H<halt code> <flags> <PC>
000,000,0,04,10,1,00,0,00,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,1240,00,7,00,0,0,0,0769|2877|WHSB2: ZERO_[W1],CALL [SET INT RCOVR] ;In case was SI cmd
000,000,0,04,06,1,47,0,00,0,0,00,14,00,00,00,0,20,1,1,0,16,00,00,0003,00,7,01,0,0,0,0770|2878| [BIT4]J[F.O!F.S]_[W1], ;(F.USR) Flags to clear
|0770|2879| SET LOCAL
|0770|2880| CALL [CLEAR CMDFLG]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,0743,00,7,00,0,0,0,0771|2881| J[0110]_[W6] ; Ascii "H"
000,000,0,04,10,1,00,0,24,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0110,00,7,01,0,0,0,0772|2882| CALL [PUT ? W6]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,0556,00,7,00,0,0,0,0773|2883| J[HALT CODE]_RAMFILE ADR
000,000,0,04,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,0533,00,7,04,0,0,0,0775|2884| RAMFILE_[W1], ;Get halt code from ramfile
|0775|2885| CALL [PUT CMR NUM] ; and type it
|0775|2886| CALL [PUT CMR SPACE] ;Type a space
000,000,0,04,06,1,03,0,00,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,0540,00,7,00,0,0,0,0777|2887| [PC FLAGS]_[W1], ;Type flags
|0777|2888| CALL [P6DNUM]
|0777|2889| CALL [PUT CMR SPACE]
000,000,0,04,06,1,36,0,00,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,0533,00,7,00,0,0,0,0779|2890| [PC]_[W1],
|0779|2891| CALL [PUT CMR NUM]
|0779|2892| GOTO [CONSOLE PROMPT]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,03,01,00,0341,00,7,00,0,0,0,0780|2893|
|0780|2894|
|0780|2895|;Here in case of memory errors while writing HSB
|0780|2896|
000,000,0,04,10,1,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0005,00,7,01,0,0,0,0781|2897|HSB MER:
|0781|2898| J[HALT HSBMER]_[W1]
|0781|2899| J[HALT CODE]_RAMFILE ADR
000,000,0,14,14,0,77,0,00,0,0,00,00,00,00,00,0,20,1,1,1,03,01,00,1401,00,7,04,0,0,0,0783|2900| [W1]_RAMFILE,
|0783|2901| GOTO [WHSB2]
|0783|2902|
|0783|2903|.TOC "Instruction fetch"
|0783|2904|
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,03,35,00,1304,00,7,00,0,0,0,0784|2905|IFETCH:
|0784|2906|.IF/DEBUG2
|0784|2907| IF [GLOBAL] THEN [U-CODE ERR]
|0784|2908|.ENDIF/DEBUG2
|0784|2909|.IF/SH_N_TL
|0784|2910| CALL [SHOW&TELL]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,0356,00,7,00,0,0,0,0785|2911|.ENDIF/SH_N_TL
000,000,0,07,06,1,36,0,40,0,0,00,00,00,00,77,0,20,1,1,1,13,43,00,1310,00,7,00,0,0,0,0786|2912| [PC]_Q_[E], ;Put PC in ram address & Q
|0786|2913| SPEC SEL/PAGE TABLE ENTRY,
|0786|2914| IF [NOT RUN] THENP [WRITE HSB]
|0786|2915|
000,000,0,04,14,1,72,0,00,0,0,00,60,00,00,00,0,20,1,0,0,13,72,00,1427,00,7,04,0,0,0,0787|2916|IFETCH 0:
|0787|2917| Q&[K 777]_Q RAMFILE_[W1], ;Put on page adr in Q
|0787|2918| CLEAR PXCT,IX_MX, ; Put page entry in W1
|0787|2919| IF [UNPAGED OR AC] THENP [IFETCH 1]
000,000,0,04,17,1,02,0,33,0,0,00,00,05,00,00,0,20,1,1,1,13,30,00,1431,00,1,02,0,0,0,0788|2920| Q.OR.[W1]_[PMA], ;Start memory
|0788|2921| MEM START READ,
|0788|2922| IF [CONTEXT MATCH] THENP [IFETCH 3]
000,000,0,04,06,1,36,0,36,0,1,00,00,00,00,00,0,20,1,1,1,01,01,00,4662,00,7,00,0,0,0,0789|2923|IFETCH 05:
|0789|2924| [PC]+1_[PC RH], ;Increment PC
|0789|2925| CALL [MEM READ 0]
|0789|2926| GOTOP [IFETCH 4]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,13,01,00,1435,00,7,00,0,0,0,0790|2927|
|0790|2928|;Here if not paged or AC REF
000,000,0,04,06,1,42,0,33,0,0,00,00,00,00,23,0,20,1,1,1,13,23,00,1425,00,7,00,0,0,0,0791|2929|IFETCH 1:
|0791|2930| [E]_[PMA],SPEC SEL/VMA, ;Address AC in Ramfile
|0791|2931| IF [AC REF] THENP [IFETCH 05]
000,000,0,04,06,1,42,0,33,0,0,00,00,05,00,00,0,20,1,1,1,16,00,00,0000,00,1,02,0,0,0,0792|2932| [E]_[PMA],MEM START READ ;Start memory
|0792|2933|
|0792|2934|;Here if not paged or paging done
000,000,0,04,06,1,36,0,36,0,1,00,00,00,00,00,0,20,1,1,1,01,21,00,4154,00,0,00,0,0,0,0793|2935|IFETCH 3:
|0793|2936| [PC]+1_[PC RH],MEM HOLD, ; Increment PC
|0793|2937| CHECK INTERRUPTS
000,000,0,04,10,0,00,0,30,0,0,00,00,00,00,33,0,20,1,0,0,16,00,00,0000,00,5,11,0,0,0,0794|2938| MEM_IR_[IR],SPEC SEL/XR ;Read memory into IR
|0794|2939| ; Set XR=0 and @ flops
000,000,0,04,06,1,32,0,42,0,0,00,00,00,00,00,0,20,1,1,1,13,61,00,1436,00,0,00,0,0,0,0795|2940| [IR]_[E RH],MEM HOLD,
|0795|2941| IF [NO BUS ERROR] THENP [IFETCH EFA]
000,000,0,04,03,0,77,0,36,0,0,00,00,00,00,00,0,20,1,1,1,03,01,00,1425,00,7,00,0,0,0,0796|2942| [K -1]+[PC RH]_B, ;Backup the PC
|0796|2943| GOTO [IFETCH 05] ; And try again
|0796|2944|
|0796|2945|;Here on an XCT, PXCT, LUUO
000,000,0,04,06,1,46,0,30,0,0,00,00,00,00,33,0,20,1,1,1,16,00,00,0000,00,7,11,0,0,0,0797|2946|IFETCH 4:
|0797|2947| [MB]_[IR],SPEC SEL/XR, ;Set XR-O and @ flops
|0797|2948| LOAD IR
|0797|2949|
|0797|2950|;Here with SPEC SEL/XR to set XR=O and @ flags
000,000,0,04,06,1,32,0,42,0,0,00,00,00,00,27,0,20,1,1,1,06,12,00,0000,10,7,00,0,0,0,0798|2951|IFETCH EFA:
|0798|2952| [IR]_[E RH],SEL AC+[0] , ;Y rh E rh
|0798|2953| IF [NOT (I OR XR)] D [OPERAND FETCH] ;Dispatch on op code to get operands
000,000,0,14,06,1,32,0,00,0,0,00,00,00,00,33,0,20,1,1,1,01,01,00,1450,00,7,00,0,0,0,0799|2954| [IR]_Y,SPEC SEL/XR, ;Do effective adr calc
|0799|2955| CALL [EFA 2]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,27,0,20,1,1,0,06,01,00,0000,10,7,00,0,0,0,0800|2956| SEL AC+[0],
|0800|2957| DISPATCH [OPERAND FETCH] ;Dispatch on op code to get operands
|0800|2958|
|0800|2959|;Here if instruction being done under PXCT
|0800|2960|
000,000,0,04,10,1,00,0,62,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0400,00,7,01,0,0,0,0801|2961|IFETCH PXCT:
|0801|2962| J[0400]_[PXCT RH] ;PXCT bit for effective adr calc
000,000,0,04,14,0,67,0,40,0,0,00,14,00,00,00,0,20,1,1,1,01,01,00,2432,00,7,00,0,0,0,0802|2963| [K 7777.-1]&[E]_B,SET LOCAL,
|0802|2964| CALL [SET PXCT CTXT] ;Set context
000,000,0,04,06,1,32,0,42,0,0,00,00,00,00,33,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,0803|2965| [IR]_[E RH],SPEC SEL/XR ;Y rh_E rh
|0803|2966| IF [I OR XR] CALL [EFA 2]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,01,13,00,1450,00,7,00,0,0,0,0804|2967| CALL [SET CURRENT CTXT]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,27,0,20,1,1,0,06,01,00,0000,10,7,00,0,0,0,0806|2968| SEL AC+[0], ;Dispatch on op code to get operands
|0806|2969| DISPATCH [OPERAND FETCH]
|0806|2970|
|0806|2971|.TOC "Effective Address Calculation"
|0806|2972|
|0806|2973|;Here to do an effective address calculation
|0806|2974|; Call: x_[MB],SPEC SEL/XR
|0806|2975|; Returns adr in E
|0806|2976|; clobbers W1
000,000,0,04,06,1,46,0,42,0,0,00,14,00,00,00,0,20,1,1,1,12,12,00,0000,00,7,00,0,0,0,0807|2977|EFA CALC:
|0807|2978| [MB]_[E RH],SET LOCAL,
|0807|2979| IF [NOT (I OR XR)] RETURN
|0807|2980|
000,000,0,07,06,1,73,0,00,0,0,00,00,00,00,00,0,20,1,1,0,03,04,00,1462,00,7,04,0,0,0,0808|2981|EFA 2: [K 407777.0]_Q RAMFILE_[W1], ;Get index register
|0808|2982| IF [NOT INDEXED] THEN [FETCH IW]
|0808|2983| RAMFILE_[MB]
000,000,0,14,14,1,02,0,00,0,0,00,00,00,00,00,0,20,1,0,1,03,27,00,1461,00,7,00,0,0,0,0810|2984| Q&[W1]_Y,IX_MX, ;Check section # in IDX
|0810|2985| IF [SECTION 0] THEN [EFA LCL INDEX]
000,000,0,06,11,0,76,0,40,0,0,00,00,00,00,00,0,40,1,1,0,03,02,00,1461,00,7,00,0,0,0,0811|2986| [K -1.0]BAR&[E]_Q, ;Put E rh in Q
|0811|2987| IF CT [(MNxMOVR)!MZ] THEN [EFA LCL INDEX]
000,000,0,04,03,1,02,0,40,0,0,00,10,00,00,00,0,20,1,1,1,03,57,00,1457,00,7,00,0,0,0,0812|2988| Q+[W1]_[E],SET GLOBAL, ;IDX(6-35)+Y(18-35)_E(6-35)
|0812|2989| IF [NOT B BIT 18] THEN [EFA 4]
000,000,0,04,03,0,76,0,40,0,0,00,00,00,00,00,0,20,1,1,1,12,11,00,0000,00,7,00,0,0,0,0813|2990| [K -1.0]+[E]_B, ;Sign extend Y
|0813|2991| IF [NOT INDIRECT] RETURN
|0813|2992| GOTO [FETCH IW]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,12,11,00,0000,00,7,00,0,0,0,0815|2993|EFA 4: IF [NOT INDIRECT] RETURN
|0815|2994| GOTO [FETCH IW]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,03,01,00,1462,00,7,00,0,0,0,0816|2995|
000,000,0,04,03,0,02,0,42,0,0,00,14,00,00,00,0,20,1,1,1,12,11,00,0000,00,7,00,0,0,0,0817|2996|EFA LCL INDEX:
|0817|2997| [W1]+[E RH]_B, ;Y rh+IDX rh_E rh
|0817|2998| SET LOCAL,
|0817|2999| IF [NOT INDIRECT] RETURN
|0817|3000| ;GOTO [FETCH IW]
|0817|3001|
000,000,0,07,06,1,42,0,40,0,0,00,00,00,00,77,0,20,1,1,1,01,01,00,4663,00,7,00,0,0,0,0818|3002|FETCH IW:
|0818|3003| READ [E] ;Fetch indirect word
|0818|3004| ; and SPEC SEL/IW
|0818|3005|.IFNOT/FT20PAG
|0818|3006| GOTO [EFA CALC]
|0818|3007|.ENDIF/FT20PAG
|0818|3008|.IF/FT20PAG
000,000,0,04,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,03,27,00,1447,00,7,04,0,0,0,0819|3009| RAMFILE_[W1], ;Get index register
|0819|3010| IF [SECTION 0] THEN [EFA CALC]
000,000,0,14,10,0,00,0,00,0,0,00,10,00,00,00,0,20,1,1,0,13,14,00,4747,00,7,00,0,0,0,0820|3011| CLEAR LOCAL,
|0820|3012| IF [ILLEGAL IW] THENP [PF X24]
|0820|3013| IF [LOCAL IW] THEN [EFA CALC]
000,000,0,04,06,1,46,0,40,0,0,00,00,00,00,77,0,20,1,1,1,12,12,00,0000,00,7,00,0,0,0,0822|3014| [MB]_[E],
|0822|3015| SPEC SEL/PAGE TABLE ENTRY,
|0822|3016| IF [NOT (I OR XR)] RETURN
000,000,0,06,03,0,46,0,00,0,0,00,00,00,00,00,0,20,1,1,0,03,04,00,1462,00,7,00,0,0,0,0823|3017| [MB]+[W1]_Q, ;XR(6-35)+IW(6-35) Q
|0823|3018| IF [NOT INDEXED] THEN [FETCH IW]
000,000,0,04,14,1,77,0,40,0,0,00,00,00,00,77,0,20,1,1,1,12,11,00,0000,00,7,00,0,0,0,0824|3019| Q_[E],
|0824|3020| SPEC SEL/PAGE TABLE ENTRY,
|0824|3021| IF [NOT INDIRECT] RETURN
|0824|3022| GOTO [FETCH IW]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,03,01,00,1462,00,7,00,0,0,0,0825|3023|.ENDIF/FT20PAG
|0825|3024|
|0825|3025|.TOC "Operand Fetch"
|0825|3026|
|0825|3027|;These routines fetch instruction operands
|0825|3028|; if single operand is put in MEM-OP
|0825|3029|; AC & mem operands are put in AC-OP and MEM-OP
|0825|3030|; IX_MX for MEM-OP
|0825|3031|; IX_UX for AC-OP
|0825|3032|
|0825|3033|;Double AC fetch - AC_MEM-OP, AC+I_MEM-OP+1
000,000,0,04,10,0,00,0,54,0,0,00,00,00,00,27,0,20,1,0,0,16,00,01,0000,00,7,04,0,0,0,0826|3034|DFETCH AC:
|0826|3035| RAMFILE_[MEM-OP], ;Fetch first AC
|0826|3036| IX_MX, ; Latch IZ in MZ
|0826|3037| SEL AC+[1] ; Point RAMFILE at AC+1
000,000,0,04,10,0,00,0,13,0,0,00,00,00,00,27,0,20,1,1,0,06,01,00,0000,11,7,04,0,0,0,0827|3038| RAMFILE_[MEM-OP+1], ;Get 2nd AC from RAMFILE
|0827|3039| SEL AC+[0], ; Repoint RAMFILE at AC
|0827|3040| DISPATCH [INST EXCT]
|0827|3041|
|0827|3042|;Double AC & Mem fetch
000,000,0,04,10,0,00,0,50,0,0,00,00,00,00,27,0,20,1,1,0,16,00,01,0000,00,7,04,0,0,0,0828|3043|DFETCH AC&MEM:
|0828|3044| RAMFILE_[AC-OP], ;Get 1st AC
|0828|3045| SEL AC+[1]
000,000,0,04,10,0,00,0,07,0,0,00,00,00,00,00,0,20,1,1,0,03,01,00,1476,00,7,04,0,0,0,0829|3046| RAMFILE_[AC-OP+1], ;Get 2nd AC
|0829|3047| GOTO [DFETCH MEM]
|0829|3048|
|0829|3049|;Double word fetch from memory
|0829|3050|; Sets MX according to highorder operand
000,000,0,07,14,0,67,0,40,0,0,00,00,00,00,77,0,20,1,1,1,03,46,00,1502,00,7,00,0,0,0,0830|3051|DFETCH MEM:
|0830|3052| [K 7777.-1]&[E]_F,F_Q_B, ;Get 1st operand
|0830|3053| SPEC SEL/PAGE TABLE ENTRY,
|0830|3054| IF [PXCT] THEN [PXCT DFETCH]
|0830|3055| CALL [MEMORY READ]
000,000,0,04,06,1,46,0,54,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,4660,00,7,00,0,0,0,0832|3056| [MB]_[MEM-OP], ;Save 1st operand
|0832|3057| CALL [READ NEXT]
000,000,0,04,06,1,46,0,13,0,0,00,00,00,00,00,0,20,1,1,1,03,01,00,1507,00,7,00,0,0,0,0833|3058| [MB]_[MEM-OP+1], ;We do not need to backup E
|0833|3059| GOTO [DFM 8] ; because noone uses it again
000,000,0,04,10,1,00,0,62,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0200,00,7,01,0,0,0,0834|3060|PXCT DFETCH:
|0834|3061| J[0200]_[PXCT RH] ;Bit for this flavour PXCT
|0834|3062| CALL [SET PXCT CTXT]
000,000,0,07,14,0,67,0,40,0,0,00,00,00,00,77,0,20,1,1,1,01,01,00,4663,00,7,00,0,0,0,0836|3063| [K 7777.-1]&[E]_F,F_Q_B, ;Get 1st operand
|0836|3064| SPEC SEL/PAGE TABLE ENTRY,
|0836|3065| CALL [MEMORY READ]
000,000,0,04,06,1,46,0,54,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,4660,00,7,00,0,0,0,0837|3066| [MB]_[MEM-OP], ;Save 1st operand
|0837|3067| CALL [READ NEXT]
000,000,0,04,06,1,46,0,13,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,2424,00,7,00,0,0,0,0838|3068| [MB]_[MEM-OP+1],
|0838|3069| CALL [SET CURRENT CTXT]
000,000,0,14,06,1,56,0,00,0,0,00,00,00,00,27,0,20,1,0,1,06,01,00,0000,11,7,00,0,0,0,0839|3070|DFM 8: [MEM-OP]_Y,IX_MX,SEL AC+[0], ;Set flags
|0839|3071| DISPATCH [INST EXCT]
|0839|3072|
|0839|3073|;Single AC and memory word fetch
000,000,0,04,10,0,00,0,50,0,0,00,00,00,00,00,0,20,1,1,0,03,01,00,1511,00,7,04,0,0,0,0840|3074|FETCH AC&MEM:
|0840|3075| RAMFILE_[AC-OP], ;Get AC from RAMFILE
|0840|3076| GOTO [FETCH MEM]
|0840|3077|
|0840|3078|;Single word fetch from memory and set MX according to data
000,000,0,07,06,1,42,0,33,0,0,00,00,00,00,77,0,20,1,1,1,01,47,00,4663,00,7,00,0,0,0,0841|3079|FETCH MEM:
|0841|3080| [E]_Q_[PMA], ;Read memory operand if not PXCT
|0841|3081| SPEC SEL/PAGE TABLE ENTRY,
|0841|3082| IF [NOT PXCT] CALL [MEMORY READ]
000,000,0,07,06,1,46,0,54,0,0,00,00,00,00,27,0,20,1,0,1,06,47,00,0000,11,7,00,0,0,0,0842|3083| [MB]_F,F_Q_[MEM-OP], ;Copy to right reg and set flags
|0842|3084| IX_MX,SEL AC+[0],
|0842|3085| IF [NOT PXCT] D [INST EXCT]
|0842|3086| CALL [PXCT FETCH 200] ;Get data
000,000,0,07,06,1,46,0,54,0,0,00,00,00,00,27,0,20,1,0,1,06,01,00,0000,11,7,00,0,0,0,0844|3087| [MB]_F,F_Q_[MEM-OP], ;Copy to right reg and set flags
|0844|3088| IX_MX,SEL AC+[0],
|0844|3089| DISPATCH [INST EXCT]
|0844|3090|
|0844|3091|;Single AC and memory word fetch
000,000,0,04,10,0,00,0,50,0,0,00,00,00,00,00,0,20,1,1,0,03,01,00,1516,00,7,04,0,0,0,0845|3092|FETCH AC&MEM(W):
|0845|3093| RAMFILE_[AC-OP], ;Get AC from RAMFILE
|0845|3094| GOTO [FETCH MEM(W)]
|0845|3095|
|0845|3096|;Single word fetch and verify writable from memory
000,000,0,07,06,1,42,0,40,0,0,00,00,00,00,77,0,20,1,1,1,01,47,00,4663,00,7,00,0,0,0,0846|3097|FETCH MEM(W):
|0846|3098| [E]_Q_[E], ;Read memory operand if not PXCT
|0846|3099| SPEC SEL/PAGE TABLE ENTRY,
|0846|3100| IF [NOT PXCT] CALL [MEMORY READ]
000,000,0,07,06,1,46,0,54,0,0,00,00,00,00,00,0,20,1,0,1,03,47,00,1522,00,7,00,0,0,0,0847|3101| [MB]_F,F_Q_[MEM-OP], ;Copy to right reg and set flags
|0847|3102| IX_MX,
|0847|3103| IF [NOT PXCT] THEN [FM(W) 2]
|0847|3104| CALL [PXCT FETCH 200] ;Fetch data
000,000,0,07,06,1,46,0,54,0,0,00,00,00,00,27,0,20,1,0,1,16,00,00,0000,00,7,00,0,0,0,0849|3105| [MB]_F,F_Q_[MEM-OP], ;Copy to right reg and set flags
|0849|3106| IX_MX, SEL AC+[0]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,27,0,20,1,1,0,06,50,00,0000,11,7,00,0,0,0,0850|3107|FM(W) 2:
|0850|3108| B SEL/W1,SEL AC+[0], ;Check writable from paging ram
|0850|3109| IF [B BIT 3] D [INST EXCT]
|0850|3110| IF [UNPAGED OR AC] D [INST EXCT]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,06,72,00,0000,11,7,00,0,0,0,0851|3111| CALL [M W XX] ;Try to make writable
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,27,0,20,1,1,0,06,01,00,0000,11,7,00,0,0,0,0853|3112| SEL AC+[0],DISPATCH [INST EXCT]
|0853|3113|
|0853|3114|;Single AC fetch and immediate operand
000,000,0,04,10,0,00,0,50,0,0,00,00,00,00,00,0,20,1,1,0,03,01,00,1527,00,7,04,0,0,0,0854|3115|FETCH AC&I:
|0854|3116| RAMFILE_[AC-OP], ;Get AC from ramfile
|0854|3117| GOTO [FETCH I]
|0854|3118|; Immediate mode operation
000,000,0,04,10,0,76,2,54,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0000,00,7,07,0,0,0,0855|3119|FETCH I:
|0855|3120| SWAP [K -1.0]_[MEM-OP] ;Mask for immediate operand
000,000,0,07,14,0,42,0,54,0,0,00,00,00,00,27,0,20,1,0,1,06,01,00,0000,11,7,00,0,0,0,0856|3121| [E]&[MEM-OP]_F,F_Q_B,IX_MX, ;Get immediate operand
|0856|3122| SEL AC+[0],
|0856|3123| DISPATCH [INST EXCT]
|0856|3124|
|0856|3125|;Single AC fetch but do not set Mx flags
000,000,0,04,10,0,00,0,54,0,0,00,00,00,00,00,0,20,1,1,0,06,01,00,0000,11,7,04,0,0,0,0857|3126|FETCH AC:
|0857|3127|.IF/FAST
|0857|3128| RAMFILE_[MEM-OP], ;Get AC from RAMFILE
|0857|3129| DISPATCH [INST EXCT]
|0857|3130|.ENDIF/FAST
|0857|3131|
|0857|3132|;Single AC fetch and set Kx flags
000,000,0,04,10,0,00,0,54,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0000,00,7,04,0,0,0,0858|3133|FETCH AC(MX):
|0858|3134| RAMFILE_[MEM-OP] ;Get AC from RAMFILE
000,000,0,04,06,1,56,0,54,0,0,00,00,00,00,00,0,20,1,0,1,06,01,00,0000,11,7,00,0,0,0,0859|3135| [MEM-OP]_[MEM-OP],IX_MX, ;Set Mx flags
|0859|3136| DISPATCH [INST EXCT]
|0859|3137|
|0859|3138|;Fetch AC and Fetch IO word
|0859|3139|
000,000,0,04,10,0,00,0,50,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0000,00,7,04,0,0,0,0860|3140|FETCH AC&IO:
|0860|3141| RAMFILE_[AC-OP] ;Get AC from RAMFILE
|0860|3142|
|0860|3143|; Fetch IO word
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,1540,00,7,00,0,0,0,0861|3144|FETCH IO:
|0861|3145| CALL [RDIOX] ;Get data
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,27,0,26,1,1,0,06,03,00,0000,12,7,00,0,0,0,0862|3146| SEL AC+[0], ; Repoint RAMFILE at AC
|0862|3147| IF NOT CT [UOVR] D [DISPATCH 3]
|0862|3148| GOTO [IO PF]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,03,01,00,4745,00,7,00,0,0,0,0863|3149|
|0863|3150|;Here to do an IO write
|0863|3151|; returns with UOVR if illegal
000,000,0,04,14,0,67,0,40,0,0,00,00,00,00,00,0,17,0,1,1,01,01,00,1545,00,7,00,0,0,0,0864|3152|RDIOX: [K 7777.-1]&[E]_B,#1_UOVR, ;Strip extraneous bits
|0864|3153| CALL [VAL IO ADR] ;Validate IO address
000,000,0,04,06,1,42,0,33,0,0,00,00,05,00,00,0,56,1,1,1,03,02,00,1562,00,3,02,0,0,0,0865|3154| [E]_[PMA],START IO READ, ;Send IO address
|0865|3155| IF CT [MN] THEN [RDIO TTY]
|0865|3156| IO_[MEM-OP] ;Perform transfer
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,16,0,1,0,12,61,00,0000,00,7,00,0,0,0,0867|3157| #0_UOVR,IF [NO BUS ERROR] RETURN
|0867|3158|.IFNOT/FTCKBP
|0867|3159| IF [NOT MEM EXISTS] THEN [SET UOVR]
|0867|3160| IF [NOT MEM FAULT] RETURN
|0867|3161|.ENDIF/FTCKBP
|0867|3162|;Here to set the u-overflow flag
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,17,0,1,0,12,01,00,0000,00,7,00,0,0,0,0868|3163|SET UOVR:
|0868|3164| #1_UOVR,RETURN ;Set flag and exit
|0868|3165|
|0868|3166|;Here to validate IO address
|0868|3167|; Call with address in E
|0868|3168|; If tty returns IN, address in W6, TTYRCV in W1, 7 in W2
000,000,0,04,10,1,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,7760,00,7,01,0,0,0,0869|3169|VAL IO ADR:
|0869|3170|.IF/FTMBZ
|0869|3171| J[07760]_[W1] ;Build mask for address
000,000,0,04,10,0,02,2,00,0,0,00,00,00,00,00,0,17,0,1,0,16,00,00,0000,00,7,07,0,0,0,0870|3172| SWAP [W1]_[W1],#1_UOVR ;We are checking bits 6-13 of E
000,000,0,14,14,0,02,0,40,0,0,00,00,00,00,00,0,64,1,1,1,13,03,00,1551,00,7,00,0,0,0,0871|3173| [W1]&[E]_Y, ;If nonzero illegal
|0871|3174| IF NOT CT [IZ] THENP [VIA9] ;If illegal POP, POPJ
|0871|3175|.ENDIF/FTMBZ
|0871|3176| J[LNZSW]_[W1] ;First non tty adr
000,000,0,14,02,0,42,0,00,0,0,00,00,00,00,00,0,76,1,0,1,12,03,00,0000,00,7,00,0,0,0,0873|3177|VIA9: [E]-[W1]_Y,
|0873|3178| IF NOT CT [IN IX_MX] RETURN
000,000,0,04,06,1,42,0,24,0,0,00,00,00,00,03,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,0874|3179| [E]_[W6],Y_RAMFILE ADR ;Address ramfile
000,000,0,01,06,1,26,0,10,0,0,00,00,01,00,00,0,20,1,1,1,04,01,00,0001,00,7,00,0,0,0,0875|3180| LRS [W6]_[W3],PUSH J[1]_CTR ;Copy & shift address
000,000,0,01,06,1,12,0,10,0,0,00,00,01,00,00,0,20,1,1,1,10,00,00,0000,00,7,00,0,0,0,0876|3181| LRS [W3]_[W3],RFCT ;Shift right
|0876|3182| J[7]_[W2]
000,000,0,04,10,1,00,0,04,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0007,00,7,01,0,0,0,0877|3183| [W2]BAR&[W6]_B ;Make adr of status word
000,000,0,04,11,0,06,0,24,0,0,00,00,00,00,00,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,0878|3184| [W2]&[W3]_B ;Leave only line number in W3
000,000,0,04,14,0,06,0,10,0,0,00,00,00,00,00,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,0879|3185| SWAP [W3]_[W6 LH]
000,000,0,04,10,1,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,12,01,00,0177,00,7,01,0,0,0,0881|3186| J[TTYRCV BITS]_[W1], ;Min legal address
|0881|3187| RETURN
|0881|3188|
|0881|3189|;Here when reading TTY register
000,000,0,06,02,0,42,0,00,0,1,00,00,00,00,00,0,76,1,0,1,12,02,00,0000,00,7,00,0,0,0,0882|3190|RDIO TTY:
|0882|3191| [E]-[W1]_F,F_Q_Y,
|0882|3192| IF CT [IN IX_MX] RETURN
000,000,0,04,10,0,00,0,54,0,0,00,00,00,00,00,0,44,1,1,0,03,02,00,1577,00,7,04,0,0,0,0883|3193| RAMFILE_[MEM-OP], ;Get data from ramfile
|0883|3194| IF CT [MZ] THEN [RDIOTM]
|0883|3195| #0_UOVR
000,000,0,06,14,0,06,0,24,0,0,00,00,00,00,00,0,64,1,1,1,12,03,00,0000,00,7,00,0,0,0,0885|3196| [W2]&[W6]_F,F_Q_Y, ;Leave only word offset
|0885|3197| IF NOT CT [IZ] RETURN ;If not reading status done
|0885|3198|
|0885|3199|;Here if reading the status register
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,3707,00,7,00,0,0,0,0886|3200|RDIOT0:
|0886|3201| CALL [RD PCI SR]
|0886|3202| J[0300]_[W2] ;Mask for SR7&SR6
000,000,0,04,14,0,06,0,00,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,4027,00,7,00,0,0,0,0888|3203| [W2]&[W1]_B, ;Leave only SR7&SR6
|0888|3204| CALL [SWAP W2_W2]
000,000,0,04,11,0,06,0,54,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,4026,00,7,00,0,0,0,0889|3205| [W2]BAR&[MEM-OP]_B, ;Clear old SR7&SR6
|0889|3206| CALL [SWAP W1_W1]
000,000,0,04,17,0,02,0,54,0,0,00,00,00,00,00,0,20,1,1,1,12,01,00,0000,00,7,00,0,0,0,0890|3207| [W1].OR.[MEM-OP]_B,
|0890|3208| RETURN
|0890|3209|
|0890|3210|.IF/FTTTYF
000,000,0,04,10,0,00,0,54,0,0,00,00,00,00,00,0,16,0,1,0,01,01,00,3416,00,7,04,0,0,0,0891|3211| RAMFILE_[MEM-OP],#0_UOVR, ;Get received char
|0891|3212| CALL [ZERO RAMFILE]
000,000,0,04,11,0,02,0,24,0,0,00,00,00,00,03,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,0892|3213| [W1]BAR&[W6]_B,Y_RAMFILE ADR ;Make adr of line block
000,000,0,04,10,0,00,0,20,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,3665,00,7,04,0,0,0,0893|3214| RAMFILE_[W5], ;Get current status
|0893|3215| CALL [CLR RDN]
|0893|3216| GOTO [SET PROC REG] ;Be sure int flags are correct
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,03,01,00,3225,00,7,00,0,0,0,0894|3217|.ENDIF/FTTTYF
|0894|3218|
|0894|3219|;Here to read TTYRCV BITS
000,000,0,04,10,0,00,0,54,0,0,00,00,00,00,00,0,16,0,1,0,12,01,00,0000,00,7,04,0,0,0,0895|3220|RDIOTM: RAMFILE_[MEM-OP],#0_UOVR,
|0895|3221| RETURN
|0895|3222|
|0895|3223|.TOC "User Instructions"
|0895|3224|
|0895|3225|;Here for LUUOs have already been through CHK PC SECT
|0895|3226|
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,03,27,00,1612,00,7,00,0,0,0,0896|3227|LUUO: IF [SECTION 0] THEN [LUUO0] ;Check PC section
|0896|3228| IF [EXEC] THEN [MUUO]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,03,37,00,1637,00,7,00,0,0,0,0897|3229| J[0420]_[PMA] ;Offset into UPT for LUUO block
000,000,0,04,03,0,23,0,33,0,0,00,00,05,00,00,0,20,1,1,1,01,01,00,4573,00,1,02,0,0,0,0899|3230| [UPT]+[PMA]_B,MEM START READ, ;Location which has block adr
|0899|3231| CALL [UNMAPPED READ]
000,000,0,04,06,1,46,0,33,0,0,00,10,00,00,00,0,20,1,1,1,01,01,00,1625,00,7,00,0,0,0,0900|3232| [MB]_[PMA],SET GLOBAL, ;Save adr in PMA
|0900|3233| CALL [SV UUO STS]
|0900|3234| WRITE [PMA] ;Write flags,code,ac
000,000,0,04,06,1,36,0,44,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,4710,00,7,00,0,0,0,0902|3235| [PC]_[MB],CALL [WRITE NEXT] ;Write 30 bit PC
000,000,0,04,06,1,56,0,44,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,4710,00,7,00,0,0,0,0903|3236| [MEM-OP]_[MB],CALL [WRITE NEXT] ;Write 30 bit E
000,000,0,04,06,1,42,0,40,0,1,00,00,00,00,77,0,20,1,1,1,01,01,00,4663,00,7,00,0,0,0,0904|3237| [E]+1_[E], ;Fetch new PC
|0904|3238| SPEC SEL/PAGE TABLE ENTRY,
|0904|3239| CALL [MEMORY READ]
000,000,0,04,06,1,46,0,34,0,0,00,14,00,00,00,0,20,1,1,1,13,01,00,1420,00,7,00,0,0,0,0905|3240| [MB]_[PC],SET LOCAL,
|0905|3241| GOTOP [IFETCH]
|0905|3242|
|0905|3243|;Here if LUUO is done in section 0
000,000,0,04,10,0,32,2,44,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,1635,00,7,07,0,0,0,0906|3244|LUUO0: SWAP [IR]_[MB], ;Put opcode A in MB rh
|0906|3245| CALL [LUUO 2]
000,000,0,04,10,0,42,2,45,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,1624,00,7,07,0,0,0,0907|3246| SWAP [E]_[MB LH], ;Want E in RH
|0907|3247| CALL [SWAP MB_MB]
|0907|3248| J[040]_[E]
000,000,0,04,06,1,42,0,33,0,0,00,00,00,00,00,0,20,1,1,1,03,37,00,1621,00,7,00,0,0,0,0909|3249| [E]_[PMA],
|0909|3250| IF [EXEC] THEN [LUUOOE]
|0909|3251| WRITE [E] ;Save info
000,000,0,07,06,1,42,0,40,0,1,00,00,00,00,77,0,20,1,1,1,01,01,00,4663,00,7,00,0,0,0,0911|3252| [E]+1_Q_[E], ;Get instruction to execute
|0911|3253| SPEC SEL/PAGE TABLE ENTRY,
|0911|3254| CALL [MEMORY READ]
|0911|3255| GOTOP [IFETCH 4]
000,000,0,04,03,0,17,0,33,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,4704,00,7,00,0,0,0,0913|3256|LUUOOE: [EPT]+[PMA]_B, ;Save opcode and E
|0913|3257| CALL [UNMAPPED WRITE]
000,000,0,04,06,1,33,0,33,0,1,00,00,05,00,00,0,20,1,1,1,01,01,00,4573,00,1,02,0,0,0,0914|3258| [PMA]+1_[PMA],MEM START READ,
|0914|3259| CALL [UNMAPPED READ]
|0914|3260| GOTO [IFETCH 4]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,03,01,00,1435,00,7,00,0,0,0,0915|3261|
000,000,0,04,10,0,46,2,44,0,0,00,00,00,00,00,0,20,1,1,0,12,01,00,0000,00,7,07,0,0,0,0916|3262|SWAP MB_MB:
|0916|3263| SWAP [MB]_[MB], ;Put Opcode in LH
|0916|3264| RETURN
|0916|3265|
|0916|3266|;Here as part of MUUO or LUUO to put [flags t,opcd],[PC]_F, [E] in MB
|0916|3267|; Strips PC to 30 bits, puts E in MEM-OP
000,000,0,04,10,0,32,2,44,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,1635,00,7,07,0,0,0,0917|3268|SV UUO STS:
|0917|3269| SWAP [IR]_[MB], ;Put opcode A in MB rh
|0917|3270| CALL [LUUO 2] ;Put O,,opcode A in MB
|0917|3271| [PC FLAGS]_[MB LH]
000,000,0,04,06,1,03,0,45,0,0,00,00,00,00,00,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,0918|3272| [K 7777.-1]&[PC]_B ;Strip PC to 30 bits
000,000,0,04,06,1,42,0,54,0,0,00,00,00,00,77,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,0920|3273|E_MEM-OP:
|0920|3274| [E]_[MEM-OP],SECTION SELECT ;Preserve RH of AC
000,000,0,04,14,0,67,0,54,0,0,00,00,00,00,00,0,20,1,1,1,12,22,00,0000,00,7,00,0,0,0,0921|3275| [K 7777.-1]&[MEM-OP]_B, ;Strip extraneous bits
|0921|3276| IF [NOT AC REF] RETURN
000,000,0,14,06,1,36,0,00,0,0,00,00,00,00,77,0,20,1,1,1,12,35,00,0000,00,7,00,0,0,0,0922|3277| [PC]_Y,SECTION SELECT, ;Check PC section
|0922|3278| IF [GLOBAL] RETURN
|0922|3279| IF [SECTION 0] RETURN
000,000,0,04,06,1,57,0,55,0,0,00,00,00,00,00,0,20,1,1,1,12,01,00,0000,00,7,00,0,0,0,0924|3280| [BIT17]_[MEM-OP LH], ;Sect == 1 here
|0924|3281| RETURN
|0924|3282|
|0924|3283|;Here to put O,,opcode A in MB
000,000,0,04,10,1,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0037,00,7,01,0,0,0,0925|3284|LUUO 2: J[037]_[W1] ;Get mask for OPcode and AC field
000,000,0,04,11,0,02,0,44,0,0,00,00,00,00,00,0,20,1,1,1,12,01,00,0000,00,7,00,0,0,0,0926|3285| [W1]BAR&[MB]_B, ;Clear extraneous bits
|0926|3286| RETURN
|0926|3287|
|0926|3288|; TOPS20 TOPS10
|0926|3289|; +-----------------------------------+ +----------------------------------+
|0926|3290|; 424 | flags | 0 | opcode | A | 00 | | opcode | AC | 00 | E |
|0926|3291|; +-----------------------------------+ +----------------------------------+
|0926|3292|; 425 | 00 | PC | | flags | PC |
|0926|3293|; +-----------------------------------+ +----------------------------------+
|0926|3294|; 426 | 00 | E | | process context word |
|0926|3295|; +-----------------------------------+ +----------------------------------+
|0926|3296|; 427 | process context word |
|0926|3297|; +-----------------------------------+
|0926|3298|
|0926|3299|;Here for MUUOs
|0926|3300|; Will do several 2910 pops just in case
000,000,0,04,10,1,00,0,33,0,0,00,00,00,00,00,0,20,1,1,0,15,01,00,0424,00,7,01,0,0,0,0927|3301|MUUO: J[0424]_[PMA],POP ;Offset into UPT for block
000,000,0,04,03,0,23,0,33,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,1625,00,7,00,0,0,0,0928|3302| [UPT]+[PMA]_B, ;Physical adr of block
|0928|3303| CALL [SV UUO STS]
|0928|3304|.IF/FT20PAG
|0928|3305|.IF/FT10PAG
|0928|3306| IF [TOPS20] THEN [MUUO 1]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,03,44,00,1651,00,7,00,0,0,0,0929|3307|.ENDIF/FT10PAG
|0929|3308|.ENDIF/FT20PAG
|0929|3309|.IF/FT10PAG
|0929|3310| SWAP [MB]_[MB] ;Other side please
000,000,0,04,06,1,42,0,46,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,4704,00,7,00,0,0,0,0931|3311| [E]_[MB RH],
|0931|3312| CALL [UNMAPPED WRITE]
|0931|3313| [PC FLAGS]_[MB]
000,000,0,04,06,1,36,0,46,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,4703,00,7,00,0,0,0,0933|3314| [PC]_[MB RH],
|0933|3315| CALL [UNMAPPED WRITE NEXT]
|0933|3316| CALL [GET CONTEXT WD]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,3360,00,7,00,0,0,0,0934|3317| CALL [UNMAPPED WRITE NEXT]
000,000,0,04,06,1,33,0,33,0,1,00,00,00,00,00,0,20,1,1,1,03,01,00,1656,00,7,00,0,0,0,0936|3318| [PMA]+1_[PMA], ;Point to 427
|0936|3319| GOTO [MUUO 2]
|0936|3320|.ENDIF/FT10PAG
|0936|3321|;Here for TOPS20 MUUO
|0936|3322|.IF/FT20PAG
000,000,0,04,14,0,67,0,34,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,4704,00,7,00,0,0,0,0937|3323|MUUO 1: [K 7777.-1]&[PC]_B, ;Strip PC to 30 bits
|0937|3324| CALL [UNMAPPED WRITE] ;Write flags, op cd, ac
000,000,0,04,06,1,36,0,44,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,4703,00,7,00,0,0,0,0938|3325| [PC]_[MB], ;Write 30 bit PC
|0938|3326| CALL [UNMAPPED WRITE NEXT]
000,000,0,04,06,1,56,0,44,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,4703,00,7,00,0,0,0,0939|3327| [MEM-OP]_[MB], ; Write 30 bit E
|0939|3328| CALL [UNMAPPED WRITE NEXT]
|0939|3329| CALL [GET CONTEXT WD] ;Get context word next
000,000,0,07,06,1,33,0,33,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,4703,00,7,00,0,0,0,0941|3330| [PMA]_Q_[PMA], ;Write context word in block
|0941|3331| CALL [UNMAPPED WRITE NEXT]
|0941|3332|.ENDIF/FT2OPAG
|0941|3333|;Heree to get new PC on an MUUO
000,000,0,04,10,1,00,0,03,0,0,00,00,00,00,00,0,20,1,1,1,03,37,00,1663,00,7,00,0,0,0,0942|3334|MUUO 2: ZERO_[PC FLAGS], ;Clear flags
|0942|3335| IF [EXEC] THEN [MUUO 4]
000,000,0,04,10,1,00,0,00,0,0,00,20,00,00,00,0,20,1,1,0,15,01,00,0004,00,7,01,0,0,0,0943|3336| J[4]_[W1],POP,SET EXEC
000,000,0,04,03,0,02,0,33,0,0,00,00,00,00,00,0,20,1,1,1,15,01,00,0000,00,7,00,0,0,0,0944|3337| [W1]+[PMA]_B,POP
|0944|3338| J[04000]_[W1] ;Bit for previous context user
000,000,0,04,10,1,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,4000,00,7,01,0,0,0,0945|3339| SWAP [W1]_[PC FLAGS]
000,000,0,04,06,1,33,0,33,0,1,00,00,05,00,00,0,20,1,1,1,01,01,00,4573,00,1,02,0,0,0,0947|3340|MUUO 4: [PMA]+1_[PMA],MEM START READ,
|0947|3341| CALL [UNMAPPED READ] ;Get new PC
000,000,0,04,06,1,46,0,34,0,0,00,14,00,00,00,0,20,1,1,1,03,44,00,1420,00,7,00,0,0,0,0948|3342| [MB]_[PC],SET LOCAL,
|0948|3343| IF [TOPS20] THEN [IFETCH]
000,000,0,04,17,0,03,0,44,0,0,00,00,00,00,00,0,20,1,1,1,03,01,00,2315,00,7,00,0,0,0,0949|3344| [PC FLAGS].OR.[MB]_B, ;Add prev context user
|0949|3345| GOTO [MB_PC FLAGS]
|0949|3346|
|0949|3347|;Here for DMOVNX
000,000,0,06,03,0,13,0,13,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0000,00,7,00,0,0,0,0950|3348|DMOVNX:
|0950|3349| #2*[MEM-OP+1]_Q ;Put low order bits in Q
000,000,0,06,05,1,00,0,00,0,1,00,00,00,00,00,0,20,1,0,1,16,00,00,0000,00,7,00,0,0,0,0951|3350| NEGATE Q_F,F_Q_Y,IX_MX ;Negate low order bits
000,000,0,04,07,1,56,0,54,0,0,00,00,00,00,00,0,52,0,1,1,16,00,00,0000,00,7,00,0,0,0,0952|3351| [MEM-OP]BAR+C_F,MC_C IX_UX, ;Negate high order bits
|0952|3352| F_[MEM-OP]
000,000,0,01,14,1,77,0,13,0,0,00,00,01,00,00,0,44,1,1,1,06,03,00,0000,12,7,00,0,0,0,0953|3353| Q_F,LRS F_B,B SEL/MEM-OP+1, ;Save loworder portion
|0953|3354| #0_SION #0_QION,
|0953|3355| IF NOT CT [MZ] D [OPERAND STORE]
|0953|3356| IF CT [UZ] THEN [SET C0!C1 STORE]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,24,1,1,0,03,02,00,2075,00,7,00,0,0,0,0954|3357| IF NOT CT [UOVR] D [OPERAND STORE]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,26,1,1,0,06,03,00,0000,12,7,00,0,0,0,0955|3358| GOTO [SET OV!C1!T1 STORE]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,03,01,00,2070,00,7,00,0,0,0,0956|3359|
|0956|3360|;Here after P&S SETUP for ADJBP
000,000,0,04,06,1,52,0,07,0,0,00,00,00,00,00,0,20,1,0,1,03,06,00,4127,00,7,00,0,0,0,0957|3361|ADJBP0: [AC-OP]_[AC-OP+1],IX_MX, ;Copy # of bytes to adjust
|0957|3362| IF [AC.EQ.0] THEN [TO NOWHERE] ;In case was really IBP
000,000,0,14,06,1,26,0,00,0,0,00,00,00,00,00,0,56,1,0,1,03,02,00,1700,00,7,00,0,0,0,0958|3363| [W6]_Y, ; Check for S=0
|0958|3364| IF CT [MN IX_MX] THEN [ADJ04]
000,000,0,04,10,1,00,0,50,0,0,00,00,00,00,00,0,20,1,1,1,03,01,00,1701,00,7,00,0,0,0,0959|3365| ZERO_[AC-OP],GOTO [ADJ06] ;Set high order word
000,000,0,04,00,1,00,0,50,0,0,00,00,00,00,00,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,0960|3366|ADJ04: ONES_[AC-OP]
000,000,0,06,11,0,76,0,20,0,0,00,00,00,00,00,0,44,1,0,0,03,02,00,1727,00,7,00,0,0,0,0961|3367|ADJ06: [K -1.0]BAR&[W5]_Q, ;Copy P
|0961|3368| IF CT [MZ IX_MX] THEN [ADJBP9] ;If S=O done
000,000,0,06,01,1,26,0,00,0,1,00,00,00,00,00,0,76,1,1,0,03,03,00,1702,00,7,00,0,0,0,0962|3369|ADJBP1: Q-[W6]_F,F_Q,
|0962|3370| IF NOT CT [IN] THEN [ADJBP1]
|0962|3371|;Count bytes in word
|0962|3372| J[044]_[W1]
000,000,0,04,00,1,00,0,10,0,0,00,00,00,00,00,0,20,1,0,1,16,00,00,0000,00,7,00,0,0,0,0964|3373| ONES_[W3],IX_MX ;Count bytes in word here
000,000,0,06,03,1,26,0,00,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0000,00,7,00,0,0,0,0965|3374|ADJBP2: Q+[W6]_F,F_Q
000,000,0,14,02,1,02,0,00,0,1,00,00,00,00,00,0,76,1,1,1,03,02,00,1710,00,7,00,0,0,0,0966|3375| [W1]-Q_F,F_Y,
|0966|3376| IF CT [IN] THEN [ADJBP3]
000,000,0,04,06,1,12,0,10,0,1,00,00,00,00,00,0,20,1,0,1,03,01,00,1705,00,7,00,0,0,0,0967|3377| [W3]+1_[W3],IX_MX, ;Count bytes in word
|0967|3378| GOTO [ADJBP2]
000,000,0,04,06,1,52,0,07,0,0,00,00,00,00,00,0,40,1,0,1,03,02,00,2157,00,7,00,0,0,0,0968|3379|ADJBP3: [AC-OP]_[AC-OP+1], ;Copy # of bytes to adjust
|0968|3380| IF CT [(MNxMOVR)!MZ IX_MX] THEN [SET NO DIVIDE]
000,000,0,04,06,1,12,0,54,0,0,00,00,00,00,00,0,20,1,0,1,01,01,00,2126,00,7,00,0,0,0,0969|3381| [W3]_[MEM-OP],IX_MX, ;Copy divisor
|0969|3382| CALL [DIVSUB] ;Get quotient in MEM-OP
000,000,0,14,06,1,13,0,00,0,0,00,00,00,00,00,0,64,0,1,1,03,02,00,1713,00,7,00,0,0,0,0970|3383| [MEM-OP+1]_Y, ;Test remainder
|0970|3384| IF CT [IZ IX_MX] THEN [ADJBP5]
000,000,0,01,06,1,22,0,50,0,0,00,00,51,00,00,0,20,1,1,1,04,01,00,0004,00,7,00,0,0,0,0971|3385|ADJBP5: ROR [W5]_[AC-OP],PUSH J[4]_CTR
000,000,0,01,06,1,52,0,50,0,0,00,00,51,00,00,0,20,1,1,1,10,00,00,0000,00,7,00,0,0,0,0972|3386| ROR [AC-OP]_[AC-OP], ;Justify pointer in AC-OP
|0972|3387| RFCT
|0972|3388| J[04000]_[W1]
000,000,0,04,10,0,02,2,00,0,0,00,00,00,00,27,0,20,1,1,0,16,00,00,0000,00,7,07,0,0,0,0974|3389| SWAP [W1]_[W1],SEL AC+[0]
000,000,0,14,14,0,02,0,50,0,0,00,00,00,00,00,0,64,1,1,0,03,03,00,1721,00,7,00,0,0,0,0975|3390| [W1]&[AC-OP]_F,
|0975|3391| IF NOT CT [IZ] THEN [ADJBP6]
000,000,0,04,03,0,56,0,52,0,0,00,00,00,00,00,0,20,1,1,1,13,01,00,4350,00,7,00,0,0,0,0976|3392| [MEM-OP]+[AC-OP RH]_B,
|0976|3393| GOTOP [AC TO AC]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,4660,00,7,00,0,0,0,0977|3394|ADJBP6: CALL [READ NEXT] ;Get 2nd half of pointer
000,000,0,04,03,0,46,0,54,0,0,00,00,00,00,27,0,20,1,1,1,16,00,01,0000,00,7,00,0,0,0,0978|3395| [MB]+[MEM-OP]_B,SEL AC+[1]
|0978|3396| [K 7777.-1]&[MEM-OP]_B
000,000,0,04,14,0,67,0,54,0,0,00,00,00,00,00,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,0979|3397| [K 7777.-1]BAR&[MB]_B
000,000,0,14,17,0,56,0,44,0,0,00,00,00,00,27,0,20,1,1,1,16,00,00,0000,00,7,04,0,0,0,0981|3398| [MEM-OP].OR.[MB]_Y,
|0981|3399| ALU_RAMFILE,SEL AC+[0]
000,000,0,14,14,0,77,0,50,0,0,00,14,00,00,00,0,20,1,1,1,13,01,00,1420,00,7,04,0,0,0,0982|3400| [AC-OP]_RAMFILE,SET LOCAL,
|0982|3401| GOTOP [IFETCH]
|0982|3402|
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,27,0,24,1,1,0,06,03,01,0000,13,7,00,0,0,0,0983|3403|ADJBP9: SEL AC+[1],
|0983|3404| IF NOT CT [UZ] D [DISPATCH 4] ;Dispatch if not global
000,000,0,14,14,0,77,0,13,0,0,00,00,00,00,00,0,20,1,1,1,06,01,00,0000,13,7,04,0,0,0,0984|3405| [MEM-OP+1]_RAMFILE,
|0984|3406| DISPATCH [DISPATCH 4]
|0984|3407|
|0984|3408|;Here for IBP or ADJBP
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,03,06,00,1761,00,7,00,0,0,0,0985|3409|ADJBP: IF [AC.EQ.0] THEN [IBP0]
|0985|3410| ;GOTO [P&S SETUP]
|0985|3411|
|0985|3412|.TOC 2, "Byte Instructions"
|0985|3413|
|0985|3414|;
|0985|3415|; +------+------+-+-+----+-----------------+
|0985|3416|; | P | S |X|I| AC | Y |
|0985|3417|; +------+------+-+-+----+-----------------+
|0985|3418|; 0 0 0 1 1 1 1 1 1 3
|0985|3419|; 0 5 6 1 2 3 4 7 8 5
|0985|3420|;Common setup routine for byte instructions
|0985|3421|; Returns W5/P W6/S Q/S UZ set if global format
|0985|3422|
|0985|3423|.IF/FTBYTE
000,000,1,11,06,1,56,0,20,0,0,00,00,11,00,00,0,20,1,1,1,14,00,00,0001,00,7,00,0,0,0,0986|3424|P&S SETUP:
|0986|3425| #2*[MEM-OP]_[W5], ;Copy pointer to W5
|0986|3426| J[1]_CTR
000,000,1,11,03,0,22,0,20,0,0,00,00,11,00,00,0,20,1,1,1,11,00,00,1733,00,7,00,0,0,0,0987|3427|P&S 2: #4*[W5]_B, ;Shift left 2 at a time
|0987|3428| LOOP [P&S 2]
|0987|3429| #2*[W5]_Q ;Leave S left justified in Q
000,000,1,13,06,1,56,0,20,0,0,00,00,51,00,00,0,20,1,1,1,14,00,00,0004,00,7,00,0,0,0,0989|3430|P&S 3: ROL [MEM-OP]_[W5] ROL Q_Q, ;Rotate pointer in W5, also rot Q
|0989|3431| J[4]_CTR
000,000,1,13,06,1,22,0,20,0,0,00,00,51,00,00,0,20,1,1,1,11,00,00,1736,00,7,00,0,0,0,0990|3432|P&S 4: ROL [W5]_[W5] ROL Q_Q, ;Rotate pointer in W5, also rot Q
|0990|3433| LOOP [P&S 4]
|0990|3434| [K 77]&[W5]_B ;Mask P to 6 bits
000,000,0,07,14,1,66,0,24,0,0,00,00,00,00,00,0,20,1,1,1,03,27,00,1744,00,7,00,0,0,0,0992|3435| Q&[K 77]_F,F_Q_[W6], ;Mask S to 6 bits
|0992|3436| IF [SECTION 0] THEN [P&S 5]
000,000,0,14,14,0,53,0,54,0,0,00,00,00,00,00,0,64,1,1,1,03,02,00,1744,00,7,00,0,0,0,0993|3437| [BIT12]&[MEM-OP]_Y, ;Check for local/global format
|0993|3438| IF CT [IZ] THEN [P&S 5]
000,000,0,07,06,1,42,0,42,0,1,00,00,00,00,00,0,11,0,1,1,03,34,00,1745,00,7,00,0,0,0,0994|3439| [E]+1_F,F_Q_[E RH],#1_UZ, ;Make adr of 2nd half
|0994|3440| IF [LOCAL] THEN [P&S 6]
000,000,0,04,14,1,77,0,40,0,0,00,00,00,00,00,0,20,1,1,1,03,01,00,1745,00,7,00,0,0,0,0995|3441| Q_[E],GOTO [P&S 6] ;Propagate carry
|0995|3442|;Here if EFA calc is from first word
000,000,0,14,06,1,56,0,00,0,0,00,00,00,00,33,0,10,0,1,1,14,00,00,1447,00,7,00,0,0,0,0996|3443|P&S 5: [MEM-OP]_Y,SPEC SEL/XR, ;Set AC and @ flags
|0996|3444| #0_UZ,J[EFA CALC]_CTR ; Load 2910 reg for subroutine call
|0996|3445|;Here to do EFA calc for byte pointer
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,24,1,1,0,05,02,00,1462,00,7,00,0,0,0,0997|3446|P&S 6: IF CT [UZ] JSRP [FETCH IW] ;Do EFA calc
|0997|3447| IF [NOT PXCT] THEN [P&S 64]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,03,47,00,1752,00,7,00,0,0,0,0998|3448| J[0100]_[PXCT RH]
000,000,0,04,10,1,00,0,62,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0100,00,7,01,0,0,0,0999|3449| CALL [PXCT FETCH]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,2422,00,7,00,0,0,0,1000|3450| GOTO [P&S 66]
000,000,0,07,06,1,42,0,40,0,0,00,00,00,00,77,0,20,1,1,1,01,01,00,4663,00,7,00,0,0,0,1002|3451|P&S 64: READ [E] ;Get word to write
000,000,0,04,10,1,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0000,00,7,01,0,0,0,1003|3452|P&S 66: J[BYTE MASK]_[W1] ;Base of mask for byte size
000,000,0,14,03,0,02,0,24,0,0,00,00,00,00,03,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,1004|3453| [W1]+[W6]_Y,Y_RAMFILE ADR ;Address mask for byte
000,000,0,14,03,0,77,0,20,0,0,00,00,00,00,00,0,20,1,0,1,16,00,00,0000,00,7,01,0,0,0,1005|3454|P&S 7: [K -1]+[W5]_Y,ALU_CTR, IX_MX ;Check P for 0 & load ctr
000,000,0,04,10,0,00,0,04,0,0,00,00,00,00,27,0,20,1,1,0,16,00,00,0000,00,7,04,0,0,0,1006|3455| RAMFILE_[W2],SEL AC+[0] ;Get mask
|1006|3456| DISPATCH [DISPATCH 4]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,06,01,00,0000,13,7,00,0,0,0,1007|3457|
|1007|3458|;Setup routine for ILOB, IDPB, and IBP instructions
|1007|3459|; Returns W5/P W6/S Q/S UZ set if global format
|1007|3460|
000,000,0,14,14,0,47,0,03,0,0,00,00,00,00,00,0,64,1,1,1,03,03,00,1732,00,7,00,0,0,0,1008|3461|IP&S SETUP:
|1008|3462| [BIT4]&[PC FLAGS]_Y, ;Check first part done
|1008|3463| IF NOT CT [IZ] THEN [P&S SETUP]
000,000,1,11,06,1,56,0,20,0,0,00,00,11,00,00,0,20,1,1,1,14,00,00,0001,00,7,00,0,0,0,1009|3464|IBP0: #2*[MEM-OP]_[W5], ;Copy pointer to W5
|1009|3465| J[1]_CTR
000,000,1,11,03,0,22,0,20,0,0,00,00,11,00,00,0,20,1,1,1,11,00,00,1762,00,7,00,0,0,0,1010|3466|IP&S 2: #4*[W5]_B,LOOP [IP&S 2] ;Shift left 2 at a time
|1010|3467| [W5]+[W5]_Q ;Put S left justified in Q
000,000,0,07,11,1,67,0,24,0,0,00,00,00,00,00,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,1012|3468| [K 7777.-1]BAR&Q_F,F_Q_[W6] ;Leave only S in Q
000,000,0,04,02,1,56,0,54,0,1,00,00,00,00,00,0,72,1,1,1,03,02,00,2006,00,7,00,0,0,0,1013|3469| [MEM-OP]-Q_F,F_[MEM-OP], ; Increment pointer
|1013|3470| IF CT [IC] THEN [IP&S 3]
|1013|3471| JS[4]_[W1] ; Put 400000,,4
000,000,0,04,14,0,67,0,54,0,0,00,00,00,00,00,0,20,1,1,1,04,01,00,0002,00,7,00,0,0,0,1015|3472| [K 7777.-1]&[MEM-OP]_B, ;Clear old P
|1015|3473| PUSH J[2]_CTR
000,000,0,01,06,1,02,0,00,0,0,00,00,51,00,00,0,20,1,1,1,10,00,00,0000,00,7,00,0,0,0,1016|3474| ROR [W1]_[W1],RFCT ;Leave 440000,,0 in W1
|1016|3475| [W1].OR.[MEM-OP]_B ; Put 36. in P
000,000,0,04,02,1,56,0,54,0,1,00,00,00,00,00,0,20,1,1,1,03,27,00,2005,00,7,00,0,0,0,1018|3476| [MEM-OP]-Q_F,F_[MEM-OP], ;Make pointer
|1018|3477| IF [SECTION 0] THEN [IP&S27]
000,000,0,14,14,0,53,0,54,0,0,00,00,00,00,00,0,64,1,1,1,03,02,00,2005,00,7,00,0,0,0,1019|3478| [BIT12]&[MEM-OP]_Y,
|1019|3479| IF CT [IZ] THEN [IP&S27]
000,000,0,07,06,1,42,0,42,0,1,00,00,00,00,00,0,20,1,1,1,03,34,00,1776,00,7,00,0,0,0,1020|3480| [E]+1_F,F_Q_[E RH],
|1020|3481| IF [LOCAL] THEN [IP&S24]
|1020|3482| Q_[E] ;Propagate carry
000,000,0,07,06,1,42,0,40,0,0,00,00,00,00,77,0,20,1,1,1,01,01,00,4663,00,7,00,0,0,0,1022|3483|IP&S24: READ [E] ;Fetch 2nd half of pointer
|1022|3484| [K 7777.-1]BAR&[MB]_Q ;Save non Y portion
000,000,0,06,11,0,67,0,44,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0000,00,7,00,0,0,0,1023|3485| [MB]+1_[MB] ; Increment Y
000,000,0,04,06,1,46,0,44,0,1,00,00,00,00,00,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,1024|3486| [K 7777.-1]&[MB]_B ;Strip non Y portion
000,000,0,04,17,1,46,0,44,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,4711,00,7,00,0,0,0,1026|3487| Q.OR.[MB]_[MB], ;Add non Y portion
|1026|3488| CALL [MEMORY WRITE]
|1026|3489| ;[MB]+1_[MB], ;Increment 2nd half of pointer
|1026|3490| ;CALL [MEMORY WRITE]
000,000,0,07,03,0,77,0,42,0,0,00,00,00,00,00,0,20,1,1,1,03,34,00,2006,00,7,00,0,0,0,1027|3491| [K -1]+[E RH]_F,F_Q_[E RH], ;Make adr of 1st half of pointer
|1027|3492| IF [LOCAL] THEN [IP&S 3]
000,000,0,04,14,1,77,0,40,0,0,00,00,00,00,00,0,20,1,1,1,03,01,00,2006,00,7,00,0,0,0,1028|3493| Q_[E], GOTO [IP&S 3] ;Propagate carry
000,000,0,04,06,1,56,0,56,0,1,00,00,00,00,00,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,1029|3494|IP&S27: [MEM-OP]+1_[MEM-OP RH] ;Increment adr
000,000,0,04,06,1,56,0,44,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,4711,00,7,00,0,0,0,1030|3495|IP&S 3: [MEM-OP]_[MB],
|1030|3496| CALL [MEMORY WRITE] ;Write updated pointer in memory
000,000,0,06,06,1,26,0,00,0,0,00,00,00,00,00,0,20,1,1,0,06,01,00,0000,12,7,00,0,0,0,1031|3497| [W6]_Q, ;Load Q with S left justified
|1031|3498| DISPATCH [DISPATCH 3] ;IBP is done, otherwise continue
000,000,0,04,17,0,47,0,03,0,0,00,00,00,00,00,0,20,1,1,1,03,01,00,1735,00,7,00,0,0,0,1032|3499|IP&S 5: [BIT4].OR.[PC FLAGS]_B, ;Set first part done
|1032|3500| GOTO [P&S 3] ; Rest 1ike P&S setup
|1032|3501|
|1032|3502|;Here for LDB or ILDB after P&S SETUP, memory word in MB
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,56,1,1,0,03,02,00,2020,00,7,00,0,0,0,1033|3503|LDB: IF CT [MN] THEN [LDB5] ;Branch if P=0
|1033|3504| J[18.]_[W1] ;Half word shift
000,000,0,14,02,0,22,0,00,0,0,00,00,00,00,00,0,76,1,0,1,03,02,00,2017,00,7,00,0,0,0,1035|3505| [W5]-[W1]_Y,
|1035|3506| IF CT [IN IX_MX] THEN [LDB4]
|1035|3507| SWAP [MB]_[MB] ;Do first 18 shifts
000,000,0,04,10,1,00,0,45,0,0,00,00,00,00,00,0,44,1,1,1,03,02,00,2020,00,7,00,0,0,0,1037|3508| ZERO_[MB LH], ;Clear half
|1037|3509| IF CT [MZ] THEN [LDB5]
000,000,0,14,02,0,22,0,00,0,0,00,00,00,00,00,0,20,1,1,1,16,00,00,0000,00,7,01,0,0,0,1038|3510| [W5]-[W1]-1_F,F_Y,ALU_CTR ;Load ctr with excess 18.
000,000,0,01,06,1,46,0,44,0,0,00,00,01,00,00,0,20,1,1,1,11,00,00,2017,00,7,00,0,0,0,1039|3511|LDB4: LRS [MB]_[MB],LOOP [LDB4]
000,000,0,14,14,0,46,0,04,0,0,00,00,00,00,00,0,20,1,1,1,13,01,00,2037,00,7,04,0,0,0,1040|3512|LDB5: [MB]&[W2]_Y,ALU_RAMFILE, ;Mask to byte size
|1040|3513| GOTOP [TO NOWHERE CFPD]
|1040|3514|
|1040|3515|;Here for DPB or IDPB after P&S SETUP, memory word in MB
000,000,0,04,14,0,06,0,50,0,0,00,00,00,00,00,0,56,1,1,1,03,02,00,2033,00,7,00,0,0,0,1041|3516|DPB: [W2]&[AC-OP]_B, ;Clear extra bits from byte
|1041|3517| IF CT [MN] THEN [DPB5] ; Branch if P=0
|1041|3518| J[18.]_[W1] ;Half word shift
000,000,0,14,02,0,22,0,00,0,0,00,00,00,00,00,0,76,1,0,1,03,02,00,2030,00,7,00,0,0,0,1043|3519| [W5]-[W1]_Y,
|1043|3520| IF CT [IN IX_MX] THEN [DPB3]
|1043|3521| SWAP [AC-OP]_[AC-OP] ;Do first 18 shifts
000,000,0,04,10,1,00,0,52,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,4027,00,7,00,0,0,0,1045|3522| ZERO_[AC-OP RH], ;Clear half
|1045|3523| CALL [SWAP W2_W2] ;Shift mask also
000,000,0,04,10,1,00,0,06,0,0,00,00,00,00,00,0,44,1,1,1,03,02,00,2030,00,7,00,0,0,0,1046|3524| ZERO_[W2 RH], ;Clear half of mask
|1046|3525| IF CT [MZ] THEN [DPB3] ; FIXME: Cant read code
|1046|3526|.WARNING "Can not read the code in the previous line. It is probably wrong"
000,000,0,14,02,0,22,0,00,0,0,00,00,00,00,00,0,20,1,1,1,16,00,00,0000,00,7,01,0,0,0,1047|3527| [W5]-[W1]-1_F,F_Y,ALU_CTR ;Load ctr with excess 18.
000,000,0,06,06,1,06,0,00,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0000,00,7,00,0,0,0,1048|3528|DPB3: [W2]_Q ;Put mask in Q reg
000,000,1,13,06,1,52,0,50,0,0,00,00,11,00,00,0,20,1,1,1,11,00,00,2031,00,7,00,0,0,0,1049|3529|DPB4: LLS [AC-OP]_[AC-OP] LLS Q_Q,
|1049|3530| LOOP [DPB4]
|1049|3531| Q_[W2] ;Get mask back from Q
000,000,0,04,11,0,06,0,44,0,0,00,00,00,00,00,0,20,1,1,1,03,47,00,2036,00,7,00,0,0,0,1051|3532|DPB5: [W2]BAR&[MB]_B, ;Clear old bits from mem word
|1051|3533| IF [NOT PXCT] THEN [DPB6]
000,000,0,04,17,0,52,0,44,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,2414,00,7,00,0,0,0,1052|3534| [AC-OP].OR.[MB]_B, ;Set new bits
|1052|3535| CALL [PXCT STORE] ;Write word back
|1052|3536| GOTO [TO NOWHERE CFPD]
000,000,0,04,17,0,52,0,44,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,4711,00,7,00,0,0,0,1054|3537|DPB6: [AC-OP].OR.[MB]_B, ;Set new bits
|1054|3538| CALL [MEMORY WRITE] ;Write word in memory
|1054|3539| ;GOTO [TO NOWHERE CFPD]
|1054|3540|.ENDIF/FTBYTE
|1054|3541|;Here when instruction done, clear first part done
000,000,0,04,11,0,47,0,03,0,0,00,14,00,00,00,0,20,1,1,1,13,01,00,1420,00,7,00,0,0,0,1055|3542|TO NOWHERE CFPD:
|1055|3543| [BIT4]BAR&[PC FLAGS]_B, ;Clear 1st part done and exit
|1055|3544| SET LOCAL,GOTOP [IFETCH]
|1055|3545|
|1055|3546|.TOC 2, "Floating Point Instructions"
|1055|3547|
|1055|3548|;Format for floating point numbers is
|1055|3549|; 0 1 2 3 4 5 6 7 8 9l0lll2l~14l5l6l7l8l9202l2223242526272829303l32333435
|1055|3550|; | \ / \ /
|1055|3551|; | | + ---fraction
|1055|3552|; | + ---exponent (excess 200)
|1055|3553|; + ---sign
|1055|3554|
|1055|3555|;Here for FIX instruction
000,000,1,11,06,1,56,0,54,0,0,00,00,11,00,00,0,56,1,1,1,03,03,00,2042,00,7,00,0,0,0,1056|3556|FIX:
|1056|3557|.IF/FTFP
|1056|3558| #2*[MEM-OP]_[MEM-OP],
|1056|3559| IF NOT CT [MN] THEN [FIX 1]
000,000,0,04,07,1,56,0,54,0,1,00,00,00,00,00,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,1057|3560| NEGATE [MEM-OP]_F,F_[MEM-OP] ;Work with positive copy
000,000,1,11,06,1,56,0,54,0,0,00,00,51,00,00,0,20,1,1,1,04,01,00,0006,00,7,00,0,0,0,1058|3561|FIX 1: ROL [MEM-OP]_[MEM-OP], ;Copy operand to extract exponent
|1058|3562| PUSH J[6]_CTR
000,000,1,11,06,1,56,0,54,0,0,00,00,51,00,00,0,20,1,1,1,10,00,00,0000,00,7,00,0,0,0,1059|3563| ROL [MEM-OP]_[MEM-OP], ;Rotate exponent to rh of W1
|1059|3564| RFCT
000,000,0,06,14,0,72,0,54,0,0,00,14,00,00,00,0,20,1,1,0,16,00,00,0000,00,7,00,0,0,0,1060|3565| [K 777]&[MEM-OP]_Q, ;Get the exponent
|1060|3566| SET LOCAL
|1060|3567| [K 777]BAR&[MEM-OP]_B ;Strip exponent from number
000,000,0,04,11,0,72,0,54,0,0,00,00,00,00,00,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,1061|3568| J[0242]_[W2]
000,000,0,14,02,1,06,0,00,0,1,00,00,00,00,00,0,20,0,1,1,16,00,00,0000,00,7,01,0,0,0,1063|3569| [W2]-Q_F,F_Y,ALU_CTR,IX_UX
|1063|3570| IF CT [UN] THEN [SET OV!T1 TRAP]
000,000,0,03,14,0,77,0,54,0,0,00,00,31,00,00,0,24,1,1,1,03,02,00,2053,00,7,00,0,0,0,1065|3571| [K -1]&[MEM-OP]_F, ; Position result
|1065|3572| LSRC_B,#0_SION SIO0_QION,
|1065|3573| IF CT [UZ] THEN [FIX 6]
000,000,0,03,14,0,77,0,54,0,0,00,00,31,00,00,0,20,1,1,1,11,00,00,2052,00,7,00,0,0,0,1066|3574|FIX 5: [K -1]&[MEM-OP]_F, ;Position result
|1066|3575| LSRC_B,#0_SION SIO0_QION,
|1066|3576| LOOP [FIX 5]
000,000,0,14,14,0,77,0,54,0,0,00,00,00,00,00,0,56,1,1,1,06,03,00,0000,12,7,04,0,0,0,1067|3577|FIX 6: [MEM-OP]_RAMFILE,
|1067|3578| IF NOT CT [MN] D [OPERAND STORE]
000,000,0,04,07,1,56,0,54,0,1,00,00,00,00,00,0,20,1,1,1,06,01,00,0000,12,7,04,0,0,0,1068|3579| NEGATE [MEM-OP]_F,F_[MEM-OP],
|1068|3580| ALU_RAMFILE,
|1068|3581| DISPATCH [OPERAND STORE]
|1068|3582|.ENDIF/FTFP
|1068|3583|
|1068|3584|;Here for FIXR = fix and round
000,000,0,14,14,1,77,0,00,0,0,00,00,00,00,00,0,76,1,1,1,13,03,00,1420,00,7,00,0,0,0,1069|3585|FIXR:
|1069|3586|.IF/FTFP
|1069|3587| Q_Y,
|1069|3588| IF NOT CT [IN] THENP [IFETCH]
000,000,0,14,06,1,56,0,00,0,1,00,00,00,00,00,0,56,1,1,1,13,03,00,1420,00,7,04,0,0,0,1070|3589| [MEM-OP]+1_Y,ALU_RAMFILE,
|1070|3590| IF NOT CT [MN] THENP [IFETCH]
000,000,0,14,03,0,77,0,54,0,0,00,00,00,00,00,0,20,1,1,1,13,01,00,1420,00,7,04,0,0,0,1071|3591| [K -1]+[MEM-OP]_Y,ALU_RAMFILE,
|1071|3592| GOTOP [IFETCH]
|1071|3593| GOTO [TO AC]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,03,01,00,4343,00,7,00,0,0,0,1072|3594|.ENDIF/FTFP
|1072|3595|
|1072|3596|;Here for FLTR = float and round
000,000,0,14,11,0,76,0,40,0,0,00,14,00,00,00,0,20,1,1,1,13,01,00,1420,00,7,04,0,0,0,1073|3597|FLTR: ;DISPATCH [OPERAND STORE]
|1073|3598|
|1073|3599|;Here for FADx
|1073|3600|FADX: ;DISPATCH [OPERAND STORE]
|1073|3601|
|1073|3602|;Here for FADRx
|1073|3603|FADRX: ;DISPATCH [OPERAND STORE]
|1073|3604|
|1073|3605|;Here for FSBx
|1073|3606|FSBX: ;DISPATCH [OPERAND STORE]
|1073|3607|
|1073|3608|;Here for FSBRx
|1073|3609|FSBRX: ;DISPATCH [OPERAND STORE]
|1073|3610|
|1073|3611|;Here for FMPx
|1073|3612|FMPX: ;DISPATCH [OPERAND STORE]
|1073|3613|
|1073|3614|;Here for FMPRx
|1073|3615|FMPRX: ;DISPATCH [OPERAND STORE]
|1073|3616|
|1073|3617|;Here for FDVx
|1073|3618|FDVX: ;DISPATCH [OPERAND STORE]
|1073|3619|
|1073|3620|;Here for FDVRx
|1073|3621|FDVRX: ;DISPATCH [OPERAND STORE]
|1073|3622|
|1073|3623|.TOC "Full Word Data Transmission"
|1073|3624|
|1073|3625|;Here for MOVEI
|1073|3626|
|1073|3627|.IF/FAST
|1073|3628|MOVEI: [K -1.0]BAR&[E]_F,F_Y, ;Strip extra bits
|1073|3629| ALU_RAMFILE,SET LOCAL,
|1073|3630| GOTOP [IFETCH]
|1073|3631|
|1073|3632|;Here for MOVSI
000,000,0,04,10,0,42,2,40,0,0,00,00,00,00,27,0,20,1,1,0,16,00,00,0000,00,7,07,0,0,0,1074|3633|MOVSI: SWAP [E]_[E],SEL AC+[0] ;Position bits
000,000,0,14,14,0,76,0,40,0,0,00,14,00,00,00,0,20,1,1,1,03,01,00,1420,00,7,04,0,0,0,1075|3634| [K -1.0]&[E]_Y,ALU_RAMFILE,
|1075|3635| SET LOCAL,GOTO [IFETCH]
|1075|3636|.ENDIF/FAST
|1075|3637|
|1075|3638|;Here for MOVSx (also some Hxx instructions)
000,000,0,04,10,0,56,2,54,0,0,00,00,00,00,00,0,20,1,1,0,06,01,00,0000,12,7,07,0,0,0,1076|3639|MOVSX: SWAP [MEM-OP]_[MEM-OP],
|1076|3640| DISPATCH [OPERAND STORE]
|1076|3641|
|1076|3642|;Here for MOVMx
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,56,1,1,0,06,03,00,0000,12,7,00,0,0,0,1077|3643|MOVMX: IF NOT CT [MN] D [OPERAND STORE]
|1077|3644| ;GOTO [MOVNX]
|1077|3645|
|1077|3646|;Here for MOVNx
000,000,0,04,07,1,56,0,54,0,1,00,00,00,00,00,0,64,0,1,1,03,02,00,2075,00,7,00,0,0,0,1078|3647|MOVNX: NEGATE [MEM-OP]_F,F_[MEM-OP], ;Negate operand
|1078|3648| IF CT [IZ IX_MX] THEN [SET C0!C1 STORE]
|1078|3649| IF NOT CT [MOVR] D [OPERAND STORE]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,46,1,1,0,06,03,00,0000,12,7,00,0,0,0,1079|3650|
000,000,0,04,10,1,00,0,00,0,0,00,74,00,00,00,0,20,1,1,0,16,00,00,5002,00,7,01,0,0,0,1080|3651|SET OV!C1!T1 STORE:
|1080|3652| J[05002]_[W1],SET TRAP ;Set overflow, carry 1, and trap 1
000,000,0,04,10,0,02,2,00,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,4151,00,7,07,0,0,0,1081|3653| SWAP [W1]_[W1],
|1081|3654| CALL [#64*W1!PCF]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,27,0,20,1,1,0,06,01,00,0000,12,7,00,0,0,0,1082|3655| SEL AC+[0],
|1082|3656| DISPATCH [OPERAND STORE]
|1082|3657|
|1082|3658|.TOC 2, "Fixed Point Instructions"
|1082|3659|
|1082|3660|;Here for ADDx
000,000,0,04,03,0,52,0,54,0,0,00,00,00,00,00,0,66,1,0,1,03,02,00,2077,00,7,00,0,0,0,1083|3661|ADDX: [AC-OP]+[MEM-OP]_B, ;Add AC & HEM
|1083|3662| IF CT [IOVR IX_MX] THEN [ADDXOV]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,53,1,1,0,06,02,00,0000,12,7,00,0,0,0,1084|3663|ADDX2: IF CT [NOT MC] D [OPERAND STORE] ;No carry means done
000,000,0,04,17,0,63,0,03,0,0,00,00,00,00,27,0,20,1,1,1,06,01,00,0000,12,7,00,0,0,0,1085|3664|SET C0!C1 STORE:
|1085|3665| [C0!C1].OR.[PC FLAGS]_B,
|1085|3666| SEL AC+[0],
|1085|3667| DISPATCH [OPERAND STORE]
|1085|3668|
|1085|3669|;Here for SUBx
000,000,0,04,02,0,52,0,54,0,0,00,00,00,00,00,0,67,1,0,1,03,02,00,2074,00,7,00,0,0,0,1086|3670|SUBX: [AC-OP]-[MEM-OP]_B, ;AC-MEM_MEM and then store
|1086|3671| IF CT [NOT IOVR IX_MX] THEN [ADDX2]
|1086|3672|
|1086|3673|;Here if got overflow
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,53,1,1,0,03,02,00,2070,00,7,00,0,0,0,1087|3674|ADDXOV: IF CT [NOT MC] THEN [SET OV!C1!T1 STORE]
000,000,0,04,10,1,00,0,00,0,0,00,74,00,00,00,0,20,1,1,0,16,00,00,6002,00,7,01,0,0,0,1088|3675|SET OV!C0!T1 STORE:
|1088|3676| J[06002]_[W1],SET TRAP ;Set overflow, carry 0, and trap 1
000,000,0,04,10,0,02,2,00,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,4151,00,7,07,0,0,0,1089|3677| SWAP [W1]_[W1],
|1089|3678| CALL [#64*W1!PCF]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,27,0,20,1,1,0,06,01,00,0000,12,7,00,0,0,0,1090|3679| SEL AC+[0],
|1090|3680| DISPATCH [OPERAND STORE]
|1090|3681|
|1090|3682|
|1090|3683|;Here for MULx or IMULx
|1090|3684|; Memory operand already in Q
|1090|3685|.IF/FAST
000,000,0,04,10,1,00,0,54,0,0,00,00,00,00,00,0,20,1,1,1,14,00,00,0041,00,7,00,0,0,0,1091|3686|MULX: ZERO_[MEM-OP],J[33.]_CTR ;Initialize work register
|1091|3687| TCM [AC-OP] [MEM-OP] ;Do shift and add
000,100,0,14,10,0,52,0,54,0,0,00,00,31,00,00,0,20,1,1,1,11,00,00,2105,00,7,00,0,0,0,1093|3688|MULX 2: TCM [AC-OP] [MEM-OP], ;Do shift and add
|1093|3689| LOOP [MULX 2]
|1093|3690|.ENDIF/FAST
|1093|3691|.IFNOT/FAST
|1093|3692|MULX: ZERO_[MEM-OP],J[34.]_CTR ;Initialize work register
|1093|3693|MULX 2: TCM [AC-OP] [MEM-OP] ;Do shift and add
|1093|3694| LOOP [MULX 2]
|1093|3695|.ENDIF/FAST
|1093|3696| TCM COR [AC-OP] [MEM-OP] ;Final shift and add
000,000,1,12,06,1,56,0,54,0,0,00,00,21,00,00,0,20,1,0,1,16,00,00,0000,00,7,00,0,0,0,1095|3697| [MEM-OP]_F,B SEL/MEM-OP,ALSC_B, ;Shift product left
|1095|3698| SION_MC QION_SIO0 #0_QIO0,IX_MX ; put carry out in MC
000,000,0,01,14,1,77,0,13,0,0,00,00,25,00,00,0,56,1,1,1,06,02,00,0000,12,7,00,0,0,0,1096|3699| Q_F, (MN F)RS_[MEM-OP+1], ;Get low order portion
|1096|3700| IF CT [MN] D [OPERAND STORE]
|1096|3701| IF NOT CT [MC] D [OPERAND STORE]
000,000,0,01,10,1,00,0,54,0,0,00,00,05,00,00,0,20,1,1,1,01,01,00,4143,00,7,00,0,0,0,1098|3702| BIT0_[MEM-OP], ;Architecture says to do this
|1098|3703| CALL [SET OV!T1] ;Set overflow & trap 1
000,000,0,01,10,1,00,0,13,0,0,00,00,05,00,00,0,20,1,1,1,06,01,00,0000,12,7,00,0,0,0,1099|3704| BIT0_[MEM-OP+1], ;More architecture cyberkrud
|1099|3705| DISPATCH [OPERAND STORE]
|1099|3706|
|1099|3707|;Here for IMULx after doing MULx
000,000,0,04,06,1,56,0,54,0,1,00,00,00,00,00,0,44,1,0,1,03,02,00,2116,00,7,00,0,0,0,1100|3708|IMULX: [MEM-OP]+1_[MEM-OP], ;In case high order portion neg
|1100|3709| IF CT [MZ IX_MX] THEN [IMULX4]
|1100|3710| IF NOT CT [MZ] CALL [SET OV!T1] ;Set overflow if high order bits
000,000,0,04,06,1,13,0,54,0,0,00,00,00,00,00,0,20,1,1,1,06,01,00,0000,13,7,00,0,0,0,1102|3711|IMULX4: [MEM-OP+1]_[MEM-OP],
|1102|3712| DISPATCH [DISPATCH 4]
|1102|3713|
|1102|3714|;Here for IDIVx
000,000,0,04,06,1,52,0,07,0,0,00,00,00,00,00,0,76,1,1,1,03,02,00,2121,00,7,00,0,0,0,1103|3715|IDIVX: [AC-OP]_[AC-OP+1], ;Put argument in right place
|1103|3716| IF CT [IN] THEN [IDIVXN]
000,000,0,04,10,1,00,0,50,0,0,00,00,00,00,00,0,20,1,1,1,03,01,00,2124,00,7,00,0,0,0,1104|3717| ZERO_[AC-OP],GOTO [DIVX0] ;Extend sign
000,000,0,04,00,1,00,0,50,0,0,00,00,00,00,00,0,20,1,1,1,03,01,00,2124,00,7,00,0,0,0,1105|3718|IDIVXN: ONES_[AC-OP],GOTO [DIVX0] ;Extend sign
|1105|3719|
|1105|3720|;Here for DIVx
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,27,0,20,1,1,0,16,00,01,0000,00,7,00,0,0,0,1106|3721|DIVX: SEL AC+[1] ;Address low order portion
|1106|3722| RAMFILE_[AC-OP+1]
000,000,0,04,06,1,56,0,10,0,0,00,00,00,00,00,0,20,1,0,1,01,01,00,2126,00,7,00,0,0,0,1108|3723|DIVX0: [MEM-OP]_[W3],IX_MX, ;Copy divisor
|1108|3724| CALL [DIVSUB]
|1108|3725| DISPATCH [OPERAND STORE]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,06,01,00,0000,12,7,00,0,0,0,1109|3726|
|1109|3727|;Subroutine to do a divide
|1109|3728|; Call with dividend in AC-OP, AC-OP+1, divisor in MEM-OP_W3,IX_MX
000,000,0,04,06,1,52,0,04,0,0,00,00,00,00,00,0,56,1,0,1,03,03,00,2130,00,7,00,0,0,0,1110|3729|DIVSUB: [AC-OP]_[W2], ;Copy highorder dividend
|1110|3730| IF NOT CT [MN IX_MX] THEN [DIVX02]
000,000,0,04,07,1,12,0,10,0,1,00,00,00,00,00,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,1111|3731| NEGATE [W3]_F,F_[W3] ;Make magnitude of divisor
000,000,0,06,03,0,07,0,07,0,0,00,00,00,00,00,0,56,1,1,0,03,03,00,2133,00,7,00,0,0,0,1112|3732|DIVX02: [AC-OP+1]+[AC-OP+1]_F,F_Q, ;Put loworder dividend in Q
|1112|3733| IF NOT CT [MN] THEN [DIVX04]
|1112|3734|;Following 2 ins for KL10 compatible divide
000,000,0,14,05,1,00,0,00,0,1,00,00,00,00,00,0,20,0,1,0,16,00,00,0000,00,7,00,0,0,0,1113|3735| NEGATE Q_F,IX_UX ;Latch carry out of loworder
000,000,0,04,07,1,06,0,04,0,3,00,00,00,00,00,0,00,1,1,1,16,00,00,0000,00,7,00,0,0,0,1114|3736| [W2]BAR+C_F,UC_C,F_[W2]
|1114|3737|;Following for non KL10 compatible
|1114|3738| ;[W2]BAR+C_F,#0_CO,F_[W2]
000,000,0,14,02,0,06,0,10,0,1,00,00,00,00,00,0,76,1,1,0,03,03,00,2157,00,7,00,0,0,0,1115|3739|DIVX04: [W2]-[W3]_F,
|1115|3740| IF NOT CT [IN] THEN [SET NO DIVIDE]
000,000,0,02,06,1,52,0,50,0,0,00,00,25,00,00,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,1116|3741| [AC-OP]_F,ASRC_B,B SEL/AC-OP,
|1116|3742| MN_SION SIO0_QION
|1116|3743|.IF/FAST
000,500,1,14,10,0,56,0,50,0,0,00,00,75,00,00,0,20,1,1,1,14,00,00,0041,00,7,00,0,0,0,1117|3744| R SEL/MEM-OP,S SEL[AC-OP],
|1117|3745| #0_CO,ALU SP FUN/DLN,ALU_Y/YES,
|1117|3746| SION_QIO0 QION_SIO0,J[33.]_CTR
|1117|3747| TCDIV [MEM-OP] [AC-OP]_B
000,600,1,14,10,0,56,0,50,0,2,00,00,75,00,00,0,20,1,1,1,11,00,00,2137,00,7,00,0,0,0,1119|3748|DIVX15: TCDIV [MEM-OP] [AC-OP]_B,
|1119|3749| LOOP [DIVX15]
|1119|3750|.ENDIF/FAST
|1119|3751|.IFNOT/FAST
|1119|3752| R SEL/MEM-OP,S SEL[AC-OP],
|1119|3753| #0_CO,ALU SP FUN/DLN,ALU_Y/YES,
|1119|3754| SION_QIO0 QION_SIO0,J[34.]_CTR
|1119|3755|DIVX15: TCDIV [MEM-OP] [AC-OP]_B,
|1119|3756| LOOP [DIVX15]
|1119|3757|.ENDIF/FAST
|1119|3758| TCDIV COR [MEM-OP] [AC-OP]_B
000,000,0,04,06,1,52,0,13,0,0,00,00,00,00,00,0,56,0,1,1,03,02,00,2146,00,7,00,0,0,0,1121|3759| [AC-OP]_[MEM-OP+1], ;Latch remainder sign
|1121|3760| IF CT [MN IX_UX] THEN [DIVX40] ; Branch if dividend negative
000,000,0,14,06,1,56,0,00,0,0,00,00,00,00,00,0,36,1,0,1,03,03,00,2156,00,7,00,0,0,0,1122|3761| [MEM-OP]_Y, ;Latch sign of divisor
|1122|3762| IF NOT CT [UN IX_MX] THEN [DIVX90] ;Positive remainder = OK
|1122|3763| IF CT [MN] THEN [DIVXR]
000,000,0,04,03,0,56,0,13,0,0,00,00,00,00,00,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,1124|3764|DIVXQ: [MEM-OP]+[MEM-OP+1]_B ;Add divisor to remainoer
000,000,0,04,03,1,77,0,54,0,0,00,00,00,00,00,0,20,1,1,1,12,01,00,0000,00,7,00,0,0,0,1125|3765|DIVXQ1: Q+[K -1]_[MEM-OP], ;Adjust quotient and store
|1125|3766| RETURN
|1125|3767|
|1125|3768|;Here because dividend was negative
000,000,0,14,06,1,56,0,00,0,0,00,00,00,00,00,0,24,1,0,1,03,02,00,2156,00,7,00,0,0,0,1126|3769|DIVX40: [MEM-OP]_Y, ;Latch sign of divisor
|1126|3770| IF CT [UZ IX_MX] THEN [DIVX90] ;Remainder=O OK
000,000,0,14,03,0,13,0,10,0,0,00,00,00,00,00,0,36,0,1,1,03,02,00,2153,00,7,00,0,0,0,1127|3771| [MEM-OP+1]+[W3]_Y, ;Remainder vs divisor magnitude
|1127|3772| IF CT [UN IX_UX] THEN [DIVX46] ;R=negative, check quotient
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,56,1,1,0,03,02,00,2144,00,7,00,0,0,0,1128|3773|DIVX42: IF CT [MN] THEN [DIVXQ] ;Branch if divisor was negative
000,000,0,04,01,0,56,0,13,0,1,00,00,00,00,00,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,1129|3774|DIVXR: [MEM-OP+1]-[MEM-OP]_A ;Subtract divisor from remainder
000,000,0,04,06,1,00,0,54,0,1,00,00,00,00,00,0,20,1,1,1,12,01,00,0000,00,7,00,0,0,0,1130|3775| Q+1_F,F_[MEM-OP], ;Adjust quotient and store
|1130|3776| RETURN
|1130|3777|
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,24,1,1,0,03,03,00,2156,00,7,00,0,0,0,1131|3778|DIVX46: IF NOT CT [UZ] THEN [DIVX90]
|1131|3779| IF CT [MN] THEN [DIVXR] ;Branch if divisor was negative
000,000,0,04,03,0,56,0,13,0,0,00,00,00,00,00,0,20,1,1,1,03,01,00,2145,00,7,00,0,0,0,1133|3780| [MEM-OP]+[MEM-OP+1]_B,
|1133|3781| GOTO [DIVXQ1]
|1133|3782|
000,000,0,04,14,1,77,0,54,0,0,00,00,00,00,00,0,20,1,1,1,12,01,00,0000,00,7,00,0,0,0,1134|3783|DIVX90: Q_[MEM-OP], ;Save quotient
|1134|3784| RETURN
|1134|3785|
000,000,0,04,10,1,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0040,00,7,01,0,0,0,1135|3786|SET NO DIVIDE:
|1135|3787| J[040]_[W1] ;Will become no divide
000,000,0,04,10,0,02,2,00,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,4153,00,7,07,0,0,0,1136|3788| SWAP [W1]_[W1],
|1136|3789| CALL [W1!PCF]
000,000,0,14,10,0,00,0,00,0,0,00,14,00,00,00,0,20,1,1,0,01,01,00,4143,00,7,00,0,0,0,1137|3790|SET OV!T1 TRAP:
|1137|3791| CALL [SET OV!T1],SET LOCAL ;Set overflow and trap1
|1137|3792| GOTOP [TRAP]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,13,01,00,4130,00,7,00,0,0,0,1138|3793|
|1138|3794|.TOC 2, "Double Precision Fixed Point Instructions"
|1138|3795|
|1138|3796|;Here for DADD
000,000,1,11,06,1,07,0,07,0,0,00,00,11,00,00,0,20,1,1,1,01,01,00,2171,00,7,00,0,0,0,1139|3797|DADD: #2*[AC-OP+1]_[AC-OP+1], ;Adjust low order AC operand
|1139|3798| CALL [DADD4] ; and adjust low order mem operand
000,000,0,04,03,0,07,0,13,0,0,00,00,00,00,00,0,20,1,0,1,16,00,00,0000,00,7,00,0,0,0,1140|3799| [AC-OP+1]+[MEM-OP+1]_B, ;Add low order parts
|1140|3800| IX_MX
000,000,0,04,03,0,52,0,54,0,0,00,00,00,00,00,0,52,1,0,1,16,00,00,0000,00,7,00,0,0,0,1141|3801| [AC-OP]+[MEM-OP]+C_B, ;Add AC & MEM
|1141|3802| MC_C IX_MX
000,000,0,01,06,1,13,0,13,0,0,00,00,25,00,00,0,46,1,1,1,03,02,00,2077,00,7,00,0,0,0,1142|3803|DADD2: ASR [MEM-OP+1]_[MEM-OP+1], ;Put sign on low order portion
|1142|3804| IF CT [MOVR] THEN [ADDXOV] ;No carry means done
|1142|3805| IF CT [NOT MC] D [OPERAND STORE]
000,000,0,04,17,0,63,0,03,0,0,00,00,00,00,00,0,20,1,1,1,06,01,00,0000,12,7,00,0,0,0,1144|3806| [C0!C1].OR.[PC FLAGS]_B,
|1144|3807| DISPATCH [OPERAND STORE]
|1144|3808|
000,000,1,11,06,1,13,0,13,0,0,00,00,11,00,00,0,20,1,1,1,12,01,00,0000,00,7,00,0,0,0,1145|3809|DADD4: #2*[MEM-OP+1]_[MEM-OP+1], ;Adjust low order mem operand
|1145|3810| RETURN
|1145|3811|
|1145|3812|;Here for DSUB
000,000,1,11,06,1,07,0,07,0,0,00,00,11,00,00,0,20,1,1,1,01,01,00,2171,00,7,00,0,0,0,1146|3813|DSUB: #2*[AC-OP+1]_[AC-OP+1], ;Adjust low order AC operand
|1146|3814| CALL [DADD4] ; and adjust low order mem operand
000,000,0,04,02,0,07,0,13,0,0,00,00,00,00,00,0,20,1,0,1,16,00,00,0000,00,7,00,0,0,0,1147|3815| [AC-OP+1]-[MEM-OP+1]_B, ;Subtract low order parts
|1147|3816| IX_MX
000,000,0,04,02,0,52,0,54,0,0,00,00,00,00,00,0,52,1,0,1,03,01,00,2166,00,7,00,0,0,0,1148|3817| [AC-OP]-[MEM-OP]-1+C_F,F_B, ;AC-MEM_MEM and then store
|1148|3818| MC_C IX_MX,
|1148|3819| GOTO [DADD2]
|1148|3820|
|1148|3821|;Here for DMUL
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,06,01,00,0000,12,7,00,0,0,0,1149|3822|DMUL: ;DISPATCH [OPERAND STORE]
|1149|3823|
|1149|3824|;Here for DDIV
|1149|3825|DDIV: DISPATCH [OPERAND STORE]
|1149|3826|
|1149|3827|.TOC 2, "Shift and Rotate Instructions"
|1149|3828|
000,000,0,14,06,1,56,0,00,0,0,00,00,00,00,00,0,20,1,0,0,16,00,00,0000,00,7,00,0,0,0,1150|3829|ASHC SETUP:
|1150|3830| [MEM-OP]_F,IX_MX ;Latch MN
000,000,0,06,03,0,13,0,13,0,0,00,00,00,00,00,0,20,1,1,0,03,01,00,2201,00,7,00,0,0,0,1151|3831| #2*[MEM-OP+1]_Q, ;Load Q with low order portion
|1151|3832| GOTO [ASH SETUP]
|1151|3833|
000,000,0,06,06,1,13,0,00,0,0,00,00,00,00,00,0,20,1,1,0,03,01,00,2201,00,7,00,0,0,0,1152|3834|LSHC SETUP:
|1152|3835| [MEM-OP+1]_Q, ;Load Q with low order portion
|1152|3836| GOTO [ASH SETUP]
|1152|3837|
|1152|3838|;Here for ASH, etc. setup
000,000,0,04,10,1,00,0,00,0,0,00,14,00,00,00,0,20,1,1,0,16,00,00,0377,00,7,01,0,0,0,1153|3839|ASH SETUP:
|1153|3840| J[0377]_[W1],SET LOCAL ;Generate mask for extraneous bits
000,000,0,04,14,0,02,0,40,0,0,00,00,00,00,00,0,20,0,1,1,03,56,00,2206,00,7,00,0,0,0,1154|3841| [W1]&[E]_B,IX_UX, ;Strip extraneous bits
|1154|3842| IF [B BIT 18] THEN [ASHR SETUP]
000,000,0,04,03,0,77,0,40,0,0,00,00,00,00,00,0,20,1,1,1,16,00,00,0000,00,7,01,0,0,0,1155|3843| [K -1]+[E]_B,ALU_CTR ;Load counter
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,27,0,24,1,1,0,06,03,00,0000,12,7,00,0,0,0,1156|3844| SEL AC+[0],
|1156|3845| IF NOT CT [UZ] D [DISPATCH 3]
000,000,0,14,10,0,00,0,00,0,0,00,14,00,00,00,0,20,1,1,0,13,01,00,1420,00,7,00,0,0,0,1157|3846| SET LOCAL,GOTOP [IFETCH]
|1157|3847|
000,000,0,04,02,0,02,0,40,0,0,00,00,00,00,00,0,20,1,1,1,16,00,00,0000,00,7,01,0,0,0,1158|3848|ASHR SETUP:
|1158|3849| [W1]-[E]_B,ALU_CTR ;Load counter
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,27,0,20,1,1,0,06,01,00,0000,13,7,00,0,0,0,1159|3850| SEL AC+[0],
|1159|3851| DISPATCH [DISPATCH 4]
|1159|3852|
|1159|3853|;Here for ASH
000,000,0,04,03,0,56,0,54,0,0,00,00,00,00,00,0,06,0,1,1,11,00,00,2210,00,7,00,0,0,0,1160|3854|ASH: [MEM-OP]+[MEM-OP]_B, ;Shift left
|1160|3855| IX!UOVR_UX,LOOP [ASH] ; Latch overflow if any
000,000,0,14,14,0,77,0,54,0,0,00,14,00,00,00,0,26,1,1,1,13,03,00,1420,00,7,04,0,0,0,1161|3856| [MEM-OP]_RAMFILE,SET LOCAL, ;Write AC
|1161|3857| IF NOT CT [UOVR] THENP [IFETCH]
000,000,0,04,03,0,56,0,54,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,4143,00,7,00,0,0,0,1162|3858| [MEM-OP]+[MEM-OP]_B, ;Shift off sign
|1162|3859| CALL [SET OV!T1]
000,000,0,01,04,0,00,0,54,0,0,00,00,25,00,00,0,20,1,1,1,13,01,00,4130,00,7,04,0,0,0,1163|3860| B[MEM-OP]_F,MN_SION SIO0_QION,
|1163|3861| LRS F_B,ALU_RAMFILE,
|1163|3862| GOTOP [TRAP]
|1163|3863|
000,000,0,01,06,1,56,0,54,0,0,00,00,25,00,00,0,20,1,1,1,11,00,00,2214,00,7,00,0,0,0,1164|3864|ASHR: ASR [MEM-OP]_[MEM-OP], ;Shift right
|1164|3865| LOOP [ASHR]
000,000,0,14,14,0,77,0,54,0,0,00,14,00,00,00,0,20,1,1,1,13,01,00,1420,00,7,04,0,0,0,1165|3866| [MEM-OP]_RAMFILE, ;Write AC
|1165|3867| SET LOCAL,
|1165|3868| GOTOP [IFETCH]
|1165|3869|
|1165|3870|;Here for ASHC
000,000,0,02,06,1,56,0,54,0,0,00,00,25,00,00,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,1166|3871|ASHC: ASRC [MEM-OP]_[MEM-OP] ;Shift right once
000,500,1,14,10,0,56,0,54,0,0,00,00,31,00,00,0,06,0,1,1,11,00,00,2217,00,7,00,0,0,0,1167|3872|ASCH1: R SEL/MEM-OP,S SEL[MEM-OP], ;Shift left & latch overflow
|1167|3873| IX!UOVR_UX,
|1167|3874| #0_CO,ALU SP FUN/DLN,ALU_Y/YES,
|1167|3875| QION_SIO0 #0_QIO0,LOOP [ASCH1]
|1167|3876| LLSC [MEM-OP]_[MEM-OP] ;Shift left
000,000,1,13,06,1,56,0,54,0,0,00,00,31,00,00,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,1168|3877| LLSC [MEM-OP]_[MEM-OP] ;Shift left
000,000,0,03,04,0,00,0,54,0,0,00,00,25,00,00,0,20,1,1,1,16,00,00,0000,00,7,04,0,0,0,1170|3878| MN_SION SIO0_QION,LSRC_B, ;Shift right adding sign
|1170|3879| B[MEM-OP]_F,ALU_RAMFILE ; Save AC
|1170|3880| SEL AC+[1] ;Address AC+1
000,000,0,01,14,1,77,0,13,0,0,00,00,25,00,00,0,26,1,1,1,03,03,00,1420,00,7,04,0,0,0,1172|3881| Q_F,LRS F_B,MN_SION SIO0_QION,
|1172|3882| B SEL/MEM-OP+1,ALU_RAMFILE,
|1172|3883| IF NOT CT [UOVR] THEN [IFETCH]
|1172|3884| GOTOP [SET OV!T1 TRAP]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,13,01,00,2161,00,7,00,0,0,0,1173|3885|
|1173|3886|;Here for an ASH shifting right
|1173|3887|
000,000,0,02,06,1,56,0,54,0,0,00,00,25,00,00,0,20,1,1,1,11,00,00,2226,00,7,00,0,0,0,1174|3888|ASHCR: ASRC [MEM-OP]_[MEM-OP], ;Shift right
|1174|3889| LOOP [ASHCR]
000,000,0,14,06,1,56,0,00,0,0,00,00,00,00,27,0,20,1,1,1,16,00,01,0000,00,7,04,0,0,0,1175|3890| [MEM-OP]_Y,ALU_RAMFILE,
|1175|3891| SEL AC+[1]
000,000,0,01,14,1,77,0,13,0,0,00,00,25,00,00,0,20,1,1,1,13,01,00,1420,00,7,04,0,0,0,1176|3892| Q_F,LRS F_B,MN_SION SIO0_QION,
|1176|3893| B SEL/MEM-OP+1,
|1176|3894| ALU_RAMFILE,
|1176|3895| GOTOP [IFETCH]
|1176|3896|
|1176|3897|;Here for LSH
000,000,1,11,06,1,56,0,54,0,0,00,00,11,00,00,0,20,1,1,1,11,00,00,2231,00,7,00,0,0,0,1177|3898|LSH: #2*[MEM-OP]_[MEM-OP],
|1177|3899| LOOP [LSH]
000,000,0,14,14,0,77,0,54,0,0,00,14,00,00,00,0,20,1,1,1,13,01,00,1420,00,7,04,0,0,0,1178|3900| [MEM-OP]_RAMFILE, ;Write AC
|1178|3901| SET LOCAL,
|1178|3902| GOTOP [IFETCH]
|1178|3903|
000,000,0,01,06,1,56,0,54,0,0,00,00,01,00,00,0,20,1,1,1,11,00,00,2233,00,7,00,0,0,0,1179|3904|LSHR: LRS [MEM-OP]_[MEM-OP], ;Shift right
|1179|3905| LOOP [LSHR]
000,000,0,14,14,0,77,0,54,0,0,00,14,00,00,00,0,20,1,1,1,13,01,00,1420,00,7,04,0,0,0,1180|3906| [MEM-OP]_RAMFILE, ;Write AC
|1180|3907| SET LOCAL,
|1180|3908| GOTOP [IFETCH]
|1180|3909|
|1180|3910|;Here for LSHC
000,000,1,13,06,1,56,0,54,0,0,00,00,31,00,00,0,20,1,1,1,11,00,00,2235,00,7,00,0,0,0,1181|3911|LSHC: LLSC [MEM-OP]_[MEM-OP], ;Shift left with Q
|1181|3912| LOOP [LSHC]
000,000,0,04,14,1,77,0,13,0,0,00,00,00,00,00,0,20,1,1,1,03,01,00,4340,00,7,00,0,0,0,1182|3913| Q_[MEM-OP+1],
|1182|3914| GOTO [D TO AC.0]
000,000,0,03,06,1,56,0,54,0,0,00,00,31,00,00,0,20,1,1,1,11,00,00,2237,00,7,00,0,0,0,1183|3915|LSHCR: LSRC [MEM-OP]_[MEM-OP], ;Shift right with Q
|1183|3916| LOOP [LSHCR]
000,000,0,04,14,1,77,0,13,0,0,00,00,00,00,00,0,20,1,1,1,03,01,00,4340,00,7,00,0,0,0,1184|3917| Q_[MEM-OP+1],
|1184|3918| GOTO [D TO AC.0]
|1184|3919|
|1184|3920|;Here for ROT
000,000,1,11,06,1,56,0,54,0,0,00,00,51,00,00,0,20,1,1,1,11,00,00,2241,00,7,00,0,0,0,1185|3921|ROT: ROL [MEM-OP]_[MEM-OP],
|1185|3922| LOOP [ROT]
000,000,0,14,14,0,77,0,54,0,0,00,14,00,00,00,0,20,1,1,1,13,01,00,1420,00,7,04,0,0,0,1186|3923| [MEM-OP]_RAMFILE, ;Write AC
|1186|3924| SET LOCAL,
|1186|3925| GOTOP [IFETCH]
|1186|3926|
000,000,0,01,06,1,56,0,54,0,0,00,00,51,00,00,0,20,1,1,1,11,00,00,2243,00,7,00,0,0,0,1187|3927|ROTR: ROR [MEM-OP]_[MEM-OP],
|1187|3928| LOOP [ROTR]
000,000,0,14,14,0,77,0,54,0,0,00,14,00,00,00,0,20,1,1,1,13,01,00,1420,00,7,04,0,0,0,1188|3929| [MEM-OP]_RAMFILE, ;Write AC
|1188|3930| SET LOCAL,
|1188|3931| GOTOP [IFETCH]
|1188|3932|
|1188|3933|;Here for ROTC
000,000,1,13,06,1,56,0,54,0,0,00,00,75,00,00,0,20,1,1,1,11,00,00,2245,00,7,00,0,0,0,1189|3934|ROTC: ROLC [MEM-OP]_[MEM-OP], ;Rotate left
|1189|3935| LOOP [ROTC]
000,000,0,04,14,1,77,0,13,0,0,00,00,00,00,00,0,20,1,1,1,03,01,00,4340,00,7,00,0,0,0,1190|3936| Q_[MEM-OP+1],
|1190|3937| GOTO [D TO AC.0]
000,000,0,03,06,1,56,0,54,0,0,00,00,75,00,00,0,20,1,1,1,11,00,00,2247,00,7,00,0,0,0,1191|3938|ROTCR: RORC [MEM-OP]_[MEM-OP], ;Rotate right
|1191|3939| LOOP [ROTCR]
000,000,0,04,14,1,77,0,13,0,0,00,00,00,00,00,0,20,1,1,1,03,01,00,4340,00,7,00,0,0,0,1192|3940| Q_[MEM-OP+1],
|1192|3941| GOTO [D TO AC.0]
|1192|3942|
|1192|3943|;Register usage:
|1192|3944|; MEM-OP AC contents
|1192|3945|; AC-OP BLT 1imi t
|1192|3946|;Here for BLT
000,000,0,04,14,0,67,0,40,0,0,00,00,00,00,00,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,1193|3947|BLT: [K 7777.-1]&[E]_B ;Mask E to 30 bits
000,000,0,04,06,1,42,0,50,0,0,00,00,00,00,00,0,20,1,1,1,03,46,00,2264,00,7,00,0,0,0,1194|3948| [E]_[AC-OP], ;Copy final adr
|1194|3949| IF [PXCT] THEN [BLT PXCT]
|1194|3950|.IF/FAST
|1194|3951| SWAP [MEM-OP]_[E RH] ;Make first address to read
000,000,0,04,10,0,56,2,42,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0000,00,7,07,0,0,0,1195|3952| [E]_[W1] ;Copy section number
000,000,0,04,06,1,42,0,00,0,0,00,00,00,00,00,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,1196|3953| [MEM-OP]_[W1 RH] ;Make destination adr
000,000,0,14,02,0,02,0,40,0,0,00,00,00,00,00,0,64,1,1,1,03,02,00,2271,00,7,00,0,0,0,1198|3954| [W1]-[E]-1_F,F_Y, ; Check for "Clear core" case
|1198|3955| IF CT [IZ] THEN [BLT+1]
|1198|3956|.ENDIF/FAST
000,000,0,04,10,0,56,2,42,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,4662,00,7,07,0,0,0,1199|3957|BLT 2: SWAP [MEM-OP]_[E RH], ;Make adr of location to read
|1199|3958| CALL [MEM READ 0] ;Get word to transfer
000,000,0,04,06,1,56,0,42,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,4711,00,7,00,0,0,0,1200|3959| [MEM-OP]_[E RH], ;Make destination adr
|1200|3960| CALL [MEMORY WRITE]
000,000,0,14,02,0,42,0,50,0,0,00,00,00,00,27,0,20,1,0,1,16,00,00,0000,00,7,00,0,0,0,1201|3961| [E]-[AC-OP]_Y,SEL AC+[0],IX_MX
000,000,0,04,03,0,57,0,54,0,1,00,00,00,00,00,0,56,1,1,1,03,03,00,4127,00,7,00,0,0,0,1202|3962| [BIT17]+[MEM-OP]+1_F,F_B, ;Increment pointer
|1202|3963| IF NOT CT [MN] THEN [TO NOWHERE]
000,000,0,14,06,1,56,0,00,0,0,00,00,00,00,00,0,20,1,1,1,03,01,00,2257,00,7,04,0,0,0,1203|3964| [MEM-OP]_Y,ALU_RAMFILE, ;Remember how far we got
|1203|3965| GOTO [BLT 2]
|1203|3966|
000,000,0,04,10,0,56,2,42,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,2417,00,7,07,0,0,0,1204|3967|BLT PXCT:
|1204|3968| SWAP [MEM-OP]_[E RH], ;Make adr of loc to read
|1204|3969| CALL [PXCT FETCH 40]
000,000,0,04,06,1,56,0,42,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,2413,00,7,00,0,0,0,1205|3970| [MEM-OP]_[E RH], ;Make destination adr
|1205|3971| CALL [PXCT STORE 200] ; Copy data
000,000,0,14,02,0,42,0,50,0,0,00,00,00,00,27,0,20,1,0,1,16,00,00,0000,00,7,00,0,0,0,1206|3972| [E]-[AC-OP]_Y,SEL AC+[0],IX_MX
000,000,0,04,03,0,57,0,54,0,1,00,00,00,00,00,0,56,1,1,1,03,03,00,4127,00,7,00,0,0,0,1207|3973| [BIT17]+[MEM-OP]+1_F,F_B, ;Increment pointer
|1207|3974| IF NOT CT [MN] THEN [TO NOWHERE]
000,000,0,14,06,1,56,0,00,0,0,00,00,00,00,00,0,20,1,1,1,03,01,00,2257,00,7,04,0,0,0,1208|3975| [MEM-OP]_Y,ALU_RAMFILE, ;Remember how far we got
|1208|3976| GOTO [BLT 2]
|1208|3977|
|1208|3978|.IF/FAST
|1208|3979|;Here for BLT [#,#+1]
000,000,0,07,06,1,42,0,40,0,0,00,00,00,00,77,0,20,1,1,1,01,01,00,4663,00,7,00,0,0,0,1209|3980|BLT+1: READ [E] ;Fetch first word in block
000,000,0,04,06,1,56,0,42,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,4711,00,7,00,0,0,0,1210|3981| [MEM-OP]_[E RH], ;Write next word
|1210|3982| CALL [MEMORY WRITE]
|1210|3983| GOTO [BLT 14]
000,000,0,04,03,0,57,0,54,0,1,00,00,00,00,00,0,20,1,1,1,01,21,00,4154,00,7,04,0,0,0,1212|3984|BLT+1N: [BIT17]+[MEM-OP]+1_F,F_B,
|1212|3985| ALU_RAMFILE,
|1212|3986| CHECK INTERRUPTS
000,000,0,07,06,1,42,0,40,0,1,00,00,00,00,77,0,20,1,1,1,01,01,00,4712,00,7,00,0,0,0,1213|3987| [E]+1_F,F_Q_[E],
|1213|3988| SPEC SEL/PAGE TABLE ENTRY,
|1213|3989| CALL [MEM WRITE 1]
000,000,0,14,02,0,52,0,40,0,0,00,00,00,00,27,0,76,1,1,1,06,03,00,0000,12,7,00,0,0,0,1214|3990|BLT 14: [AC-OP]-[E]-1_F,F_Y,
|1214|3991| SEL AC+[0],
|1214|3992| IF NOT CT [IN] D [DISPATCH 3]
000,000,0,14,10,0,00,0,00,0,0,00,14,00,00,00,0,20,1,1,0,03,01,00,1420,00,7,00,0,0,0,1215|3993| SET LOCAL,GOTO [IFETCH]
|1215|3994|.ENDIF/FAST
|1215|3995|
|1215|3996|.TOC 2, "Program Control Instructions"
|1215|3997|;Here for AOBJX instructions
000,000,0,04,06,1,56,0,56,0,1,00,00,00,00,00,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,1216|3998|AOBJX: [MEM-OP]+1_[MEM-OP RH] ; Increment RH of AC
000,000,0,04,03,0,57,0,54,0,0,00,00,00,00,00,0,20,1,0,1,06,01,00,0000,12,7,00,0,0,0,1217|3999| [BIT17]+[MEM-OP]_B,IX_MX, ; Increment LH
|1217|4000| DISPATCH [DISPATCH 3]
|1217|4001|
|1217|4002|;Here for JRST
000,000,1,11,06,1,32,0,00,0,0,00,00,11,00,00,0,20,1,1,1,03,06,00,2647,00,7,00,0,0,0,1218|4003|JRST: #2*[IR]_[W1],
|1218|4004| IF [AC.EQ.0] THEN [JXA]
000,000,1,11,03,0,02,0,00,0,0,00,00,11,00,00,0,20,1,1,1,01,01,00,3067,00,7,00,0,0,0,1219|4005| #4*[W1]_B, ;Keep shifting
|1219|4006| CALL [#2*W1_W1 LOAD IR]
000,000,0,04,14,0,67,0,34,0,0,00,00,00,00,77,0,20,1,1,1,06,01,00,0000,17,7,00,0,0,0,1220|4007| [K 7777.-1]&[PC]_B, ;Reduce PC to 30 bits
|1220|4008| SECTION SELECT, ;load SECTION 0 from PC
|1220|4009| DISPATCH [MISC]
|1220|4010|
|1220|4011|;Jump and restore flags from bits 0-12 of the final indirect or index word
|1220|4012|; JRST 2,
000,000,0,04,06,1,32,0,44,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,1447,00,7,00,0,0,0,1221|4013|JRSTF:
|1221|4014|.IF/SILLY
|1221|4015| [IR]_[MB], ;Reseed MB
|1221|4016| CALL [EFA CALC]
|1221|4017|.ENDIF/SILLY
|1221|4018| IF [NOT SECTION 0] THEN [MUUO]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,03,26,00,1637,00,7,00,0,0,0,1222|4019| [E]_[PC RH] ;New PC
000,000,0,01,06,1,47,0,00,0,0,00,00,01,00,00,0,20,1,1,1,03,37,00,2315,00,7,00,0,0,0,1224|4020|JRSTFX: LRS [BIT4]_[W1], ;Make a user mode bit
|1224|4021| IF [EXEC] THEN [MB_PC FLAGS]
|1224|4022| [W1].OR.[MB]_B ;Will still be user mode
000,000,0,04,17,0,02,0,44,0,0,00,00,00,00,00,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,1225|4023| LRS [W1]_[W2] ;Make a user I/O bit
000,000,0,01,06,1,02,0,04,0,0,00,00,01,00,00,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,1226|4024| [PC FLAGS]BAR&[W2]_B ;Make mask for user I/O
000,000,0,04,11,0,03,0,04,0,0,00,00,00,00,00,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,1227|4025| [W2]BAR&[MB]_B ;Prohibit new user I/O
000,000,0,06,03,0,46,0,44,0,0,00,00,00,00,03,0,20,1,1,0,16,00,00,0027,00,7,01,0,0,0,1229|4026|MB_PC FLAGS:
|1229|4027| [MB]+[MB]_Q, ;Make user into bit4
|1229|4028| J[#23B MASK]_RAMFILE ADR
000,000,0,14,14,1,47,0,00,0,0,00,20,00,00,00,0,20,1,0,1,01,45,00,2332,00,7,00,0,0,0,1230|4029| Q&[BIT4]_Y,IX_MX,SET EXEC, ;Latch new exec as MZ
|1230|4030| IF [TOPS10] CALL [ZERO_PC LH] ;Size PC for TOPS10
000,000,0,07,06,1,46,0,04,0,0,00,00,00,00,00,0,44,1,1,0,01,03,00,2322,00,7,04,0,0,0,1231|4031| [MB]_Q RAMFILE_[W2], ;Get mask for allowable flags to set
|1231|4032| IF NOT CT [MZ] CALL [SET USER LATCH]
000,000,0,04,11,1,06,0,03,0,0,00,00,00,00,00,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,1232|4033| [W2]BAR&Q_F,F_[PC FLAGS] ;Set new flags
000,000,0,14,10,0,00,0,00,0,0,00,14,00,00,00,0,20,1,1,0,13,01,00,4130,00,7,00,0,0,0,1233|4034| SET LOCAL,
|1233|4035| GOTOP [TRAP]
|1233|4036|
000,000,0,14,10,0,00,0,00,0,0,00,24,00,00,00,0,20,1,1,0,12,01,00,0000,00,7,00,0,0,0,1234|4037|SET USER LATCH:
|1234|4038| SET USER,RETURN
|1234|4039|
|1234|4040|;JRST 4,
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,01,36,00,3072,00,7,00,0,0,0,1235|4041|HALT: IF [USER] CALL [CHECK IO OK] ;Check if this is legal
|1235|4042| J[HALT INS]_[W1] ;Code fer JRST 4,
000,000,0,04,06,1,42,0,34,0,0,00,00,00,00,00,0,20,1,1,1,13,01,00,1166,00,7,00,0,0,0,1237|4043| [E]_[PC], ;Set new PC from E
|1237|4044| GOTOP [SET HALT CODE]
|1237|4045|
|1237|4046|;Here for a JRST 5,
000,000,0,07,06,1,42,0,40,0,0,00,00,00,00,77,0,20,1,1,1,01,01,00,4663,00,7,00,0,0,0,1238|4047|XJRSTF:
|1238|4048| READ [E] ;Get new flag word
000,000,0,04,06,1,46,0,54,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,4660,00,7,00,0,0,0,1239|4049| [MB]_[MEM-OP], ;Save flag word
|1239|4050| CALL [READ NEXT] ; Get new PC
000,000,0,04,06,1,46,0,34,0,0,00,00,00,00,00,0,20,1,1,1,01,45,00,2332,00,7,00,0,0,0,1240|4051| [MB]_[PC], ;Set new PC
|1240|4052| IF [TOPS10] CALL [ZERO_PC LH]
000,000,0,04,06,1,56,0,44,0,0,00,00,00,00,00,0,20,1,1,1,13,01,00,2310,00,7,00,0,0,0,1241|4053| [MEM-OP]_[MB],
|1241|4054| GOTOP [JRSTFX]
|1241|4055|
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,12,41,00,0000,00,7,00,0,0,0,1242|4056|ZERO_PC LH:
|1242|4057| IF [NOT PAGED] RETURN ;If not paged do not do
000,000,0,04,10,1,00,0,35,0,0,00,00,00,00,00,0,20,1,1,1,12,01,00,0000,00,7,00,0,0,0,1243|4058| ZERO_[PC LH],RETURN ;Be sure only 18 bits
|1243|4059|
|1243|4060|;JRST 6,
000,000,0,07,06,1,42,0,40,0,0,00,00,00,00,77,0,20,1,1,1,01,01,00,4663,00,7,00,0,0,0,1244|4061|XJEN: READ [E] ;Get new flag word
000,000,0,04,06,1,46,0,54,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,4660,00,7,00,0,0,0,1245|4062| [MB]_[MEM-OP], ;Save flag word
|1245|4063| CALL [READ NEXT] ; Get new PC
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,2354,00,7,00,0,0,0,1246|4064|XJNO: CALL [DISMISS INT] ;Dismiss interrupt
|1246|4065| ; If not legal do an MUUO
000,000,0,04,06,1,46,0,34,0,0,00,00,00,00,00,0,20,1,1,1,01,45,00,2332,00,7,00,0,0,0,1247|4066| [MB]_[PC], ;Set new PC
|1247|4067| IF [TOPS10] CALL [ZERO_PC LH]
000,000,0,04,06,1,56,0,44,0,0,00,00,00,00,00,0,20,1,1,1,03,01,00,2315,00,7,00,0,0,0,1248|4068| [MEM-OP]_[MB],
|1248|4069| GOTO [MB_PC FLAGS]
|1248|4070|
|1248|4071|;JRST 7,
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,01,36,00,3072,00,7,00,0,0,0,1249|4072|XPCW: IF [USER] CALL [CHECK IO OK] ;Be sure legal
000,000,0,04,06,1,03,0,44,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,4711,00,7,00,0,0,0,1250|4073| [PC FLAGS]_[MB], ;Save flags
|1250|4074| CALL [MEMORY WRITE]
000,000,0,04,06,1,36,0,44,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,4710,00,7,00,0,0,0,1251|4075| [PC]_[MB],
|1251|4076| CALL [WRITE NEXT]
|1251|4077| CALL [READ NEXT] ;Get new flags
000,000,0,04,06,1,46,0,54,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,4660,00,7,00,0,0,0,1253|4078| [MB]_[MEM-OP], ;Save new flags
|1253|4079| CALL [READ NEXT] ; Get new PC
000,000,0,04,06,1,46,0,34,0,0,00,00,00,00,00,0,20,1,1,1,01,45,00,2332,00,7,00,0,0,0,1254|4080| [MB]_[PC], ;Set new PC
|1254|4081| IF [TOPS10] CALL [ZERO_PC LH]
000,000,0,04,06,1,56,0,44,0,0,00,00,00,00,00,0,20,1,1,1,03,01,00,2315,00,7,00,0,0,0,1255|4082| [MEM-OP]_[MB],
|1255|4083| GOTO [MB_PC FLAGS]
|1255|4084|
|1255|4085|;JRST 10,
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,2354,00,7,00,0,0,0,1256|4086|JRST 10:
|1256|4087| CALL [DISMISS INT]
000,000,0,04,06,1,42,0,34,0,0,00,14,00,00,00,0,20,1,1,1,13,01,00,1420,00,7,00,0,0,0,1257|4088| [E]_[PC],
|1257|4089| SET LOCAL,
|1257|4090| GOTOP [IFETCH]
|1257|4091|
|1257|4092|;JRST 12,
000,000,0,04,06,1,46,0,54,0,0,00,00,00,00,00,0,20,1,1,1,03,26,00,1637,00,7,00,0,0,0,1258|4093|JEN: [MB]_[MEM-OP], ;Save new flags
|1258|4094| IF [NOT SECTION 0] THEN [MUUO] ;Not legal in section 0
000,000,0,04,06,1,42,0,44,0,0,00,00,00,00,00,0,20,1,1,1,13,01,00,2336,00,7,00,0,0,0,1259|4095| [E]_[MB], ;Save new PC
|1259|4096| GOTOP [XJNO]
|1259|4097|
|1259|4098|;Here to dismiss an interrupt
|1259|4099|; If IO not legal will do an MUUO
|1259|4100|; uses Q, W1, W2, updates RF(PI IN PROG) and PI REG
|1259|4101|
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,03,0,20,1,1,0,16,00,00,0557,00,7,01,0,0,0,1260|4102|DISMISS INT:
|1260|4103| J[PI IN PROG]_RAMFILE ADR ;Address of PIs in progress
|1260|4104| J[0100]_[W2] ;Mask for highest PI
000,000,0,07,06,1,06,0,04,0,0,00,00,00,00,00,0,20,1,0,0,01,36,00,3072,00,7,04,0,0,0,1262|4105| [W2]_Q RAMFILE_[W2],IX_MX, ;Put mask in Q, Pis in W2
|1262|4106| IF [USER] CALL [CHECK IO OK] ;Be sure IO is legal
|1262|4107| IF CT [MZ] RETURN ;Check if any PIs in progress
000,000,0,05,14,1,06,0,00,0,0,00,00,51,00,00,0,64,1,1,1,03,02,00,2360,00,7,00,0,0,0,1264|4108|JEN2: Q&[W2]_F,F_Y RORQ_Q,
|1264|4109| IF CT [IZ] THEN [JEN2]
000,000,1,11,14,1,77,0,00,0,0,00,00,51,00,00,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,1265|4110| Q_F,ROL F_B,B SEL/W1 ;Make mask for level
000,000,0,04,11,0,02,0,04,0,0,00,00,00,00,00,0,64,1,1,1,03,03,00,2364,00,7,04,0,0,0,1266|4111| [W1]BAR&[W2]_B,ALU_RAMFILE, ;One less PI in progress
|1266|4112| IF NOT CT [IZ] THEN [JEN3]
000,000,0,04,10,1,00,0,43,0,0,00,00,00,46,00,0,20,1,1,1,12,01,00,0000,00,7,00,0,0,0,1267|4113| ZERO_[PI REG],Y_2914 STATUS,
|1267|4114| RETURN
|1267|4115|
000,000,0,05,14,1,06,0,00,0,0,00,00,51,00,00,0,20,1,0,1,16,00,00,0000,00,7,00,0,0,0,1268|4116|JEN3: Q&[W2]_F,F_Y RORQ_Q,IX_MX
000,000,0,04,03,0,77,0,43,0,0,00,00,00,46,00,0,44,1,1,1,03,02,00,2364,00,7,00,0,0,0,1269|4117| [K -1]+[PI REG]_B,
|1269|4118| Y_2914 STATUS,
|1269|4119| IF CT [MZ] THEN [JEN3]
|1269|4120| RETURN
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,12,01,00,0000,00,7,00,0,0,0,1270|4121|
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,03,26,00,2371,00,7,00,0,0,0,1271|4122|SFM: IF [NOT SECTION 0] THEN [SFM 2] ;Legal in nonzero sections
|1271|4123| IF [USER] CALL [CHECK IO OK] ;Or if IO is 1egal
000,000,0,04,06,1,03,0,54,0,0,00,00,00,00,00,0,20,1,1,1,03,01,00,4371,00,7,00,0,0,0,1273|4124|SFM 2: [PC FLAGS]_[MEM-OP], ;Copy flags and then write them
|1273|4125| GOTO [TO MEM]
|1273|4126|
|1273|4127|;Here for JFFO
000,000,0,04,10,1,00,0,00,0,0,00,00,00,00,00,0,44,1,1,1,03,02,00,2376,00,7,00,0,0,0,1274|4128|JFFO: ZERO_[W1], ;Count leading zeros here
|1274|4129| IF CT [MZ] THEN [JFFO X]
000,000,0,04,06,1,42,0,34,0,0,00,00,00,00,00,0,56,1,1,1,03,02,00,2376,00,7,00,0,0,0,1275|4130| [E]_[PC], ;Take branch
|1275|4131| IF CT [MN] THEN [JFFO X]
000,000,0,04,03,0,56,0,54,0,0,00,00,00,00,00,0,20,1,0,1,16,00,00,0000,00,7,00,0,0,0,1276|4132|JFFO 1: [MEM-OP]+[MEM-OP]_B,IX_MX ;Left shift word
000,000,0,04,06,1,02,0,00,0,1,00,00,00,00,00,0,56,1,1,1,03,03,00,2374,00,7,00,0,0,0,1277|4133| [W1]+1_[W1], ;Count leading zeros
|1277|4134| IF NOT CT [MN] THEN [JFFO 1]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,27,0,20,1,1,0,16,00,01,0000,00,7,00,0,0,0,1278|4135|JFFO X: SEL AC+[1] ;Address AC+1
000,000,0,14,14,0,77,0,00,0,0,00,00,00,00,00,0,20,1,1,1,13,01,00,1420,00,7,04,0,0,0,1279|4136| [W1]_RAMFILE, ;Clear AC+1
|1279|4137| GOTOP [IFETCH]
|1279|4138|
|1279|4139|;Here for JFCL
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,03,0,20,1,1,0,16,00,00,0040,00,7,01,0,0,0,1280|4140|JFCL: J[JFCL MASK]_RAMFILE ADR ;Point to 037777 777777
000,000,1,11,06,1,32,0,00,0,0,00,00,11,00,00,0,20,1,1,1,14,00,00,0003,00,7,00,0,0,0,1281|4141| #2*[IR]_[W1], ;Copy IR and shift left once
|1281|4142| J[3]_CTR
000,000,1,11,03,0,02,0,00,0,0,00,00,11,00,00,0,20,1,1,1,11,00,00,2402,00,7,00,0,0,0,1282|4143|JFCL4: #4*[W1]_B,LOOP [JFCL4] ;Shift copy of IR
000,000,0,04,10,0,00,0,04,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,3134,00,7,04,0,0,0,1283|4144| RAMFILE_[W2], ;Get mask for JFCL test bits
|1283|4145| CALL [W2BAR&W1_B] ; Leave only bits to test
000,000,0,14,14,0,02,0,03,0,0,00,14,00,00,00,0,64,1,1,1,13,02,00,1420,00,7,00,0,0,0,1284|4146| [W1]&[PC FLAGS]_Y, ;Test flag bits
|1284|4147| SET LOCAL,
|1284|4148| IF CT [IZ] THENP [IFETCH]
000,000,0,04,11,0,02,0,03,0,0,00,00,00,00,00,0,20,1,1,1,03,01,00,2647,00,7,00,0,0,0,1285|4149| [W1]BAR&[PC FLAGS]_B, ;Clear flags
|1285|4150| GOTO [JXA]
|1285|4151|
|1285|4152|;Here for XCT
|1285|4153|; MEM-OP contains instruction to execute
000,000,0,06,14,0,76,0,30,0,0,00,00,00,00,00,0,20,1,1,0,03,36,00,1435,00,7,00,0,0,0,1286|4154|XCT: [K -1.0]&[IR]_Q, ; In case this is PXCT
|1286|4155| IF [USER] THEN [IFETCH 4]
000,000,0,04,14,1,77,0,60,0,0,00,00,00,00,00,0,20,1,1,1,03,06,00,1435,00,7,00,0,0,0,1287|4156| Q_[PXCT], ;In case this is PXCT
|1287|4157| IF [AC.EQ.0] THEN [IFETCH 4] ;If plain just do it
000,000,0,04,06,1,56,0,30,0,0,00,64,00,00,00,0,20,1,1,1,13,01,00,1441,00,7,11,0,0,0,1288|4158| [MEM-OP]_[IR],SET PXCT,LOAD IR, ;Set flag this is PXCT
|1288|4159| GOTOP [IFETCH PXCT]
|1288|4160|
000,000,0,04,10,1,00,0,62,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0040,00,7,01,0,0,0,1289|4161|PXCT STORE 40:
|1289|4162| J[0040]_[PXCT RH]
|1289|4163| GOTO [PXCT STORE]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,03,01,00,2414,00,7,00,0,0,0,1290|4164|
|1290|4165|;Here for usual case of writing operands to memory
000,000,0,04,10,1,00,0,62,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0200,00,7,01,0,0,0,1291|4166|PXCT STORE 200:
|1291|4167| J[0200]_[PXCT RH] ;Flavour of store
|1291|4168| ;GOTO [PXCT STORE]
|1291|4169|
|1291|4170|;Here when doing memory write under PXCT
|1291|4171|; Cali J[testbit]_[PXCT RH]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,2432,00,7,00,0,0,0,1292|4172|PXCT STORE:
|1292|4173| CALL [SET PXCT CTXT]
000,000,0,07,14,0,67,0,40,0,0,00,00,00,00,77,0,20,1,1,1,01,01,00,4711,00,7,00,0,0,0,1293|4174| [K 7777.-1]&[E]_F,F_Q_B, ;Get 1st operand
|1293|4175| SPEC SEL/PAGE TABLE ENTRY,
|1293|4176| CALL [MEMORY WRITE]
|1293|4177| GOTO [SET CURRENT CTXT]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,03,01,00,2424,00,7,00,0,0,0,1294|4178|
000,000,0,04,10,1,00,0,62,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0040,00,7,01,0,0,0,1295|4179|PXCT FETCH 40:
|1295|4180| J[0040]_[PXCT RH]
|1295|4181| GOTO [PXCT FETCH]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,03,01,00,2422,00,7,00,0,0,0,1296|4182|
|1296|4183|;Here for usual PXCT FETCH (i.e. 200)
000,000,0,04,10,1,00,0,62,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0200,00,7,01,0,0,0,1297|4184|PXCT FETCH 200:
|1297|4185| J[0200]_[PXCT RH] ;Flavour of fetch
|1297|4186| ;GOTO [PXCT FETCH]
|1297|4187|
|1297|4188|;Here when doing a memory read under PXCT
|1297|4189|; Call J[testbit]_[PXCT RH]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,2432,00,7,00,0,0,0,1298|4190|PXCT FETCH:
|1298|4191| CALL [SET PXCT CTXT]
000,000,0,07,14,0,67,0,40,0,0,00,00,00,00,77,0,20,1,1,1,01,01,00,4663,00,7,00,0,0,0,1299|4192| [K 7777.-1]&[E]_F,F_Q_B, ;Get 1st operand
|1299|4193| SPEC SEL/PAGE TABLE ENTRY,
|1299|4194| CALL [MEMORY READ]
|1299|4195| ;GOTO [SET CURRENT CTXT]
|1299|4196|
|1299|4197|;Here to set current context
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,03,0,20,1,1,0,16,00,00,0562,00,7,01,0,0,0,1300|4198|SET CURRENT CTXT:
|1300|4199| J[PROC REG]_RAMFILE ADR ;Get what AC blocks should be
000,000,0,04,10,0,00,0,05,0,0,00,20,00,00,00,0,20,1,1,0,16,00,00,0000,00,7,04,0,0,0,1301|4200| RAMFILE_[W2 LH],
|1301|4201| CLEAR USER
|1301|4202| J[RF PROC REG]_RAMFILE ADR ;Get current proc reg
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,03,0,20,1,1,0,16,00,00,0563,00,7,01,0,0,0,1302|4203| RAMFILE_[W2 RH]
000,000,0,14,06,1,06,0,00,0,0,00,00,00,00,00,0,20,1,1,1,16,00,00,0000,00,7,10,0,0,0,1304|4204| [W2]_Y,ALU_PROC REG ;Set proper processor reg
000,000,0,14,14,0,77,0,04,0,0,00,00,00,00,00,0,20,1,1,1,12,01,00,0000,00,7,04,0,0,0,1305|4205| [W2]_RAMFILE,
|1305|4206| RETURN
|1305|4207|
000,000,0,04,10,0,62,2,00,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0000,00,7,07,0,0,0,1306|4208|SET PXCT CTXT:
|1306|4209| SWAP [PXCT]_[W1] ;Copy test bits
000,000,0,14,14,0,02,0,60,0,0,00,00,00,00,00,0,64,1,1,1,12,02,00,0000,00,7,00,0,0,0,1307|4210| [W1]&[PXCT]_Y,
|1307|4211| IF CT [IZ] RETURN
|1307|4212| ;GOTO [SET PREV CTXT]
|1307|4213|
|1307|4214|;Here to set previous context
|1307|4215|;Called only in exec mode !!
|1307|4216| J[04000]_[W1] ;bit 24
000,000,0,04,10,1,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,4000,00,7,01,0,0,0,1308|4217| SWAP [W1]_[W1] ;becomes bit 6-prev context user
000,000,0,14,14,0,02,0,03,0,0,00,00,00,00,00,0,20,1,0,1,16,00,00,0000,00,7,00,0,0,0,1310|4218| [W1]&[PC FLAGS]_Y,IX_MX ;See if he can do this
|1310|4219| J[RF PROC REG]_RAMFILE ADR ;Address last value of PROC REG
000,000,0,04,10,0,00,0,00,0,0,00,00,00,00,00,0,44,1,1,0,01,03,00,2322,00,7,04,0,0,0,1312|4220| RAMFILE_[W1], ;Get last PROC REG
|1312|4221| IF NOT CT [MZ] CALL [SET USER LATCH]
|1312|4222| #2*([W1]+[W1 LH])_B ;Shift left twice
000,000,1,11,03,0,02,0,01,0,0,00,00,11,00,00,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,1313|4223| #2*[W1]_[W1 LH] ;Puts prev AC in position
000,000,1,11,06,1,02,0,01,0,0,00,00,11,00,00,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,1314|4224| [W1]_RAMFILE ;In case clock interrupts
000,000,0,14,06,1,02,0,00,0,0,00,00,00,00,00,0,20,1,1,1,12,01,00,0000,00,7,10,0,0,0,1316|4225| [W1]_Y,ALU_PROC REG,
|1316|4226| RETURN
|1316|4227| ;RAMFILE [E LH], ;Get previous section
|1316|4228| ;J[PCS]_RAMFILE ADR ;Remember previous section
|1316|4229|
|1316|4230|;Here for MAP
000,000,0,04,14,0,67,0,40,0,0,00,00,00,00,77,0,20,1,1,1,01,36,00,3072,00,7,00,0,0,0,1317|4231|MAP: [K 7777.-1]&[E]_B, ;Strip E to 30 bits
|1317|4232| SPEC SEL/PAGE TABLE ENTRY, ; Set section flags
|1317|4233| IF [USER] CALL [CHECK IO OK] ;Be sure allowed to do this
|1317|4234| J[MAP 3]_[W1]
000,000,0,04,10,1,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,2451,00,7,01,0,0,0,1318|4235| CALL [SET PF RCOVR]
000,000,0,04,10,1,00,0,00,0,0,00,00,00,00,00,0,12,0,1,1,01,40,00,4426,00,7,00,0,0,0,1320|4236| ZERO_[W1],#0_UC,
|1320|4237| IF [PAGED] CALL [PAGE R REFIL] ;Get page info for E
000,000,0,04,14,0,72,0,40,0,0,00,00,00,00,27,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,1321|4238|MAP 3: [K 777]&[E]_B,SEL AC+[0] ;Leave only on page portion
|1321|4239| J[01000]_[W2] ;Will become V bit
000,000,0,04,10,0,06,2,04,0,0,00,00,00,00,00,0,20,1,1,0,01,40,00,3140,00,7,07,0,0,0,1323|4240| SWAP [W2]_[W2], ;Make bit8 = V bit
|1323|4241| IF [PAGED] CALL [W2.OR.W1]
000,000,0,04,17,0,42,0,00,0,0,00,14,00,00,00,0,20,1,1,1,13,01,00,1420,00,7,04,0,0,0,1324|4242| [E].OR.[W1]_B,ALU_RAMFILE, ;Add on page portion
|1324|4243| SET LOCAL,GOTOP [IFETCH]
|1324|4244|
|1324|4245|.TOC 2, "Stack Operation Instructions"
|1324|4246|
|1324|4247|;Here for ADJSP after FETCH AC&I and CHK PC SECT
|1324|4248|
000,000,0,14,14,0,73,0,50,0,0,00,00,00,00,27,0,20,1,0,1,06,27,00,0000,13,7,00,0,0,0,1325|4249|ADJSP: [K 407777.0]&[AC-OP]_Y,IX_MX, ;Latch sign of stack pointer
|1325|4250| SEL AC+[0], ; Address AC
|1325|4251| IF [SECTION 0] D [DISPATCH 4] ; D4 = ADJSP V
000,000,0,14,10,0,00,0,00,0,0,00,14,00,00,00,0,40,1,1,0,03,02,00,2461,00,7,00,0,0,0,1326|4252| SET LOCAL,
|1326|4253| IF CT [(MNxMOVR)!MZ] THEN [ADJSP V]
000,000,0,04,03,0,52,0,54,0,0,00,00,00,00,00,0,20,1,1,1,03,57,00,4343,00,7,04,0,0,0,1327|4254| [AC-OP]+[MEM-OP]_B,ALU_RAMFILE, ;Add adjustment
|1327|4255| IF [NOT B BIT 18] THEN [TO AC]
000,000,0,04,03,0,76,0,54,0,0,00,00,00,00,00,0,20,1,1,1,03,01,00,4343,00,7,04,0,0,0,1328|4256| [K -1.0]+[MEM-OP]_B,ALU_RAMFILE,
|1328|4257| GOTO [TO AC]
|1328|4258|
000,000,0,04,03,0,56,0,52,0,0,00,14,00,00,00,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,1329|4259|ADJSP V:
|1329|4260| [MEM-OP]+[AC-OP RH]_B, ;Adjust RH
|1329|4261| SET LOCAL
|1329|4262| SWAP [MEM-OP]_[MEM-OP] ;Prepare to add to LH
000,000,0,04,03,0,56,0,50,0,0,00,00,00,00,00,0,16,1,1,1,03,03,00,1420,00,7,04,0,0,0,1331|4263| [MEM-OP]+[AC-OP]_B,ALU_RAMFILE,
|1331|4264| IF NOT CT [INxorMN] THEN [IFETCH]
000,000,0,14,06,1,56,0,00,0,0,00,00,00,00,00,0,16,1,1,1,01,02,00,4147,00,7,00,0,0,0,1332|4265| [MEM-OP]_Y, ;Compare sign of E to AC
|1332|4266| IF CT [INxorMN] CALL [SET TRAP 2]
|1332|4267| GOTO [TRAP]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,03,01,00,4130,00,7,00,0,0,0,1333|4268|
|1333|4269|;Here for PUSHJ
|1333|4270|; CHK PS SECT loaded SECTION 0 from PC and loaded MB with PC
000,000,0,04,06,1,42,0,13,0,0,00,00,00,00,00,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,1334|4271|PUSHJ: [E]_[MEM-OP+1] ;Save adr where we will go
000,000,0,06,06,1,03,0,00,0,0,00,00,00,00,03,0,20,1,1,0,16,00,00,0145,00,7,01,0,0,0,1335|4272| [PC FLAGS]_Q, ;Save pc flags fer sectO case
|1335|4273| J[PUSHJ FLAGS]_RAMFILE ADR ;Adr of mask for flags to clear
000,000,0,04,10,0,00,0,24,0,0,00,00,00,00,00,0,20,1,1,0,03,27,00,2500,00,7,04,0,0,0,1336|4274| RAMFILE_[W6], ;Get mask
|1336|4275| IF [SECTION 0] THEN [PUSHJ VANILLA]
000,000,0,14,14,0,73,0,54,0,0,00,00,00,00,00,0,20,1,0,1,16,00,00,0000,00,7,00,0,0,0,1337|4276| [K 407777.0]&[MEM-OP]_Y, ;Check for which extended case
|1337|4277| IX_MX
|1337|4278| SWAP [K 777]_[W1] ;9bit mask for PC section
000,000,0,04,10,0,72,2,00,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0000,00,7,07,0,0,0,1338|4279| ; PC sect to 9 bits (strange but ok)
000,000,0,04,14,0,02,0,45,0,0,00,00,00,00,00,0,40,1,1,1,03,02,00,2501,00,7,00,0,0,0,1339|4280| [W1]&[MB LH]_B, ;We are going to write PC in memory
|1339|4281| IF CT [(MNxMOVR)!MZ] THEN [PJ H]
000,000,0,04,06,1,56,0,54,0,1,00,10,00,00,00,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,1340|4282| [MEM-OP]+1_[MEM-OP],SET GLOBAL ;Increment pointer
|1340|4283| WRITE [MEM-OP]
000,000,0,04,11,0,26,0,03,0,0,00,00,00,00,27,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,1342|4284| [W6]BAR&[PC FLAGS]_B, ;Clear flags
|1342|4285| SEL AC+[0] ;Select AC to restore pointer
000,000,0,04,06,1,13,0,34,0,0,00,00,00,00,00,0,20,1,1,1,03,01,00,4343,00,7,00,0,0,0,1343|4286| [MEM-OP+1]_[PC],
|1343|4287| GOTO [TO AC]
|1343|4288|
000,000,0,04,14,1,77,0,45,0,0,00,00,00,00,00,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,1344|4289|PUSHJ VANILLA:
|1344|4290| Q_[MB LH] ;<PC flags,,PC> in MB
000,000,0,04,03,0,57,0,55,0,0,00,00,00,00,00,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,1345|4291|PJ H: [BIT17]+[MEM-OP LH]_B ;Increment LH
|1345|4292| [MEM-OP]+1_[MEM-OP RH] ;Increment RH of AC
000,000,0,04,06,1,56,0,42,0,0,00,14,00,00,00,0,20,1,1,1,01,01,00,4711,00,7,00,0,0,0,1347|4293| [MEM-OP]_[E RH],SET LOCAL, ;Address to write into
|1347|4294| CALL [MEMORY WRITE]
000,000,0,14,14,0,76,0,54,0,0,00,00,00,00,27,0,20,1,0,1,16,00,00,0000,00,7,00,0,0,0,1348|4295| [K -1.0]&[MEM-OP]_Y,
|1348|4296| IX_MX,SEL AC+[0] ;Check for overflow
|1348|4297| [W6]BAR&[PC FLAGS]_B ;Clear flags
000,000,0,04,06,1,13,0,34,0,0,00,14,00,00,00,0,44,1,1,1,13,03,00,4343,00,7,00,0,0,0,1350|4298| [MEM-OP+1]_[PC], ;Perform branch
|1350|4299| SET LOCAL,
|1350|4300| IF NOT CT [MZ] THENP [TO AC]
000,000,0,14,06,1,56,0,00,0,0,00,00,00,00,00,0,20,1,1,1,03,01,00,2526,00,7,04,0,0,0,1351|4301| [MEM-OP]_Y,ALU_RAMFILE, ;Update pointer
|1351|4302| GOTO [PUSH TRAP] ;Set trap flags
|1351|4303|
|1351|4304|;Here to check PC section, set MZ if section 0
000,000,0,04,06,1,36,0,44,0,0,00,00,00,00,77,0,20,1,1,1,06,01,00,0000,12,7,00,0,0,0,1352|4305|CHK PC SECT:
|1352|4306| [PC]_[MB],SECTION SELECT, ;Select our section
|1352|4307| DISPATCH [DISPATCH 3]
|1352|4308|
|1352|4309|
|1352|4310|;Here for PUSH
|1352|4311|; CHK PC SECT loaded SECTION 0 from PC
000,000,0,14,06,1,36,0,00,0,0,00,00,00,00,77,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,1353|4312|PUSH: [PC]_Y,SECTION SELECT ;Select our section
000,000,0,14,14,0,73,0,50,0,0,00,00,00,00,00,0,20,1,0,1,03,27,00,2520,00,7,00,0,0,0,1354|4313| [K 407777.0]&[AC-OP]_Y, ;Test for extended case
|1354|4314| IX_MX,
|1354|4315| IF [SECTION 0] THEN [PUSH VANILLA]
|1354|4316| IF CT [(MNxMOVR)!MZ] THEN [PUSH VANILLA]
000,000,0,04,06,1,52,0,40,0,1,00,00,00,00,00,0,20,1,1,1,01,46,00,2411,00,7,00,0,0,0,1356|4317| [AC-OP]+1_[E], ;New stack address
|1356|4318| IF [PXCT] CALL [PXCT STORE 40]
000,000,0,07,14,0,67,0,40,0,0,00,00,00,00,77,0,20,1,1,1,01,47,00,4712,00,7,00,0,0,0,1357|4319| [K 7777.-1]&[E]_F,F_Q_B,
|1357|4320| SPEC SEL/PAGE TABLE ENTRY,
|1357|4321| IF [NOT PXCT] CALL [MEM WRITE 1]
|1357|4322| SEL AC+[0] ;Address AC
000,000,0,14,06,1,52,0,00,0,1,00,10,00,00,00,0,20,1,1,1,13,01,00,1420,00,7,04,0,0,0,1359|4323| [AC-OP]+1_Y,ALU_RAMFILE, ;Update AC
|1359|4324| CLEAR LOCAL,
|1359|4325| GOTOP [IFETCH]
000,000,0,04,03,0,57,0,51,0,0,00,00,00,00,00,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,1360|4326|PUSH VANILLA:
|1360|4327| [BIT17]+[AC-OP LH]_B ; Increment LH of stack pointer
|1360|4328| [AC-OP]+1_[AC-OP RH] ; Increment RH
000,000,0,04,06,1,52,0,42,0,0,00,00,00,00,00,0,20,1,1,1,01,46,00,2411,00,7,00,0,0,0,1362|4329| [AC-OP]_[E RH], ;Set in section address
|1362|4330| IF [PXCT] CALL [PXCT STORE 40]
000,000,0,07,14,0,67,0,40,0,0,00,00,00,00,77,0,20,1,1,1,01,47,00,4712,00,7,00,0,0,0,1363|4331| [K 7777.-1]&[E]_F,F_Q_B, ; Data already in MB
|1363|4332| SPEC SEL/PAGE TABLE ENTRY,
|1363|4333| IF [NOT PXCT] CALL [MEM WRITE 1]
000,000,0,14,14,0,76,0,50,0,0,00,00,00,00,27,0,20,1,0,1,16,00,00,0000,00,7,00,0,0,0,1364|4334| [K -1.0]&[AC-OP]_Y, ;Check for overflow
|1364|4335| IX_MX,SEL AC+[0] ; Address AC to restore updated version
000,000,0,14,14,0,77,0,50,0,0,00,14,00,00,00,0,44,1,1,1,13,03,00,1420,00,7,04,0,0,0,1365|4336| [AC-OP]_RAMFILE, ;Restore stack pointer
|1365|4337| SET LOCAL,
|1365|4338| IF NOT CT [MZ] THENP [IFETCH]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,4147,00,7,00,0,0,0,1366|4339|PUSH TRAP:
|1366|4340| CALL [SET TRAP 2] ;Set trap 2 flag
000,000,0,14,10,0,00,0,00,0,0,00,14,00,00,00,0,20,1,1,0,13,01,00,4130,00,7,00,0,0,0,1367|4341| SET LOCAL,GOTOP [TRAP]
|1367|4342|
|1367|4343|
|1367|4344|;Here for POP after CHK PC SECT
000,000,0,14,14,0,73,0,54,0,0,00,00,00,00,00,0,20,1,0,1,03,27,00,2547,00,7,00,0,0,0,1368|4345|POP: [K 407777.0]&[MEM-OP]_Y,IX_MX, ;Test stack pointer
|1368|4346| IF [SECTION 0] THEN [POP VANILLA]
000,000,0,04,06,1,42,0,24,0,0,00,00,00,00,00,0,40,1,1,1,03,02,00,2550,00,7,00,0,0,0,1369|4347| [E]_[W6], ;Save effective address
|1369|4348| IF CT [(MNxMOVR)!MZ] THEN [POP V 1]
000,000,0,07,06,1,56,0,40,0,0,00,00,00,00,00,0,20,1,1,1,03,35,00,2536,00,7,00,0,0,0,1370|4349| [MEM-OP]_Q_[E], ;Address of stack data
|1370|4350| IF [GLOBAL] THEN [POP 3]
000,000,0,04,14,0,67,0,40,0,0,00,10,00,00,00,0,20,1,1,1,01,46,00,2417,00,7,00,0,0,0,1371|4351| [K 7777.-1]&[E]_B,CLEAR LOCAL,
|1371|4352| IF [PXCT] CALL [PXCT FETCH 40]
000,000,0,07,06,1,42,0,40,0,0,00,00,00,00,77,0,20,1,1,1,01,47,00,4663,00,7,00,0,0,0,1372|4353| [E]_Q_[E],
|1372|4354| SPEC SEL/PAGE TABLE ENTRY,
|1372|4355| IF [NOT PXCT] CALL [MEMORY READ]
000,000,0,14,10,0,00,0,00,0,0,00,14,00,00,00,0,20,1,1,0,03,01,00,2540,00,7,00,0,0,0,1373|4356| SET LOCAL,GOTO [POP 5] ;Restore effective address
000,000,0,04,14,0,67,0,40,0,0,00,00,00,00,00,0,20,1,1,1,01,46,00,2417,00,7,00,0,0,0,1374|4357|POP 3: [K 7777.-1]&[E]_B, ;Read location off stack
|1374|4358| IF [PXCT] CALL [PXCT FETCH 40]
000,000,0,07,06,1,42,0,40,0,0,00,00,00,00,77,0,20,1,1,1,01,47,00,4663,00,7,00,0,0,0,1375|4359| [E]_Q_[E],
|1375|4360| SPEC SEL/PAGE TABLE ENTRY,
|1375|4361| IF [NOT PXCT] CALL [MEMORY READ] ;Read location off stack
000,000,0,04,06,1,26,0,40,0,0,00,00,00,00,00,0,20,1,1,1,01,46,00,2413,00,7,00,0,0,0,1376|4362|POP 5: [W6]_[E],
|1376|4363| IF [PXCT] CALL [PXCT STORE 200]
000,000,0,07,14,0,67,0,40,0,0,00,00,00,00,77,0,20,1,1,1,01,47,00,4712,00,7,00,0,0,0,1377|4364| [K 7777.-1]&[E]_F,F_Q_B,
|1377|4365| SPEC SEL/PAGE TABLE ENTRY,
|1377|4366| IF [NOT PXCT] CALL [MEM WRITE 1]
|1377|4367| SEL AC+[0]
000,000,0,14,03,0,77,0,54,0,0,00,14,00,00,00,0,20,1,1,1,13,01,00,1420,00,7,04,0,0,0,1379|4368| [K -1]+[MEM-OP]_Y, ;Decrement stack pointer
|1379|4369| ALU_RAMFILE,
|1379|4370| SET LOCAL,
|1379|4371| GOTOP [IFETCH] ;Store stack pointer
|1379|4372|
000,000,0,04,06,1,56,0,42,0,0,00,14,00,00,00,0,20,1,1,1,01,46,00,2417,00,7,00,0,0,0,1380|4373|POP V 3:
|1380|4374| [MEM-OP]_[E RH],SET LOCAL, ;Get in section address
|1380|4375| IF [PXCT] CALL [PXCT FETCH 40]
000,000,0,07,14,0,67,0,40,0,0,00,00,00,00,77,0,20,1,1,1,01,47,00,4663,00,7,00,0,0,0,1381|4376| [K 7777.-1]&[E]_F,F_Q_B, ;Get data from stack
|1381|4377| SPEC SEL/PAGE TABLE ENTRY,
|1381|4378| IF [NOT PXCT] CALL [MEMORY READ]
000,000,0,14,10,0,00,0,00,0,0,00,10,00,00,00,0,20,1,1,0,03,01,00,2553,00,7,00,0,0,0,1382|4379| SET GLOBAL,
|1382|4380| GOTO [POP V 5]
|1382|4381|
000,000,0,04,06,1,42,0,24,0,0,00,00,00,00,00,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,1383|4382|POP VANILLA:
|1383|4383| [E]_[W6] ;Save effective address
|1383|4384|
000,000,0,04,06,1,36,0,40,0,0,00,00,00,00,00,0,20,1,1,1,03,35,00,2544,00,7,00,0,0,0,1384|4385|POP V 1:
|1384|4386| [PC]_[E], ;Copy pdl section number
|1384|4387| IF [GLOBAL] THEN [POP V 3]
000,000,0,04,06,1,56,0,42,0,0,00,14,00,00,00,0,20,1,1,1,01,46,00,2417,00,7,00,0,0,0,1385|4388| [MEM-OP]_[E RH],SET LOCAL, ;Get in section address
|1385|4389| IF [PXCT] CALL [PXCT FETCH 40]
000,000,0,07,14,0,67,0,40,0,0,00,00,00,00,77,0,20,1,1,1,01,47,00,4663,00,7,00,0,0,0,1386|4390| [K 7777.-1]&[E]_F,F_Q_B, ;Get data from stack
|1386|4391| SPEC SEL/PAGE TABLE ENTRY,
|1386|4392| IF [NOT PXCT] CALL [MEMORY READ]
000,000,0,04,06,1,26,0,40,0,0,00,00,00,00,00,0,20,1,1,1,01,46,00,2413,00,7,00,0,0,0,1387|4393|POP V 5:
|1387|4394| [W6]_[E],
|1387|4395| IF [PXCT] CALL [PXCT STORE 200]
000,000,0,07,14,0,67,0,40,0,0,00,00,00,00,77,0,20,1,1,1,01,47,00,4712,00,7,00,0,0,0,1388|4396| [K 7777.-1]&[E]_F,F_Q_B,
|1388|4397| SPEC SEL/PAGE TABLE ENTRY,
|1388|4398| IF [NOT PXCT] CALL [MEM WRITE 1]
|1388|4399| ;GOTO [POP V PNTR]
000,000,0,14,14,0,76,0,54,0,0,00,00,00,00,00,0,20,1,0,1,16,00,00,0000,00,7,00,0,0,0,1389|4400|POP V PNTR:
|1389|4401| [K -1.0]&[MEM-OP]_Y, ;Check for overflow
|1389|4402| IX_MX
000,000,0,04,01,0,57,0,54,0,1,00,00,00,00,27,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,1390|4403| [MEM-OP]-[BIT17]_A,SEL AC+[0] ;Decrement LH
000,000,0,04,03,0,77,0,56,0,0,00,14,00,00,00,0,44,1,1,1,13,03,00,4343,00,7,00,0,0,0,1391|4404| [K -1]+[MEM-OP RH]_B, ;Decrement RH of pointer
|1391|4405| SET LOCAL,
|1391|4406| IF NOT CT [MZ] THENP [TO AC]
000,000,0,14,14,0,77,0,54,0,0,00,00,00,00,00,0,20,1,1,1,03,01,00,2526,00,7,04,0,0,0,1392|4407| [MEM-OP]_RAMFILE, ;Store updated pointer
|1392|4408| GOTO [PUSH TRAP] ; Then trap
|1392|4409|
|1392|4410|;Here for POPJ
000,000,0,14,11,0,76,0,30,0,0,00,00,00,00,00,0,64,1,1,1,03,03,00,1637,00,7,00,0,0,0,1393|4411|POPJ:
|1393|4412|.IF/FTMBZ
|1393|4413| [K -1.0]BAR&[IR]_Y, ;E should be 0
|1393|4414| IF NOT CT [IZ] THEN [MUUO]
|1393|4415|.ENDIF/FTMBl
000,000,0,14,14,0,73,0,54,0,0,00,00,00,00,00,0,20,1,0,1,03,26,00,2565,00,7,00,0,0,0,1394|4416| [K 407777.0]&[MEM-OP]_Y, ;Test stack pointer
|1394|4417| IX_MX,
|1394|4418| IF [NOT SECTION 0] THEN [POPJ 1]
000,000,0,04,06,1,56,0,42,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,4662,00,7,00,0,0,0,1395|4419| [MEM-OP]_[E RH], ;Fetch new PC
|1395|4420| CALL [MEM READ 0]
000,000,0,04,06,1,46,0,36,0,0,00,00,00,00,00,0,20,1,1,1,03,01,00,2555,00,7,00,0,0,0,1396|4421| [MB]_[PC RH], ;Set new PC
|1396|4422| GOTO [POP V PNTR]
|1396|4423|
000,000,0,04,06,1,56,0,42,0,0,00,14,00,00,00,0,40,1,1,1,03,03,00,2570,00,7,00,0,0,0,1397|4424|POPJ 1: [MEM-OP]_[E RH],SET LOCAL,
|1397|4425| IF NOT CT [(MNxMOVR)!MZ] THEN [POPJ 2]
|1397|4426| READ [E] ;Fetch new PC
000,000,0,04,06,1,46,0,34,0,0,00,00,00,00,00,0,20,1,1,1,03,01,00,2555,00,7,00,0,0,0,1399|4427| [MB]_[PC], ;Set new PC
|1399|4428| GOTO [POP V PNTR]
|1399|4429|
000,000,0,04,06,1,56,0,40,0,0,00,10,00,00,00,0,20,1,1,1,01,01,00,4662,00,7,00,0,0,0,1400|4430|POPJ 2: [MEM-OP]_[E],SET GLOBAL, ;Stack address
|1400|4431| CALL [MEM READ 0] ;Fetch new PC
000,000,0,04,06,1,46,0,34,0,0,00,00,00,00,27,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,1401|4432| [MB]_[PC], ;Set new PC
|1401|4433| SEL AC+[0]
000,000,0,14,03,0,77,0,54,0,0,00,14,00,00,00,0,20,1,1,1,13,01,00,1420,00,7,04,0,0,0,1402|4434| [K -1]+[MEM-OP]_Y, ;Save new AC
|1402|4435| ALU_RAMFILE,
|1402|4436| SET LOCAL,
|1402|4437| GOTOP [IFETCH]
|1402|4438|
|1402|4439|;Here to put flags & PC in MB or PC in MB depending on section
|1402|4440|; First part of JSR and JSP
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,03,0,20,1,1,0,16,00,00,0145,00,7,01,0,0,0,1403|4441|JSR SETUP:
|1403|4442| J[PUSHJ FLAGS]_RAMFILE ADR
000,000,0,04,10,0,00,0,20,0,0,00,00,00,00,00,0,20,1,1,0,03,27,00,2576,00,7,04,0,0,0,1404|4443| RAMFILE_[W5], ;Get bits to clear from flags
|1404|4444| IF [SECTION 0] THEN [JSR SECT 0]
000,000,0,04,14,0,67,0,44,0,0,00,00,00,00,27,0,20,1,1,1,06,01,00,0000,11,7,00,0,0,0,1405|4445| [K 7777.-1]&[MB]_B, ;Mask off bits 0-5
|1405|4446| SEL AC+[0],
|1405|4447| DISPATCH [INST EXCT]
000,000,0,04,06,1,03,0,45,0,0,00,00,00,00,27,0,20,1,1,1,06,01,00,0000,11,7,00,0,0,0,1406|4448|JSR SECT 0:
|1406|4449| [PC FLAGS]_[MB LH],SEL AC+[0], ;Put flags in memory lh
|1406|4450| DISPATCH [INST EXCT]
|1406|4451|
|1406|4452|
|1406|4453|;Here for JSR
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,03,07,00,1637,00,7,00,0,0,0,1407|4454|JSR:
|1407|4455|.IF/FTMBZ
|1407|4456| IF [AC.NE.0] THEN [MUUO] ;AC field should be 0
|1407|4457|.ENDIF/FTMBZ
|1407|4458| CALL [MEMORY WRITE] ;MB already setup by JSR SETUP
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,4711,00,7,00,0,0,0,1408|4459| [E]+1_[E RH] ;Go to next location
000,000,0,04,06,1,42,0,42,0,1,00,00,00,00,00,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,1409|4460|
000,000,0,04,11,0,22,0,03,0,0,00,00,00,00,00,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,1410|4461|JSR CLEAR FLAGS:
|1410|4462| [W5]BAR&[PC FLAGS]_B ;Clear 1st part done, Address failure
|1410|4463| ; inhibit, and trap flags
000,000,0,04,06,1,42,0,34,0,0,00,14,00,00,00,0,20,1,1,1,13,01,00,1420,00,7,00,0,0,0,1411|4464| [E]_[PC],SET LOCAL, ;Set new PC
|1411|4465| GOTOP [IFETCH]
|1411|4466|
|1411|4467|;Here for JSP
000,000,0,14,14,0,77,0,44,0,0,00,00,00,00,00,0,20,1,1,1,03,01,00,2602,00,7,04,0,0,0,1412|4468|JSP: [MB]_RAMFILE, ;Write AC and exit
|1412|4469| GOTO [JSR CLEAR FLAGS]
|1412|4470|
|1412|4471|
|1412|4472|;Here for JSA
|1412|4473|
000,000,0,04,06,1,56,0,44,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,4711,00,7,00,0,0,0,1413|4474|JSA: [MEM-OP]_[MB], ;Copy AC to write in E
|1413|4475| CALL [MEMORY WRITE]
|1413|4476| SWAP [E]_[MEM-OP] ;Put E rh in mem lh
000,000,0,04,10,0,42,2,54,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0000,00,7,07,0,0,0,1414|4477| [PC]_[MEM-OP RH] ;Put PC rh in mem rh
000,000,0,04,06,1,36,0,56,0,0,00,00,00,00,00,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,1415|4478| [E]_[PC] ;Set new PC
000,000,0,04,06,1,36,0,36,0,1,00,00,00,00,00,0,20,1,1,1,03,01,00,4342,00,7,00,0,0,0,1417|4479| [PC]+1_[PC RH], ;Make E+1 new PC
|1417|4480| GOTO [TO AC.0]
|1417|4481|
|1417|4482|;Here for JRA
000,000,0,04,06,1,42,0,24,0,0,00,00,00,00,00,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,1418|4483|JRA: [E]_[W6] ;Save E
000,000,0,04,10,0,56,2,42,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,4662,00,7,07,0,0,0,1419|4484| SWAP [MEM-OP]_[E RH], ;Address to load AC with
|1419|4485| CALL [MEM READ 0]
000,000,0,04,06,1,26,0,34,0,0,00,00,00,00,27,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,1420|4486| [W6]_[PC],SEL AC+[0] ;Set new PC
000,000,0,14,06,1,46,0,00,0,0,00,14,00,00,00,0,20,1,1,1,03,01,00,1420,00,7,04,0,0,0,1421|4487| [MB]_Y,ALU_RAMFILE, ;Write AC and done
|1421|4488| SET LOCAL,GOTO [IFETCH]
|1421|4489|
|1421|4490|
|1421|4491|.TOC 2, "Arithmetic Testing Instructions"
|1421|4492|
|1421|4493|;Here for CAxx instructions to compare operands
|1421|4494|
000,000,0,14,02,0,52,0,54,0,0,00,00,00,00,00,0,20,1,0,1,06,01,00,0000,12,7,00,0,0,0,1422|4495|CAX: [AC-OP]-[MEM-OP]_Y,IX_MX, ;Compare operands and dispatch
|1422|4496| DISPATCH [DISPATCH 3]
|1422|4497|
|1422|4498|;Here for AOxx instructions to increment AC or memory
000,000,0,04,06,1,56,0,54,0,1,00,00,00,00,00,0,64,0,1,1,03,02,00,2075,00,7,00,0,0,0,1423|4499|AOXX: [MEM-OP]+1_[MEM-OP], ;Increment and dispatch
|1423|4500| IF CT [IZ IX_MX] THEN [SET C0!C1 STORE]
|1423|4501| IF NOT CT [MOVR] D [DISPATCH 3]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,46,1,1,0,06,03,00,0000,12,7,00,0,0,0,1424|4502| GOTO [SET OV!C1!T1 STORE]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,03,01,00,2070,00,7,00,0,0,0,1425|4503|
|1425|4504|;Here for SOxx instructions to decrement AC or memory
|1425|4505|
000,000,0,04,03,0,77,0,54,0,0,00,00,00,00,00,0,44,1,0,1,06,02,00,0000,12,7,00,0,0,0,1426|4506|SOXX: [K -1]+[MEM-OP]_B, ;Decrement and dispatch
|1426|4507| IF CT [MZ IX_MX] D [DISPATCH 3]
|1426|4508| IF NOT CT [MOVR] THEN [SET C0!C1 STORE]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,46,1,1,0,03,03,00,2075,00,7,00,0,0,0,1427|4509| GOTO [SET OV!C0!T1 STORE]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,03,01,00,2100,00,7,00,0,0,0,1428|4510|
|1428|4511|;Here for SxL instructions to conditionally skip
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,42,1,1,0,06,03,00,0000,13,7,00,0,0,0,1429|4512|SXL: IF NOT CT [MNxMOVR] D [DISPATCH 4]
000,000,0,04,06,1,36,0,36,0,1,00,00,00,00,00,0,20,1,1,1,06,01,00,0000,13,7,00,0,0,0,1430|4513| [PC]+1_[PC RH],
|1430|4514| DISPATCH [DISPATCH 4]
|1430|4515|
|1430|4516|;Here for SxE instructions to conditionally skip
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,44,1,1,0,06,03,00,0000,13,7,00,0,0,0,1431|4517|SXE: IF NOT CT [MZ] D [DISPATCH 4]
000,000,0,04,06,1,36,0,36,0,1,00,00,00,00,00,0,20,1,1,1,06,01,00,0000,13,7,00,0,0,0,1432|4518| [PC]+1_[PC RH],
|1432|4519| DISPATCH [DISPATCH 4]
|1432|4520|
|1432|4521|;Here for SxLE instructions to conditionaly skip
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,40,1,1,0,06,03,00,0000,13,7,00,0,0,0,1433|4522|SXLE: IF NOT CT [(MNxMOVR)!MZ] D [DISPATCH 4]
|1433|4523| ; G070 [SXA]
|1433|4524|
|1433|4525|;Here for SxA instructions to conditionaly skip
000,000,0,04,06,1,36,0,36,0,1,00,00,00,00,00,0,20,1,1,1,06,01,00,0000,13,7,00,0,0,0,1434|4526|SXA: [PC]+1_[PC RH],
|1434|4527| DISPATCH [DISPATCH 4]
|1434|4528|
|1434|4529|;Here for SxGE instructions to conditionaly skip
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,42,1,1,0,06,02,00,0000,13,7,00,0,0,0,1435|4530|SXGE: IF CT [MNxMOVR] D [DISPATCH 4]
000,000,0,04,06,1,36,0,36,0,1,00,00,00,00,00,0,20,1,1,1,06,01,00,0000,13,7,00,0,0,0,1436|4531| [PC]+1_[PC RH],
|1436|4532| DISPATCH [DISPATCH 4]
|1436|4533|
|1436|4534|;Here for SxN instructions to conditionaly skip
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,44,1,1,0,06,02,00,0000,13,7,00,0,0,0,1437|4535|SXN: IF CT [MZ] D [DISPATCH 4]
000,000,0,04,06,1,36,0,36,0,1,00,00,00,00,00,0,20,1,1,1,06,01,00,0000,13,7,00,0,0,0,1438|4536| [PC]+1_[PC RH],
|1438|4537| DISPATCH [DISPATCH 4]
|1438|4538|
|1438|4539|;Here for SxG instructions to conditionaly skip
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,40,1,1,0,06,02,00,0000,13,7,00,0,0,0,1439|4540|SXG: IF CT [(MNxMOVR)!MZ] D [DISPATCH 4]
000,000,0,04,06,1,36,0,36,0,1,00,00,00,00,00,0,20,1,1,1,06,01,00,0000,13,7,00,0,0,0,1440|4541| [PC]+1_[PC RH],
|1440|4542| DISPATCH [DISPATCH 4]
|1440|4543|
|1440|4544|;Here for JXL instructions to conditionaly branch
000,000,0,14,10,0,00,0,00,0,0,00,14,00,00,00,0,56,1,1,0,06,03,00,0000,13,7,00,0,0,0,1441|4545|JXL: IF NOT CT [MN] D [DISPATCH 4],
|1441|4546| SET LOCAL
000,000,0,04,06,1,42,0,34,0,0,00,00,00,00,00,0,20,1,1,1,06,01,00,0000,13,7,00,0,0,0,1442|4547| [E]_[PC],DISPATCH [DISPATCH 4]
|1442|4548|
|1442|4549|;Here for JxE instruction to conditionaly branch
000,000,0,14,10,0,00,0,00,0,0,00,14,00,00,00,0,44,1,1,0,06,03,00,0000,13,7,00,0,0,0,1443|4550|JXE: IF NOT CT [MZ] D [DISPATCH 4],
|1443|4551| SET LOCAL
000,000,0,04,06,1,42,0,34,0,0,00,00,00,00,00,0,20,1,1,1,06,01,00,0000,13,7,00,0,0,0,1444|4552| [E]_[PC],DISPATCH [DISPATCH 4]
|1444|4553|
|1444|4554|;Here for JxLE instructions to conditionaly branch
000,000,0,14,10,0,00,0,00,0,0,00,14,00,00,00,0,40,1,1,0,06,03,00,0000,13,7,00,0,0,0,1445|4555|JXLE: IF NOT CT [(MNxMOVR)!MZ] D [DISPATCH 4],
|1445|4556| SET LOCAL
000,000,0,04,06,1,42,0,34,0,0,00,00,00,00,00,0,20,1,1,1,06,01,00,0000,13,7,00,0,0,0,1446|4557| [E]_[PC],DISPATCH [DISPATCH 4]
|1446|4558|
|1446|4559|;Here for JxA instructions to conditionaly branch
000,000,0,04,06,1,42,0,34,0,0,00,14,00,00,00,0,20,1,1,1,06,01,00,0000,13,7,00,0,0,0,1447|4560|JXA: [E]_[PC],SET LOCAL,
|1447|4561| DISPATCH [DISPATCH 4]
|1447|4562|
|1447|4563|;Here for JxGE instructions !o conditionaly branch
000,000,0,14,10,0,00,0,00,0,0,00,14,00,00,00,0,57,1,1,0,06,03,00,0000,13,7,00,0,0,0,1448|4564|JXGE: IF NOT CT [NOT MN] D [DISPATCH 4],
|1448|4565| SET LOCAL
000,000,0,04,06,1,42,0,34,0,0,00,00,00,00,00,0,20,1,1,1,06,01,00,0000,13,7,00,0,0,0,1449|4566| [E]_[PC],DISPATCH [DISPATCH 4]
|1449|4567|
|1449|4568|;Here for JxN instructions to conditionaly branch
000,000,0,14,10,0,00,0,00,0,0,00,14,00,00,00,0,44,1,1,0,06,02,00,0000,13,7,00,0,0,0,1450|4569|JXN: IF CT [MZ] D [DISPATCH 4],
|1450|4570| SET LOCAL
000,000,0,04,06,1,42,0,34,0,0,00,00,00,00,00,0,20,1,1,1,06,01,00,0000,13,7,00,0,0,0,1451|4571| [E]_[PC],DISPATCH [DISPATCH 4]
|1451|4572|
|1451|4573|;Here for JxG instructions to conditionaly branch
000,000,0,14,10,0,00,0,00,0,0,00,14,00,00,00,0,40,1,1,0,06,02,00,0000,13,7,00,0,0,0,1452|4574|JXG: IF CT [(MNxMOVR)!MZ] D [DISPATCH 4],
|1452|4575| SET LOCAL
000,000,0,04,06,1,42,0,34,0,0,00,00,00,00,00,0,20,1,1,1,06,01,00,0000,13,7,00,0,0,0,1453|4576| [E]_[PC],DISPATCH [DISPATCH 4]
|1453|4577|
|1453|4578|;Here for SKIPx instructions to store in AC if AC.NE.0
000,000,0,14,10,0,00,0,00,0,0,00,14,00,00,00,0,20,1,1,0,13,06,00,1420,00,7,00,0,0,0,1454|4579|SKIPX: SET LOCAL,
|1454|4580| IF [AC.EQ.0] THENP [IFETCH] ;If nc AC we are done
000,000,0,14,14,0,77,0,54,0,0,00,00,00,00,00,0,20,1,1,1,13,01,00,1420,00,7,04,0,0,0,1455|4581| [MEM-OP]_RAMFILE, ;Store in AC
|1455|4582| GOTOP [IFETCH]
|1455|4583|
|1455|4584|.TOC 2, "Boolean Instructions"
|1455|4585|
|1455|4586|;Here for SETZx
000,000,0,04,10,1,00,0,54,0,0,00,00,00,00,00,0,20,1,1,1,06,01,00,0000,11,7,00,0,0,0,1456|4587|SETZX: ZERO_[MEM-OP],
|1456|4588| DISPATCH [INST EXCT]
|1456|4589|
|1456|4590|;Here for ANDx
000,000,0,04,14,0,52,0,54,0,0,00,00,00,00,00,0,20,1,1,1,06,01,00,0000,12,7,00,0,0,0,1457|4591|ANDX: [AC-OP]&[MEM-OP]_B, ;And AC with MEM and store
|1457|4592| DISPATCH [OPERAND STORE]
|1457|4593|
|1457|4594|;Here for ANDCAx
000,000,0,04,11,0,52,0,54,0,0,00,00,00,00,00,0,20,1,1,1,06,01,00,0000,12,7,00,0,0,0,1458|4595|ANDCAX: [AC-OP]BAR&[MEM-OP]_B, ;And AC complement with mem and store
|1458|4596| DISPATCH [OPERAND STORE]
|1458|4597|
|1458|4598|;Here for SETMI = XMOVEI
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,1630,00,7,00,0,0,0,1459|4599|XMOVEI: CALL [E_MEM-OP]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,27,0,20,1,1,0,06,01,00,0000,12,7,00,0,0,0,1460|4600| SEL AC+[0],
|1460|4601| DISPATCH [OPERAND STORE]
|1460|4602|
|1460|4603|;Here for ANDCMx
000,000,0,04,07,0,56,0,54,0,0,00,00,00,00,00,0,20,1,1,1,03,01,00,2661,00,7,00,0,0,0,1461|4604|ANDCMX: COMPLEMENT [MEM-OP]_F, ;Complement mem operand then
|1461|4605| F_[MEM-OP],GOTO [ANDX] ; same as AND
|1461|4606|
|1461|4607|;Here for XORx
000,000,0,04,13,0,52,0,54,0,0,00,00,00,00,00,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,1462|4608|XORX: [AC-OP].XOR.[MEM-OP]_F,F_B ;Xor operands and store
|1462|4609| DISPATCH [OPERAND STORE]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,06,01,00,0000,12,7,00,0,0,0,1463|4610|
|1463|4611|;Here for IORx
000,000,0,04,17,0,52,0,54,0,0,00,00,00,00,00,0,20,1,1,1,06,01,00,0000,12,7,00,0,0,0,1464|4612|IORX: [AC-OP].OR.[MEM-OP]_B, ;Ior operands and store
|1464|4613| DISPATCH [OPERAND STORE]
|1464|4614|
000,000,0,04,07,0,56,0,54,0,0,00,00,00,00,00,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,1465|4615|ANDCBX:
|1465|4616|;Small way is:
|1465|4617|; COMPLEMENT [AC-OP]_F, ;Comp1ement AC operand
|1465|4618|; F_[AC-OP], GOTO [ANDCMX]
|1465|4619|;Fast way is:
|1465|4620| COMPLEMENT [MEM-OP]_F,
|1465|4621| F_[MEM-OP]
000,000,0,04,11,0,52,0,54,0,0,00,00,00,00,00,0,20,1,1,1,06,01,00,0000,12,7,00,0,0,0,1466|4622| [AC-OP]BAR&[MEM-OP]_B, ;And complements and store
|1466|4623| DISPATCH [OPERAND STORE]
|1466|4624|
|1466|4625|;Here for EQVx
000,000,0,04,12,0,52,0,54,0,0,00,00,00,00,00,0,20,1,1,1,06,01,00,0000,12,7,00,0,0,0,1467|4626|EQVX: [AC-OP].XNOR.[MEM-OP]_F, F_B, ;Put eqv (XNOR) in mem store
|1467|4627| DISPATCH [OPERAND STORE]
|1467|4628|
|1467|4629|;Here for SETCAx
000,000,0,04,07,0,56,0,54,0,0,00,00,00,00,00,0,20,1,1,1,06,01,00,0000,12,7,00,0,0,0,1468|4630|SETCAX: COMPLEMENT [MEM-OP]_F, ;Complement AC and store
|1468|4631| F_[MEM-OP],
|1468|4632| DISPATCH [OPERAND STORE]
|1468|4633|
|1468|4634|;Here for ORCAx
000,000,0,04,07,0,52,0,50,0,0,00,00,00,00,00,0,20,1,1,1,03,01,00,2670,00,7,00,0,0,0,1469|4635|ORCAX: COMPLEMENT [AC-OP]_F, ;Complement AC then same as OR
|1469|4636| F_[AC-OP],
|1469|4637| GOTO [IORX]
|1469|4638|
|1469|4639|;Here for SETCMx
000,000,0,04,07,0,56,0,54,0,0,00,00,00,00,00,0,20,1,1,1,06,01,00,0000,12,7,00,0,0,0,1470|4640|SETCMX: COMPLEMENT [MEM-OP]_F, ;Complement mem and store
|1470|4641| F_[MEM-OP],
|1470|4642| DISPATCH [OPERAND STORE]
|1470|4643|
|1470|4644|;Here for ORCMx
000,000,0,04,07,0,56,0,54,0,0,00,00,00,00,00,0,20,1,1,1,03,01,00,2670,00,7,00,0,0,0,1471|4645|ORCMX: COMPLEMENT [MEM-OP]_F, ;Complement mem and then same as OR
|1471|4646| F_[MEM-OP],
|1471|4647| GOTO [IORX]
|1471|4648|
|1471|4649|;Here for ORCBx ;And operands then same as SETCM
000,000,0,14,14,0,52,0,54,0,0,00,00,00,00,00,0,20,1,1,0,03,01,00,2676,00,7,00,0,0,0,1472|4650|ORCBX: [AC-OP]&[MEM-OP]_F,
|1472|4651| GOTO [SETCMX]
|1472|4652|
|1472|4653|;Here for SETOx
000,000,0,04,00,1,00,0,54,0,0,00,00,00,00,00,0,20,1,1,1,06,01,00,0000,11,7,00,0,0,0,1473|4654|SETOX: ONES_[MEM-OP],
|1473|4655| DISPATCH [INST EXCT]
|1473|4656|
|1473|4657|
|1473|4658|.TOC 2, "Half Word Instructions"
|1473|4659|
|1473|4660|;Here for HLL
000,000,0,04,06,1,52,0,56,0,0,00,00,00,00,00,0,20,1,1,1,06,01,00,0000,12,7,00,0,0,0,1474|4661|HLL: [AC-OP]_[MEM-OP RH], ;Preserve RH of AC then store
|1474|4662| DISPATCH [OPERAND STORE]
|1474|4663|
|1474|4664|;Here for HLLI = XHLLI
000,000,0,04,06,1,42,0,55,0,0,00,00,00,00,77,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,1475|4665|XHLLI: [E]_[MEM-OP LH],SECTION SELECT ;Preserve RH of AC
000,000,0,04,14,0,67,0,54,0,0,00,00,00,00,00,0,20,1,1,1,03,22,00,4342,00,7,00,0,0,0,1476|4666| [K 7777.-1]&[MEM-OP]_B, ;Strip extraneous bits
|1476|4667| IF [NOT AC REF] THEN [TO AC.0]
000,000,0,14,06,1,36,0,00,0,0,00,00,00,00,77,0,20,1,1,1,03,35,00,4342,00,7,00,0,0,0,1477|4668| [PC]_Y,SECTION SELECT, ;Check PC section
|1477|4669| IF [GLOBAL] THEN [TO AC.0]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,27,0,20,1,1,0,06,27,00,0000,12,7,00,0,0,0,1478|4670| SEL AC+[0],
|1478|4671| IF [SECTION 0] D [OPERAND STORE]
000,000,0,04,06,1,57,0,55,0,0,00,00,00,00,00,0,20,1,1,1,03,01,00,4343,00,7,00,0,0,0,1479|4672| [BIT17]_[MEM-OP LH], ;Sect = 1 here
|1479|4673| GOTO [TO AC]
|1479|4674|
|1479|4675|; Here for HRU,
000,000,0,04,10,0,52,2,50,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0000,00,7,07,0,0,0,1480|4676|HRLM: SWAP [AC-OP]_[AC-OP] ;Swap AC op then same as HLLM
|1480|4677| ;GOTO [HLLM]
|1480|4678|
|1480|4679|;Here for HLLM
000,000,0,04,06,1,52,0,55,0,0,00,00,00,00,00,0,20,1,1,1,06,01,00,0000,12,7,00,0,0,0,1481|4680|HLLM: [AC-OP]_[MEM-OP LH], ;Preserve LH of AC then store
|1481|4681| DISPATCH [OPERAND STORE]
|1481|4682|
|1481|4683|;Here for HRL & HRLI
000,000,0,04,10,0,56,2,51,0,0,00,00,00,00,00,0,20,1,1,0,06,01,00,0000,12,7,07,0,0,0,1482|4684|HRL: SWAP [MEM-OP]_[AC-OP LH], ;Swap memory op then same as HLL
|1482|4685| DISPATCH [OPERAND STORE]
|1482|4686|
|1482|4687|;Here for HRLS
000,000,0,04,10,0,56,2,55,0,0,00,00,00,00,00,0,20,1,1,0,06,01,00,0000,12,7,07,0,0,0,1483|4688|HRLS: SWAP [MEM-OP]_[MEM-OP LH], ;Put RH in LH then store
|1483|4689| DISPATCH [OPERAND STORE]
|1483|4690|
|1483|4691|;Here for HLLZX
000,000,0,04,14,0,76,0,54,0,0,00,00,00,00,00,0,20,1,1,1,06,01,00,0000,13,7,00,0,0,0,1484|4692|HLLZX: [K -1.0]&[MEM-OP]_B, ;Mask off rh and store
|1484|4693| DISPATCH [DISPATCH 4]
|1484|4694|
|1484|4695|;Here for HRLEX
000,000,0,14,06,1,56,0,00,0,0,00,00,00,00,00,0,20,1,0,1,16,00,00,0000,00,7,00,0,0,0,1485|4696|HRLEX: [MEM-OP]_Y,IX_MX ;Test sign bit
|1485|4697| ;GOTO [HLLEX]
|1485|4698|
|1485|4699|;Here for HLLEX
000,000,0,04,10,1,00,0,56,0,0,00,00,00,00,00,0,56,1,1,1,06,03,00,0000,13,7,00,0,0,0,1486|4700|HLLEX: ZERO_[MEM-OP RH], ;Clear RH
|1486|4701| IF NOT CT [MN] D [DISPATCH 4]
|1486|4702| ;GOTO [HLLOX]
|1486|4703|
|1486|4704|;Here for HLLOX
000,000,0,04,00,1,00,0,56,0,0,00,00,00,00,00,0,20,1,1,1,06,01,00,0000,13,7,00,0,0,0,1487|4705|HLLOX: ONES_[MEM-OP RH], ;Add ones to rh and store
|1487|4706| DISPATCH [DISPATCH 4]
|1487|4707|
|1487|4708|
|1487|4709|;Here for HRR & HRRI
000,000,0,04,06,1,52,0,55,0,0,00,00,00,00,00,0,20,1,1,1,06,01,00,0000,12,7,00,0,0,0,1488|4710|HRR: [AC-OP]_[MEM-OP LH], ;Preserve ACs lh then store
|1488|4711| DISPATCH [OPERAND STORE]
|1488|4712|
|1488|4713|;Here for HLRM
000,000,0,04,10,0,52,2,50,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0000,00,7,07,0,0,0,1489|4714|HLRM: SWAP [AC-OP]_[AC-OP] ;Swap AC arg then same as HRRM
|1489|4715| ;GOTO [HRRM}
|1489|4716|
|1489|4717|;Here for HRRK
000,000,0,04,06,1,52,0,56,0,0,00,00,00,00,00,0,20,1,1,1,06,01,00,0000,12,7,00,0,0,0,1490|4718|HRRM: [AC-OP]_[MEM-OP RH], ;Copy Rh then store
|1490|4719| DISPATCH [OPERAND STORE]
|1490|4720|
|1490|4721|;Here for HLR & HLRI
000,000,0,04,10,0,56,2,52,0,0,00,00,00,00,00,0,20,1,1,0,06,01,00,0000,12,7,07,0,0,0,1491|4722|HLR: SWAP [MEM-OP]_[AC-OP RH], ;Swap mem arg then same as HRR
|1491|4723| DISPATCH [OPERAND STORE]
|1491|4724|
|1491|4725|;Here for HLRS
000,000,0,04,10,0,56,2,56,0,0,00,00,00,00,00,0,20,1,1,0,03,01,00,4355,00,7,07,0,0,0,1492|4726|HLRS: SWAP [MEM-OP]_[MEM-OP RH], ;Put LH in RH then store
|1492|4727| GOTO [TO SELF]
|1492|4728|
|1492|4729|;Here for HRRZX
000,000,0,04,10,1,00,0,55,0,0,00,00,00,00,00,0,20,1,1,1,06,01,00,0000,13,7,00,0,0,0,1493|4730| HRRZX: ZERO_[MEM-OP LH], ;Clear LH and store
|1493|4731| DISPATCH [DISPATCH 4]
|1493|4732|
|1493|4733|;Here for HRREX
000,000,0,04,11,0,76,0,54,0,0,00,00,00,00,00,0,20,1,1,1,06,57,00,0000,13,7,00,0,0,0,1494|4734|HRREX: [K -1.0]BAR&[MEM-OP]_B, ; Clear RH and check sign
|1494|4735| IF [NOT B BIT 18] D [DISPATCH 4]
|1494|4736| ;GOTO [HRROX]
|1494|4737|
|1494|4738|;Here for HRROX
000,000,0,04,00,1,00,0,55,0,0,00,00,00,00,00,0,20,1,1,1,06,01,00,0000,13,7,00,0,0,0,1495|4739|HRROX: ONES_[MEM-OP LH], ;Put ones in LH and store operand
|1495|4740| DISPATCH [DISPATCH 4]
|1495|4741|
|1495|4742|
|1495|4743|.TOC 2, "Logical Testing and Modification Instructions"
|1495|4744|
|1495|4745|;Here for TRxx Instructions to get test bits and AC
000,000,0,04,10,1,00,0,41,0,0,00,00,00,00,00,0,20,1,1,1,03,01,00,2735,00,7,00,0,0,0,1496|4746|TRX: ZERO_[E LH], ;Leave only E RH, then set AC
|1496|4747| GOTO [TDXX]
|1496|4748|
|1496|4749|;Here for TLxx Instructions to get test bits and AC
000,000,0,04,10,1,00,0,41,0,0,00,00,00,00,00,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,1497|4750|TLX: ZERO_[E LH] ;Strip RH and select AC
000,000,0,04,10,0,42,2,40,0,0,00,00,00,00,00,0,20,1,1,0,03,01,00,2735,00,7,07,0,0,0,1498|4751| SWAP [E]_[E], ;Put test bits in LH and select AC
|1498|4752| GOTO [TDXX]
|1498|4753|
|1498|4754|;Here for TDxx Instructions to get test bits and AC
000,000,0,07,06,1,42,0,40,0,0,00,00,00,00,77,0,20,1,1,1,01,01,00,4663,00,7,00,0,0,0,1499|4755|TDX: READ [E] ;Fetch test bits
000,000,0,04,06,1,46,0,40,0,0,00,00,00,00,27,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,1500|4756| [MB]_[E],SEL AC+[0] ;Copy test bits, and select AC
000,000,0,04,10,0,00,0,54,0,0,00,14,00,00,00,0,20,1,1,0,06,01,00,0000,11,7,04,0,0,0,1501|4757|TDXX: RAMFILE_[MEM-OP], ;Get AC and dispatch
|1501|4758| SET LOCAL,
|1501|4759| DISPATCH [DISPATCH 2]
|1501|4760|
|1501|4761|;Here for TSxx Instructions to get test bits and AC
000,000,0,07,06,1,42,0,40,0,0,00,00,00,00,77,0,20,1,1,1,01,01,00,4663,00,7,00,0,0,0,1502|4762|TSX: READ [E] ;Fetch test bits
000,000,0,04,10,0,46,2,40,0,0,00,00,00,00,27,0,20,1,1,0,16,00,00,0000,00,7,07,0,0,0,1503|4763| SWAP [MB]_[E],SEL AC+[0] ;Swap test bits and select AC
000,000,0,04,10,0,00,0,54,0,0,00,14,00,00,00,0,20,1,1,0,06,01,00,0000,11,7,04,0,0,0,1504|4764| RAMFILE_[MEM-OP], ;Get AC and dispatch
|1504|4765| SET LOCAL,
|1504|4766| DISPATCH [DISPATCH 2]
|1504|4767|
|1504|4768|;Here for TxE Instructions for conditional skip
000,000,0,14,14,0,42,0,54,0,0,00,00,00,00,00,0,64,1,1,1,06,03,00,0000,12,7,00,0,0,0,1505|4769|TXE: [E]&[MEM-OP]_Y, ; Check for need to skip
|1505|4770| IF NOT CT [IZ] D [DISPATCH 3]
|1505|4771| ;GOTO [TXA]
|1505|4772|
|1505|4773|;Here for TxA Instructions for conditional skip
000,000,0,04,06,1,36,0,36,0,1,00,00,00,00,00,0,20,1,1,1,06,01,00,0000,12,7,00,0,0,0,1506|4774|TXA: [PC]+1_[PC RH],
|1506|4775| DISPATCH [DISPATCH 3]
|1506|4776|
|1506|4777|;Here for TxN Instructions for conditional skip
000,000,0,14,14,0,42,0,54,0,0,00,00,00,00,00,0,64,1,1,1,06,02,00,0000,12,7,00,0,0,0,1507|4778|TXN: [E]&[MEM-OP]_Y, ;Check for need to skip
|1507|4779| IF CT [IZ] D [DISPATCH 3]
000,000,0,04,06,1,36,0,36,0,1,00,00,00,00,00,0,20,1,1,1,06,01,00,0000,12,7,00,0,0,0,1508|4780| [PC]+1_[PC RH],
|1508|4781| DISPATCH [DISPATCH 3]
|1508|4782|
|1508|4783|;Here for TxZ Instructions to change bits
000,000,0,14,11,0,42,0,54,0,0,00,00,00,00,00,0,20,1,1,1,13,01,00,1420,00,7,04,0,0,0,1509|4784|TXZ: [E]BAR&[MEM-OP]_Y, ;Store new bits
|1509|4785| ALU_RAMFILE,
|1509|4786| GOTOP [IFETCH]
|1509|4787|
|1509|4788|;Here for TxC Instructions to change bits
000,000,0,14,13,0,42,0,54,0,0,00,00,00,00,00,0,20,1,1,1,13,01,00,1420,00,7,04,0,0,0,1510|4789|TXC: [E].XOR.[MEM-OP]_Y, ;Store new bits
|1510|4790| ALU_RAMFILE,
|1510|4791| GOTOP [IFETCH]
|1510|4792|
|1510|4793|;Here for TxO Instructions to change bits
000,000,0,14,17,0,42,0,54,0,0,00,00,00,00,00,0,20,1,1,1,13,01,00,1420,00,7,04,0,0,0,1511|4794|TXO: [E].OR.[MEM-OP]_Y, ;Store new bits
|1511|4795| ALU_RAMFILE,
|1511|4796| GOTOP [IFETCH]
|1511|4797|
|1511|4798|
|1511|4799|.TOC 2, "Extend Instructions"
|1511|4800|
|1511|4801|.IF/FTEXTEND
000,000,0,07,06,1,42,0,40,0,0,00,00,00,00,77,0,20,1,1,1,01,01,00,4663,00,7,00,0,0,0,1512|4802|EXTEND: READ [E] ;Get EO word
|1512|4803| CALL [EFA CALC]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,1447,00,7,00,0,0,0,1513|4804|.ENDIF/FTEXTEND
|1513|4805|
|1513|4806|
|1513|4807|.TOC 2, "CIS Instructions"
|1513|4808|
|1513|4809|.IF/FTCIS
|1513|4810|;Current block AC0 wi11 be as follows for interrupts
|1513|4811|;
|1513|4812|; 11111111112222222 222333333
|1513|4813|; 012345678901234567890123456 789012345
|1513|4814|; +---------------------------+---------+
|1513|4815|; + + +
|1513|4816|; +---------------------------+---------+
|1513|4817|; \ /
|1513|4818|; + ---number of bytes so far
|1513|4819|;Register usage
|1513|4820|; W1 current byte
|1513|4821|; W2 src adr (bit0-immediate;bits 4-35 are 32bit byte adr)
|1513|4822|; W3 src wrd
|1513|4823|; W4 dest adr
|1513|4824|; W5 dest wrd
|1513|4825|; W6 0,,bytes left to do
|1513|4826|; ACO number of bytes to do,,number of bytes written
|1513|4827|
|1513|4828|;Common routine to do setup for CIS instructions
000,000,0,04,10,1,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0400,00,7,01,0,0,0,1514|4829|CIS SETUP:
|1514|4830| J[0400]_[W1]
|1514|4831| SWAP [W1]_[W1] ;Make a bit9
000,000,0,04,10,0,02,2,00,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0000,00,7,07,0,0,0,1515|4832| [W1]_Q ;Save copy in Q reg
000,000,0,05,14,1,32,0,00,0,0,00,00,01,00,00,0,20,1,0,1,16,00,00,0000,00,7,00,0,0,0,1517|4833| Q&[IR]_F,F_Y LSRQ_Q,IX_MX ;Test bit 9
000,000,0,05,14,1,32,0,00,0,0,00,00,01,00,00,0,44,1,0,1,03,02,00,2774,00,7,00,0,0,0,1518|4834| Q&[IR]_F,F_Y LSRQ_Q, ;Test bit 10
|1518|4835| IF CT [MZ IX_MX] THEN [CS 2]
|1518|4836|;Here if bit 9 is 0
000,000,0,05,14,1,32,0,00,0,0,00,00,01,00,00,0,44,1,0,1,03,03,00,2765,00,7,00,0,0,0,1519|4837| Q&[IR]_F,F_Y LSRQ_Q, ;Test bit 11
|1519|4838| IF NOT CT [MZ IX_MX] THEN [CS 1]
|1519|4839| [E]_[W2] ;Copy source adr
000,000,1,11,06,1,06,0,04,0,0,00,00,11,00,00,0,64,1,1,1,01,03,00,2764,00,7,00,0,0,0,1521|4840| #2*[W2]_[W2],
|1521|4841| IF NOT CT [IZ] CALL [W2+1]
000,000,1,11,06,1,06,0,04,0,0,00,00,11,00,00,0,64,1,1,1,01,03,00,2764,00,7,00,0,0,0,1522|4842| #2*[W2]_[W2],
|1522|4843| IF NOT CT [IZ] CALL [W2+1]
|1522|4844| [PC FLAGS]&[BIT4]_F ;Check first part done
000,000,0,04,06,1,06,0,04,0,1,00,00,00,00,00,0,20,1,1,1,12,01,00,0000,00,7,00,0,0,0,1524|4845|W2+1: [W2]+1_[W2],RETURN
|1524|4846|;Here if bits 9,10 are 0,1
000,000,0,05,14,1,32,0,00,0,0,00,00,01,00,00,0,44,1,0,1,03,03,00,1637,00,7,00,0,0,0,1525|4847|CS 1: Q&[IR]_F,F_Y LSRQ_Q, ;Test bit 12
|1525|4848| IF NOT CT [MZ IX_MX] THEN [MUUO]
000,000,0,04,06,1,42,0,10,0,0,00,00,00,00,00,0,44,1,1,1,03,03,00,2774,00,7,00,0,0,0,1526|4849| [E]_[W3], ;In case immediate
|1526|4850| IF NOT CT [MZ] THEN [CS1 IM]
|1526|4851|;Here if first operand is deferred mode
|1526|4852| READ [E] ;Get adr of operand
000,000,0,07,06,1,42,0,40,0,0,00,00,00,00,77,0,20,1,1,1,01,01,00,4663,00,7,00,0,0,0,1527|4853|.IF/FTMBZ
|1527|4854| J[#32B MASK]_RAMFILE ADR
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,03,0,20,1,1,0,16,00,00,0040,00,7,01,0,0,0,1528|4855| RAMFILE_[W1]
000,000,0,14,11,0,02,0,44,0,0,00,00,00,00,00,0,20,1,0,1,16,00,00,0000,00,7,00,0,0,0,1530|4856| [W1]BAR&[MB]_Y,IX_MX ;Test for illegal bits
000,000,0,04,06,1,46,0,04,0,0,00,00,00,00,00,0,44,1,1,1,03,03,00,1637,00,7,00,0,0,0,1531|4857| [MB]_[W2], ;Copy adr
|1531|4858| IF NOT CT [MZ] THEN [MUUO]
|1531|4859|.ENDIF/FTMBZ
|1531|4860|.IFNOT/FTMBZ
|1531|4861| [MB]_[W2] ;Copy adr
|1531|4862|.ENDIF/FTKBZ
|1531|4863|
|1531|4864|; Here if immediate operand
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,06,01,00,0000,11,7,00,0,0,0,1532|4865|CS1 IM:
|1532|4866|
|1532|4867|;Here is bit 9 is 1
|1532|4868|CS 2: DISPATCH [DISPATCH 2]
|1532|4869|
000,000,0,14,14,0,47,0,03,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0000,00,7,00,0,0,0,1533|4870|MOVC:
|1533|4871| [BIT4]&[PC FLAGS]_F ;Check first part done
|1533|4872| JS[0]_[W6]
000,000,0,01,10,1,00,0,24,0,0,00,00,05,00,00,0,20,1,1,0,16,00,00,0000,00,7,01,0,0,0,1534|4873| LRS [W6]_[W6]
000,000,0,01,06,1,26,0,24,0,0,00,00,01,00,00,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,1535|4874| LRS [W6]_[W6]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,3017,00,7,00,0,0,0,1537|4875|MOVC 7:
|1537|4876| CALL [NXT SRC BYT] ;Get next byte to transfer
|1537|4877| CALL [W NXT DST BYT] ;Copy it
000,000,0,04,03,0,77,0,24,0,0,00,00,00,00,00,0,64,1,1,1,03,03,00,3001,00,7,00,0,0,0,1539|4878| [K -1]+[W6]_B,
|1539|4879| IF NOT CT [IZ] THEN [MOVC 7]
|1539|4880| GOTOP [IFETCH]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,13,01,00,1420,00,7,00,0,0,0,1540|4881|
|1540|4882|;Register conventions same as MOVC
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,3017,00,7,00,0,0,0,1541|4883|CMPC:
|1541|4884|CMPC 7: CALL [NXT SRC BYT] ;Get first operand byte
|1541|4885| J[EIS W1]_RAMFILE ADR
000,000,0,14,14,0,72,0,00,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,3035,00,7,04,0,0,0,1543|4886| [K 777]&[W1]_Y,ALU_RAMFILE, ;Save first operand
|1543|4887| CALL [R NXT DST BYT] ;Get other byte
000,000,0,06,14,0,72,0,00,0,0,00,00,00,00,03,0,20,1,1,0,16,00,00,0446,00,7,01,0,0,0,1544|4888| [K 777]&[W1]_Q,
|1544|4889| J[EIS W1]_RAMFILE ADR
|1544|4890| RAMFILE_[W1]
000,000,0,14,01,1,02,0,00,0,1,00,00,00,00,00,0,64,0,1,1,03,03,00,3015,00,7,00,0,0,0,1546|4891| Q-[W1]_Y,
|1546|4892| IF NOT CT [IZ IX_MX] THEN [CMPC 8]
000,000,0,04,03,0,77,0,24,0,0,00,00,00,00,00,0,64,1,1,1,03,03,00,3005,00,7,00,0,0,0,1547|4893| [K -1]+[W6]_B,
|1547|4894| IF NOT CT [IZ] THEN [CMPC 7]
|1547|4895| GOTOP [IFETCH]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,56,1,1,0,03,02,00,3016,00,7,00,0,0,0,1549|4896|CMPC 8: IF CT [MN] THEN [CMPC 9]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,13,01,00,1420,00,7,00,0,0,0,1550|4897|CMPC 9: GOTOP [IFETCH]
|1550|4898|
|1550|4899|
|1550|4900|;Move Characters Variable Length
000,000,0,04,06,1,06,0,04,0,1,00,00,00,00,00,0,76,1,0,1,03,02,00,3034,00,7,00,0,0,0,1551|4901|MOVCV:
|1551|4902|;Compare Characters Variable Length
|1551|4903|CMPCV:
|1551|4904|;Compare Numeric Display
|1551|4905|CMPND:
|1551|4906|;Add Numeric Display
|1551|4907|ADDND:
|1551|4908|;Subtract Numeric Display
|1551|4909|SUBND:
|1551|4910|;Move Numeric Display
|1551|4911|MOVND:
|1551|4912|;Arithmetic Shift Numeric Display
|1551|4913|ASHND:
|1551|4914|;Convert Numeric Display to Binary
|1551|4915|CVTNDB:
|1551|4916|;Convert Binary to Numeric Display
|1551|4917|CVTBND:
|1551|4918|;Test for Legal Numeric Display
|1551|4919|TLGND:
|1551|4920|;Compare Packed
|1551|4921|CMPP:
|1551|4922|;Add Packed
|1551|4923|ADDP:
|1551|4924|;Subtract Packed
|1551|4925|SUBP:
|1551|4926|;Move Packed
|1551|4927|MOVP:
|1551|4928|;Arithmetic Shift Packed
|1551|4929|ASHP:
|1551|4930|;Clear High Order Packed
|1551|4931|CHOP:
|1551|4932|;Convert Packed to Binary
|1551|4933|CVTPB:
|1551|4934|;Convert Binary to Packed
|1551|4935|CVTBP:
|1551|4936|;Convert Numeric Display to Packed
|1551|4937|CVTNDP:
|1551|4938|;Convert Packed to Numeric Display
|1551|4939|CVTPND:
|1551|4940|; Convert EBCDIC Numeric Display to Packed
|1551|4941|CVTEP:
|1551|4942|; Convert Packed to EBCDIC Numeric Display
|1551|4943|CVTPE:
|1551|4944|
|1551|4945|;Here to read the next source byte
|1551|4946|NXT SRC BYT:
|1551|4947| [W2]+1_[W2], ;Next byte adr
|1551|4948| IF CT [IN IX_MX] THEN [NXT SRC I]
|1551|4949| ASR [W2]_[E] MC ;Copy adr to E
000,000,0,01,06,1,06,0,40,0,0,00,00,11,00,00,0,52,1,1,1,03,02,00,3032,00,7,00,0,0,0,1553|4950| ASR [W2]_[E] MC, ;Copy word adr
|1553|4951| IF CT [MC] THEN [NSB 2] ; Check for odd or even byte
|1553|4952| IF CT [MC] THEN [NSB 3]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,52,1,1,0,03,02,00,3027,00,7,00,0,0,0,1554|4953|
|1554|4954|;Here if need to fetch next source word
|1554|4955| READ [E]
000,000,0,04,06,1,46,0,10,0,0,00,00,00,00,00,0,20,1,1,1,14,00,00,0002,00,7,00,0,0,0,1556|4956| [MB]_[W3], ;Copy data
|1556|4957| J[2]_CTR
|1556|4958| SWAP [W3]_[W1]
000,000,1,11,06,1,02,0,00,0,0,00,00,11,00,00,0,20,1,1,1,03,01,00,3030,00,7,00,0,0,0,1558|4959| #2*[W1]_[W1],
|1558|4960| GOTO [NSB 30]
|1558|4961|
|1558|4962|;Here for 3rd byte in word
000,000,1,11,06,1,12,0,00,0,0,00,00,11,00,00,0,20,1,1,1,14,00,00,0003,00,7,00,0,0,0,1559|4963|NSB 3: #2*[W3]_[W1], ;Copy to right word
|1559|4964| J[3]_CTR
000,000,1,11,03,0,02,0,00,0,0,00,00,11,00,00,0,20,1,1,1,11,00,00,3030,00,7,00,0,0,0,1560|4965|NSB 30: #4*[W1]_B,
|1560|4966| LOOP [NSB 30]
000,000,0,04,10,0,02,2,00,0,0,00,00,00,00,00,0,20,1,1,0,12,01,00,0000,00,7,07,0,0,0,1561|4967|SWAP W1 W1:
|1561|4968| SWAP [W1]_[W1],
|1561|4969| RETURN
|1561|4970|
|1561|4971|;Here for 2nd or 4th byte in word
000,000,0,04,06,1,12,0,00,0,0,00,00,00,00,00,0,52,1,1,1,12,02,00,0000,00,7,00,0,0,0,1562|4972|NSB 2: [W3]_[W1],
|1562|4973| IF CT [MC] RETURN
|1562|4974|;Here for 2nd byte in word
000,000,0,04,10,0,02,2,00,0,0,00,00,00,00,00,0,20,1,1,0,12,01,00,0000,00,7,07,0,0,0,1563|4975| SWAP [W1]_[W1],
|1563|4976| RETURN
|1563|4977|
000,000,0,04,06,1,12,0,00,0,0,00,00,00,00,00,0,20,1,1,1,12,01,00,0000,00,7,00,0,0,0,1564|4978|NXT SRC I:
|1564|4979| [W3]_[W1], ;Next byte
|1564|4980| RETURN
|1564|4981|
|1564|4982|;Here to read the next destination byte
000,000,0,04,06,1,16,0,14,0,1,00,00,00,00,00,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,1565|4983|R NXT DST BYT:
|1565|4984|
|1565|4985|;Here to write the next destination byte
|1565|4986|; Call with byte right justified in W1
|1565|4987|W NXT DST BYT:
|1565|4988| [W4]+1_[W4] ;Next byte adr
|1565|4989| ASR [W4]_[E] MC ;Copy adr to E
000,000,0,01,06,1,16,0,40,0,0,00,00,11,00,00,0,52,1,1,1,03,02,00,3052,00,7,00,0,0,0,1567|4990| ASR [W4]_[E] MC, ;Copy word adr
|1567|4991| IF CT [MC] THEN [WNDB 2] ; Check for odd or even byte
|1567|4992| IF CT [MC] THEN [WNDB 3]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,52,1,1,0,03,02,00,3046,00,7,00,0,0,0,1568|4993|;Here if need to fetch next source word
|1568|4994| READ [E]
000,000,0,04,06,1,46,0,20,0,0,00,00,00,00,00,0,20,1,1,1,14,00,00,0003,00,7,00,0,0,0,1570|4995| [MB]_[W5], ;Copy data
|1570|4996| J[3]_CTR
|1570|4997| J[NBBYTE1]_RAMFILE ADR
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,03,0,20,1,1,0,16,00,00,0454,00,7,01,0,0,0,1571|4998| SWAP [W1]_[W1]
000,000,1,11,06,1,02,0,00,0,0,00,00,11,00,00,0,20,1,1,1,03,01,00,3050,00,7,00,0,0,0,1573|4999| #2*[W1]_[W1],
|1573|5000| GOTO [WNDB 30]
|1573|5001|
|1573|5002|;Here for 3rd byte in word
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,03,0,20,1,1,0,16,00,00,0455,00,7,01,0,0,0,1574|5003|WNDB 3: J[NBBYTE3]_RAMFILE ADR
000,000,1,11,06,1,22,0,00,0,0,00,00,11,00,00,0,20,1,1,1,14,00,00,0003,00,7,00,0,0,0,1575|5004| #2*[W5]_[W1], ;Copy to right word
|1575|5005| J[3]_CTR
000,000,1,11,03,0,02,0,00,0,0,00,00,11,00,00,0,20,1,1,1,11,00,00,3050,00,7,00,0,0,0,1576|5006|WNDB 30:#4*[W1]_B,
|1576|5007| LOOP [WNDB 30]
000,000,0,04,10,0,00,0,44,0,0,00,00,00,00,00,0,20,1,1,0,12,01,00,0000,00,7,04,0,0,0,1577|5008| RAMFILE_[MB], ;Get mask for character
|1577|5009| RETURN
|1577|5010|
000,000,0,04,10,0,72,2,44,0,0,00,00,00,00,00,0,52,1,1,0,03,02,00,3057,00,7,07,0,0,0,1578|5011|WNDB 2: SWAP [K 777]_[MB], ;Mask for byte
|1578|5012| IF CT [MC] THEN [WNDB 4]
|1578|5013|;Here for 2nd byte in word
|1578|5014| SWAP [W1]_[W1] ;Position data
000,000,0,04,11,0,46,0,20,0,0,00,00,00,00,00,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,1580|5015|WNDB 20:[MB]BAR&[W5]_B ;Strip old byte from word
|1580|5016| [MB]&[W1]_B ;Strip data to move
000,000,0,04,17,0,02,0,20,0,0,00,00,00,00,00,0,20,1,1,1,12,01,00,0000,00,7,00,0,0,0,1582|5017| [W1].OR.[W5]_B, ;Add new bits to word
|1582|5018| RETURN
|1582|5019|
|1582|5020|;Here for 4th byte in word
000,000,0,06,11,0,72,0,20,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0000,00,7,00,0,0,0,1583|5021|WNDB 4: [K 777]BAR&[W5]_Q ;Mask off old data
|1583|5022| [K 777]&[W1]_B ;Mask off extraneous bits from data
000,000,0,04,17,1,02,0,44,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,4711,00,7,00,0,0,0,1585|5023| Q.OR.[W1]_[MB], ;Add new byte to data
|1585|5024| CALL [MEMORY WRITE]
000,000,0,07,06,1,42,0,40,0,1,00,00,00,00,77,0,20,1,1,1,01,01,00,4663,00,7,00,0,0,0,1586|5025| [E]+1_Q_[E],
|1586|5026| SPEC SEL/PAGE TABLE ENTRY,
|1586|5027| CALL [MEMORY READ]
000,000,0,04,06,1,46,0,20,0,0,00,00,00,00,00,0,20,1,1,1,12,01,00,0000,00,7,00,0,0,0,1587|5028| [MB]_[W5],
|1587|5029| RETURN
|1587|5030|.ENDIF/FTCIS
|1587|5031|
|1587|5032|.TOC 2, "IO Instructions"
|1587|5033|
000,000,1,11,06,1,32,0,00,0,0,00,00,11,00,00,0,20,1,1,1,01,36,00,3072,00,7,00,0,0,0,1588|5034|IO: #2*[IR]_[W1], ;Copy IR to W1 shifted left
|1588|5035| IF [USER] CALL [CHECK IO OK]
000,000,1,11,03,0,02,0,00,0,0,00,00,11,00,00,0,20,1,1,1,01,01,00,3067,00,7,00,0,0,0,1589|5036| #4*[W1]_B, ;Keep shifting
|1589|5037| CALL [#2*W1_W1 LOAD IR]
|1589|5038| DISPATCH [IO 0]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,06,01,00,0000,16,7,00,0,0,0,1590|5039|
000,000,1,11,06,1,02,0,00,0,0,00,00,11,00,00,0,20,1,1,1,12,01,00,0000,00,7,11,0,0,0,1591|5040|#2*W1_W1 LOAD IR:
|1591|5041| #2*[W1]_[W1], ;Keep shifting
|1591|5042| LOAD IR,RETURN
|1591|5043|
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,01,36,00,3072,00,7,00,0,0,0,1592|5044|IO 4:
|1592|5045|
|1592|5046|;Here for an illegal IO instruction
|1592|5047|XIO: IF [USER] CALL [CHECK IO OK]
|1592|5048| GOTOP [IFETCH]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,13,01,00,1420,00,7,00,0,0,0,1593|5049|
|1593|5050|;Here to check if EXEC or user IO is set
|1593|5051|; If IO is legal return, else do MUUO
000,000,0,04,10,1,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,12,37,00,4000,00,7,01,0,0,0,1594|5052|CHECK IO OK:
|1594|5053| J[04000]_[W1],IF [EXEC] RETURN ;Bit 24
000,000,0,04,10,0,02,2,00,0,0,00,00,00,00,00,0,20,1,1,0,12,46,00,0000,00,7,07,0,0,0,1595|5054| SWAP [W1]_[W1],IF [PXCT] RETURN ;Make bit 6-User I/O
000,000,0,14,14,0,02,0,03,0,0,00,00,00,00,00,0,64,1,1,1,12,03,00,0000,00,7,00,0,0,0,1596|5055| [W1]&[PC FLAGS]_Y,
|1596|5056| IF NOT CT [IZ] RETURN
|1596|5057| GOTOP [MUUO]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,13,01,00,1637,00,7,00,0,0,0,1597|5058|
|1597|5059|.TOC 1, "Executive Instructions"
|1597|5060|.TOC 2, "Arithmetic Processor"
|1597|5061|.TOC 3, "APRID - APR Identification"
|1597|5062|
|1597|5063|;Arithmetic Processor Identification
|1597|5064|; APRID
|1597|5065|; +-------+---+---+---+
|1597|5066|; | 70000 | I | X | Y |
|1597|5067|; +-------+---+---+---+
|1597|5068|;
|1597|5069|; 0 1 2 3 4 5 6 7 8 91011121314151617181920212223242526272829303132333435
|1597|5070|; | \ /\ / \ /
|1597|5071|; | | | + ---reserved
|1597|5072|; | | + ---u-code version number
|1597|5073|; | + ---reserved
|1597|5074|; +---u-code includes address break
|1597|5075|
000,000,0,01,06,1,57,0,54,0,0,00,00,51,00,00,0,20,1,1,0,16,00,00,4002,00,7,01,0,0,0,1598|5076|APRID:
|1598|5077|
|1598|5078|;Possible coding
|1598|5079|; J[X]_[MEM-OP] ;load bits 0-11
|1598|5080|; ROL [MEM-OP]_[MEM-OP],J[10.]_CTR
|1598|5081|; ROL [MEM-OP]-[MEM-OP],LOOP [.]
|1598|5082|; [MEM-OP]J[Y]-[MEM-OP] ;Add bits 12-23
|1598|5083|; ROL [MEM-OP]-[MEM-OP],J[10.]_CTR
|1598|5084|; ROL [MEM-OP]-[MEM-OP],LOOP [.]
|1598|5085|; [MEM-OP]J[Z]-[MEM-OP], ;Add bits 24-35
|1598|5086|; GOTO [TO MEMORY]
|1598|5087|
|1598|5088|
|1598|5089|.IFNOT/FTADRB
|1598|5090| J[U-CODE VERSION]_[MEM-OP] ;Put u-code version in register
|1598|5091|.ENDIF/FTADRB
|1598|5092|.IF/FTADRB
|1598|5093| J[U-CODE VERSION]_Y24-Y35, ;Put u-code version in register
|1598|5094| [BIT17]_F,F_ROR Y_[MEM-OP] ;Bit for address break feature
|1598|5095|.ENDIF/FTADRB
000,000,0,04,10,0,56,2,54,0,0,00,00,00,00,00,0,20,1,1,0,03,01,00,4371,00,7,07,0,0,0,1599|5096| SWAP [MEM-OP]_[MEM-OP], ;Put u-code version in lh
|1599|5097| GOTO [TO MEM]
|1599|5098|
|1599|5099|.TOC 3, "WRAPR - Write APR Conditions"
|1599|5100|;Conditions Out, arithmetic processor
|1599|5101|; WRAPR,
|1599|5102|; +-------+---+---+---+
|1599|5103|; | 70020 | I | X | Y |
|1599|5104|; +-------+---+---+---+
|1599|5105|;
|1599|5106|; E bits
|1599|5107|;
|1599|5108|; 181920212223242526272829303132333435
|1599|5109|; | | | | | | \ flags / | \ /
|1599|5110|; | | | | | | | + ---PIA
|1599|5111|; | | | | | | + ---should be zero
|1599|5112|; | | | | | + ---Set selected flags
|1599|5113|; | | | | + ---Clear selected flags
|1599|5114|; | | | + ---disable selected flags
|1599|5115|; | | + ---enable selected flags
|1599|5116|; | + ---clear all IO devices
|1599|5117|; + ---should be zero
|1599|5118|
000,000,0,01,06,1,57,0,00,0,0,00,00,51,00,00,0,20,1,1,0,16,00,00,0010,00,7,01,0,0,0,1600|5119|WRAPR:
|1600|5120|.IFNOT/FT7PI
|1600|5121| J[6]_[W1] ;Mask for PI channel
|1600|5122| [W1]&[E]_Y,IX_MX
|1600|5123| ROR [W1]_[W1], ;Make mask for bit 35
|1600|5124| IF NOT CT [MZ] THEN [CNAPR1]
|1600|5125| [W1]&[E]_Y, ;May not put on channel 1
|1600|5126| IF NOT CT [IZ] THEN [MUUO]
|1600|5127|CNAPR1:
|1600|5128|.ENDIF/FT7PI
|1600|5129|.IF/FTMBZ
|1600|5130| J[0010]_Y24-Y35,[BIT17]_F, ;Makes 0,,400010
|1600|5131| F_ROR Y_[W1]
000,000,0,14,14,0,02,0,40,0,0,00,00,00,00,00,0,64,1,1,1,03,03,00,1637,00,7,00,0,0,0,1601|5132| [W1]&[E]_Y, ;Check for illegitimate bits
|1601|5133| IF NOT CT [IZ] THEN [MUUO]
|1601|5134|.ENDIF/FTMBZ
|1601|5135| J[04000]_[W1] ;Mask to test bits
000,000,0,06,03,0,02,0,00,0,0,00,00,00,00,03,0,20,1,1,0,16,00,00,0556,00,7,01,0,0,0,1603|5136| [W1]+[W1]_Q, ;Put mask in Q reg
|1603|5137| J[APR FLAGS]_RAMFILE ADR
|1603|5138| J[07760]_[W2] ;Mask for flags
000,000,0,04,10,1,00,0,04,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,7760,00,7,01,0,0,0,1604|5139| [E]&[W2]_B ;leave only flags
000,000,0,04,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,3132,00,7,04,0,0,0,1606|5140| RAMFILE_[W1], ;Get processor flags
|1606|5141| CALL [CAPR X] ; Turn on/turn off flags
000,000,0,04,10,0,06,2,04,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,3135,00,7,07,0,0,0,1607|5142| SWAP [W2]_[W2], ;Swap halves
|1607|5143| CALL [CAPR Y] ; Turn off/turn on flags
|1607|5144| J[7]_[W2] ;Mask for PI chnl
000,000,0,04,10,1,00,0,04,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0007,00,7,01,0,0,0,1608|5145| [W2]BAR&[W1]_B ;Strip old PI chnl
000,000,0,04,11,0,06,0,00,0,0,00,00,00,00,00,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,1609|5146| [E]&[W2]_B ;leave only PI chnl
000,000,0,04,14,0,42,0,04,0,0,00,00,00,00,00,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,1610|5147|.IFNOT/FT7PI
|1610|5148| [W2]+[K -1]_Y, ;Check for setting PI level 1
|1610|5149| IF CT [IZ] THEN [MUUO] ;No you do not
|1610|5150|.ENDIF/FT7PI
000,000,0,14,17,0,06,0,00,0,0,00,00,00,00,00,0,20,1,1,1,16,00,00,0000,00,7,04,0,0,0,1611|5151| [W2].OR.[W1]_Y,ALU_RAMFILE ;Save updated APR flags
000,000,1,15,14,1,42,0,00,0,0,00,00,11,00,00,0,64,1,1,1,01,03,00,3117,00,7,00,0,0,0,1612|5152| Q&[E]_F,ALU_Y/YES,#2*Q_Q, ;Test for IO reset
|1612|5153| IF NOT CT [IZ] CALL [RESET IO]
|1612|5154| CALL [SET PROC REG]
000,000,0,14,10,0,00,0,00,0,0,00,14,00,00,00,0,20,1,1,0,13,01,00,1420,00,7,00,0,0,0,1614|5155| SET LOCAL,
|1614|5156| GOTOP [IFETCH]
|1614|5157|
|1614|5158|;Here to perform an IO reset function
|1614|5159|; Wave IO RESET, clear all APR flags, clear all TTY flags
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,03,0,20,1,1,0,16,00,00,0556,00,7,01,0,0,0,1615|5160|RESET IO:
|1615|5161| J[APR FLAGS]_RAMFILE ADR ;Address APR flags
000,000,0,14,10,1,00,0,00,0,0,00,00,00,00,00,0,20,1,1,1,16,00,00,0000,00,7,04,0,0,0,1616|5162| ZERO_Y,ALU_RAMFILE ;Clear flags
000,000,0,04,10,1,00,0,24,0,0,00,00,00,00,03,0,20,1,1,0,16,00,00,0200,00,7,01,0,0,0,1617|5163| J[LNOSW]_[W6],Y_RAMFILE ADR ;Address first TTY link block
|1617|5164| J[04200]_[W6] ; CR5-RTS, CR1=DTR
000,000,0,04,10,1,00,0,24,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,4200,00,7,01,0,0,0,1618|5165| SWAP [W5]_[W5]
000,000,1,11,03,0,22,0,20,0,0,00,00,11,00,00,0,20,1,1,1,16,00,00,0000,00,7,04,0,0,0,1620|5166| #4*[W5]_B,ALU_RAMFILE ;Save initial CTY status
000,000,0,06,06,1,26,0,00,0,1,00,00,00,00,00,0,20,1,1,0,14,00,00,0075,00,7,00,0,0,0,1621|5167| [W6]+1_F,F_Q,J[075]_CTR ;Address mode word
000,000,0,06,06,1,00,0,00,0,1,00,00,00,00,03,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,1622|5168|IOR2: Q+1_F,F_Q_Y,Y_RAMFILE ADR ;Address next location
000,000,0,14,10,1,00,0,00,0,0,00,00,00,00,00,0,20,1,1,1,11,00,00,3126,00,7,04,0,0,0,1623|5169| ZERO_Y,ALU_RAMFILE,LOOP [IOR2]
|1623|5170| ;J[02000]_[W1] ;Bit for IO reset
|1623|5171| ;[W1]_Y,ALU_PROC REG, ;Tell processor reset
|1623|5172| ; CALL [SET PROC REG] ; Then tell it right info
000,000,0,14,10,1,00,0,00,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,3225,00,7,10,0,0,0,1624|5173| ZERO_Y,ALU_PROC REG, ;Clean processor reg
|1624|5174| CALL [SET PROC REG] ; Then load it
|1624|5175| GOTO [SET PCI MODE] ;Set mode for CTY
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,03,01,00,3500,00,7,00,0,0,0,1625|5176|
|1625|5177|;Here to test for set/lest for clear flags
|1625|5178|; Mask (to be shifted left) is in Q and is tested with E
|1625|5179|; W2 is ored or bar&ed into W1
|1625|5180|
000,000,1,15,14,1,42,0,00,0,0,00,00,11,00,00,0,64,1,1,1,01,03,00,3140,00,7,00,0,0,0,1626|5181|CAPR X: Q&[E]_F,ALU_Y/YES,#2*Q_Q, ;Test for set selected flags/enables
|1626|5182| IF NOT CT [IZ] CALL [W2.OR.W1] ;Set selected flags/enables
000,000,1,15,14,1,42,0,00,0,0,00,00,11,00,00,0,64,1,1,1,12,02,00,0000,00,7,00,0,0,0,1627|5183| Q&[E]_F,ALU_Y/YES,#2*Q_Q, ;Test for clear selected flags/enables
|1627|5184| IF CT [IZ] RETURN
000,000,0,04,11,0,06,0,00,0,0,00,00,00,00,00,0,20,1,1,1,12,01,00,0000,00,7,00,0,0,0,1628|5185|W2BAR&W1_B:
|1628|5186| [W2]BAR&[W1]_B, ;Clear selected flags/enables
|1628|5187| RETURN
|1628|5188|
|1628|5189|;Here to test for clear/test for set flags
|1628|5190|; Mask (to be shifted left) is in Q and is tested with E
|1628|5191|; W2 is ored or bar&ed into W1
000,000,1,15,14,1,42,0,00,0,0,00,00,11,00,00,0,64,1,1,1,03,02,00,3137,00,7,00,0,0,0,1629|5192|CAPR Y: Q&[E]_F,ALU_Y/YES,#2*Q_Q, ;Test for set selected flags/enables
|1629|5193| IF CT [IZ] THEN [CAPRY2]
|1629|5194| [W2]BAR&[W1]_B ;Clear selected flags/enables
000,000,1,15,14,1,42,0,00,0,0,00,00,11,00,00,0,64,1,1,1,12,02,00,0000,00,7,00,0,0,0,1631|5195|CAPRY2: Q&[E]_F,ALU_Y/YES,#2*Q_Q, ;Test for clear selected flags/enables
|1631|5196| IF CT [IZ] RETURN
000,000,0,04,17,0,06,0,00,0,0,00,00,00,00,00,0,20,1,1,1,12,01,00,0000,00,7,00,0,0,0,1632|5197|W2.OR.W1:
|1632|5198| [W2].OR.[W1]_B, ;Set selected flags/enables
|1632|5199| RETURN
|1632|5200|
|1632|5201|.TOC 3, "RDAPR - Read APR Conditions"
|1632|5202|;Conditions In, arithmetic processor
|1632|5203|; RDAPR,
|1632|5204|; +-------+---+---+---+
|1632|5205|; | 70024 | I | X | Y |
|1632|5206|; +-------+---+---+---+
|1632|5207|;
|1632|5208|; 0 1 2 3 4 5 6 7 8 91011121314151617181920212223242526272829303132333435
|1632|5209|; \ flags / \ flags / | \ /
|1632|5210|; | | | + ---PIA
|1632|5211|; | | + ---intrupt req
|1632|5212|; | + ---flags
|1632|5213|; + ---flags enabled for interrupts
|1632|5214|
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,3143,00,7,00,0,0,0,1633|5215|RDAPR:
|1633|5216| CALL [CI APR]
|1633|5217| GOTO [TO MEM] ;Store results and exit
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,03,01,00,4371,00,7,00,0,0,0,1634|5218|
|1634|5219|;Here for RDAPR, SZAPR, or SNAPR,
|1634|5220|
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,03,0,20,1,1,0,16,00,00,0556,00,7,01,0,0,0,1635|5221|CI APR: J[APR FLAGS]_RAMFILE ADR ;Where we keep f1ags
|1635|5222| RAMFILE_[MEM-OP]
000,000,0,04,10,0,00,0,54,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0000,00,7,04,0,0,0,1636|5223| SWAP [MEM-OP]_[W1] ;Put enables in RH
000,000,0,14,14,0,56,0,00,0,0,00,00,00,00,00,0,20,1,0,1,16,00,00,0000,00,7,00,0,0,0,1638|5224| [MEM-OP]&[W1]_Y,IX_MX ;Mask bits
000,000,0,04,10,1,00,0,00,0,0,00,00,00,00,00,0,44,1,1,0,12,02,00,0010,00,7,01,0,0,0,1639|5225| J[0010]_[W1], ;Bit for interrupt request
|1639|5226| IF CT [MZ] RETURN
000,000,0,04,17,0,02,0,54,0,0,00,00,00,00,00,0,20,1,1,1,12,01,00,0000,00,7,00,0,0,0,1640|5227| [W1].OR.[MEM-OP]_B,
|1640|5228| RETURN
|1640|5229|
|1640|5230|.TOC 3, "SZAPR (CONSZ APR) - Skip on masked APR conditions all zero"
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,3143,00,7,00,0,0,0,1641|5231|CONSZ APR:
|1641|5232|SZAPR:
|1641|5233| CALL [CI APR] ;Get APR bits for CONI
000,000,0,04,10,1,00,0,55,0,0,00,00,00,00,00,0,20,1,1,1,03,01,00,3276,00,7,00,0,0,0,1642|5234| ZERO_[MEM-OP LH],
|1642|5235| GOTO [CONSZ]
|1642|5236|
|1642|5237|.TOC 3, "SNAPR (CONSO APR) - Skip on any masked APR conditions non-zero"
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,3143,00,7,00,0,0,0,1643|5238|CONSO APR:
|1643|5239|SNAPR:
|1643|5240| CALL [CI APR] ;Get APR bits for CONI
000,000,0,04,10,1,00,0,55,0,0,00,00,00,00,00,0,20,1,1,1,03,01,00,3301,00,7,00,0,0,0,1644|5241| ZERO_[MEM-OP LH],
|1644|5242| GOTO [CONSO]
|1644|5243|
|1644|5244|
|1644|5245|.TOC 2, "PI System"
|1644|5246|.TOC 3, "WRPI - Write PI Conditions"
|1644|5247|;Conditions Out, Priority Interrupt
|1644|5248|; WRPI,
|1644|5249|; +-------+---+---+---+
|1644|5250|; | 70060 | I | X | Y |
|1644|5251|; +-------+---+---+---+
|1644|5252|;
|1644|5253|; E bits
|1644|5254|; 181920212223242526272829303132333435
|1644|5255|; \ / | | | | | | | 1 2 3 4 5 6 7
|1644|5256|; \ / | | | | | | | \ /
|1644|5257|; \ / | | | | | | | + ---Select levels
|1644|5258|; | | | | | | | + ---Turn on PI system
|1644|5259|; | | | | | | + ---Turn off PI system
|1644|5260|; | | | | | + ---Turn off level
|1644|5261|; | | | | + ---Turn on level
|1644|5262|; | | | + ---initiate interrupt on level
|1644|5263|; | | + ---clear PI system
|1644|5264|; | + ---drop program request on level
|1644|5265|; + ---should be zero
|1644|5266|
000,000,0,04,10,1,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,7400,00,7,01,0,0,0,1645|5267|WRPI:
|1645|5268|.IF/FT7PI
|1645|5269|.IF/FTMBZ
|1645|5270| J[07400]_[W1] ;Mask for must be zero bits
000,000,1,11,03,0,02,0,00,0,0,00,00,11,00,00,0,20,1,1,1,01,01,00,3322,00,7,00,0,0,0,1646|5271| #4*[W1]_B, ;Shift 6 places and check
|1646|5272| CALL [LLS4 MBZ]
|1646|5273|.ENDIF/FTMBZ
|1646|5274| BIT0_[W2] ;Bit for PI on
000,000,0,01,10,1,00,0,04,0,0,00,00,05,00,00,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,1647|5275| J[0177]_[W3] ;Mask for chnl bits
000,000,0,06,06,1,12,0,00,0,1,00,00,00,00,03,0,20,1,1,0,16,00,00,0561,00,7,01,0,0,0,1649|5276| [W3]+1_Q, ; Put 200 in Q
|1649|5277| J[PI LVL REG]_RAMFILE ADR
|1649|5278| [E]&[W3]_B ;Leave only chnls to select
000,000,0,04,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,3132,00,7,04,0,0,0,1651|5279| RAMFILE_[W1], ;Get PI LVL REG from ramfile
|1651|5280| CALL [CAPR X] ; Test for PION/PIOFF
|1651|5281|.ENDIF/FT7PI
|1651|5282|.IFNOT/FT7PI
|1651|5283|.IF/FTMBZ
|1651|5284| J[07401]_[W1] ;Mask for must be zero bits
000,000,1,11,03,0,02,0,00,0,0,00,00,11,00,00,0,20,1,1,1,01,01,00,3322,00,7,00,0,0,0,1653|5285| #4*[W1]_B, ;Shift 6 places and check
|1653|5286| CALL [LLS4 MBZ]
|1653|5287|.ENDIF/FTMBZ
|1653|5288| BIT0_[W2] ;Bit for PI on
000,000,0,01,10,1,00,0,04,0,0,00,00,05,00,00,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,1654|5289| [K 77]_[W3] ;Mask for chnl bits
000,000,0,06,06,1,12,0,00,0,1,00,00,00,00,03,0,20,1,1,0,16,00,00,0561,00,7,01,0,0,0,1656|5290| [W3]+1_Q, ; Put 100 in Q
|1656|5291| J[PI LVL REG]_RAMFILE ADR
|1656|5292| [E]&[W3]_B ;Leave only chnls to select
000,000,1,13,10,0,00,0,00,0,0,00,00,31,00,00,0,20,1,1,0,01,01,00,3132,00,7,04,0,0,0,1658|5293| RAMFILE_Y,Y_[W1] QLS_Q, ;Put PI LVL REG in W1
|1658|5294| QION_SIO0 #0_QIO0, ; Put 200 in Q
|1658|5295| CALL [CAPR X] ; Test for PION/PIOFF
|1658|5296|.ENDIF/FT7PI
000,000,0,04,06,1,12,0,04,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,3135,00,7,00,0,0,0,1659|5297| [W3]_[W2], ;Test for turn off/on levels
|1659|5298| CALL [CAPR Y] ; Set/clear bits in W1
|1659|5299| [W1]_RAMFILE ;Save updated PI LVL REG
000,000,0,14,14,0,77,0,00,0,0,00,00,00,00,00,0,20,1,1,1,16,00,00,0000,00,7,04,0,0,0,1660|5300| J[PI SFT REQ]_RAMFILE ADR
000,000,1,15,14,1,42,0,00,0,0,00,00,11,00,00,0,20,1,0,1,16,00,00,0000,00,7,00,0,0,0,1662|5301| Q&[E]_F,ALU_Y/YES,#2*Q_Q,IX_MX ;Test for initiate int on level
000,000,0,04,10,0,00,0,04,0,0,00,00,00,00,00,0,44,1,1,0,03,02,00,3201,00,7,04,0,0,0,1663|5302| RAMFILE_[W2], ;Get software interrupt requests
|1663|5303| IF CT [MZ] THEN [C PI 5]
000,000,0,04,17,0,12,0,04,0,0,00,00,00,00,00,0,20,1,1,1,16,00,00,0000,00,7,04,0,0,0,1664|5304| [W3].OR.[W2]_B,ALU_RAMFILE ;Add new levels
000,000,1,15,14,1,42,0,00,0,0,00,00,11,00,00,0,64,1,1,1,03,02,00,3204,00,7,00,0,0,0,1665|5305|C PI 5: Q&[E]_F,ALU_Y/YES,#2*Q_Q, ;Test for clear PI system
|1665|5306| IF CT [IZ] THEN [C PI 6]
|1665|5307| CALL [RESET PI] ;Reset the PI system
000,000,0,14,10,0,00,0,00,0,0,00,14,00,00,00,0,20,1,1,0,13,01,00,1420,00,7,00,0,0,0,1667|5308| SET LOCAL, GOTOP [IFETCH]
|1667|5309|
000,000,0,14,14,1,42,0,00,0,0,00,00,00,00,00,0,64,1,1,1,03,02,00,3206,00,7,00,0,0,0,1668|5310|C PI 6: Q&[E]_Y, ;Test for drop int on level
|1668|5311| IF CT [IZ] THEN [C PI 7]
000,000,0,04,11,0,12,0,04,0,0,00,00,00,00,00,0,20,1,1,1,16,00,00,0000,00,7,04,0,0,0,1669|5312| [W3]BAR&[W2]_B,ALU_RAMFILE ;Clear some levels
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,3224,00,7,00,0,0,0,1670|5313|C PI 7: CALL [SET PI SYSTEM] ;Setup PI hdw
000,000,0,14,10,0,00,0,00,0,0,00,14,00,00,00,0,20,1,1,0,13,01,00,1420,00,7,00,0,0,0,1671|5314| SET LOCAL,GOTOP [IFETCH]
|1671|5315|
|1671|5316|
|1671|5317|;Here to reset the PI system
|1671|5318|
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,03,0,20,1,1,0,16,00,00,0557,00,7,01,0,0,0,1672|5319|RESET PI:
|1672|5320| J[PI IN PROG]_RAMFILE ADR ;Ints in progress in bits 29-35
000,000,0,14,10,1,00,0,00,0,0,00,00,00,00,00,0,20,1,1,1,16,00,00,0000,00,7,04,0,0,0,1673|5321| ZERO_Y,ALU_RAMFILE
|1673|5322| J[PI SFT REQ]_RAMFILE ADR ;Software PI requests
000,000,0,14,10,1,00,0,00,0,0,00,00,00,02,00,0,20,1,1,1,16,00,00,0000,00,7,04,0,0,0,1675|5323| ZERO_Y,ALU_RAMFILE,
|1675|5324| INT OP/MASTER CLEAR ;bits 29-35 are levels on
|1675|5325| J[PI LVL REG]_RAMFILE ADR ;bit 0 is PI system on/off flag
000,000,0,04,10,1,00,0,43,0,0,00,00,00,46,00,0,20,1,1,1,03,01,00,3224,00,7,04,0,0,0,1677|5326| ZERO_[PI REG],ALU_RAMFILE,
|1677|5327| Y_2914 STATUS,
|1677|5328| GOTO [SET PI SYSTEM] ;Set mask register
|1677|5329|
|1677|5330|;Here to set up 2914 PI mask
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,03,0,20,1,1,0,16,00,00,0561,00,7,01,0,0,0,1678|5331|SET PI MASK:
|1678|5332| J[PI LVL REG]_RAMFILE ADR ;Address ramfile list of levels on
|1678|5333| J[0300]_[W2] ;Always enable level 0 and 1
000,000,0,04,10,1,00,0,04,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0300,00,7,01,0,0,0,1679|5334| RAMFILE_[W1] ;Get levels from ramfile
000,000,0,14,06,1,02,0,00,0,0,00,00,00,00,00,0,76,1,1,1,03,03,00,3223,00,7,00,0,0,0,1681|5335| [W1]_Y,
|1681|5336| IF NOT CT [IN] THEN [SPM 7]
|1681|5337| [W1].OR.[W2]_B ;Enable software levels also
000,000,0,14,07,0,06,0,00,0,0,00,00,00,72,00,0,20,1,1,1,12,01,00,0000,00,7,00,0,0,0,1683|5338|SPM 7: COMPLEMENT [W2]_F,F_Y, ;Load mask with PIs to permit
|1683|5339| Y_2914 MASK,
|1683|5340| RETURN
|1683|5341|
|1683|5342|;Here to setup PI system
|1683|5343|
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,3216,00,7,00,0,0,0,1684|5344|SET PI SYSTEM:
|1684|5345| CALL [SET PI MASK]
|1684|5346| ;GOTO [SET PROC REG]
|1684|5347|
|1684|5348|
|1684|5349|;PROC REG (Processor register)
|1684|5350|; 0 1 2 3 4 5 6 7 8 91011121314151617181920212223242526272829303132333435
|1684|5351|; \ / \ / |\ / \ /
|1684|5352|; | | | | + ---PI req
|1684|5353|; | | | + ---Line PI reg
|1684|5354|; | | + ---IO reset
|1684|5355|; + ---Current AC block + ---reserved
|1684|5356|;
|1684|5357|;Ramfile word [PROC REG]
|1684|5358|;0 1 2 3 4 5 6 7 8 91011l2l3l41516l7l81920212223242526272829303132333435
|1684|5359|; \ / \ / \ / \ /
|1684|5360|; | + ---Prev ctxt AC block | + ---Line PI lvl
|1684|5361|; + ---Current AC block + ---reserved
|1684|5362|
|1684|5363|
|1684|5364|;Here to set up hardware PROC reg according to Ramfile
|1684|5365|; Called whenever APR/TTY/SoftwarePIReq change
|1684|5366|; Uses W1-W4
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,03,0,20,1,1,0,16,00,00,0560,00,7,01,0,0,0,1685|5367| SET PROC REG:
|1685|5368| J[PI SFT REQ]_RAMFILE ADR ;Ramfile list of software pi reqs
|1685|5369| RAMFILE_[W4]
000,000,0,04,10,0,00,0,14,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0000,00,7,04,0,0,0,1686|5370| J[APR FLAGS]_RAMFILE ADR ;Address APR flags
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,03,0,20,1,1,0,16,00,00,0556,00,7,01,0,0,0,1687|5371| RAMFILE_[W1] ;Get APR flags
000,000,0,04,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0000,00,7,04,0,0,0,1688|5372| SWAP [W1]_[W2] ;Swap flags and enables
000,000,0,14,14,0,02,0,04,0,0,00,00,00,00,00,0,64,1,1,1,01,03,00,3251,00,7,00,0,0,0,1690|5373| [W1]&[W2]_Y, ;Check for flags with enables
|1690|5374| IF NOT CT [IZ] CALL [SPR 77] ;Set request level
|1690|5375| J[04000]_[W1] ;Will become 020000
000,000,1,11,03,0,02,0,00,0,0,00,00,11,00,00,0,20,1,1,0,16,00,00,2220,00,7,01,0,0,0,1692|5376| J[02220]_Y24-Y35, ;Mask for flags -022220
|1692|5377| [W1]+[W1]_F,F_LSZ Y_[W1]
000,000,0,06,06,1,02,0,00,0,0,00,00,00,00,00,0,20,1,1,0,14,00,00,0007,00,7,00,0,0,0,1693|5378| [W1]_Q,J[7]_CTR ;Save mask
000,000,0,04,10,1,00,0,10,0,0,00,00,00,00,03,0,20,1,1,0,16,00,00,0200,00,7,01,0,0,0,1694|5379| J[LNOSW]_[W3],Y_RAMFILE ADR ;Address line block
000,000,0,04,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0000,00,7,04,0,0,0,1695|5380|SPR 2: RAMFILE_[W1] ;Get status for line
000,000,1,11,14,1,02,0,04,0,0,00,00,11,00,00,0,64,1,1,1,03,02,00,3242,00,7,00,0,0,0,1696|5381| Q&[W1]_F,LSZ F_[W2], ;Check for any flags set
|1696|5382| IF CT [IZ] THEN [SPR 4]
000,000,0,14,14,0,02,0,04,0,0,00,00,00,00,00,0,64,1,1,1,01,03,00,3251,00,7,00,0,0,0,1697|5383| [W1]&[W2]_Y, ;Check for enables for flags
|1697|5384| IF NOT CT [IZ] CALL [SPR 77] ; Set int req
000,000,0,04,10,1,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0010,00,7,01,0,0,0,1698|5385|SPR 4: J[010]_[W1] ;To make next line adr
000,000,0,04,03,0,02,0,10,0,0,00,00,00,00,03,0,20,1,1,1,11,00,00,3237,00,7,00,0,0,0,1699|5386| [W1]+[W3]_B,Y_RAMFILE ADR, ;Next block adr
|1699|5387| LOOP [SPR 2]
|1699|5388| J[PROC REG]_RAMFILE ADR ; Address ramfile copy of proc reg
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,03,0,20,1,1,0,16,00,00,0562,00,7,01,0,0,0,1700|5389| RAMFILE_[W3] ;Get ramfile copy of proc reg
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,03,0,20,1,1,0,16,00,00,0563,00,7,01,0,0,0,1702|5390|SET RFPRG:
|1702|5391| J[RF PROC REG]_RAMFILE ADR
000,000,0,14,17,0,16,0,10,0,0,00,00,00,00,00,0,20,1,1,1,16,00,00,0000,00,7,04,0,0,0,1703|5392| [W4].OR.[W3]_Y,ALU_RAMFILE
000,000,0,14,17,0,16,0,10,0,0,00,00,00,00,00,0,20,1,1,1,12,01,00,0000,00,7,10,0,0,0,1704|5393| [W4].OR.[W3]_Y,ALU_PROC REG, ;Change software interrupts
|1704|5394| RETURN
|1704|5395|
000,000,0,04,10,1,00,0,04,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0007,00,7,01,0,0,0,1705|5396|SPR 77: J[7]_[W2] ;Mask for PI level
000,000,0,04,14,0,06,0,00,0,0,00,00,00,00,00,0,64,1,1,1,12,02,00,0000,00,7,00,0,0,0,1706|5397| [W2]&[W1]_B,IF CT [IZ] RETURN ;If no channel dismiss
|1706|5398| J[BIT28]_[W2] ;Base to index into bit table
000,000,0,14,03,0,06,0,00,0,0,00,00,00,00,03,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,1708|5399| [W2]+[W1]_Y,Y_RAMFILE ADR ;Make bit for our level
|1708|5400| RAMFILE_[W1] ;Get bit for interrupt
000,000,0,04,17,0,02,0,14,0,0,00,00,00,00,00,0,20,1,1,1,12,01,00,0000,00,7,00,0,0,0,1710|5401| [W1].OR.[W4]_B,RETURN ; Set 1evel
|1710|5402|
|1710|5403|
|1710|5404|.TOC 3, "RDPI - Read PI Conditions"
|1710|5405|;Conditions In, Priority Interrupt
|1710|5406|; RDPI,
|1710|5407|; +-------+---+---+---+
|1710|5408|; | 70064 | I | X | Y |
|1710|5409|; +-------+---+---+---+
|1710|5410|;
|1710|5411|;0 1 2 3 4 5 6 7 8 91011121314151617181920212223242526272829303132333435
|1710|5412|; 1 2 3 4 5 6 7 1 2 3 4 5 6 7 | 1 2 3 4 5 6 7
|1710|5413|; \ / \ / | \ /
|1710|5414|; | | | + ---levels on
|1710|5415|; | | + ---PI system on
|1710|5416|; | + ---interrupt in progress on
|1710|5417|; + ---program requests on
|1710|5418|
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,3263,00,7,00,0,0,0,1711|5419|RDPI:
|1711|5420| CALL [CPI] ;Get PI bits
|1711|5421| J[PI SFT REQ]_RAMFILE ADR ;Get software requests
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,03,0,20,1,1,0,16,00,00,0560,00,7,01,0,0,0,1712|5422| RAMFILE_[W1] ;Get software requests
000,000,0,04,10,0,02,2,55,0,0,00,00,00,00,00,0,20,1,1,0,03,01,00,4371,00,7,07,0,0,0,1714|5423| SWAP [W1]_[MEM-OP LH],
|1714|5424| GOTO [TO MEM] ;Give user result
|1714|5425|
|1714|5426|;Here from CONI PI, or CONSO PI, or CONSZ PI
|1714|5427|; Returns bits in MEM-OP, and 177 in W1
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,03,0,20,1,1,0,16,00,00,0561,00,7,01,0,0,0,1715|5428|CPI: J[PI LVL REG]_RAMFILE ADR ;Get PI levels on
|1715|5429| J[0177]_[W1] ;Mask for levels
000,000,0,07,06,1,02,0,00,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0000,00,7,04,0,0,0,1717|5430| RAMFILE_Y,[W1]_F,F_Q Y_[W1]
|1717|5431| J[PI IN PROG]_RAMFILE ADR
000,000,0,14,06,1,02,0,00,0,0,00,00,00,00,00,0,20,1,0,1,16,00,00,0000,00,7,00,0,0,0,1719|5432| [W1]_Y,IX_MX ;Test for PI on
000,000,0,04,14,1,02,0,54,0,0,00,00,00,00,00,0,56,1,1,1,03,03,00,3272,00,7,00,0,0,0,1720|5433| Q&[W1]_[MEM-OP], ;Leave only PI levels on
|1720|5434| IF NOT CT [MN] THEN [CP12] ; Branch if PI OFF
000,000,0,04,03,1,56,0,54,0,1,00,00,00,00,00,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,1721|5435| Q+[MEM-OP]+1_F,F_[MEM-OP] ;Add 200 to MEM-OP
000,000,0,04,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,04,01,00,0003,00,7,04,0,0,0,1722|5436|CP12: RAMFILE_[W1],PUSH J[3]_CTR
000,000,1,11,03,0,02,0,00,0,0,00,00,11,00,00,0,20,1,1,1,10,00,00,0000,00,7,00,0,0,0,1723|5437| #4*[W1]_B,RFCT ;Shift left 8 places
000,000,0,04,17,0,02,0,54,0,0,00,00,00,00,00,0,20,1,1,1,12,01,00,0000,00,7,00,0,0,0,1724|5438| [W1].OR.[MEM-OP]_B, ;Add interrupts in progress
|1724|5439| RETURN
|1724|5440|
|1724|5441|.TOC 3, "SZPI - Skip on masked PI conditions all zero"
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,3263,00,7,00,0,0,0,1725|5442|SZPI:
|1725|5443| CALL [CPI] ;Get bits to test in MEM-OP
000,000,0,14,14,0,56,0,40,0,0,00,14,00,00,00,0,64,1,1,1,13,03,00,1420,00,7,00,0,0,0,1726|5444|CONSZ: [MEM-OP]&[E]_Y,
|1726|5445| SET LOCAL,
|1726|5446| IF NOT CT [IZ] THENP [IFETCH]
000,000,0,04,06,1,36,0,36,0,1,00,00,00,00,00,0,20,1,1,1,13,01,00,1420,00,7,00,0,0,0,1727|5447| [PC]+1_[PC RH],
|1727|5448| GOTOP [IFETCH]
|1727|5449|
|1727|5450|.TOC 3, "SNPI - Skip on any masked PI conditions non-zero"
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,3263,00,7,00,0,0,0,1728|5451|SNPI:
|1728|5452| CALL [CPI] ;Get bits to test in MEM-OP
000,000,0,14,14,0,56,0,40,0,0,00,14,00,00,00,0,64,1,1,1,13,02,00,1420,00,7,00,0,0,0,1729|5453|CONSO: [MEM-OP]&[E]_Y,
|1729|5454| SET LOCAL,
|1729|5455| IF CT [IZ] THENP [IFETCH]
000,000,0,04,06,1,36,0,36,0,1,00,00,00,00,00,0,20,1,1,1,13,01,00,1420,00,7,00,0,0,0,1730|5456| [PC]+1_[PC RH],
|1730|5457| GOTOP [IFETCH]
|1730|5458|
|1730|5459|.TOC 2, "Pager"
|1730|5460|.TOC 3, "WREBR - Write Executive Base Address"
|1730|5461|
|1730|5462|; WREBR
|1730|5463|; +-------+---+---+---+
|1730|5464|; | 70120 | I | X | Y |
|1730|5465|; +-------+---+---+---+
|1730|5466|;
|1730|5467|; E format
|1730|5468|; 181920212223242526272829303132333435
|1730|5469|; \ / | | \ /
|1730|5470|; \ / | | + ---Executive base address (page number)
|1730|5471|; | | + ---Enable Pager
|1730|5472|; | + ---Tops20 Paging
|1730|5473|; + ---should be zero
|1730|5474|
000,000,0,04,10,1,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,7000,00,7,01,0,0,0,1731|5475|WREBR:
|1731|5476|.IF/FTMBZ
|1731|5477| J[07000]_[W1]
000,000,1,11,03,0,02,0,00,0,0,00,00,11,00,00,0,20,1,1,1,01,01,00,3322,00,7,00,0,0,0,1732|5478| #4*[W1]_B,
|1732|5479| CALL [LLS4 MBZ]
|1732|5480|.ENDIF/FTMBZ
|1732|5481| CALL [PAGE TABLE CLEAR] ;Clear entire page table
000,000,0,04,06,1,42,0,00,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,3316,00,7,00,0,0,0,1734|5482| [E]_[W1], ;Get page number
|1734|5483| CALL [W1(22) LLS9]
|1734|5484| J[BIT22]_RAMFILE ADR ;Mask for enable
000,000,0,04,14,1,06,0,17,0,0,00,54,00,00,00,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,1736|5485| Q&[W2]_[EPT],SET TOPS20 ;Set new EPT
000,000,0,07,06,1,42,0,04,0,0,00,30,00,00,00,0,20,1,1,0,16,00,00,0000,00,7,04,0,0,0,1737|5486| [E]_Q RAMFILE_[W2],CLEAR PAGED ;Get bit for enable
000,000,0,03,14,0,06,0,40,0,0,00,00,51,00,00,0,64,1,1,1,01,03,00,3315,00,7,00,0,0,0,1738|5487| [W2]&[E]_F,ROR F_B ROR Q_Q,
|1738|5488| IF NOT CT [IZ] CALL [SET PAGED LATCH]
|1738|5489|.IF/FT10PAG
|1738|5490|.IF/FT20PAG
000,000,0,14,14,1,06,0,00,0,0,00,00,00,00,00,0,64,1,1,1,03,03,00,4127,00,7,00,0,0,0,1739|5491| Q&[W2]_Y,
|1739|5492| IF NOT CT [IZ] THEN [TO NOWHERE]
|1739|5493|.ENDIF/FT20PAG
000,000,0,14,10,0,00,0,00,0,0,00,50,00,00,00,0,20,1,1,0,03,01,00,4127,00,7,00,0,0,0,1740|5494| CLEAR TOPS20,
|1740|5495| GOTO [TO NOWHERE]
|1740|5496|.ENDIF/FT10PAG
|1740|5497|.IFNOT/FT10PAG
|1740|5498| SET LOCAL,
|1740|5499| GOTO [IFETCH]
|1740|5500|.ENDIF/FT10PAG
|1740|5501|
000,000,0,14,10,0,00,0,00,0,0,00,34,00,00,00,0,20,1,1,0,12,01,00,0000,00,7,00,0,0,0,1741|5502|SET PAGED LATCH:
|1741|5503| SET PAGED,RETURN
|1741|5504|
|1741|5505|;Here to shift W1 left 9 places and get 22 bit mask
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,03,0,20,1,1,0,16,00,00,0026,00,7,01,0,0,0,1742|5506|W1(22) LLS9:
|1742|5507| J[#22B MASK]_RAMFILE ADR ;Mask for EPT adr
|1742|5508|
|1742|5509|;Here to shift W1 left 9 places, leave it in Q and W1 and read ramfile into W2
000,000,1,11,06,1,02,0,00,0,0,00,00,11,00,00,0,20,1,1,1,04,01,00,0003,00,7,00,0,0,0,1743|5510|W1 LLS9:
|1743|5511| #2*[W1]_[W1],PUSH J[3]_CTR ;Shift left 1 place
000,000,1,11,03,0,02,0,00,0,0,00,00,11,00,00,0,20,1,1,1,10,00,00,0000,00,7,00,0,0,0,1744|5512| #4*[W1]_B,RFCT ;Keep shifting 2 at a time
000,000,0,07,06,1,02,0,04,0,0,00,00,00,00,00,0,20,1,1,0,12,01,00,0000,00,7,04,0,0,0,1745|5513| [W1]_Q RAMFILE_[W2], ;Get ramfile
|1745|5514| RETURN
|1745|5515|
|1745|5516|.IF/FTMBZ
000,000,1,11,03,0,02,0,00,0,0,00,00,11,00,00,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,1746|5517|LLS4 MBZ:
|1746|5518| #4*[W1]_B
|1746|5519| #4*[W1]_B
000,000,0,14,14,0,02,0,40,0,0,00,00,00,00,00,0,64,1,1,1,12,02,00,0000,00,7,00,0,0,0,1748|5520| [W1]&[E]_Y,
|1748|5521| IF CT [IZ] RETURN
|1748|5522| GOTO [MUUO]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,03,01,00,1637,00,7,00,0,0,0,1749|5523|.ENDIF/FTMBZ
|1749|5524|
|1749|5525|.TOC 3, "RDEBR - Read the Executive Base Address"
|1749|5526|
|1749|5527|; RDEBR
|1749|5528|; +-------+---+---+---+
|1749|5529|; | 70124 | I | X | Y |
|1749|5530|; +-------+---+---+---+
|1749|5531|;
|1749|5532|; E format
|1749|5533|; 181920212223242526272829303132333435
|1749|5534|; \ / | | \ /
|1749|5535|; \ / | | + ---Executive base address (page number)
|1749|5536|; | | + ---Enable Pager
|1749|5537|; | + ---Tops20 Paging
|1749|5538|; + ---reserved
|1749|5539|
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,03,0,20,1,1,0,16,00,00,0126,00,7,01,0,0,0,1750|5540|RDEBR:
|1750|5541| J[BIT22]_RAMFILE ADR ;Bit for paging enabled
000,000,0,04,06,1,17,0,00,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,3317,00,7,00,0,0,0,1751|5542| [EPT]_[W1],
|1751|5543| CALL [W1 LLS9]
000,000,0,04,10,0,02,2,00,0,0,00,00,00,00,00,0,20,1,1,0,01,40,00,3140,00,7,07,0,0,0,1752|5544| SWAP [W1]_[W1], ;Put page number in right half
|1752|5545| IF [PAGED] CALL [W2.OR.W1] ;We are paged
000,000,1,11,06,1,06,0,04,0,0,00,00,11,00,00,0,20,1,1,1,01,44,00,3140,00,7,00,0,0,0,1753|5546| #2*[W2]_[W2], ;Make a bit 21
|1753|5547| IF [TOPS20] CALL [W2.OR.W1] ;Flag this is TOPS20
000,000,0,04,06,1,02,0,54,0,0,00,00,00,00,00,0,20,1,1,1,03,01,00,4371,00,7,00,0,0,0,1754|5548| [W1]_[MEM-OP],
|1754|5549| GOTO [TO MEM]
|1754|5550|
|1754|5551|.TOC 3, "WRUBR (DATAO PAG) - Write User Base Address"
|1754|5552|
|1754|5553|; WRUBR
|1754|5554|; +-------+---+---+---+
|1754|5555|; | 70114 | I | X | Y |
|1754|5556|; +-------+---+---+---+
|1754|5557|;
|1754|5558|; 0 1 2 3 4 5 6 7 8 91011121314151617181920212223242526272829303132333435
|1754|5559|; | | | \ / \ / \ / | \ /
|1754|5560|; | | | \ / \ / \ / | + ---User Base adr (page #)
|1754|5561|; | | | | | \ / + ---Do not update accounts
|1754|5562|; | | | | | + ---previous context section
|1754|5563|; | | | | + ---previous context ac block
|1754|5564|; | | | + ---current ac block
|1754|5565|; | | + ---load user base address
|1754|5566|; | + ---select previous context section
|1754|5567|; + ---select ac blocks
|1754|5568|
000,000,0,07,06,1,42,0,40,0,0,00,00,00,00,77,0,20,1,1,1,01,01,00,4663,00,7,00,0,0,0,1755|5569|DATAO PAG:
|1755|5570|WRUBR:
|1755|5571| READ [E] ;Get data word
|1755|5572| CALL [PAGE TABLE CLEAR] ;Clear entire page table
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,4420,00,7,00,0,0,0,1756|5573| BIT0_[W3] ;Get mask for enable
000,000,0,06,06,1,12,0,00,0,0,00,00,00,00,03,0,20,1,1,0,16,00,00,0562,00,7,01,0,0,0,1758|5574| J[PROC REG]_RAMFILE ADR, ;Where we keep AC block numbers
|1758|5575| [W3]_Q ;Save mask in Q reg
000,000,0,05,14,1,46,0,00,0,0,00,00,01,00,00,0,20,1,0,1,16,00,00,0000,00,7,00,0,0,0,1759|5576| Q&[MB]_F,F_Y LSRQ_Q,IX_MX ;latch request to set AC blocks
|1759|5577| RAMFILE_[W3] ;Get old value for AC block numbers
000,000,0,04,10,0,00,0,10,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0000,00,7,04,0,0,0,1760|5578| J[07700]_[4] ;Build mask for AC blocks
000,000,0,04,10,0,16,2,14,0,0,00,00,00,00,00,0,44,1,1,0,03,02,00,3346,00,7,07,0,0,0,1762|5579| SWAP [W4]_[W4],
|1762|5580| IF CT [MZ] THEN [DATOP2] ;If do not want to set blocks
|1762|5581| [W4]BAR&[W3]_B ;Strip old AC blocks
000,000,0,04,11,0,16,0,10,0,0,00,00,00,00,00,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,1763|5582| [MB]&[W4]_B ;New AC blocks
000,000,0,04,17,0,16,0,10,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,3246,00,7,04,0,0,0,1765|5583| [W4].OR.[W3]_B,ALU_RAMFILE,
|1765|5584| CALL [SET RFPRG]
000,000,0,05,14,1,46,0,00,0,0,00,00,01,00,00,0,64,1,1,1,03,02,00,3353,00,7,00,0,0,0,1766|5585|DATOP2: Q&[MB]_F,F_Y LSRQ_Q, ;Check for select prev context sect
|1766|5586| IF CT [IZ] THEN [DATOP4]
|1766|5587| J[PCS]_RAMFILE ADR ;Previous context section
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,03,0,20,1,1,0,16,00,00,0576,00,7,01,0,0,0,1767|5588| J[037]_[W1] ;Get maskk for section
000,000,0,04,10,1,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0037,00,7,01,0,0,0,1768|5589| SWAP [W1]_[W1]
000,000,0,14,14,0,02,0,44,0,0,00,00,00,00,00,0,20,1,1,1,16,00,00,0000,00,7,04,0,0,0,1770|5590| [W1]&[MB]_Y,ALU_RAMFILE ;Save previous context section
000,000,0,14,14,1,46,0,00,0,0,00,00,00,00,00,0,64,1,1,1,13,02,00,1420,00,7,00,0,0,0,1771|5591|DATOP4: Q&[MB]_Y, ;Check for load UBR
|1771|5592| IF CT [IZ] THENP [IFETCH]
000,000,0,04,06,1,46,0,00,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,3316,00,7,00,0,0,0,1772|5593| [MB]_[W1], ;Get page ruBber
|1772|5594| CALL [W1(22) LLS9]
000,000,0,04,14,1,06,0,23,0,0,00,00,00,00,00,0,20,1,1,1,13,01,00,1420,00,7,00,0,0,0,1773|5595| Q&[W2]_[UPT], ;Set new UPT
|1773|5596| GOTOP [IFETCH]
|1773|5597|
|1773|5598|.TOC 3, "RDUBR - Read User Base Address"
|1773|5599|;Data In, Pager
|1773|5600|; RDUBR
|1773|5601|; +-------+---+---+---+
|1773|5602|; | 70104 | I | X | Y |
|1773|5603|; +-------+---+---+---+
|1773|5604|;
|1773|5605|; 0 1 2 3 4 5 6 7 8 91011121314151617181920212223242526272829303132333435
|1773|5606|; | | | \ / \ / \ / \ /
|1773|5607|; | | | \ / \ / \ / + ---User Base adr (page #)
|1773|5608|; | | | | | \ /
|1773|5609|; | | | | | + ---previous context section
|1773|5610|; | | | | + ---previous context ac block
|1773|5611|; | | + ---1 + --- current ac block
|1773|5612|; | + ---1
|1773|5613|; + ---1
|1773|5614|
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,3360,00,7,00,0,0,0,1774|5615|RDUBR:
|1774|5616| CALL [GET CONTEXT WD] ;Get process context word
000,000,0,04,06,1,46,0,54,0,0,00,00,00,00,00,0,20,1,1,1,03,01,00,4371,00,7,00,0,0,0,1775|5617| [MB]_[MEM-OP], ;Put in right register
|1775|5618| GOTO [TO MEM]
|1775|5619|
|1775|5620|;Here to get a "process context word"
000,000,0,04,06,1,23,0,00,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,3317,00,7,00,0,0,0,1776|5621|GET CONTEXT WD:
|1776|5622| [UPT]_[W1], ;Put UPT page number in LH
|1776|5623| CALL [W1 LLS9]
|1776|5624| J[PCS]_RAMFILE ADR ;Previous context section
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,03,0,20,1,1,0,16,00,00,0576,00,7,01,0,0,0,1777|5625| SWAP [W1]_[W1] ;Put UPT page number in RH
000,000,0,04,10,0,02,2,00,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0000,00,7,07,0,0,0,1778|5626| [W1]_Q RAMFILE_[W1]
000,000,0,07,06,1,02,0,00,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0000,00,7,04,0,0,0,1779|5627| J[PROC REG]_RAMFILE ADR ;Get current AC block number
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,03,0,20,1,1,0,16,00,00,0562,00,7,01,0,0,0,1780|5628| Q.OR.[W1]_[MB]
000,000,0,04,17,1,02,0,44,0,0,00,00,00,00,00,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,1781|5629| RAMFILE_[W1]
000,000,0,04,17,0,02,0,45,0,0,00,00,00,00,00,0,20,1,1,1,12,01,00,0000,00,7,00,0,0,0,1783|5630| [W1].OR.[MB LH]_B, ;Add AC blocks to word
|1783|5631| RETURN
|1783|5632|
|1783|5633|.IF/FT20PAG
|1783|5634|.TOC 3, "WRSPB - Write the SPT base address"
000,000,0,07,06,1,42,0,40,0,0,00,00,00,00,77,0,20,1,1,1,01,01,00,4663,00,7,00,0,0,0,1784|5635|WRSPB: READ [E] ;Get data
000,000,0,04,06,1,46,0,27,0,0,00,00,00,00,00,0,20,1,1,1,13,01,00,1420,00,7,00,0,0,0,1785|5636| [MB]_[SPT], ;Set SPT base adr, no checking
|1785|5637| GOTOP [IFETCH]
|1785|5638|
|1785|5639|.TOC 3, "RDSPB - Read SPT base address"
000,000,0,04,06,1,27,0,54,0,0,00,00,00,00,00,0,20,1,1,1,03,01,00,4371,00,7,00,0,0,0,1786|5640|RDSPB: [SPT]_[MEM-OP], ;Get information he wants
|1786|5641| GOTO [TO MEM]
|1786|5642|
|1786|5643|.TOC 3, "WRCSTM - Write CST Mask register"
000,000,0,07,06,1,42,0,40,0,0,00,00,00,00,77,0,20,1,1,1,01,01,00,4663,00,7,00,0,0,0,1787|5644|WRCSTM:
|1787|5645| READ [E] ;Get data
|1787|5646| J[CSTMASK]_RAMFILE ADR ;Address ramfile
000,000,0,14,14,0,77,0,44,0,0,00,14,00,00,00,0,20,1,1,1,13,01,00,1420,00,7,04,0,0,0,1789|5647| [MB]_RAMFILE, ;Set mask register, no checking
|1789|5648| SET LOCAL,
|1789|5649| GOTOP [IFETCH]
|1789|5650|
|1789|5651|.TOC 3, "RDCSTM - Read CST Mask register"
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,03,0,20,1,1,0,16,00,00,0572,00,7,01,0,0,0,1790|5652|RDCSTM: J[CSTMASK]_RAMFILE ADR ;Address ramfile location
000,000,0,04,10,0,00,0,54,0,0,00,00,00,00,00,0,20,1,1,0,03,01,00,4371,00,7,04,0,0,0,1791|5653| RAMFILE_[MEM-OP], ;Get information he wants
|1791|5654| GOTO [TO MEM]
|1791|5655|
|1791|5656|.TOC 3, "WRPUR - Write process use register (CSTDATA)"
000,000,0,07,06,1,42,0,40,0,0,00,00,00,00,77,0,20,1,1,1,01,01,00,4663,00,7,00,0,0,0,1792|5657|WRPUR: READ [E] ;Get data
|1792|5658| J[CSTDATA]_RAMFILE ADR ;Address ramfile location for data
000,000,0,14,14,0,77,0,44,0,0,00,14,00,00,00,0,20,1,1,1,13,01,00,1420,00,7,04,0,0,0,1794|5659| [MB]_RAMFILE, ;Set data word (age) register
|1794|5660| SET LOCAL,
|1794|5661| GOTOP [IFETCH]
|1794|5662|
|1794|5663|.TOC 3, "RDPUR - Read process use register (CSTDATA)"
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,03,0,20,1,1,0,16,00,00,0573,00,7,01,0,0,0,1795|5664|RDPUR: J[CSTDATA]_RAMFILE ADR ;Address ramfile location for data
000,000,0,04,10,0,00,0,54,0,0,00,00,00,00,00,0,20,1,1,0,03,01,00,4371,00,7,04,0,0,0,1796|5665| RAMFILE_[MEM-OP], ;Get information he wants
|1796|5666| GOTO [TO MEM]
|1796|5667|
|1796|5668|.TOC 3, "WRCSB - Write Core status table base address"
000,000,0,07,06,1,42,0,40,0,0,00,00,00,00,77,0,20,1,1,1,01,01,00,4663,00,7,00,0,0,0,1797|5669|WRCSB: READ [E] ;Get data
|1797|5670| J[CST]_RAMFILE ADR ;Ramfile adr of CST
000,000,0,14,14,0,77,0,44,0,0,00,14,00,00,00,0,20,1,1,1,13,01,00,1420,00,7,04,0,0,0,1799|5671| [MB]_RAMFILE, ;Set CST register, no checking
|1799|5672| SET LOCAL,
|1799|5673| GOTOP [IFETCH]
|1799|5674|
|1799|5675|.TOC 3, "RDCSB - Read Core status table base address"
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,03,0,20,1,1,0,16,00,00,0571,00,7,01,0,0,0,1800|5676|RDCSB: J[CST]_RAMFILE ADR ;Address Ramfile
000,000,0,04,10,0,00,0,54,0,0,00,00,00,00,00,0,20,1,1,0,03,01,00,4371,00,7,04,0,0,0,1801|5677| RAMFILE_[MEM-OP], ;Get information he wants
|1801|5678| GOTO [TO MEM]
|1801|5679|.ENDIF/FT20PAG
|1801|5680|
|1801|5681|.TOC 3, "CLRPT - Clear Page Tables"
000,000,0,14,10,0,00,0,00,0,0,00,24,00,00,00,0,20,1,1,0,01,01,00,3415,00,7,00,0,0,0,1802|5682|CLRPT: SET USER,CALL [CLR PTE] ;Clear user entry first
000,000,0,14,10,0,00,0,00,0,0,00,20,00,00,00,0,20,1,1,0,01,01,00,3415,00,7,00,0,0,0,1803|5683| CLEAR USER,CALL [CLR PTE] ;Now clear exec entry
|1803|5684| GOTOP [IFETCH]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,13,01,00,1420,00,7,00,0,0,0,1804|5685|
000,000,0,14,06,1,42,0,00,0,0,00,00,00,00,77,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,1805|5686|CLR PTE:
|1805|5687| [E]_Y,SECTION SELECT,
|1805|5688| SPEC SEL/PAGE TABLE ENTRY
000,000,0,14,10,1,00,0,00,0,0,00,00,00,00,00,0,20,1,1,1,12,01,00,0000,00,7,04,0,0,0,1806|5689|ZERO RAMFILE:
|1806|5690| ZERO_Y,ALU_RAMFILE, ;Clear entry
|1806|5691| RETURN
|1806|5692|
|1806|5693|.TOC 2, "Timer"
|1806|5694|.TOC 3, "RDTIM - Read time base register"
|1806|5695|
|1806|5696|;TIMER FLAG goes true 27 times/millisecond
|1806|5697|; note: 27.*37.=999. note: 37.=45
|1806|5698|; note: 27.*148.=3996. note: 148.=224
|1806|5699|;Ramfile locations TIME & TIME+1 are 72bit u-second counter
|1806|5700|
000,000,0,04,10,1,00,0,54,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0033,00,7,01,0,0,0,1807|5701|RDTIM: J[27.]_[MEM-OP]
|1807|5702| [MEM-OP]-[TIME]_A ;Number of clock ticks this ms
000,000,0,04,10,1,00,0,13,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,3432,00,7,00,0,0,0,1809|5703| ZERO_[MEM-OP+1],CALL [RDT 4]
|1809|5704| CALL [RDT 4]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,3432,00,7,00,0,0,0,1810|5705| J[TIME BASE+1]_RAMFILE ADR
000,000,1,11,06,1,56,0,54,0,0,00,00,11,00,00,0,20,1,1,1,01,01,00,3432,00,7,00,0,0,0,1812|5706| #2*[MEM-OP]_[MEM-OP],
|1812|5707| CALL [RDT 4]
|1812|5708| RAMFILE_[MEM-OP] ;Get low order part of uptime
000,000,0,04,10,0,00,0,54,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0000,00,7,04,0,0,0,1813|5709| J[TIME BASE]_RAMFILE ADR
000,000,0,04,03,0,56,0,13,0,0,00,00,00,00,00,0,20,1,0,1,16,00,00,0000,00,7,00,0,0,0,1815|5710| [MEM-OP]+[MEM-OP+1]_B,IX_MX
000,000,0,04,10,0,00,0,54,0,0,00,00,00,00,00,0,46,1,1,0,03,03,00,4377,00,7,04,0,0,0,1816|5711| RAMFILE_[MEM-OP],
|1816|5712| IF NOT CT [MOVR] THEN [D TO MEM]
000,000,0,04,06,1,56,0,54,0,1,00,00,00,00,00,0,20,1,1,1,03,01,00,4377,00,7,00,0,0,0,1817|5713| [MEM-OP]+1_[MEM-OP],
|1817|5714| GOTO [D TO MEM]
|1817|5715|
|1817|5716|;Shift MEM-OP left 2 then add to MEM-OP+1
000,000,1,11,03,0,56,0,54,0,0,00,00,11,00,00,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,1818|5717|RDT 4: #4*[MEM-OP]_B ;Shift two left
000,000,0,04,03,0,56,0,13,0,0,00,00,00,00,00,0,20,1,1,1,12,01,00,0000,00,7,00,0,0,0,1819|5718| [MEM-OP]+[MEM-OP+1]_B,
|1819|5719| RETURN
|1819|5720|
|1819|5721|.TOC 3, "WRTIM - Write time base register"
000,000,0,07,06,1,42,0,40,0,0,00,00,00,00,77,0,20,1,1,1,01,01,00,4663,00,7,00,0,0,0,1820|5722|WRTIM: READ [E] ;Get high order bits
|1820|5723| J[TIME BASE]_RAMFILE ADR
000,000,0,14,06,1,46,0,00,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,4660,00,7,04,0,0,0,1822|5724| [MB]_Y,ALU_RAMFILE, ;Write high order bits
|1822|5725| CALL [READ NEXT] ;Get low order bits
|1822|5726| J[TIME BASE+1]_RAMFILE ADR
000,000,0,14,14,0,77,0,44,0,0,00,14,00,00,00,0,20,1,1,1,13,01,00,1420,00,7,04,0,0,0,1824|5727| [MB]_RAMFILE, ;Write low order bits
|1824|5728| SET LOCAL,
|1824|5729| GOTOP [IFETCH]
|1824|5730|
|1824|5731|.TOC 3, "RDINT - Read Interval Timer register"
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,03,0,20,1,1,0,16,00,00,0564,00,7,01,0,0,0,1825|5732|RDINT: J[TIME INTERVAL]_RAMFILE ADR ;Address ramfile location he wants
|1825|5733| RAMFILE_[MEM-OP]
000,000,1,11,03,0,56,0,54,0,0,00,00,11,00,00,0,20,1,1,1,03,01,00,4371,00,7,00,0,0,0,1827|5734| #4*[MEM-OP]_B, ;Display as u-seconds
|1827|5735| GOTO [TO MEM]
|1827|5736|
|1827|5737|.TOC 3, "WRINT - Write Interval Timer register"
000,000,0,07,06,1,42,0,40,0,0,00,00,00,00,77,0,20,1,1,1,01,01,00,4663,00,7,00,0,0,0,1828|5738|WRINT: READ [E]
|1828|5739| J[INTERVAL COUNTER]_RAMFILE ADR ;Start interval counter again
000,000,0,01,06,1,46,0,44,0,1,00,00,01,00,00,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,1830|5740| [MB]+1_F,B SEL/MB,
|1830|5741| LRS F_B,#0_SION #0_QION
000,000,0,01,06,1,46,0,44,0,1,00,00,01,00,00,0,20,1,1,1,16,00,00,0000,00,7,04,0,0,0,1831|5742| [MB]+1_F,B SEL/MB,
|1831|5743| LRS F_B,#0_SION #0_QION,
|1831|5744| ALU_RAMFILE
|1831|5745| J[TIME INTERVAL]_RAMFILE ADR ;Save for restarting counter
000,000,0,14,14,0,77,0,44,0,0,00,14,00,00,00,0,20,1,1,1,13,01,00,1420,00,7,04,0,0,0,1833|5746| [MB]_RAMFILE,
|1833|5747| SET LOCAL,
|1833|5748| GOTOP [IFETCH]
|1833|5749|
|1833|5750|.TOC 2, "Halt Status Block"
|1833|5751|.TOC 3, "WRHSB - Write Halt Status Block Address"
|1833|5752|
000,000,0,07,06,1,42,0,40,0,0,00,00,00,00,77,0,20,1,1,1,01,01,00,4663,00,7,00,0,0,0,1834|5753|WRHSB: READ [E] ;Get new value for HSB
|1834|5754| J[HSB]_RAMFILE ADR ;Address ramfile
000,000,0,14,14,0,77,0,44,0,0,00,14,00,00,00,0,20,1,1,1,13,01,00,1420,00,7,04,0,0,0,1836|5755| [MB]_RAMFILE, ;Put new value in ramfile
|1836|5756| SET LOCAL,
|1836|5757| GOTOP [IFETCH]
|1836|5758|
|1836|5759|.TOC 3, "RDHSB - Read Halt Status Block Address"
|1836|5760|
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,03,0,20,1,1,0,16,00,00,0553,00,7,01,0,0,0,1837|5761|RDHSB: J[HSB]_RAMFILE ADR ;Address of halt status block
000,000,0,04,10,0,00,0,54,0,0,00,00,00,00,00,0,20,1,1,0,03,01,00,4371,00,7,04,0,0,0,1838|5762| RAMFILE_[MEM-OP],
|1838|5763| GOTO [TO MEM]
|1838|5764|
|1838|5765|.TOC 2, "PCI Devices"
|1838|5766|.TOC 3, "RDTTY - Read TTY Conditions"
|1838|5767|
|1838|5768|;Status word in ramfile
|1838|5769|;
|1838|5770|; 0 1 2 3 4 5 6 7 8 91011121314151617181920212223242526272829303132333435
|1838|5771|; | | \ CR / | | \ / | | | | | | | \ RCV /\ /
|1838|5772|; | | | | | | | | | | | | | | | | | + ---PI chn 1
|1838|5773|; | | | | | | | | | | | | | | | | + ---xof flag
|1838|5774|; | | | | | | | | | | | | | | | + ---xof enable
|1838|5775|; | | | | | | | | | | | | | | + ---rcv done
|1838|5776|; | | | | | | | | | | | | | + ---rcv int enable
|1838|5777|; | | | | | | | | | | | | + ---xmt done
|1838|5778|; | | | | | | | | | | | + ---xmt enable
|1838|5779|; | | | | | | | | | | + ---dataset change flag
|1838|5780|; | | | | + ---SR6 | | | | + ---data set change enable
|1838|5781|; | | | + ---SR7 | | | + ---Nxm or mem err on rcv
|1838|5782|; | | + CR7 ... CRO | | + ---Nxm or mem err on xmt
|1838|5783|; | + Half duplex. | + ---flag for TTYRCV BITS
|1838|5784|; + ---DDT mode. + ---protocol
|1838|5785|;
|1838|5786|;Mode word in ramfile
|1838|5787|;0 1 2 3 4 5 6 7 8 91011121314151617181920212223242526272829303132333435
|1838|5788|;\ / \ / \ / \ /
|1838|5789|; | | + ---MR17-MR10 + ---CRC seed
|1838|5790|; | + ---MR25-MR20
|1838|5791|; + ---reserved
|1838|5792|;
|1838|5793|;Syn word in ramfile
|1838|5794|;0 1 2 3 4 5 6 7 8 91011121314151617181920212223242526272829303132333435
|1838|5795|; \ / \ / \ /
|1838|5796|; | | + ---Syn1 char
|1838|5797|; + ---OLE char + ---Syn2 char
|1838|5798|;
|1838|5799|;CRC word in ramfi1e
|1838|5800|;0 1 2 3 4 5 6 7 8 91011121314151617181920212223242526272829303132333435
|1838|5801|; \ / \ /
|1838|5802|; + ---Incoming CRC + ---Outgoing CRC
|1838|5803|;
|1838|5804|;Transmit and receive header words
|1838|5805|; 0 1 2 3 4 5 6 7 8 9101112131415161718192021222324252627282~303132333435
|1838|5806|; \ / \ /
|1838|5807|; + ---reserved + ---phys adr of current header
|1838|5808|;
|1838|5809|;
|1838|5810|;Transmit and receive byte pointer words
|1838|5811|; 0 1 2 3 4 5 6 7 8 91011121314151617181920212223242526272829303132333435
|1838|5812|;\ /\ /\ /
|1838|5813|; | | + ---byte number
|1838|5814|; + ---byte count + ---phys adr of byte word
|1838|5815|
|1838|5816|
|1838|5817|.IF/DEBUGTTY
000,000,0,14,06,1,42,0,00,0,0,00,00,00,00,03,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,1839|5818|RDTTY: [E]_Y, Y_TTY ADR ;Address register
000,000,0,04,10,0,00,0,54,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0000,00,7,03,0,0,0,1840|5819| PCI_ALU,Y_[MEM-OP] ;Read register
000,000,0,04,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0000,00,7,03,0,0,0,1841|5820| PCI_ALU,Y_[W1] ;Get 2nd half
000,000,0,04,10,0,02,2,55,0,0,00,00,00,00,00,0,20,1,1,0,03,01,00,4342,00,7,07,0,0,0,1842|5821| SWAP [W1]_[MEM-OP LH],
|1842|5822| GOTO [TO AC.0]
|1842|5823|.ENDIF/DEBUGTTY
|1842|5824|
|1842|5825|
|1842|5826|;Here to reset a PCI line
|1842|5827|
|1842|5828|.IF/FTTTYR
000,000,0,14,14,0,76,0,24,0,0,00,00,00,00,00,0,20,1,0,1,16,00,00,0000,00,7,00,0,0,0,1843|5829|RESET PCI:
|1843|5830| [K -1.0]&[W6]_Y,IX_MX ;Check for CTY
|1843|5831| J[0200]_[W5] ;Transmit done
000,000,0,14,06,1,26,0,00,0,0,00,00,00,00,03,0,44,1,1,1,03,03,00,3471,00,7,00,0,0,0,1845|5832| [W6]_Y,Y_RAMFILE ADR, ;Address status word
|1845|5833| IF NOT CT [MZ] THEN [RPC11]
|1845|5834| J[04200]_[W1] ;For RTS & DTR
000,000,0,04,10,1,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,4200,00,7,01,0,0,0,1846|5835| #4*[W1]_B
000,000,1,11,03,0,02,0,00,0,0,00,00,11,00,00,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,1847|5836| SWAP [W1]_[W5 LH] ;Put in LH
000,000,0,14,06,1,22,0,00,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,3524,00,7,04,0,0,0,1849|5837|RPC11: [W5]_Y,ALU_RAMFILE, ;Update status word
|1849|5838| CALL [SET PCI CR]
000,000,0,06,06,1,26,0,00,0,1,00,00,00,00,03,0,20,1,1,1,14,00,00,0005,00,7,00,0,0,0,1850|5839| [W6]+1_F,F_Q_Y,Y_RAMFILE ADR, ;Address of Mode word
|1850|5840| J[5]_CTR
|1850|5841| ZERO_[W1 RH] ;Clear CRC seed
000,000,0,04,10,0,00,0,01,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,5020,00,7,04,0,0,0,1852|5842| RAMFILE_[W1 LH], ;Get mode word
|1852|5843| CALL [W1_RAMFILE]
000,000,0,14,06,1,00,0,00,0,1,00,00,00,00,03,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,1853|5844|RPC12: Q+1_F,F_Y,Y_RAMFILE ADR ;Address next ramfile word
000,000,0,14,10,1,00,0,00,0,0,00,00,00,00,00,0,20,1,1,1,11,00,00,3475,00,7,04,0,0,0,1854|5845| ZERO_Y,ALU_RAMFILE, ;Zero next location
|1854|5846| LOOP [RPC12]
|1854|5847| ;GOTO [SET USART MODE]
|1854|5848| RETURN
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,12,01,00,0000,00,7,00,0,0,0,1855|5849|.ENDIF/FTTTYR
|1855|5850|
|1855|5851|;Here to set mode register in USART line
|1855|5852|; Call with [W6]-linenumber,,adr of ramfile line block
|1855|5853|
000,000,0,04,10,1,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0030,00,7,01,0,0,0,1856|5854|SET PCI MODE:
|1856|5855| J[A1!A0]_[W1] ;Address bits for CR
000,000,0,04,10,1,00,0,04,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,3715,00,7,00,0,0,0,1857|5856| ZERO_[W2],CALL [WR PCI] ;Clear command register
000,000,0,14,06,1,26,0,00,0,1,00,00,00,00,03,0,20,1,1,1,01,01,00,1216,00,7,00,0,0,0,1858|5857| [W6]+1_Y,Y_RAMFILE ADR, ;Address mode word
|1858|5858| CALL [RAMFILE_W1] ;Get mode word from ramfile
|1858|5859| SWAP [W1]_[W1] ;Put mode words in RH
000,000,0,04,10,0,02,2,00,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0000,00,7,07,0,0,0,1859|5860| J[A1]_[W2] ;Makes A1 for mode register
000,000,0,04,10,0,26,2,10,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,3516,00,7,07,0,0,0,1861|5861| SWAP [W6]_[W3], ;Get line number
|1861|5862| CALL [SUM 40] ; write MR1 & MR2
000,000,0,14,06,1,02,0,00,0,0,00,00,00,00,00,0,20,1,1,1,16,00,00,0000,00,7,05,0,0,0,1862|5863| [W1]_Y,ALU_MR2 ;Write M8626 copy of MR2
|1862|5864| J[A0]_[W2]; ;Set A0 for SYN1/SYN2/DLE
000,000,0,04,10,1,00,0,04,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0010,00,7,01,0,0,0,1863|5865| J[LNXSYN]_[W1] ;Offset for syn word
000,000,0,14,03,0,26,0,00,0,0,00,00,00,00,03,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,1865|5866| [W6]+[W1]_Y,Y_RAMFILE ADR ;Address ramfile word
000,000,0,04,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,3516,00,7,04,0,0,0,1866|5867| RAMFILE_[W1], ;Get synchs and OLE chars
|1866|5868| CALL [SUM 40] ;Write SYN1, SYN2 registers
|1866|5869| CALL [SUM 1] ;Write DLE register
000,000,0,14,06,1,26,0,00,0,0,00,00,00,00,03,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,1868|5870| [W6]_Y,Y_RAMFILE ADR ;Address ramfile copy of CR
000,000,0,04,10,0,00,0,20,0,0,00,00,00,00,00,0,20,1,1,0,03,01,00,3524,00,7,04,0,0,0,1869|5871| RAMFILE_[W5], ;Set CR according to ramfile
|1869|5872| GOTO [SET PCI CR]
|1869|5873|
|1869|5874|;Here to set 2651 mode or syn registers
|1869|5875|; Call with MR2, MR1 as low order 8-bit bytes in W1,
|1869|5876|; and with A1 or AO in W2 and line number in W3
|1869|5877|
000,000,0,14,03,0,06,0,10,0,0,00,00,00,00,03,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,1870|5878|SUM 40: [W2]+[W3]_Y,Y_TTY ADR ;Address line and mode registers
000,000,0,14,06,1,02,0,00,0,0,00,00,00,00,00,0,20,1,1,1,16,00,00,0000,00,7,03,0,0,0,1871|5879| [W1]_Y,ALU_PCI ;Write MR1/SYNl
000,000,1,11,03,0,02,0,00,0,0,00,00,11,00,00,0,20,1,1,1,14,00,00,0003,00,7,00,0,0,0,1872|5880|SUM 1: #4*[W1]_B, ; Shift 1eft 2 at a time
|1872|5881| J[3]_CTR
000,000,1,11,03,0,02,0,00,0,0,00,00,11,00,00,0,20,1,1,1,11,00,00,3521,00,7,00,0,0,0,1873|5882|SUM 2: #4*[W1]_B, ;Shift left 2 at a time
|1873|5883| LOOP [SUM 2] ; 10 all together
|1873|5884| SWAP [W1]_[W1]
000,000,0,14,06,1,02,0,00,0,0,00,00,00,00,00,0,20,1,1,1,12,01,00,0000,00,7,03,0,0,0,1875|5885| [W1]_Y,ALU_PCI, ;Write MR2/SYN2
|1875|5886| RETURN
|1875|5887|
|1875|5888|;Here to set PCI CR
000,000,1,11,06,1,22,0,04,0,0,00,00,51,00,00,0,20,1,1,1,14,00,00,0010,00,7,00,0,0,0,1876|5889|SET PCI CR:
|1876|5890|; SWAP [W5]_[W2],J[4.]_CTR ;Copy CR
|1876|5891|;SPCR2: #4*[W2]_B,LOOP [SPCR2] ;Shift left 10 places
|1876|5892|; SWAP [W2]_[W2] ;Right justify CR
|1876|5893| ROL [W5]_[W2],J[8.]_CTR ;Copy CR from status word
000,000,1,11,06,1,06,0,04,0,0,00,00,51,00,00,0,20,1,1,1,11,00,00,3525,00,7,00,0,0,0,1877|5894|SPCR2: ROL [W2]_[W2],LOOP [SPCR2] ;Put CR in W2 rh
000,000,0,14,14,0,76,0,24,0,0,00,00,00,00,00,0,20,1,0,1,16,00,00,0000,00,7,00,0,0,0,1878|5895| [K -1.0]&[W6]_Y,IX_MX ;Check for CTY line
|1878|5896| J[A1!A0]_[W1] ;Address bits for CR
000,000,0,04,04,0,26,2,00,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0000,00,7,07,0,0,0,1880|5897| SWAP [W6]_[W1],F_Q,B[W1]_F ;Get line number
000,000,0,14,03,1,02,0,00,0,0,00,00,00,00,03,0,44,1,1,1,03,02,00,3533,00,7,00,0,0,0,1881|5898| Q+[W1]_Y,Y_TTY ADR, ;Address command register
|1881|5899| IF CT [MZ] THEN [SPCR7]
000,000,0,14,06,1,06,0,00,0,0,00,00,00,00,00,0,20,1,1,1,12,01,00,0000,00,7,03,0,0,0,1882|5900| [W2]_Y,ALU_PCI, ;Write CR
|1882|5901| RETURN
|1882|5902|;Here when writing CR for CTY
000,000,0,04,10,1,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0004,00,7,01,0,0,0,1883|5903|SPCR7: J[4]_[W1] ;Bits we always leave on in CTY
000,000,0,14,17,0,02,0,04,0,0,00,00,00,00,00,0,20,1,1,1,12,01,00,0000,00,7,03,0,0,0,1884|5904| [W1].OR.[W2]_Y,ALU_PCI, ;Write CR
|1884|5905| RETURN
|1884|5906|
|1884|5907|;Here for a transmitter interrupt for a PCI line
|1884|5908|; call with adr of line status register in W6. and status in W5
000,000,0,14,14,0,76,0,24,0,0,00,00,00,00,00,0,64,1,1,1,03,03,00,3555,00,7,00,0,0,0,1885|5909|INT XMT:
|1885|5910| [K -1.0]&[W6]_Y, ;See if this is the cty
|1885|5911| IF NOT CT [IZ] THEN [XINT10] ; Branch if not cty
|1885|5912| J[CMDFLG]_RAMFILE ADR ;Address console flags
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,03,0,20,1,1,0,16,00,00,0300,00,7,01,0,0,0,1886|5913| RAMFILE_[W1]
000,000,0,04,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0000,00,7,04,0,0,0,1887|5914| J[CMRTKR]_RAMFILE ADR ;Get taker for response buffer
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,03,0,20,1,1,0,16,00,00,0303,00,7,01,0,0,0,1888|5915|.IF/FTCRAM
|1888|5916| RAMFILE_[W2] ;If no data stop transmitter
|1888|5917| [W2]_[W2], ;Let latches go
|1888|5918| IF CT [IZ] THEN [XINT05]
|1888|5919|.ENDIF/FTCRAM
|1888|5920|.IFNOT/FTCRAM
000,000,0,04,10,0,00,0,04,0,0,00,00,00,00,00,0,64,1,1,0,03,02,00,3554,00,7,04,0,0,0,1889|5921| RAMFILE_[W2], ;If no data stop transmitter
|1889|5922| IF CT [IZ] THEN [XINT05]
|1889|5923|.ENDIF/FTCRAM
|1889|5924| J[F.S]_[W2] ;Xoff flag
000,000,0,14,14,0,02,0,04,0,0,00,00,00,00,00,0,64,1,1,1,03,03,00,3626,00,7,00,0,0,0,1891|5925| [W1]&[W2]_Y, ;If Xoff stop typing
|1891|5926| IF NOT CT [IZ] THEN [XINT95]
|1891|5927| CALL [CMB NXT] ;Get next byte
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,1005,00,7,00,0,0,0,1892|5928| CALL [XMT CHR] ;Type it
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,3652,00,7,00,0,0,0,1893|5929| J[CMRPTR]_RAMFILE ADR ;Get response putter
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,03,0,20,1,1,0,16,00,00,0302,00,7,01,0,0,0,1894|5930| RAMFILE_[W1]
000,000,0,04,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0000,00,7,04,0,0,0,1895|5931| J[CMRTKR]_RAMFILE ADR ;Address response taker
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,03,0,20,1,1,0,16,00,00,0303,00,7,01,0,0,0,1896|5932| RAMFILE_[W2]
000,000,0,14,13,0,02,0,04,0,0,00,00,00,00,00,0,64,1,1,1,01,02,00,0774,00,7,00,0,0,0,1898|5933| [W1].XOR.[W2]_Y, ;Check for buffer empty
|1898|5934| IF CT [IZ] CALL [CMRBUF FLUSH]
|1898|5935| GOTO [CMDC X] ;Process waiting commands if any
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,03,01,00,0656,00,7,00,0,0,0,1899|5936|
000,000,0,14,14,0,47,0,00,0,0,00,00,00,00,00,0,64,1,1,1,03,02,00,3626,00,7,00,0,0,0,1900|5937|XINT05: [BIT4]&[W1]_Y, ; (f.USR) Exec mode-shut off xmtr
|1900|5938| IF CT [IZ] THEN [XINT95]
|1900|5939|
|1900|5940|;Here because line is in user mode
000,000,0,04,10,1,00,0,14,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0004,00,7,01,0,0,0,1901|5941|XINT10:
|1901|5942| J[LNXXHD]_[W4] ;Offset for header
|1901|5943|.IF/FTDDTM
000,000,0,14,06,1,22,0,00,0,0,00,00,00,00,00,0,76,1,1,1,03,03,00,3564,00,7,00,0,0,0,1902|5944| [W5]_Y,
|1902|5945| IF NOT CT [IN] THEN [XINT30] ;Check for DDT mode
|1902|5946|
|1902|5947|;Here because line is in DDT mode
000,000,0,14,03,0,26,0,14,0,1,00,00,00,00,03,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,1903|5948| [W6]+[W4]+1_Y,Y_RAMFILE ADR ;Address ramfile word
|1903|5949|.IF/FTCRAM
|1903|5950| RAMFILE_[W1] ;Get next char to type
|1903|5951| [W1]_[W1], ;Let latches go
|1903|5952| IF CT [IZ] THEN [XINT95] ; If nothing shut down
|1903|5953|.ENDIF/FTCRAM
|1903|5954|.IFNOT/FTCRAM
000,000,0,04,10,0,00,0,00,0,0,00,00,00,00,00,0,64,1,1,0,03,02,00,3626,00,7,04,0,0,0,1904|5955| RAMFILE_[W1], ;Get next char to type
|1904|5956| IF CT [IZ] THEN [XINT95] ; If nothing shut down
|1904|5957|.ENDIF/FTCRAM
000,000,0,14,10,1,00,0,00,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,3652,00,7,04,0,0,0,1905|5958| ZERO_Y,ALU_RAMFILE, ;Have sent char now
|1905|5959| CALL [XMT CHR] ; Type char
|1905|5960| CALL [SET XDN] ;Set done flag in status wcrd
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,3670,00,7,00,0,0,0,1906|5961| GOTOP [PCI INT CLR] ;Here because line is not in DDT mode
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,13,01,00,3613,00,7,00,0,0,0,1907|5962|.ENDIF/FTDDTM
|1907|5963|
000,000,0,04,10,1,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0400,00,7,01,0,0,0,1908|5964|XINT30:
|1908|5965| J[0400]_[W1] ;Will become CR0
|1908|5966| SWAP [W1]_[W1] ;Makes CRO
000,000,0,14,14,0,22,0,00,0,0,00,00,00,00,00,0,64,1,1,1,03,02,00,3626,00,7,00,0,0,0,1910|5967| [W5]&[W1]_Y,
|1910|5968| IF CT [IZ] THEN [XINT95]
|1910|5969|;Here to get next byte from buffer
|1910|5970| J[XMT TTY PF]_[W1]
000,000,0,04,10,1,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,3622,00,7,01,0,0,0,1911|5971| CALL [SET PF RCOVR]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,5017,00,7,00,0,0,0,1912|5972| J[#24B MASK]_RAMFILE ADR
000,000,0,04,10,0,00,0,04,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,3630,00,7,04,0,0,0,1914|5973| RAMFILE_[W2], ;Get 24 bit Mask
|1914|5974| CALL [NXT RX WRD]
000,000,1,11,06,1,33,0,00,0,0,00,00,51,00,00,0,20,1,0,1,16,00,00,0000,00,7,00,0,0,0,1915|5975| ROL [PMA]_[W1],IX_MX ; byte #ab, a_MN
000,000,1,11,06,1,02,0,00,0,0,00,00,51,00,00,0,56,1,0,1,03,03,00,3577,00,7,00,0,0,0,1916|5976| ROL [W1]_[W1], ;Byte #ab, B_MN
|1916|5977| IF NOT CT [MN IX_MX] THEN [XINT70]
|1916|5978| IF NOT CT [MN] THEN [XINT72] ;Check for byte 2 or 3
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,56,1,1,0,03,03,00,3600,00,7,00,0,0,0,1917|5979| GOTO [XINT73]
000,000,0,04,10,0,46,2,44,0,0,00,00,00,00,00,0,56,1,1,0,03,02,00,3603,00,7,07,0,0,0,1919|5980|XINT70: SWAP [MB]_[MB], ;Enter here for byte 0
|1919|5981| IF CT [MN] THEN [XINT73] ;Check for byte 0 or 1
000,000,1,11,06,1,46,0,44,0,0,00,00,11,00,00,0,20,1,1,1,14,00,00,0003,00,7,00,0,0,0,1920|5982|XINT72: #2*[MB]_[MB],J[3]_CTR ;Enter here for byte 2
000,000,1,11,03,0,46,0,44,0,0,00,00,11,00,00,0,20,1,1,1,11,00,00,3601,00,7,00,0,0,0,1921|5983|XINT74: #4*[MB]_B,LOOP [XINT74]
|1921|5984| SWAP [MB]_[MB] ;Enter here for byte 1
000,000,0,04,06,1,46,0,00,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,3652,00,7,00,0,0,0,1923|5985|XINT73: [MB]_[W1],CALL [XMT CHR] ;Enter here for byte 3
|1923|5986| IF NOT CT [UZ] THENP [PCI INT CLR] ;Check for buffer exhausted
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,3670,00,7,00,0,0,0,1925|5987|XINT93: CALL [SET XDN] ;We are done with buffer
|1925|5988| J[LNXXHD]_[W4] ;Got clobbered so restore
000,000,0,14,03,0,26,0,14,0,0,00,00,00,00,03,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,1927|5989| [W6]+[W4]_Y,Y_RAMFILE ADR ; Addr RF copy of current hdr addr
000,000,0,04,10,0,00,0,33,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,4105,00,7,04,0,0,0,1928|5990| RAMFILE_[PMA], ;Get adr of header
|1928|5991| CALL [CHNG2] ; write pointer back
|1928|5992| CALL [GET NXT RX HDR] ;Get header for next buffer
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,3636,00,7,00,0,0,0,1929|5993| IF CT [UOVR] CALL [CLR XGO] ;We have now stopped
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,03,0,20,1,1,0,16,00,00,0520,00,7,01,0,0,0,1931|5994|PCI INT CLR:
|1931|5995|.IF/DEBUG3
|1931|5996| J[POOP FLAG]_RAMFILE ADR
000,000,0,14,10,1,00,0,00,0,0,00,00,00,00,00,0,20,1,1,1,16,00,00,0000,00,7,04,0,0,0,1932|5997| ZERO_Y,ALU_RAMFILE
|1932|5998|.ENDIF/DEBUG3
000,000,0,04,10,1,00,0,00,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,5017,00,7,00,0,0,0,1933|5999| ZERO_[W1],CALL [SET PF RCOVR] ; FIXME:
000,000,0,04,06,1,62,0,43,0,0,00,00,00,46,00,0,20,1,1,1,13,01,00,0342,00,7,00,0,0,0,1934|6000| [PXCT]_[PI REG], Y_2914 STATUS, ; Restore previous level
|1934|6001| GOTOP [CONSOLE] ;This is not reatly an int
|1934|6002|
|1934|6003|;Here because memory error reading transmit buffer
|1934|6004|
000,000,0,01,06,1,57,0,00,0,0,00,00,51,00,00,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,1935|6005|XINT91: ROR [BIT17]_[W1] ;Need to make a bit 19
|1935|6006| ROR [W1]_[W1] ;Make a bit 19
000,000,0,04,17,0,02,0,20,0,0,00,00,00,00,00,0,20,1,1,1,03,01,00,3605,00,7,00,0,0,0,1937|6007| [W1].OR.[W5]_B, ;5et xmtr err bit
|1937|6008| GOTO [XINT93] ; and stop transMitter
|1937|6009|
|1937|6010|;Here when page fail (=nxm or mem fault)
000,000,0,01,06,1,57,0,00,0,0,00,00,51,00,00,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,1938|6011|XMT TTY PF:
|1938|6012| ROR [BIT17]_[W1] ;Make a bit 18
|1938|6013| ROR [W1]_[W1] ;Make a bit 19
000,000,0,04,17,0,02,0,20,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,3670,00,7,00,0,0,0,1940|6014| [W1].OR.[W5]_B, ;Set xmt mem err flag
|1940|6015| CALL [SET XDN] ; And flag transMitter stopped
|1940|6016| CALL [CLR XGO] ;Clear CRO in status word
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,3657,00,7,00,0,0,0,1941|6017|
|1941|6018|;Here to stop the transmitter
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,3677,00,7,00,0,0,0,1942|6019|XINT95: CALL [CLR PCI TXEN] ;Disable transmitter
|1942|6020| GOTOP [PCI INT CLR]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,13,01,00,3613,00,7,00,0,0,0,1943|6021|
|1943|6022|;Here to get next word fra. transmit or receive buffer
|1943|6023|; Call with LNXXHD or LNXRHD in W4, 24b mask in W2
|1943|6024|; Returns with word :n ~
|1943|6025|; Returns UZ if count expires
|1943|6026|
000,000,0,14,03,0,26,0,14,0,1,00,00,00,00,03,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,1944|6027|NXT RX WRD:
|1944|6028| [W6]+[W4]+1_F,F_Y,Y_RAMFILE ADR ;Address byte pointer
|1944|6029| RAMFILE_[PMA] ;Get byte header
000,000,0,04,01,0,06,0,33,0,1,00,00,00,00,00,0,20,1,1,1,16,00,00,0000,00,7,04,0,0,0,1946|6030| [PMA]-[W2]_A, ; Increment pointer, decrement count
|1946|6031| ALU_RAMFILE ; save updated byte pointer
000,000,0,14,11,0,06,0,33,0,0,00,00,00,00,00,0,20,0,1,1,16,00,00,0000,00,7,00,0,0,0,1947|6032| [W2]BAR&[PMA]_Y,IX_UX ;Set UZ if count has expired
|1947|6033| ROR [PMA]_[PMA] ;Address of word which haS byte
000,000,0,01,06,1,33,0,33,0,0,00,00,51,00,00,0,20,1,1,1,03,01,00,4572,00,7,00,0,0,0,1949|6034| ROR [PMA]_[PMA], ;Divide by 2
|1949|6035| GOTO [UNMAPPED READ 0] ; get word
|1949|6036|
|1949|6037|
|1949|6038|;Here to get next receive or transmit header
|1949|6039|; CALL with LNXXHD or LNXRHD in W1
000,000,0,14,03,0,26,0,14,0,0,00,00,00,00,03,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,1950|6040|GET NXT RX HDR:
|1950|6041| [W6]+[W4]_Y,Y_RAMFILE ADR ;Address ramfile
|1950|6042|.IF/FTTTYSB
000,000,0,04,10,0,00,0,33,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,4572,00,7,04,0,0,0,1951|6043| RAMFILE_[PMA], ;Get address of header
|1951|6044| CALL [UNMAPPED READ 0] ;Get header status
000,000,0,14,14,0,57,0,44,0,0,00,00,00,00,00,0,64,1,1,1,03,03,00,1544,00,7,00,0,0,0,1952|6045| [BIT17]&[MB]_Y, ;Check for stop on buffer
|1952|6046| IF NOT CT [IZ] THEN [SET UOVR]
|1952|6047|.ENDIF/FTTTYSB
|1952|6048|.IFNOT/FTTTYSB
|1952|6049| RAMFILE_[PMA] ;Get adr of header
|1952|6050|.ENDIF/FTTTYSB
000,200,0,14,10,0,00,0,33,0,1,00,00,05,00,00,0,20,1,1,1,01,01,00,4573,00,1,02,0,0,0,1953|6051| [PMA]+2_B,MEM START READ, ;ftakes adr of next header adr
|1953|6052| CALL [UNMAPPED READ]
000,000,0,14,03,0,26,0,14,0,0,00,00,00,00,03,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,1954|6053| [W6]+[W4]_Y,Y_RAMFILE ADR ;Address LNXXHD or LNXRHD
000,000,0,04,06,1,46,0,33,0,0,00,00,00,00,00,0,64,1,1,1,03,02,00,1544,00,7,04,0,0,0,1955|6054| [MB]_[PMA],ALU_RAMFILE, ;Save adr of new header
|1955|6055| IF CT [IZ] THEN [SET UOVR]
000,000,0,04,06,1,33,0,33,0,1,00,00,05,00,00,0,20,1,1,1,01,01,00,4573,00,1,02,0,0,0,1956|6056|GET RX HDR:
|1956|6057| [PMA]+1_[PMA],MEM START READ, ;Get byte pointer for new header
|1956|6058| CALL [UNMAPPED READ]
|1956|6059| J[#24B MASK]_RAMFILE ADR
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,03,0,20,1,1,0,16,00,00,0030,00,7,01,0,0,0,1957|6060| RAMFILE_[W1] ;Get mask for count
000,000,0,14,11,0,02,0,44,0,0,00,00,00,00,00,0,64,1,1,1,03,02,00,1544,00,7,00,0,0,0,1959|6061| [W1]BAR&[MB]_F,F_Y, ;Check count field
|1959|6062| IF CT [IZ] THEN [SET UOVR]
000,000,0,14,03,0,26,0,14,0,1,00,00,00,00,03,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,1960|6063| [W6]+[W4]+1_F,F_Y,Y_RAMFILE ADR
000,000,0,14,14,0,77,0,44,0,0,00,00,00,00,00,0,16,0,1,1,12,01,00,0000,00,7,04,0,0,0,1961|6064| [MB]_RAMFILE,#0_UOVR, ;Save new pointer
|1961|6065| RETURN
|1961|6066|
|1961|6067|;Here to transmit a char on a 2651 line
|1961|6068|; Call with [W6]-line number,,adr of ramfile line block, char in W1
|1961|6069|
000,000,0,04,10,0,26,2,04,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0000,00,7,07,0,0,0,1962|6070|XMT CHR:
|1962|6071| SWAP [W6]_[W2] ;Put line number in RH
000,000,0,14,06,1,06,0,00,0,0,00,00,00,00,03,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,1963|6072| [W2]_Y,Y_TTY ADR ;Address line and mode registers
000,000,0,14,06,1,02,0,00,0,0,00,00,00,00,00,0,20,1,1,1,12,01,00,0000,00,7,03,0,0,0,1964|6073| [W1]_Y,ALU_PCI, ;Transmit character
|1964|6074| RETURN
|1964|6075|
|1964|6076|;Here to clear LS.RGO in LNXSWD
000,000,0,04,10,1,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,2000,00,7,01,0,0,0,1965|6077|CLR RGO:
|1965|6078| J[02000]_[W1] ;Bit to clear
000,000,0,14,06,1,26,0,00,0,0,00,00,00,00,03,0,20,1,1,1,03,01,00,3661,00,7,00,0,0,0,1966|6079| [W6]_Y,Y_RAMFILE ADR, ;Address the status word
|1966|6080| GOTO [CLR RXGO]
|1966|6081|
|1966|6082|;Here to stop transmitter
000,000,0,14,06,1,26,0,00,0,0,00,00,00,00,03,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,1967|6083|CLR XGO:
|1967|6084| [W6]_Y,Y_RAMFILE ADR ;Address the status word
|1967|6085| J[0400]_[W1] ;Will become CR0
000,000,0,04,10,0,02,2,00,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0000,00,7,07,0,0,0,1969|6086|CLR RXGO:
|1969|6087| SWAP [W1]_[W1] ;Make CRO
000,000,0,04,11,0,02,0,20,0,0,00,00,00,00,00,0,20,1,1,1,12,01,00,0000,00,7,04,0,0,0,1970|6088| [W1]BAR&[W5]_B,ALU_RAMFILE, ;Write updated status
|1970|6089| RETURN
|1970|6090|
|1970|6091|;Here to set LS.RDN in LNXSWD
000,000,0,04,10,1,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0200,00,7,01,0,0,0,1971|6092|SET RDN:
|1971|6093| J[LS.RDN]_[W1] ;Bit to set
000,000,0,14,06,1,26,0,00,0,0,00,00,00,00,03,0,20,1,1,1,03,01,00,3672,00,7,00,0,0,0,1972|6094| [W6]_Y,Y_RAMFILE ADR,
|1972|6095| GOTO [W1!W5_RAMFILE]
|1972|6096|
|1972|6097|.IF/FTTTYF
|1972|6098|;Here to clear LS.RDN in LNXSWD
000,000,0,04,10,1,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0200,00,7,01,0,0,0,1973|6099|CLR RDN:
|1973|6100| J[LS.RDN]_[W1] ;Bit to set
000,000,0,14,06,1,26,0,00,0,0,00,00,00,00,03,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,1974|6101| [W6]_Y,Y_RAMFILE ADR
000,000,0,04,11,0,02,0,20,0,0,00,00,00,00,00,0,20,1,1,1,03,01,00,3225,00,7,04,0,0,0,1975|6102|W1BAR&W5_RAMFILE:
|1975|6103| [W1]BAR&[W5]_B,ALU_RAMFILE, ;Write updated status
|1975|6104| GOTO [SET PROC REG]
|1975|6105|.ENDIF/FTTTYF
|1975|6106|
|1975|6107|;Here to set LS.XDN in LNXSWD
000,000,0,04,10,1,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,2000,00,7,01,0,0,0,1976|6108|SET XDN:
|1976|6109| J[LS.XDN]_[W1] ;Bit to set
000,000,0,14,06,1,26,0,00,0,0,00,00,00,00,03,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,1977|6110| [W6]_Y,Y_RAMFILE ADR
000,000,0,04,17,0,02,0,20,0,0,00,00,00,00,00,0,20,1,1,1,03,01,00,3225,00,7,04,0,0,0,1978|6111|W1!W5_RAMFILE:
|1978|6112| [W1].OR.[W5]_B,ALU_RAMFILE, ;Write updated status
|1978|6113| GOTO [SET PROC REG] ; Adjust int requests
|1978|6114|
|1978|6115|.IF/FTTTYF
|1978|6116|;Here to clear LS.XDN in LNXSWD
000,000,0,04,10,1,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,2000,00,7,01,0,0,0,1979|6117|CLR XDN:
|1979|6118| J[LS.XDN]_[W1] ;Bit to set
000,000,0,14,06,1,26,0,00,0,0,00,00,00,00,03,0,20,1,1,1,03,01,00,3667,00,7,00,0,0,0,1980|6119| [W6]_Y,Y_RAMFILE ADR,
|1980|6120| GOTO [W1BAR&W5_RAMFILE]
|1980|6121|.ENDIF/FTTTYF
|1980|6122|
|1980|6123|;Here to set TXEN = transmit enable in a PCI
|1980|6124|; call with [W6] = line #,,x
|1980|6125|; clobbers W1, W2
000,000,0,04,06,1,57,0,04,0,1,00,00,00,00,00,0,20,1,1,1,01,01,00,3711,00,7,00,0,0,0,1981|6126|SET PCI TXEN:
|1981|6127| [BIT17]+1_[W2], ;Get bit for TXEN
|1981|6128| CALL [RD PCI CR]
000,000,0,14,17,0,02,0,04,0,0,00,00,00,00,00,0,20,1,1,1,12,01,00,0000,00,7,03,0,0,0,1982|6129| [W1].OR.[W2]_Y,ALU_PCI, ;Set bit
|1982|6130| RETURN
|1982|6131|
|1982|6132|;Here to clear TXEN = transmit enable in a PCI
|1982|6133|; call with [W6] = line #,,x
|1982|6134|; clobbers W1 & W2
000,000,0,04,06,1,57,0,04,0,1,00,00,00,00,00,0,20,1,1,1,01,01,00,3711,00,7,00,0,0,0,1983|6135|CLR PCI TXEN:
|1983|6136| [BIT17]+1_[W2], ;Get bit for TXEN
|1983|6137| CALL [RD PCI CR]
000,000,0,14,11,0,06,0,00,0,0,00,00,00,00,00,0,20,1,1,1,12,01,00,0000,00,7,03,0,0,0,1984|6138| [W2]BAR&[W1]_Y,ALU_PCI, ;Clear bit
|1984|6139| RETURN
|1984|6140|
|1984|6141|;Here to set RXEN = receive enable in a PCI
|1984|6142|; call with [W6] = line #,,x
|1984|6143|; clobbers W1 & W2
000,000,0,04,10,1,00,0,04,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0004,00,7,01,0,0,0,1985|6144|SET PCI RXEN:
|1985|6145| J[RXEN]_[W2] ;Get bit for RXEN
|1985|6146| CALL [RD PCI CR]
000,000,0,14,17,0,02,0,04,0,0,00,00,00,00,00,0,20,1,1,1,12,01,00,0000,00,7,03,0,0,0,1987|6147| [W1].OR.[W2]_Y,ALU_PCI, ;Set bit
|1987|6148| RETURN
|1987|6149|
|1987|6150|;Here to clear RXEN = receive enable in a PCI
|1987|6151|; call with [W6] = line #,,x
|1987|6152|; clobbers W1 & W2
|1987|6153|
000,000,0,04,10,1,00,0,04,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0004,00,7,01,0,0,0,1988|6154|CLR PCI RXEN:
|1988|6155| J[RXEN]_[W2] ;Get bit for RXEN
|1988|6156| CALL [RD PCI CR]
000,000,0,14,11,0,06,0,00,0,0,00,00,00,00,00,0,20,1,1,1,12,01,00,0000,00,7,03,0,0,0,1990|6157| [W2]BAR&[W1]_Y,ALU_PCI, ;Clear bit
|1990|6158| RETURN
|1990|6159|
|1990|6160|;Here to read PCI SR register
000,000,0,04,10,1,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0010,00,7,01,0,0,0,1991|6161|RD PCI SR:
|1991|6162| J[A0]_[W1] ;Address of status register
000,000,0,07,04,0,26,2,00,0,0,00,00,00,00,00,0,20,1,1,0,03,01,00,3713,00,7,07,0,0,0,1992|6163| SWAP [W6]_[W1] F_Q,B[W1]_F, ;Get line number
|1992|6164| GOTO [RDPCI2]
|1992|6165|
|1992|6166|;Here to read PCI CR register
000,000,0,04,10,1,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0030,00,7,01,0,0,0,1993|6167|RD PCI CR:
|1993|6168| J[A1!A0]_[W1] ;Bits to address command register
|1993|6169| ;GOTO [RD PCI]
|1993|6170|
|1993|6171|;Here to read a PCI register
000,000,0,07,04,0,26,2,00,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0000,00,7,07,0,0,0,1994|6172|RD PCI: SWAP [W6]_[W1] F_Q,B[W1]_F ;Get line number
000,000,0,14,03,1,02,0,00,0,0,00,00,00,00,03,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,1995|6173|RDPCI2: Q+[W1]_Y,Y_TTY ADR ;Address register
000,000,0,04,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,12,01,00,0000,00,7,03,0,0,0,1996|6174| PCI_ALU,Y_[W1], ;Read register
|1996|6175| RETURN
|1996|6176|
|1996|6177|;Here to write a PCI register
|1996|6178|; Call with A[1:0] in W1, and data in W2
000,000,0,07,04,0,26,2,00,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0000,00,7,07,0,0,0,1997|6179|WR PCI: SWAP [W6]_[W1] F_Q,B[W1]_F ;Get line number
000,000,0,14,03,1,02,0,00,0,0,00,00,00,00,03,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,1998|6180| Q+[W1]_Y,Y_TTY ADR ;Address register
000,000,0,14,06,1,06,0,00,0,0,00,00,00,00,00,0,20,1,1,1,12,01,00,0000,00,7,03,0,0,0,1999|6181| [W2]_Y,ALU_PCI, ;Write register
|1999|6182| RETURN
|1999|6183|
|1999|6184|;Here for a receiver interrupt for a PCI line
|1999|6185|; call with adr of line status register in W6, and status in W1
000,000,0,04,10,1,00,0,14,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0006,00,7,01,0,0,0,2000|6186|INT RCV:
|2000|6187| J[LNXRHD]_[W4] ;Offset for receive header
000,000,0,07,10,1,26,2,00,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,3713,00,7,07,0,0,0,2001|6188| SWAP [W6]_[W1] F_Q,ZERO_F, ;Get line number
|2001|6189| CALL [RDPCI2] ;Read receiver register
|2001|6190| J[0377]_[W3] ;Mask to strip extraneous bits
000,000,0,04,14,0,02,0,10,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,3707,00,7,00,0,0,0,2003|6191| [W1]&[W3]_B, ;Strip extraneous bits
|2003|6192| CALL [RD PCI SR] ; and get SR
|2003|6193| J[070]_[W2] ;Mask for error bits
000,000,0,04,14,0,06,0,00,0,0,00,00,00,00,00,0,64,1,0,1,03,02,00,3731,00,7,00,0,0,0,2005|6194| [W2]&[W1]_B, ;Leave only error flags
|2005|6195| IF CT [IZ IX_UX] THEN [RINT2]
|2005|6196| J[0400]_[W2] ;Error flag
000,000,0,04,10,1,00,0,04,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0400,00,7,01,0,0,0,2006|6197| [W2].OR.[W3]_B ;Add flag
000,000,0,04,17,0,06,0,10,0,0,00,00,00,00,00,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,2007|6198| SWAP [W1]_[W3 LH] ;Add flags
000,000,0,14,14,0,76,0,24,0,0,00,00,00,00,00,0,64,1,1,1,03,03,00,3740,00,7,00,0,0,0,2009|6199|RINT2: [K -1.0]&[W6]_Y, ;See if this is the cty
|2009|6200| IF NOT CT [IZ] THEN [RINT10] ; Branch if not cty
|2009|6201| J[0177]_[W2] ;Mask to strip parity
000,000,0,07,14,0,12,0,04,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0034,00,7,01,0,0,0,2011|6202| [W3]&[W2]_F,F_Q FJ[034]_[W2] ;^\ char
|2011|6203| J[CMDFLG]_RAMFILE ADR ;Address console flags
000,000,0,14,01,1,06,0,00,0,1,00,00,00,00,00,0,64,1,1,1,03,02,00,0722,00,7,00,0,0,0,2013|6204| Q-[W2]_Y, ;Check for typing ^\
|2013|6205| IF CT [IZ] THEN [CNTRL BKSLSH]
000,000,0,04,10,0,00,0,04,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0000,00,7,04,0,0,0,2014|6206| RAMFILE_Y,Y_[W2] ;Get console flags
000,000,0,14,14,0,47,0,04,0,0,00,00,00,00,00,0,64,1,1,1,03,02,00,0624,00,7,00,0,0,0,2015|6207| [BIT4]&[W2]_Y, ;(F.USR) Branch if user mode
|2015|6208| IF CT [IZ] THEN [CONSOLE CHAR] ;Treat as CTY input
|2015|6209|
|2015|6210|;Here for a receive interrupt except for CTY in Console mode
|2015|6211|; received char in W4
000,000,0,14,06,1,22,0,00,0,0,00,00,00,00,00,0,20,1,0,1,16,00,00,0000,00,7,00,0,0,0,2016|6212|RINT10:
|2016|6213|.IFNOT/FTDDTM
|2016|6214| [W4]+[W6]_Y,Y_RAMFILE ADR ;Address char word
|2016|6215|.ENDIF/FTDDTM
|2016|6216|.IF/FTDDTM
|2016|6217| [W5]_Y, IX_MX ;Check status reg
000,000,0,14,03,0,16,0,24,0,0,00,00,00,00,03,0,56,1,1,1,03,03,00,3751,00,7,00,0,0,0,2017|6218| [W4]+[W6]_Y,Y_RAMFILE ADR, ;Address char word
|2017|6219| IF NOT CT [MN] THEN [RINT30] ; Branch if not DDT mode
|2017|6220|
|2017|6221|;Here because line is in DDT mode
|2017|6222|.IF/FTCRAM
|2017|6223| RAMFILE_[W2] ;Check for already holding
|2017|6224| [W2]_[W2], ;Let latches go
|2017|6225| IF CT [IZ] THEN [RINTI2]
|2017|6226|.ENDIF/FTCRAM
|2017|6227|.IFNOT/FTCRAM
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,64,1,1,0,03,02,00,3745,00,7,04,0,0,0,2018|6228| RAMFILE_Y, ;Check for already holding
|2018|6229| IF CT [IZ] THEN [RINT12]
|2018|6230|.ENDIF/FTCRAM
|2018|6231| J[0420]_[W2] ;Overrun error
000,000,0,04,10,1,00,0,04,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0420,00,7,01,0,0,0,2019|6232| [W2].OR.[W1]_B ;Add error flag
000,000,0,04,10,0,02,2,15,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0000,00,7,07,0,0,0,2021|6233|RINT12: SWAP [W1]_[W4 LH] ;Put flags in LH
|2021|6234| [W4]_RAMFILE ;Save character
000,000,0,14,14,0,77,0,14,0,0,00,00,00,00,00,0,20,1,1,1,16,00,00,0000,00,7,04,0,0,0,2022|6235| CALL [SET RDN] ;Set receiver done
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,3663,00,7,00,0,0,0,2023|6236| GOTOP [PCI INT CLR]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,13,01,00,3613,00,7,00,0,0,0,2024|6237|.ENDIF/FTDDTM
|2024|6238|
|2024|6239|;Here because line is not in DDT mode
000,000,0,04,10,1,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,2000,00,7,01,0,0,0,2025|6240|RINT30: J[02000]_[W1] ;Will become bit RXEN
|2025|6241| SWAP [W1]_[W1] ;Make RXEN
000,000,0,14,14,0,22,0,00,0,0,00,00,00,00,00,0,64,1,1,1,03,02,00,4004,00,7,00,0,0,0,2027|6242| [W5]&[W1]_Y,
|2027|6243| IF CT [IZ] THEN [RINT99]
|2027|6244|;Here to put next byte into buffer
|2027|6245| J[RCV TTY PF]_[W1]
000,000,0,04,10,1,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,4010,00,7,01,0,0,0,2028|6246| CALL [SET PF RCOVR]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,5017,00,7,00,0,0,0,2029|6247| J[#24B MASK]_RAMFILE ADR
000,000,0,04,10,0,00,0,04,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,3630,00,7,04,0,0,0,2031|6248| RAMFILE_[W2], ;Get 24 bit mask
|2031|6249| CALL [NXT RX WRD] ; Get word for char
|2031|6250| J[0777]_[W1] ;Mask for data
000,000,1,11,06,1,33,0,04,0,0,00,00,51,00,00,0,20,1,0,1,16,00,00,0000,00,7,00,0,0,0,2033|6251| ROL [PMA]_[W2],IX_MX ;Byte #ab, b_MN
000,000,1,11,06,1,06,0,04,0,0,00,00,51,00,00,0,56,1,0,1,03,03,00,3765,00,7,00,0,0,0,2034|6252| ROL [W2]_[W2], ;Byte #ab, a_MN
|2034|6253| IF NOT CT [MN IX_MX] THEN [RINT70]
|2034|6254| IF NOT CT [MN] THEN [RINT72] ;Check for byte 2 or 3
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,56,1,1,0,03,03,00,3767,00,7,00,0,0,0,2035|6255| GOTO [RINT73]
000,000,0,04,10,0,12,2,10,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0000,00,7,07,0,0,0,2037|6256|RINT70: SWAP [W3]_[W3] ;Enter here for byte 0
000,000,0,04,10,0,02,2,00,0,0,00,00,00,00,00,0,56,1,1,0,03,02,00,3773,00,7,07,0,0,0,2038|6257| SWAP [W1]_[W1], ;Swap mask also
|2038|6258| IF CT [MN] THEN [RINT73] ;Check for byte 0 or 1
000,000,1,11,06,1,12,0,10,0,0,00,00,11,00,00,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,2039|6259|RINT72: #2*[W3]_[W3] ;Enter here for byte 2
000,000,1,11,06,1,02,0,00,0,0,00,00,11,00,00,0,20,1,1,1,14,00,00,0003,00,7,00,0,0,0,2040|6260| #2*[W1]_[W1],J[3]_CTR
000,000,1,11,03,0,12,0,10,0,0,00,00,11,00,00,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,2041|6261|RINT74: #4*[W3]_B
000,000,1,11,03,0,02,0,00,0,0,00,00,11,00,00,0,20,1,1,1,11,00,00,3771,00,7,00,0,0,0,2042|6262| #4*[W1]_B,LOOP [RINT74] ;Shift mask also
000,000,0,04,11,0,02,0,44,0,0,00,00,00,00,00,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,2043|6263|RINT73: [W1]BAR&[MB]_B ;Enter here for byte 3
|2043|6264| ; Clear slot for byte
000,000,0,04,17,0,12,0,44,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,4704,00,7,00,0,0,0,2044|6265| [W3].OR.[MB]_B, ;Add new byte
|2044|6266| CALL [UNMAPPED WRITE] ; Save in buffer
|2044|6267| IF NOT CT [UZ] THEN [RINT99] ;Check for buffer exhausted
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,3663,00,7,00,0,0,0,2046|6268|RINT93: CALL [SET RDN] ;We are done with buffer
|2046|6269| J[LNXRHD]_[W4] ;Got clobbered so restore
000,000,0,14,03,0,26,0,14,0,0,00,00,00,00,03,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,2048|6270| [W6]+[W4]_Y,Y_RAMFILE ADR ;Addr RF copy of current hdr adr
000,000,0,04,10,0,00,0,33,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,4105,00,7,04,0,0,0,2049|6271| RAMFILE_[PMA], ;Get adr of header
|2049|6272| CALL [CHNG2] ; write pointer back
|2049|6273| CALL [GET NXT RX HDR] ;Get header for next buffer
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,3636,00,7,00,0,0,0,2050|6274| IF CT [UOVR] CALL [CLR RGO] ;We have now stopped
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,13,01,00,3613,00,7,00,0,0,0,2052|6275|RINT99: GOTOP [PCI INT CLR] ;Dismiss interrupt
|2052|6276|
|2052|6277|;Here because memory error on receive
000,000,0,01,06,1,57,0,00,0,0,00,00,51,00,00,0,20,1,1,1,14,00,00,0001,00,7,00,0,0,0,2053|6278|RINT91: ROR [BIT17]_[W1], J[1]_CTR ;Need to make a bit 20
000,000,0,01,06,1,02,0,00,0,0,00,00,51,00,00,0,20,1,1,1,11,00,00,4006,00,7,00,0,0,0,2054|6279|RINT92: ROR [W1]_[W1],LOOP [RINT92] ;Rotate to bit20
000,000,0,04,17,0,02,0,20,0,0,00,00,00,00,00,0,20,1,1,1,03,01,00,3776,00,7,00,0,0,0,2055|6280| [W1].OR.[W5]_B, ;Add rcv mem err flag
|2055|6281| GOTO [RINT93] ; and stop transmission
|2055|6282|
|2055|6283|;Here when page fail (=nxm or mem fault) on rcv
000,000,0,01,06,1,57,0,00,0,0,00,00,51,00,00,0,20,1,1,1,04,01,00,0001,00,7,00,0,0,0,2056|6284|RCV TTY PF:
|2056|6285| ROR [BIT17]_[W1],PUSH J[1]_CTR ;Make a bit 18
000,000,0,01,06,1,02,0,00,0,0,00,00,51,00,00,0,20,1,1,1,10,00,00,0000,00,7,00,0,0,0,2057|6286| ROR [W1]_[W1],RFCT ;Make a bit 20
000,000,0,04,17,0,02,0,20,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,3663,00,7,00,0,0,0,2058|6287| [W1].OR.[W5]_B, ;Set rcv mem err flag
|2058|6288| CALL [SET RDN] ; And flag transmitter stopped
|2058|6289| GOTO [PCI INT CLR]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,03,01,00,3613,00,7,00,0,0,0,2059|6290|
|2059|6291|;Here for a dataset change interrupt for a PCI line
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,3707,00,7,00,0,0,0,2060|6292|INT DSC:
|2060|6293| CALL [RD PCI SR] ; Get status register
|2060|6294| J[0300]_[W2] ;Mask for DSD & DCD
000,000,0,04,14,0,06,0,00,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,4027,00,7,00,0,0,0,2062|6295| [W2]&[W1]_B, ;Leave only new DSD&DCD in W1
|2062|6296| CALL [SWAP W2_W2] ;Put mask in LH
000,000,0,06,14,0,06,0,20,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,3031,00,7,00,0,0,0,2063|6297| [W2]&[W5]_Q, ;Put only DSD & DCD in Q
|2063|6298| CALL [SWAP W1 W1] ;Put new status in LH
000,000,0,14,13,1,02,0,00,0,0,00,00,00,00,00,0,64,1,1,1,03,02,00,4025,00,7,00,0,0,0,2064|6299| Q.XOR.[W1]_F,F_Y, ;Check for change
|2064|6300| IF CT [IZ] THEN [IDSC3]
|2064|6301| [W2]BAR&[W5]_B ;Clear old status bits
000,000,0,04,11,0,06,0,20,0,0,00,00,00,00,00,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,2065|6302| J[04000]_[W2 RH] ;Get bit to make dataset change
000,000,0,04,10,1,00,0,06,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,4000,00,7,01,0,0,0,2066|6303| #2*([W2]+[W2 RH])_B ;Makes dataset change bit
000,000,0,14,17,0,06,0,20,0,0,00,00,00,00,00,0,20,1,1,1,16,00,00,0000,00,7,04,0,0,0,2068|6304| [W2].OR.[W5]_Y, ;Set bits
|2068|6305| ALU_RAMFILE
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,13,01,00,3613,00,7,00,0,0,0,2069|6306|IDSC3: GOTOP [PCI INT CLR] ;Dismiss interrupt
|2069|6307|
000,000,0,04,10,0,02,2,00,0,0,00,00,00,00,00,0,20,1,1,0,12,01,00,0000,00,7,07,0,0,0,2070|6308|SWAP W1_W1:
|2070|6309| SWAP [W1]_[W1],
|2070|6310| RETURN
000,000,0,04,10,0,06,2,04,0,0,00,00,00,00,00,0,20,1,1,0,12,01,00,0000,00,7,07,0,0,0,2071|6311|SWAP W2_W2:
|2071|6312| SWAP [W2]_[W2],
|2071|6313| RETURN
|2071|6314|
|2071|6315|;Here to accumulate CRC for character
|2071|6316|; call with [W1] char
|2071|6317|; [W2] CRC so far
|2071|6318|; [W3] CRC seed
|2071|6319|.IF/FTCRC
|2071|6320|CRC CALC:
|2071|6321| [W1].XOR.[W2]_F,F_B,
|2071|6322| J[7]_CTR
|2071|6323|CRC 2: [W2]_F,F LRS_[W2] SIO0_MC
|2071|6324| IF CT [MC] THEN [CRC 3]
|2071|6325| LOOP [CRC 2]
|2071|6326| RETURN
|2071|6327|CRC 3: [W3].XOR.[W2]_F,F_B,
|2071|6328| LOOP [CRC 2]
|2071|6329| RETURN
|2071|6330|.ENDIF/FTCRC
|2071|6331|
|2071|6332|.TOC 2, "External IO"
|2071|6333|
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,01,36,00,3072,00,7,00,0,0,0,2072|6334|IO EFA:
|2072|6335| IF [USER] CALL [CHECK IO OK] ;Give users MUUOs
|2072|6336| DISPATCH [DISPATCH 2]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,06,01,00,0000,11,7,00,0,0,0,2073|6337|
000,000,0,14,14,0,52,0,54,0,0,00,14,00,00,00,0,64,1,1,1,13,03,00,1420,00,7,00,0,0,0,2074|6338|TIOE: [AC-OP]&[MEM-OP]_Y, ;Check for need to skip
|2074|6339| IF NOT CT [IZ] THENP [IFETCH],
|2074|6340| SET LOCAL
000,000,0,04,06,1,36,0,36,0,1,00,00,00,00,00,0,20,1,1,1,13,01,00,1420,00,7,00,0,0,0,2075|6341| [PC]+1_[PC RH], ; Skip
|2075|6342| GOTOP [IFETCH]
|2075|6343|
|2075|6344|;TIOEB:
|2075|6345|
000,000,0,14,14,0,52,0,54,0,0,00,14,00,00,00,0,64,1,1,1,03,02,00,1420,00,7,00,0,0,0,2076|6346|TION: [AC-OP]&[MEM-OP]_Y, ;Check for need to skip
|2076|6347| IF CT [IZ] THEN [IFETCH],
|2076|6348| SET LOCAL
000,000,0,04,06,1,36,0,36,0,1,00,00,00,00,00,0,20,1,1,1,13,01,00,1420,00,7,00,0,0,0,2077|6349| [PC]+1_[PC RH], ; Skip
|2077|6350| GOTOP [IFETCH]
|2077|6351|
|2077|6352|;TIONB:
|2077|6353|
000,000,0,04,10,0,00,0,54,0,0,00,00,00,00,00,0,20,1,1,0,03,01,00,4037,00,7,04,0,0,0,2078|6354|WRIO: RAMFILE_[MEM-OP],
|2078|6355| GOTO [WRIO.1]
|2078|6356|
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,4042,00,7,00,0,0,0,2079|6357|WRIO.1: CALL [WRIOX]
000,000,0,14,10,0,00,0,00,0,0,00,14,00,00,00,0,26,1,1,0,13,03,00,1420,00,7,00,0,0,0,2080|6358| SET LOCAL,
|2080|6359| IF NOT CT [UOVR] THENP [IFETCH]
|2080|6360| GOTOP [IO PF] ;Win an IO page fail
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,13,01,00,4745,00,7,00,0,0,0,2081|6361|
|2081|6362|;Here to to an IO write
|2081|6363|; Call with data in [MEM-OP] and adr in [E]
|2081|6364|; returns with UOVR if illegal
000,000,0,04,14,0,67,0,40,0,0,00,00,00,00,00,0,17,0,1,1,01,01,00,1545,00,7,00,0,0,0,2082|6365|WRIOX: [K 7777.-1]&[E]_B,#1_UOVR, ;Strip extraneous bits
|2082|6366| CALL [VAL IO ADR] ; Validate IO address
000,000,0,04,06,1,42,0,33,0,0,00,00,05,00,00,0,56,1,1,1,03,02,00,4047,00,4,02,0,0,0,2083|6367| [E]_[PMA],START IO WRITE, ;Put out IO address
|2083|6368| IF CT [MN] THEN [WRIO TTY]
000,000,0,04,06,1,56,0,54,0,0,00,00,05,00,00,0,20,1,0,1,16,00,00,0000,00,5,02,0,0,0,2084|6369| [MEM-OP]_[MEM-OP],ALU_IO ;Perform transfer
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,16,0,1,0,12,61,00,0000,00,0,00,0,0,0,2085|6370| #0_UOVR,MEM HOLD,
|2085|6371| IF [NO BUS ERROR] RETURN
|2085|6372|.IFNOT/FTCKBP
|2085|6373| IF [NOT MEM EXISTS] THEN [SET UOVR]
|2085|6374| IF [NOT MEM FAULT] RETURN
|2085|6375|.ENDIF/FTCKBP
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,17,0,1,0,12,01,00,0000,00,7,00,0,0,0,2086|6376| #1_UOVR,RETURN ;Set error flag
|2086|6377|
|2086|6378|;Here to do an IO write to a TTY register
000,000,0,14,02,0,42,0,00,0,1,00,00,00,00,00,0,76,1,0,1,12,02,00,0000,00,7,00,0,0,0,2087|6379|WRIO TTY:
|2087|6380| [E]-[W1]_F,F_Y,
|2087|6381| IF CT [IN IX_MX] RETURN
000,000,0,04,10,0,00,0,10,0,0,00,00,00,00,00,0,44,1,1,0,03,02,00,4124,00,7,04,0,0,0,2088|6382| RAMFILE_[W3], ;Get old contents of word
|2088|6383| IF CT [MZ] THEN [WRIOTM]
000,000,0,04,06,1,56,0,20,0,0,00,00,00,00,00,0,16,0,1,1,16,00,00,0000,00,7,04,0,0,0,2089|6384| [MEM-OP]_[W5],ALU_RAMFILE, ;Write word
|2089|6385| #0_UOVR
000,000,0,06,14,0,06,0,40,0,0,00,00,00,00,00,0,64,1,1,1,03,02,00,4061,00,7,00,0,0,0,2090|6386| [W2]&[E]_F,F_Q_Y, ;Test which word was written
|2090|6387| IF CT [IZ] THEN [WRIOTO] ; Branch for wrote status reg
|2090|6388|.IF/FTTTYF
|2090|6389| J[LNXXCHR]_[W2] ;Offset for xmt char
000,000,0,14,01,1,06,0,00,0,1,00,00,00,00,00,0,20,1,0,1,16,00,00,0000,00,7,00,0,0,0,2092|6390| Q-[W2]_F,F_Y,IX_MX ;See if wrote xmt char
000,000,0,04,11,0,02,0,24,0,0,00,00,00,00,00,0,64,1,1,1,03,02,00,4121,00,7,00,0,0,0,2093|6391| [W1]BAR&[W6]_B, ;Make adr of line block
|2093|6392| IF CT [IZ] THEN [WRIOT5]
|2093|6393|.ENDIF/FTTTYF
000,000,0,06,03,1,77,0,00,0,0,00,00,00,00,00,0,64,1,1,1,03,02,00,4060,00,7,00,0,0,0,2094|6394| Q+[K -1]_F,F_Q_Y,
|2094|6395| IF CT [IZ] THEN [WRIOT12]
000,000,0,06,03,1,77,0,00,0,0,00,00,00,00,00,0,64,1,1,1,12,03,00,0000,00,7,00,0,0,0,2095|6396| Q+[K -1]_F,F_Q_Y,
|2095|6397| IF NOT CT [IZ] RETURN
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,03,01,00,3500,00,7,00,0,0,0,2096|6398|WRIOT12:
|2096|6399| GOTO [SET PCI MODE] ;Wrote Synch reg
|2096|6400|
|2096|6401|;Here because wrote status register
000,000,0,04,10,1,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,4000,00,7,01,0,0,0,2097|6402|WRIOTO:
|2097|6403|.IFNOT/FT7PI
|2097|6404| J[6]_[W1] ;Mask for PI channel
|2097|6405| [W1]&[MEM-OP]_Y,IX_MX
|2097|6406| ROR [W1]_[W1]: ;Make mask for bit 35
|2097|6407| IF NOT CT [MZ] THEN [WRIOT1]
|2097|6408| [W1]&[MEM-OP]_Y, ; Check for putting on channel 1
|2097|6409| IF NOT CT [IZ] THEN [MUUO] ; Putting on chnl 1 illegal
|2097|6410|WRIOT1:
|2097|6411|.ENDIF/FT7PI
|2097|6412|.IF/FTTTYR
|2097|6413| J[04000]_[W1] ;Make a bit 23 from this
|2097|6414| ROL [W1]_[W1] ;Makes a bit 23
000,000,0,14,14,0,02,0,54,0,0,00,00,00,00,00,0,64,1,1,1,03,03,00,3463,00,7,00,0,0,0,2099|6415| [W1]&[MEM-OP]_Y, ;Check for doing Reset
|2099|6416| IF NOT CT [IZ] THEN [RESET PCI]
|2099|6417|.ENDIF/FTTTYR
|2099|6418| J[WRIO TMP]_RAMFILE ADR ;Address temp location
000,000,0,04,13,0,22,0,10,0,0,00,00,00,00,00,0,20,1,1,1,16,00,00,0000,00,7,04,0,0,0,2101|6419| [W5].XOR.[W3]_F,F_B,ALU_RAMFILE ;Find flags which changed
000,000,0,14,10,0,00,0,10,0,0,00,00,00,00,00,0,20,1,1,0,01,54,00,4100,00,7,00,0,0,0,2102|6420| S SEL[W3], ;Check for transmit enable changed
|2102|6421| IF [B BIT 9] CALL [CHNG TXEN]
|2102|6422| J[BIT7]_RAMFILE ADR ;Address a bit 7
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,03,0,20,1,1,0,16,00,00,0107,00,7,01,0,0,0,2103|6423| RAMFILE_[W1] ;Get a bit 7
000,000,0,14,14,0,02,0,10,0,0,00,00,00,00,00,0,64,1,1,1,01,03,00,4074,00,7,00,0,0,0,2105|6424| [W1]&[W3]_Y, ;Check for RXEN changed
|2105|6425| IF NOT CT [IZ] CALL [CHNG RXEN]
|2105|6426| CALL [SET PCI CR] ;Set CR according to status word
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,16,0,1,0,03,01,00,3225,00,7,00,0,0,0,2107|6427| #0_UOVR, ;Flag WRIO won
|2107|6428| GOTO [SET PROC REG] ; Be sure ints are right
|2107|6429|
000,000,0,04,10,1,00,0,14,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0006,00,7,01,0,0,0,2108|6430|CHNG RXEN:
|2108|6431| J[LNXRHD]_[W4] ;Offset for receive header
000,000,0,14,03,0,26,0,14,0,0,00,00,00,00,03,0,17,0,1,1,16,00,00,0000,00,7,00,0,0,0,2109|6432| [W6]+[W4]_Y,Y_RAMFILE ADR, ;Address ramfile copy
|2109|6433| #1_UOVR ; of current hdr adr
000,000,0,14,14,0,02,0,20,0,0,00,00,00,00,00,0,64,1,1,1,03,03,00,4112,00,7,00,0,0,0,2110|6434| [W1]&[W5]_Y, ;Check for went off or on
|2110|6435| IF NOT CT [IZ] THEN [SET RXEN]
|2110|6436| GOTO [CHNG2]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,03,01,00,4105,00,7,00,0,0,0,2111|6437|
000,000,0,04,10,1,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0400,00,7,01,0,0,0,2112|6438|CHNG TXEN:
|2112|6439| J[0400]_[W1] ;Make a bit 9 = CR0
|2112|6440| SWAP [W1]_[W1] ;Offset for transmit header
000,000,0,04,10,0,02,2,00,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0000,00,7,07,0,0,0,2113|6441| J[LNXXHD]_[W4]
000,000,0,14,03,0,26,0,14,0,0,00,00,00,00,03,0,17,0,1,1,16,00,00,0000,00,7,00,0,0,0,2115|6442| [W6]+[W4]_Y,Y_RAMFILE ADR, ;Address ramfile copy
|2115|6443| #1_UOVR ; of current hdr adr
000,000,0,14,14,0,02,0,20,0,0,00,00,00,00,00,0,64,1,1,1,03,03,00,4115,00,7,00,0,0,0,2116|6444| [W1]&[W5]_Y, ;Check went on or off
|2116|6445| IF NOT CT [IZ] THEN [SET TXEN]
000,000,0,14,03,0,26,0,14,0,1,00,00,00,00,03,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,2117|6446|CHNG2: [W6]+[W4]+1_F,F_Y,Y_RAMFILE ADR ;Address ramfile copy of pointer
000,000,0,04,10,0,00,0,44,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,3416,00,7,04,0,0,0,2118|6447| RAMFILE_[MB], ;Get ramfile copy of pointer
|2118|6448| CALL [ZERO RAMFILE] ;Clear ramfile copy
000,000,0,04,06,1,33,0,33,0,1,00,00,00,00,00,0,20,1,1,1,01,01,00,4704,00,7,00,0,0,0,2119|6449| [PMA]+1_[PMA], ;Make adr of pointer in header
|2119|6450| CALL [UNMAPPED WRITE]
|2119|6451| J[WRIO TMP]_RAMFILE ADR
000,000,0,04,10,0,00,0,10,0,0,00,00,00,00,00,0,20,1,1,0,12,01,00,0000,00,7,04,0,0,0,2121|6452| RAMFILE_[W3], ;Get changed bits back
|2121|6453| RETURN
|2121|6454|
000,000,0,04,10,0,00,0,33,0,0,00,00,00,00,00,0,64,1,1,0,01,03,00,3644,00,7,04,0,0,0,2122|6455|SET RXEN:
|2122|6456| RAMFILE_[PMA], ;Get current header adr
|2122|6457| IF NOT CT [IZ] CALL [GET RX HDR]
|2122|6458| IF CT [UOVR] CALL [CLR RGO] ;In case lost
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,26,1,1,0,01,02,00,3655,00,7,00,0,0,0,2123|6459| GOTO [RSTWTM]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,03,01,00,4117,00,7,00,0,0,0,2124|6460|
000,000,0,04,10,0,00,0,33,0,0,00,00,00,00,00,0,64,1,1,0,01,03,00,3644,00,7,04,0,0,0,2125|6461|SET TXEN:
|2125|6462| RAMFILE_[PMA], ;Get adr of current header
|2125|6463| IF NOT CT [IZ] CALL [GET RX HDR]
|2125|6464| IF CT [UOVR] CALL [CLR XGO] ;In case lost
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,03,0,20,1,1,0,16,00,00,0541,00,7,01,0,0,0,2127|6465|RSTWTM: J[WRIO TMP]_RAMFILE ADR ;Address tmp loc again
000,000,0,04,10,0,00,0,10,0,0,00,00,00,00,00,0,20,1,1,0,12,01,00,0000,00,7,04,0,0,0,2128|6466| RAMFILE_[W3],RETURN ;Restore W3 and exit
|2128|6467|
|2128|6468|.IF/FTTTYF
|2128|6469|;Here because wrote XMT char word
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,3675,00,7,00,0,0,0,2129|6470|WRIOT5: CALL [SET PCI TXEN] ;Be sure xmtr going
000,000,0,14,06,1,26,0,00,0,0,00,00,00,00,03,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,2130|6471| [W6]_Y,Y_RAMFILE ADR ;Address status word
000,000,0,04,10,0,00,0,20,0,0,00,00,00,00,00,0,20,1,1,0,03,01,00,3673,00,7,04,0,0,0,2131|6472| RAMFILE_[W5],
|2131|6473| GOTO [CLR XDN] ;Clear transmit done int flag
|2131|6474|.ENDIF/FTTTYF
|2131|6475|
|2131|6476|;Here to write TTYRCV BITS
000,000,0,14,06,1,56,0,00,0,0,00,00,00,00,00,0,16,0,1,1,12,01,00,0000,00,7,04,0,0,0,2132|6477|WRIOTM: [MEM-OP]_Y,ALU_RAMFILE,#0_UOVR,
|2132|6478| RETURN
|2132|6479|
000,000,0,04,17,0,52,0,54,0,0,00,00,00,00,00,0,20,1,1,1,13,01,00,4037,00,7,00,0,0,0,2133|6480|BSIO: [AC-OP].OR.[MEM-OP]_B, ;Add new bits we want
|2133|6481| GOTOP [WRIO.1]
|2133|6482|
|2133|6483|;BSIOB:
|2133|6484|
000,000,0,04,11,0,52,0,54,0,0,00,00,00,00,00,0,20,1,1,1,13,01,00,4037,00,7,00,0,0,0,2134|6485|BCIO: [AC-OP]BAR&[MEM-OP]_B, ;Clear bits we do not like
|2134|6486| GOTOP [WRIO.1]
|2134|6487|
|2134|6488|;BCIOB:
|2134|6489|
|2134|6490|.TOC "Trap Handling"
|2134|6491|
|2134|6492|;Here to store nothing
000,000,0,14,10,0,00,0,00,0,0,00,14,00,00,00,0,20,1,1,0,13,67,00,1420,00,7,00,0,0,0,2135|6493|TO NOWHERE:
|2135|6494| SET LOCAL,
|2135|6495| IF [NOT TRAP] THENP [IFETCH]
|2135|6496| ;GOTOP [TRAP]
|2135|6497|
|2135|6498|;Here at end of instruction to see if need to trap
000,000,0,04,10,1,00,0,00,0,0,00,70,00,00,00,0,20,1,1,0,16,00,00,0600,00,7,01,0,0,0,2136|6499|TRAP: J[0600]_[W1],CLEAR TRAP ;Trap flags
000,000,0,04,10,0,02,2,33,0,0,00,14,00,00,00,0,20,1,1,0,13,41,00,1420,00,7,07,0,0,0,2137|6500| SWAP [W1]_[PMA],SET LOCAL,
|2137|6501| IF [NOT PAGED] THENP [IFETCH]
000,000,0,04,14,0,03,0,33,0,0,00,00,00,00,00,0,64,1,1,1,13,02,00,1420,00,7,00,0,0,0,2138|6502| [PC FLAGS]&[PMA]_B, ;Check for need to do a trap
|2138|6503| IF CT [IZ] THENP [IFETCH]
|2138|6504| PUSH J[010]_CTR
000,000,1,11,06,1,33,0,33,0,0,00,00,51,00,00,0,20,1,1,1,10,00,00,0000,00,7,00,0,0,0,2140|6505| ROL [PMA]_[PMA],RFCT
|2140|6506| J[0420]_[W1]
000,000,0,04,03,0,02,0,33,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,4140,00,7,00,0,0,0,2142|6507| [W1]+[PMA]_B,
|2142|6508| CALL [U!E READ]
|2142|6509| GOTO [IFETCH 4] ;Do instruction
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,03,01,00,1435,00,7,00,0,0,0,2143|6510|
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,03,37,00,4142,00,7,00,0,0,0,2144|6511|U!E READ:
|2144|6512| IF [EXEC] THEN [U!E R2]
000,000,0,04,03,0,23,0,33,0,0,00,00,05,00,00,0,20,1,1,1,03,01,00,4573,00,1,02,0,0,0,2145|6513| [UPT]+[PMA]_B,MEM START READ,
|2145|6514| GOTO [UNMAPPED READ]
000,000,0,04,03,0,17,0,33,0,0,00,00,05,00,00,0,20,1,1,1,03,01,00,4573,00,1,02,0,0,0,2146|6515|U!E R2: [EPT]+[PMA]_B,MEM START READ,
|2146|6516| GOTO [UNMAPPED READ]
|2146|6517|
|2146|6518|;Here to set overflow and trap 1
000,000,0,04,10,1,00,0,00,0,0,00,74,00,00,00,0,20,1,1,0,16,00,00,4002,00,7,01,0,0,0,2147|6519|SET OV!T1:
|2147|6520| J[04002]_[W1],SET TRAP
000,000,0,04,10,0,02,2,00,0,0,00,00,00,00,00,0,20,1,1,0,03,01,00,4151,00,7,07,0,0,0,2148|6521| SWAP [W1]_[W1],
|2148|6522| GOTO [#64*W1!PCF]
|2148|6523|
000,000,0,04,10,1,00,0,00,0,0,00,74,00,00,00,0,20,1,1,0,16,00,00,0200,00,7,01,0,0,0,2149|6524|SET TRAP 1: ;Set trap 1
|2149|6525| J[0200]_[W1],SET TRAP ;Bit 28
000,000,0,04,10,0,02,2,00,0,0,00,00,00,00,00,0,20,1,1,0,03,01,00,4153,00,7,07,0,0,0,2150|6526| SWAP [W1]_[W1], ;Becomes a bit 10
|2150|6527| GOTO [W1!PCF]
|2150|6528|
000,000,0,04,10,1,00,0,00,0,0,00,74,00,00,00,0,20,1,1,0,16,00,00,0400,00,7,01,0,0,0,2151|6529|SET TRAP 2: ;Set trap 2
|2151|6530| J[0400]_[W1],SET TRAP ;Bit 27
000,000,0,04,10,0,02,2,00,0,0,00,00,00,00,00,0,20,1,1,0,03,01,00,4153,00,7,07,0,0,0,2152|6531| SWAP [W1]_[W1], ;Becomes bit 9
|2152|6532| GOTO [W1!PCF]
|2152|6533|
000,000,1,11,03,0,02,0,00,0,0,00,00,11,00,00,0,20,1,1,1,14,00,00,0001,00,7,00,0,0,0,2153|6534|#64*W1!PCF:
|2153|6535| #4*[W1]_B,J[1]_CTR ;Shift bits left
000,000,1,11,03,0,02,0,00,0,0,00,00,11,00,00,0,20,1,1,1,11,00,00,4152,00,7,00,0,0,0,2154|6536|SPCF 2: #4*[W1]_B,LOOP [SPCF 2] ;Keep shifting bits
000,000,0,04,17,0,02,0,03,0,0,00,00,00,00,00,0,20,1,1,1,12,01,00,0000,00,7,00,0,0,0,2155|6537|W1!PCF: [W1].OR.[PC FLAGS]_B,
|2155|6538| RETURN
|2155|6539|
|2155|6540|.TOC "Interrupt Handling"
|2155|6541|
|2155|6542|;If this is a clock interrupt will return, but may clobber W2-W3
|2155|6543|; If not clock will return to IFETCH
000,000,0,04,03,0,77,0,37,0,0,00,00,00,26,00,0,20,1,0,1,13,74,00,4226,00,0,00,0,0,0,2156|6544|CHK INT:
|2156|6545| [K -1]+[TIME]_B,IX_MX, ;Assume clock & tick it
|2156|6546| MEM HOLD, ; do not mess up memory
|2156|6547| GRANT INTERRUPT, ; Grant interrupt
|2156|6548| IF [NOT TIMER FLAG] THENP [SKIP CHAIN]
|2156|6549|
|2156|6550|;Here for an interrupt on level 0 ... clock
000,000,0,14,06,1,43,0,00,0,0,00,00,00,46,00,0,44,1,1,1,12,03,00,0000,00,0,00,0,0,0,2157|6551| [PI REG]_Y,Y_2914 STATUS,
|2157|6552| MEM HOLD,
|2157|6553| IF NOT CT [MZ] RETURN
|2157|6554|
|2157|6555|;Here once/millisecond
|2157|6556| J[CLK W2]_RAMFILE ADR
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,03,0,20,1,1,0,16,00,00,0535,00,7,01,0,0,0,2158|6557| [W2]_RAMFILE
000,000,0,14,14,0,77,0,04,0,0,00,00,00,00,00,0,20,1,1,1,16,00,00,0000,00,7,04,0,0,0,2159|6558| J[CLK W3]_RAMFILE ADR
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,03,0,20,1,1,0,16,00,00,0536,00,7,01,0,0,0,2160|6559| [W3]_RAMFILE
000,000,0,14,14,0,77,0,10,0,0,00,00,00,00,00,0,20,1,1,1,16,00,00,0000,00,7,04,0,0,0,2161|6560| J[27.]_[TIME] ;Restart tick counter
000,000,0,04,10,1,00,0,37,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0033,00,7,01,0,0,0,2162|6561| J[TIME BASE+1]_RAMFILE ADR
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,03,0,20,1,1,0,16,00,00,0567,00,7,01,0,0,0,2163|6562| J[4000.]_[W2] ;Will add four milliseconds
000,000,0,04,10,1,00,0,04,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,7640,00,7,01,0,0,0,2164|6563| [W2]_Q RAMFILE_[W2] ;Get timebase from ramfile
000,000,0,06,03,1,06,0,00,0,0,00,00,00,00,00,0,66,1,1,1,03,03,00,4174,00,7,04,0,0,0,2166|6564| Q+[W2]_F,F_Q_Y,ALU_RAMFILE, ;Update time base in ramfile
|2166|6565| IF NOT CT [IOVR] THEN [LO12]
|2166|6566| JS[0000]_[W2]
000,000,0,14,03,1,06,0,00,0,0,00,00,00,00,00,0,20,1,1,1,16,00,00,0000,00,7,04,0,0,0,2168|6567| Q+[W2]_Y,ALU_RAMFILE ;With positive sign
|2168|6568| J[TIME BASE]_RAMFILE ADR ;Address high order part of count
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,03,0,20,1,1,0,16,00,00,0566,00,7,01,0,0,0,2169|6569| RAMFILE_[W2]
000,000,0,14,06,1,06,0,00,0,1,00,00,00,00,00,0,20,1,1,1,16,00,00,0000,00,7,04,0,0,0,2171|6570| [W2]+1_Y,ALU_RAMFILE
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,03,0,20,1,1,0,16,00,00,0564,00,7,01,0,0,0,2172|6571|LO12: J[TIME INTERVAL]_RAMFILE ADR
000,000,0,04,10,0,00,0,04,0,0,00,00,00,00,00,0,20,1,0,0,16,00,00,0000,00,7,04,0,0,0,2173|6572| RAMFILE_[W2],IX_MX
|2173|6573| J[INTERVAL COUNTER]_RAMFILE ADR ;Address the interval counter
000,000,0,07,06,1,06,0,04,0,0,00,00,00,00,00,0,44,1,1,0,03,02,00,4221,00,7,04,0,0,0,2175|6574| [W2]_Q RAMFILE_[W2], ;Get the interval counter
|2175|6575| IF CT [MZ] THEN [LO15] ; No interval = no counter
000,000,0,14,03,0,77,0,04,0,0,00,00,00,00,00,0,64,1,1,1,03,03,00,4221,00,7,04,0,0,0,2176|6576| [K -1]+[W2]_Y,ALU_RAMFILE, ;Count this interval
|2176|6577| IF NOT CT [IZ] THEN [LO15]
000,000,0,14,14,1,77,0,00,0,0,00,00,00,00,00,0,20,1,1,1,16,00,00,0000,00,7,04,0,0,0,2177|6578| Q_Y,ALU_RAMFILE ;Reinitialize interval counter
|2177|6579| J[APR FLAGS]_RAMFILE ADR ;Need to set interval flag in APR
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,03,0,20,1,1,0,16,00,00,0556,00,7,01,0,0,0,2178|6580| J[040]_[W2] ;Bit for interval
000,000,0,04,10,1,00,0,04,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0040,00,7,01,0,0,0,2179|6581| [W1]_Q RAMFILE_[W2]
000,000,0,04,17,1,06,0,04,0,0,00,00,00,00,00,0,20,1,1,1,16,00,00,0000,00,7,04,0,0,0,2181|6582| Q.OR.[W2]_[W2],ALU_RAMFILE ;Save updated APR FLAGS
|2181|6583| SWAP [W2]_[W3] ;Get enables
000,000,0,14,14,0,06,0,10,0,0,00,00,00,00,00,0,20,1,0,1,16,00,00,0000,00,7,00,0,0,0,2183|6584| [W2]&[W3]_Y,IX_MX ;Check for flag was enabled
|2183|6585| J[7]_[W3] ;Mask for PI level
000,000,0,04,14,0,06,0,10,0,0,00,00,00,00,00,0,44,1,0,1,03,02,00,4221,00,7,00,0,0,0,2185|6586| [W2]&[W3]_B, ;Check for zero PI level
|2185|6587| IF CT [MZ IX_MX] THEN [LO15] ; If not enabled done
|2185|6588| J[BIT28]_[W2] ;Base to index into bit table
000,000,0,14,03,0,06,0,10,0,0,00,00,00,00,03,0,44,1,1,1,03,02,00,4221,00,7,00,0,0,0,2187|6589| [W2]+[W3]_Y,Y_RAMFILE ADR, ;Address bit
|2187|6590| IF CT [MZ] THEN [LO15] ; If PI level=O done
|2187|6591| RAMFILE_[W3] ;Get bit
000,000,0,04,10,0,00,0,10,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0000,00,7,04,0,0,0,2188|6592| J[RF PROC REG]_RAMFILE ADR ;Address last value of PROC REG
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,03,0,20,1,1,0,16,00,00,0563,00,7,01,0,0,0,2189|6593| RAMFILE_[W2] ;Get last value of processor reg
000,000,0,14,06,1,12,0,00,0,0,00,00,00,00,00,0,20,1,1,1,16,00,00,0000,00,7,04,0,0,0,2191|6594| [W2].OR:[W3]_Y,ALU_RAMFILE ;Save new last value of PROC REG
000,000,0,14,17,0,06,0,10,0,0,00,00,00,00,00,0,20,1,1,1,16,00,00,0000,00,7,10,0,0,0,2192|6595| [W2].OR.[W3]_Y,ALU_PROC REG ;Change software interrupts
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,03,0,20,1,1,0,16,00,00,0535,00,7,01,0,0,0,2193|6596|LO15: J[CLK W2]_RAMFILE ADR ;Where we saved W2
|2193|6597| RAMFILE_[W2]
000,000,0,04,10,0,00,0,04,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0000,00,7,04,0,0,0,2194|6598| J[CLK W3]_RAMFILE ADR ;Where we saved W3
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,03,0,20,1,1,0,16,00,00,0536,00,7,01,0,0,0,2195|6599| RAMFILE_[W3]
000,000,0,04,06,1,33,0,33,0,0,00,00,05,00,00,0,20,1,1,1,12,01,00,0000,00,1,02,0,0,0,2197|6600| [PMA]_[PMA],MEM START READ, ;Restart memory read
|2197|6601| RETURN
|2197|6602|
|2197|6603|;Here if interrupt is not clock
000,000,0,04,06,1,37,0,37,0,1,00,00,00,00,00,0,20,1,1,1,13,43,00,4230,00,7,00,0,0,0,2198|6604|SKIP CHAIN:
|2198|6605| [TIME]+1_[TIME], ;Correct time register
|2198|6606| IF [NOT RUN] THENP [SKPC2]
000,000,0,04,03,0,77,0,36,0,0,00,00,00,00,00,0,20,1,1,1,15,01,00,0000,00,7,00,0,0,0,2199|6607| [K -1]+[PC RH]_B,POP ;Back up PC
000,000,0,04,06,1,43,0,60,0,0,00,14,00,00,00,0,20,1,1,1,15,01,00,0000,00,7,00,0,0,0,2200|6608|SKPC2: SET LOCAL,[PI REG]_[PXCT],POP ;Save previous level
000,000,0,04,10,0,00,0,43,0,0,00,00,00,32,00,0,20,1,1,0,15,01,00,0000,00,7,00,0,0,0,2201|6609| #2914 STATUS_Y,Y_[PI REG],POP ;Get PI REG in case of int
000,000,0,04,10,1,00,0,24,0,0,00,00,00,00,00,0,20,1,1,0,15,01,00,0007,00,7,01,0,0,0,2202|6610| J[7]_[W6],POP ;In case this is PI lvl 1 int
|2202|6611|.IF/DEBUG3
|2202|6612| [W6]&[PXCT]_B
000,000,0,14,13,0,26,0,60,0,0,00,00,00,00,00,0,64,1,1,1,03,02,00,4234,00,7,00,0,0,0,2204|6613|FOOEY: [W6].XOR.[PXCT]_Y,
|2204|6614| IF CT [IZ] THEN [FOOEY]
|2204|6615|.ENDIF/DEBUG3
000,000,0,04,14,0,26,0,43,0,0,00,00,00,00,00,0,20,1,1,1,15,01,00,0000,00,7,00,0,0,0,2205|6616| [W6]&[PI REG]_B,POP ;Clear extraneous bits
|2205|6617| IF [PXCT] CALL [SET CURRENT CTXT]
000,000,0,14,13,0,26,0,43,0,0,00,00,00,00,00,0,64,1,1,1,03,03,00,4262,00,7,00,0,0,0,2207|6618| [W6].XOR.[PI REG]_Y, ;Check level
|2207|6619| IF NOT CT [IZ] THEN [SKPC8] ; If not 1evel 1 not PCI
|2207|6620|.IF/DEBUG3
|2207|6621| J[POOP FLAG]_RAMFILE ADR
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,03,0,20,1,1,0,16,00,00,0520,00,7,01,0,0,0,2208|6622| RAMFILE_[W1]
000,000,0,04,06,1,02,0,00,0,0,00,00,00,00,00,0,64,1,1,1,03,03,00,4242,00,7,00,0,0,0,2210|6623|POOP: [W1]_[W1],
|2210|6624| IF NOT CT [IZ] THEN [POOP]
000,000,0,14,00,1,00,0,00,0,0,00,00,00,00,00,0,20,1,1,1,16,00,00,0000,00,7,04,0,0,0,2211|6625| ONES_F,F_Y,ALU_RAMFILE
|2211|6626|.ENDIF/DEBUG3
000,000,0,04,06,1,00,1,00,0,0,00,00,00,00,00,0,20,1,1,1,15,01,00,0000,00,7,00,0,0,0,2212|6627| LINE #_[W1],POP ;In case this is a line int
|2212|6628|
|2212|6629|;Contents of W1 (line # reg) are
|2212|6630|; bits 33-35 =line number
|2212|6631|; bit 31-32 =code, 0-receive, l-transmit, 2-dschange
|2212|6632|; bit 30 = 0
|2212|6633|; bit 29 = invalid
|2212|6634|; bits 0-28 = garbage
|2212|6635| J[0100]_[W2] ;Mask for invalid flag
000,000,0,14,14,0,02,0,04,0,0,00,00,00,00,00,0,64,1,1,1,03,03,00,4246,00,7,00,0,0,0,2214|6636|SKPC5: [W1]&[W2]_Y, ;Check for invalid flag
|2214|6637| IF NOT CT [IZ] THEN [SKPC5] ;If not valid chase skip chain
|2214|6638| [W1]&[W6]_B ;Leave only line number
000,000,0,04,14,0,02,0,24,0,0,00,00,00,00,00,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,2215|6639| SWAP [W6]_[W6 LH] ;Put line number in LH also
000,000,0,04,10,0,26,2,25,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0000,00,7,07,0,0,0,2216|6640| #2*([W6]+[W6 RH])_B ;Makes 4*linel in W6 RH
000,000,0,07,03,0,26,0,26,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0200,00,7,01,0,0,0,2218|6641| [W6]+[W6 RH]_F, ;Make 10*line#
|2218|6642| F_Q FJ[LNOSW]_[W6 RH] ; adr of first line block
000,000,0,04,03,1,26,0,26,0,0,00,00,00,00,03,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,2219|6643| Q+[W6]_[W6 RH], ;Leaves line#,,line block adr
|2219|6644| Y_RAMFILE ADR
|2219|6645| RAMFILE_[W5] ;Get status word for line
000,000,0,04,10,0,00,0,20,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0000,00,7,04,0,0,0,2220|6646| J[010]_[W2] ;Mask for dispatch
000,000,0,14,14,0,02,0,04,0,0,00,00,00,00,00,0,64,1,1,1,13,03,00,3535,00,7,00,0,0,0,2222|6647| [W1]&[W2]_Y, ;Check for transmit
|2222|6648| IF NOT CT [IZ] THENP [INT XMT]
|2222|6649| J[020]_[W2] ;Another mask
000,000,0,14,14,0,02,0,04,0,0,00,00,00,00,00,0,64,1,1,1,13,02,00,3720,00,7,00,0,0,0,2224|6650| [W1]&[W2]_Y, ;Check for rcv or dsc
|2224|6651| IF CT [IZ] THENP [INT RCV]
|2224|6652| GOTOP [INT DSC]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,13,01,00,4014,00,7,00,0,0,0,2225|6653|
|2225|6654|
|2225|6655|;Here if interrupt is not for a PCI line
000,000,0,04,10,1,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0144,00,7,01,0,0,0,2226|6656|SKPC8: J[BIT36]_[W1] ;Bit table
000,000,0,14,02,0,02,0,43,0,0,00,00,00,00,03,0,20,1,1,1,01,01,00,1216,00,7,00,0,0,0,2227|6657| [W1]-[PI REG]_Y,Y_RAMFILE ADR, ;Address bit for level
|2227|6658| CALL [RAMFILE_W1] ; Get bit for level
|2227|6659| J[PI IN PROG]_RAMFILE ADR
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,03,0,20,1,1,0,16,00,00,0557,00,7,01,0,0,0,2228|6660| [W1]_Q RAMFILE_[W1]
000,000,0,14,17,1,02,0,00,0,0,00,00,00,00,00,0,20,1,1,1,16,00,00,0000,00,7,04,0,0,0,2230|6661| Q.OR.[W1]_Y,ALU_RAMFILE ;Add this level also in progress
|2230|6662| J[060]_[E] ;New PC is 40+2n
000,000,0,06,02,0,42,0,43,0,0,00,00,00,00,03,0,20,1,1,0,16,00,00,0027,00,7,01,0,0,0,2232|6663| [E]-[PI REG]_Q,
|2232|6664| J[#23B MASK]_RAMFILE ADR ; virtual addresses are 23 bits
000,000,0,07,01,1,43,0,20,0,1,00,00,00,00,00,0,20,1,1,0,03,44,00,4273,00,7,04,0,0,0,2233|6665| Q-[PI REG]_F,RAMFILE_Y,
|2233|6666| F_Q Y_[W5],IF [TOPS20] THEN [SKPC82]
000,000,0,04,07,0,76,0,20,0,0,00,00,00,00,00,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,2234|6667| COMPLEMENT [K -1.0]_F,F_[W5] ;Smaller address for TOPS10
000,000,0,04,10,1,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,4317,00,7,01,0,0,0,2235|6668|SKPC82: J[INT HALT]_[W1] ; In case we get a page fail
|2235|6669| CALL [SET PF RCOVR]
000,000,0,04,03,1,17,0,33,0,0,00,00,05,00,00,0,20,1,1,1,01,01,00,4573,00,1,02,0,0,0,2237|6670| Q+[EPT]_[PMA],MEM START READ, ;Pick up interrupt instruction
|2237|6671| CALL [UNMAPPED READ]
000,000,0,04,06,1,46,0,40,0,0,00,00,00,00,00,0,20,1,0,1,16,00,00,0000,00,7,00,0,0,0,2238|6672| [MB]_[E],IX_MX ;This is adr of XPCW block
000,000,0,14,11,0,22,0,44,0,0,00,00,00,00,00,0,44,1,0,1,03,02,00,4317,00,7,00,0,0,0,2239|6673| [W5]BAR&[MB]_Y,
|2239|6674| IF CT [MZ IX_MX] THEN [INT HALT] ; If location is 0 stop
|2239|6675| [PC FLAGS]_[MB] ;Save program flags
000,000,0,01,06,1,47,0,00,0,0,00,00,51,00,00,0,20,1,1,1,01,01,00,4321,00,7,00,0,0,0,2241|6676| ROR [BIT4]_[W1], ;Clear user mode
|2241|6677| CALL [W1BAR&FLAGS]
000,000,0,01,06,1,02,0,00,0,0,00,00,51,00,00,0,20,1,1,1,01,01,00,4321,00,7,00,0,0,0,2242|6678| ROR [W1]_[W1], ;Make a bit 6 a prev ctx user
|2242|6679| CALL [W1BAR&FLAGS]
|2242|6680| IF [USER] CALL [W1!PCF] ;Set prev ctxt user
000,000,0,04,14,0,67,0,34,0,0,00,20,00,00,00,0,44,1,1,1,03,02,00,4322,00,7,00,0,0,0,2244|6681| [K 7777.-1]&[PC]_B,SET EXEC, ;References are now exec
|2244|6682| IF CT [MZ] THEN [SKPC9] ; Check high order bits
|2244|6683|.IF/FT10PAG
|2244|6684| J[0264]_[W1] ;JSR instruction
000,000,0,04,10,0,02,2,00,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,3317,00,7,07,0,0,0,2246|6685| SWAP [W1]_[W1],CALL [W1 LLS9] ;Make a JSR instruction
000,000,0,14,14,0,76,0,34,0,0,00,00,00,00,00,0,20,1,0,1,03,44,00,4317,00,7,00,0,0,0,2247|6686| [K -1.0]&[PC]_Y,IX_MX, ;Check for illegal PC
|2247|6687| IF [TOPS20] THEN [INT HALT] ; JSR is only for TOPS10
000,000,0,04,13,0,02,0,40,0,0,00,00,00,00,00,0,44,1,1,1,03,03,00,4317,00,7,00,0,0,0,2248|6688| [W1].XOR.[E]_F,F_B, ;Check opcode
|2248|6689| IF NOT CT [MZ] THEN [INT HALT] ; Check illegal PC
000,000,0,14,14,0,76,0,40,0,0,00,00,00,00,00,0,64,1,1,1,03,03,00,4317,00,7,00,0,0,0,2249|6690| [K -1.0]&[E]_Y, ;Check if it was a JSR
|2249|6691| IF NOT CT [IZ] THEN [INT HALT]
|2249|6692| J[PUSHJ FLAGS]_RAMFILE ADR ;Flags to clear on a JSR
000,000,0,04,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,4321,00,7,04,0,0,0,2251|6693| RAMFILE_[W1], ;Get flags to clear
|2251|6694| CALL [W1BAR&FLAGS]
000,000,0,04,06,1,36,0,46,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,4711,00,7,00,0,0,0,2252|6695| [PC]_[MB RH], ;Add PC
|2252|6696| CALL [MEMORY WRITE] ;Do JSR
000,000,0,04,10,1,00,0,00,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,5017,00,7,00,0,0,0,2253|6697| ZERO_[W1],
|2253|6698| CALL [SET PF RCOVR]
000,000,0,04,06,1,42,0,36,0,1,00,14,00,00,00,0,20,1,1,1,13,01,00,1420,00,7,00,0,0,0,2254|6699| [E]+1_[PC RH],SET LOCAL, ;Set new PC
|2254|6700| GOTOP [IFETCH]
|2254|6701|.ENDIF/FT10PAG
|2254|6702|
000,000,0,04,10,1,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0101,00,7,01,0,0,0,2255|6703|INT HALT:
|2255|6704| J[HALT III]_[W1] ;Illegal interrupt instruction
|2255|6705| GOTOP [SET HALT CODE]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,13,01,00,1166,00,7,00,0,0,0,2256|6706|
000,000,0,04,11,0,02,0,03,0,0,00,00,00,00,00,0,20,1,1,1,12,01,00,0000,00,7,00,0,0,0,2257|6707|W1BAR&FLAGS:
|2257|6708| [W1]BAR&[PC FLAGS]_B,
|2257|6709| RETURN
|2257|6710|
|2257|6711|;Here because interrupt instruction is a 23bit virtual address
000,000,0,04,06,1,02,0,20,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,4711,00,7,00,0,0,0,2258|6712|SKPC9: [W1]_[W5], ;Save bit6
|2258|6713| CALL [MEMORY WRITE] ;Save flags in block
000,000,0,04,06,1,36,0,44,0,0,00,10,00,00,00,0,20,1,1,1,01,01,00,4710,00,7,00,0,0,0,2259|6714| [PC]_[MB],SET GLOBAL, ;Save PC in block
|2259|6715| CALL [WRITE NEXT]
000,000,0,07,06,1,42,0,40,0,1,00,00,00,00,77,0,20,1,1,1,01,01,00,4663,00,7,00,0,0,0,2260|6716| [E]+1_Q_[E], ;Read new flags
|2260|6717| SPEC SEL/PAGE TABLE ENTRY,
|2260|6718| CALL [MEMORY READ]
000,000,0,01,06,1,47,0,00,0,0,00,00,51,00,00,0,20,1,1,1,01,01,00,4333,00,7,00,0,0,0,2261|6719| ROR [BIT4]_[W1], ;Make a user mode bit
|2261|6720| CALL [W1BAR&MB_B]
|2261|6721| [W5]BAR&[MB]_B ;Clear prev ctxt user
000,000,0,04,11,0,22,0,44,0,0,00,00,00,00,00,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,2262|6722| [W5]&[PC FLAGS]_B ;Leave only previous context user
000,000,0,04,17,0,46,0,03,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,4660,00,7,00,0,0,0,2264|6723| [MB].OR.[PC FLAGS]_B, ;Set new flags
|2264|6724| CALL [READ NEXT] ;Read new PC
000,000,0,04,10,1,00,0,00,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,5017,00,7,00,0,0,0,2265|6725| ZERO_[W1], ;Done with special
|2265|6726| CALL [SET PF RCOVR] ; Page fail recovery
000,000,0,04,06,1,46,0,34,0,0,00,14,00,00,00,0,20,1,1,1,13,01,00,1420,00,7,00,0,0,0,2266|6727| [MB]_[PC],SET LOCAL, ;Set new PC
|2266|6728| GOTOP [IFETCH]
|2266|6729|
000,000,0,04,11,0,02,0,44,0,0,00,00,00,00,00,0,20,1,1,1,12,01,00,0000,00,7,00,0,0,0,2267|6730|W1BAR&MB_B:
|2267|6731| [W1]BAR&[MB]_B, ; Force exec mode
|2267|6732| RETURN
|2267|6733|
|2267|6734|
|2267|6735|.TOC 1, "Memory Operations"
|2267|6736|.TOC 2, "Store Instruction Results"
|2267|6737|
|2267|6738|;Store one word in memory, and two ACs (MULB, DIVB)
000,000,0,04,06,1,56,0,44,0,0,00,00,00,00,00,0,20,1,1,1,03,47,00,4337,00,7,00,0,0,0,2268|6739|TO MEM D AC:
|2268|6740| [MEM-OP]_[MB],
|2268|6741| IF [NOT PXCT] THEN [TMDAC4]
|2268|6742| CALL [PXCT STORE 200]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,2413,00,7,00,0,0,0,2269|6743| GOTO [D TO AC.0]
000,000,0,07,14,0,67,0,40,0,0,00,00,00,00,77,0,13,0,1,1,01,01,00,4712,00,7,00,0,0,0,2271|6744|TMDAC4: [K 7777.-1]&[E]_F,F_Q_B,#1_UC, ;Address paging ram
|2271|6745| SPEC SEL/PAGE TABLE ENTRY,
|2271|6746| CALL [MEM WRITE 1]
|2271|6747| ;GOTO [D TO AC.0]
|2271|6748|
|2271|6749|;Here to store two words in ACs SEL AC+[0] not already selected
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,27,0,20,1,1,0,16,00,01,0000,00,7,00,0,0,0,2272|6750|D TO AC.0:
|2272|6751| SEL AC+[1] ;Point ramfile at AC+1
000,000,0,14,14,0,77,0,13,0,0,00,00,00,00,00,0,20,1,1,1,03,01,00,4342,00,7,04,0,0,0,2273|6752| [MEM-OP+1]_RAMFILE, ;Store AC+1
|2273|6753| GOTO [TO AC.0]
|2273|6754|
|2273|6755|;Store a word in an AC
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,27,0,20,1,1,0,16,00,00,0000,00,7,00,0,0,0,2274|6756|TO AC.0:
|2274|6757| SEL AC+[0] ;Point ramfile at AC
|2274|6758|
|2274|6759|;Store a word in an AC, AC already selected
000,000,0,14,14,0,77,0,54,0,0,00,14,00,00,00,0,20,1,1,1,13,67,00,1420,00,7,04,0,0,0,2275|6760|TO AC: [MEM-OP]_RAMFILE,SET LOCAL, ;Write AC
|2275|6761| IF [NOT TRAP] THENP [IFETCH]
|2275|6762| GOTOP [TRAP]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,13,01,00,4130,00,7,00,0,0,0,2276|6763|
|2276|6764|;Here to store two words in ACs SEL AC+[0] already selected
000,000,0,14,14,0,77,0,54,0,0,00,00,00,00,27,0,20,1,1,1,16,00,01,0000,00,7,04,0,0,0,2277|6765|D TO AC:
|2277|6766| [MEM-OP]_RAMFILE,SEL AC+[1] ;Save first half of result
000,000,0,14,14,0,77,0,13,0,0,00,14,00,00,00,0,20,1,1,1,03,67,00,1420,00,7,04,0,0,0,2278|6767| [MEM-OP+1]_RAMFILE,SET LOCAL, ;Save second operand
|2278|6768| IF [NOT TRAP] THEN [IFETCH]
|2278|6769| GOTOP [TRAP]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,13,01,00,4130,00,7,00,0,0,0,2279|6770|
|2279|6771|;Store a word in an AC, AC already selected
000,000,0,14,14,0,77,0,50,0,0,00,14,00,00,00,0,20,1,1,1,13,67,00,1420,00,7,04,0,0,0,2280|6772|AC TO AC:
|2280|6773| [AC-OP]_RAMFILE, ;Write AC
|2280|6774| SET LOCAL,
|2280|6775| IF [NOT TRAP] THENP [IFETCH]
|2280|6776| GOTOP [TRAP]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,13,01,00,4130,00,7,00,0,0,0,2281|6777|
|2281|6778|;Here to store to self after having read location
000,000,0,04,06,1,33,0,33,0,0,00,00,05,00,00,0,20,1,1,1,03,23,00,4355,00,2,02,0,0,0,2282|6779|BACK TO SELF:
|2282|6780|.IF/FAST
|2282|6781| [PMA]_[PMA],MEM START WRITE,
|2282|6782| IF [AC REF] THEN [TO SELF]
000,000,0,04,06,1,56,0,54,0,0,00,00,05,00,00,0,20,1,0,1,03,06,00,4370,00,5,02,0,0,0,2283|6783| [MEM-OP]_MEM, ;Write data in memory
|2283|6784| IF [AC.EQ.0] THEN [BACK TO MEM 2]
000,000,0,04,06,1,56,0,44,0,0,00,00,00,00,00,0,20,1,1,1,03,61,00,4127,00,0,04,0,0,0,2284|6785| [MEM-OP]_[MB],ALU_RAMFILE, ;Write data in AC
|2284|6786| MEM HOLD,
|2284|6787| IF [NO BUS ERROR] THEN [TO NOWHERE]
|2284|6788| ;GOTO (TO SELF] ;Try again
|2284|6789|.ENDIF/FAST
|2284|6790|
|2284|6791|;Store to self, At already selected
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,03,06,00,4371,00,7,00,0,0,0,2285|6792|TO SELF:
|2285|6793| IF [AC.EQ.0] THEN [TO MEM] ;IF AC is zero store mem, else both
|2285|6794|.IF/FAST
000,000,0,14,14,0,77,0,54,0,0,00,00,00,00,00,0,20,1,1,1,03,01,00,4371,00,7,04,0,0,0,2286|6795| [MEM-OP]_RAMFILE, ;Store AC
|2286|6796| GOTO [TO MEM]
|2286|6797|.ENDIF/FAST
|2286|6798|
|2286|6799|;Store to both
|2286|6800|
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,27,0,20,1,1,0,16,00,00,0000,00,7,00,0,0,0,2287|6801|TO BOTH.0:
|2287|6802| SEL AC+[0] ;Point ramfile at AC
|2287|6803|;Store to both, AC already selected
000,000,0,14,14,0,77,0,54,0,0,00,00,00,00,00,0,20,1,1,1,03,01,00,4371,00,7,04,0,0,0,2288|6804|TO BOTH:
|2288|6805| [MEM-OP]_RAMFILE, ;Store AC
|2288|6806| GOTO [TO MEM]
|2288|6807|
|2288|6808|;Store memory data in AC and AC data in memory (EXCH instruction)
000,000,0,14,14,0,77,0,54,0,0,00,00,00,00,00,0,20,1,1,1,16,00,00,0000,00,7,04,0,0,0,2289|6809|TO EACH:
|2289|6810| [MEM-OP]_RAMFILE ;Write AC
|2289|6811| [AC-OP]_[MEM-OP]
000,000,0,04,06,1,52,0,54,0,0,00,00,00,00,00,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,2290|6812| ;GOTO [BACK TO MEM]
|2290|6813|
|2290|6814|;Here when fetched word from memory and want to write back updated number
000,000,0,04,06,1,33,0,33,0,0,00,00,05,00,00,0,20,1,1,1,03,22,00,4367,00,2,02,0,0,0,2291|6815|BACK TO MEM:
|2291|6816|.IF/FAST
|2291|6817| [PMA]_[PMA],MEM START WRITE,
|2291|6818| IF [NOT AC REF] THEN [BACK TO MEM 1]
000,000,0,14,06,1,33,0,00,0,0,00,00,00,00,23,0,20,1,1,1,03,46,00,4371,00,7,00,0,0,0,2292|6819| [PMA]_Y,SPEC SEL/VMA, ;Address AC
|2292|6820| IF [PXCT] THEN [TO MEM]
000,000,0,14,14,0,77,0,54,0,0,00,14,00,00,00,0,20,1,1,1,13,67,00,1420,00,7,04,0,0,0,2293|6821| [MEM-OP]_RAMFILE,SET LOCAL,
|2293|6822| IF [NOT TRAP] THENP [IFETCH]
|2293|6823| GOTO [TRAP]
000,000,0,04,06,1,56,0,54,0,0,00,00,05,00,00,0,20,1,0,1,16,00,00,0000,00,5,02,0,0,0,2295|6824|BACK TO MEM 1:
|2295|6825| [MEM-OP]_MEM ;Write data
000,000,0,14,10,0,00,0,00,0,0,00,14,00,00,00,0,20,1,1,0,03,61,00,4127,00,0,00,0,0,0,2296|6826|BACK TO MEM 2:
|2296|6827| MEM HOLD,SET LOCAL,
|2296|6828| IF [NO BUS ERROR] THEN [TO NOWHERE]
|2296|6829| ;GOTO [TO MEM] ;Try again
|2296|6830|.ENDIF/FAST
|2296|6831|;Store AC to memory
000,000,0,04,06,1,56,0,44,0,0,00,00,00,00,00,0,20,1,1,1,03,46,00,4375,00,7,00,0,0,0,2297|6832|TO MEM: [MEM-OP]_[MB], ;Put data in MB
|2297|6833| IF [PXCT] THEN [TO MEM PXCT]
000,000,0,07,14,0,67,0,40,0,0,00,00,00,00,77,0,13,0,1,1,01,01,00,4712,00,7,00,0,0,0,2298|6834| [K 7777.-1]&[E]_F,F_Q_B,#1_UC, ;Address paging ram
|2298|6835| SPEC SEL/PAGE TABLE ENTRY,
|2298|6836| CALL [MEM WRITE 1]
|2298|6837|.IF/FAST
000,000,0,14,10,0,00,0,00,0,0,00,14,00,00,00,0,20,1,1,0,03,67,00,1420,00,7,00,0,0,0,2299|6838| SET LOCAL,
|2299|6839| IF [NOT TRAP] THEN [IFETCH]
|2299|6840| GOTO [TRAP]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,03,01,00,4130,00,7,00,0,0,0,2300|6841|.ENDIF/FAST
|2300|6842|.IFNOT/FAST
|2300|6843| GOTO [TO NOWHERE]
|2300|6844|.ENDIF/FAST
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,2413,00,7,00,0,0,0,2301|6845|TO MEM PXCT:
|2301|6846| CALL [PXCT STORE 200] ;Store data
|2301|6847| GOTOP [TO NOWHERE]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,13,01,00,4127,00,7,00,0,0,0,2302|6848|
|2302|6849|;Store 2 words to memory
000,000,0,04,06,1,56,0,44,0,0,00,00,00,00,00,0,20,1,1,1,03,46,00,4404,00,7,00,0,0,0,2303|6850|D TO MEM:
|2303|6851| [MEM-OP]_[MB], ;Put date in right reg
|2303|6852| IF [PXCT] THEN [D TO MEM PXCT]
000,000,0,07,14,0,67,0,40,0,0,00,00,00,00,77,0,13,0,1,1,01,01,00,4712,00,7,00,0,0,0,2304|6853| [K 7777.-1]&[E]_F,F_Q_B,#1_UC, ;Address paging ram
|2304|6854| SPEC SEL/PAGE TABLE ENTRY,
|2304|6855| CALL [MEM WRITE 1]
000,000,0,04,06,1,13,0,44,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,4710,00,7,00,0,0,0,2305|6856| [MEM-OP+1]_[MB], ;copy rest of data to memory
|2305|6857| CALL [WRITE NEXT]
|2305|6858|.IF/FAST
000,000,0,14,10,0,00,0,00,0,0,00,14,00,00,00,0,20,1,1,0,03,67,00,1420,00,7,00,0,0,0,2306|6859| SET LOCAL,
|2306|6860| IF [NOT TRAP] THEN [IFETCH]
|2306|6861| GOTO [TRAP]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,03,01,00,4130,00,7,00,0,0,0,2307|6862|.ENDIF/FAST
|2307|6863|.IFNOT/FAST
|2307|6864| GOTO [TO NOWHERE]
|2307|6865|.ENDIF/FAST
|2307|6866|
000,000,0,04,10,1,00,0,62,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0200,00,7,01,0,0,0,2308|6867|D TO MEM PXCT:
|2308|6868| J[0200]_[PXCT RH]
|2308|6869| CALL [SET PXCT CTXT]
000,000,0,07,14,0,67,0,40,0,0,00,00,00,00,77,0,13,0,1,1,01,01,00,4712,00,7,00,0,0,0,2310|6870| [K 7777.-1]&[E]_F,F_Q_B, #1_UC, ;Address paging ram
|2310|6871| SPEC SEL/PAGE TABLE ENTRY,
|2310|6872| CALL [MEM WRITE 1]
000,000,0,04,06,1,13,0,44,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,4710,00,7,00,0,0,0,2311|6873| [MEM-OP+1]_[MB], ;Copy rest of data to memory
|2311|6874| CALL [WRITE NEXT]
|2311|6875| CALL [SET CURRENT CTXT]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,2424,00,7,00,0,0,0,2312|6876| GOTOP [TO NOWHERE]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,13,01,00,4127,00,7,00,0,0,0,2313|6877|
|2313|6878|;Here to store 4 words in ACs
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,27,0,20,1,1,0,16,00,00,0000,00,7,00,0,0,0,2314|6879|Q TO AC.0:
|2314|6880| SEL AC+[0]
000,000,0,14,14,0,77,0,54,0,0,00,00,00,00,27,0,20,1,1,1,16,00,01,0000,00,7,04,0,0,0,2315|6881| [MEM-OP]_RAMFILE,
|2315|6882| SEL AC+[1]
000,000,0,14,14,0,77,0,13,0,0,00,00,00,00,27,0,20,1,1,1,16,00,02,0000,00,7,04,0,0,0,2316|6883| [MEM-OP+1]_RAMFILE,
|2316|6884| SEL AC+[2]
000,000,0,14,14,0,77,0,50,0,0,00,00,00,00,27,0,20,1,1,1,16,00,03,0000,00,7,04,0,0,0,2317|6885| [AC-OP]_RAMFILE,
|2317|6886| SEL AC+[3]
000,000,0,14,14,0,77,0,07,0,0,00,14,00,00,00,0,20,1,1,1,13,67,00,1420,00,7,04,0,0,0,2318|6887| [AC-OP+1]_RAMFILE,
|2318|6888| SET LOCAL,
|2318|6889| IF [NOT TRAP] THENP [IFETCH]
|2318|6890| GOTOP [TRAP]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,13,01,00,4130,00,7,00,0,0,0,2319|6891|
|2319|6892|;Here to clear page table
000,000,0,04,10,1,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,14,00,00,0777,00,7,01,0,0,0,2320|6893|PAGE TABLE CLEAR:
|2320|6894| J[511.]_CTR, ;Want to clear 512 entries
|2320|6895| J[PAGE TABLE-1]_[W1]
000,000,0,04,06,1,02,0,00,0,1,00,00,00,00,03,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,2321|6896|CLR RAM:
|2321|6897| [W1]+1_[W1],Y_RAMFILE ADR ;Address next page table entry
000,000,0,14,10,1,00,0,00,0,0,00,00,00,00,00,0,20,1,1,1,11,00,00,4421,00,7,04,0,0,0,2322|6898| ZERO_Y,ALU_RAMFILE,
|2322|6899| LOOP [CLR RAM]
|2322|6900| RETURN
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,12,01,00,0000,00,7,00,0,0,0,2323|6901|
|2323|6902|
|2323|6903|.TOC 2, "TOPS20 Page Refill"
|2323|6904|;TOPS20 page refill logic
|2323|6905|;Call : x&[K 7777.-1]_[E], ;Virtual adr to do page refill for
|2323|6906|; SPEC SEL/PAGE TABLE ENTRY ;Set section flags
|2323|6907|; #1_UC,CALL [PAGE W REFIL] ;To do refill for a write reference
|2323|6908|; O=UC,CALL [PAGE R REFIL] ;To do refill for a read reference
|2323|6909|;
|2323|6910|;flag usage:
|2323|6911|; uc = T
|2323|6912|; uz = section pointer
|2323|6913|;
|2323|6914|;reg usage:
|2323|6915|; W1 = Virtual section number
|2323|6916|; W3 = AND of all section and page pointers (for W)
|2323|6917|
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,03,0,13,0,1,0,16,00,00,0441,00,7,01,0,0,0,2324|6918|PAGE W REFIL:
|2324|6919| J[MB REFIL]_RAMFILE ADR,#1_UC ;Address location to save MB
000,000,0,14,14,0,77,0,44,0,0,00,00,00,00,00,0,20,1,1,1,03,01,00,4426,00,7,04,0,0,0,2325|6920| [MB]_RAMFILE, ;Save MB
|2325|6921| GOTO [PR 1]
|2325|6922|
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,03,45,00,4526,00,7,00,0,0,0,2326|6923|PAGE R REFIL:
|2326|6924| ; #0_UC
|2326|6925|PR 1:
|2326|6926|.IF/FT20PAG
|2326|6927|.IF/FT10PAG
|2326|6928| IF [TOPS10] THEN [T10PR]
|2326|6929|.ENDIF/FT10PAG
000,000,0,04,10,0,42,2,33,0,0,00,00,00,00,00,0,20,1,1,0,13,25,00,4751,00,7,07,0,0,0,2327|6930| SWAP [E]_[PMA], ;Put section number in RH
|2327|6931| IF [ILLEGAL SECTION] THENP [PF X27]
000,000,0,04,14,0,66,0,33,0,0,00,00,00,00,00,0,20,1,1,1,03,37,00,4432,00,7,00,0,0,0,2328|6932| [K 77]&[PMA]_B, ;Strip LH
|2328|6933| IF [EXEC] THEN [PR 2]
000,000,0,04,03,0,23,0,33,0,0,00,00,00,00,00,0,20,1,1,1,03,01,00,4433,00,7,00,0,0,0,2329|6934| [UPT]+[PMA]_B,GOTO [PR 3] ;UPT + section # to PMA
000,000,0,04,03,0,17,0,33,0,0,00,00,00,00,00,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,2330|6935|PR 2: [EPT]+[PMA]_B ;EPT + section # to PMA
000,000,0,04,10,1,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0540,00,7,01,0,0,0,2331|6936|PR 3: J[ESECT]_[W1] ;Get offset for section pointers
000,000,0,04,06,1,47,0,10,0,0,00,00,00,00,00,0,10,0,1,1,16,00,00,0000,00,7,00,0,0,0,2332|6937| [BIT4]_[W3],#0_UZ ;W bit(Mask for AND of pointers)
000,000,0,07,03,0,02,0,33,0,0,00,00,05,00,00,0,20,1,1,1,01,01,00,4463,00,1,02,0,0,0,2333|6938| [W1]+[PMA]_F,F_Q_B, ;EPT(UPT)+sect+ESECT
|2333|6939| MEM START READ,
|2333|6940| CALL [PTR EVAL] ; Get page adr from section table
000,000,0,04,06,1,46,0,04,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,4507,00,7,00,0,0,0,2334|6941| [MB]_[W2], ;Save page number
|2334|6942| CALL [CST UPDATE] ;Update CST for page table
000,000,1,11,06,1,42,0,00,0,0,00,00,11,00,00,0,20,1,1,1,04,01,00,0003,00,7,00,0,0,0,2335|6943| #2*[E]_[W1],PUSH J[3]_CTR ;Copy virtual address to
000,000,1,11,03,0,02,0,00,0,0,00,00,11,00,00,0,20,1,1,1,10,00,00,0000,00,7,00,0,0,0,2336|6944| #4*[W1]_B,RFCT ;Convert to page number
|2336|6945| SWAP [W1]_[PMA] ;Right justifty page number
000,000,0,04,10,0,02,2,33,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0000,00,7,07,0,0,0,2337|6946| [K 777]&[PMA]_B ;Make in section page number
000,000,0,04,03,0,16,0,33,0,0,00,00,05,00,00,0,20,1,1,1,01,01,00,4463,00,1,02,0,0,0,2339|6947| [W4]+[PMA]_B,MEM START READ, ;Address page table entry
|2339|6948| CALL [PTR EVAL] ; and fetch pointer
000,000,0,04,06,1,46,0,04,0,0,00,00,00,00,00,0,11,0,1,1,01,01,00,4507,00,7,00,0,0,0,2340|6949| [MB]_[W2],#1_UZ, ;Update M
|2340|6950| CALL [CST UPDATE] ; Update CST for page
|2340|6951| J[1]_[W1] ;Mask for M bit
000,000,0,14,14,0,46,0,00,0,0,00,00,00,00,00,0,20,1,0,1,16,00,00,0000,00,7,00,0,0,0,2342|6952| [MB]&[W1]_Y,IX_MX ;Latch M as #0_MZ
000,000,0,06,03,0,12,0,10,0,0,00,00,00,00,00,0,44,1,1,0,03,02,00,4451,00,7,00,0,0,0,2343|6953| #2*[W3]_Q, ;Make a bit 4 if writable
|2343|6954| IF CT [MZ] THEN [PR 6]
|2343|6955| Q.OR.[W3]_[W3] ;Add M bit if W
000,000,0,06,17,0,12,0,14,0,0,00,00,00,00,03,0,20,1,1,0,16,00,00,0102,00,7,01,0,0,0,2345|6956|PR 6: J[BIT2]_RAMFILE ADR, ;Bit for valid mapping
|2345|6957| [W3].OR.[W4]_Q ;Add W bit
|2345|6958| RAMFILE_[W1] ;Get valid bit from ramfile
000,000,0,04,17,1,02,0,44,0,0,00,00,00,00,00,0,20,1,1,1,01,36,00,5012,00,7,00,0,0,0,2347|6959| Q.OR.[W1]_[MB], ;Add valid bit to paging ram word
|2347|6960| IF [USER] CALL [B0!MB]
000,000,0,14,06,1,42,0,00,0,0,00,00,00,00,77,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,2348|6961| [E]_Y, ;Address paging ram location
|2348|6962| SPEC SEL/PAGE TABLE ENTRY
|2348|6963|.IF/DEBUGPF
|2348|6964| JS[01776]_[W2]
000,000,0,01,10,1,00,0,04,0,0,00,00,05,00,00,0,20,1,1,0,16,00,00,1776,00,7,01,0,0,0,2349|6965| ROR [W2]_[W2]
000,000,0,14,14,0,46,0,04,0,0,00,00,00,00,00,0,64,1,1,1,03,03,00,4755,00,7,00,0,0,0,2351|6966| [MB]&[W2]_Y,
|2351|6967| IF NOT CT [IZ] THEN [HALT PG]
|2351|6968|.ENDIF/DEBUGPF
000,000,0,04,06,1,46,0,00,0,0,00,00,00,00,00,0,32,1,1,1,12,03,00,0000,00,7,04,0,0,0,2352|6969| [MB]_[W1],ALU_RAMFILE, ;Fill paging ram
|2352|6970| IF NOT CT [UC] RETURN ; If read refill we are done
|2352|6971| J[MB REFIL]_RAMFILE ADR
000,000,0,04,10,0,00,0,44,0,0,00,00,00,00,00,0,20,1,1,0,12,01,00,0000,00,7,04,0,0,0,2354|6972| RAMFILE_[MB],
|2354|6973| RETURN
|2354|6974|
|2354|6975|;Here to evaluate a section pointer or map pointer
|2354|6976|; call: x_Q_[PMA], ;Physical address of 1st pointer
|2354|6977|; MEM START READ,
|2354|6978|; CALL [PTR EVAL]
|2354|6979|; Returns
|2354|6980|; accumulates W in W3
|2354|6981|; page number in MB (maybe also other junk)
|2354|6982|; address in W4
|2354|6983|
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,4573,00,0,00,0,0,0,2355|6984|PTR EVAL:
|2355|6985| MEM HOLD, ;Get pointer from memory
|2355|6986| CALL [UNMAPPED READ]
|2355|6987| [MB]&[W3]_B ;Accumulate W
000,000,1,11,06,1,46,0,14,0,0,00,00,11,00,00,0,20,1,0,1,16,00,00,0000,00,7,00,0,0,0,2357|6988| #2*[MB]_[W4],IX_MX ;latch bitO as MN
000,000,1,11,06,1,16,0,14,0,0,00,00,11,00,00,0,56,1,0,1,03,02,00,4744,00,7,00,0,0,0,2358|6989| #2*[W4]_[W4], ;Copy pointer to W4 and shift it
|2358|6990| IF CT [MN IX_MX] THEN [PF X0] ; for decode on bits 0,1,2
000,000,1,11,06,1,16,0,14,0,0,00,00,11,00,00,0,56,1,0,1,03,03,00,4500,00,7,00,0,0,0,2359|6991| #2*[W4]_[W4],
|2359|6992| IF NOT CT [MN IX_MX] THEN [PTE 7] ;Branch if bits OOx
|2359|6993|
|2359|6994|;Here if bits 0-2 of section pointer are 0
000,000,0,06,11,0,76,0,44,0,0,00,00,00,00,00,0,56,1,1,0,03,03,00,4475,00,7,00,0,0,0,2360|6995| [K -1.0]BAR&[MB]_Q, ;Get SPT index
|2360|6996| IF NOT CT [MN] THEN [PTE 1] ;branch for 010
|2360|6997|
|2360|6998|;Here if bits 0-2 of section pointer are 011 = indirect pointer
|2360|6999| SWAP [MB]_[W1] ;Put offset in RH
000,000,0,04,14,0,72,0,00,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,4475,00,7,00,0,0,0,2362|7000| [K 777]&[W1]_B, ;Mask off extra bits
|2362|7001| CALL [PTE 1] ;Get table address from SPT
|2362|7002| [W4]_[PMA] ;Address of indirect table
000,000,0,04,03,0,02,0,33,0,0,00,00,05,00,00,0,20,1,1,1,03,01,00,4463,00,1,02,0,0,0,2364|7003| [W1]+[PMA]_B,MEM START READ,
|2364|7004| GOTO [PTR EVAL]
|2364|7005|
|2364|7006|;Here if bits 0-2 of section poin~er are 010 = shared pointer
000,000,0,07,03,1,27,0,33,0,0,00,00,05,00,00,0,20,1,1,1,16,00,00,0000,00,1,02,0,0,0,2365|7007|PTE 1: Q+[SPT]_F,F_Q_[PMA], ;Get SPT entry for page map
|2365|7008| MEM START READ
|2365|7009| CALL [UNMAPPED READ]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,4573,00,7,00,0,0,0,2366|7010| ;This word is not included in the W accumulation
000,000,1,11,06,1,46,0,14,0,0,00,00,11,00,00,0,01,1,0,1,01,01,00,4505,00,7,00,0,0,0,2367|7011| #2*[MB]_[W4],#1_MX, ;Copy page address to WJt
|2367|7012| CALL [#4*W4_B]
|2367|7013|
|2367|7014|;Here if bits 0-2 of pointer are OOx
000,000,1,11,03,0,16,0,14,0,0,00,00,11,00,00,0,56,1,1,1,03,03,00,4744,00,7,00,0,0,0,2368|7015|PTE 7: #4*[W4]_B,
|2368|7016| IF NOT CT [MN] THEN [PF X0]
|2368|7017|
|2368|7018|;Here if bits 0-2 of pointer are 001 = immediate pointer
|2368|7019|
000,000,0,04,10,0,66,2,00,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0000,00,7,07,0,0,0,2369|7020|PTE 8: SWAP [K 77]_[W1] ;Mask for storage medium
000,000,0,14,14,0,46,0,00,0,0,00,00,00,00,00,0,20,1,0,1,16,00,00,0000,00,7,00,0,0,0,2370|7021| [MB]&[W1]_Y,IX_MX ;See if in core or else where
000,000,0,04,06,1,42,0,15,0,0,00,00,00,00,00,0,44,1,1,1,03,03,00,4744,00,7,00,0,0,0,2371|7022| [E]_[W4 LH], ;Add virtual section
|2371|7023| IF NOT CT [MZ] THEN [PF X0]
|2371|7024| #4*[W4]_B ;Shift page number to make adr
000,000,1,11,03,0,16,0,14,0,0,00,00,11,00,00,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,2373|7025|#4*W4_B: #4*[W4]_B
|2373|7026| RETURN
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,12,01,00,0000,00,7,00,0,0,0,2374|7027|
|2374|7028|;Here to update a CST entry
|2374|7029|; Call: x_[MB] ;Physica1 page number for update
|2374|7030|; Call with UC if write reference
|2374|7031|; Call with UZ if want M updated
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,03,0,20,1,1,0,16,00,00,0571,00,7,01,0,0,0,2375|7032|CST UPDATE:
|2375|7033| J[CST]_RAMFILE ADR
|2375|7034| J[07777]_[PMA]
000,000,1,11,14,0,77,0,33,0,0,00,00,15,00,00,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,2377|7035| [K -1]&[PMA]_F,LLS F_B, ;leave 17777 in PMA
|2377|7036| #1_SIO0 #1_QIO0
000,000,0,07,14,0,46,0,33,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0000,00,7,04,0,0,0,2378|7037| [MB]&[PMA]_F, ;Leave only page number in Q
|2378|7038| F_Q RAMFILE_[PMA] ; Get CST adr in PMA
000,000,0,04,03,1,33,0,33,0,0,00,00,05,00,00,0,20,1,1,1,01,01,00,4573,00,1,02,0,0,0,2379|7039| Q+[PMA]_[PMA],MEM START READ, ;Get CST entry for page map
|2379|7040| CALL [UNMAPPED READ]
|2379|7041| J[CSTMASK]_RAMFILE ADR
000,000,0,14,11,0,67,0,44,0,0,00,00,00,00,00,0,20,1,0,1,16,00,00,0000,00,7,00,0,0,0,2381|7042| [K 7777.-1]BAR&[MB]_Y,IX_MX ;Check age field
000,000,0,07,06,1,46,0,44,0,0,00,00,00,00,00,0,44,1,1,0,03,02,00,4742,00,7,04,0,0,0,2382|7043| [MB]_Q RAMFILE_[MB], ;Get CSTmask register
|2382|7044| IF CT [MZ] THEN [AGE PF] ; If age trap page fail
000,000,0,06,14,1,46,0,00,0,0,00,00,00,00,03,0,20,1,1,0,16,00,00,0573,00,7,01,0,0,0,2383|7045| Q&[MB]_Q, ;Mask off bits
|2383|7046| J[CSTDATA]_RAMFILE ADR
|2383|7047| RAMFILE_[MB]
000,000,0,07,17,1,46,0,44,0,0,00,00,00,00,00,0,32,1,1,1,03,03,00,4525,00,7,00,0,0,0,2385|7048| Q.OR.[MB]_F,F_Q_[MB], ; ;Add new bits
|2385|7049| IF NOT CT [UC] THEN [CSTUD8] ;B ranch if read refill
000,000,0,14,06,1,12,0,00,0,0,00,00,00,00,00,0,24,1,0,1,03,03,00,4525,00,7,00,0,0,0,2386|7050| [W3]_Y, ;Test W bit
|2386|7051| IF NOT CT [UZ IX_MX] THEN [CSTUD8]
|2386|7052| J[1]_[MB] ;Get M bit for CST entry
000,000,0,04,17,1,46,0,44,0,0,00,00,00,00,00,0,44,1,1,1,03,02,00,4744,00,7,00,0,0,0,2388|7053| Q.OR.[MB]_[MB], ;Set M bit
|2388|7054| IF CT [MZ] THEN [PF X0] ; If not W, page fail
000,000,0,04,06,1,33,0,33,0,0,00,00,05,00,00,0,20,1,1,1,03,01,00,4704,00,2,02,0,0,0,2389|7055|CSTUD8: [PMA]_[PMA],MEM START WRITE, ;Write updated CST entry
|2389|7056| GOTO [UNMAPPED WRITE]
|2389|7057|.ENDIF/FT20PAG
|2389|7058|
|2389|7059|
|2389|7060|.TOC 2, "TOPS10 Page Refill"
|2389|7061|
|2389|7062|.IF/FT10PAG
000,000,0,14,14,0,76,0,40,0,0,00,00,00,00,00,0,64,1,1,1,13,03,00,4751,00,7,00,0,0,0,2390|7063|T10PR: [K -1.0]&[E]_Y, ;Check for legal section
|2390|7064| IF NOT CT [IZ] THENP [PF X27]
000,000,0,06,11,0,72,0,40,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0000,00,7,00,0,0,0,2391|7065| [K 777]BAR&[E]_F,F_Q ;Strip onpage portion
000,000,0,04,14,1,77,0,00,0,0,00,00,00,00,00,0,20,1,1,1,04,01,00,0003,00,7,00,0,0,0,2392|7066| Q_[W1],PUSH J[3]_CTR ;Shift E left 8 places
000,000,1,11,03,0,02,0,00,0,0,00,00,11,00,00,0,20,1,1,1,10,00,00,0000,00,7,00,0,0,0,2393|7067| #4*[W1]_B,RFCT
000,000,0,04,10,0,02,2,33,0,0,00,00,00,00,00,0,20,1,1,0,03,36,00,4545,00,7,07,0,0,0,2394|7068| SWAP [W1]_[PMA], ;Sign bit = E bit 26
|2394|7069| IF [USER] THEN [T1PR14] ; Page #/2 in bits 28-35
000,000,0,14,10,0,00,0,40,0,0,00,00,00,00,00,0,20,1,1,0,03,56,00,4543,00,7,00,0,0,0,2395|7070| B SEL/E,
|2395|7071| IF [B BIT 18] THEN [T1PR13]
|2395|7072| ROL [PMA]_[W2] ;Page # goes to bits 27-35
000,000,1,11,06,1,33,0,04,0,0,00,00,51,00,00,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,2396|7073| J[0340]_[W1]
000,000,0,14,02,0,06,0,00,0,0,00,00,00,00,00,0,76,1,1,1,03,02,00,4541,00,7,00,0,0,0,2398|7074| [W2]-[W1]_Y, ;Check for up to 34OOOO
|2398|7075| IF CT [IN] THEN [T1PR12]
|2398|7076| J[0220]_[W1] ;Offset for 340000 in UPT
000,000,0,04,03,0,02,0,33,0,0,00,00,00,00,00,0,20,1,1,1,03,01,00,4545,00,7,00,0,0,0,2400|7077| [W1]+[PMA]_B,
|2400|7078| GOTO [T1PR14]
000,000,0,04,10,1,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0600,00,7,01,0,0,0,2401|7079|T1PR12: J[0600]_[W1] ;Offset for 000000 in exec
|2401|7080| [W1]+[PMA]_B
000,000,0,04,03,0,17,0,33,0,0,00,00,05,00,00,0,20,1,1,1,01,01,00,4573,00,1,02,0,0,0,2403|7081|T1PR13: [EPT]+[PMA]_B,MEM START READ, ;Offset for 4OOOOO in EPT
|2403|7082| CALL [UNMAPPED READ] ;Get word from EPT
|2403|7083| GOTO [T1PR15]
000,000,0,04,03,0,23,0,33,0,0,00,00,05,00,00,0,20,1,1,1,01,01,00,4573,00,1,02,0,0,0,2405|7084|T1PR14: [UPT]+[PMA]_B,MEM START READ, ;Get word from UPT
|2405|7085| CALL [UNMAPPED READ]
000,000,0,14,06,1,33,0,00,0,0,00,00,00,00,00,0,20,1,0,1,16,00,00,0000,00,7,00,0,0,0,2406|7086|T1PR15: [PMA]_Y,IX_MX ;Check for odd or even
|2406|7087| IF NOT CT [MN] CALL [SWAP MB_MB]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,56,1,1,0,01,03,00,1624,00,7,00,0,0,0,2407|7088| J[07777]_[W2] ;Want mask for physical page
000,000,1,11,06,1,06,0,04,0,0,00,00,15,00,00,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,2409|7089| [W2]_F,LLS F_B,B SEL/W2, ;Put 17777 in W2
|2409|7090| #1_SIO0 #1_QIO0
000,000,0,04,10,1,00,0,00,0,0,00,00,00,00,00,0,20,1,1,1,03,37,00,4555,00,7,00,0,0,0,2410|7091| ZERO_[W1], ;Build paging ram word here
|2410|7092| IF [EXEC] THEN [T1PR24]
|2410|7093| J[0002]_[W1] ;Bit for user
000,000,0,04,10,1,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0002,00,7,01,0,0,0,2411|7094| SWAP [W1]_[W1]
000,000,0,04,06,1,46,0,02,0,0,00,00,00,00,00,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,2413|7095|T1PR24: [MB]_[W1 RH] ;Add APWS
|2413|7096| #2*[W1]_[W1] ;Put A in bit17
000,000,1,11,06,1,02,0,00,0,0,00,00,11,00,00,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,2414|7097| #2*[W1]_[W1 RH] ;Put W in bit18(discard P)
000,000,1,11,06,1,02,0,02,0,0,00,00,11,00,00,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,2415|7098| #4*[W1]_B ;Put S in bit17
000,000,1,11,03,0,02,0,00,0,0,00,00,11,00,00,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,2416|7099| [MB]_[W1 RH] ;Add page #
000,000,0,04,14,0,06,0,02,0,0,00,00,00,00,00,0,20,1,1,1,04,01,00,0001,00,7,00,0,0,0,2418|7100| [W2]&[W1 RH]_B,PUSH J[1]_CTR ;Clear extra bits
000,000,0,11,03,0,02,0,01,0,0,00,00,00,00,00,0,20,1,1,1,10,00,00,0000,00,7,00,0,0,0,2419|7101| [W1]+[W1 LH]_F,LLS F_B,RFCT ;Put S in bit 13
000,000,0,14,06,1,42,0,00,0,0,00,00,00,00,77,0,20,1,1,1,16,00,00,0000,00,7,00,0,0,0,2420|7102| [E]_Y,SPEC SEL/PAGE TABLE ENTRY ;Address paging ram
000,000,1,11,06,1,02,0,00,0,0,00,00,11,00,00,0,20,1,1,1,04,01,00,0003,00,7,00,0,0,0,2421|7103| #2*[W1]_[W1],PUSH J[3]_CTR ;Want to shift left 9
000,000,1,11,03,0,02,0,00,0,0,00,00,11,00,00,0,20,1,0,1,10,00,00,0000,00,7,00,0,0,0,2422|7104| #4*[W1]_B,IX_MX,RFCT
000,000,0,14,06,1,02,0,00,0,0,00,00,00,00,00,0,32,1,1,1,12,03,00,0000,00,7,04,0,0,0,2423|7105| [W1]_Y,ALU_RAMFILE, ;Write new paging ram word
|2423|7106| IF NOT CT [UC] RETURN
|2423|7107| J[MB REFIL]_RAMFILE ADR ;Address where we left MB
000,000,0,04,10,0,00,0,44,0,0,00,00,00,00,00,0,20,1,1,0,12,01,00,0000,00,7,04,0,0,0,2425|7108| RAMFILE_[MB],RETURN ;Restore MB
|2425|7109|.ENDIF/FT10PAG
|2425|7110|
|2425|7111|.TOC 2, "Unmapped Memory Read"
|2425|7112|
|2425|7113|; CALL: x_[PMA],MEM START READ
|2425|7114|; returns with data in MB
000,000,0,04,06,1,33,0,33,0,0,00,00,05,00,00,0,20,1,1,1,16,00,00,0000,00,1,02,0,0,0,2426|7115|UNMAPPED READ 0:
|2426|7116| [PMA]_[PMA],MEM START READ
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,01,21,00,4154,00,0,00,0,0,0,2427|7117|UNMAPPED READ:
|2427|7118| MEM HOLD,
|2427|7119| CHECK INTERRUPTS
|2427|7120| MEM_[MB] ;Get contents of memory
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,12,61,00,0000,00,0,00,0,0,0,2429|7121| MEM HOLD,
|2429|7122| IF [NO BUS ERROR] RETURN
|2429|7123| ;GOTO [MEM ERR]
|2429|7124|
|2429|7125|;Here on a mem fault
|2429|7126|;If soft (ECC correctable error) will save status (even if already
|2429|7127|; latched) set APR flag, SPEC SEL/IW, and return.
|2429|7128|; Will clobber W1&W2
|2429|7129|;If RAMFILE_[ME RCOVR] is nonzero will go there with status in W1
|2429|7130|;Else will build a page fail code and go to PF XX
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,03,0,20,1,1,0,16,00,00,0537,00,7,01,0,0,0,2430|7131|MEM ERR:
|2430|7132| J[ME W1]_RAMFILE ADR ;Have to save W1
|2430|7133| [W1]_RAMFILE
000,000,0,14,14,0,77,0,00,0,0,00,00,00,00,00,0,20,1,1,1,16,00,00,0000,00,7,04,0,0,0,2431|7134| J[ME W2]_RAMFILE ADR ;Have to save W2
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,03,0,20,1,1,0,16,00,00,0540,00,7,01,0,0,0,2432|7135| [W2]_RAMFILE
000,000,0,04,06,1,33,0,04,0,0,00,00,00,00,00,0,20,1,1,1,16,00,00,0000,00,0,00,0,0,0,2434|7136| [PMA]_[W2],MEM HOLD ;Copy offending address
000,000,1,11,03,0,06,0,04,0,0,00,00,11,00,00,0,20,1,1,1,16,00,00,0000,00,0,00,0,0,0,2435|7137| #4*[W2]_B,MEM HOLD ;Put board number in lh
000,000,0,04,10,0,06,2,04,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0000,00,0,07,0,0,0,2436|7138| SWAP [W2]_[W2],MEM HOLD ;Put board number in rh
000,000,0,06,14,0,66,0,04,0,0,00,00,00,00,03,0,20,1,1,0,16,00,00,0124,00,0,01,0,0,0,2437|7139| [K 77]&[W2]_Q,MEM HOLD,
|2437|7140| J[BIT20]_RAMFILE ADR
000,000,0,04,10,0,00,0,04,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0000,00,0,04,0,0,0,2438|7141| RAMFILE_[W2],MEM HOLD ;Get 100000
000,000,0,06,03,1,06,0,00,0,0,00,00,05,00,00,0,20,1,1,1,16,00,00,0000,00,3,02,0,0,0,2439|7142| Q+[W2]_F,F_Q_Y,START IO READ ;Address memory status reg
000,000,0,04,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0000,00,5,02,0,0,0,2440|7143| IO TRANSFER,XFER MEM, ;Get status from memory
|2440|7144| Y_[W1],ALU_Y/NO,
|2440|7145| M STATUS ENAB/NO ;do not change error flags
000,000,0,04,06,1,57,0,01,0,0,00,00,00,00,00,0,20,1,1,1,03,71,00,4614,00,7,00,0,0,0,2441|7146| [BIT17]_[W1 LH], ;Check for NXM
|2441|7147| IF [NOT MEM EXISTS] THEN [MEM NXM]
000,000,0,04,03,0,57,0,00,0,0,00,00,00,00,00,0,20,1,1,1,03,33,00,4616,00,7,00,0,0,0,2442|7148| [BIT17]+[W1]_B, ;1st check Bus fault line
|2442|7149| IF [MEM FAULT] THEN [MEM FAULT]
|2442|7150|
|2442|7151|;Here if we detected parity from bus
|2442|7152|.IF/FTCKBP
000,000,0,04,03,0,57,0,00,0,0,00,00,00,00,00,0,20,1,1,1,03,01,00,4640,00,7,00,0,0,0,2443|7153| [BIT17]+[W1]_B, ;Must be a bus parity error
|2443|7154| GOTO [MER05]
|2443|7155|.ENDIF/FTCKBP
|2443|7156|.IFNOT/FTCKBP
|2443|7157| J[ME W1]_RAMFILE ADR ;Where we saved W1
|2443|7158| RAMFILE_[W1]
|2443|7159| J[ME W2]_RAMFILE ADR ;Where we saved W2
|2443|7160| RAMFILE_[W2]
|2443|7161| [MB]_[MB],SPEC SEL/IW, ;In case part of efa calc
|2443|7162| RETURN
|2443|7163|.ENDIF/FTCKBP
|2443|7164|
|2443|7165|;Here because we won a NXM
000,000,0,04,10,1,00,0,04,0,0,00,00,00,00,03,0,20,1,1,0,16,00,00,0155,00,7,01,0,0,0,2444|7166|MEM NXM:
|2444|7167| J[NXM STS]_[W2],Y_RAMFILE ADR ;Save status as "nxm"
|2444|7168| GOTO [MER10]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,03,01,00,4641,00,7,00,0,0,0,2445|7169|
|2445|7170|;Here when memory complains
000,000,0,04,10,1,00,0,04,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,6550,00,7,01,0,0,0,2446|7171|MEM FAULT:
|2446|7172|.IF/FTSMER
|2446|7173| J[06550]_[W2]
000,000,1,11,03,0,06,0,04,0,0,00,00,11,00,00,0,20,1,1,1,01,01,00,4656,00,7,00,0,0,0,2447|7174| #4*[W2]_B,CALL [#4*W2_B]
|2447|7175| [W1]&[W2]_Q ;Leave only bits we care about
000,000,0,06,14,0,02,0,04,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0000,00,7,00,0,0,0,2448|7176| J[04010]_[W2] ;Bits we expect
000,000,1,11,03,0,06,0,04,0,0,00,00,11,00,00,0,20,1,1,1,01,01,00,4656,00,7,00,0,0,0,2450|7177| #4*[W2]_B,CALL [#4*W2_B]
000,000,0,14,13,1,06,0,00,0,0,00,00,00,00,00,0,64,1,1,1,03,03,00,4640,00,7,00,0,0,0,2451|7178| Q.XOR.[W2]_F,F_Y,
|2451|7179| IF NOT CT [IZ] THEN [MER05]
|2451|7180| J[APR FLAGS]_RAMFILE ADR
000,000,0,07,06,1,66,0,04,0,1,00,00,00,00,00,0,20,1,1,0,16,00,00,0000,00,7,04,0,0,0,2453|7181| [K 77]+1_F,F_Q Y_[W2], ;Make 100 = SME flag
|2453|7182| RAMFILE_Y
000,000,0,07,17,1,06,0,04,0,0,00,00,00,00,00,0,20,1,1,1,16,00,00,0000,00,7,04,0,0,0,2454|7183| Q.OR.[W2]_F,F_Q_[W2],
|2454|7184| ALU_RAMFILE
|2454|7185| SWAP [W2]_[W2]
000,000,0,14,14,1,06,0,00,0,0,00,00,00,00,00,0,64,1,1,1,03,02,00,4631,00,7,00,0,0,0,2456|7186| Q&[W2]_Y,
|2456|7187| IF CT [IZ] THEN [MER04]
|2456|7188|;**** add code to make interrupt ****
000,000,0,04,10,1,00,0,04,0,0,00,00,00,00,03,0,20,1,1,0,16,00,00,0160,00,7,01,0,0,0,2457|7189|MER04: J[SME STS]_[W2],Y_RAMFILE ADR ;Save status as "soft"
|2457|7190| CALL [MESAV2] ;Save status and exit
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,4653,00,7,00,0,0,0,2458|7191| J[ME W1]_RAMFILE ADR
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,03,0,20,1,1,0,16,00,00,0537,00,7,01,0,0,0,2459|7192| RAMFILE_[W1]
000,000,0,04,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0000,00,7,04,0,0,0,2460|7193| J[ME W2]_RAMFILE ADR
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,03,0,20,1,1,0,16,00,00,0540,00,7,01,0,0,0,2461|7194| RAMFILE_[W2]
000,000,0,14,06,1,46,0,00,0,0,00,00,00,00,53,0,20,1,1,1,12,01,00,0000,00,7,00,0,0,0,2463|7195| [MB]_Y,SPEC SEL/IW,
|2463|7196| RETURN
|2463|7197|.ENDIF/FTSMER
000,000,0,04,10,1,00,0,04,0,0,00,00,00,00,03,0,20,1,1,0,15,01,00,0152,00,7,01,0,0,0,2464|7198|MER05: J[HME STS]_[W2],Y_RAMFILE ADR, ;Save status as "hard"
|2464|7199| POP
000,000,0,06,06,1,06,0,00,0,0,00,00,00,00,03,0,20,1,1,0,15,01,00,0150,00,7,01,0,0,0,2465|7200|MER10: J[ME RCOVR]_RAMFILE ADR, ;Check for recovery routine
|2465|7201| [W2]_Q,POP
000,000,0,04,10,0,00,0,04,0,0,00,00,00,00,00,0,20,1,1,0,15,01,00,0000,00,7,04,0,0,0,2466|7202| RAMFILE_[W2],POP ;Get recovery routine
000,000,0,14,06,1,06,0,00,0,0,00,00,00,00,00,0,64,1,1,1,03,03,00,0000,00,7,01,0,0,0,2467|7203| [W2]_Y,IF NOT CT [IZ] THEN Y ;If there is one do it
|2467|7204|.IFNOT/FTPFRMER
|2467|7205| J[PF RCOVR]_RAMFILE ADR ;Page fail recovery
|2467|7206| ZERO_Y,ALU_RAMFILE ;does not help here
|2467|7207|.ENDIF/FTPFRMER
000,000,0,04,14,1,77,0,04,0,0,00,00,00,00,03,0,20,1,1,1,01,01,00,4651,00,7,00,0,0,0,2468|7208| Q_[W2],Y_RAMFILE ADR,
|2468|7209| CALL [MERSAV] ;Save error status
000,000,0,04,13,0,57,0,00,0,0,00,00,00,00,00,0,20,1,1,0,15,01,00,3700,00,7,01,0,0,0,2469|7210| [BIT17].XOR.[W1]_F,POP,
|2469|7211| FJ[03700]_[W1] ;Code for NXM
000,000,0,14,14,0,76,0,00,0,0,00,00,00,00,00,0,64,1,1,1,13,02,00,4752,00,7,00,0,0,0,2470|7212| [K -1.0]&[W1]_Y,
|2470|7213| IF CT [IZ] THENP [PF XX]
|2470|7214| J[03600]_[W1] ;Code for mem err
000,000,0,04,10,1,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,3600,00,7,01,0,0,0,2471|7215| GOTOP [PF XX] ;Perform a page fail
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,13,01,00,4752,00,7,00,0,0,0,2472|7216|
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,0,0,16,00,00,0000,00,7,04,0,0,0,2473|7217|MERSAV: RAMFILE_Y,IX_MX ;See if already latched error
|2473|7218| IF NOT CT [MZ] RETURN ;Do not overwrite
000,000,0,14,14,0,77,0,00,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,4657,00,7,04,0,0,0,2475|7219|MESAV2: [W1]_RAMFILE, ;Save status
|2475|7220| CALL [W2+1_RFA]
000,000,0,14,14,0,77,0,33,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,4657,00,7,04,0,0,0,2476|7221| [PMA]_RAMFILE, ;Save address of losing location
|2476|7222| CALL [W2+1_RFA]
000,000,0,14,14,0,77,0,44,0,0,00,00,00,00,53,0,20,1,1,1,12,01,00,0000,00,7,04,0,0,0,2477|7223| [MB]_RAMFILE,SPEC SEL/IW,
|2477|7224| RETURN
|2477|7225|
000,000,1,11,03,0,06,0,04,0,0,00,00,11,00,00,0,20,1,1,1,12,01,00,0000,00,7,00,0,0,0,2478|7226|#4*W2_B: #4*[W2]_B,RETURN
|2478|7227|
000,000,0,04,06,1,06,0,04,0,1,00,00,00,00,03,0,20,1,1,1,12,01,00,0000,00,7,00,0,0,0,2479|7228|W2+1_RFA:
|2479|7229| [W2]+1_[W2],Y_RAMFILE ADR, ;Address next ramfile location
|2479|7230| RETURN
|2479|7231|
|2479|7232|.TOC 2, "Memory Read Routine"
|2479|7233|; CALL: x_Q_[E], ;Put address in E & Q
|2479|7234|; CLEAR LOCAL,SET LOCAL, ; Only one please
|2479|7235|; SPEC SEL/PAGE TABLE ENTRY, ; Address paging entry
|2479|7236|; CALL [MEMORY READ]
|2479|7237|; RETURNS with data in MB and with SPEC SEL/IW set
|2479|7238|; paging RAM word is in W1
|2479|7239|; clobbers W2-W4 (if page refill)
|2479|7240|
|2479|7241|;Here to fetch next virtual address
000,000,0,07,06,1,42,0,42,0,1,00,00,00,00,00,0,20,1,1,1,03,34,00,4662,00,7,00,0,0,0,2480|7242|READ NEXT:
|2480|7243| [E]+1_Q_[E RH],
|2480|7244| IF [LOCAL] THEN [MEM READ 0]
000,000,0,04,14,1,77,0,40,0,0,00,00,00,00,77,0,20,1,1,1,03,01,00,4663,00,7,00,0,0,0,2481|7245| Q_[E], ;Address to read
|2481|7246| SPEC SEL/PAGE TABLE ENTRY,
|2481|7247| GOTO [MEMORY READ]
|2481|7248|
000,000,0,07,14,0,67,0,40,0,0,00,00,00,00,77,0,20,1,1,1,03,01,00,4663,00,7,00,0,0,0,2482|7249|MEM READ 0:
|2482|7250| [K 7777.-1]&[E]_F,F_Q_B, ;Address to read
|2482|7251| SPEC SEL/PAGE TABLE ENTRY,
|2482|7252| GOTO [MEMORY READ]
|2482|7253|
000,000,0,07,14,1,72,0,00,0,0,00,00,00,00,00,0,12,0,0,0,03,72,00,4677,00,7,04,0,0,0,2483|7254|MEMORY READ:
|2483|7255| Q&[K 777]_F,RAMFILE_Y, ;Put page entry in W1
|2483|7256| #0_UC IX_MX,
|2483|7257| Y_[W1] F_Q, ;Put on page adr in Q
|2483|7258| IF [UNPAGED OR AC] THEN [M R 8]
|2483|7259|.IF/DEBUGPF
|2483|7260| JS[01776]_[W2]
000,000,0,01,10,1,00,0,04,0,0,00,00,05,00,00,0,20,1,1,0,16,00,00,1776,00,7,01,0,0,0,2484|7261| ROR [W2]_[W2]
000,000,0,14,14,0,02,0,04,0,0,00,00,00,00,00,0,64,1,1,1,03,03,00,4755,00,7,00,0,0,0,2486|7262| [W1]&[W2]_Y,
|2486|7263| IF NOT CT [IZ] THEN [HALT PG]
|2486|7264|.ENDIF/DEBUGPF
000,000,0,04,17,1,02,0,33,0,0,00,00,05,00,00,0,20,1,1,1,03,30,00,4673,00,1,02,0,0,0,2487|7265| Q.OR.[W1]_[PMA],MEM START READ,
|2487|7266| IF [CONTEXT MATCH] THEN [MEM READ 4]
000,000,0,04,14,0,67,0,40,0,0,00,00,00,00,00,0,12,0,1,1,01,01,00,4426,00,7,00,0,0,0,2488|7267| [K 7777.-1]&[E]_B,#0_UC, ;Mask address to 30 bits
|2488|7268| CALL [PAGE R REFIL]
|2488|7269| GOTO [MEM READ 0]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,03,01,00,4662,00,7,00,0,0,0,2489|7270|
000,000,0,04,06,1,42,0,33,0,0,00,00,05,00,00,0,20,1,1,1,16,00,00,0000,00,1,02,0,0,0,2490|7271|MEM READ 3:
|2490|7272| [E]_[PMA],MEM START READ ;Address location
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,01,21,00,4154,00,0,00,0,0,0,2491|7273|MEM READ 4:
|2491|7274| CHECK INTERRUPTS,
|2491|7275| MEM HOLD
000,000,0,04,10,0,00,0,44,0,0,00,00,00,00,53,0,20,1,0,0,16,00,00,0000,00,5,02,0,0,0,2492|7276| MEM_[MB],SPEC SEL/IW ;Read memory into MB & select IW
000,000,0,04,06,1,46,0,44,0,0,00,00,00,00,00,0,20,1,1,1,12,61,00,0000,00,0,00,0,0,0,2493|7277| [MB]_[MB],MEM HOLD,
|2493|7278| IF [NO BUS ERROR] RETURN
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,03,01,00,4576,00,0,00,0,0,0,2494|7279| MEM HOLD,GOTO [MEM ERR]
|2494|7280|
|2494|7281|;Here if reference is unpaged or ac
000,000,0,04,06,1,42,0,33,0,0,00,00,00,00,23,0,20,1,1,1,03,22,00,4672,00,7,00,0,0,0,2495|7282|M R 8: [E]_[PMA],SPEC SEL/VMA, ;Address register
|2495|7283| IF [NOT AC REF] THEN [MEM READ 3]
000,000,0,04,10,0,00,0,44,0,0,00,00,00,00,00,0,20,1,1,0,13,25,00,4751,00,7,04,0,0,0,2496|7284| RAMFILE_[MB], ;Read AC into MB & select IW
|2496|7285| IF [ILLEGAL SECTION] THENP [PF X27]
|2496|7286| CHECK INTERRUPTS
000,000,0,14,06,1,46,0,00,0,0,00,00,00,00,53,0,20,1,1,1,12,01,00,0000,00,7,00,0,0,0,2498|7287| [MB]_Y,SPEC SEL/IW,
|2498|7288| RETURN
|2498|7289|
|2498|7290|
|2498|7291|.TOC 2, "Unmapped Memory Write Routine"
|2498|7292|
|2498|7293|;CALL: x_[MB] ;Put data in KB
|2498|7294|; x_[PMA] ;Physical location to write into
|2498|7295|; CALL [UNMAPPED WRITE]
|2498|7296|
|2498|7297|;Here to write memory with contents of MB and then increment PMA
000,000,0,04,06,1,33,0,33,0,1,00,00,05,00,00,0,20,1,1,1,03,01,00,4705,00,2,02,0,0,0,2499|7298|UNMAPPED WRITE NEXT:
|2499|7299| [PMA]+1_[PMA],MEM START WRITE, ;Give memory address
|2499|7300| GOTO [UNMAPPED WRITE 2]
|2499|7301|
000,000,0,04,06,1,33,0,33,0,0,00,00,05,00,00,0,20,1,1,1,16,00,00,0000,00,2,02,0,0,0,2500|7302|UNMAPPED WRITE:
|2500|7303| [PMA]_[PMA], ;Give memory address to write
|2500|7304| MEM START WRITE
|2500|7305|
000,000,0,04,06,1,46,0,44,0,0,00,00,05,00,00,0,20,1,0,1,16,00,00,0000,00,5,02,0,0,0,2501|7306|UNMAPPED WRITE 2:
|2501|7307| [MB]_MEM ;Write data in memory
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,12,61,00,0000,00,0,00,0,0,0,2502|7308| MEM HOLD,
|2502|7309| IF [NO BUS ERROR] RETURN
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,03,01,00,4576,00,0,00,0,0,0,2503|7310| MEM HOLD,GOTO [MEM ERR]
|2503|7311|
|2503|7312|
|2503|7313|
|2503|7314|.TOC 2, "Memory Write Routine"
|2503|7315|
|2503|7316|;CALL: x_[E] ;Virtual adr
|2503|7317|; x_[MB] ;Put data in MB
|2503|7318|; CALL [MEMORY WRITE]
|2503|7319|; with GLOBAL/LOCAL flag set,
|2503|7320|; may clobber W1-W5
|2503|7321|
000,000,0,07,06,1,42,0,40,0,1,00,00,00,00,77,0,20,1,1,1,03,01,00,4712,00,7,00,0,0,0,2504|7322|WRITE NEXT:
|2504|7323| [E]+1_F,F_Q_[E],
|2504|7324| SPEC SEL/PAGE TABLE ENTRY,
|2504|7325| GOTO [MEM WRITE 1]
000,000,0,07,14,0,67,0,40,0,0,00,00,00,00,77,0,13,0,1,1,03,41,00,4737,00,7,00,0,0,0,2505|7326|MEMORY WRITE:
|2505|7327| [K 7777.-1]&[E]_F,F_Q_B,#1_UC, ;Address paging ram
|2505|7328| SPEC SEL/PAGE TABLE ENTRY,
|2505|7329| IF [NOT PAGED] THEN [M W 8]
|2505|7330|
000,000,0,04,14,1,72,0,00,0,0,00,00,00,00,00,0,13,0,0,0,03,72,00,4737,00,7,04,0,0,0,2506|7331|MEM WRITE 1:
|2506|7332| Q&[K 777]_Q RAMFILE_[W1], ;Get paging ram entry
|2506|7333| #1_UC IX_MX,
|2506|7334| IF [UNPAGED OR AC] THEN [M W 8]
|2506|7335|.IF/DEBUGPF
|2506|7336| JS[01776]_[W2]
000,000,0,01,10,1,00,0,04,0,0,00,00,05,00,00,0,20,1,1,0,16,00,00,1776,00,7,01,0,0,0,2507|7337| ROR [W2]_[W2]
000,000,0,14,14,0,02,0,04,0,0,00,00,00,00,00,0,64,1,1,1,03,03,00,4755,00,7,00,0,0,0,2509|7338| [W1]&[W2]_Y,
|2509|7339| IF NOT CT [IZ] THEN [HALT PG]
|2509|7340|.ENDIF/DEBUGPF
|2509|7341|.IF/FTADRB
000,000,0,06,14,1,67,0,00,0,0,00,00,00,00,03,0,20,1,1,0,16,00,00,0443,00,7,01,0,0,0,2510|7342| J[AB WR]_RAMFILE ADR, ;Get address to stop on
|2510|7343| Q&[K 7777.-1]_F,F_Q
|2510|7344| RAMFILE_[W2]
000,000,0,14,13,1,06,0,00,0,0,00,00,00,00,00,0,64,1,1,1,03,02,00,4724,00,7,00,0,0,0,2512|7345| Q.XOR.[W2]_F,F_Y,
|2512|7346| IF CT [IZ] THEN [M W 2]
|2512|7347| J[HALT CODE]_RAMFILE ADR
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,03,0,20,1,1,0,16,00,00,0151,00,7,01,0,0,0,2513|7348| J[HALT ADRBRK]_[W2]
000,000,0,14,14,0,77,0,04,0,0,00,40,00,00,00,0,20,1,1,1,16,00,00,0000,00,7,04,0,0,0,2515|7349| [W2]_RAMFILE,CLEAR RUN
|2515|7350|.ENDIF/FTADRB
000,000,0,04,17,1,02,0,33,0,0,00,00,05,00,00,0,20,1,1,1,03,30,00,4727,00,2,02,0,0,0,2516|7351|M W 2: Q.OR.[W1]_[PMA],
|2516|7352| MEM START WRITE,
|2516|7353| IF [CONTEXT MATCH] THEN [M W 3]
000,000,0,04,14,0,67,0,40,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,4424,00,7,00,0,0,0,2517|7354|M W 25: [K 7777.-1]&[E]_B, ;Mask address to 30 bits
|2517|7355| CALL [PAGE W REFIL]
|2517|7356| GOTO [MEMORY WRITE]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,03,01,00,4711,00,7,00,0,0,0,2518|7357|
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,03,50,00,4734,00,0,00,0,0,0,2519|7358|M W 3: B SEL/W1,MEM HOLD,
|2519|7359| IF [B BIT 3] THEN [M W 5] ;Check M bit is set
000,000,0,14,14,0,47,0,00,0,0,00,00,00,00,00,0,20,1,0,1,03,45,00,4732,00,7,00,0,0,0,2520|7360|M W XX:
|2520|7361|.IF/FT20PAG
|2520|7362| [BIT4]&[W1]_Y,IX_MX, ;Check W bit
|2520|7363| IF [TOPS10] THEN [M W PF]
|2520|7364| IF NOT CT [MZ] THEN [M W 25]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,44,1,1,0,03,03,00,4725,00,7,00,0,0,0,2521|7365|;***** clever code here could just call CST UPDATE
|2521|7366|.ENDIF/FT20PAG
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,03,01,00,4756,00,7,00,0,0,0,2522|7367|M W PF: GOTO [PAGE FAIL]
000,000,0,04,06,1,42,0,33,0,0,00,00,05,00,00,0,20,1,1,1,16,00,00,0000,00,2,02,0,0,0,2523|7368|M W 4: [E]_[PMA],MEM START WRITE
000,000,0,04,06,1,46,0,44,0,0,00,00,05,00,00,0,20,1,0,1,16,00,00,0000,00,5,02,0,0,0,2524|7369|M W 5: [MB]_MEM ;Write memory into MB
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,12,61,00,0000,00,0,00,0,0,0,2525|7370| MEM HOLD,
|2525|7371| IF [NO BUS ERROR] RETURN
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,03,01,00,4576,00,0,00,0,0,0,2526|7372| MEM HOLD,GOTO [MEM ERR]
|2526|7373|
|2526|7374|;Here if writing AC or unpaged
000,000,0,04,06,1,42,0,33,0,0,00,00,00,00,23,0,20,1,1,1,03,22,00,4733,00,7,00,0,0,0,2527|7375|M W 8: [E]_[PMA],SPEC SEL/VMA, ;Address register
|2527|7376| IF [NOT AC REF] THEN [M W 4] ;Check for unpaged
|2527|7377| IF [ILLEGAL SECTION] THENP [PF X27]
000,000,0,14,14,0,77,0,44,0,0,00,00,00,00,00,0,20,1,1,1,12,01,00,0000,00,7,04,0,0,0,2529|7378| [MB]_RAMFILE,RETURN ;Write AC in RAMFILE
|2529|7379|
|2529|7380|
|2529|7381|.TOC 2, "Page Fail"
|2529|7382|
|2529|7383|
|2529|7384|
|2529|7385|; TOPS20 TOPS10
|2529|7386|; +-----------------------------------+ +----------------------------------+
|2529|7387|; 500 | Page fail word | | Page fail word |
|2529|7388|; +-----------------------------------+ +----------------------------------+
|2529|7389|; 501 | Page fail flags | | Page fail old flags,,PC |
|2529|7390|; +-----------------------------------+ +----------------------------------+
|2529|7391|; 502 | Page fail old PC | | Page fail new PC |
|2529|7392|; +-----------------------------------+ +----------------------------------+
|2529|7393|; 503 | Page fail new PC | | Reserved |
|2529|7394|; +-----------------------------------+ +----------------------------------+
|2529|7395|
|2529|7396|
|2529|7397|
|2529|7398|;Here for an aged page fail
000,000,0,04,10,1,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,2100,00,7,01,0,0,0,2530|7399|AGE PF:
|2530|7400|.IF/FTAGEPF
|2530|7401| J[02100]_[W1]
|2530|7402| GOTOP [PF XX]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,13,01,00,4752,00,7,00,0,0,0,2531|7403|.ENDIF/FTAGEPF
|2531|7404|
|2531|7405|;Here for uncoded page fail
000,000,0,04,10,1,00,0,00,0,0,00,00,00,00,00,0,20,1,1,1,13,01,00,4756,00,7,00,0,0,0,2532|7406|PF X0: ZERO_[W1],
|2532|7407| GOTOP [PAGE FAIL]
|2532|7408|
|2532|7409|;Here for an IO page fail
000,000,0,04,10,1,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,2000,00,7,01,0,0,0,2533|7410|IO PF:
|2533|7411|PF X20: J[02000]_[W1]
|2533|7412| GOTOP [PF XX]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,13,01,00,4752,00,7,00,0,0,0,2534|7413|
|2534|7414|;Here for a Illegal Indirect page fail
000,000,0,04,10,1,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,2400,00,7,01,0,0,0,2535|7415|PF X24: J[02400]_[W1]
|2535|7416| GOTOP [PF XX]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,13,01,00,4752,00,7,00,0,0,0,2536|7417|
|2536|7418|;Here for an Illegal Section page fail
000,000,0,04,10,1,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,2700,00,7,01,0,0,0,2537|7419|PF X27: J[02700]_[W1]
|2537|7420| ;GOTOP [PF XX]
|2537|7421|
000,000,0,04,10,0,02,2,00,0,0,00,00,00,00,00,0,20,1,1,0,04,01,00,0002,00,7,07,0,0,0,2538|7422|PF XX: SWAP [W1]_[W1],PUSH J[2]_CTR ;Move code to lh
000,000,1,11,03,0,02,0,00,0,0,00,00,11,00,00,0,20,1,1,1,10,00,00,0000,00,7,00,0,0,0,2539|7423| #4*[W1]_B,RFCT ;Shift 6 places left
|2539|7424| GOTO [PF XX1]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,03,01,00,4763,00,7,00,0,0,0,2540|7425|
|2540|7426|.IF/DEBUGPF
000,000,0,04,00,1,00,0,00,0,0,00,00,00,00,00,0,20,1,1,1,03,01,00,1166,00,7,00,0,0,0,2541|7427|HALT PG:
|2541|7428| ONES_[W1],
|2541|7429| GOTO [SET HALT CODE]
|2541|7430|.ENDIF/DEBUGPF
|2541|7431|
|2541|7432|;Here to do a Page fail, with page fail word in W1
000,000,0,01,10,1,00,0,04,0,0,00,00,05,00,00,0,20,1,1,0,16,00,00,0001,00,7,01,0,0,0,2542|7433|PAGE FAIL:
|2542|7434|.IF/DEBUGPF
|2542|7435| JS[1]_[W2] ;Mask for illegal bits
|2542|7436| ROR [W2]_[W2]
000,000,0,14,14,0,02,0,04,0,0,00,00,00,00,00,0,64,1,1,1,03,03,00,4755,00,7,00,0,0,0,2544|7437| [W1]&[W2]_Y,
|2544|7438| IF NOT CT [IZ] THEN [HALT PG]
|2544|7439|.ENDIF/DEBUGPF
000,000,0,01,06,1,47,0,04,0,0,00,00,51,00,00,0,32,1,1,1,03,03,00,4763,00,7,00,0,0,0,2545|7440| ROR [BIT4]_[W2], ;Make a type-l bit
|2545|7441| IF NOT CT [UC] THEN [PF XX1]
|2545|7442| [W2].OR.[W1]_B ;Add T bit
000,000,0,04,10,1,00,0,04,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0037,00,7,01,0,0,0,2547|7443|PF XX1: J[037]_[W2] ;Build mask
|2547|7444| SWAP [W2]_[W2]
000,000,0,04,14,0,06,0,41,0,0,00,00,00,00,00,0,20,1,1,1,01,46,00,2424,00,7,00,0,0,0,2549|7445| [W2]&[E LH]_B,
|2549|7446| IF [PXCT] CALL [SET CURRENT CTXT]
000,000,0,06,11,0,67,0,00,0,0,00,00,00,00,03,0,20,1,1,0,16,00,00,0164,00,7,01,0,0,0,2550|7447| J[PF RCOVR]_RAMFILE ADR,
|2550|7448| [K 7777.-1]BAR&[W1]_Q ;Strip mapping info
000,000,0,04,17,1,42,0,00,0,0,00,00,00,00,00,0,20,1,1,1,13,41,00,4772,00,7,00,0,0,0,2551|7449| Q.OR.[E]_[W1], ;Put virtual address in PF wcrd
|2551|7450| IF [NOT PAGED] THENP [PF XX2]
|2551|7451| J[01000]_[W2] ;Will become V bit
000,000,0,04,10,0,06,2,04,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,3140,00,7,07,0,0,0,2553|7452| SWAP [W2]_[W2],
|2553|7453| CALL [W2.OR.W1]
000,000,0,04,06,1,02,0,44,0,0,00,00,00,00,00,0,20,1,1,1,01,36,00,5012,00,7,00,0,0,0,2554|7454|PF XX2: [W1]_[MB], ;Copy page fail word
|2554|7455| IF [USER] CALL [B0!MB] ;Add user mode if needed
000,000,0,04,10,0,00,0,04,0,0,00,00,00,00,00,0,20,1,0,0,16,00,00,0000,00,7,04,0,0,0,2555|7456| RAMFILE_[W2],IX_MX ;Get recovery routine adr
000,000,0,14,06,1,06,0,00,0,0,00,00,00,00,00,0,44,1,1,1,03,03,00,0000,00,7,01,0,0,0,2556|7457| [W2]_Y,
|2556|7458| IF NOT CT [MZ] THEN Y ;If there is one do it
|2556|7459| J[PF MER]_[W1] ;In case error fetching from UPT
000,000,0,04,03,0,77,0,36,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,5021,00,7,00,0,0,0,2558|7460| [K -1]+[PC RH]_B, ;Backup the PC
|2558|7461| CALL [SET MER] ; Set memory err recovery
|2558|7462| J[PFW]_[PMA] ;Get offset into UPT for page fail word
000,000,0,04,03,0,23,0,33,0,0,00,00,05,00,00,0,20,1,1,1,01,01,00,4704,00,2,02,0,0,0,2560|7463| [UPT]+[PMA]_B,MEM START WRITE, ;Physical location of word
|2560|7464| CALL [UNMAPPED WRITE]
000,000,0,04,06,1,03,0,44,0,0,00,00,00,00,00,0,20,1,1,1,03,44,00,5003,00,7,00,0,0,0,2561|7465| [PC FLAGS]_[MB], ;Next word is flags
|2561|7466| IF [TOPS20] THEN [PF 34]
000,000,0,04,06,1,36,0,46,0,0,00,00,00,00,00,0,20,1,1,1,03,01,00,5005,00,7,00,0,0,0,2562|7467| [PC]_[MB RH],GOTO [PF 35] ;Put PC in rh
000,000,0,04,06,1,33,0,33,0,1,00,00,05,00,00,0,20,1,1,1,01,01,00,4704,00,2,02,0,0,0,2563|7468|PF 34: [PMA]+1_[PMA],MEM START WRITE, ;Store flags
|2563|7469| CALL [UNMAPPED WRITE]
|2563|7470| [PC]_[MB] ;Next word is PC
000,000,0,04,06,1,33,0,33,0,1,00,00,05,00,00,0,20,1,1,1,01,01,00,4704,00,2,02,0,0,0,2565|7471|PF 35: [PMA]+1_[PMA],MEM START WRITE, ;Store PC
|2565|7472| CALL [UNMAPPED WRITE]
000,000,0,04,06,1,33,0,33,0,1,00,00,05,00,00,0,20,1,1,1,01,01,00,4573,00,1,02,0,0,0,2566|7473|PF 40: [PMA]+1_[PMA],MEM START READ,
|2566|7474| CALL [UNMAPPED READ] ;Get new PC
000,000,0,04,10,1,00,0,00,0,0,00,00,00,00,00,0,20,1,1,1,01,01,00,5021,00,7,00,0,0,0,2567|7475| ZERO_[W1],CALL [SET MER] ;Have now passed any errors
000,000,0,04,06,1,46,0,34,0,0,00,20,00,00,00,0,20,1,1,1,03,45,00,2315,00,7,00,0,0,0,2568|7476| [MB]_[PC],SET EXEC,
|2568|7477| IF [TOPS10] THEN [MB_PC FLAGS]
000,000,0,04,10,1,00,0,03,0,0,00,14,00,00,00,0,20,1,1,1,03,01,00,1420,00,7,00,0,0,0,2569|7478| ZERO_[PC FLAGS],SET LOCAL,
|2569|7479| GOTO [IFETCH]
|2569|7480|
000,000,0,01,10,1,00,0,00,0,0,00,00,05,00,00,0,20,1,1,0,16,00,00,0000,00,7,01,0,0,0,2570|7481|B0!MB: JS[0]_[W1] ;Put 400000,,0 in W1
000,000,0,04,17,0,02,0,44,0,0,00,00,00,00,00,0,20,1,1,1,12,01,00,0000,00,7,00,0,0,0,2571|7482|W1!MB: [W1].OR.[MB]_B, ;Set bit
|2571|7483| RETURN
|2571|7484|
|2571|7485|;Here if encounter NXK, bus error, or ECC error
000,000,0,04,10,1,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,16,00,00,0004,00,7,01,0,0,0,2572|7486|PF MER: J[HALT PFMER]_[W1]
|2572|7487| GOTOP [SET HALT CODE] ;Set halt code and quit
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,13,01,00,1166,00,7,00,0,0,0,2573|7488|
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,00,0,20,1,1,0,01,01,00,5021,00,7,00,0,0,0,2574|7489|SET PF ME RCOVR:
|2574|7490| CALL [SET MER]
|2574|7491| ;GOTO [SET PF RCOVR]
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,03,0,20,1,1,0,16,00,00,0164,00,7,01,0,0,0,2575|7492|SET PF RCOVR:
|2575|7493| J[PF RCOVR]_RAMFILE ADR ;In case errors handling int
|2575|7494|
000,000,0,14,14,0,77,0,00,0,0,00,00,00,00,00,0,20,1,1,1,12,01,00,0000,00,7,04,0,0,0,2576|7495|W1_RAMFILE:
|2576|7496| [W1]_RAMFILE,
|2576|7497| RETURN
|2576|7498|
|2576|7499|;Here to set memory error recovery location
000,000,0,14,10,0,00,0,00,0,0,00,00,00,00,03,0,20,1,1,0,16,00,00,0150,00,7,01,0,0,0,2577|7500|SET MER:
|2577|7501| J[ME RCOVR]_RAMFILE ADR
000,000,0,14,06,1,02,0,00,0,0,00,00,00,00,00,0,20,1,1,1,12,01,00,0000,00,7,04,0,0,0,2578|7502| [W1]_Y,ALU_RAMFILE,
|2578|7503| RETURN
|2578|7504|
|2578|7505|.TOC 1, "Dispatch Table"
|2578|7506|.TOC 2, "Dispatch Table Field Definitions"
|2578|7507|
|2578|7508|.DCODE
|00-1|7509|
|00-1|7510|J/=< 0:11>,.ADDRESS,.DEFAULT=<MCE> ;1st Dispatch = OPERAND FETCH Dispatch
|00-1|7511|K/=<12:23>,.ADDRESS,.DEFAULT=<MCE> ;2nd Dispatch = INST EXCT Dispatch
|00-1|7512|L/=<24:35>,.ADDRESS,.DEFAULT=<MCE> ;3rd Dispatch = OPERAND STORE Dispatch
|00-1|7513|M/=<36:47>,.ADDRESS,.DEFAULT=<MCE> ;4th Dispatch = final inst dispatch
|00-1|7514|N/=<48:59>,.ADDRESS,.DEFAULT=<MCE> ;5th Dispatch = free
|00-1|7515|O/=<60:71>,.ADDRESS,.DEFAULT=<MCE> ;6th Dispatch = free
|00-1|7516|P/=<72:83>,.ADDRESS,.DEFAULT=<MCE> ;7th Dispatch = 1st half of IO dispatch
|00-1|7517|Q/=<84:95>,.ADDRESS,.DEFAULT=<MCE> ;8th Dispatch = 2nd half of IO dispatch
|00-1|7518|
|00-1|7519|.TOC 2, "Dispatch Table Macros"
|00-1|7520|
|00-1|7521|[] [] [] [] [] [] [] [] "J/@1,K/@2,L/@3,M/@4,N/@5,O/@6,P/@7,Q/@8"
|00-1|7522|[] "[@1] [MCE] [MCE] [MCE] [MCE] [MCE] [MUUO] [MCE]"
|00-1|7523|[]#[] "[@1] [MCE] [MCE] [MCE] [MCE] [MCE] [@2] [MCE]"
|00-1|7524|[]##[] "[@1] [MCE] [MCE] [MCE] [MCE] [MCE] [MUUO] [@2]"
|00-1|7525|[] [] "[@1] [@2] [MCE] [MCE] [MCE] [MCE] [MUUO] [MCE]"
|00-1|7526|[] []#[] "[@1] [@2] [MCE] [MCE] [MCE] [MCE] [@3] [MCE]"
|00-1|7527|[] []##[] "[@1] [@2] [MCE] [MCE] [MCE] [MCE] [MUUO] [@3]"
|00-1|7528|[] [] [] "[@1] [@2] [@3] [MCE] [MCE] [MCE] [MUUO] [MCE]"
|00-1|7529|[] [] []#[] "[@1] [@2] [@3] [MCE] [MCE] [MCE] [@4] [MCE]"
|00-1|7530|[] [] []##[] "[@1] [@2] [@3] [MCE] [MCE] [MCE] [MUUO] [@4]"
|00-1|7531|[] [] [] [] "[@1] [@2] [@3] [@4] [MCE] [MCE] [MUUO] [MCE]"
|00-1|7532|[] [] [] []#[] "[@1] [@2] [@3] [@4] [MCE] [MCE] [@5] [MCE] "
|00-1|7533|[] [] [] []##[] "[@1] [@2] [@3] [@4] [MCE] [MCE] [MUUO] [@5]"
|00-1|7534|
|00-1|7535|
|00-1|7536|.TOC 2, "Opcodes 000 - 037"
|00-1|7537|
1637,1304,1304,1304,1304,1304,3076,1304,0000|7538|0:
|0000|7539| [MUUO]#[APRID] ;000 70000 Illegal
|0000|7540| [CHK PC SECT] [MCE] [LUUO] ;001 70004 LUUO
2510,1304,1600,1304,1304,1304,1637,1304,0001|7541| [CHK PC SECT] [MCE] [LUUO] ;002 70010 LUUO
2510,1304,1600,1304,1304,1304,1637,1304,0002|7542| [CHK PC SECT] [MCE] [LUUO] ;003 70014 LUUO
2510,1304,1600,1304,1304,1304,1637,1304,0003|7543| [CHK PC SECT] [MCE] [LUUO]#[WRAPR] ;004 70020 LUUO
2510,1304,1600,1304,1304,1304,3100,1304,0004|7544| [CHK PC SECT] [MCE] [LUUO]#[RDAPR] ;005 70024 LUUO
2510,1304,1600,1304,1304,1304,3141,1304,0005|7545| [CHK PC SECT] [MCE] [LUUO]#[SZAPR] ;006 70030 LUUO
2510,1304,1600,1304,1304,1304,3151,1304,0006|7546| [CHK PC SECT] [MCE] [LUUO]#[SNAPR] ;007 70034 LUUO
2510,1304,1600,1304,1304,1304,3153,1304,0007|7547| [CHK PC SECT] [MCE] [LUUO] ;010 70040 LUUO
2510,1304,1600,1304,1304,1304,1637,1304,0008|7548| [CHK PC SECT] [MCE] [LUUO] ;011 70044 LUUO
2510,1304,1600,1304,1304,1304,1637,1304,0009|7549| [CHK PC SECT] [MCE] [LUUO] ;012 70050 LUUO
2510,1304,1600,1304,1304,1304,1637,1304,0010|7550| [CHK PC SECT] [MCE] [LUUO] ;013 70054 LUUO
2510,1304,1600,1304,1304,1304,1637,1304,0011|7551| [CHK PC SECT] [MCE] [LUUO]#[WRPI] ;014 70060 LUUO
2510,1304,1600,1304,1304,1304,3155,1304,0012|7552| [CHK PC SECT] [MCE] [LUUO]#[RDPI] ;015 70064 LUUO
2510,1304,1600,1304,1304,1304,3257,1304,0013|7553| [CHK PC SECT] [MCE] [LUUO]#[SZPI] ;0l6 70070 LUUO
2510,1304,1600,1304,1304,1304,3275,1304,0014|7554| [CHK PC SECT] [MCE] [LUUO]#[SNPI] ;017 70074 LUUO
2510,1304,1600,1304,1304,1304,3300,1304,0015|7555| [CHK PC SECT] [MCE] [LUUO] ;020 70100 LUUO
2510,1304,1600,1304,1304,1304,1637,1304,0016|7556| [CHK PC SECT] [MCE] [LUUO]#[RDUBR] ;021 70104 LUUO
2510,1304,1600,1304,1304,1304,3356,1304,0017|7557| [CHK PC SECT] [MCE] [LUUO]#[CLRPT] ;022 70110 LUUO
2510,1304,1600,1304,1304,1304,3412,1304,0018|7558| [CHK PC SECT] [MCE] [LUUO]#[WRUBR] ;023 70114 LUUO
2510,1304,1600,1304,1304,1304,3333,1304,0019|7559| [CHK PC SECT] [MCE] [LUUO]#[WREBR] ;024 70120 LUUO
2510,1304,1600,1304,1304,1304,3303,1304,0020|7560| [CHK PC SECT] [MCE] [LUUO]#[RDEBR] ;025 70124 LUUO
2510,1304,1600,1304,1304,1304,3326,1304,0021|7561| [CHK PC SECT] [MCE] [LUUO] ;026 70130 LUUO
2510,1304,1600,1304,1304,1304,1637,1304,0022|7562| [CHK PC SECT] [MCE] [LUUO] ;027 70134 LUUO
2510,1304,1600,1304,1304,1304,1637,1304,0023|7563| [CHK PC SECT] [MCE] [LUUO] ;030 70140 LUUO
2510,1304,1600,1304,1304,1304,1637,1304,0024|7564| [CHK PC SECT] [MCE] [LUUO] ;031 70144 LUUO
2510,1304,1600,1304,1304,1304,1637,1304,0025|7565| [CHK PC SECT] [MCE] [LUUO] ;032 70150 LUUO
2510,1304,1600,1304,1304,1304,1637,1304,0026|7566| [CHK PC SECT] [MCE] [LUUO] ;033 70154 LUUO
2510,1304,1600,1304,1304,1304,1637,1304,0027|7567| [CHK PC SECT] [MCE] [LUUO] ;034 70160 LUUO
2510,1304,1600,1304,1304,1304,1637,1304,0028|7568| [CHK PC SECT] [MCE] [LUUO] ;035 70164 LUUO
2510,1304,1600,1304,1304,1304,1637,1304,0029|7569| [CHK PC SECT] [MCE] [LUUO] ;036 70170 LUUO
2510,1304,1600,1304,1304,1304,1637,1304,0030|7570| [CHK PC SECT] [MCE] [LUUO] ;037 70174 LUUO
2510,1304,1600,1304,1304,1304,1637,1304,0031|7571|
|0031|7572|.TOC 2, "Opcodes 040 - 077"
|0031|7573|.IF/FT20PAG
|0031|7574| [MUUO]#[RDSPB] ;040 70200 MUUO
1637,1304,1304,1304,1304,1304,3372,1304,0032|7575| [MUUO]#[RDCSB] ;041 70204 MUUO
1637,1304,1304,1304,1304,1304,3410,1304,0033|7576| [MUUO]#[RDPUR] ;042 70210 MUUO
1637,1304,1304,1304,1304,1304,3403,1304,0034|7577| [MUUO]#[RDCSTM] ;043 70214 MUUO
1637,1304,1304,1304,1304,1304,3376,1304,0035|7578|.ENDIF/FT20PAG
|0035|7579|.IFNOT/FT20PAG
|0035|7580| [MUUO] ;040 70200 MUUO
|0035|7581| [MUUO] ;041 70204 MUUO
|0035|7582| [MUUO] ;042 70210 MUUO
|0035|7583| [MUUO] ;043 70214 MUUO
|0035|7584|.ENDIF/FT20PAG
|0035|7585| [MUUO]#[RDTIM] ;044 70220 MUUO
1637,1304,1304,1304,1304,1304,3417,1304,0036|7586| [MUUO]#[RDINT] ;045 70224 MUUO
1637,1304,1304,1304,1304,1304,3441,1304,0037|7587| [MUUO]#[RDHSB] ;046 70230 MUUO
1637,1304,1304,1304,1304,1304,3455,1304,0038|7588| [MUUO] ;047 70234 MUUO
1637,1304,1304,1304,1304,1304,1637,1304,0039|7589|.IF/FT20PAG
|0039|7590| [MUUO]#[WRSPB] ;050 70240 MUUO
1637,1304,1304,1304,1304,1304,3370,1304,0040|7591| [MUUO]#[WRCSB] ;051 70244 MUUO
1637,1304,1304,1304,1304,1304,3405,1304,0041|7592| [MUUO]#[WRPUR] ;052 70250 MUUO
1637,1304,1304,1304,1304,1304,3400,1304,0042|7593| [MUUO]#[WRCSTM] ;053 70254 MUUO
1637,1304,1304,1304,1304,1304,3373,1304,0043|7594|.ENDIF/FT20PAG
|0043|7595|.IFNOT/FT20PAG
|0043|7596| [MUUO] ;050 70240 MUUO
|0043|7597| [MUUO] ;051 70244 MUUO
|0043|7598| [MUUO] ;052 70250 MUUO
|0043|7599| [MUUO] ;053 70254 MUUO
|0043|7600|.ENDIF/FT20PAG
|0043|7601| [MUUO]#[WRTIM] ;054 70260 MUUO
1637,1304,1304,1304,1304,1304,3434,1304,0044|7602| [MUUO]#[WRINT] ;055 70264 MUUO
1637,1304,1304,1304,1304,1304,3444,1304,0045|7603| [MUUO]#[WRHSB] ;056 70270 MUUO
1637,1304,1304,1304,1304,1304,3452,1304,0046|7604| [MUUO] ;057 70274 MUUO
1637,1304,1304,1304,1304,1304,1637,1304,0047|7605| [MUUO] ;060 70300 MUUO
1637,1304,1304,1304,1304,1304,1637,1304,0048|7606| [MUUO] ;061 70304 MUUO
1637,1304,1304,1304,1304,1304,1637,1304,0049|7607| [MUUO] ;062 70310 MUUO
1637,1304,1304,1304,1304,1304,1637,1304,0050|7608| [MUUO] ;063 70314 MUUO
1637,1304,1304,1304,1304,1304,1637,1304,0051|7609| [MUUO] ;064 70320 MUUO
1637,1304,1304,1304,1304,1304,1637,1304,0052|7610| [MUUO] ;065 70324 MUUO
1637,1304,1304,1304,1304,1304,1637,1304,0053|7611| [MUUO] ;066 70330 MUUO
1637,1304,1304,1304,1304,1304,1637,1304,0054|7612| [MUUO] ;067 70334 MUUO
1637,1304,1304,1304,1304,1304,1637,1304,0055|7613| [MUUO] ;070 70340 MUUO
1637,1304,1304,1304,1304,1304,1637,1304,0056|7614| [MUUO] ;071 70344 MUUO
1637,1304,1304,1304,1304,1304,1637,1304,0057|7615| [MUUO] ;072 70350 MUUO
1637,1304,1304,1304,1304,1304,1637,1304,0058|7616| [MUUO] ;073 70354 MUUO
1637,1304,1304,1304,1304,1304,1637,1304,0059|7617| [MUUO] ;074 70360 MUUO
1637,1304,1304,1304,1304,1304,1637,1304,0060|7618| [MUUO] ;075 70364 MUUO
1637,1304,1304,1304,1304,1304,1637,1304,0061|7619| [MUUO] ;076 70370 MUUO
1637,1304,1304,1304,1304,1304,1637,1304,0062|7620| [MUUO] ;077 70374 MUUO
1637,1304,1304,1304,1304,1304,1637,1304,0063|7621|.TOC 2, "Opcodes 100 - 137"
|0063|7622| [MUUO] ;100 70400 MUUO
1637,1304,1304,1304,1304,1304,1637,1304,0064|7623| [MUUO] ;101 70404 MUUO
1637,1304,1304,1304,1304,1304,1637,1304,0065|7624| [MUUO] ;102 70410 MUUO
1637,1304,1304,1304,1304,1304,1637,1304,0066|7625| [MUUO] ;103 70414 MUUO
1637,1304,1304,1304,1304,1304,1637,1304,0067|7626| [MUUO] ;104 70420 MUUO
1637,1304,1304,1304,1304,1304,1637,1304,0068|7627| [FETCH AC&I] [CHK PC SECT] [ADJSP] [ADJSP V] ;105 70424 ADJSP
1526,2510,2455,2461,1304,1304,1637,1304,0069|7628| [MUUO] ;106 70430 MUUO
1637,1304,1304,1304,1304,1304,1637,1304,0070|7629| [MUUO] ;107 70434 MUUO
1637,1304,1304,1304,1304,1304,1637,1304,0071|7630| [MUUO] ;110 70440 DFAD
1637,1304,1304,1304,1304,1304,1637,1304,0072|7631| [MUUO] ;111 70444 DFSB
1637,1304,1304,1304,1304,1304,1637,1304,0073|7632| [MUUO] ;112 70450 DFMP
1637,1304,1304,1304,1304,1304,1637,1304,0074|7633| [MUUO] ;113 70454 DFDV
1637,1304,1304,1304,1304,1304,1637,1304,0075|7634| [DFETCH AC&MEM] [DADD] [D TO AC.0] ;114 70460 DADD
1474,2163,4340,1304,1304,1304,1637,1304,0076|7635| [DFETCH AC&MEM] [DSUB] [D TO AC.0] ;115 70464 DSUB
1474,2172,4340,1304,1304,1304,1637,1304,0077|7636| [DFETCH AC&MEM] [DMUL] [Q TO AC.0] ;116 70470 DMUL
1474,2175,4412,1304,1304,1304,1637,1304,0078|7637| [DFETCH AC&MEM] [DDIV] [Q TO AC.0] ;117 70474 DDIV
1474,2175,4412,1304,1304,1304,1637,1304,0079|7638| [DFETCH MEM] [D TO AC] ;120 70500 DMOVE
1476,4345,1304,1304,1304,1304,1637,1304,0080|7639| [DFETCH MEM] [DMOVNX] [D TO AC.0] ;121 70504 DMOVN
1476,1666,4340,1304,1304,1304,1637,1304,0081|7640| [FETCH MEM] [FIX] [IFETCH] ;122 70510 FIX
1511,2040,1420,1304,1304,1304,1637,1304,0082|7641|.IF/FTEXTEND
|0082|7642| [EXTEND] ;123 70514 EXTEND
2750,1304,1304,1304,1304,1304,1637,1304,0083|7643|.ENDIF/FTEXTEND
|0083|7644|.IFNOT/FTEXTEND
|0083|7645| [MUUO] ;123 70514 EXTEND
|0083|7646|.ENDIF/FTEXTEND
|0083|7647| [DFETCH AC] [D TO MEM] ;124 70520 DMOVEM
1472,4377,1304,1304,1304,1304,1637,1304,0084|7648| [DFETCH AC] [DMOVNX] [D TO MEM] ;125 70524 DMOVMN
1472,1666,4377,1304,1304,1304,1637,1304,0085|7649| [FETCH MEM] [FIX] [FIXR] ;126 70530 FIXR
1511,2040,2055,1304,1304,1304,1637,1304,0086|7650| [FETCH MEM] [FLTR] [TO AC] ;127 70534 FLTR
1511,2061,4343,1304,1304,1304,1637,1304,0087|7651| [MUUO] ;130 70540 UFA(obs)
1637,1304,1304,1304,1304,1304,1637,1304,0088|7652| [MUUO] ;131 70544 DFN(obs)
1637,1304,1304,1304,1304,1304,1637,1304,0089|7653| [MUUO] ;132 70550 FSC
1637,1304,1304,1304,1304,1304,1637,1304,0090|7654|.IF/FTBYTE
|0090|7655| [FETCH AC&MEM] [ADJBP] [TO NOWHERE] [ADJBP0] ;133 70554 ADJBP/IBP
1510,1731,4127,1675,1304,1304,1637,1304,0091|7656| [FETCH MEM(W)] [IP&S SETUP] [IP&S 5] [LDB] ;134 70560 ILDB
1516,1760,2010,2011,1304,1304,1637,1304,0092|7657| [FETCH MEM] [P&S SETUP] [MCE] [LDB] ;135 70564 LDB
1511,1732,1304,2011,1304,1304,1637,1304,0093|7658| [FETCH AC&MEM(W)] [IP&S SETUP] [IP&S 5] [DPB] ;136 70570 IDPB
1515,1760,2010,2021,1304,1304,1637,1304,0094|7659| [FETCH AC&MEM] [P&S SETUP] [MCE] [DPB] ;137 70574 DPB
1510,1732,1304,2021,1304,1304,1637,1304,0095|7660|.ENDIF/FTBYTE
|0095|7661|.IFNOT/FTBYTE
|0095|7662| [MUUO] ;133 70554 ADJBP/IBP
|0095|7663| [MUUO] ;134 70560 ILDB
|0095|7664| [MUUO] ;135 70564 LDB
|0095|7665| [MUUO] ;136 70570 IDPB
|0095|7666| [MUUO] ;137 70574 DPB
|0095|7667|.ENDIF/FTBYTE
|0095|7668|
|0095|7669|.TOC 2, "Opcodes 140 - 177"
|0095|7670| [FETCH AC&MEM] [FADX] [TO AC.0] ;140 70600 FAD
1510,2061,4342,1304,1304,1304,1637,1304,0096|7671| [MUUO] ;141 70604 FADL(obs)
1637,1304,1304,1304,1304,1304,1637,1304,0097|7672| [FETCH AC&MEM(W)] [FADX] [TO MEM] ;142 70610 FADM
1515,2061,4371,1304,1304,1304,1637,1304,0098|7673| [FETCH AC&MEM(W)] [FADX] [TO BOTH.0] ;143 70614 FADB
1515,2061,4357,1304,1304,1304,1637,1304,0099|7674| [FETCH AC&MEM] [FADRX] [TO AC.0] ;144 70620 FADR
1510,2061,4342,1304,1304,1304,1637,1304,0100|7675| [FETCH AC&I] [FADRX] [TO AC.0] ;145 70624 FADRI
1526,2061,4342,1304,1304,1304,1637,1304,0101|7676| [FETCH AC&MEM(W)] [FADRX] [TO MEM] ;146 70630 FADRM
1515,2061,4371,1304,1304,1304,1637,1304,0102|7677| [FETCH AC&MEM(W)] [FADRX] [TO BOTH.0] ;147 70634 FADRB
1515,2061,4357,1304,1304,1304,1637,1304,0103|7678| [FETCH AC&MEM] [FSBX] [TO AC.0] ;150 70640 FSB
1510,2061,4342,1304,1304,1304,1637,1304,0104|7679| [MUUO] ;151 70644 FSBL(obs)
1637,1304,1304,1304,1304,1304,1637,1304,0105|7680| [FETCH AC&MEM(W)] [FSBX] [TO MEM] ;152 70650 FSBM
1515,2061,4371,1304,1304,1304,1637,1304,0106|7681| [FETCH AC&MEM(W)] [FSBX] [TO BOTH.0] ;153 70654 FSBB
1515,2061,4357,1304,1304,1304,1637,1304,0107|7682| [FETCH AC&MEM] [FSBX] [TO AC.0] ;154 70660 FSBR
1510,2061,4342,1304,1304,1304,1637,1304,0108|7683| [FETCH AC&I] [FSBX] [TO AC.0] ;155 70664 FSBRI
1526,2061,4342,1304,1304,1304,1637,1304,0109|7684| [FETCH AC&MEM(W)] [FSBX] [TO MEM] ;156 70670 FSBRM
1515,2061,4371,1304,1304,1304,1637,1304,0110|7685| [FETCH AC&MEM(W)] [FSBX] [TO BOTH.0] ;157 70674 FSBRB
1515,2061,4357,1304,1304,1304,1637,1304,0111|7686| [FETCH AC&MEM] [FMPX] [TO AC.0] ;160 70700 FMP
1510,2061,4342,1304,1304,1304,1637,1304,0112|7687| [MUUO] ;161 70704 FMPL(Obs)
1637,1304,1304,1304,1304,1304,1637,1304,0113|7688| [FETCH AC&MEM(W)] [FMPX] [TO MEM] ;162 70710 FMPM
1515,2061,4371,1304,1304,1304,1637,1304,0114|7689| [FETCH AC&MEM(W)] [FMPX] [TO BOTH.0] ;163 70714 FMPB
1515,2061,4357,1304,1304,1304,1637,1304,0115|7690| [FETCH AC&MEM] [FMPRX] [TO AC.0] ;164 70720 FMPR
1510,2061,4342,1304,1304,1304,1637,1304,0116|7691| [FETCH AC&MEM] [FMPRX] [TO AC.0] ;165 70724 FMPRI
1510,2061,4342,1304,1304,1304,1637,1304,0117|7692| [FETCH AC&MEM(W)] [FMPRX] [TO MEM] ;166 70730 FMPRM
1515,2061,4371,1304,1304,1304,1637,1304,0118|7693| [FETCH AC&MEM(W)] [FMPRX] [TO BOTH.0] ;167 70734 FMPRB
1515,2061,4357,1304,1304,1304,1637,1304,0119|7694|
|0119|7695| [FETCH MEM] [FDVX] [TO AC.0] ;170 70740 FDV
1511,2061,4342,1304,1304,1304,1637,1304,0120|7696| [MUUO] ;171 70744 FDVL(Obs)
1637,1304,1304,1304,1304,1304,1637,1304,0121|7697| [FETCH AC&MEM(W)] [FDVX] [TO MEM] ;172 70750 FDVM
1515,2061,4371,1304,1304,1304,1637,1304,0122|7698| [FETCH AC&MEM(W)] [FDVX] [TO BOTH.0] ;173 70754 FDVB
1515,2061,4357,1304,1304,1304,1637,1304,0123|7699| [FETCH AC&MEM] [FDVX] [TO AC.0] ;174 70760 FDVR
1510,2061,4342,1304,1304,1304,1637,1304,0124|7700| [FETCH AC&MEM] [FDVX] [TO AC.0] ;175 70764 FDVRI
1510,2061,4342,1304,1304,1304,1637,1304,0125|7701| [FETCH AC&MEM(W)] [FDVX] [TO MEM] ;176 70770 FDVRM
1515,2061,4371,1304,1304,1304,1637,1304,0126|7702| [FETCH AC&MEM(W)] [FDVX] [TO BOTH.0] ;177 70774 FDVRB
1515,2061,4357,1304,1304,1304,1637,1304,0127|7703|
|0127|7704|.TOC 2, "Opcodes 200 - 237"
|0127|7705| [FETCH MEM] [TO AC] ;200 71000 MOVE
1511,4343,1304,1304,1304,1304,1637,1304,0128|7706|.IF/FAST
|0128|7707| [MOVEI] ;201 71004 MOVEI
2061,1304,1304,1304,1304,1304,1637,1304,0129|7708|.ENDIF/FAST
|0129|7709|.IFNOT/FAST
|0129|7710| [FETCHI] [TO AC] ;201 71004 MOVEI
|0129|7711|.ENDIF/FAST
|0129|7712| [FETCH AC] [TO MEM] ;202 71010 MOVEM
1531,4371,1304,1304,1304,1304,1637,1304,0130|7713| [FETCH MEM(W)] [BACK TO SELF] ;203 71014 MOVES
1516,4352,1304,1304,1304,1304,1637,1304,0131|7714| [FETCH MEM] [MOVSX] [TO AC] ;204 71020 MOVS
1511,2064,4343,1304,1304,1304,1637,1304,0132|7715|.IF/FAST
|0132|7716| [MOVSI] ;205 71024 MOVSI
2062,1304,1304,1304,1304,1304,1637,1304,0133|7717|.ENDIF/FAST
|0133|7718|.IFNOT/FAST
|0133|7719| [FETCH I] [MOVSI] [TO AC] ;205 71024 MOVSI
|0133|7720|.ENDIF/FAST
|0133|7721| [FETCH AC] [MOVSX] [TO MEM] ;206 71030 MOVSM
1531,2064,4371,1304,1304,1304,1637,1304,0134|7722| [FETCH AC&MEM(W)] [MOVSX] [BACK TO SELF] ;207 71034 MOVSS
1515,2064,4352,1304,1304,1304,1637,1304,0135|7723| [FETCH MEM] [MOVNX] [TO AC] ;210 71040 MOVN
1511,2066,4343,1304,1304,1304,1637,1304,0136|7724| [FETCH I] [MOVNX] [TO AC] ;211 71044 MOVNI
1527,2066,4343,1304,1304,1304,1637,1304,0137|7725| [FETCH AC(MX)] [MOVNX] [TO MEM] ;212 71050 MOVNM
1532,2066,4371,1304,1304,1304,1637,1304,0138|7726| [FETCH MEM(W)] [MOVNX] [BACK TO SELF] ;213 71054 MOVNS
1516,2066,4352,1304,1304,1304,1637,1304,0139|7727| [FETCH MEM] [MOVMX] [TO AC] ;214 71060 MOVM
1511,2065,4343,1304,1304,1304,1637,1304,0140|7728|.IF/FAST
|0140|7729| [MOVEI] ;215 71064 MOYMI (=MOVEI)
2061,1304,1304,1304,1304,1304,1637,1304,0141|7730|.ENDIF/FAST
|0141|7731|.IFNOT/FAST
|0141|7732| [FETCH I] [TO AC] ;215 71064 MOYMI (=MOVEI)
|0141|7733|.ENDIF/FAST
|0141|7734| [FETCH AC(MX)] [MOVMX] [TO MEM] ;216 71070 MOVMM
1532,2065,4371,1304,1304,1304,1637,1304,0142|7735| [FETCH MEM(W)] [MOVMX] [BACK TO SELF] ;217 71074 MOVMS
1516,2065,4352,1304,1304,1304,1637,1304,0143|7736| [FETCH AC&MEM] [MULX] [IMULX] [TO AC.0] ;220 71100 IMUL
1510,2103,2114,4342,1304,1304,1637,1304,0144|7737| [FETCH AC&I] [MULX] [IMULX] [TO AC.0] ;221 71104 IMULI
1526,2103,2114,4342,1304,1304,1637,1304,0145|7738| [FETCH AC&MEM(W)] [MULX] [IMULX] [BACK TO MEM] ;222 71110 IMULM
1515,2103,2114,4363,1304,1304,1637,1304,0146|7739| [FETCH AC&MEM(W)] [MULX] [IMULX] [TO BOTH.0] ;223 71114 IMULB
1515,2103,2114,4357,1304,1304,1637,1304,0147|7740| [FETCH AC&MEM] [MULX] [D TO AC] ;224 71120 MUL
1510,2103,4345,1304,1304,1304,1637,1304,0148|7741| [FETCH AC&I] [MULX] [D TO AC] ;225 71124 MULI
1526,2103,4345,1304,1304,1304,1637,1304,0149|7742| [FETCH AC&MEM(W)] [MULX] [BACK TO MEM] ;226 71130 MULM
1515,2103,4363,1304,1304,1304,1637,1304,0150|7743| [FETCH AC&MEM(W)] [MULX] [TO MEM D AC] ;227 71134 MULB
1515,2103,4334,1304,1304,1304,1637,1304,0151|7744| [FETCH AC&MEM] [IDIVX] [D TO AC.0] ;230 71140 IDIV
1510,2117,4340,1304,1304,1304,1637,1304,0152|7745| [FETCH AC&I] [IDIVX] [D TO AC.0] ;231 71144 IDIVI
1526,2117,4340,1304,1304,1304,1637,1304,0153|7746| [FETCH AC&MEM(W)] [IDIVX] [BACK TO MEM] ;232 71150 IDIVM
1515,2117,4363,1304,1304,1304,1637,1304,0154|7747| [FETCH AC&MEM(W)] [IDIVX] [TO MEM D AC] ;233 71154 IDIVB
1515,2117,4334,1304,1304,1304,1637,1304,0155|7748| [FETCH AC&MEM] [DIVX] [D TO AC.0] ;234 71160 DIV
1510,2122,4340,1304,1304,1304,1637,1304,0156|7749| [FETCH AC&I] [DIVX] [D TO AC.0] ;235 71164 DIVI
1526,2122,4340,1304,1304,1304,1637,1304,0157|7750| [FETCH AC&MEM(W)] [DIVX] [BACK TO MEM] ;236 71170 DIVM
1515,2122,4363,1304,1304,1304,1637,1304,0158|7751| [FETCH AC&MEM(W)] [DIVX] [TO MEM D AC] ;237 71174 DIVB
1515,2122,4334,1304,1304,1304,1637,1304,0159|7752|
|0159|7753|.TOC 2, "Opcodes 240 - 277"
|0159|7754| [FETCH AC(MX)] [ASH SETUP] [ASH] [ASHR] ;240 71200 ASH
1532,2201,2210,2214,1304,1304,1637,1304,0160|7755| [FETCH AC] [ASH SETUP] [ROT] [ROTR] ;241 71204 ROT
1531,2201,2241,2243,1304,1304,1637,1304,0161|7756| [FETCH AC] [ASH SETUP] [LSH] [LSHR] ;242 71210 LSH
1531,2201,2231,2233,1304,1304,1637,1304,0162|7757| [FETCH AC(MX)] [JFFO] ;243 71214 JFFO
1532,2372,1304,1304,1304,1304,1637,1304,0163|7758| [DFETCH AC] [ASHC SETUP] [ASHC] [ASHCR] ;244 71220 ASHC
1472,2176,2216,2226,1304,1304,1637,1304,0164|7759| [DFETCH AC] [LSHC SETUP] [ROTC] [ROTCR] ;245 71224 ROTC
1472,2200,2245,2247,1304,1304,1637,1304,0165|7760| [DFETCH AC] [LSHC SETUP] [LSHC] [LSHCR] ;246 71230 LSHC
1472,2200,2235,2237,1304,1304,1637,1304,0166|7761| [MUUO] ;247 71234 MUUO
1637,1304,1304,1304,1304,1304,1637,1304,0167|7762| [FETCH AC&MEM(W)] [TO EACH] ;250 71240 EXCH
1515,4361,1304,1304,1304,1304,1637,1304,0168|7763|.IF/FAST
|0168|7764| [FETCH AC] [BLT] [BLT+1N] ;251 71244 BLT
1531,2251,2274,1304,1304,1304,1637,1304,0169|7765|.ENDIF/FAST
|0169|7766|.IFNOT/FAST
|0169|7767| [FETCH AC] [BLT] ;251 71244 BLT
|0169|7768|.ENDIF/FAST
|0169|7769| [FETCH AC] [AOBJX] [JXGE] [TO AC.0] ;252 71250 AOBJP
1531,2300,2650,4342,1304,1304,1637,1304,0170|7770| [FETCH AC] [AOBJX] [JXL] [TO AC.0] ;253 71254 AOBJN
1531,2300,2641,4342,1304,1304,1637,1304,0171|7771| [JRST] [MCE] [MCE] [IFETCH] ;254 71260 JRST
2302,1304,1304,1420,1304,1304,1637,1304,0172|7772| [JFCL] [MCE] [MCE] [IFETCH] ;255 71264 JFCL
2400,1304,1304,1420,1304,1304,1637,1304,0173|7773| [FETCH MEM] [XCT] ;256 71270 XCT
1511,2406,1304,1304,1304,1304,1637,1304,0174|7774| [MAP] ;257 71274 MAP
2445,1304,1304,1304,1304,1304,1637,1304,0175|7775| [FETCH AC] [CHK PC SECT] [PUSHJ] ;260 71300 PUSHJ
1531,2510,2466,1304,1304,1304,1637,1304,0176|7776| [FETCH AC&MEM] [PUSH] ;261 71304 PUSH
1510,2511,1304,1304,1304,1304,1637,1304,0177|7777| [FETCH AC] [CHK PC SECT] [POP] ;262 71310 POP
1531,2510,2530,1304,1304,1304,1637,1304,0178|7778| [FETCH AC] [CHK PC SECT] [POPJ] ;263 71314 POPJ
1531,2510,2561,1304,1304,1304,1637,1304,0179|7779| [CHK PC SECT] [JSR] [JSR SETUP] ;264 71320 JSR
2510,2577,2573,1304,1304,1304,1637,1304,0180|7780| [CHK PC SECT] [JSP] [JSR SETUP] ;265 71324 JSP
2510,2604,2573,1304,1304,1304,1637,1304,0181|7781| [FETCH AC] [JSA] ;266 71330 JSA
1531,2605,1304,1304,1304,1304,1637,1304,0182|7782| [FETCH AC] [JRA] ;267 71334 JRA
1531,2612,1304,1304,1304,1304,1637,1304,0183|7783| [FETCH AC&MEM] [ADDX] [TO AC] ;270 71340 ADD
1510,2073,4343,1304,1304,1304,1637,1304,0184|7784| [FETCH AC&I] [ADDX] [TO AC] ;271 71344 ADDI
1526,2073,4343,1304,1304,1304,1637,1304,0185|7785| [FETCH AC&MEM(W)] [ADDX] [BACK TO MEM] ;272 71350 ADDK
1515,2073,4363,1304,1304,1304,1637,1304,0186|7786| [FETCH AC&MEM(W)] [ADDX] [TO BOTH.0] ;273 71354 ADDB
1515,2073,4357,1304,1304,1304,1637,1304,0187|7787| [FETCH AC&MEM] [SUBX] [TO AC] ;274 11360 SUB
1510,2076,4343,1304,1304,1304,1637,1304,0188|7788| [FETCH AC&I] [SUBX] [TO AC] ;275 71364 SUBI
1526,2076,4343,1304,1304,1304,1637,1304,0189|7789| [FETCH AC&MEM(W)] [SUBX] [BACK TO MEM] ;276 71370 SUBK
1515,2076,4363,1304,1304,1304,1637,1304,0190|7790| [FETCH AC&MEM(W)] [SUBX] [TO BOTH.0] ;277 71374 SUBB
1515,2076,4357,1304,1304,1304,1637,1304,0191|7791|
|0191|7792|.TOC 2, "Opcodes 300 - 337"
|0191|7793| [TO NOWHERE] ;300 71400 CAI
4127,1304,1304,1304,1304,1304,1637,1304,0192|7794| [FETCH AC&I] [CAX] [SXL] [IFETCH]##[JXA] ;301 71404 CAIL JRST 1,
1526,2616,2625,1420,1304,1304,1637,2647,0193|7795| [FETCH AC&I] [CAX] [SXE] [IFETCH]##[JRSTF] ;302 71410 CAIE JRST 2,
1526,2616,2627,1420,1304,1304,1637,2305,0194|7796| [FETCH AC&I] [CAX] [SXLE] [IFETCH]##[MUUO] ;303 71414 CAILE JRST 3,
1526,2616,2631,1420,1304,1304,1637,1637,0195|7797| [FETCH AC&I] [CAX] [SXA] [IFETCH]##[HALT] ;304 71420 CAIA JRST 4,
1526,2616,2632,1420,1304,1304,1637,2323,0196|7798| [FETCH AC&I] [CAX] [SXGE] [IFETCH]##[XJRSTF] ;305 71424 CAIGE JRST 5,
1526,2616,2633,1420,1304,1304,1637,2326,0197|7799| [FETCH AC&I] [CAX] [SXN] [IFETCH]##[XJEN] ;306 71430 CAIN JRST 6,
1526,2616,2635,1420,1304,1304,1637,2334,0198|7800| [FETCH AC&I] [CAX] [SXG] [IFETCH]##[XPCW] ;307 71434 CAIG JRST 7,
1526,2616,2637,1420,1304,1304,1637,2341,0199|7801| [FETCH MEM] [IFETCH]##[JRST 10] ;310 71440 CAM JRST 10,
1511,1420,1304,1304,1304,1304,1637,2350,0200|7802| [FETCH AC&MEM] [CAX] [SXL] [IFETCH]##[MUUO] ;311 71444 CAML JRST 11,
1510,2616,2625,1420,1304,1304,1637,1637,0201|7803| [FETCH AC&MEM] [CAX] [SXE] [IFETCH]##[JEN] ;312 71450 CAME JRST 12,
1510,2616,2627,1420,1304,1304,1637,2352,0202|7804| [FETCH AC&MEM] [CAX] [SXLE] [IFETCH]##[MUUO] ;313 71454 CAMLE JRST 13,
1510,2616,2631,1420,1304,1304,1637,1637,0203|7805| [FETCH AC&MEM] [CAX] [SXA] [IFETCH]##[SFM] ;314 71460 CAMA JRST 14,
1510,2616,2632,1420,1304,1304,1637,2367,0204|7806| [FETCH AC&MEM] [CAX] [SXGE] [IFETCH]##[MUUO] ;315 71464 CAMGE JRST 15,
1510,2616,2633,1420,1304,1304,1637,1637,0205|7807| [FETCH AC&MEM] [CAX] [SXN] [IFETCH]##[MUUO] ;316 71470 CAMN JRST 16,
1510,2616,2635,1420,1304,1304,1637,1637,0206|7808| [FETCH AC&MEM] [CAX] [SXG] [IFETCH]##[MUUO] ;317 71474 CAMG JRST 17,
1510,2616,2637,1420,1304,1304,1637,1637,0207|7809| [TO NOWHERE] ;320 71500 JUMP
4127,1304,1304,1304,1304,1304,1637,1304,0208|7810| [FETCH AC(MX)] [JXL] [MCE] [IFETCH] ;321 71504 JUMPL
1532,2641,1304,1420,1304,1304,1637,1304,0209|7811| [FETCH AC(MX)] [JXE] [MCE] [IFETCH] ;322 71510 JUKPE
1532,2643,1304,1420,1304,1304,1637,1304,0210|7812| [FETCH AC(MX)] [JXLE] [MCE] [IFETCH] ;323 71514 JUMPLE
1532,2645,1304,1420,1304,1304,1637,1304,0211|7813| [JXA] [MCE] [MCE] [IFETCH] ;324 71520 JUKPA
2647,1304,1304,1420,1304,1304,1637,1304,0212|7814| [FETCH AC(MX)] [JXGE] [MCE] [IFETCH] ;325 71524 JUKPGE
1532,2650,1304,1420,1304,1304,1637,1304,0213|7815| [FETCH AC(MX)] [JXN] [MCE] [IFETCH] ;326 71530 JUKPN
1532,2652,1304,1420,1304,1304,1637,1304,0214|7816| [FETCH AC(MX)] [JXG] [MCE] [IFETCH] ;327 71534 JUKPG
1532,2654,1304,1420,1304,1304,1637,1304,0215|7817| [FETCH MEM] [SKIPX] ;330 7154O SKIP
1511,2656,1304,1304,1304,1304,1637,1304,0216|7818| [FETCH MEM] [SXL] [MCE] [SKIPX] ;331 71544 SKIPL
1511,2625,1304,2656,1304,1304,1637,1304,0217|7819| [FETCH MEM] [SXE] [MCE] [SKIPX] ;332 71550 SKIPE
1511,2627,1304,2656,1304,1304,1637,1304,0218|7820| [FETCH MEM] [SXLE] [MCE] [SKIPX] ;333 71554 SKIPLE
1511,2631,1304,2656,1304,1304,1637,1304,0219|7821| [FETCH MEM] [SXA] [MCE] [SKIPX] ;334 71560 SKIPA
1511,2632,1304,2656,1304,1304,1637,1304,0220|7822| [FETCH MEM] [SXGE] [MCE] [SKIPX] ;335 71564 SKIPGE
1511,2633,1304,2656,1304,1304,1637,1304,0221|7823| [FETCH MEM] [SXN] [MCE] [SKIPX] ;336 71570 SKIPN
1511,2635,1304,2656,1304,1304,1637,1304,0222|7824| [FETCH MEM] [SXG] [MCE] [SKIPX] ;337 71574 SKIPG
1511,2637,1304,2656,1304,1304,1637,1304,0223|7825|
|0223|7826|.TOC 2, "Opcodes 340 - 377"
|0223|7827| [FETCH AC] [AOXX] [TO AC] ;340 71600 AOJ
1531,2617,4343,1304,1304,1304,1637,1304,0224|7828| [FETCH AC] [AOXX] [JXL] [TO AC] ;341 71604 AOJL
1531,2617,2641,4343,1304,1304,1637,1304,0225|7829| [FETCH AC] [AOXX] [JXE] [TO AC] ;342 71610 AOJE
1531,2617,2643,4343,1304,1304,1637,1304,0226|7830| [FETCH AC] [AOXX] [JXLE] [TO AC] ;343 71614 AOJLE
1531,2617,2645,4343,1304,1304,1637,1304,0227|7831| [FETCH AC] [AOXX] [JXA] [TO AC] ;344 71620 AOJA
1531,2617,2647,4343,1304,1304,1637,1304,0228|7832| [FETCH AC] [AOXX] [JXGE] [TO AC] ;345 71624 AOJGE
1531,2617,2650,4343,1304,1304,1637,1304,0229|7833| [FETCH AC] [AOXX] [JXN] [TO AC] ;346 71630 AOJN
1531,2617,2652,4343,1304,1304,1637,1304,0230|7834| [FETCH AC] [AOXX] [JXG] [TO AC] ;347 71634 AOJG
1531,2617,2654,4343,1304,1304,1637,1304,0231|7835| [FETCH MEM(W)] [AOXX] [BACK TO SELF] ;350 71640 AOS
1516,2617,4352,1304,1304,1304,1637,1304,0232|7836| [FETCH MEM(W)] [AOXX] [SXL] [BACK TO SELF] ;351 ji644 AOSL
1516,2617,2625,4352,1304,1304,1637,1304,0233|7837| [FETCH MEM(W)] [AOXX] [SXE] [BACK TO SELF] ;352 71650 AOSE
1516,2617,2627,4352,1304,1304,1637,1304,0234|7838| [FETCH MEM(W)] [AOXX] [SXLE] [BACK TO SELF] ;353 71654 AOSLE
1516,2617,2631,4352,1304,1304,1637,1304,0235|7839| [FETCH MEM(W)] [AOXX] [SXA] [BACK TO SELF] ;354 71660 AOSA
1516,2617,2632,4352,1304,1304,1637,1304,0236|7840| [FETCH MEM(W)] [AOXX] [SXGE] [BACK TO SELF] ;355 71664 AOSGE
1516,2617,2633,4352,1304,1304,1637,1304,0237|7841| [FETCH MEM(W)] [AOXX] [SXN] [BACK TO SELF] ;356 71670 AOSN
1516,2617,2635,4352,1304,1304,1637,1304,0238|7842| [FETCH MEM(W)] [AOXX] [SXG] [BACK TO SELF] ;357 71674 AOSG
1516,2617,2637,4352,1304,1304,1637,1304,0239|7843| [FETCH AC] [SOXX] [TO AC] ;360 71700 SOJ
1531,2622,4343,1304,1304,1304,1637,1304,0240|7844| [FETCH AC] [SOXX] [JXL] [TO AC] ;361 71704 SOJL
1531,2622,2641,4343,1304,1304,1637,1304,0241|7845| [FETCH AC] [SOXX] [JXE] [TO AC] ;362 71710 SOJE
1531,2622,2643,4343,1304,1304,1637,1304,0242|7846| [FETCH AC] [SOXX] [JXLE] [TO AC] ;363 71714 SOJLE
1531,2622,2645,4343,1304,1304,1637,1304,0243|7847| [FETCH AC] [SOXX] [JXA] [TO AC] ;364 71720 SOJA
1531,2622,2647,4343,1304,1304,1637,1304,0244|7848| [FETCH AC] [SOXX] [JXGE] [TO AC] ;365 71724 SOJGE
1531,2622,2650,4343,1304,1304,1637,1304,0245|7849| [FETCH AC] [SOXX] [JXN] [TO AC] ;366 71730 SOJN
1531,2622,2652,4343,1304,1304,1637,1304,0246|7850| [FETCH AC] [SOXX] [JXG] [TO AC] ;367 71734 SOJG
1531,2622,2654,4343,1304,1304,1637,1304,0247|7851| [FETCH MEM(W)] [SOXX] [BACK TO SELF] ;370 71740 SOS
1516,2622,4352,1304,1304,1304,1637,1304,0248|7852| [FETCH MEM(W)] [SOXX] [SXL] [BACK TO SELF] ;371 71744 SOSL
1516,2622,2625,4352,1304,1304,1637,1304,0249|7853| [FETCH MEM(W)] [SOXX] [SXE] [BACK TO SELF] ;372 71750 SOSE
1516,2622,2627,4352,1304,1304,1637,1304,0250|7854| [FETCH MEM(W)] [SOXX] [SXLE] [BACK TO SELF] ;373 71754 SOSLE
1516,2622,2631,4352,1304,1304,1637,1304,0251|7855| [FETCH MEM(W)] [SOXX] [SXA] [BACK TO SELF] ;374 71760 SOSA
1516,2622,2632,4352,1304,1304,1637,1304,0252|7856| [FETCH MEM(W)] [SOXX] [SXGE] [BACK TO SELF] ;375 71764 SOSGE
1516,2622,2633,4352,1304,1304,1637,1304,0253|7857| [FETCH MEM(W)] [SOXX] [SXN] [BACK TO SELF] ;376 71770 SOSN
1516,2622,2635,4352,1304,1304,1637,1304,0254|7858| [FETCH MEM(W)] [SOXX] [SXG] [BACK TO SELF] ;377 71774 SOSG
1516,2622,2637,4352,1304,1304,1637,1304,0255|7859|
|0255|7860|.TOC 2, "Opcodes 400 - 437"
|0255|7861| [SETZX] [TO AC] ;400 72000 SETZ
2660,4343,1304,1304,1304,1304,1637,1304,0256|7862| [SETZX] [TO AC] ;401 72004 SETZI
2660,4343,1304,1304,1304,1304,1637,1304,0257|7863| [SETZX] [TO MEM] ;402 72010 SETZM
2660,4371,1304,1304,1304,1304,1637,1304,0258|7864| [SETZX] [TO BOTH] ;403 72014 SETZB
2660,4360,1304,1304,1304,1304,1637,1304,0259|7865| [FETCH AC&MEM] [ANDX] [TO AC] ;404 72020 AND
1510,2661,4343,1304,1304,1304,1637,1304,0260|7866| [FETCH AC&I] [ANDX] [TO AC] ;405 72024 ANDI
1526,2661,4343,1304,1304,1304,1637,1304,0261|7867| [FETCH AC&MEM(W)] [ANDX] [BACK TO MEM] ;406 72030 ANDM
1515,2661,4363,1304,1304,1304,1637,1304,0262|7868| [FETCH AC&MEM(W)] [ANDX] [TO BOTH] ;407 72034 ANDB
1515,2661,4360,1304,1304,1304,1637,1304,0263|7869| [FETCH AC&MEM] [ANDCAX] [TO AC] ;410 72040 ANDCA
1510,2662,4343,1304,1304,1304,1637,1304,0264|7870| [FETCH AC&I] [ANDCAX] [TO AC] ;411 72044 ANDCAI
1526,2662,4343,1304,1304,1304,1637,1304,0265|7871| [FETCH AC&MEM(W)] [ANDCAX] [BACK TO MEM] ;412 72050 ANDCAM
1515,2662,4363,1304,1304,1304,1637,1304,0266|7872| [FETCH AC&MEM(W)] [ANDCAX] [TO BOTH] ;413 72054 ANDCAB
1515,2662,4360,1304,1304,1304,1637,1304,0267|7873| [FETCH MEM] [TO AC] ;414 72060 SETM
1511,4343,1304,1304,1304,1304,1637,1304,0268|7874| [XMOVEI] [MCE] [TO AC] ;415 72064 SETMI XMOVEI
2663,1304,4343,1304,1304,1304,1637,1304,0269|7875| [FETCH MEM(W)] [BACK TO MEM] ;416 72070 SETMM
1516,4363,1304,1304,1304,1304,1637,1304,0270|7876| [FETCH MEM(W)] [TO BOTH] ;417 72074 SETMB
1516,4360,1304,1304,1304,1304,1637,1304,0271|7877| [FETCH AC&MEM] [ANDCMX] [TO AC] ;420 72100 ANDCM
1510,2665,4343,1304,1304,1304,1637,1304,0272|7878| [FETCH AC&I] [ANDCMX] [TO AC] ;421 72104 ANDCMI
1526,2665,4343,1304,1304,1304,1637,1304,0273|7879| [FETCH AC&MEM(W)] [ANDCMX] [BACK TO MEM] ;422 72110 ANDCMM
1515,2665,4363,1304,1304,1304,1637,1304,0274|7880| [FETCH AC&MEM(W)] [ANDCMX] [TO BOTH] ;423 72114 ANDCMB
1515,2665,4360,1304,1304,1304,1637,1304,0275|7881| [TO NOWHERE] ;424 72120 SETA (no-op)
4127,1304,1304,1304,1304,1304,1637,1304,0276|7882| [TO NOWHERE] ;425 72124 SETAI (no-op)
4127,1304,1304,1304,1304,1304,1637,1304,0277|7883| [FETCH AC] [TO MEM] ;426 72130 SETAM (= MOVEM)
1531,4371,1304,1304,1304,1304,1637,1304,0278|7884| [FETCH AC] [TO MEM] ;427 72134 SETAB (= MOVEM)
1531,4371,1304,1304,1304,1304,1637,1304,0279|7885| [FETCH AC&MEM] [XORX] [TO AC] ;430 72140 XOR
1510,2666,4343,1304,1304,1304,1637,1304,0280|7886| [FETCH AC&I] [XORX] [TO AC] ;431 72144 XORI
1526,2666,4343,1304,1304,1304,1637,1304,0281|7887| [FETCH AC&MEM(W)] [XORX] [BACK TO MEM] ;432 72150 XORM
1515,2666,4363,1304,1304,1304,1637,1304,0282|7888| [FETCH AC&MEM(W)] [XORX] [TO BOTH] ;433 72154 XORB
1515,2666,4360,1304,1304,1304,1637,1304,0283|7889| [FETCH AC&MEM] [IORX] [TO AC] ;434 72160 IOR
1510,2670,4343,1304,1304,1304,1637,1304,0284|7890| [FETCH AC&I] [IORX] [TO AC] ;435 72164 IORI
1526,2670,4343,1304,1304,1304,1637,1304,0285|7891| [FETCH AC&MEM(W)] [IORX] [BACK TO MEM] ;436 72170 10RM
1515,2670,4363,1304,1304,1304,1637,1304,0286|7892| [FETCH AC&MEM(W)] [IORX] [TO BOTH] ;437 72174 IORB
1515,2670,4360,1304,1304,1304,1637,1304,0287|7893|
|0287|7894|.TOC 2, "Opcodes 440 - 477"
|0287|7895| [FETCH AC&MEM] [ANDCBX] [TO AC] ;440 72200 ANDCB
1510,2671,4343,1304,1304,1304,1637,1304,0288|7896| [FETCH AC&I] [ANDCBX] [TO AC] ;441 72204 ANDCBI
1526,2671,4343,1304,1304,1304,1637,1304,0289|7897| [FETCH AC&MEM(W)] [ANDCBX] [BACK TO MEM] ;442 72210 ANDCBM
1515,2671,4363,1304,1304,1304,1637,1304,0290|7898| [FETCH AC&MEM(W)] [ANDCBX] [TO BOTH] ;443 72214 ANDCBB
1515,2671,4360,1304,1304,1304,1637,1304,0291|7899| [FETCH AC&MEM] [EQVX] [TO AC] ;444 72220 EQV
1510,2673,4343,1304,1304,1304,1637,1304,0292|7900| [FETCH AC&I] [EQVX] [TO AC] ;445 72224 EQVI
1526,2673,4343,1304,1304,1304,1637,1304,0293|7901| [FETCH AC&MEM(W)] [EQVX] [BACK TO MEM] ;446 72230 EQVM
1515,2673,4363,1304,1304,1304,1637,1304,0294|7902| [FETCH AC&MEM(W)] [EQVX] [TO BOTH] ;447 72234 EQVB
1515,2673,4360,1304,1304,1304,1637,1304,0295|7903| [FETCH AC] [SETCAX] [TO AC] ;450 72240 SETCA
1531,2674,4343,1304,1304,1304,1637,1304,0296|7904| [FETCH AC] [SETCAX] [TO AC] ;451 72244 SETCAI
1531,2674,4343,1304,1304,1304,1637,1304,0297|7905| [FETCH AC] [SETCAX] [TO MEM] ;452 72250 SETCAM
1531,2674,4371,1304,1304,1304,1637,1304,0298|7906| [FETCH AC] [SETCAX] [TO BOTH] ;453 72254 SETCAB
1531,2674,4360,1304,1304,1304,1637,1304,0299|7907| [FETCH AC&MEM] [ORCAX] [TO AC] ;454 72260 ORCA
1510,2675,4343,1304,1304,1304,1637,1304,0300|7908| [FETCH AC&I] [ORCAX] [TO AC] ;455 72264 ORCAI
1526,2675,4343,1304,1304,1304,1637,1304,0301|7909| [FETCH AC&MEM(W)] [ORCAX] [BACK TO MEM] ;456 72270 ORCAM
1515,2675,4363,1304,1304,1304,1637,1304,0302|7910| [FETCH AC&MEM(W)] [ORCAX] [TO BOTH] ;457 72274 ORCAB
1515,2675,4360,1304,1304,1304,1637,1304,0303|7911| [FETCH MEM] [SETCMX] [TO AC] ;460 72300 SETCM
1511,2676,4343,1304,1304,1304,1637,1304,0304|7912| [FETCH I] [SETCMX] [TO AC] ;461 72304 SETCMI
1527,2676,4343,1304,1304,1304,1637,1304,0305|7913| [FETCH MEM(W)] [SETCMX] [BACK TO MEM] ;462 72310 SETCMM
1516,2676,4363,1304,1304,1304,1637,1304,0306|7914| [FETCH MEM(W)] [SETCMX] [TO BOTH] ;463 72314 SETCMB
1516,2676,4360,1304,1304,1304,1637,1304,0307|7915| [FETCH AC&MEM] [ORCMX] [TO AC] ;464 72320 ORCM
1510,2677,4343,1304,1304,1304,1637,1304,0308|7916| [FETCH AC&I] [ORCMX] [TO AC] ;465 72324 ORCMI
1526,2677,4343,1304,1304,1304,1637,1304,0309|7917| [FETCH AC&MEM(W)] [ORCMX] [BACK TO MEM] ;466 72330 ORCMM
1515,2677,4363,1304,1304,1304,1637,1304,0310|7918| [FETCH AC&MEM(W)] [ORCMX] [TO BOTH] ;467 72334 ORCMB
1515,2677,4360,1304,1304,1304,1637,1304,0311|7919| [FETCH AC&MEM] [ORCBX] [TO AC] ;470 72340 ORCB
1510,2700,4343,1304,1304,1304,1637,1304,0312|7920| [FETCH AC&I] [ORCBX] [TO AC] ;471 72344 ORCBI
1526,2700,4343,1304,1304,1304,1637,1304,0313|7921| [FETCH AC&MEM(W)] [ORCBX] [BACK TO MEM] ;472 72350 ORCBM
1515,2700,4363,1304,1304,1304,1637,1304,0314|7922| [FETCH AC&MEM(W)] [ORCBX] [TO BOTH] ;473 72354 ORCBB
1515,2700,4360,1304,1304,1304,1637,1304,0315|7923| [SETOX] [TO AC] ;474 72360 SETO
2701,4343,1304,1304,1304,1304,1637,1304,0316|7924| [SETOX] [TO AC] ;475 72364 SETOI
2701,4343,1304,1304,1304,1304,1637,1304,0317|7925| [SETOX] [TO MEM] ;476 72370 SETOM
2701,4371,1304,1304,1304,1304,1637,1304,0318|7926| [SETOX] [TO BOTH] ;477 72374 SETOB
2701,4360,1304,1304,1304,1304,1637,1304,0319|7927|
|0319|7928|.TOC 2, "Opcodes 500 - 537"
|0319|7929| [FETCH AC&MEM] [HLL] [TO AC] ;500 72400 HLL
1510,2702,4343,1304,1304,1304,1637,1304,0320|7930| [FETCH AC] [XHLLI] [TO AC.0] ;501 72404 HLLI XHLLI
1531,2703,4342,1304,1304,1304,1637,1304,0321|7931| [FETCH AC&MEM(W)] [HLLM] [TO MEM] ;502 72410 HLLM
1515,2711,4371,1304,1304,1304,1637,1304,0322|7932| [FETCH MEM(W)] [BACK TO SELF] ;503 72414 HLLS
1516,4352,1304,1304,1304,1304,1637,1304,0323|7933| [FETCH AC&MEM] [HRL] [AC TO AC] ;504 72420 HRL
1510,2712,4350,1304,1304,1304,1637,1304,0324|7934| [FETCH AC&I] [HRL] [AC TO AC] ;505 72424 HRLI
1526,2712,4350,1304,1304,1304,1637,1304,0325|7935| [FETCH AC&MEM(W)] [HRLM] [TO MEM] ;506 72430 HRLM
1515,2710,4371,1304,1304,1304,1637,1304,0326|7936| [FETCH AC&MEM(W)] [HRLS] [BACK TO SELF] ;507 72434 HRLS
1515,2713,4352,1304,1304,1304,1637,1304,0327|7937| [FETCH MEM] [HLLZX] [MCE] [TO AC] ;510 72440 HLLZ
1511,2714,1304,4343,1304,1304,1637,1304,0328|7938| [FETCH I] [HLLZX] [MCE] [TO AC] ;511 72444 HLLZI
1527,2714,1304,4343,1304,1304,1637,1304,0329|7939| [FETCH AC] [HLLZX] [MCE] [TO MEM] ;512 72450 HLLZM
1531,2714,1304,4371,1304,1304,1637,1304,0330|7940| [FETCH MEM(W)] [HLLZX] [MCE] [BACK TO SELF] ;513 72454 HLLZS
1516,2714,1304,4352,1304,1304,1637,1304,0331|7941| [FETCH MEM] [MOVSX] [HLLZX] [TO AC] ;514 72460 HRLZ
1511,2064,2714,4343,1304,1304,1637,1304,0332|7942|.IF/FAST
|0332|7943| [MOVSI] ;515 72464 HRLZI
2062,1304,1304,1304,1304,1304,1637,1304,0333|7944|.ENDIF/FAST
|0333|7945|.IFNOT/FAST
|0333|7946| [FETCH I] [MOVSX] [HLLZX] [TO AC] ;515 72464 HRLZI
|0333|7947|.ENDIF/FAST
|0333|7948| [FETCH AC] [MOVSX] [HLLZX] [TO MEM] ;516 72470 HRLZM
1531,2064,2714,4371,1304,1304,1637,1304,0334|7949| [FETCH MEM(W)] [MOVSX] [HLLZX] [BACK TO SELF] ;517 72474 HRLZS
1516,2064,2714,4352,1304,1304,1637,1304,0335|7950| [FETCH MEM] [HLLOX] [MCE] [TO AC] ;520 72500 HLLO
1511,2717,1304,4343,1304,1304,1637,1304,0336|7951| [FETCH I] [HLLOX] [MCE] [TO AC] ;521 72504 HLLOI
1527,2717,1304,4343,1304,1304,1637,1304,0337|7952| [FETCH AC] [HLLOX] [MCE] [TO MEM] ;522 72510 HLLOM
1531,2717,1304,4371,1304,1304,1637,1304,0338|7953| [FETCH MEM(W)] [HLLOX] [MCE] [BACK TO SELF] ;523 72514 HLLOS
1516,2717,1304,4352,1304,1304,1637,1304,0339|7954| [FETCH MEM] [MOVSX] [HLLOX] [TO AC] ;524 72520 HRLO
1511,2064,2717,4343,1304,1304,1637,1304,0340|7955| [FETCH I] [MOVSX] [HLLOX] [TO AC] ;525 72524 HRLOI
1527,2064,2717,4343,1304,1304,1637,1304,0341|7956| [FETCH AC] [MOVSX] [HLLOX] [TO MEM] ;526 72530 HRLOM
1531,2064,2717,4371,1304,1304,1637,1304,0342|7957| [FETCH MEM(W)] [MOVSX] [HLLOX] [BACK TO SELF] ;527 72534 HRlOS
1516,2064,2717,4352,1304,1304,1637,1304,0343|7958| [FETCH MEM] [HLLEX] [MCE] [TO AC] ;530 72540 HLLE
1511,2716,1304,4343,1304,1304,1637,1304,0344|7959| [FETCH I] [HLLEX] [MCE] [TO AC] ;531 72544 HLLEI
1527,2716,1304,4343,1304,1304,1637,1304,0345|7960| [FETCH AC(MX)] [HLLEX] [MCE] [TO MEM] ;532 72550 HLLEM
1532,2716,1304,4371,1304,1304,1637,1304,0346|7961| [FETCH MEM(W)] [HLLEX] [MCE] [BACK TO SELF] ;533 72554 HLLES
1516,2716,1304,4352,1304,1304,1637,1304,0347|7962| [FETCH MEM] [MOVSX] [HRLEX] [TO AC] ;534 72560 HRLE
1511,2064,2715,4343,1304,1304,1637,1304,0348|7963| [FETCH I] [MOVSX] [HRLEX] [TO AC] ;535 72564 HRLEI
1527,2064,2715,4343,1304,1304,1637,1304,0349|7964| [FETCH AC(MX)] [MOVSX] [HRLEX] [TO MEM] ;536 72570 HRLEM
1532,2064,2715,4371,1304,1304,1637,1304,0350|7965| [FETCH MEM(W)] [MOVSX] [HRLEX] [BACK TO SELF] ;537 72574 HRLES
1516,2064,2715,4352,1304,1304,1637,1304,0351|7966|
|0351|7967|.TOC 2, "Opcodes 540 - 577"
|0351|7968| [FETCH AC&MEM] [HRR] [TO AC] ;540 72600 HRR
1510,2720,4343,1304,1304,1304,1637,1304,0352|7969| [FETCH AC&I] [HRR] [TO AC] ;541 72604 HRRI
1526,2720,4343,1304,1304,1304,1637,1304,0353|7970| [FETCH AC&MEM(W)] [HRRM] [TO MEM] ;542 72610 HRRM
1515,2722,4371,1304,1304,1304,1637,1304,0354|7971| [FETCH MEM(W)] [BACK TO SELF] ;543 72614 HRRS
1516,4352,1304,1304,1304,1304,1637,1304,0355|7972| [FETCH AC&MEM] [HLR] [AC TO AC] ;544 72620 HLR
1510,2723,4350,1304,1304,1304,1637,1304,0356|7973| [FETCH AC&I] [HLR] [AC TO AC] ;545 72624 HLRI
1526,2723,4350,1304,1304,1304,1637,1304,0357|7974| [FETCH AC&MEM(W)] [HLRM] [TO MEM] ;546 72630 HLRM
1515,2721,4371,1304,1304,1304,1637,1304,0358|7975| [FETCH AC&MEM(W)] [HLRS] [BACK TO SELF] ;547 72634 HLRS
1515,2724,4352,1304,1304,1304,1637,1304,0359|7976|
|0359|7977| [FETCH MEM] [HRRZX] [MCE] [TO AC] ;550 72640 HRRZ
1511,2725,1304,4343,1304,1304,1637,1304,0360|7978|.IF/FAST
|0360|7979| [MOVEI] ;551 72644 HRRZI
2061,1304,1304,1304,1304,1304,1637,1304,0361|7980|.ENDIF/FAST
|0361|7981|.IFNOT/FAST
|0361|7982| [FETCH I] [HRRZX] [MCE] [TO AC] ;551 72644 HRRZI
|0361|7983|.ENDIF/FAST
|0361|7984| [FETCH AC] [HRRZX] [MCE] [TO MEM] ;552 72650 HRRZM
1531,2725,1304,4371,1304,1304,1637,1304,0362|7985| [FETCH MEM(W)] [HRRZX] [MCE] [BACK TO SELF] ;553 72654 HRRZS
1516,2725,1304,4352,1304,1304,1637,1304,0363|7986| [FETCH MEM] [MOVSX] [HRRZX] [TO AC] ;554 72660 HlRZ
1511,2064,2725,4343,1304,1304,1637,1304,0364|7987| [FETCH I] [MOVSX] [HRRZX] [TO AC] ;555 72664 HlRZI
1527,2064,2725,4343,1304,1304,1637,1304,0365|7988| [FETCH AC] [MOVSX] [HRRZX] [TO MEM] ;556 72610 HLRZM
1531,2064,2725,4371,1304,1304,1637,1304,0366|7989| [FETCH MEM(W)] [MOVSX] [HRRZX] [BACK TO SELF] ;557 72614 HLRZS
1516,2064,2725,4352,1304,1304,1637,1304,0367|7990| [FETCH MEM] [HRROX] [MCE] [TO AC] ;560 72700 HRRO
1511,2727,1304,4343,1304,1304,1637,1304,0368|7991| [FETCH I] [HRROX] [MCE] [TO AC] ;561 72704 HRROI
1527,2727,1304,4343,1304,1304,1637,1304,0369|7992| [FETCH AC] [HRROX] [MCE] [TO MEM] ;562 72710 HRROM
1531,2727,1304,4371,1304,1304,1637,1304,0370|7993| [FETCH MEM(W)] [HRROX] [MCE] [BACK TO SELF] ;563 72714 HRROS
1516,2727,1304,4352,1304,1304,1637,1304,0371|7994| [FETCH MEM] [MOVSX] [HRROX] [TO AC] ;564 72720 HLRO
1511,2064,2727,4343,1304,1304,1637,1304,0372|7995| [FETCH I] [MOVSX] [HRROX] [TO AC] ;565 72724 HLROI
1527,2064,2727,4343,1304,1304,1637,1304,0373|7996| [FETCH AC] [MOVSX] [HRROX] [TO MEM] ;566 12730 HLROM
1531,2064,2727,4371,1304,1304,1637,1304,0374|7997| [FETCH MEM(W)] [MOVSX] [HRROX] [BACK TO SELF] ;567 72734 HLROS
1516,2064,2727,4352,1304,1304,1637,1304,0375|7998| [FETCH MEM] [HRREX] [MCE] [TO AC] ;570 72740 HRRE
1511,2726,1304,4343,1304,1304,1637,1304,0376|7999| [FETCH I] [HRREX] [MCE] [TO AC] ;571 72744 HRREI
1527,2726,1304,4343,1304,1304,1637,1304,0377|8000| [FETCH AC(MX)] [HRREX] [MCE] [TO MEM] ;572 72750 HRREM
1532,2726,1304,4371,1304,1304,1637,1304,0378|8001| [FETCH MEM(W)] [HRREX] [MCE] [BACK TO SELF] ;573 72754 HRRES
1516,2726,1304,4352,1304,1304,1637,1304,0379|8002| [FETCH MEM] [MOVSX] [HRREX] [TO AC] ;574 72760 HLRE
1511,2064,2726,4343,1304,1304,1637,1304,0380|8003| [FETCH I] [MOVSX] [HRREX] [TO AC] ;575 72764 HLREI
1527,2064,2726,4343,1304,1304,1637,1304,0381|8004| [FETCH AC(MX)] [MOVSX] [HRREX] [TO MEM] ;576 72770 HLREM
1532,2064,2726,4371,1304,1304,1637,1304,0382|8005| [FETCH MEM(W)] [MOVSX] [HRREX] [BACK TO SELF] ;577 72774 HLRES
1516,2064,2726,4352,1304,1304,1637,1304,0383|8006|
|0383|8007|.TOC 2, "Opcodes 600 - 637"
|0383|8008| [TO NOWHERE] ;600 73000 TRN
4127,1304,1304,1304,1304,1304,1637,1304,0384|8009| [TO NOWHERE] ;601 73004 TLN
4127,1304,1304,1304,1304,1304,1637,1304,0385|8010| [TRX] [TXE] [IFETCH] ;602 73010 TRNE
2730,2741,1420,1304,1304,1304,1637,1304,0386|8011| [TLX] [TXE] [IFETCH] ;603 73014 TLNE
2731,2741,1420,1304,1304,1304,1637,1304,0387|8012| [TRX] [TXA] [IFETCH] ;604 73020 TRNA
2730,2742,1420,1304,1304,1304,1637,1304,0388|8013| [TLX] [TXA] [IFETCH] ;605 73024 TLNA
2731,2742,1420,1304,1304,1304,1637,1304,0389|8014| [TRX] [TXN] [IFETCH] ;606 73030 TRNN
2730,2743,1420,1304,1304,1304,1637,1304,0390|8015| [TLX] [TXN] [IFETCH] ;607 73034 TLNN
2731,2743,1420,1304,1304,1304,1637,1304,0391|8016| [TDX] [IFETCH] ;610 73040 TDN
2733,1420,1304,1304,1304,1304,1637,1304,0392|8017| [TSX] [IFETCH] ;611 73044 TSN
2736,1420,1304,1304,1304,1304,1637,1304,0393|8018| [TDX] [TXE] [IFETCH] ;612 73050 TDNE
2733,2741,1420,1304,1304,1304,1637,1304,0394|8019| [TSX] [TXE] [IFETCH] ;613 73054 TSNE
2736,2741,1420,1304,1304,1304,1637,1304,0395|8020| [TDX] [TXA] [IFETCH] ;614 73060 TDNA
2733,2742,1420,1304,1304,1304,1637,1304,0396|8021| [TSX] [TXA] [IFETCH] ;615 73064 TSNA
2736,2742,1420,1304,1304,1304,1637,1304,0397|8022| [TDX] [TXN] [IFETCH] ;616 73070 TDNN
2733,2743,1420,1304,1304,1304,1637,1304,0398|8023| [TSX] [TXN] [IFETCH] ;617 73074 TSNN
2736,2743,1420,1304,1304,1304,1637,1304,0399|8024| [TRX] [TXZ] ;620 73100 TRZ
2730,2745,1304,1304,1304,1304,1637,1304,0400|8025| [TLX] [TXZ] ;621 73104 TLZ
2731,2745,1304,1304,1304,1304,1637,1304,0401|8026| [TRX] [TXE] [TXZ] ;622 73110 TRZE
2730,2741,2745,1304,1304,1304,1637,1304,0402|8027| [TLX] [TXE] [TXZ] ;623 73114 TLZE
2731,2741,2745,1304,1304,1304,1637,1304,0403|8028| [TRX] [TXA] [TXZ] ;624 73120 TRZA
2730,2742,2745,1304,1304,1304,1637,1304,0404|8029| [TLX] [TXA] [TXZ] ;625 73124 TLZA
2731,2742,2745,1304,1304,1304,1637,1304,0405|8030| [TRX] [TXN] [TXZ] ;626 73130 TRZN
2730,2743,2745,1304,1304,1304,1637,1304,0406|8031| [TLX] [TXN] [TXZ] ;627 73134 TLZN
2731,2743,2745,1304,1304,1304,1637,1304,0407|8032| [TDX] [TXZ] ;630 73140 TDZ
2733,2745,1304,1304,1304,1304,1637,1304,0408|8033| [TSX] [TXZ] ;631 73144 TSZ
2736,2745,1304,1304,1304,1304,1637,1304,0409|8034| [TDX] [TXE] [TXZ] ;632 73150 TDZE
2733,2741,2745,1304,1304,1304,1637,1304,0410|8035| [TSX] [TXE] [TXZ] ;633 73154 TSZE
2736,2741,2745,1304,1304,1304,1637,1304,0411|8036| [TDX] [TXA] [TXZ] ;634 73160 TDZA
2733,2742,2745,1304,1304,1304,1637,1304,0412|8037| [TSX] [TXA] [TXZ] ;635 73164 TSZA
2736,2742,2745,1304,1304,1304,1637,1304,0413|8038| [TDX] [TXN] [TXZ] ;636 73170 TDZN
2733,2743,2745,1304,1304,1304,1637,1304,0414|8039| [TSX] [TXN] [TXZ] ;637 73174 TSZN
2736,2743,2745,1304,1304,1304,1637,1304,0415|8040|
|0415|8041|.TOC 2, "Opcodes 640 - 677"
|0415|8042| [TRX] [TXC] ;640 73200 TRC
2730,2746,1304,1304,1304,1304,1637,1304,0416|8043| [TLX] [TXC] ;641 73204 TLC
2731,2746,1304,1304,1304,1304,1637,1304,0417|8044| [TRX] [TXE] [TXC] ;642 73210 TRCE
2730,2741,2746,1304,1304,1304,1637,1304,0418|8045| [TLX] [TXE] [TXC] ;643 73214 TLCE
2731,2741,2746,1304,1304,1304,1637,1304,0419|8046| [TRX] [TXA] [TXC] ;644 73220 TRCA
2730,2742,2746,1304,1304,1304,1637,1304,0420|8047| [TLX] [TXA] [TXC] ;645 73224 TLCA
2731,2742,2746,1304,1304,1304,1637,1304,0421|8048| [TRX] [TXN] [TXC] ;646 73230 TRCN
2730,2743,2746,1304,1304,1304,1637,1304,0422|8049| [TLX] [TXN] [TXC] ;647 73234 TLCN
2731,2743,2746,1304,1304,1304,1637,1304,0423|8050| [TDX] [TXC] ;650 73240 TDC
2733,2746,1304,1304,1304,1304,1637,1304,0424|8051| [TSX] [TXC] ;651 73244 TSC
2736,2746,1304,1304,1304,1304,1637,1304,0425|8052| [TDX] [TXE] [TXC] ;652 73250 TDCE
2733,2741,2746,1304,1304,1304,1637,1304,0426|8053| [TSX] [TXE] [TXC] ;653 73254 TSCE
2736,2741,2746,1304,1304,1304,1637,1304,0427|8054| [TDX] [TXA] [TXC] ;654 73260 TDCA
2733,2742,2746,1304,1304,1304,1637,1304,0428|8055| [TSX] [TXA] [TXC] ;655 73264 TSCA
2736,2742,2746,1304,1304,1304,1637,1304,0429|8056| [TDX] [TXN] [TXC] ;656 73270 TDCN
2733,2743,2746,1304,1304,1304,1637,1304,0430|8057| [TSX] [TXN] [TXC] ;651 73274 TSCN
2736,2743,2746,1304,1304,1304,1637,1304,0431|8058| [TRX] [TXO] ;660 73300 TRO
2730,2747,1304,1304,1304,1304,1637,1304,0432|8059| [TLX] [TXO] ;661 73304 TLO
2731,2747,1304,1304,1304,1304,1637,1304,0433|8060| [TRX] [TXE] [TXO] ;662 73310 TROE
2730,2741,2747,1304,1304,1304,1637,1304,0434|8061| [TLX] [TXE] [TXO] ;663 73314 TLOE
2731,2741,2747,1304,1304,1304,1637,1304,0435|8062| [TRX] [TXA] [TXO] ;664 73310 TROA
2730,2742,2747,1304,1304,1304,1637,1304,0436|8063| [TLX] [TXA] [TXO] ;665 73324 TLOA
2731,2742,2747,1304,1304,1304,1637,1304,0437|8064| [TRX] [TXN] [TXO] ;666 73330 TRON
2730,2743,2747,1304,1304,1304,1637,1304,0438|8065| [TLX] [TXN] [TXO] ;667 73334 TLON
2731,2743,2747,1304,1304,1304,1637,1304,0439|8066| [TDX] [TXO] ;670 73340 TDO
2733,2747,1304,1304,1304,1304,1637,1304,0440|8067| [TSX] [TXO] ;671 73344 TSO
2736,2747,1304,1304,1304,1304,1637,1304,0441|8068| [TDX] [TXE] [TXO] ;672 73350 TDOE
2733,2741,2747,1304,1304,1304,1637,1304,0442|8069| [TSX] [TXE] [TXO] ;673 73354 TSOE
2736,2741,2747,1304,1304,1304,1637,1304,0443|8070| [TDX] [TXA] [TXO] ;674 73360 TDOA
2733,2742,2747,1304,1304,1304,1637,1304,0444|8071| [TSX] [TXA] [TXO] ;675 73364 TSOA
2736,2742,2747,1304,1304,1304,1637,1304,0445|8072| [TDX] [TXN] [TXO] ;676 73370 TDON
2733,2743,2747,1304,1304,1304,1637,1304,0446|8073| [TSX] [TXN] [TXO] ;677 73374 TSON
2736,2743,2747,1304,1304,1304,1637,1304,0447|8074|
|0447|8075|.TOC 2, "Opcodes 700 - 737"
|0447|8076| [IO] ;700 73400 IO
3064,1304,1304,1304,1304,1304,1637,1304,0448|8077| [IO] ;701 73404 IO
3064,1304,1304,1304,1304,1304,1637,1304,0449|8078| [IO] ;702 73410 IO
3064,1304,1304,1304,1304,1304,1637,1304,0450|8079| [IO] ;703 73414 IO
3064,1304,1304,1304,1304,1304,1637,1304,0451|8080| [IO] ;704 73420 IO
3064,1304,1304,1304,1304,1304,1637,1304,0452|8081| [IO] ;705 73424 IO
3064,1304,1304,1304,1304,1304,1637,1304,0453|8082| [IO] ;706 73430 IO
3064,1304,1304,1304,1304,1304,1637,1304,0454|8083| [IO] ;707 73434 IO
3064,1304,1304,1304,1304,1304,1637,1304,0455|8084| [IO EFA] [FETCH AC&IO] [TIOE] ;710 73440 TIOE
4030,1534,4032,1304,1304,1304,1637,1304,0456|8085| [IO EFA] [FETCH AC&IO] [TION] ;711 73444 TION
4030,1534,4034,1304,1304,1304,1637,1304,0457|8086| [IO EFA] [FETCH IO] [TO AC] ;712 73450 RDIO
4030,1535,4343,1304,1304,1304,1637,1304,0458|8087| [IO EFA] [WRIO] ;713 73454 WRIO
4030,4036,1304,1304,1304,1304,1637,1304,0459|8088| [IO EFA] [FETCH AC&IO] [BSIO] ;714 73460 BSIO
4030,1534,4125,1304,1304,1304,1637,1304,0460|8089| [IO EFA] [FETCH AC&IO] [BCIO] ;715 73464 BCIO
4030,1534,4126,1304,1304,1304,1637,1304,0461|8090| [IO] ;716 73470 IO
3064,1304,1304,1304,1304,1304,1637,1304,0462|8091| [IO] ;717 73474 IO
3064,1304,1304,1304,1304,1304,1637,1304,0463|8092| [MUUO] ;720 73500 TIOEB
1637,1304,1304,1304,1304,1304,1637,1304,0464|8093| [MUUO] ;721 73504 TIONB
1637,1304,1304,1304,1304,1304,1637,1304,0465|8094|.IF/DEBUGTTY
|0465|8095| [RDTTY] ;722 73510 RDIOB
3457,1304,1304,1304,1304,1304,1637,1304,0466|8096|.ENDIF/DEBUGTTY
|0466|8097|.IFNOT/DEBUGTTY
|0466|8098| [MUUO] ;722 73510 RDIOB
|0466|8099|.ENDIF/DEBUGTTY
|0466|8100| [MUUO] ;723 73514 WRIOB
1637,1304,1304,1304,1304,1304,1637,1304,0467|8101| [MUUO] ;724 73520 BSIOB
1637,1304,1304,1304,1304,1304,1637,1304,0468|8102| [MUUO] ;725 73524 BCIOB
1637,1304,1304,1304,1304,1304,1637,1304,0469|8103| [IO] ;726 73530 IO
3064,1304,1304,1304,1304,1304,1637,1304,0470|8104| [IO] ;727 73530 IO
3064,1304,1304,1304,1304,1304,1637,1304,0471|8105| [IO] ;730 73530 IO
3064,1304,1304,1304,1304,1304,1637,1304,0472|8106| [IO] ;731 73530 IO
3064,1304,1304,1304,1304,1304,1637,1304,0473|8107| [IO] ;732 73530 IO
3064,1304,1304,1304,1304,1304,1637,1304,0474|8108| [IO] ;733 73530 IO
3064,1304,1304,1304,1304,1304,1637,1304,0475|8109| [IO] ;734 73530 IO
3064,1304,1304,1304,1304,1304,1637,1304,0476|8110| [IO] ;735 73530 IO
3064,1304,1304,1304,1304,1304,1637,1304,0477|8111| [IO] ;736 73530 IO
3064,1304,1304,1304,1304,1304,1637,1304,0478|8112| [IO] ;737 73530 IO
3064,1304,1304,1304,1304,1304,1637,1304,0479|8113|
|0479|8114|.TOC 2, "Opcodes 740 - 777"
|0479|8115|.IF/FTCIS
|0479|8116| [CIS SETUP] [MOVC] ;740 73740 IO
2752,2775,1304,1304,1304,1304,1637,1304,0480|8117| [CIS SETUP] [CMPC] ;741 73744 IO
2752,3005,1304,1304,1304,1304,1637,1304,0481|8118| [CIS SETUP] [MOVCV] ;742 73610 IO
2752,3017,1304,1304,1304,1304,1637,1304,0482|8119| [CIS SETUP] [CMPCV] ;743 73614 IO
2752,3017,1304,1304,1304,1304,1637,1304,0483|8120| [CIS SETUP] [CMPND] ;744 73620 IO
2752,3017,1304,1304,1304,1304,1637,1304,0484|8121| [CIS SETUP] [ADDND] ;745 73624 IO
2752,3017,1304,1304,1304,1304,1637,1304,0485|8122| [CIS SETUP] [SUBND] ;746 73630 IO
2752,3017,1304,1304,1304,1304,1637,1304,0486|8123| [CIS SETUP] [MOVND] ;747 73634 IO
2752,3017,1304,1304,1304,1304,1637,1304,0487|8124| [CIS SETUP] [CVTNDB] ;750 73640 IO
2752,3017,1304,1304,1304,1304,1637,1304,0488|8125| [CIS SETUP] [CMPP] ;751 73644 IO
2752,3017,1304,1304,1304,1304,1637,1304,0489|8126| [CIS SETUP] [ADDP] ;752 73650 IO
2752,3017,1304,1304,1304,1304,1637,1304,0490|8127| [CIS SETUP] [SUBP] ;753 73654 IO
2752,3017,1304,1304,1304,1304,1637,1304,0491|8128| [CIS SETUP] [MOVP] ;754 73660 IO
2752,3017,1304,1304,1304,1304,1637,1304,0492|8129| [CIS SETUP] [CHOP] ;755 73664 IO
2752,3017,1304,1304,1304,1304,1637,1304,0493|8130|.ENDIF/FTCIS
|0493|8131|.IFNOT/FTCIS
|0493|8132| [IO 4] ;740 73600 IO
|0493|8133| [IO 4] ;741 73604 IO
|0493|8134| [IO 4] ;742 736IO IO
|0493|8135| [IO 4] ;743 73614 IO
|0493|8136| [IO 4] ;744 73620 IO
|0493|8137| [IO 4] ;745 73624 IO
|0493|8138| [IO 4] ;746 73630 IO
|0493|8139| [IO 4] ;747 73634 IO
|0493|8140| [IO 4] ;750 73640 IO
|0493|8141| [IO 4] ;751 73644 IO
|0493|8142| [IO 4] ;752 73650 IO
|0493|8143| [IO 4] ;753 73654 IO
|0493|8144| [IO 4] ;754 73660 IO
|0493|8145| [IO 4] ;755 73664 IO
|0493|8146|.ENDIF/FTCIS
|0493|8147| [IO 4] ;756 73670 IO
3070,1304,1304,1304,1304,1304,1637,1304,0494|8148| [IO 4] ;757 73674 IO
3070,1304,1304,1304,1304,1304,1637,1304,0495|8149| [IO 4] ;760 73700 IO
3070,1304,1304,1304,1304,1304,1637,1304,0496|8150| [IO 4] ;761 73704 IO
3070,1304,1304,1304,1304,1304,1637,1304,0497|8151| [IO 4] ;762 73110 IO
3070,1304,1304,1304,1304,1304,1637,1304,0498|8152| [IO 4] ;763 73714 IO
3070,1304,1304,1304,1304,1304,1637,1304,0499|8153| [IO 4] ;764 73720 IO
3070,1304,1304,1304,1304,1304,1637,1304,0500|8154| [IO 4] ;765 73724 IO
3070,1304,1304,1304,1304,1304,1637,1304,0501|8155| [IO 4] ;766 73730 IO
3070,1304,1304,1304,1304,1304,1637,1304,0502|8156| [IO 4] ;767 73734 IO
3070,1304,1304,1304,1304,1304,1637,1304,0503|8157| [IO 4] ;770 73740 IO
3070,1304,1304,1304,1304,1304,1637,1304,0504|8158| [IO 4] ;771 73744 IO
3070,1304,1304,1304,1304,1304,1637,1304,0505|8159| [IO 4] ;772 73750 IO
3070,1304,1304,1304,1304,1304,1637,1304,0506|8160| [IO 4] ;773 73754 IO
3070,1304,1304,1304,1304,1304,1637,1304,0507|8161| [IO 4] ;774 73760 IO
3070,1304,1304,1304,1304,1304,1637,1304,0508|8162| [IO 4] ;775 73764 IO
3070,1304,1304,1304,1304,1304,1637,1304,0509|8163| [IO 4] ;776 73770 IO
3070,1304,1304,1304,1304,1304,1637,1304,0510|8164| [IO 4] ;777 73774 IO
3070,1304,1304,1304,1304,1304,1637,1304,0511|8165|
|0511|8166|;END OF FILE
|0511|8167|