# Model → FPGA → RF → Measurement
This page is the **core of the course**. It describes how a signal travels from a mathematical idea to a real RF waveform and back to data.
---
## End-to-end system view
```mermaid
flowchart TB
MODEL["1. Reference model
MATLAB / Simulink, ideal floating-point behavior and expected spectrum"]
FIXED["2. Fixed-point model
word length, scaling, overflow margins and quantization noise"]
FPGA["3. FPGA pipeline
DDS, mixer, FIR, interpolation, AXI-Stream and latency"]
RF["4. RF transmit path
AD9363 DAC, mixer, filters, gain and frequency plan"]
CHANNEL["5. Physical channel
coax with attenuation or controlled over-the-air path"]
RX["6. Independent receiver
RTL-SDR / HDSDR observation outside the main board"]
IQ["7. IQ recording
WAV / RAW / CI16 data with sample-rate and frequency metadata"]
ANALYSIS["8. Offline analysis
FFT, EVM, BER, SNR, spurs and repeatability checks"]
DECISION["9. Engineering decision
accept, retune, redesign or repeat the experiment"]
MODEL --> FIXED --> FPGA --> RF --> CHANNEL --> RX --> IQ --> ANALYSIS --> DECISION
DECISION -. algorithm redesign .-> MODEL
DECISION -. numeric scaling fix .-> FIXED
DECISION -. RF gain retuning .-> RF
```
---
## Engineering interpretation
| Stage | Key risk | What you verify |
|---|---|---|
| Model | wrong assumptions | spectrum, waveform |
| Fixed-point | quantization | SNR degradation |
| FPGA | architecture | real-time capability |
| RF | analog effects | distortions, gain |
| Receiver | measurement errors | independent observation |
| Analysis | wrong metrics | false conclusions |
---
## FPGA signal path
```mermaid
flowchart TB
IN["1. Input sample stream
test vector, DMA stream or internally generated waveform"]
DDS["2. DDS / NCO
phase accumulator, LUT/CORDIC and frequency word"]
MIX["3. Digital mixer
complex multiplication and frequency translation"]
FIR["4. FIR filter
pulse shaping, low-pass filtering or image rejection"]
RATE["5. Rate adaptation
interpolation / decimation for the RF frontend rate"]
AXI["6. AXI-Stream output
valid/ready timing, framing and backpressure"]
OUT["7. AD9363 interface
samples delivered to the RF transmit path"]
IN --> DDS --> MIX --> FIR --> RATE --> AXI --> OUT
```
---
## SDR TX/RX chain
```mermaid
flowchart TB
SRC["1. Source and framing
tone, packet, payload or waveform definition"]
MOD["2. Modulation and shaping
BPSK/QPSK/QAM/FSK plus pulse-shaping filters"]
TXRF["3. TX path
DUC, DAC, mixer, filters and transmit gain"]
CH["4. Channel
coax, attenuator, antenna path, noise and offsets"]
RXRF["5. RX path
LNA, mixer, ADC, DDC and AGC"]
SYNC["6. Synchronization and demodulation
CFO, timing, frame sync, matched filter and bits"]
VALID["7. Validation and replay
IQ taps, FFT, EVM, BER, reports and notebooks"]
SRC --> MOD --> TXRF --> CH --> RXRF --> SYNC --> VALID
VALID -. model tuning .-> MOD
VALID -. hardware tuning .-> RXRF
```
---
## Measurement loop
```mermaid
flowchart LR
TX["Zynq TX
configured waveform"]
AIR["RF path
safe level"]
RTL["RTL-SDR
external RX"]
HDSDR["HDSDR
observe"]
FILE["IQ file
record"]
MATLAB["MATLAB / Python
analyze"]
TX --> AIR --> RTL --> HDSDR --> FILE --> MATLAB
MATLAB -. feedback .-> TX
```
---
## Key takeaway
```text
Model → Hardware → Measurement → Decision
```
If any stage is skipped, the engineering result is unreliable.