(kicad_pcb (version 20221018) (generator pcbnew) (general (thickness 2.0) (legacy_teardrops no) ) (paper "A1") (title_block (title "LightRail AI Gen3 - LR-P8A Photonic Accelerator") (date "2026-04-08") (rev "A01") (company "LightRail") (comment 1 "PCIe Full-Height Half-Length (FHHL): 167.65 x 111.15 mm") (comment 2 "4-layer Megtron 6 stackup -- see Setup > Board Stackup") (comment 3 "PLACEHOLDERS: replace footprints with vendor parts before fab") ) ;; ------------------------------------------------------------------------- ;; Layer definitions ;; ------------------------------------------------------------------------- (layers (0 "F.Cu" signal) (1 "In1.Cu" power "GND plane") (2 "In2.Cu" power "PWR plane") (31 "B.Cu" signal) (32 "B.Adhes" user "B.Adhesive") (33 "F.Adhes" user "F.Adhesive") (34 "B.Paste" user) (35 "F.Paste" user) (36 "B.SilkS" user "B.Silkscreen") (37 "F.SilkS" user "F.Silkscreen") (38 "B.Mask" user) (39 "F.Mask" user) (40 "Dwgs.User" user "User.Drawings") (41 "Cmts.User" user "User.Comments") (44 "Edge.Cuts" user) (45 "Margin" user) (46 "B.CrtYd" user "B.Courtyard") (47 "F.CrtYd" user "F.Courtyard") (48 "B.Fab" user "B.Fabrication") (49 "F.Fab" user "F.Fabrication") ) ;; ------------------------------------------------------------------------- ;; Setup: stackup + DRC rules ;; ------------------------------------------------------------------------- (setup (pad_to_mask_clearance 0.05) (solder_mask_min_width 0) (allow_soldermask_bridges_in_footprints no) ;; 4-layer Megtron 6 stackup (2.0 mm total) ;; Optimised for PCIe Gen 6 (64 GT/s): Dk=3.65, Df=0.004 @ 16 GHz (stackup (layer "F.SilkS" (type "Top Silk Screen")) (layer "F.Paste" (type "Top Solder Paste")) (layer "F.Mask" (type "Top Solder Mask") (thickness 0.01)) (layer "F.Cu" (type "copper") (thickness 0.035)) (layer "dielectric 1" (type "prepreg") (thickness 0.1) (material "Megtron6") (epsilon_r 3.65) (loss_tangent 0.004)) (layer "In1.Cu" (type "copper") (thickness 0.0175)) (layer "dielectric 2" (type "core") (thickness 1.625) (material "Megtron6") (epsilon_r 3.65) (loss_tangent 0.004)) (layer "In2.Cu" (type "copper") (thickness 0.0175)) (layer "dielectric 3" (type "prepreg") (thickness 0.1) (material "Megtron6") (epsilon_r 3.65) (loss_tangent 0.004)) (layer "B.Cu" (type "copper") (thickness 0.035)) (layer "B.Mask" (type "Bottom Solder Mask") (thickness 0.01)) (layer "B.Paste" (type "Bottom Solder Paste")) (layer "B.SilkS" (type "Bottom Silk Screen")) (copper_finish "ENIG") (dielectric_constraints no) (edge_connector "beveled") (castellated_pads no) (edge_plating yes) ) (pcbplotparams (outputdirectory "gerbers/") (layerselection 0x00010fc_ffffffff) (disableapertmacros no) (usegerberextensions no) (usegerberattributes yes) (usegerberadvancedattributes yes) (creategerberjobfile yes) (excludeedgelayer yes) (plotframeref no) (viasonmask no) (mode 1) (useauxorigin no) (hpglpennumber 1) (hpglpenspeed 20) (hpglpendiameter 15.0) (psnegative no) (plotreference yes) (plotvalue yes) (plotinvisibletext no) (sketchpadsonfab no) (subtractmaskfromsilk yes) (outputformat 1) (mirror no) (drillshape 1) (scaleselection 1) ) ) ;; ------------------------------------------------------------------------- ;; Net declarations ;; ------------------------------------------------------------------------- (net 0 "") (net 1 "GND") (net 2 "+12V") (net 3 "+3V3") (net 4 "+1V8") (net 5 "+0V9") (net 6 "PCIE_TX0_P") (net 7 "PCIE_TX0_N") (net 8 "PCIE_RX0_P") (net 9 "PCIE_RX0_N") (net 10 "PCIE_TX1_P") (net 11 "PCIE_TX1_N") (net 12 "PCIE_RX1_P") (net 13 "PCIE_RX1_N") (net 14 "REFCLK_P") (net 15 "REFCLK_N") (net 16 "OPT_A_TX_P") (net 17 "OPT_A_TX_N") (net 18 "OPT_A_RX_P") (net 19 "OPT_A_RX_N") (net 20 "OPT_B_TX_P") (net 21 "OPT_B_TX_N") (net 22 "OPT_B_RX_P") (net 23 "OPT_B_RX_N") (net 24 "OPT_C_TX_P") (net 25 "OPT_C_TX_N") (net 26 "OPT_C_RX_P") (net 27 "OPT_C_RX_N") (net 28 "OPT_D_TX_P") (net 29 "OPT_D_TX_N") (net 30 "OPT_D_RX_P") (net 31 "OPT_D_RX_N") ;; ------------------------------------------------------------------------- ;; Board outline (Edge.Cuts) ;; FHHL PCIe card: 167.65 mm (L) x 111.15 mm (H) ;; Origin (0,0) = top-left corner ;; ------------------------------------------------------------------------- (gr_rect (start 0 0) (end 167.65 111.15) (stroke (width 0.05) (type solid)) (layer "Edge.Cuts") ) ;; ------------------------------------------------------------------------- ;; Silkscreen annotations ;; ------------------------------------------------------------------------- (gr_text "LightRail AI Gen3 -- LR-P8A" (at 83.825 4 0) (layer "F.SilkS") (effects (font (size 3 3) (thickness 0.5)) (justify center)) ) (gr_text "Rev A01" (at 155 4 0) (layer "F.SilkS") (effects (font (size 2 2) (thickness 0.3)) (justify center)) ) (gr_text "PCIe Gen 6 x16" (at 55.15 108 0) (layer "F.SilkS") (effects (font (size 1.5 1.5) (thickness 0.25)) (justify center)) ) ;; Fab layer: component area labels (gr_text "DIE 1" (at 60 55 0) (layer "F.Fab") (effects (font (size 3 3) (thickness 0.5)) (justify center)) ) (gr_text "DIE 2" (at 110 55 0) (layer "F.Fab") (effects (font (size 3 3) (thickness 0.5)) (justify center)) ) (gr_text "OPT" (at 11 55 0) (layer "F.Fab") (effects (font (size 2 2) (thickness 0.3)) (justify center)) ) (gr_text "VRM" (at 148 30 0) (layer "F.Fab") (effects (font (size 2 2) (thickness 0.3)) (justify center)) ) ;; ------------------------------------------------------------------------- ;; Component footprints (all placeholders) ;; ------------------------------------------------------------------------- ;; J1: PCIe x16 Gen 6 edge connector ;; Position: x=55.15 (center of x16 span), y=108 (near bottom edge) ;; TODO: replace with vendor footprint per PCIe CEM spec (footprint "LR_P8A:PCIE_X16_EDGE_PH" (layer "F.Cu") (at 55.15 108.0) (descr "PCIe x16 Gen 6 edge connector placeholder -- REPLACE WITH VENDOR FOOTPRINT") (fp_text reference "J1" (at 0 -7) (layer "F.SilkS") (effects (font (size 1.5 1.5) (thickness 0.2)))) (fp_text value "PCIe_x16_Gen6" (at 0 -5) (layer "F.Fab") (effects (font (size 1.2 1.2) (thickness 0.18)))) (fp_text user "REPLACE WITH VENDOR FOOTPRINT" (at 0 0) (layer "F.Fab") (effects (font (size 1.2 1.2) (thickness 0.18)) (justify center))) (fp_rect (start -43 -4) (end 43 4) (layer "F.CrtYd") (stroke (width 0.05) (type solid))) (fp_rect (start -43 -4) (end 43 4) (layer "F.Fab") (stroke (width 0.1) (type solid))) (fp_line (start -43 -4) (end -43 -8) (layer "F.SilkS") (stroke (width 0.15) (type solid))) (fp_line (start 43 -4) (end 43 -8) (layer "F.SilkS") (stroke (width 0.15) (type solid))) ) ;; U1: Photonic ASIC Die 1 (40 x 40 mm placeholder) ;; Position: center at (60, 55) ;; TODO: replace with actual photonic ASIC footprint from die spec (footprint "LR_P8A:ASIC_DIE_PH_40x40" (layer "F.Cu") (at 60 55) (descr "Photonic ASIC Die 1 placeholder -- 40x40 mm -- REPLACE WITH VENDOR FOOTPRINT") (fp_text reference "U1" (at 0 -23) (layer "F.SilkS") (effects (font (size 1.5 1.5) (thickness 0.2)))) (fp_text value "LR-P8A-DIE1" (at 0 -21) (layer "F.Fab") (effects (font (size 1.2 1.2) (thickness 0.18)))) (fp_text user "PHOTONIC DIE 1\n40x40 mm placeholder\nREPLACE WITH VENDOR FOOTPRINT" (at 0 0) (layer "F.Fab") (effects (font (size 2 2) (thickness 0.3)) (justify center))) (fp_rect (start -20 -20) (end 20 20) (layer "F.CrtYd") (stroke (width 0.05) (type solid))) (fp_rect (start -20 -20) (end 20 20) (layer "F.Fab") (stroke (width 0.15) (type solid))) (fp_rect (start -20 -20) (end 20 20) (layer "F.SilkS") (stroke (width 0.15) (type solid))) ) ;; U2: Photonic ASIC Die 2 (40 x 40 mm placeholder) ;; Position: center at (110, 55) (footprint "LR_P8A:ASIC_DIE_PH_40x40" (layer "F.Cu") (at 110 55) (descr "Photonic ASIC Die 2 placeholder -- 40x40 mm -- REPLACE WITH VENDOR FOOTPRINT") (fp_text reference "U2" (at 0 -23) (layer "F.SilkS") (effects (font (size 1.5 1.5) (thickness 0.2)))) (fp_text value "LR-P8A-DIE2" (at 0 -21) (layer "F.Fab") (effects (font (size 1.2 1.2) (thickness 0.18)))) (fp_text user "PHOTONIC DIE 2\n40x40 mm placeholder\nREPLACE WITH VENDOR FOOTPRINT" (at 0 0) (layer "F.Fab") (effects (font (size 2 2) (thickness 0.3)) (justify center))) (fp_rect (start -20 -20) (end 20 20) (layer "F.CrtYd") (stroke (width 0.05) (type solid))) (fp_rect (start -20 -20) (end 20 20) (layer "F.Fab") (stroke (width 0.15) (type solid))) (fp_rect (start -20 -20) (end 20 20) (layer "F.SilkS") (stroke (width 0.15) (type solid))) ) ;; CAGE1: QSFP-DD optical channel A (left edge, top) ;; TODO: replace with OSFP or QSFP-DD cage vendor footprint (footprint "LR_P8A:QSFP_DD_CAGE_PH" (layer "F.Cu") (at 11 18) (descr "QSFP-DD cage CH-A placeholder -- REPLACE WITH VENDOR FOOTPRINT") (fp_text reference "CAGE1" (at 0 -13) (layer "F.SilkS") (effects (font (size 1.2 1.2) (thickness 0.18)))) (fp_text value "QSFP-DD_CH-A" (at 0 -11) (layer "F.Fab") (effects (font (size 1.2 1.2) (thickness 0.18)))) (fp_text user "CH-A" (at 0 0) (layer "F.Fab") (effects (font (size 2 2) (thickness 0.3)) (justify center))) (fp_rect (start -10 -10) (end 10 10) (layer "F.CrtYd") (stroke (width 0.05) (type solid))) (fp_rect (start -10 -10) (end 10 10) (layer "F.Fab") (stroke (width 0.1) (type solid))) (fp_rect (start -10 -10) (end 10 10) (layer "F.SilkS") (stroke (width 0.15) (type solid))) ) ;; CAGE2: QSFP-DD optical channel B (footprint "LR_P8A:QSFP_DD_CAGE_PH" (layer "F.Cu") (at 11 42) (descr "QSFP-DD cage CH-B placeholder -- REPLACE WITH VENDOR FOOTPRINT") (fp_text reference "CAGE2" (at 0 -13) (layer "F.SilkS") (effects (font (size 1.2 1.2) (thickness 0.18)))) (fp_text value "QSFP-DD_CH-B" (at 0 -11) (layer "F.Fab") (effects (font (size 1.2 1.2) (thickness 0.18)))) (fp_text user "CH-B" (at 0 0) (layer "F.Fab") (effects (font (size 2 2) (thickness 0.3)) (justify center))) (fp_rect (start -10 -10) (end 10 10) (layer "F.CrtYd") (stroke (width 0.05) (type solid))) (fp_rect (start -10 -10) (end 10 10) (layer "F.Fab") (stroke (width 0.1) (type solid))) (fp_rect (start -10 -10) (end 10 10) (layer "F.SilkS") (stroke (width 0.15) (type solid))) ) ;; CAGE3: QSFP-DD optical channel C (footprint "LR_P8A:QSFP_DD_CAGE_PH" (layer "F.Cu") (at 11 66) (descr "QSFP-DD cage CH-C placeholder -- REPLACE WITH VENDOR FOOTPRINT") (fp_text reference "CAGE3" (at 0 -13) (layer "F.SilkS") (effects (font (size 1.2 1.2) (thickness 0.18)))) (fp_text value "QSFP-DD_CH-C" (at 0 -11) (layer "F.Fab") (effects (font (size 1.2 1.2) (thickness 0.18)))) (fp_text user "CH-C" (at 0 0) (layer "F.Fab") (effects (font (size 2 2) (thickness 0.3)) (justify center))) (fp_rect (start -10 -10) (end 10 10) (layer "F.CrtYd") (stroke (width 0.05) (type solid))) (fp_rect (start -10 -10) (end 10 10) (layer "F.Fab") (stroke (width 0.1) (type solid))) (fp_rect (start -10 -10) (end 10 10) (layer "F.SilkS") (stroke (width 0.15) (type solid))) ) ;; CAGE4: QSFP-DD optical channel D (footprint "LR_P8A:QSFP_DD_CAGE_PH" (layer "F.Cu") (at 11 90) (descr "QSFP-DD cage CH-D placeholder -- REPLACE WITH VENDOR FOOTPRINT") (fp_text reference "CAGE4" (at 0 -13) (layer "F.SilkS") (effects (font (size 1.2 1.2) (thickness 0.18)))) (fp_text value "QSFP-DD_CH-D" (at 0 -11) (layer "F.Fab") (effects (font (size 1.2 1.2) (thickness 0.18)))) (fp_text user "CH-D" (at 0 0) (layer "F.Fab") (effects (font (size 2 2) (thickness 0.3)) (justify center))) (fp_rect (start -10 -10) (end 10 10) (layer "F.CrtYd") (stroke (width 0.05) (type solid))) (fp_rect (start -10 -10) (end 10 10) (layer "F.Fab") (stroke (width 0.1) (type solid))) (fp_rect (start -10 -10) (end 10 10) (layer "F.SilkS") (stroke (width 0.15) (type solid))) ) ;; VR1: VRM 12V -> 1.8V / 0.9V / 3.3V ;; Position: top-right area (148, 30) (footprint "LR_P8A:VRM_PH" (layer "F.Cu") (at 148 30) (descr "VRM placeholder -- REPLACE WITH VENDOR MODULE") (fp_text reference "VR1" (at 0 -19) (layer "F.SilkS") (effects (font (size 1.5 1.5) (thickness 0.2)))) (fp_text value "VRM_12V_TO_MULTI" (at 0 -17) (layer "F.Fab") (effects (font (size 1.2 1.2) (thickness 0.18)))) (fp_text user "VRM\n12V -> 1.8V / 0.9V / 3.3V\nREPLACE WITH VENDOR MODULE" (at 0 0) (layer "F.Fab") (effects (font (size 1.5 1.5) (thickness 0.2)) (justify center))) (fp_rect (start -14 -16) (end 14 16) (layer "F.CrtYd") (stroke (width 0.05) (type solid))) (fp_rect (start -14 -16) (end 14 16) (layer "F.Fab") (stroke (width 0.1) (type solid))) (fp_rect (start -14 -16) (end 14 16) (layer "F.SilkS") (stroke (width 0.15) (type solid))) ) ;; U3: PCIe Gen 6 Retimer ;; Position: between edge connector and dies (83.825, 93) (footprint "LR_P8A:RETIMER_PH" (layer "F.Cu") (at 83.825 93) (descr "PCIe Gen 6 retimer placeholder -- e.g. Astera Labs PT5125, Parade PS8471") (fp_text reference "U3" (at 0 -11) (layer "F.SilkS") (effects (font (size 1.5 1.5) (thickness 0.2)))) (fp_text value "PCIe_Retimer_Gen6" (at 0 -9) (layer "F.Fab") (effects (font (size 1.2 1.2) (thickness 0.18)))) (fp_text user "PCIe Retimer\n(e.g. Astera Labs PT5125)\nREPLACE WITH VENDOR PART" (at 0 0) (layer "F.Fab") (effects (font (size 1.2 1.2) (thickness 0.18)) (justify center))) (fp_rect (start -12 -8) (end 12 8) (layer "F.CrtYd") (stroke (width 0.05) (type solid))) (fp_rect (start -12 -8) (end 12 8) (layer "F.Fab") (stroke (width 0.1) (type solid))) (fp_rect (start -12 -8) (end 12 8) (layer "F.SilkS") (stroke (width 0.15) (type solid))) ) ;; ------------------------------------------------------------------------- ;; Mounting holes (per PCIe CEM spec) ;; H1: rear bracket, upper hole ;; H2: rear bracket, lower hole ;; ------------------------------------------------------------------------- (footprint "MountingHole:MountingHole_3.2mm_M3" (layer "F.Cu") (at 3.2 6.35) (fp_text reference "H1" (at 0 -5) (layer "F.Fab") (effects (font (size 1.0 1.0) (thickness 0.15)))) (fp_text value "M3" (at 0 5) (layer "F.Fab") (effects (font (size 1.0 1.0) (thickness 0.15)))) (pad "" thru_hole circle (at 0 0) (size 6.4 6.4) (drill 3.2) (layers "*.Cu" "*.Mask") (net 1 "GND")) ) (footprint "MountingHole:MountingHole_3.2mm_M3" (layer "F.Cu") (at 3.2 104.8) (fp_text reference "H2" (at 0 -5) (layer "F.Fab") (effects (font (size 1.0 1.0) (thickness 0.15)))) (fp_text value "M3" (at 0 5) (layer "F.Fab") (effects (font (size 1.0 1.0) (thickness 0.15)))) (pad "" thru_hole circle (at 0 0) (size 6.4 6.4) (drill 3.2) (layers "*.Cu" "*.Mask") (net 1 "GND")) ) )