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	(generator "pcbnew")
	(generator_version "9.0")
	(general
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		(legacy_teardrops no)
	)
	(paper "A4")
	(layers
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		(4 "In1.Cu" power "GNDU.Cu")
		(6 "In2.Cu" signal "SIGL.Cu")
		(2 "B.Cu" power "GNDL.Cu")
		(13 "F.Paste" user)
		(15 "B.Paste" user)
		(5 "F.SilkS" user "F.Silkscreen")
		(7 "B.SilkS" user "B.Silkscreen")
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		(17 "Dwgs.User" user "User.Drawings")
		(25 "Edge.Cuts" user)
		(27 "Margin" user)
		(31 "F.CrtYd" user "F.Courtyard")
		(29 "B.CrtYd" user "B.Courtyard")
	)
	(setup
		(stackup
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				(type "Top Silk Screen")
				(color "White")
			)
			(layer "F.Paste"
				(type "Top Solder Paste")
			)
			(layer "F.Mask"
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				(thickness 0.01)
			)
			(layer "F.Cu"
				(type "copper")
				(thickness 0.035)
			)
			(layer "dielectric 1"
				(type "prepreg")
				(thickness 0.2104)
				(material "FR4")
				(epsilon_r 4.4)
				(loss_tangent 0.02)
			)
			(layer "In1.Cu"
				(type "copper")
				(thickness 0.0152)
			)
			(layer "dielectric 2"
				(type "core")
				(thickness 1.065)
				(material "FR4")
				(epsilon_r 4.6)
				(loss_tangent 0.02)
			)
			(layer "In2.Cu"
				(type "copper")
				(thickness 0.0152)
			)
			(layer "dielectric 3"
				(type "prepreg")
				(thickness 0.2104)
				(material "FR4")
				(epsilon_r 4.4)
				(loss_tangent 0.02)
			)
			(layer "B.Cu"
				(type "copper")
				(thickness 0.035)
			)
			(layer "B.Mask"
				(type "Bottom Solder Mask")
				(color "Green")
				(thickness 0.01)
			)
			(layer "B.Paste"
				(type "Bottom Solder Paste")
			)
			(layer "B.SilkS"
				(type "Bottom Silk Screen")
				(color "White")
			)
			(copper_finish "ENIG")
			(dielectric_constraints yes)
		)
		(pad_to_mask_clearance 0)
		(allow_soldermask_bridges_in_footprints no)
		(tenting front back)
		(pcbplotparams
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			(pdf_front_fp_property_popups yes)
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			(dxfpolygonmode yes)
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			(plot_black_and_white yes)
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			(plotpadnumbers no)
			(hidednponfab no)
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			(subtractmaskfromsilk no)
			(outputformat 1)
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			(drillshape 1)
			(scaleselection 1)
			(outputdirectory "")
		)
	)
	(net 0 "")
	(net 1 "+5VA")
	(net 2 "GND")
	(net 3 "VDD")
	(net 4 "Net-(U3B--)")
	(net 5 "/BASE")
	(net 6 "/SETPOINT")
	(net 7 "/FB_BUF")
	(net 8 "/FB")
	(net 9 "/DIN")
	(net 10 "/CS#")
	(net 11 "/SCLK")
	(net 12 "/VOUT")
	(net 13 "Net-(U1-B)")
	(net 14 "Net-(U1-E)")
	(net 15 "Net-(U2-B)")
	(net 16 "Net-(U2-E)")
	(net 17 "Net-(U4-VOUT)")
	(footprint "PCM_JLCPCB:R_0603"
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		(at 135.2 84 -90)
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