![\"Open](\"https://colab.research.google.com/assets/colab-badge.svg\"){kind=icon}
"
]
},
{
"cell_type": "markdown",
"source": [
"Monte Carlo simulation of a trend towards achieving terabyte (TB) level L1 cache memory. See below for gigabyte level L1 cache memory."
],
"metadata": {
"id": "BCstvk1WraL8"
}
},
{
"cell_type": "code",
"execution_count": 2,
"metadata": {
"colab": {
"base_uri": "https://localhost:8080/",
"height": 1000
},
"id": "Ry6i0ZQ1rY8m",
"outputId": "fd8f0608-0537-4c72-82cb-f4a6e1e954f9"
},
"outputs": [
{
"output_type": "stream",
"name": "stdout",
"text": [
"Simulation runs: 10000\n",
"Required Doublings to 1TB from 64KB: 24\n",
"Mean Years to Achieve: 60.2\n",
"Median Years to Achieve: 60.2\n",
"Min/Max Years to Achieve: 43.1/74.5\n",
"Mean Finish Year (starting 2025): ~2085\n",
"Median Finish Year (starting 2025): ~2085\n"
]
},
{
"output_type": "display_data",
"data": {
"text/plain": [
"| \n", " | Reference | \n", "Year | \n", "Note | \n", "
|---|---|---|---|
| 0 | \n", "Hennessy & Patterson, Computer Architecture: A... | \n", "2017 | \n", "Discussion on exponential trends in cache and ... | \n", "
| 1 | \n", "International Technology Roadmap for Semicondu... | \n", "2015 | \n", "Predictions of semiconductor technology scalin... | \n", "
| 2 | \n", "Samuel K. Moore, IEEE Spectrum: 'Chipmakers Pu... | \n", "2022 | \n", "Recent advancements and breakthroughs in SRAM ... | \n", "
| 3 | \n", "T. Naffziger, IEEE ISSCC Keynote: 'Future of P... | \n", "2023 | \n", "Insights into future scaling of processor cach... | \n", "
| 4 | \n", "AMD Technical Roadmap Presentation | \n", "2024 | \n", "Projected exponential growth in processor cach... | \n", "