Keil STM32G4xx_DFP STMicroelectronics STM32G4 Series Device Support https://www.keil.com/pack/ https://github.com/Open-CMSIS-Pack/STM32G4xx_DFP.git LICENSES Active development ... Updated STM32Cube FW to STM32Cube_FW_G4_V1.5.2 (HAL V1.2.3). Device Support: - Flash Option Bytes template files can be added to the project as a user template. - Updated SVD files. Board Examples: - Updated STM32G474E-EVAL CMSIS-RTOS2 Blinky example to CMSIS_6. CMSIS-Driver: - USART: -- Corrected Flow Control capabilities -- Removed Rx Timeout capability and event signalization - Improved documentation CMSIS-Driver: - USART: Added CMSIS Driver - SPI: Added CMSIS Driver -- Corrected Control function to support more than 16 data bits in DMA mode CMSIS Flash: - rebuild current algorithms. Board Examples: - Overwritten default HAL_InitTick function. Package Description (pdsc): - Added RAMstart and RAMsize attributes to Flash Algorithm elements. CMSIS Flash: - Added external Flash Algorithm for STM32G474E-EVAL. - Added Option Byte Flash Algorithm example. Board Examples: - STM32G474E-EVAL: -- Migrated example to STM32CubeG4 Firmware Package version V1.4.0. -- Changed default compiler to Arm Compiler 6. -- Changed Assembler option to armclang (Auto Select). -- Updated RTX config files to CMSIS 5.8.0. CMSIS Device Support: - Updated STM32Cube Firmware G4 library to version V1.4.0. - Updated SVD files. - Updated documentation. CMSIS Flash Algorithm: - Adding support to the QSPI external Loader for the STM32G474E-EVAL. - Adding internal flash algorithm support for 128k dual bank devices. - Fixing internal flash last word programming. - Fixing internal flash extra sector erasing on dual bank mode for dual bank config devices. Added global define USE_HAL_DRIVER and USE_FULL_LL_DRIVER to the component ::Device:STM32Cube Framework:STM32CubeMX. Added debugProbe to board description. Added devices: - STM32G491xxxx, STM32G4A1xxxx and STM32G483xx series. - STM32G474Px/STM32G484Px/STM32G473Px/STM32G483Px BGA121 variants. - STM32G431MBTx, STM32G441MBTx variants. Updated STM32CubeG4 Firmware Package to V1.3.0. - Updated svd files - Fixed flash programming algorithm issue for the STM32G4xxxC devices to support both Dual/Single Bank configuration in STM32G4xx_256.FLM. - Updated the Flash category 3 (512kB) with one FLM that supports the D/S Bank config. FrameworkCubeMX_gpdsc.ftl: - Added support for Timebase Source TIMx Updated example: - Terminating app_main thread with osThreadExit() to avoid endless loop Initial public release of STM32G4 Series Device Support: - Requires STM32CubeMX Version 5.2 or higher and STM32CubeG4 Firmware Package V1.0.0 Added debug sequences: - configure ETM Trace. Added board support for STM32G474E-EVAL: - Added Blinky example. ST Device Support Device Family Package STMicroelectronics STM32G4 STM32G4xx High-performance STM32G4 MCUs with Arm Cortex-M4 core, MPU, DSP, FPU, 213 DMIPS at 170MHz. Sequence("CheckID"); // Replication of Standard Functionality Write32(0xE000EDF0, 0xA05F0001); // Enable Core Debug via DHCSR Write32(0xE0042004, DbgMCU_CR); // DBGMCU_CR: Configure MCU Debug Write32(0xE0042008, DbgMCU_APB1_Fz1); // DBGMCU_APB1_FZ1: Configure APB1 Peripheral Freeze Behavior Write32(0xE004200C, DbgMCU_APB1_Fz2); // DBGMCU_APB1_FZ2: Configure APB1 Peripheral Freeze Behavior Write32(0xE0042010, DbgMCU_APB2_Fz); // DBGMCU_APB2_FZ: Configure APB2 Peripheral Freeze Behavior __var traceSWO = (__traceout & 0x1) != 0; // SWO (asynchronous) Trace Selected? __var traceTPIU = (__traceout & 0x2) != 0; // TPIU (synchronous) Trace Selected? Sequence("EnableTraceSWO"); // Call SWO Trace Setup Sequence("EnableTraceTPIU"); // Call TPIU Trace Setup // Nothing required for SWO Trace __var traceSWO = (__traceout & 0x1) != 0; // SWO enabled? __var traceTPIU = (__traceout & 0x2) != 0; // Synchronous trace port enabled? Sequence("DisableTraceSWO"); Sequence("DisableTraceTPIU"); __var pidr1 = 0; __var pidr2 = 0; __var jep106id = 0; __var ROMTableBase = 0; __ap = 0; // AHB-AP ROMTableBase = ReadAP(0xF8) & ~0x3; pidr1 = Read32(ROMTableBase + 0x0FE4); pidr2 = Read32(ROMTableBase + 0x0FE8); jep106id = ((pidr2 & 0x7) << 4 ) | ((pidr1 >> 4) & 0xF); Query(0, "Not a genuine ST Device! Abort connection", 1); Message(2, "Not a genuine ST Device! Abort connection."); __var dbgmcu_val = 0; // DBGMCU_CR Value __var dbgmcu_trace_val = 0; // DBGMCU_CR Value dbgmcu_val = Read32(0xE0042004) & (~0xE0); // Read DBGMCU_CR and clear trace setup dbgmcu_trace_val = (1 << 5); // Trace I/O Enable + Trace Mode Asynchronous Sequence("ConfigureTraceSWOPin"); Write32(0xE0042004, dbgmcu_val | dbgmcu_trace_val); // Write DBGMCU_CR: Trace Settings __var dbgmcu_val = 0; // DBGMCU_CR Value dbgmcu_val = Read32(0xE0042004) & (~0xE0); // Read DBGMCU_CR and clear trace setup Write32(0xE0042004, dbgmcu_val); // Write DBGMCU_CR: Trace Settings __var width = (__traceout & 0x003F0000) >> 16; __var dbgmcu_val = 0; // DBGMCU_CR Value __var dbgmcu_trace_val = 0; // DBGMCU_CR Value dbgmcu_val = Read32(0xE0042004) & (~0xE0); // Read DBGMCU_CR and clear trace setup Sequence("ConfigureTraceTPIUPins"); dbgmcu_trace_val = (3 << 5); dbgmcu_trace_val = (5 << 5); dbgmcu_trace_val = (7 << 5); Write32(0xE0042004, dbgmcu_val | dbgmcu_trace_val); // Write DBGMCU_CR: Trace Settings __var dbgmcu_val = 0; // DBGMCU_CR Value dbgmcu_val = Read32(0xE0042004) & (~0xE0); // Read DBGMCU_CR and clear trace setup Write32(0xE0042004, dbgmcu_val); // Write DBGMCU_CR: Trace Settings __var pin = 0; __var port = 0; __var portAdr = 0; __var pos = 0; __var SWO_Pin = 0x00010003; // PB3 pin = ((SWO_Pin ) & 0x0000FFFF); port = ((SWO_Pin >> 16) & 0x0000FFFF); portAdr = 0x48000000 + (((SWO_Pin >> 16) & 0x0000FFFF) * 0x400); pos = pin * 2; Write32(0x4002104C, ((Read32(0x4002104C ) ) | (1 << port)) ); // RCC_AHB2ENR: IO port clock enable Write32(portAdr + 0x00, ((Read32(portAdr + 0x00) & ~( 3 << pos)) | (2 << pos )) ); // GPIOx_MODER: Set Mode (Alternate Function) Write32(portAdr + 0x08, ((Read32(portAdr + 0x08) ) | (3 << pos )) ); // GPIOx_OSPEEDR: Set Speed (Very High Speed) Write32(portAdr + 0x0C, ((Read32(portAdr + 0x0C) & ~( 3 << pos)) ) ); // GPIOx_PUPDR: Set I/O to no pull-up/pull-down pos = ((pin ) & 7) * 4; Write32(portAdr + 0x20, ((Read32(portAdr + 0x20) & ~(15 << pos)) ) ); // GPIOx_AFRL: Alternate Function to AF0 pos = ((pin - 8) & 7) * 4; Write32(portAdr + 0x24, ((Read32(portAdr + 0x24) & ~(15 << pos)) ) ); // GPIOx_AFRH: Alternate Function to AF0 __var pin = 8; __var port = 0; __var portAdr = 0; __var pos = 0; __var width = (__traceout & 0x003F0000) >> 16; pin = (TraceClk_Pin ) & 0x0000FFFF; port = (TraceClk_Pin >> 16) & 0x0000FFFF; portAdr = 0x48000000 + (((TraceClk_Pin >> 16) & 0x0000FFFF) * 0x400); pos = pin * 2; Write32(0x4002104C, ((Read32(0x4002104C ) ) | (1 << port)) ); // RCC_AHB2ENR: IO port clock enable Write32(portAdr + 0x00, ((Read32(portAdr + 0x00) & ~( 3 << pos)) | (2 << pos )) ); // GPIOx_MODER: Set Mode (Alternate Function) Write32(portAdr + 0x08, ((Read32(portAdr + 0x08) ) | (3 << pos )) ); // GPIOx_OSPEEDR: Set Speed (Very High Speed) Write32(portAdr + 0x0C, ((Read32(portAdr + 0x0C) & ~( 3 << pos)) ) ); // GPIOx_PUPDR: Set I/O to no pull-up/pull-down pos = ((pin ) & 7) * 4; Write32(portAdr + 0x20, ((Read32(portAdr + 0x20) & ~(15 << pos)) ) ); // GPIOx_AFRL: Alternate Function to AF0 pos = ((pin - 8) & 7) * 4; Write32(portAdr + 0x24, ((Read32(portAdr + 0x24) & ~(15 << pos)) ) ); // GPIOx_AFRH: Alternate Function to AF0 pin = (TraceD0_Pin ) & 0x0000FFFF; port = (TraceD0_Pin >> 16) & 0x0000FFFF; portAdr = 0x48000000 + (((TraceD0_Pin >> 16) & 0x0000FFFF) * 0x400); pos = pin * 2; Write32(0x4002104C, ((Read32(0x4002104C ) ) | (1 << port)) ); // RCC_AHB2ENR: IO port clock enable Write32(portAdr + 0x00, ((Read32(portAdr + 0x00) & ~( 3 << pos)) | (2 << pos )) ); // GPIOx_MODER: Set Mode (Alternate Function) Write32(portAdr + 0x08, ((Read32(portAdr + 0x08) ) | (3 << pos )) ); // GPIOx_OSPEEDR: Set Speed (Very High Speed) Write32(portAdr + 0x0C, ((Read32(portAdr + 0x0C) & ~( 3 << pos)) ) ); // GPIOx_PUPDR: Set I/O to no pull-up/pull-down pos = ((pin ) & 7) * 4; Write32(portAdr + 0x20, ((Read32(portAdr + 0x20) & ~(15 << pos)) ) ); // GPIOx_AFRL: Alternate Function to AF0 pos = ((pin - 8) & 7) * 4; Write32(portAdr + 0x24, ((Read32(portAdr + 0x24) & ~(15 << pos)) ) ); // GPIOx_AFRH: Alternate Function to AF0 pin = (TraceD1_Pin ) & 0x0000FFFF; port = (TraceD1_Pin >> 16) & 0x0000FFFF; portAdr = 0x48000000 + (((TraceD1_Pin >> 16) & 0x0000FFFF) * 0x400); pos = pin * 2; Write32(0x4002104C, ((Read32(0x4002104C ) ) | (1 << port)) ); // RCC_AHB2ENR: IO port clock enable Write32(portAdr + 0x00, ((Read32(portAdr + 0x00) & ~( 3 << pos)) | (2 << pos )) ); // GPIOx_MODER: Set Mode (Alternate Function) Write32(portAdr + 0x08, ((Read32(portAdr + 0x08) ) | (3 << pos )) ); // GPIOx_OSPEEDR: Set Speed (Very High Speed) Write32(portAdr + 0x0C, ((Read32(portAdr + 0x0C) & ~( 3 << pos)) ) ); // GPIOx_PUPDR: Set I/O to no pull-up/pull-down pos = ((pin ) & 7) * 4; Write32(portAdr + 0x20, ((Read32(portAdr + 0x20) & ~(15 << pos)) ) ); // GPIOx_AFRL: Alternate Function to AF0 pos = ((pin - 8) & 7) * 4; Write32(portAdr + 0x24, ((Read32(portAdr + 0x24) & ~(15 << pos)) ) ); // GPIOx_AFRH: Alternate Function to AF0 pin = (TraceD2_Pin ) & 0x0000FFFF; port = (TraceD2_Pin >> 16) & 0x0000FFFF; portAdr = 0x48000000 + (((TraceD2_Pin >> 16) & 0x0000FFFF) * 0x400); pos = pin * 2; Write32(0x4002104C, ((Read32(0x4002104C ) ) | (1 << port)) ); // RCC_AHB2ENR: IO port clock enable Write32(portAdr + 0x00, ((Read32(portAdr + 0x00) & ~( 3 << pos)) | (2 << pos )) ); // GPIOx_MODER: Set Mode (Alternate Function) Write32(portAdr + 0x08, ((Read32(portAdr + 0x08) ) | (3 << pos )) ); // GPIOx_OSPEEDR: Set Speed (Very High Speed) Write32(portAdr + 0x0C, ((Read32(portAdr + 0x0C) & ~( 3 << pos)) ) ); // GPIOx_PUPDR: Set I/O to no pull-up/pull-down pos = ((pin ) & 7) * 4; Write32(portAdr + 0x20, ((Read32(portAdr + 0x20) & ~(15 << pos)) ) ); // GPIOx_AFRL: Alternate Function to AF0 pos = ((pin - 8) & 7) * 4; Write32(portAdr + 0x24, ((Read32(portAdr + 0x24) & ~(15 << pos)) ) ); // GPIOx_AFRH: Alternate Function to AF0 pin = (TraceD3_Pin ) & 0x0000FFFF; port = (TraceD3_Pin >> 16) & 0x0000FFFF; portAdr = 0x48000000 + (((TraceD3_Pin >> 16) & 0x0000FFFF) * 0x400); pos = pin * 2; Write32(0x4002104C, ((Read32(0x4002104C ) ) | (1 << port)) ); // RCC_AHB2ENR: IO port clock enable Write32(portAdr + 0x00, ((Read32(portAdr + 0x00) & ~( 3 << pos)) | (2 << pos )) ); // GPIOx_MODER: Set Mode (Alternate Function) Write32(portAdr + 0x08, ((Read32(portAdr + 0x08) ) | (3 << pos )) ); // GPIOx_OSPEEDR: Set Speed (Very High Speed) Write32(portAdr + 0x0C, ((Read32(portAdr + 0x0C) & ~( 3 << pos)) ) ); // GPIOx_PUPDR: Set I/O to no pull-up/pull-down pos = ((pin ) & 7) * 4; Write32(portAdr + 0x20, ((Read32(portAdr + 0x20) & ~(15 << pos)) ) ); // GPIOx_AFRL: Alternate Function to AF0 pos = ((pin - 8) & 7) * 4; Write32(portAdr + 0x24, ((Read32(portAdr + 0x24) & ~(15 << pos)) ) ); // GPIOx_AFRH: Alternate Function to AF0 __var connectionFlash = ( __connection & 0xF ) == 2 ; __var FLASH_BASE = 0x40022000 ; __var FLASH_CR = FLASH_BASE + 0x14 ; __var OBL_LAUNCH_BIT = ( 1 << 27 ) ; __var LOCK_BIT = ( 1 << 31 ) ; __var OPTLOCK_BIT = ( 1 << 30 ) ; __var FLASH_KEYR = FLASH_BASE + 0x08 ; __var FLASH_KEY1 = 0x45670123 ; __var FLASH_KEY2 = 0xCDEF89AB ; __var FLASH_OPTKEYR = FLASH_BASE + 0x0C ; __var FLASH_OPTKEY1 = 0x08192A3B ; __var FLASH_OPTKEY2 = 0x4C5D6E7F ; __var FLASH_CR_Value = 0 ; __var DoDebugPortStop = 1 ; __var DP_CTRL_STAT = 0x4 ; __var DP_SELECT = 0x8 ; // unlock the FLASH_CR Write32( FLASH_KEYR, FLASH_KEY1 ) ; Write32( FLASH_KEYR, FLASH_KEY2 ) ; // unlock the option byte block Write32( FLASH_OPTKEYR, FLASH_OPTKEY1 ) ; Write32( FLASH_OPTKEYR, FLASH_OPTKEY2 ) ; FLASH_CR_Value = Read32( FLASH_CR ) ; DoDebugPortStop = 0 ; __errorcontrol = 1 ; // write OBL_LAUNCH bit (causes a reset) Write32( FLASH_CR, FLASH_CR_Value | ( OBL_LAUNCH_BIT ) ) ; __errorcontrol = 0 ; // Switch to DP Register Bank 0 WriteDP(DP_SELECT, 0x00000000); // Power Down Debug port WriteDP(DP_CTRL_STAT, 0x00000000); __var DbgMCU_CR = 0x00000007; // DBGMCU_CR: DBG_SLEEP, DBG_STOP, DBG_STANDBY __var DbgMCU_APB1_Fz1 = 0xC060183F; // DGBMCU_APB1_FZ1: Configure APB1 peripheral freeze behavior __var DbgMCU_APB1_Fz2 = 0x00000002; // DGBMCU_APB1_FZ2: Configure APB1 peripheral freeze behavior __var DbgMCU_APB2_Fz = 0x04172800; // DGBMCU_APB2_FZ : Configure APB2 peripheral freeze behavior __var TraceClk_Pin = 0x00040002; // PE2 __var TraceD0_Pin = 0x00040003; // PE3 __var TraceD1_Pin = 0x00040004; // PE4 __var TraceD2_Pin = 0x00040005; // PE5 __var TraceD3_Pin = 0x00040006; // PE6 __var DoOptionByteLoading = 0; // Disabled __var DbgMCU_CR = 0x00000007; // DBGMCU_CR: DBG_SLEEP, DBG_STOP, DBG_STANDBY __var DbgMCU_APB1_Fz1 = 0x00000000; // DGBMCU_APB1_FZ1: All Peripherals Operate as in Normal Mode __var DbgMCU_APB1_Fz2 = 0x00000000; // DGBMCU_APB1_FZ2: All Peripherals Operate as in Normal Mode __var DbgMCU_APB2_Fz = 0x00000000; // DGBMCU_APB2_FZ: All Peripherals Operate as in Normal Mode __var TraceClk_Pin = 0x00040002; // PE2 __var TraceD0_Pin = 0x00040003; // PE3 __var TraceD1_Pin = 0x00040004; // PE4 __var TraceD2_Pin = 0x00040005; // PE5 __var TraceD3_Pin = 0x00040006; // PE6 __var DoOptionByteLoading = 0; // Disabled __var DbgMCU_CR = 0x00000007; // DBGMCU_CR: DBG_SLEEP, DBG_STOP, DBG_STANDBY __var DbgMCU_APB1_Fz1 = 0xC060183F; // DGBMCU_APB1_FZ1: Configure APB1 peripheral freeze behavior __var DbgMCU_APB1_Fz2 = 0x00000002; // DGBMCU_APB1_FZ2: Configure APB1 peripheral freeze behavior __var DbgMCU_APB2_Fz = 0x04172800; // DGBMCU_APB2_FZ : Configure APB2 peripheral freeze behavior __var TraceClk_Pin = 0x00040002; // PE2 __var TraceD0_Pin = 0x00040003; // PE3 __var TraceD1_Pin = 0x00040004; // PE4 __var TraceD2_Pin = 0x00040005; // PE5 __var TraceD3_Pin = 0x00040006; // PE6 __var DoOptionByteLoading = 0; // Disabled __var DbgMCU_CR = 0x00000007; // DBGMCU_CR: DBG_SLEEP, DBG_STOP, DBG_STANDBY __var DbgMCU_APB1_Fz1 = 0xC060183F; // DGBMCU_APB1_FZ1: Configure APB1 peripheral freeze behavior __var DbgMCU_APB1_Fz2 = 0x00000002; // DGBMCU_APB1_FZ2: Configure APB1 peripheral freeze behavior __var DbgMCU_APB2_Fz = 0x04172800; // DGBMCU_APB2_FZ : Configure APB2 peripheral freeze behavior __var TraceClk_Pin = 0x00040002; // PE2 __var TraceD0_Pin = 0x00040003; // PE3 __var TraceD1_Pin = 0x00040004; // PE4 __var TraceD2_Pin = 0x00040005; // PE5 __var TraceD3_Pin = 0x00040006; // PE6 __var DoOptionByteLoading = 0; // Disabled __var DbgMCU_CR = 0x00000007; // DBGMCU_CR: DBG_SLEEP, DBG_STOP, DBG_STANDBY __var DbgMCU_APB1_Fz1 = 0xC060183F; // DGBMCU_APB1_FZ1: Configure APB1 peripheral freeze behavior __var DbgMCU_APB1_Fz2 = 0x00000002; // DGBMCU_APB1_FZ2: Configure APB1 peripheral freeze behavior __var DbgMCU_APB2_Fz = 0x04172800; // DGBMCU_APB2_FZ : Configure APB2 peripheral freeze behavior __var TraceClk_Pin = 0x00040002; // PE2 __var TraceD0_Pin = 0x00040003; // PE3 __var TraceD1_Pin = 0x00040004; // PE4 __var TraceD2_Pin = 0x00040005; // PE5 __var TraceD3_Pin = 0x00040006; // PE6 __var DoOptionByteLoading = 0; // Disabled __var DbgMCU_CR = 0x00000007; // DBGMCU_CR: DBG_SLEEP, DBG_STOP, DBG_STANDBY __var DbgMCU_APB1_Fz1 = 0xC060183F; // DGBMCU_APB1_FZ1: Configure APB1 peripheral freeze behavior __var DbgMCU_APB1_Fz2 = 0x00000002; // DGBMCU_APB1_FZ2: Configure APB1 peripheral freeze behavior __var DbgMCU_APB2_Fz = 0x04172800; // DGBMCU_APB2_FZ : Configure APB2 peripheral freeze behavior __var TraceClk_Pin = 0x00040002; // PE2 __var TraceD0_Pin = 0x00040003; // PE3 __var TraceD1_Pin = 0x00040004; // PE4 __var TraceD2_Pin = 0x00040005; // PE5 __var TraceD3_Pin = 0x00040006; // PE6 __var DoOptionByteLoading = 0; // Disabled __var DbgMCU_CR = 0x00000007; // DBGMCU_CR: DBG_SLEEP, DBG_STOP, DBG_STANDBY __var DbgMCU_APB1_Fz1 = 0xC060183F; // DGBMCU_APB1_FZ1: Configure APB1 peripheral freeze behavior __var DbgMCU_APB1_Fz2 = 0x00000002; // DGBMCU_APB1_FZ2: Configure APB1 peripheral freeze behavior __var DbgMCU_APB2_Fz = 0x04172800; // DGBMCU_APB2_FZ : Configure APB2 peripheral freeze behavior __var TraceClk_Pin = 0x00040002; // PE2 __var TraceD0_Pin = 0x00040003; // PE3 __var TraceD1_Pin = 0x00040004; // PE4 __var TraceD2_Pin = 0x00040005; // PE5 __var TraceD3_Pin = 0x00040006; // PE6 __var DoOptionByteLoading = 0; // Disabled __var DbgMCU_CR = 0x00000007; // DBGMCU_CR: DBG_SLEEP, DBG_STOP, DBG_STANDBY __var DbgMCU_APB1_Fz1 = 0xC060183F; // DGBMCU_APB1_FZ1: Configure APB1 peripheral freeze behavior __var DbgMCU_APB1_Fz2 = 0x00000002; // DGBMCU_APB1_FZ2: Configure APB1 peripheral freeze behavior __var DbgMCU_APB2_Fz = 0x04172800; // DGBMCU_APB2_FZ : Configure APB2 peripheral freeze behavior __var TraceClk_Pin = 0x00040002; // PE2 __var TraceD0_Pin = 0x00040003; // PE3 __var TraceD1_Pin = 0x00040004; // PE4 __var TraceD2_Pin = 0x00040005; // PE5 __var TraceD3_Pin = 0x00040006; // PE6 __var DoOptionByteLoading = 0; // Disabled __var DbgMCU_CR = 0x00000007; // DBGMCU_CR: DBG_SLEEP, DBG_STOP, DBG_STANDBY __var DbgMCU_APB1_Fz1 = 0xC060183F; // DGBMCU_APB1_FZ1: Configure APB1 peripheral freeze behavior __var DbgMCU_APB1_Fz2 = 0x00000002; // DGBMCU_APB1_FZ2: Configure APB1 peripheral freeze behavior __var DbgMCU_APB2_Fz = 0x04172800; // DGBMCU_APB2_FZ : Configure APB2 peripheral freeze behavior __var TraceClk_Pin = 0x00040002; // PE2 __var TraceD0_Pin = 0x00040003; // PE3 __var TraceD1_Pin = 0x00040004; // PE4 __var TraceD2_Pin = 0x00040005; // PE5 __var TraceD3_Pin = 0x00040006; // PE6 __var DoOptionByteLoading = 0; // Disabled __var DbgMCU_CR = 0x00000007; // DBGMCU_CR: DBG_SLEEP, DBG_STOP, DBG_STANDBY __var DbgMCU_APB1_Fz1 = 0xC060183F; // DGBMCU_APB1_FZ1: Configure APB1 peripheral freeze behavior __var DbgMCU_APB1_Fz2 = 0x00000002; // DGBMCU_APB1_FZ2: Configure APB1 peripheral freeze behavior __var DbgMCU_APB2_Fz = 0x04172800; // DGBMCU_APB2_FZ : Configure APB2 peripheral freeze behavior __var TraceClk_Pin = 0x00040002; // PE2 __var TraceD0_Pin = 0x00040003; // PE3 __var TraceD1_Pin = 0x00040004; // PE4 __var TraceD2_Pin = 0x00040005; // PE5 __var TraceD3_Pin = 0x00040006; // PE6 __var DoOptionByteLoading = 0; // Disabled __var DbgMCU_CR = 0x00000007; // DBGMCU_CR: DBG_SLEEP, DBG_STOP, DBG_STANDBY __var DbgMCU_APB1_Fz1 = 0xC060183F; // DGBMCU_APB1_FZ1: Configure APB1 peripheral freeze behavior __var DbgMCU_APB1_Fz2 = 0x00000002; // DGBMCU_APB1_FZ2: Configure APB1 peripheral freeze behavior __var DbgMCU_APB2_Fz = 0x04172800; // DGBMCU_APB2_FZ : Configure APB2 peripheral freeze behavior __var TraceClk_Pin = 0x00040002; // PE2 __var TraceD0_Pin = 0x00040003; // PE3 __var TraceD1_Pin = 0x00040004; // PE4 __var TraceD2_Pin = 0x00040005; // PE5 __var TraceD3_Pin = 0x00040006; // PE6 __var DoOptionByteLoading = 0; // Disabled STMicroelectronics STM32G4 Series devices STMicroelectronics STM32G4 Device and CMSIS-CORE Configuration via STM32CubeMX #define RTE_DEVICE_CUBE_MX #define CMSIS_device_header "stm32g4xx.h"