Keil STM32L4xx_DFP STMicroelectronics STM32L4 Series Device Support https://www.keil.com/pack/ https://github.com/Open-CMSIS-Pack/STM32L4xx_DFP.git LICENSES Active development ... Updated STM32Cube FW to STM32Cube_FW_L4_V1.18.0 (HAL V1.13.4). Device Support: - Added devices: STM32L443CCFx, STM32L452REYxP, STM32L452CETxP, STM32L476QGIxP, STM32L496QGIxS, STM32L4R5QGIxS, STM32L4R5QIIxP, STM32L4R5AIIxP, STM32L4P5QGIxS - Updated SVD files and documentation. - Removed STM32L4Rx, STM32L4Px Single Flash algorithm Board Examples: - Updated to STM32Cube_FW_L4_V1.18.0 - Updated to fixed pack versions CMSIS Driver: - fixed include file name in MCI_STM32L4xx.c using non portable case. CMSIS SVD: Updated to most recent versions CMSIS Flash Algorithm: - Updated flash algorithms: STM32L4Rx_2048_Dual, STM32L4Rx_1024_Dual, STM32L4P5xx_1M, STM32L4P5xx_512 - Addeded flash algorithms: STM32L4Rx_2048_Single, STM32L4Rx_1024_Single, STM32L4P5x_1024_Single, STM32L4P5x_512_Single CMSIS-Driver: - I2C: -- Corrected MasterTransmit and MasterReceive functions when not generating STOP condition (when xfer_pending is "true") -- Corrected GetDataCount function operation when DMA is used -- Corrected Bus Clear functionality -- Updated check if I2C peripheral is enabled in the CubeMx and improved user experience if it is not enabled -- Updated busy flag handling in Transmit and Receive functions -- Added DMA functionality for Slave transfers -- Added internal function to retrieve peripheral clock - USBD: -- Updated patched stm32l4xx_ll_usb.c to be in sync with latest one from the FW package V1.17.0 - SPI: Corrected STM32CubeMX configuration documentation Boards: - Examples: Overwritten default HAL_InitTick function. Added 32L496GDISCOVERY board details for better web display. PDSC file: add RAMstart/size attributes to algorithm elements CMSIS-Driver: - I2C: Corrected pins configuration Updated Pack to STM32Cube_FW_L4 Firmware Package version V1.17.0 Package Description: - Added global define USE_FULL_LL_DRIVER to component ::Device:STM32Cube LL:Common. - Added debugProbe board description. Device Support: - Updated SVD files and documentation. - Reworked device RAM size. - Added missing devices: STM32L451CETx, STM32L452CETx, STM32L462CETx, STM32L4Q5CGTxP, STM32L4Q5CGUxP, STM32L4Q5VGTxP, STM32L4Q5QGIxP, STM32L4Q5ZGTxP, STM32L4Q5AGIxP, STM32L4Q5RGTxP. - Removed devices: STM32L451RCYx, STM32L452RCYx, STM32L485xx. - Updated dbgconf files - Add missing variable DoOptionByteLoading. CMSIS Flash Algorithm: - Added algorithm for STM32L4RxxG devices. - Updated flash algorithms: STM32L4Rx_2048_Dual, STM32L4P5xx_1M, STM32L4P5xx_512: -- Added empty check, disable interrupts while programming, fix programming while IWDG in HW mode. - Fixed last word programming. CMSIS-Driver: - USBH: -- Fixed port resume occasionally getting stuck in resume signaling. -- Added compile time configuration for reducing Bulk IN NAK rate. - SPI: -- Updated Control function to: Set SPI bus speed only for master mode and disable DMA before reconfigure DMA -- Updated SPI_GetStatus function with correct error code -- Updated SPI_GetDataCount function when SPI is not initialized Board Examples: - Updated Assembler option to armclang(Auto Select). - Updated config files to CMSIS 5.8.0 and MDK-Middleware 7.13.0. Updated Pack to STM32Cube_FW_L4 Firmware Package version V1.16.0 using HAL Drivers V1.12.0 Package Description (pdsc): Added global define USE_HAL_DRIVER to the component ::Device:STM32Cube HAL:Common. Device support: Aligned devices with CubeMX DB. CMSIS Flash Algorithm: - Removed targets (STM32L4xx_512, STM32L4xx_256) from STM32L4Rx Flash Algorithm project. - Added source code for: STM32L476G-Disco QSPI, STM32L4P5G-DK OSPI, STM32L4P5G-DK PSRAM STM32L4R9I-DK PSRAM, STM32L4R9I-DK OSPI1 and STM32L4R9I-EVAL OSPI. - Added PSRAM external Loader support for STM32L4R9I-Disco. - Fixed STM32L4P5 1M internal flash Loader sector erase with DBANK mode. - Fixed STM32L4xx 512K and 128K internal flash Loader sector erase. CMSIS-Driver: - MCI: -- Replaced empty delay loops with _NOP(). -- Added handling for separate SD and MMC HAL layers. -- Added busy signal handling after CMDREND interrupt. - SPI: -- Corrected PowerControl function (to return error if Initialize was not called, to abort active transfer if power off was requested). -- Updated GetDataCount function to give accurate count. -- Corrected Uninitialize function (to power off the peripheral if it is powered). - USART: -- Added Driver_USART6 (uses LPUART1). -- Corrected GetTxCount/GetRxCount implementation. - USBD: -- Removed include of stm32l4xx_hal_pcd.h header. -- Corrected documentation of STM32CubeMx configuration. Updated Boards Examples: - Migrated CubeMX projects to V6.0.1. - Changed variant selection to "MDK-Plus" where possible. - Updated all USB Host/Device examples with user templates from MDK-Middleware v7.11.1. Updated STM32CubeL4 Firmware Package version to version 1.15.1 (using HAL Drivers V1.11.1) Board support for B-L475E-IOT01A got moved to dedicated board support pack Keil.B-L475E-IOT01A_BSP Flash Programming: - Adding support of the PSRAM loader for the STM32L4P5x Disco Board - Corrected: the OSPI loader for the STM32L4P5x Disco Board Package Description (pdsc): - Added missing devices: STM32L412R8Tx, STM32L412R8Ix, STM32L412RBTx, STM32L412RBTxP, STM32L412RBIx, STM32L412RBIxP - Renaming devices for: STM32L4P5 : STM32L4P5QGIx and STM32L4P5AGIx STM32L4Q5 : STM32L4Q5QGIx and STM32L4Q5AGIx - Eliminating Flash device and rename it to STM32L4S9VITx - Updating svd files: STM32L4x1 and STM32L412 CMSIS-Driver: - Added I2C driver - USART: -- Added Hardware Flow Control RTS/CTS - MCI: -- Added DMA support for Transmit -- Added MCI driver for STM32L4Plus devices (STM32L4Px, STM32L4Rx, STM32L4Sx, STM32L4Qx) Updated STM32CubeL4 Firmware to version 1.15.0 (requires STM32CubeMX 5.5.0 or higher) Added device support for STM32L4P5 and STM32L4Q5 Series (reworked device descriptions) Flash Programming: - Added support to the OSPI loader for the STM32L4P5x Disco Board and STM32L4Pxx/L4Qxx. - Corrected: STM32L4Rx dualbank erase function Package Description (pdsc): - Added capability to launch the Option Byte Loading after a Flash Download. - Added new STM32Cube HAL Components: MMC, PKA and PSSI. - Added new STM32Cube LL Component: PKA. - Added a patch to stm32l4xx_hal_def.h to support ARM Compiler 6. - FrameworkCubeMX_gpdsc.ftl: Added support for Timebase Source TIMx. CMSIS-Driver: - USB Device: -- Updated USBD_EndpointConfigure function to check that maximum packet size requested fits into configured FIFO (compile time configured). -- Added driver for STM32L412, STM32L422, STM32L432, STM32L433, STM32L442, STM32L443, STM32L452 and STM32L462 devices. Board support: - Updated examples with CMSIS-RTOS terminating app_main thread with osThreadExit() to avoid endless loop. - Added B-L475E-IOT01 board. - Added Blinky Low Power for STM32L476G-EVAL board. Corrected: launching STM32CubeMX via "play" button for existing projects overwrites with a new STM32CubeMX project file instead of loading it. CMSIS Driver: - SPI: Removed __HAL_SPI_ENABLE from SPI_Control function. This DFP requires STM32CubeMX V5.0 and STM32Cube_FW_L4 V1.13.0 or higher to be installed. This pack only contains 'Drivers', 'Documentation' and 'Fonts' from Firmware Library pack. New projects require the component 'Device:STM32Cube Framework:STM32CubeMX' for configuration of pins and clocks. Device support: - Added STM32L412, STM32L422 device support. - Added some STM32L4R device variants. - Added STM32L4R 1024KB Flash variants. - Added device STM32L496VE. - Corrected dbgconf file selection. CMSIS Driver: - SPI: Corrected Slave select handling. - USART: Corrected UARTx/USARTx related typing mistakes. - USB Device: -- Updated to be compliant with HAL Driver version 1.9.0. -- USB Device: Corrected transmitted count for non-control IN endpoints. - USB Host: Corrected Device Family name in USBH CMSIS driver description. STM32CubeMX integration - MX_Device.h generation: - Updated parsing of USART virtual mode. - Updated generation of macros: Added handling for '(' and ')' symbols. Board example projects: - Updated Blinky example projects. - Updated board support LED_*.c files. This DFP requires STM32CubeMX V4.22.1 and STM32Cube_FW_L4 V1.9.0 or higher to be installed. Reduced overall pack size by extracting only 'Drivers', 'Documentation' and 'Fonts' from Firmware Library pack. Updated documentation for STM32Cube Framework usage. - New projects require the component 'Device:STM32Cube Framework:STM32CubeMX' for configuration of pins and clocks. Device support: - Added STM32L4Rx, STM32L4Sx device support. CMSIS Driver: - Added USART driver. - Added SPI driver. - Added USB Host and Device drivers without CMSIS-RTOS dependency. Example projects: - Introducing debug and release project targets focussing on debug visibility versus application performance. - Added STM32L4R9I-Eval board support. - Updated STM32L476G-EVAL board support. - Updated STM32L496G-DISCO board support. Added STM32CubeMX support based on STM32Cube_FW_L4_V1.8.0 - Removed large media files to reduce the overall pack size - Added a patch to stm32l4xx_hal_def.h to support ARM Compiler 6. Added STM32L442 basic device support. Added STM32L496G-Discovery Board Support: - Added File_Demo Example - Added RTOS Blinky example Updated documentation. Updated Flash Programming Algorithms. Updated Pack Description (pdsc) - Added debug sequences and debug configuration - Corrected SRAM1/SRAM2 settings. Added basic device support for subfamilies STM32L4A6 and STM32L496 Updated device support files to version V1.2.0 (except subfamilies STM32L4A6, STM32L496) Added QUADSPI peripheral to STM32L4x2.svd, STM32L4x3.svd Added device support for subfamilies STM32L462 STM32L452, STM32L451 Updated documentation. Added device support for subfamilies STM32L431, STM32L432, STM32L433, STM32L443 Updated documentation. Updated device support files and documentation Initial version of STM32L4 Device Family Pack. ST Device Support Device Family Package STMicroelectronics STM32L4 STM32L4xx STM32L4+ STM32L4P5x STM32L4Q5x Ultra-low-power STM32L4 MCUs with Arm Cortex-M4 core, MPU, DSP, ART Accelerator, FPU, 150 DMIPS at 120MHz. --branchpatch=sdcomp-29491-629360 Sequence("CheckID"); // Replication of Standard Functionality Write32(0xE000EDF0, 0xA05F0001); // Enable Core Debug via DHCSR Write32(0xE0042004, DbgMCU_CR); // DBGMCU_CR: Configure MCU Debug Write32(0xE0042008, DbgMCU_APB1_Fz1); // DBGMCU_APB1_FZ1: Configure APB1 Peripheral Freeze Behavior Write32(0xE004200C, DbgMCU_APB1_Fz2); // DBGMCU_APB1_FZ2: Configure APB1 Peripheral Freeze Behavior Write32(0xE0042010, DbgMCU_APB2_Fz); // DBGMCU_APB2_FZ: Configure APB2 Peripheral Freeze Behavior __var traceSWO = (__traceout & 0x1) != 0; // SWO (asynchronous) Trace Selected? __var traceTPIU = (__traceout & 0x2) != 0; // TPIU (synchronous) Trace Selected? Sequence("EnableTraceSWO"); // Call SWO Trace Setup Sequence("EnableTraceTPIU"); // Call TPIU Trace Setup // Nothing required for SWO Trace __var traceSWO = (__traceout & 0x1) != 0; // SWO enabled? __var traceTPIU = (__traceout & 0x2) != 0; // Synchronous trace port enabled? Sequence("DisableTraceSWO"); Sequence("DisableTraceTPIU"); __var pidr1 = 0; __var pidr2 = 0; __var jep106id = 0; __var ROMTableBase = 0; __ap = 0; // AHB-AP ROMTableBase = ReadAP(0xF8) & ~0x3; pidr1 = Read32(ROMTableBase + 0x0FE4); pidr2 = Read32(ROMTableBase + 0x0FE8); jep106id = ((pidr2 & 0x7) << 4 ) | ((pidr1 >> 4) & 0xF); Query(0, "Not a genuine ST Device! Abort connection", 1); Message(2, "Not a genuine ST Device! Abort connection."); __var dbgmcu_val = 0; // DBGMCU_CR Value __var dbgmcu_trace_val = 0; // DBGMCU_CR Value dbgmcu_val = Read32(0xE0042004) & (~0xE0); // Read DBGMCU_CR and clear trace setup dbgmcu_trace_val = (1 << 5); // Trace I/O Enable + Trace Mode Asynchronous Sequence("ConfigureTraceSWOPin"); Write32(0xE0042004, dbgmcu_val | dbgmcu_trace_val); // Write DBGMCU_CR: Trace Settings __var dbgmcu_val = 0; // DBGMCU_CR Value dbgmcu_val = Read32(0xE0042004) & (~0xE0); // Read DBGMCU_CR and clear trace setup Write32(0xE0042004, dbgmcu_val); // Write DBGMCU_CR: Trace Settings __var width = (__traceout & 0x003F0000) >> 16; __var dbgmcu_val = 0; // DBGMCU_CR Value __var dbgmcu_trace_val = 0; // DBGMCU_CR Value dbgmcu_val = Read32(0xE0042004) & (~0xE0); // Read DBGMCU_CR and clear trace setup Sequence("ConfigureTraceTPIUPins"); dbgmcu_trace_val = (3 << 5); dbgmcu_trace_val = (5 << 5); dbgmcu_trace_val = (7 << 5); Write32(0xE0042004, dbgmcu_val | dbgmcu_trace_val); // Write DBGMCU_CR: Trace Settings __var dbgmcu_val = 0; // DBGMCU_CR Value dbgmcu_val = Read32(0xE0042004) & (~0xE0); // Read DBGMCU_CR and clear trace setup Write32(0xE0042004, dbgmcu_val); // Write DBGMCU_CR: Trace Settings __var pin = 0; __var port = 0; __var portAdr = 0; __var pos = 0; __var SWO_Pin = 0x00010003; // PB3 pin = ((SWO_Pin ) & 0x0000FFFF); port = ((SWO_Pin >> 16) & 0x0000FFFF); portAdr = 0x48000000 + (((SWO_Pin >> 16) & 0x0000FFFF) * 0x400); pos = pin * 2; Write32(0x4002104C, ((Read32(0x4002104C ) ) | (1 << port)) ); // RCC_AHB2ENR: IO port clock enable Write32(portAdr + 0x00, ((Read32(portAdr + 0x00) & ~( 3 << pos)) | (2 << pos )) ); // GPIOx_MODER: Set Mode (Alternate Function) Write32(portAdr + 0x08, ((Read32(portAdr + 0x08) ) | (3 << pos )) ); // GPIOx_OSPEEDR: Set Speed (Very High Speed) Write32(portAdr + 0x0C, ((Read32(portAdr + 0x0C) & ~( 3 << pos)) ) ); // GPIOx_PUPDR: Set I/O to no pull-up/pull-down pos = ((pin ) & 7) * 4; Write32(portAdr + 0x20, ((Read32(portAdr + 0x20) & ~(15 << pos)) ) ); // GPIOx_AFRL: Alternate Function to AF0 pos = ((pin - 8) & 7) * 4; Write32(portAdr + 0x24, ((Read32(portAdr + 0x24) & ~(15 << pos)) ) ); // GPIOx_AFRH: Alternate Function to AF0 __var pin = 8; __var port = 0; __var portAdr = 0; __var pos = 0; __var width = (__traceout & 0x003F0000) >> 16; pin = (TraceClk_Pin ) & 0x0000FFFF; port = (TraceClk_Pin >> 16) & 0x0000FFFF; portAdr = 0x48000000 + (((TraceClk_Pin >> 16) & 0x0000FFFF) * 0x400); pos = pin * 2; Write32(0x4002104C, ((Read32(0x4002104C ) ) | (1 << port)) ); // RCC_AHB2ENR: IO port clock enable Write32(portAdr + 0x00, ((Read32(portAdr + 0x00) & ~( 3 << pos)) | (2 << pos )) ); // GPIOx_MODER: Set Mode (Alternate Function) Write32(portAdr + 0x08, ((Read32(portAdr + 0x08) ) | (3 << pos )) ); // GPIOx_OSPEEDR: Set Speed (Very High Speed) Write32(portAdr + 0x0C, ((Read32(portAdr + 0x0C) & ~( 3 << pos)) ) ); // GPIOx_PUPDR: Set I/O to no pull-up/pull-down pos = ((pin ) & 7) * 4; Write32(portAdr + 0x20, ((Read32(portAdr + 0x20) & ~(15 << pos)) ) ); // GPIOx_AFRL: Alternate Function to AF0 pos = ((pin - 8) & 7) * 4; Write32(portAdr + 0x24, ((Read32(portAdr + 0x24) & ~(15 << pos)) ) ); // GPIOx_AFRH: Alternate Function to AF0 pin = (TraceD0_Pin ) & 0x0000FFFF; port = (TraceD0_Pin >> 16) & 0x0000FFFF; portAdr = 0x48000000 + (((TraceD0_Pin >> 16) & 0x0000FFFF) * 0x400); pos = pin * 2; Write32(0x4002104C, ((Read32(0x4002104C ) ) | (1 << port)) ); // RCC_AHB2ENR: IO port clock enable Write32(portAdr + 0x00, ((Read32(portAdr + 0x00) & ~( 3 << pos)) | (2 << pos )) ); // GPIOx_MODER: Set Mode (Alternate Function) Write32(portAdr + 0x08, ((Read32(portAdr + 0x08) ) | (3 << pos )) ); // GPIOx_OSPEEDR: Set Speed (Very High Speed) Write32(portAdr + 0x0C, ((Read32(portAdr + 0x0C) & ~( 3 << pos)) ) ); // GPIOx_PUPDR: Set I/O to no pull-up/pull-down pos = ((pin ) & 7) * 4; Write32(portAdr + 0x20, ((Read32(portAdr + 0x20) & ~(15 << pos)) ) ); // GPIOx_AFRL: Alternate Function to AF0 pos = ((pin - 8) & 7) * 4; Write32(portAdr + 0x24, ((Read32(portAdr + 0x24) & ~(15 << pos)) ) ); // GPIOx_AFRH: Alternate Function to AF0 pin = (TraceD1_Pin ) & 0x0000FFFF; port = (TraceD1_Pin >> 16) & 0x0000FFFF; portAdr = 0x48000000 + (((TraceD1_Pin >> 16) & 0x0000FFFF) * 0x400); pos = pin * 2; Write32(0x4002104C, ((Read32(0x4002104C ) ) | (1 << port)) ); // RCC_AHB2ENR: IO port clock enable Write32(portAdr + 0x00, ((Read32(portAdr + 0x00) & ~( 3 << pos)) | (2 << pos )) ); // GPIOx_MODER: Set Mode (Alternate Function) Write32(portAdr + 0x08, ((Read32(portAdr + 0x08) ) | (3 << pos )) ); // GPIOx_OSPEEDR: Set Speed (Very High Speed) Write32(portAdr + 0x0C, ((Read32(portAdr + 0x0C) & ~( 3 << pos)) ) ); // GPIOx_PUPDR: Set I/O to no pull-up/pull-down pos = ((pin ) & 7) * 4; Write32(portAdr + 0x20, ((Read32(portAdr + 0x20) & ~(15 << pos)) ) ); // GPIOx_AFRL: Alternate Function to AF0 pos = ((pin - 8) & 7) * 4; Write32(portAdr + 0x24, ((Read32(portAdr + 0x24) & ~(15 << pos)) ) ); // GPIOx_AFRH: Alternate Function to AF0 pin = (TraceD2_Pin ) & 0x0000FFFF; port = (TraceD2_Pin >> 16) & 0x0000FFFF; portAdr = 0x48000000 + (((TraceD2_Pin >> 16) & 0x0000FFFF) * 0x400); pos = pin * 2; Write32(0x4002104C, ((Read32(0x4002104C ) ) | (1 << port)) ); // RCC_AHB2ENR: IO port clock enable Write32(portAdr + 0x00, ((Read32(portAdr + 0x00) & ~( 3 << pos)) | (2 << pos )) ); // GPIOx_MODER: Set Mode (Alternate Function) Write32(portAdr + 0x08, ((Read32(portAdr + 0x08) ) | (3 << pos )) ); // GPIOx_OSPEEDR: Set Speed (Very High Speed) Write32(portAdr + 0x0C, ((Read32(portAdr + 0x0C) & ~( 3 << pos)) ) ); // GPIOx_PUPDR: Set I/O to no pull-up/pull-down pos = ((pin ) & 7) * 4; Write32(portAdr + 0x20, ((Read32(portAdr + 0x20) & ~(15 << pos)) ) ); // GPIOx_AFRL: Alternate Function to AF0 pos = ((pin - 8) & 7) * 4; Write32(portAdr + 0x24, ((Read32(portAdr + 0x24) & ~(15 << pos)) ) ); // GPIOx_AFRH: Alternate Function to AF0 pin = (TraceD3_Pin ) & 0x0000FFFF; port = (TraceD3_Pin >> 16) & 0x0000FFFF; portAdr = 0x48000000 + (((TraceD3_Pin >> 16) & 0x0000FFFF) * 0x400); pos = pin * 2; Write32(0x4002104C, ((Read32(0x4002104C ) ) | (1 << port)) ); // RCC_AHB2ENR: IO port clock enable Write32(portAdr + 0x00, ((Read32(portAdr + 0x00) & ~( 3 << pos)) | (2 << pos )) ); // GPIOx_MODER: Set Mode (Alternate Function) Write32(portAdr + 0x08, ((Read32(portAdr + 0x08) ) | (3 << pos )) ); // GPIOx_OSPEEDR: Set Speed (Very High Speed) Write32(portAdr + 0x0C, ((Read32(portAdr + 0x0C) & ~( 3 << pos)) ) ); // GPIOx_PUPDR: Set I/O to no pull-up/pull-down pos = ((pin ) & 7) * 4; Write32(portAdr + 0x20, ((Read32(portAdr + 0x20) & ~(15 << pos)) ) ); // GPIOx_AFRL: Alternate Function to AF0 pos = ((pin - 8) & 7) * 4; Write32(portAdr + 0x24, ((Read32(portAdr + 0x24) & ~(15 << pos)) ) ); // GPIOx_AFRH: Alternate Function to AF0 __var connectionFlash = ( __connection & 0xF ) == 2 ; __var FLASH_BASE = 0x40022000 ; __var FLASH_CR = FLASH_BASE + 0x14 ; __var OBL_LAUNCH_BIT = ( 1 << 27 ) ; __var LOCK_BIT = ( 1 << 31 ) ; __var OPTLOCK_BIT = ( 1 << 30 ) ; __var FLASH_KEYR = FLASH_BASE + 0x08 ; __var FLASH_KEY1 = 0x45670123 ; __var FLASH_KEY2 = 0xCDEF89AB ; __var FLASH_OPTKEYR = FLASH_BASE + 0x0C ; __var FLASH_OPTKEY1 = 0x08192A3B ; __var FLASH_OPTKEY2 = 0x4C5D6E7F ; __var FLASH_CR_Value = 0 ; __var DoDebugPortStop = 1 ; __var DP_CTRL_STAT = 0x4 ; __var DP_SELECT = 0x8 ; // unlock the FLASH_CR Write32( FLASH_KEYR, FLASH_KEY1 ) ; Write32( FLASH_KEYR, FLASH_KEY2 ) ; // unlock the option byte block Write32( FLASH_OPTKEYR, FLASH_OPTKEY1 ) ; Write32( FLASH_OPTKEYR, FLASH_OPTKEY2 ) ; FLASH_CR_Value = Read32( FLASH_CR ) ; DoDebugPortStop = 0 ; __errorcontrol = 1 ; // write OBL_LAUNCH bit (causes a reset) Write32( FLASH_CR, FLASH_CR_Value | ( OBL_LAUNCH_BIT ) ) ; __errorcontrol = 0 ; // Switch to DP Register Bank 0 WriteDP(DP_SELECT, 0x00000000); // Power Down Debug port WriteDP(DP_CTRL_STAT, 0x00000000); __var DbgMCU_CR = 0x00000007; // DBGMCU_CR: DBG_SLEEP, DBG_STOP, DBG_STANDBY __var DbgMCU_APB1_Fz1 = 0x82E01831; // DGBMCU_APB1_FZ1: All Peripherals Operate as in Normal Mode __var DbgMCU_APB1_Fz2 = 0x00000020; // DGBMCU_APB1_FZ2: All Peripherals Operate as in Normal Mode __var DbgMCU_APB2_Fz = 0x00030800; // DGBMCU_APB2_FZ: All Peripherals Operate as in Normal Mode __var TraceClk_Pin = 0x00040002; // PE2 __var TraceD0_Pin = 0x00040003; // PE3 __var TraceD1_Pin = 0x00040004; // PE4 __var TraceD2_Pin = 0x00040005; // PE5 __var TraceD3_Pin = 0x00040006; // PE6 __var DoOptionByteLoading = 0; // Disabled __var DbgMCU_CR = 0x00000007; // DBGMCU_CR: DBG_SLEEP, DBG_STOP, DBG_STANDBY __var DbgMCU_APB1_Fz1 = 0x82E01831; // DGBMCU_APB1_FZ1: All Peripherals Operate as in Normal Mode __var DbgMCU_APB1_Fz2 = 0x00000020; // DGBMCU_APB1_FZ2: All Peripherals Operate as in Normal Mode __var DbgMCU_APB2_Fz = 0x00030800; // DGBMCU_APB2_FZ: All Peripherals Operate as in Normal Mode __var TraceClk_Pin = 0x00040002; // PE2 __var TraceD0_Pin = 0x00040003; // PE3 __var TraceD1_Pin = 0x00040004; // PE4 __var TraceD2_Pin = 0x00040005; // PE5 __var TraceD3_Pin = 0x00040006; // PE6 __var DoOptionByteLoading = 0; // Disabled __var DbgMCU_CR = 0x00000007; // DBGMCU_CR: DBG_SLEEP, DBG_STOP, DBG_STANDBY __var DbgMCU_APB1_Fz1 = 0x82E01831; // DGBMCU_APB1_FZ1: All Peripherals Operate as in Normal Mode __var DbgMCU_APB1_Fz2 = 0x00000020; // DGBMCU_APB1_FZ2: All Peripherals Operate as in Normal Mode __var DbgMCU_APB2_Fz = 0x00030800; // DGBMCU_APB2_FZ: All Peripherals Operate as in Normal Mode __var TraceClk_Pin = 0x00040002; // PE2 __var TraceD0_Pin = 0x00040003; // PE3 __var TraceD1_Pin = 0x00040004; // PE4 __var TraceD2_Pin = 0x00040005; // PE5 __var TraceD3_Pin = 0x00040006; // PE6 __var DoOptionByteLoading = 0; // Disabled __var DbgMCU_CR = 0x00000007; // DBGMCU_CR: DBG_SLEEP, DBG_STOP, DBG_STANDBY __var DbgMCU_APB1_Fz1 = 0x82E01831; // DGBMCU_APB1_FZ1: All Peripherals Operate as in Normal Mode __var DbgMCU_APB1_Fz2 = 0x00000020; // DGBMCU_APB1_FZ2: All Peripherals Operate as in Normal Mode __var DbgMCU_APB2_Fz = 0x00030800; // DGBMCU_APB2_FZ: All Peripherals Operate as in Normal Mode __var TraceClk_Pin = 0x00040002; // PE2 __var TraceD0_Pin = 0x00040003; // PE3 __var TraceD1_Pin = 0x00040004; // PE4 __var TraceD2_Pin = 0x00040005; // PE5 __var TraceD3_Pin = 0x00040006; // PE6 __var DoOptionByteLoading = 0; // Disabled __var DbgMCU_CR = 0x00000007; // DBGMCU_CR: DBG_SLEEP, DBG_STOP, DBG_STANDBY __var DbgMCU_APB1_Fz1 = 0x82E01831; // DGBMCU_APB1_FZ1: All Peripherals Operate as in Normal Mode __var DbgMCU_APB1_Fz2 = 0x00000020; // DGBMCU_APB1_FZ2: All Peripherals Operate as in Normal Mode __var DbgMCU_APB2_Fz = 0x00030800; // DGBMCU_APB2_FZ: All Peripherals Operate as in Normal Mode __var TraceClk_Pin = 0x00040002; // PE2 __var TraceD0_Pin = 0x00040003; // PE3 __var TraceD1_Pin = 0x00040004; // PE4 __var TraceD2_Pin = 0x00040005; // PE5 __var TraceD3_Pin = 0x00040006; // PE6 __var DoOptionByteLoading = 0; // Disabled __var DbgMCU_CR = 0x00000007; // DBGMCU_CR: DBG_SLEEP, DBG_STOP, DBG_STANDBY __var DbgMCU_APB1_Fz1 = 0x82E01831; // DGBMCU_APB1_FZ1: All Peripherals Operate as in Normal Mode __var DbgMCU_APB1_Fz2 = 0x00000020; // DGBMCU_APB1_FZ2: All Peripherals Operate as in Normal Mode __var DbgMCU_APB2_Fz = 0x00030800; // DGBMCU_APB2_FZ: All Peripherals Operate as in Normal Mode __var TraceClk_Pin = 0x00040002; // PE2 __var TraceD0_Pin = 0x00040003; // PE3 __var TraceD1_Pin = 0x00040004; // PE4 __var TraceD2_Pin = 0x00040005; // PE5 __var TraceD3_Pin = 0x00040006; // PE6 __var DoOptionByteLoading = 0; // Disabled __var DbgMCU_CR = 0x00000007; // DBGMCU_CR: DBG_SLEEP, DBG_STOP, DBG_STANDBY __var DbgMCU_APB1_Fz1 = 0x82E01831; // DGBMCU_APB1_FZ1: All Peripherals Operate as in Normal Mode __var DbgMCU_APB1_Fz2 = 0x00000020; // DGBMCU_APB1_FZ2: All Peripherals Operate as in Normal Mode __var DbgMCU_APB2_Fz = 0x00030800; // DGBMCU_APB2_FZ: All Peripherals Operate as in Normal Mode __var TraceClk_Pin = 0x00040002; // PE2 __var TraceD0_Pin = 0x00040003; // PE3 __var TraceD1_Pin = 0x00040004; // PE4 __var TraceD2_Pin = 0x00040005; // PE5 __var TraceD3_Pin = 0x00040006; // PE6 __var DoOptionByteLoading = 0; // Disabled __var DbgMCU_CR = 0x00000007; // DBGMCU_CR: DBG_SLEEP, DBG_STOP, DBG_STANDBY __var DbgMCU_APB1_Fz1 = 0x82E01831; // DGBMCU_APB1_FZ1: All Peripherals Operate as in Normal Mode __var DbgMCU_APB1_Fz2 = 0x00000020; // DGBMCU_APB1_FZ2: All Peripherals Operate as in Normal Mode __var DbgMCU_APB2_Fz = 0x00030800; // DGBMCU_APB2_FZ: All Peripherals Operate as in Normal Mode __var TraceClk_Pin = 0x00040002; // PE2 __var TraceD0_Pin = 0x00040003; // PE3 __var TraceD1_Pin = 0x00040004; // PE4 __var TraceD2_Pin = 0x00040005; // PE5 __var TraceD3_Pin = 0x00040006; // PE6 __var DoOptionByteLoading = 0; // Disabled __var DbgMCU_CR = 0x00000007; // DBGMCU_CR: DBG_SLEEP, DBG_STOP, DBG_STANDBY __var DbgMCU_APB1_Fz1 = 0x82E01831; // DGBMCU_APB1_FZ1: All Peripherals Operate as in Normal Mode __var DbgMCU_APB1_Fz2 = 0x00000020; // DGBMCU_APB1_FZ2: All Peripherals Operate as in Normal Mode __var DbgMCU_APB2_Fz = 0x00030800; // DGBMCU_APB2_FZ: All Peripherals Operate as in Normal Mode __var TraceClk_Pin = 0x00040002; // PE2 __var TraceD0_Pin = 0x00040003; // PE3 __var TraceD1_Pin = 0x00040004; // PE4 __var TraceD2_Pin = 0x00040005; // PE5 __var TraceD3_Pin = 0x00040006; // PE6 __var DoOptionByteLoading = 0; // Disabled __var DbgMCU_CR = 0x00000007; // DBGMCU_CR: DBG_SLEEP, DBG_STOP, DBG_STANDBY __var DbgMCU_APB1_Fz1 = 0x82E01831; // DGBMCU_APB1_FZ1: All Peripherals Operate as in Normal Mode __var DbgMCU_APB1_Fz2 = 0x00000020; // DGBMCU_APB1_FZ2: All Peripherals Operate as in Normal Mode __var DbgMCU_APB2_Fz = 0x00030800; // DGBMCU_APB2_FZ: All Peripherals Operate as in Normal Mode __var TraceClk_Pin = 0x00040002; // PE2 __var TraceD0_Pin = 0x00040003; // PE3 __var TraceD1_Pin = 0x00040004; // PE4 __var TraceD2_Pin = 0x00040005; // PE5 __var TraceD3_Pin = 0x00040006; // PE6 __var DoOptionByteLoading = 0; // Disabled __var DbgMCU_CR = 0x00000007; // DBGMCU_CR: DBG_SLEEP, DBG_STOP, DBG_STANDBY __var DbgMCU_APB1_Fz1 = 0x86E0183F; // DGBMCU_APB1_FZ1: All Peripherals Operate as in Normal Mode __var DbgMCU_APB1_Fz2 = 0x00000020; // DGBMCU_APB1_FZ2: All Peripherals Operate as in Normal Mode __var DbgMCU_APB2_Fz = 0x00072800; // DGBMCU_APB2_FZ: All Peripherals Operate as in Normal Mode __var TraceClk_Pin = 0x00040002; // PE2 __var TraceD0_Pin = 0x00040003; // PE3 __var TraceD1_Pin = 0x00040004; // PE4 __var TraceD2_Pin = 0x00040005; // PE5 __var TraceD3_Pin = 0x00040006; // PE6 __var DoOptionByteLoading = 0; // Disabled __var DbgMCU_CR = 0x00000007; // DBGMCU_CR: DBG_SLEEP, DBG_STOP, DBG_STANDBY __var DbgMCU_APB1_Fz1 = 0x86E0183F; // DGBMCU_APB1_FZ1: All Peripherals Operate as in Normal Mode __var DbgMCU_APB1_Fz2 = 0x00000022; // DGBMCU_APB1_FZ2: All Peripherals Operate as in Normal Mode __var DbgMCU_APB2_Fz = 0x00072800; // DGBMCU_APB2_FZ: All Peripherals Operate as in Normal Mode __var TraceClk_Pin = 0x00040002; // PE2 __var TraceD0_Pin = 0x00040003; // PE3 __var TraceD1_Pin = 0x00040004; // PE4 __var TraceD2_Pin = 0x00040005; // PE5 __var TraceD3_Pin = 0x00040006; // PE6 __var DoOptionByteLoading = 0; // Disabled __var DbgMCU_CR = 0x00000007; // DBGMCU_CR: DBG_SLEEP, DBG_STOP, DBG_STANDBY __var DbgMCU_APB1_Fz1 = 0x86E0183F; // DGBMCU_APB1_FZ1: All Peripherals Operate as in Normal Mode __var DbgMCU_APB1_Fz2 = 0x00000022; // DGBMCU_APB1_FZ2: All Peripherals Operate as in Normal Mode __var DbgMCU_APB2_Fz = 0x00072800; // DGBMCU_APB2_FZ: All Peripherals Operate as in Normal Mode __var TraceClk_Pin = 0x00040002; // PE2 __var TraceD0_Pin = 0x00040003; // PE3 __var TraceD1_Pin = 0x00040004; // PE4 __var TraceD2_Pin = 0x00040005; // PE5 __var TraceD3_Pin = 0x00040006; // PE6 __var DoOptionByteLoading = 0; // Disabled __var DbgMCU_CR = 0x00000007; // DBGMCU_CR: DBG_SLEEP, DBG_STOP, DBG_STANDBY __var DbgMCU_APB1_Fz1 = 0x86E0183F; // DGBMCU_APB1_FZ1: All Peripherals Operate as in Normal Mode __var DbgMCU_APB1_Fz2 = 0x00000022; // DGBMCU_APB1_FZ2: All Peripherals Operate as in Normal Mode __var DbgMCU_APB2_Fz = 0x00072800; // DGBMCU_APB2_FZ: All Peripherals Operate as in Normal Mode __var TraceClk_Pin = 0x00040002; // PE2 __var TraceD0_Pin = 0x00040003; // PE3 __var TraceD1_Pin = 0x00040004; // PE4 __var TraceD2_Pin = 0x00040005; // PE5 __var TraceD3_Pin = 0x00040006; // PE6 __var DoOptionByteLoading = 0; // Disabled __var DbgMCU_CR = 0x00000007; // DBGMCU_CR: DBG_SLEEP, DBG_STOP, DBG_STANDBY __var DbgMCU_APB1_Fz1 = 0x86E0183F; // DGBMCU_APB1_FZ1: All Peripherals Operate as in Normal Mode __var DbgMCU_APB1_Fz2 = 0x00000022; // DGBMCU_APB1_FZ2: All Peripherals Operate as in Normal Mode __var DbgMCU_APB2_Fz = 0x00072800; // DGBMCU_APB2_FZ: All Peripherals Operate as in Normal Mode __var TraceClk_Pin = 0x00040002; // PE2 __var TraceD0_Pin = 0x00040003; // PE3 __var TraceD1_Pin = 0x00040004; // PE4 __var TraceD2_Pin = 0x00040005; // PE5 __var TraceD3_Pin = 0x00040006; // PE6 __var DoOptionByteLoading = 0; // Disabled __var DbgMCU_CR = 0x00000007; // DBGMCU_CR: DBG_SLEEP, DBG_STOP, DBG_STANDBY __var DbgMCU_APB1_Fz1 = 0x86E0183F; // DGBMCU_APB1_FZ1: All Peripherals Operate as in Normal Mode __var DbgMCU_APB1_Fz2 = 0x00000022; // DGBMCU_APB1_FZ2: All Peripherals Operate as in Normal Mode __var DbgMCU_APB2_Fz = 0x00072800; // DGBMCU_APB2_FZ: All Peripherals Operate as in Normal Mode __var TraceClk_Pin = 0x00040002; // PE2 __var TraceD0_Pin = 0x00040003; // PE3 __var TraceD1_Pin = 0x00040004; // PE4 __var TraceD2_Pin = 0x00040005; // PE5 __var TraceD3_Pin = 0x00040006; // PE6 __var DoOptionByteLoading = 0; // Disabled __var DbgMCU_CR = 0x00000007; // DBGMCU_CR: DBG_SLEEP, DBG_STOP, DBG_STANDBY __var DbgMCU_APB1_Fz1 = 0x82E0183F; // DGBMCU_APB1_FZ1: All Peripherals Operate as in Normal Mode __var DbgMCU_APB1_Fz2 = 0x00000022; // DGBMCU_APB1_FZ2: All Peripherals Operate as in Normal Mode __var DbgMCU_APB2_Fz = 0x00072800; // DGBMCU_APB2_FZ: All Peripherals Operate as in Normal Mode __var TraceClk_Pin = 0x00040002; // PE2 __var TraceD0_Pin = 0x00040003; // PE3 __var TraceD1_Pin = 0x00040004; // PE4 __var TraceD2_Pin = 0x00040005; // PE5 __var TraceD3_Pin = 0x00040006; // PE6 __var DoOptionByteLoading = 0; // Disabled __var DbgMCU_CR = 0x00000007; // DBGMCU_CR: DBG_SLEEP, DBG_STOP, DBG_STANDBY __var DbgMCU_APB1_Fz1 = 0x82E0183F; // DGBMCU_APB1_FZ1: All Peripherals Operate as in Normal Mode __var DbgMCU_APB1_Fz2 = 0x00000022; // DGBMCU_APB1_FZ2: All Peripherals Operate as in Normal Mode __var DbgMCU_APB2_Fz = 0x00072800; // DGBMCU_APB2_FZ: All Peripherals Operate as in Normal Mode __var TraceClk_Pin = 0x00040002; // PE2 __var TraceD0_Pin = 0x00040003; // PE3 __var TraceD1_Pin = 0x00040004; // PE4 __var TraceD2_Pin = 0x00040005; // PE5 __var TraceD3_Pin = 0x00040006; // PE6 __var DoOptionByteLoading = 0; // Disabled __var DbgMCU_CR = 0x00000007; // DBGMCU_CR: DBG_SLEEP, DBG_STOP, DBG_STANDBY __var DbgMCU_APB1_Fz1 = 0x82E0183F; // DGBMCU_APB1_FZ1: All Peripherals Operate as in Normal Mode __var DbgMCU_APB1_Fz2 = 0x00000022; // DGBMCU_APB1_FZ2: All Peripherals Operate as in Normal Mode __var DbgMCU_APB2_Fz = 0x00072800; // DGBMCU_APB2_FZ: All Peripherals Operate as in Normal Mode __var TraceClk_Pin = 0x00040002; // PE2 __var TraceD0_Pin = 0x00040003; // PE3 __var TraceD1_Pin = 0x00040004; // PE4 __var TraceD2_Pin = 0x00040005; // PE5 __var TraceD3_Pin = 0x00040006; // PE6 __var DoOptionByteLoading = 0; // Disabled __var DbgMCU_CR = 0x00000007; // DBGMCU_CR: DBG_SLEEP, DBG_STOP, DBG_STANDBY __var DbgMCU_APB1_Fz1 = 0x82E0183F; // DGBMCU_APB1_FZ1: All Peripherals Operate as in Normal Mode __var DbgMCU_APB1_Fz2 = 0x00000022; // DGBMCU_APB1_FZ2: All Peripherals Operate as in Normal Mode __var DbgMCU_APB2_Fz = 0x00072800; // DGBMCU_APB2_FZ: All Peripherals Operate as in Normal Mode __var TraceClk_Pin = 0x00040002; // PE2 __var TraceD0_Pin = 0x00040003; // PE3 __var TraceD1_Pin = 0x00040004; // PE4 __var TraceD2_Pin = 0x00040005; // PE5 __var TraceD3_Pin = 0x00040006; // PE6 __var DoOptionByteLoading = 0; // Disabled __var DbgMCU_CR = 0x00000007; // DBGMCU_CR: DBG_SLEEP, DBG_STOP, DBG_STANDBY __var DbgMCU_APB1_Fz1 = 0x82E0183F; // DGBMCU_APB1_FZ1: All Peripherals Operate as in Normal Mode __var DbgMCU_APB1_Fz2 = 0x00000022; // DGBMCU_APB1_FZ2: All Peripherals Operate as in Normal Mode __var DbgMCU_APB2_Fz = 0x00072800; // DGBMCU_APB2_FZ: All Peripherals Operate as in Normal Mode __var TraceClk_Pin = 0x00040002; // PE2 __var TraceD0_Pin = 0x00040003; // PE3 __var TraceD1_Pin = 0x00040004; // PE4 __var TraceD2_Pin = 0x00040005; // PE5 __var TraceD3_Pin = 0x00040006; // PE6 __var DoOptionByteLoading = 0; // Disabled __var DbgMCU_CR = 0x00000007; // DBGMCU_CR: DBG_SLEEP, DBG_STOP, DBG_STANDBY __var DbgMCU_APB1_Fz1 = 0x82E0183F; // DGBMCU_APB1_FZ1: All Peripherals Operate as in Normal Mode __var DbgMCU_APB1_Fz2 = 0x00000022; // DGBMCU_APB1_FZ2: All Peripherals Operate as in Normal Mode __var DbgMCU_APB2_Fz = 0x00072800; // DGBMCU_APB2_FZ: All Peripherals Operate as in Normal Mode __var TraceClk_Pin = 0x00040002; // PE2 __var TraceD0_Pin = 0x00040003; // PE3 __var TraceD1_Pin = 0x00040004; // PE4 __var TraceD2_Pin = 0x00040005; // PE5 __var TraceD3_Pin = 0x00040006; // PE6 __var DoOptionByteLoading = 0; // Disabled __var DbgMCU_CR = 0x00000007; // DBGMCU_CR: DBG_SLEEP, DBG_STOP, DBG_STANDBY __var DbgMCU_APB1_Fz1 = 0x82E0183F; // DGBMCU_APB1_FZ1: All Peripherals Operate as in Normal Mode __var DbgMCU_APB1_Fz2 = 0x00000022; // DGBMCU_APB1_FZ2: All Peripherals Operate as in Normal Mode __var DbgMCU_APB2_Fz = 0x00072800; // DGBMCU_APB2_FZ: All Peripherals Operate as in Normal Mode __var TraceClk_Pin = 0x00040002; // PE2 __var TraceD0_Pin = 0x00040003; // PE3 __var TraceD1_Pin = 0x00040004; // PE4 __var TraceD2_Pin = 0x00040005; // PE5 __var TraceD3_Pin = 0x00040006; // PE6 __var DoOptionByteLoading = 0; // Disabled __var DbgMCU_CR = 0x00000007; // DBGMCU_CR: DBG_SLEEP, DBG_STOP, DBG_STANDBY __var DbgMCU_APB1_Fz1 = 0x82E0183F; // DGBMCU_APB1_FZ1: All Peripherals Operate as in Normal Mode __var DbgMCU_APB1_Fz2 = 0x00000022; // DGBMCU_APB1_FZ2: All Peripherals Operate as in Normal Mode __var DbgMCU_APB2_Fz = 0x00072800; // DGBMCU_APB2_FZ: All Peripherals Operate as in Normal Mode __var TraceClk_Pin = 0x00040002; // PE2 __var TraceD0_Pin = 0x00040003; // PE3 __var TraceD1_Pin = 0x00040004; // PE4 __var TraceD2_Pin = 0x00040005; // PE5 __var TraceD3_Pin = 0x00040006; // PE6 __var DoOptionByteLoading = 0; // Disabled STMicroelectronics STM32L4 Series devices STMicroelectronics STM32L4 Device and CMSIS-CORE Configuration via STM32CubeMX #define RTE_DEVICE_CUBE_MX #define CMSIS_device_header "stm32l4xx.h"