Keil
STM32N6xx_DFP
STMicroelectronics STM32N6 Series Device Support
https://www.keil.com/pack/
https://github.com/Open-CMSIS-Pack/STM32N6xx_DFP.git
LICENSE
Active development ...
ST
Device Support
Device Family Package STMicroelectronics
STM32N6
STM32N6xx
High-performance STM32N6 MCUs with Arm Cortex-M55 core, MVE, MPU, cache, DSP, DP-FPU, 3616 DMIPS at 800MHz.
// Debug Access Variables, can be modified by user via copies of DBGCONF files as created by uVision. Also see sub-family level.
__var DbgMCU_CR = 0x80000007; // DBGMCU_CR: DBGMCU configuration register
// [31] HLT_TSGEN_EN, [28] DBTRGOEN, [21] TRACECLKEN, [20] DBGCKEN,
// [ 2] DBGSTBY, [ 1] DBGSTOP, [ 0] DBGSLEEP
__var DbgMCU_AHB1_Fzr = 0x00000000; // DBGMCU_AHB1FZR: DBGMCU AHB1 peripheral freeze register
__var DbgMCU_AHB5_Fzr = 0x00000000; // DBGMCU_AHB5FZR: DBGMCU AHB5 peripheral freeze register
__var DbgMCU_APB1L_Fzr = 0x00000000; // DBGMCU_APB1LFZR: DBGMCU APB1L peripheral freeze register
__var DbgMCU_APB1H_Fzr = 0x00000000; // DBGMCU_APB1HFZR: DBGMCU APB1H peripheral freeze register
__var DbgMCU_APB2_Fzr = 0x00000000; // DBGMCU_APB2FZR: DBGMCU APB2 peripheral freeze register
__var DbgMCU_APB4_Fzr = 0x00000000; // DBGMCU_APB4FZR: DBGMCU APB4 peripheral freeze register
__var DbgMCU_APB5_Fzr = 0x00000000; // DBGMCU_APB5FZR: DBGMCU APB5 peripheral freeze register
__var TraceClk_Pin = 0x00010003; // PB3
__var TraceD0_Pin = 0x00040003; // PE3
__var TraceD1_Pin = 0x00010000; // PB0
__var TraceD2_Pin = 0x00010006; // PB6
__var TraceD3_Pin = 0x00010007; // PB7
__var value = 0;
Sequence("CheckID");
__ap = 0; // Switch to System Debug Access Port
value = Read32(0x80001004); // Read DBGMCU_CR
value |= 0x00100000; // Enable debug clock: DBGMCU_CR[20] DBGCKEN
value |= 0x00200000; // DBGMCU_CR[21] TRACECLKEN
Write32(0x80001004 , DbgMCU_CR | value); // DBGMCU_CR: Configure MCU Debug
Write32(0x80001024 , DbgMCU_AHB1_Fzr ); // DBGMCU_AHB1FZR: Configure DBGMCU AHB1 peripheral freeze behavior
Write32(0x80001028 , DbgMCU_AHB5_Fzr ); // DBGMCU_AHB5FZR: Configure DBGMCU AHB5 peripheral freeze behavior
Write32(0x80001010 , DbgMCU_APB1L_Fzr ); // DBGMCU_APB1LFZR: Configure DBGMCU APB1L peripheral freeze behavior
Write32(0x80001014 , DbgMCU_APB1H_Fzr ); // DBGMCU_APB1HFZR: Configure DBGMCU APB1H peripheral freeze behavior
Write32(0x80001018 , DbgMCU_APB2_Fzr ); // DBGMCU_APB2FZR: Configure DBGMCU APB2 peripheral freeze behavior
Write32(0x8000101C , DbgMCU_APB4_Fzr ); // DBGMCU_APB4FZR: Configure DBGMCU APB4 peripheral freeze behavior
Write32(0x80001020 , DbgMCU_APB5_Fzr ); // DBGMCU_APB5FZR: Configure DBGMCU APB5 peripheral freeze behavior
__var traceSWO = (__traceout & 0x1) != 0; // SWO (asynchronous) Trace Selected?
__var traceTPIU = (__traceout & 0x2) != 0; // TPIU (synchronous) Trace Selected?
Sequence("EnableTraceSWO"); // Call SWO Trace Setup
Sequence("EnableTraceTPIU"); // Call TPIU Trace Setup
__var traceSWO = (__traceout & 0x1) != 0; // SWO enabled?
__var traceTPIU = (__traceout & 0x2) != 0; // Synchronous trace port enabled?
Sequence("DisableTraceSWO");
Sequence("DisableTraceTPIU");
__var pidr1 = 0;
__var pidr2 = 0;
__var jep106id = 0;
__var ROMTableBase = 0;
__ap = 0; // System debug access port (APB-AP)
ROMTableBase = ReadAP(0xF8) & ~0x3;
pidr1 = Read32(ROMTableBase + 0x0FE4);
pidr2 = Read32(ROMTableBase + 0x0FE8);
jep106id = ((pidr2 & 0x7) << 4 ) | ((pidr1 >> 4) & 0xF);
Query(0, "Not a genuine ST Device! Abort connection", 1);
Message(2, "Not a genuine ST Device! Abort connection.");
Sequence("ConfigureTraceSWOPin");
// Trace Clock is already enabled in "DebugDeviceUnlock"
__var value = 0;
__ap = 0; // Switch to System Debug Access Port
// Disable Trace Clock
value = Read32(0x80001004); // Read DBGMCU_CR
value &= ~0x00200000; // DBGMCU_CR[21] : clear TRACECLKEN
Write32(0x80001004, value); // Update DBGMCU_CR
__var value = 0;
Sequence("ConfigureTraceTPIUPins");
// Trace Clock is already enabled in "DebugDeviceUnlock"
Write32(0xE0081004, 0x00000007); // CSTF Priority Register (CSTF_PRIORITY): Increase ITM priority
// Configure CoreSight Trace Funnel (CSTF) at 0xE0081000
value = Read32(0xE0081000); // Read Trace Funnel CONTROL Register
value &= 0x00000F00; // Preserve Hold Time Settings
value |= 0x00000003; // Enable ITM and ETM slave ports
Write32(0xE0081000, value); // Update Trace Funnel CONTROL Register
// disable ETF and wait until disabled
Write32(0xE0082028, 0x00000002); // ETF Mode Register (ETF_MODE): Set to Hardware FIFO mode
Write32(0xE0082034, 0x00000000); // ETF Buffer Level Watermark Register (ETF_BUFWM): Set threshold vacancy to 0 (use full buffer)
Write32(0xE0082304, 0x00000003); // ETF Formatter and Flush Control Register (ETF_FFCR): Set ENFT and ENTI
Write32(0xE0082020, 0x00000001); // ETF ConTrol Register (ETF_CTL): Set TCEN
__var value = 0;
__ap = 0; // Switch to System Debug Access Port
// Disable Trace Clock
value = Read32(0x80001004); // Read DBGMCU_CR
value &= ~0x00200000; // DBGMCU_CR[21] : clear TRACECLKEN
Write32(0x80001004, value); // Update DBGMCU_CR
__var pin = 0;
__var port = 0;
__var portAdr = 0;
__var pos = 0;
__var SWO_Pin = 0x00010005; // PB5
pin = ((SWO_Pin ) & 0x0000FFFF);
port = ((SWO_Pin >> 16) & 0x0000FFFF);
portAdr = 0x56020000 + (((SWO_Pin >> 16) & 0x0000FFFF) * 0x400);
pos = pin * 2;
Write32(0x5602825C, ((Read32(0x5602825C ) ) | (1 << port)) ); // RCC_AHB4ENR: IO port clock enable
Write32(portAdr + 0x00, ((Read32(portAdr + 0x00) & ~( 3 << pos)) | (2 << pos )) ); // GPIOx_MODER: Set Mode (Alternate Function)
Write32(portAdr + 0x08, ((Read32(portAdr + 0x08) ) | (3 << pos )) ); // GPIOx_OSPEEDR: Set Speed (Very High Speed)
Write32(portAdr + 0x0C, ((Read32(portAdr + 0x0C) & ~( 3 << pos)) ) ); // GPIOx_PUPDR: Set I/O to no pull-up/pull-down
pos = ((pin ) & 7) * 4;
Write32(portAdr + 0x20, ((Read32(portAdr + 0x20) & ~(15 << pos)) ) ); // GPIOx_AFRL: Alternate Function to AF0
pos = ((pin - 8) & 7) * 4;
Write32(portAdr + 0x24, ((Read32(portAdr + 0x24) & ~(15 << pos)) ) ); // GPIOx_AFRH: Alternate Function to AF0
__var pin = 0;
__var port = 0;
__var portAdr = 0;
__var pos = 0;
__var width = (__traceout & 0x003F0000) >> 16;
pin = (TraceClk_Pin ) & 0x0000FFFF;
port = (TraceClk_Pin >> 16) & 0x0000FFFF;
portAdr = 0x56020000 + (((TraceClk_Pin >> 16) & 0x0000FFFF) * 0x400);
pos = pin * 2;
Write32(0x5602825C, ((Read32(0x5602825C ) ) | (1 << port)) ); // RCC_AHB4ENR: IO port clock enable
Write32(portAdr + 0x00, ((Read32(portAdr + 0x00) & ~( 3 << pos)) | (2 << pos )) ); // GPIOx_MODER: Set Mode (Alternate Function)
Write32(portAdr + 0x08, ((Read32(portAdr + 0x08) ) | (3 << pos )) ); // GPIOx_OSPEEDR: Set Speed (Very High Speed)
Write32(portAdr + 0x0C, ((Read32(portAdr + 0x0C) & ~( 3 << pos)) ) ); // GPIOx_PUPDR: Set I/O to no pull-up/pull-down
pos = ((pin ) & 7) * 4;
Write32(portAdr + 0x20, ((Read32(portAdr + 0x20) & ~(15 << pos)) ) ); // GPIOx_AFRL: Alternate Function to AF0
pos = ((pin - 8) & 7) * 4;
Write32(portAdr + 0x24, ((Read32(portAdr + 0x24) & ~(15 << pos)) ) ); // GPIOx_AFRH: Alternate Function to AF0
pin = (TraceD0_Pin ) & 0x0000FFFF;
port = (TraceD0_Pin >> 16) & 0x0000FFFF;
portAdr = 0x56020000 + (((TraceD0_Pin >> 16) & 0x0000FFFF) * 0x400);
pos = pin * 2;
Write32(0x5602825C, ((Read32(0x5602825C ) ) | (1 << port)) ); // RCC_AHB4ENR: IO port clock enable
Write32(portAdr + 0x00, ((Read32(portAdr + 0x00) & ~( 3 << pos)) | (2 << pos )) ); // GPIOx_MODER: Set Mode (Alternate Function)
Write32(portAdr + 0x08, ((Read32(portAdr + 0x08) ) | (3 << pos )) ); // GPIOx_OSPEEDR: Set Speed (Very High Speed)
Write32(portAdr + 0x0C, ((Read32(portAdr + 0x0C) & ~( 3 << pos)) ) ); // GPIOx_PUPDR: Set I/O to no pull-up/pull-down
pos = ((pin ) & 7) * 4;
Write32(portAdr + 0x20, ((Read32(portAdr + 0x20) & ~(15 << pos)) ) ); // GPIOx_AFRL: Alternate Function to AF0
pos = ((pin - 8) & 7) * 4;
Write32(portAdr + 0x24, ((Read32(portAdr + 0x24) & ~(15 << pos)) ) ); // GPIOx_AFRH: Alternate Function to AF0
pin = (TraceD1_Pin ) & 0x0000FFFF;
port = (TraceD1_Pin >> 16) & 0x0000FFFF;
portAdr = 0x56020000 + (((TraceD1_Pin >> 16) & 0x0000FFFF) * 0x400);
pos = pin * 2;
Write32(0x5602825C, ((Read32(0x5602825C ) ) | (1 << port)) ); // RCC_AHB4ENR: IO port clock enable
Write32(portAdr + 0x00, ((Read32(portAdr + 0x00) & ~( 3 << pos)) | (2 << pos )) ); // GPIOx_MODER: Set Mode (Alternate Function)
Write32(portAdr + 0x08, ((Read32(portAdr + 0x08) ) | (3 << pos )) ); // GPIOx_OSPEEDR: Set Speed (Very High Speed)
Write32(portAdr + 0x0C, ((Read32(portAdr + 0x0C) & ~( 3 << pos)) ) ); // GPIOx_PUPDR: Set I/O to no pull-up/pull-down
pos = ((pin ) & 7) * 4;
Write32(portAdr + 0x20, ((Read32(portAdr + 0x20) & ~(15 << pos)) ) ); // GPIOx_AFRL: Alternate Function to AF0
pos = ((pin - 8) & 7) * 4;
Write32(portAdr + 0x24, ((Read32(portAdr + 0x24) & ~(15 << pos)) ) ); // GPIOx_AFRH: Alternate Function to AF0
pin = (TraceD2_Pin ) & 0x0000FFFF;
port = (TraceD2_Pin >> 16) & 0x0000FFFF;
portAdr = 0x56020000 + (((TraceD2_Pin >> 16) & 0x0000FFFF) * 0x400);
pos = pin * 2;
Write32(0x5602825C, ((Read32(0x5602825C ) ) | (1 << port)) ); // RCC_AHB4ENR: IO port clock enable
Write32(portAdr + 0x00, ((Read32(portAdr + 0x00) & ~( 3 << pos)) | (2 << pos )) ); // GPIOx_MODER: Set Mode (Alternate Function)
Write32(portAdr + 0x08, ((Read32(portAdr + 0x08) ) | (3 << pos )) ); // GPIOx_OSPEEDR: Set Speed (Very High Speed)
Write32(portAdr + 0x0C, ((Read32(portAdr + 0x0C) & ~( 3 << pos)) ) ); // GPIOx_PUPDR: Set I/O to no pull-up/pull-down
pos = ((pin ) & 7) * 4;
Write32(portAdr + 0x20, ((Read32(portAdr + 0x20) & ~(15 << pos)) ) ); // GPIOx_AFRL: Alternate Function to AF0
pos = ((pin - 8) & 7) * 4;
Write32(portAdr + 0x24, ((Read32(portAdr + 0x24) & ~(15 << pos)) ) ); // GPIOx_AFRH: Alternate Function to AF0
pin = (TraceD3_Pin ) & 0x0000FFFF;
port = (TraceD3_Pin >> 16) & 0x0000FFFF;
portAdr = 0x56020000 + (((TraceD3_Pin >> 16) & 0x0000FFFF) * 0x400);
pos = pin * 2;
Write32(0x5602825C, ((Read32(0x5602825C ) ) | (1 << port)) ); // RCC_AHB4ENR: IO port clock enable
Write32(portAdr + 0x00, ((Read32(portAdr + 0x00) & ~( 3 << pos)) | (2 << pos )) ); // GPIOx_MODER: Set Mode (Alternate Function)
Write32(portAdr + 0x08, ((Read32(portAdr + 0x08) ) | (3 << pos )) ); // GPIOx_OSPEEDR: Set Speed (Very High Speed)
Write32(portAdr + 0x0C, ((Read32(portAdr + 0x0C) & ~( 3 << pos)) ) ); // GPIOx_PUPDR: Set I/O to no pull-up/pull-down
pos = ((pin ) & 7) * 4;
Write32(portAdr + 0x20, ((Read32(portAdr + 0x20) & ~(15 << pos)) ) ); // GPIOx_AFRL: Alternate Function to AF0
pos = ((pin - 8) & 7) * 4;
Write32(portAdr + 0x24, ((Read32(portAdr + 0x24) & ~(15 << pos)) ) ); // GPIOx_AFRH: Alternate Function to AF0
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