Keil STM32U5xx_DFP STMicroelectronics STM32U5 Series Device Support https://www.keil.com/pack/ https://github.com/Open-CMSIS-Pack/STM32U5xx_DFP.git LICENSES Active development... STM32CubeMX integration: - Corrected UCPD peripheral handling in FrameworkCubeMX_gpdsc.ftl Devices Support: - Updated STM32Cube_FW_U5 Firmware Package version to V1.3.0 (HAL v1.3.0) - Added STM32U5F9/G9, STM32U5F7/G7 device support - Updated SVD Files for all devices - Updated SRAM2 for the STM32U5 4MB devices - Renamed OSPI loader for the STM32U5 4MB - Updated GCC startup files (fixed improperly closed comments) - Updated GCC linker script files - Corrected linker script file header STM32CubeMX integration: - Added Component Subgroups DSI, GFXMMU, GFXTIM, GPU2D, JPEG, LTDC, XSPI - Updated GPDSC FTL file CMSIS-Driver: - I2C: -- Updated PowerControl function (added check if Instance is valid) -- Updated Control function implementation for transfer abort (added check for master mode) -- Minor cleanup (removed unused extern declarations from header file) - USB Device: -- Updated PowerControl function (removed unnecessary NVIC handling and added check if Instance is valid) - USB Host: -- Updated PowerControl function (removed unnecessary NVIC handling) Devices Support: - Updated STM32Cube_FW_U5 Firmware Package version to V1.2.0 (HAL v1.2.0) - Added STM32U595/A5, STM32U599/A9 device support - Added STM32U535/45 device support - Added C-Startup variant - Updated SVD files - Updated Flash programming algorithms - Updated STM32U5 Datasheets - Renamed DBGCONF file Pack Description: - Reworked conditions - Removed HAL dependency for component ::Device:Startup STM32CubeMX integration: - MX_Device.h: Generated definitions for GPIO Pins with assigned labels CMSIS-Driver: - Updated documentation - Added I2C driver - Added MCI driver - Added USB Host and USB Device drivers - SPI: -- Updated Receive function to properly support Default Tx Value transmission during reception (due to STM32 HAL changed functionality) -- Corrected Control function to support more than 8 data bits in DMA mode -- Corrected GetDataCount function in DMA mode - USART: -- Corrected GetStatus function and status flags handling -- Corrected Control function to support 9 data bits in DMA mode -- Corrected GetTxCount and GetRxCount functions in DMA mode -- Removed Rx Timeout capability and event signalization STM32CubeMX integration: - New workflow concept (incompatible with earlier STM32U5xx_DFPs) - Automatic migration of projects, with disabled TrustZone, that were created with earlier STM32U5xx_DFPs - Added STM32CubeMX integration for TrustZone enabled devices - STM32CubeMX can be started with a default configuration for selected board Updated Pack to STM32Cube_FW_U5 Firmware Package version V1.1.0 Updated reference manual, datasheets Corrected partition files Updated Pack to STM32Cube_FW_U5 Firmware Package version V1.0.2: - Add support for STM32U585I-IOT02A OSPI external Loader Devices Support: - Removed 'Q' devices - Updated SVD file Package Description (pdsc): - Updated schemaVersion (1.7.2) - Added RAMstart and RAMsize attributes to Flash Algorithm elements CMSIS Driver: - Added UART/USART CMSIS driver - Added SPI CMSIS driver Updated STM32Cube Firmware U5 library to version V1.0.0 - First official release of HAL and LL drivers for STM32U575xx/STM32U585xx devices ST Device Support Device Family Package STMicroelectronics STM32U5 STM32U5xx Ultra-low-power STM32U5 MCUs with Arm Cortex-M33 core, MPU, cache, DSP, FPU, 240 DMIPS at 160 MHz. __var DbgMCU_CR = 0x00000006; // DBGMCU_CR: DBG_STOP, DBG_STANDBY __var DbgMCU_APB1L_Fz = 0x0060183F; // DGBMCU_APB1L_FZ : Configure APB1L peripheral freeze behavior __var DbgMCU_APB1H_Fz = 0x000000E2; // DGBMCU_APB1H_FZ : Configure APB1H peripheral freeze behavior __var DbgMCU_APB2_Fz = 0x00072800; // DGBMCU_APB2_FZ : Configure APB2 peripheral freeze behavior __var DbgMCU_APB3_Fz = 0x000E0400; // DBGMCU_APB3_FZR : Configure AHB1 peripheral freeze behavior __var DbgMCU_AHB1_Fz = 0x0000FFFF; // DBGMCU_AHB1_FZR : Configure AHB1 peripheral freeze behavior __var DbgMCU_AHB3_Fz = 0x0000000F; // DBGMCU_AHB3_FZR : Configure AHB3 peripheral freeze behavior __var TraceClk_Pin = 0x00040002; // PE2 (Note: PA8 uses AF12) __var TraceD0_Pin = 0x00020009; // PC9 __var TraceD1_Pin = 0x0002000A; // PC10 __var TraceD2_Pin = 0x00040005; // PE5 __var TraceD3_Pin = 0x0002000C; // PC12 __var DoOptionByteLoading = 0; // Disabled __var traceSWO = (__traceout & 0x1) != 0; // SWO enabled? __var traceTPIU = (__traceout & 0x2) != 0; // Synchronous trace port enabled? Sequence("CheckID"); Sequence("ConfigureTraceSWOClock"); Sequence("ConfigureTraceTPIUClock"); // Replication of Standard Functionality Write32(0xE000EDF0, 0xA05F0001); // Enable Core Debug via DHCSR // Device Specific Debug Setup Write32(0xE0044004, DbgMCU_CR | (Read32(0xE0044004) & 0xF0)); // DBGMCU_CR: Configure MCU Debug Write32(0xE0044008, DbgMCU_APB1L_Fz); // DBGMCU_APB1_FZ: Configure APB1L Peripheral Freeze Behavior Write32(0xE004400C, DbgMCU_APB1H_Fz); // DBGMCU_APB1_FZ: Configure APB1H Peripheral Freeze Behavior Write32(0xE0044010, DbgMCU_APB2_Fz); // DBGMCU_APB1_FZ: Configure APB2 Peripheral Freeze Behavior Write32(0xE0044014, DbgMCU_APB3_Fz); // DBGMCU_APB3FZR: Configure APB3 Peripheral Freeze Behavior Write32(0xE0044020, DbgMCU_AHB1_Fz); // DBGMCU_AHB1FZR: Configure AHB1 Peripheral Freeze Behavior Write32(0xE0044028, DbgMCU_AHB3_Fz); // DBGMCU_AHB3FZR: Configure AHB3 Peripheral Freeze Behavior __var traceSWO = (__traceout & 0x1) != 0; // SWO (asynchronous) Trace Selected? __var traceTPIU = (__traceout & 0x2) != 0; // Synchronous trace port enabled? Sequence("EnableTraceSWO"); // Call SWO Trace Setup Sequence("EnableTraceTPIU"); // Call TPIU Trace Setup __var traceSWO = (__traceout & 0x1) != 0; // SWO enabled? __var traceTPIU = (__traceout & 0x2) != 0; // Synchronous trace port enabled? Sequence("DisableTraceSWO"); Sequence("DisableTraceTPIU"); __var pidr1 = 0; __var pidr2 = 0; __var jep106id = 0; __var ROMTableBase = 0; __ap = 0; // AHB-AP ROMTableBase = ReadAP(0xF8) & ~0x3; pidr1 = Read32(ROMTableBase + 0x0FE4); pidr2 = Read32(ROMTableBase + 0x0FE8); jep106id = ((pidr2 & 0x7) << 4 ) | ((pidr1 >> 4) & 0xF); Query(0, "Not a genuine ST Device! Abort connection", 1); Message(2, "Not a genuine ST Device! Abort connection."); Sequence("ConfigureTraceSWOPin"); Sequence("ConfigureTraceSWOClock"); __var dbgmcu_val = 0; // DBGMCU_CR Value dbgmcu_val = Read32(0xE0044004) & (~0xF0); // Read DBGMCU_CR and clear trace setup Write32(0xE0044004, dbgmcu_val); // Write DBGMCU_CR: Trace Settings Sequence("ConfigureTraceTPIUPins"); Sequence("ConfigureTraceTPIUClock"); __var dbgmcu_val = 0; // DBGMCU_CR Value dbgmcu_val = Read32(0xE0044004) & (~0xF0); // Read DBGMCU_CR and clear trace setup Write32(0xE0044004, dbgmcu_val); // Write DBGMCU_CR: Trace Settings __var dbgmcu_val = 0; // DBGMCU_CR Value __var dbgmcu_trace_val = 0; // DBGMCU_CR Value dbgmcu_val = Read32(0xE0044004) & (~0xF0); // Read DBGMCU_CR and clear trace setup dbgmcu_trace_val = (1 << 5) | (1 << 4); // Trace Port and Clock Enable + Trace I/O Enable + Trace Mode Asynchronous Write32(0xE0044004, dbgmcu_val | dbgmcu_trace_val); // Write DBGMCU_CR: Trace Settings __var width = (__traceout & 0x003F0000) >> 16; __var dbgmcu_val = 0; // DBGMCU_CR Value __var dbgmcu_trace_val = 0; // DBGMCU_CR Value dbgmcu_val = Read32(0xE0044004) & (~0xF0); // Read DBGMCU_CR and clear trace setup dbgmcu_trace_val = (3 << 5) | (1 << 4); dbgmcu_trace_val = (5 << 5) | (1 << 4); dbgmcu_trace_val = (7 << 5) | (1 << 4); Write32(0xE0044004, dbgmcu_val | dbgmcu_trace_val); // Write DBGMCU_CR: Trace Settings __var pin = 0; __var port = 0; __var portAdr = 0; __var pos = 0; __var secOffs = 0x00000000; __var SWO_Pin = 0x00010003; // PB3 secOffs = 0x10000000; pin = ((SWO_Pin ) & 0x0000FFFF); port = ((SWO_Pin >> 16) & 0x0000FFFF); portAdr = 0x42020000 + secOffs + (port * 0x400); pos = pin * 2; Write32(0x46020C8C + secOffs, ((Read32(0x46020C8C + secOffs) ) | (1 << port)) ); // RCC_AHB2ENR1: IO port clock enable Write32(portAdr + 0x00, ((Read32(portAdr + 0x00) & ~( 3 << pos)) | (2 << pos )) ); // GPIOx_MODER: Set Mode (Alternate Function) Write32(portAdr + 0x08, ((Read32(portAdr + 0x08) ) | (3 << pos )) ); // GPIOx_OSPEEDR: Set Speed (Very High Speed) Write32(portAdr + 0x0C, ((Read32(portAdr + 0x0C) & ~( 3 << pos)) ) ); // GPIOx_PUPDR: Set I/O to no pull-up/pull-down pos = ((pin ) & 7) * 4; Write32(portAdr + 0x20, ((Read32(portAdr + 0x20) & ~(15 << pos)) ) ); // GPIOx_AFRL: Alternate Function to AF0 pos = ((pin - 8) & 7) * 4; Write32(portAdr + 0x24, ((Read32(portAdr + 0x24) & ~(15 << pos)) ) ); // GPIOx_AFRH: Alternate Function to AF0 __var pin = 8; __var port = 0; __var portAdr = 0; __var pos = 0; __var secOffs = 0x00000000; __var width = (__traceout & 0x003F0000) >> 16; secOffs = 0x10000000; pin = (TraceClk_Pin ) & 0x0000FFFF; port = (TraceClk_Pin >> 16) & 0x0000FFFF; portAdr = 0x42020000 + secOffs + (port * 0x400); pos = pin * 2; Write32(0x46020C8C + secOffs, ((Read32(0x46020C8C + secOffs) ) | (1 << port)) ); // RCC_AHB2ENR1: IO port clock enable Write32(portAdr + 0x00, ((Read32(portAdr + 0x00) & ~( 3 << pos)) | (2 << pos )) ); // GPIOx_MODER: Set Mode (Alternate Function) Write32(portAdr + 0x08, ((Read32(portAdr + 0x08) ) | (3 << pos )) ); // GPIOx_OSPEEDR: Set Speed (Very High Speed) Write32(portAdr + 0x0C, ((Read32(portAdr + 0x0C) & ~( 3 << pos)) ) ); // GPIOx_PUPDR: Set I/O to no pull-up/pull-down pos = ((pin ) & 7) * 4; Write32(portAdr + 0x20, ((Read32(portAdr + 0x20) & ~(15 << pos)) ) ); // GPIOx_AFRL: Alternate Function to AF0 pos = ((pin - 8) & 7) * 4; Write32(portAdr + 0x24, ((Read32(portAdr + 0x24) & ~(15 << pos)) ) ); // GPIOx_AFRH: Alternate Function to AF0 pos = ((pin ) & 7) * 4; Write32(portAdr + 0x24, ((Read32(portAdr + 0x24) | (12 << pos)) ) ); // GPIOx_AFRH: Alternate Function to AF12 pin = (TraceD0_Pin ) & 0x0000FFFF; port = (TraceD0_Pin >> 16) & 0x0000FFFF; portAdr = 0x42020000 + secOffs + (port * 0x400); pos = pin * 2; Write32(0x46020C8C + secOffs, ((Read32(0x46020C8C + secOffs) ) | (1 << port)) ); // RCC_AHB2ENR1: IO port clock enable Write32(portAdr + 0x00, ((Read32(portAdr + 0x00) & ~( 3 << pos)) | (2 << pos )) ); // GPIOx_MODER: Set Mode (Alternate Function) Write32(portAdr + 0x08, ((Read32(portAdr + 0x08) ) | (3 << pos )) ); // GPIOx_OSPEEDR: Set Speed (Very High Speed) Write32(portAdr + 0x0C, ((Read32(portAdr + 0x0C) & ~( 3 << pos)) ) ); // GPIOx_PUPDR: Set I/O to no pull-up/pull-down pos = ((pin ) & 7) * 4; Write32(portAdr + 0x20, ((Read32(portAdr + 0x20) & ~(15 << pos)) ) ); // GPIOx_AFRL: Alternate Function to AF0 pos = ((pin - 8) & 7) * 4; Write32(portAdr + 0x24, ((Read32(portAdr + 0x24) & ~(15 << pos)) ) ); // GPIOx_AFRH: Alternate Function to AF0 pin = (TraceD1_Pin ) & 0x0000FFFF; port = (TraceD1_Pin >> 16) & 0x0000FFFF; portAdr = 0x42020000 + secOffs + (port * 0x400); pos = pin * 2; Write32(0x46020C8C + secOffs, ((Read32(0x46020C8C + secOffs) ) | (1 << port)) ); // RCC_AHB2ENR1: IO port clock enable Write32(portAdr + 0x00, ((Read32(portAdr + 0x00) & ~( 3 << pos)) | (2 << pos )) ); // GPIOx_MODER: Set Mode (Alternate Function) Write32(portAdr + 0x08, ((Read32(portAdr + 0x08) ) | (3 << pos )) ); // GPIOx_OSPEEDR: Set Speed (Very High Speed) Write32(portAdr + 0x0C, ((Read32(portAdr + 0x0C) & ~( 3 << pos)) ) ); // GPIOx_PUPDR: Set I/O to no pull-up/pull-down pos = ((pin ) & 7) * 4; Write32(portAdr + 0x20, ((Read32(portAdr + 0x20) & ~(15 << pos)) ) ); // GPIOx_AFRL: Alternate Function to AF0 pos = ((pin - 8) & 7) * 4; Write32(portAdr + 0x24, ((Read32(portAdr + 0x24) & ~(15 << pos)) ) ); // GPIOx_AFRH: Alternate Function to AF0 pin = (TraceD2_Pin ) & 0x0000FFFF; port = (TraceD2_Pin >> 16) & 0x0000FFFF; portAdr = 0x42020000 + secOffs + (port * 0x400); pos = pin * 2; Write32(0x46020C8C + secOffs, ((Read32(0x46020C8C + secOffs) ) | (1 << port)) ); // RCC_AHB2ENR1: IO port clock enable Write32(portAdr + 0x00, ((Read32(portAdr + 0x00) & ~( 3 << pos)) | (2 << pos )) ); // GPIOx_MODER: Set Mode (Alternate Function) Write32(portAdr + 0x08, ((Read32(portAdr + 0x08) ) | (3 << pos )) ); // GPIOx_OSPEEDR: Set Speed (Very High Speed) Write32(portAdr + 0x0C, ((Read32(portAdr + 0x0C) & ~( 3 << pos)) ) ); // GPIOx_PUPDR: Set I/O to no pull-up/pull-down pos = ((pin ) & 7) * 4; Write32(portAdr + 0x20, ((Read32(portAdr + 0x20) & ~(15 << pos)) ) ); // GPIOx_AFRL: Alternate Function to AF0 pos = ((pin - 8) & 7) * 4; Write32(portAdr + 0x24, ((Read32(portAdr + 0x24) & ~(15 << pos)) ) ); // GPIOx_AFRH: Alternate Function to AF0 pin = (TraceD3_Pin ) & 0x0000FFFF; port = (TraceD3_Pin >> 16) & 0x0000FFFF; portAdr = 0x42020000 + secOffs + (port * 0x400); pos = pin * 2; Write32(0x46020C8C + secOffs, ((Read32(0x46020C8C + secOffs) ) | (1 << port)) ); // RCC_AHB2ENR1: IO port clock enable Write32(portAdr + 0x00, ((Read32(portAdr + 0x00) & ~( 3 << pos)) | (2 << pos )) ); // GPIOx_MODER: Set Mode (Alternate Function) Write32(portAdr + 0x08, ((Read32(portAdr + 0x08) ) | (3 << pos )) ); // GPIOx_OSPEEDR: Set Speed (Very High Speed) Write32(portAdr + 0x0C, ((Read32(portAdr + 0x0C) & ~( 3 << pos)) ) ); // GPIOx_PUPDR: Set I/O to no pull-up/pull-down pos = ((pin ) & 7) * 4; Write32(portAdr + 0x20, ((Read32(portAdr + 0x20) & ~(15 << pos)) ) ); // GPIOx_AFRL: Alternate Function to AF0 pos = ((pin - 8) & 7) * 4; Write32(portAdr + 0x24, ((Read32(portAdr + 0x24) & ~(15 << pos)) ) ); // GPIOx_AFRH: Alternate Function to AF0 __var connectionFlash = ( __connection & 0xF ) == 2 ; __var FLASH_BASE = 0x40022000 ; __var FLASH_CR = FLASH_BASE + 0x28 ; __var OBL_LAUNCH_BIT = ( 1 << 27 ) ; __var LOCK_BIT = ( 1 << 31 ) ; __var OPTLOCK_BIT = ( 1 << 30 ) ; __var FLASH_KEYR = FLASH_BASE + 0x08 ; __var FLASH_KEY1 = 0x45670123 ; __var FLASH_KEY2 = 0xCDEF89AB ; __var FLASH_OPTKEYR = FLASH_BASE + 0x10 ; __var FLASH_OPTKEY1 = 0x08192A3B ; __var FLASH_OPTKEY2 = 0x4C5D6E7F ; __var FLASH_CR_Value = 0 ; __var DoDebugPortStop = 1 ; __var DP_CTRL_STAT = 0x4 ; __var DP_SELECT = 0x8 ; // unlock the FLASH_CR Write32( FLASH_KEYR, FLASH_KEY1 ) ; Write32( FLASH_KEYR, FLASH_KEY2 ) ; // unlock the option byte block Write32( FLASH_OPTKEYR, FLASH_OPTKEY1 ) ; Write32( FLASH_OPTKEYR, FLASH_OPTKEY2 ) ; FLASH_CR_Value = Read32( FLASH_CR ) ; DoDebugPortStop = 0 ; __errorcontrol = 1 ; // write OBL_LAUNCH bit (causes a reset) Write32( FLASH_CR, FLASH_CR_Value | ( OBL_LAUNCH_BIT ) ) ; __errorcontrol = 0 ; // Switch to DP Register Bank 0 WriteDP(DP_SELECT, 0x00000000); // Power Down Debug port WriteDP(DP_CTRL_STAT, 0x00000000); STMicroelectronics STM32U5 Devices STMicroelectronics STM32U5 Device and CMSIS-CORE Configuration via STM32CubeMX #define RTE_DEVICE_CUBE_MX #define CMSIS_device_header "stm32u5xx.h"