// Generated by PeakRDL-cheader - A free and open-source header generator // https://github.com/SystemRDL/PeakRDL-cheader #ifndef MSK_TOP_REGS_H #define MSK_TOP_REGS_H #ifdef __cplusplus extern "C" { #endif #include #include // Reg - msk_top_regs::msk_hash_lo #define MSK_TOP_REGS__MSK_HASH_LO__HASH_ID_LO_bm 0xffffffff #define MSK_TOP_REGS__MSK_HASH_LO__HASH_ID_LO_bp 0 #define MSK_TOP_REGS__MSK_HASH_LO__HASH_ID_LO_bw 32 #define MSK_TOP_REGS__MSK_HASH_LO__HASH_ID_LO_reset 0xaaaa5555 // Reg - msk_top_regs::msk_hash_hi #define MSK_TOP_REGS__MSK_HASH_HI__HASH_ID_HI_bm 0xffffffff #define MSK_TOP_REGS__MSK_HASH_HI__HASH_ID_HI_bp 0 #define MSK_TOP_REGS__MSK_HASH_HI__HASH_ID_HI_bw 32 #define MSK_TOP_REGS__MSK_HASH_HI__HASH_ID_HI_reset 0x5555aaaa // Reg - msk_top_regs::msk_init #define MSK_TOP_REGS__MSK_INIT__TXRXINIT_bm 0x1 #define MSK_TOP_REGS__MSK_INIT__TXRXINIT_bp 0 #define MSK_TOP_REGS__MSK_INIT__TXRXINIT_bw 1 #define MSK_TOP_REGS__MSK_INIT__TXRXINIT_reset 0x1 #define MSK_TOP_REGS__MSK_INIT__TXINIT_bm 0x2 #define MSK_TOP_REGS__MSK_INIT__TXINIT_bp 1 #define MSK_TOP_REGS__MSK_INIT__TXINIT_bw 1 #define MSK_TOP_REGS__MSK_INIT__TXINIT_reset 0x1 #define MSK_TOP_REGS__MSK_INIT__RXINIT_bm 0x4 #define MSK_TOP_REGS__MSK_INIT__RXINIT_bp 2 #define MSK_TOP_REGS__MSK_INIT__RXINIT_bw 1 #define MSK_TOP_REGS__MSK_INIT__RXINIT_reset 0x1 // Reg - msk_top_regs::msk_ctrl #define MSK_TOP_REGS__MSK_CTRL__PTT_bm 0x1 #define MSK_TOP_REGS__MSK_CTRL__PTT_bp 0 #define MSK_TOP_REGS__MSK_CTRL__PTT_bw 1 #define MSK_TOP_REGS__MSK_CTRL__PTT_reset 0x0 #define MSK_TOP_REGS__MSK_CTRL__LOOPBACK_ENA_bm 0x2 #define MSK_TOP_REGS__MSK_CTRL__LOOPBACK_ENA_bp 1 #define MSK_TOP_REGS__MSK_CTRL__LOOPBACK_ENA_bw 1 #define MSK_TOP_REGS__MSK_CTRL__LOOPBACK_ENA_reset 0x0 #define MSK_TOP_REGS__MSK_CTRL__RX_INVERT_bm 0x4 #define MSK_TOP_REGS__MSK_CTRL__RX_INVERT_bp 2 #define MSK_TOP_REGS__MSK_CTRL__RX_INVERT_bw 1 #define MSK_TOP_REGS__MSK_CTRL__RX_INVERT_reset 0x0 #define MSK_TOP_REGS__MSK_CTRL__CLEAR_COUNTS_bm 0x8 #define MSK_TOP_REGS__MSK_CTRL__CLEAR_COUNTS_bp 3 #define MSK_TOP_REGS__MSK_CTRL__CLEAR_COUNTS_bw 1 #define MSK_TOP_REGS__MSK_CTRL__CLEAR_COUNTS_reset 0x0 #define MSK_TOP_REGS__MSK_CTRL__DIFF_ENCODER_LOOPBACK_bm 0x10 #define MSK_TOP_REGS__MSK_CTRL__DIFF_ENCODER_LOOPBACK_bp 4 #define MSK_TOP_REGS__MSK_CTRL__DIFF_ENCODER_LOOPBACK_bw 1 #define MSK_TOP_REGS__MSK_CTRL__DIFF_ENCODER_LOOPBACK_reset 0x0 #define MSK_TOP_REGS__MSK_CTRL__RESERVED_bm 0xe0 #define MSK_TOP_REGS__MSK_CTRL__RESERVED_bp 5 #define MSK_TOP_REGS__MSK_CTRL__RESERVED_bw 3 #define MSK_TOP_REGS__MSK_CTRL__RESERVED_reset 0x0 #define MSK_TOP_REGS__MSK_CTRL__TX_SHIFT_bm 0x700 #define MSK_TOP_REGS__MSK_CTRL__TX_SHIFT_bp 8 #define MSK_TOP_REGS__MSK_CTRL__TX_SHIFT_bw 3 #define MSK_TOP_REGS__MSK_CTRL__TX_SHIFT_reset 0x0 // Reg - msk_top_regs::msk_stat_0 #define MSK_TOP_REGS__MSK_STAT_0__DEMOD_SYNC_LOCK_bm 0x1 #define MSK_TOP_REGS__MSK_STAT_0__DEMOD_SYNC_LOCK_bp 0 #define MSK_TOP_REGS__MSK_STAT_0__DEMOD_SYNC_LOCK_bw 1 #define MSK_TOP_REGS__MSK_STAT_0__DEMOD_SYNC_LOCK_reset 0x0 #define MSK_TOP_REGS__MSK_STAT_0__TX_ENABLE_bm 0x2 #define MSK_TOP_REGS__MSK_STAT_0__TX_ENABLE_bp 1 #define MSK_TOP_REGS__MSK_STAT_0__TX_ENABLE_bw 1 #define MSK_TOP_REGS__MSK_STAT_0__TX_ENABLE_reset 0x0 #define MSK_TOP_REGS__MSK_STAT_0__RX_ENABLE_bm 0x4 #define MSK_TOP_REGS__MSK_STAT_0__RX_ENABLE_bp 2 #define MSK_TOP_REGS__MSK_STAT_0__RX_ENABLE_bw 1 #define MSK_TOP_REGS__MSK_STAT_0__RX_ENABLE_reset 0x0 #define MSK_TOP_REGS__MSK_STAT_0__TX_AXIS_VALID_bm 0x8 #define MSK_TOP_REGS__MSK_STAT_0__TX_AXIS_VALID_bp 3 #define MSK_TOP_REGS__MSK_STAT_0__TX_AXIS_VALID_bw 1 #define MSK_TOP_REGS__MSK_STAT_0__TX_AXIS_VALID_reset 0x0 // Reg - msk_top_regs::msk_stat_1 #define MSK_TOP_REGS__MSK_STAT_1__DATA_bm 0xffffffff #define MSK_TOP_REGS__MSK_STAT_1__DATA_bp 0 #define MSK_TOP_REGS__MSK_STAT_1__DATA_bw 32 #define MSK_TOP_REGS__MSK_STAT_1__DATA_reset 0x0 // Reg - msk_top_regs::msk_stat_2 #define MSK_TOP_REGS__MSK_STAT_2__DATA_bm 0xffffffff #define MSK_TOP_REGS__MSK_STAT_2__DATA_bp 0 #define MSK_TOP_REGS__MSK_STAT_2__DATA_bw 32 #define MSK_TOP_REGS__MSK_STAT_2__DATA_reset 0x0 // Reg - msk_top_regs::config_nco_fw_desc_c4924cc6_name_0c494469 #define MSK_TOP_REGS__CONFIG_NCO_FW_DESC_C4924CC6_NAME_0C494469__CONFIG_DATA_bm 0xffffffff #define MSK_TOP_REGS__CONFIG_NCO_FW_DESC_C4924CC6_NAME_0C494469__CONFIG_DATA_bp 0 #define MSK_TOP_REGS__CONFIG_NCO_FW_DESC_C4924CC6_NAME_0C494469__CONFIG_DATA_bw 32 #define MSK_TOP_REGS__CONFIG_NCO_FW_DESC_C4924CC6_NAME_0C494469__CONFIG_DATA_reset 0x0 // Reg - msk_top_regs::config_nco_fw_desc_94d7aaf5_name_84dd0c1c #define MSK_TOP_REGS__CONFIG_NCO_FW_DESC_94D7AAF5_NAME_84DD0C1C__CONFIG_DATA_bm 0xffffffff #define MSK_TOP_REGS__CONFIG_NCO_FW_DESC_94D7AAF5_NAME_84DD0C1C__CONFIG_DATA_bp 0 #define MSK_TOP_REGS__CONFIG_NCO_FW_DESC_94D7AAF5_NAME_84DD0C1C__CONFIG_DATA_bw 32 #define MSK_TOP_REGS__CONFIG_NCO_FW_DESC_94D7AAF5_NAME_84DD0C1C__CONFIG_DATA_reset 0x0 // Reg - msk_top_regs::config_nco_fw_desc_42134a4f_name_d97dbd51 #define MSK_TOP_REGS__CONFIG_NCO_FW_DESC_42134A4F_NAME_D97DBD51__CONFIG_DATA_bm 0xffffffff #define MSK_TOP_REGS__CONFIG_NCO_FW_DESC_42134A4F_NAME_D97DBD51__CONFIG_DATA_bp 0 #define MSK_TOP_REGS__CONFIG_NCO_FW_DESC_42134A4F_NAME_D97DBD51__CONFIG_DATA_bw 32 #define MSK_TOP_REGS__CONFIG_NCO_FW_DESC_42134A4F_NAME_D97DBD51__CONFIG_DATA_reset 0x0 // Reg - msk_top_regs::config_nco_fw_desc_16fb48c8_name_8d01a20d #define MSK_TOP_REGS__CONFIG_NCO_FW_DESC_16FB48C8_NAME_8D01A20D__CONFIG_DATA_bm 0xffffffff #define MSK_TOP_REGS__CONFIG_NCO_FW_DESC_16FB48C8_NAME_8D01A20D__CONFIG_DATA_bp 0 #define MSK_TOP_REGS__CONFIG_NCO_FW_DESC_16FB48C8_NAME_8D01A20D__CONFIG_DATA_bw 32 #define MSK_TOP_REGS__CONFIG_NCO_FW_DESC_16FB48C8_NAME_8D01A20D__CONFIG_DATA_reset 0x0 // Reg - msk_top_regs::config_nco_fw_desc_43c0828f_name_bdc60ecf #define MSK_TOP_REGS__CONFIG_NCO_FW_DESC_43C0828F_NAME_BDC60ECF__CONFIG_DATA_bm 0xffffffff #define MSK_TOP_REGS__CONFIG_NCO_FW_DESC_43C0828F_NAME_BDC60ECF__CONFIG_DATA_bp 0 #define MSK_TOP_REGS__CONFIG_NCO_FW_DESC_43C0828F_NAME_BDC60ECF__CONFIG_DATA_bw 32 #define MSK_TOP_REGS__CONFIG_NCO_FW_DESC_43C0828F_NAME_BDC60ECF__CONFIG_DATA_reset 0x0 // Reg - msk_top_regs::lpf_config_0 #define MSK_TOP_REGS__LPF_CONFIG_0__LPF_FREEZE_bm 0x1 #define MSK_TOP_REGS__LPF_CONFIG_0__LPF_FREEZE_bp 0 #define MSK_TOP_REGS__LPF_CONFIG_0__LPF_FREEZE_bw 1 #define MSK_TOP_REGS__LPF_CONFIG_0__LPF_FREEZE_reset 0x0 #define MSK_TOP_REGS__LPF_CONFIG_0__LPF_ZERO_bm 0x2 #define MSK_TOP_REGS__LPF_CONFIG_0__LPF_ZERO_bp 1 #define MSK_TOP_REGS__LPF_CONFIG_0__LPF_ZERO_bw 1 #define MSK_TOP_REGS__LPF_CONFIG_0__LPF_ZERO_reset 0x0 #define MSK_TOP_REGS__LPF_CONFIG_0__PRBS_RESERVED_bm 0xfc #define MSK_TOP_REGS__LPF_CONFIG_0__PRBS_RESERVED_bp 2 #define MSK_TOP_REGS__LPF_CONFIG_0__PRBS_RESERVED_bw 6 #define MSK_TOP_REGS__LPF_CONFIG_0__PRBS_RESERVED_reset 0x0 #define MSK_TOP_REGS__LPF_CONFIG_0__LPF_ALPHA_bm 0xffffff00 #define MSK_TOP_REGS__LPF_CONFIG_0__LPF_ALPHA_bp 8 #define MSK_TOP_REGS__LPF_CONFIG_0__LPF_ALPHA_bw 24 #define MSK_TOP_REGS__LPF_CONFIG_0__LPF_ALPHA_reset 0x0 // Reg - msk_top_regs::lpf_config_1 #define MSK_TOP_REGS__LPF_CONFIG_1__I_GAIN_bm 0xffffff #define MSK_TOP_REGS__LPF_CONFIG_1__I_GAIN_bp 0 #define MSK_TOP_REGS__LPF_CONFIG_1__I_GAIN_bw 24 #define MSK_TOP_REGS__LPF_CONFIG_1__I_GAIN_reset 0x0 #define MSK_TOP_REGS__LPF_CONFIG_1__I_SHIFT_bm 0xff000000 #define MSK_TOP_REGS__LPF_CONFIG_1__I_SHIFT_bp 24 #define MSK_TOP_REGS__LPF_CONFIG_1__I_SHIFT_bw 8 #define MSK_TOP_REGS__LPF_CONFIG_1__I_SHIFT_reset 0x0 // Reg - msk_top_regs::data_width_desc_58c848dd_name_2fbd8eba #define MSK_TOP_REGS__DATA_WIDTH_DESC_58C848DD_NAME_2FBD8EBA__DATA_WIDTH_bm 0xff #define MSK_TOP_REGS__DATA_WIDTH_DESC_58C848DD_NAME_2FBD8EBA__DATA_WIDTH_bp 0 #define MSK_TOP_REGS__DATA_WIDTH_DESC_58C848DD_NAME_2FBD8EBA__DATA_WIDTH_bw 8 #define MSK_TOP_REGS__DATA_WIDTH_DESC_58C848DD_NAME_2FBD8EBA__DATA_WIDTH_reset 0x8 // Reg - msk_top_regs::data_width_desc_6097df38_name_4609588b #define MSK_TOP_REGS__DATA_WIDTH_DESC_6097DF38_NAME_4609588B__DATA_WIDTH_bm 0xff #define MSK_TOP_REGS__DATA_WIDTH_DESC_6097DF38_NAME_4609588B__DATA_WIDTH_bp 0 #define MSK_TOP_REGS__DATA_WIDTH_DESC_6097DF38_NAME_4609588B__DATA_WIDTH_bw 8 #define MSK_TOP_REGS__DATA_WIDTH_DESC_6097DF38_NAME_4609588B__DATA_WIDTH_reset 0x8 // Reg - msk_top_regs::prbs_ctrl #define MSK_TOP_REGS__PRBS_CTRL__PRBS_SEL_bm 0x1 #define MSK_TOP_REGS__PRBS_CTRL__PRBS_SEL_bp 0 #define MSK_TOP_REGS__PRBS_CTRL__PRBS_SEL_bw 1 #define MSK_TOP_REGS__PRBS_CTRL__PRBS_SEL_reset 0x0 #define MSK_TOP_REGS__PRBS_CTRL__PRBS_ERROR_INSERT_bm 0x2 #define MSK_TOP_REGS__PRBS_CTRL__PRBS_ERROR_INSERT_bp 1 #define MSK_TOP_REGS__PRBS_CTRL__PRBS_ERROR_INSERT_bw 1 #define MSK_TOP_REGS__PRBS_CTRL__PRBS_ERROR_INSERT_reset 0x0 #define MSK_TOP_REGS__PRBS_CTRL__PRBS_CLEAR_bm 0x4 #define MSK_TOP_REGS__PRBS_CTRL__PRBS_CLEAR_bp 2 #define MSK_TOP_REGS__PRBS_CTRL__PRBS_CLEAR_bw 1 #define MSK_TOP_REGS__PRBS_CTRL__PRBS_CLEAR_reset 0x0 #define MSK_TOP_REGS__PRBS_CTRL__PRBS_MANUAL_SYNC_bm 0x8 #define MSK_TOP_REGS__PRBS_CTRL__PRBS_MANUAL_SYNC_bp 3 #define MSK_TOP_REGS__PRBS_CTRL__PRBS_MANUAL_SYNC_bw 1 #define MSK_TOP_REGS__PRBS_CTRL__PRBS_MANUAL_SYNC_reset 0x0 #define MSK_TOP_REGS__PRBS_CTRL__PRBS_RESERVED_bm 0xfff0 #define MSK_TOP_REGS__PRBS_CTRL__PRBS_RESERVED_bp 4 #define MSK_TOP_REGS__PRBS_CTRL__PRBS_RESERVED_bw 12 #define MSK_TOP_REGS__PRBS_CTRL__PRBS_RESERVED_reset 0x0 #define MSK_TOP_REGS__PRBS_CTRL__PRBS_SYNC_THRESHOLD_bm 0xffff0000 #define MSK_TOP_REGS__PRBS_CTRL__PRBS_SYNC_THRESHOLD_bp 16 #define MSK_TOP_REGS__PRBS_CTRL__PRBS_SYNC_THRESHOLD_bw 16 #define MSK_TOP_REGS__PRBS_CTRL__PRBS_SYNC_THRESHOLD_reset 0x0 // Reg - msk_top_regs::config_prbs_seed #define MSK_TOP_REGS__CONFIG_PRBS_SEED__CONFIG_DATA_bm 0xffffffff #define MSK_TOP_REGS__CONFIG_PRBS_SEED__CONFIG_DATA_bp 0 #define MSK_TOP_REGS__CONFIG_PRBS_SEED__CONFIG_DATA_bw 32 #define MSK_TOP_REGS__CONFIG_PRBS_SEED__CONFIG_DATA_reset 0x0 // Reg - msk_top_regs::config_prbs_poly #define MSK_TOP_REGS__CONFIG_PRBS_POLY__CONFIG_DATA_bm 0xffffffff #define MSK_TOP_REGS__CONFIG_PRBS_POLY__CONFIG_DATA_bp 0 #define MSK_TOP_REGS__CONFIG_PRBS_POLY__CONFIG_DATA_bw 32 #define MSK_TOP_REGS__CONFIG_PRBS_POLY__CONFIG_DATA_reset 0x0 // Reg - msk_top_regs::config_prbs_errmask #define MSK_TOP_REGS__CONFIG_PRBS_ERRMASK__CONFIG_DATA_bm 0xffffffff #define MSK_TOP_REGS__CONFIG_PRBS_ERRMASK__CONFIG_DATA_bp 0 #define MSK_TOP_REGS__CONFIG_PRBS_ERRMASK__CONFIG_DATA_bw 32 #define MSK_TOP_REGS__CONFIG_PRBS_ERRMASK__CONFIG_DATA_reset 0x0 // Reg - msk_top_regs::stat_32_bits #define MSK_TOP_REGS__STAT_32_BITS__DATA_bm 0xffffffff #define MSK_TOP_REGS__STAT_32_BITS__DATA_bp 0 #define MSK_TOP_REGS__STAT_32_BITS__DATA_bw 32 #define MSK_TOP_REGS__STAT_32_BITS__DATA_reset 0x0 // Reg - msk_top_regs::stat_32_errs #define MSK_TOP_REGS__STAT_32_ERRS__DATA_bm 0xffffffff #define MSK_TOP_REGS__STAT_32_ERRS__DATA_bp 0 #define MSK_TOP_REGS__STAT_32_ERRS__DATA_bw 32 #define MSK_TOP_REGS__STAT_32_ERRS__DATA_reset 0x0 // Reg - msk_top_regs::stat_32_lpf_acc_desc_8cebc7dc_name_f20c6670 #define MSK_TOP_REGS__STAT_32_LPF_ACC_DESC_8CEBC7DC_NAME_F20C6670__DATA_bm 0xffffffff #define MSK_TOP_REGS__STAT_32_LPF_ACC_DESC_8CEBC7DC_NAME_F20C6670__DATA_bp 0 #define MSK_TOP_REGS__STAT_32_LPF_ACC_DESC_8CEBC7DC_NAME_F20C6670__DATA_bw 32 #define MSK_TOP_REGS__STAT_32_LPF_ACC_DESC_8CEBC7DC_NAME_F20C6670__DATA_reset 0x0 // Reg - msk_top_regs::stat_32_lpf_acc_desc_dea6bd99_name_758fd0ce #define MSK_TOP_REGS__STAT_32_LPF_ACC_DESC_DEA6BD99_NAME_758FD0CE__DATA_bm 0xffffffff #define MSK_TOP_REGS__STAT_32_LPF_ACC_DESC_DEA6BD99_NAME_758FD0CE__DATA_bp 0 #define MSK_TOP_REGS__STAT_32_LPF_ACC_DESC_DEA6BD99_NAME_758FD0CE__DATA_bw 32 #define MSK_TOP_REGS__STAT_32_LPF_ACC_DESC_DEA6BD99_NAME_758FD0CE__DATA_reset 0x0 // Reg - msk_top_regs::msk_stat_3 #define MSK_TOP_REGS__MSK_STAT_3__DATA_bm 0xffffffff #define MSK_TOP_REGS__MSK_STAT_3__DATA_bp 0 #define MSK_TOP_REGS__MSK_STAT_3__DATA_bw 32 #define MSK_TOP_REGS__MSK_STAT_3__DATA_reset 0x0 // Reg - msk_top_regs::rx_sample_discard #define MSK_TOP_REGS__RX_SAMPLE_DISCARD__RX_SAMPLE_DISCARD_bm 0xff #define MSK_TOP_REGS__RX_SAMPLE_DISCARD__RX_SAMPLE_DISCARD_bp 0 #define MSK_TOP_REGS__RX_SAMPLE_DISCARD__RX_SAMPLE_DISCARD_bw 8 #define MSK_TOP_REGS__RX_SAMPLE_DISCARD__RX_SAMPLE_DISCARD_reset 0x0 #define MSK_TOP_REGS__RX_SAMPLE_DISCARD__RX_NCO_DISCARD_bm 0xff00 #define MSK_TOP_REGS__RX_SAMPLE_DISCARD__RX_NCO_DISCARD_bp 8 #define MSK_TOP_REGS__RX_SAMPLE_DISCARD__RX_NCO_DISCARD_bw 8 #define MSK_TOP_REGS__RX_SAMPLE_DISCARD__RX_NCO_DISCARD_reset 0x0 // Reg - msk_top_regs::lpf_config_2 #define MSK_TOP_REGS__LPF_CONFIG_2__P_GAIN_bm 0xffffff #define MSK_TOP_REGS__LPF_CONFIG_2__P_GAIN_bp 0 #define MSK_TOP_REGS__LPF_CONFIG_2__P_GAIN_bw 24 #define MSK_TOP_REGS__LPF_CONFIG_2__P_GAIN_reset 0x0 #define MSK_TOP_REGS__LPF_CONFIG_2__P_SHIFT_bm 0xff000000 #define MSK_TOP_REGS__LPF_CONFIG_2__P_SHIFT_bp 24 #define MSK_TOP_REGS__LPF_CONFIG_2__P_SHIFT_bw 8 #define MSK_TOP_REGS__LPF_CONFIG_2__P_SHIFT_reset 0x0 // Reg - msk_top_regs::status_reg_data_f53978c8_name_d8ad3b25 #define MSK_TOP_REGS__STATUS_REG_DATA_F53978C8_NAME_D8AD3B25__DATA_bm 0xffffffff #define MSK_TOP_REGS__STATUS_REG_DATA_F53978C8_NAME_D8AD3B25__DATA_bp 0 #define MSK_TOP_REGS__STATUS_REG_DATA_F53978C8_NAME_D8AD3B25__DATA_bw 32 #define MSK_TOP_REGS__STATUS_REG_DATA_F53978C8_NAME_D8AD3B25__DATA_reset 0x0 // Reg - msk_top_regs::status_reg_data_05243a4e_name_2c154788 #define MSK_TOP_REGS__STATUS_REG_DATA_05243A4E_NAME_2C154788__DATA_bm 0xffffffff #define MSK_TOP_REGS__STATUS_REG_DATA_05243A4E_NAME_2C154788__DATA_bp 0 #define MSK_TOP_REGS__STATUS_REG_DATA_05243A4E_NAME_2C154788__DATA_bw 32 #define MSK_TOP_REGS__STATUS_REG_DATA_05243A4E_NAME_2C154788__DATA_reset 0x0 // Reg - msk_top_regs::status_reg_data_10a2e5b5_name_3b640507 #define MSK_TOP_REGS__STATUS_REG_DATA_10A2E5B5_NAME_3B640507__DATA_bm 0xffffffff #define MSK_TOP_REGS__STATUS_REG_DATA_10A2E5B5_NAME_3B640507__DATA_bp 0 #define MSK_TOP_REGS__STATUS_REG_DATA_10A2E5B5_NAME_3B640507__DATA_bw 32 #define MSK_TOP_REGS__STATUS_REG_DATA_10A2E5B5_NAME_3B640507__DATA_reset 0x0 // Reg - msk_top_regs::status_reg_data_642692cf_name_3de9a0d3 #define MSK_TOP_REGS__STATUS_REG_DATA_642692CF_NAME_3DE9A0D3__DATA_bm 0xffffffff #define MSK_TOP_REGS__STATUS_REG_DATA_642692CF_NAME_3DE9A0D3__DATA_bp 0 #define MSK_TOP_REGS__STATUS_REG_DATA_642692CF_NAME_3DE9A0D3__DATA_bw 32 #define MSK_TOP_REGS__STATUS_REG_DATA_642692CF_NAME_3DE9A0D3__DATA_reset 0x0 // Reg - msk_top_regs::tx_sync_ctrl #define MSK_TOP_REGS__TX_SYNC_CTRL__TX_SYNC_ENA_bm 0x1 #define MSK_TOP_REGS__TX_SYNC_CTRL__TX_SYNC_ENA_bp 0 #define MSK_TOP_REGS__TX_SYNC_CTRL__TX_SYNC_ENA_bw 1 #define MSK_TOP_REGS__TX_SYNC_CTRL__TX_SYNC_ENA_reset 0x0 #define MSK_TOP_REGS__TX_SYNC_CTRL__TX_SYNC_FORCE_bm 0x2 #define MSK_TOP_REGS__TX_SYNC_CTRL__TX_SYNC_FORCE_bp 1 #define MSK_TOP_REGS__TX_SYNC_CTRL__TX_SYNC_FORCE_bw 1 #define MSK_TOP_REGS__TX_SYNC_CTRL__TX_SYNC_FORCE_reset 0x0 // Reg - msk_top_regs::tx_sync_cnt #define MSK_TOP_REGS__TX_SYNC_CNT__TX_SYNC_CNT_bm 0xffffff #define MSK_TOP_REGS__TX_SYNC_CNT__TX_SYNC_CNT_bp 0 #define MSK_TOP_REGS__TX_SYNC_CNT__TX_SYNC_CNT_bw 24 #define MSK_TOP_REGS__TX_SYNC_CNT__TX_SYNC_CNT_reset 0x0 // Reg - msk_top_regs::tx_sync_pat #define MSK_TOP_REGS__TX_SYNC_PAT__TX_SYNC_PAT_bm 0xffff #define MSK_TOP_REGS__TX_SYNC_PAT__TX_SYNC_PAT_bp 0 #define MSK_TOP_REGS__TX_SYNC_PAT__TX_SYNC_PAT_bw 16 #define MSK_TOP_REGS__TX_SYNC_PAT__TX_SYNC_PAT_reset 0x1b33 // Reg - msk_top_regs::lowpass_ema_alpha #define MSK_TOP_REGS__LOWPASS_EMA_ALPHA__ALPHA_bm 0x3ffff #define MSK_TOP_REGS__LOWPASS_EMA_ALPHA__ALPHA_bp 0 #define MSK_TOP_REGS__LOWPASS_EMA_ALPHA__ALPHA_bw 18 #define MSK_TOP_REGS__LOWPASS_EMA_ALPHA__ALPHA_reset 0x0 // Reg - msk_top_regs::rx_power #define MSK_TOP_REGS__RX_POWER__DATA_bm 0x7fffff #define MSK_TOP_REGS__RX_POWER__DATA_bp 0 #define MSK_TOP_REGS__RX_POWER__DATA_bw 23 #define MSK_TOP_REGS__RX_POWER__DATA_reset 0x0 // Reg - msk_top_regs::status_reg_data_8a67e1fe_desc_aa4ec676_name_aa4ec676 #define MSK_TOP_REGS__STATUS_REG_DATA_8A67E1FE_DESC_AA4EC676_NAME_AA4EC676__DATA_bm 0xffffffff #define MSK_TOP_REGS__STATUS_REG_DATA_8A67E1FE_DESC_AA4EC676_NAME_AA4EC676__DATA_bp 0 #define MSK_TOP_REGS__STATUS_REG_DATA_8A67E1FE_DESC_AA4EC676_NAME_AA4EC676__DATA_bw 32 #define MSK_TOP_REGS__STATUS_REG_DATA_8A67E1FE_DESC_AA4EC676_NAME_AA4EC676__DATA_reset 0x0 // Reg - msk_top_regs::status_reg_data_8a67e1fe_desc_8a90eed1_name_8a90eed1 #define MSK_TOP_REGS__STATUS_REG_DATA_8A67E1FE_DESC_8A90EED1_NAME_8A90EED1__DATA_bm 0xffffffff #define MSK_TOP_REGS__STATUS_REG_DATA_8A67E1FE_DESC_8A90EED1_NAME_8A90EED1__DATA_bp 0 #define MSK_TOP_REGS__STATUS_REG_DATA_8A67E1FE_DESC_8A90EED1_NAME_8A90EED1__DATA_bw 32 #define MSK_TOP_REGS__STATUS_REG_DATA_8A67E1FE_DESC_8A90EED1_NAME_8A90EED1__DATA_reset 0x0 // Reg - msk_top_regs::frame_sync_status #define MSK_TOP_REGS__FRAME_SYNC_STATUS__FRAME_SYNC_LOCKED_bm 0x1 #define MSK_TOP_REGS__FRAME_SYNC_STATUS__FRAME_SYNC_LOCKED_bp 0 #define MSK_TOP_REGS__FRAME_SYNC_STATUS__FRAME_SYNC_LOCKED_bw 1 #define MSK_TOP_REGS__FRAME_SYNC_STATUS__FRAME_SYNC_LOCKED_reset 0x0 #define MSK_TOP_REGS__FRAME_SYNC_STATUS__FRAME_BUFFER_OVERFLOW_bm 0x2 #define MSK_TOP_REGS__FRAME_SYNC_STATUS__FRAME_BUFFER_OVERFLOW_bp 1 #define MSK_TOP_REGS__FRAME_SYNC_STATUS__FRAME_BUFFER_OVERFLOW_bw 1 #define MSK_TOP_REGS__FRAME_SYNC_STATUS__FRAME_BUFFER_OVERFLOW_reset 0x0 #define MSK_TOP_REGS__FRAME_SYNC_STATUS__FRAMES_RECEIVED_bm 0x3fffffc #define MSK_TOP_REGS__FRAME_SYNC_STATUS__FRAMES_RECEIVED_bp 2 #define MSK_TOP_REGS__FRAME_SYNC_STATUS__FRAMES_RECEIVED_bw 24 #define MSK_TOP_REGS__FRAME_SYNC_STATUS__FRAMES_RECEIVED_reset 0x0 #define MSK_TOP_REGS__FRAME_SYNC_STATUS__FRAME_SYNC_ERRORS_bm 0xfc000000 #define MSK_TOP_REGS__FRAME_SYNC_STATUS__FRAME_SYNC_ERRORS_bp 26 #define MSK_TOP_REGS__FRAME_SYNC_STATUS__FRAME_SYNC_ERRORS_bw 6 #define MSK_TOP_REGS__FRAME_SYNC_STATUS__FRAME_SYNC_ERRORS_reset 0x0 // Reg - msk_top_regs::symbol_lock_control #define MSK_TOP_REGS__SYMBOL_LOCK_CONTROL__SYMBOL_LOCK_COUNT_bm 0x3ff #define MSK_TOP_REGS__SYMBOL_LOCK_CONTROL__SYMBOL_LOCK_COUNT_bp 0 #define MSK_TOP_REGS__SYMBOL_LOCK_CONTROL__SYMBOL_LOCK_COUNT_bw 10 #define MSK_TOP_REGS__SYMBOL_LOCK_CONTROL__SYMBOL_LOCK_COUNT_reset 0x80 #define MSK_TOP_REGS__SYMBOL_LOCK_CONTROL__SYMBOL_LOCK_THRESHOLD_bm 0x3fffc00 #define MSK_TOP_REGS__SYMBOL_LOCK_CONTROL__SYMBOL_LOCK_THRESHOLD_bp 10 #define MSK_TOP_REGS__SYMBOL_LOCK_CONTROL__SYMBOL_LOCK_THRESHOLD_bw 16 #define MSK_TOP_REGS__SYMBOL_LOCK_CONTROL__SYMBOL_LOCK_THRESHOLD_reset 0x2710 // Reg - msk_top_regs::symbol_lock_status #define MSK_TOP_REGS__SYMBOL_LOCK_STATUS__F1F2_bm 0x1 #define MSK_TOP_REGS__SYMBOL_LOCK_STATUS__F1F2_bp 0 #define MSK_TOP_REGS__SYMBOL_LOCK_STATUS__F1F2_bw 1 #define MSK_TOP_REGS__SYMBOL_LOCK_STATUS__F1F2_reset 0x0 #define MSK_TOP_REGS__SYMBOL_LOCK_STATUS__F1_bm 0x2 #define MSK_TOP_REGS__SYMBOL_LOCK_STATUS__F1_bp 1 #define MSK_TOP_REGS__SYMBOL_LOCK_STATUS__F1_bw 1 #define MSK_TOP_REGS__SYMBOL_LOCK_STATUS__F1_reset 0x0 #define MSK_TOP_REGS__SYMBOL_LOCK_STATUS__F2_bm 0x4 #define MSK_TOP_REGS__SYMBOL_LOCK_STATUS__F2_bp 2 #define MSK_TOP_REGS__SYMBOL_LOCK_STATUS__F2_bw 1 #define MSK_TOP_REGS__SYMBOL_LOCK_STATUS__F2_reset 0x0 #define MSK_TOP_REGS__SYMBOL_LOCK_STATUS__UNLOCK_F1_bm 0x8 #define MSK_TOP_REGS__SYMBOL_LOCK_STATUS__UNLOCK_F1_bp 3 #define MSK_TOP_REGS__SYMBOL_LOCK_STATUS__UNLOCK_F1_bw 1 #define MSK_TOP_REGS__SYMBOL_LOCK_STATUS__UNLOCK_F1_reset 0x0 #define MSK_TOP_REGS__SYMBOL_LOCK_STATUS__UNLOCK_F2_bm 0x10 #define MSK_TOP_REGS__SYMBOL_LOCK_STATUS__UNLOCK_F2_bp 4 #define MSK_TOP_REGS__SYMBOL_LOCK_STATUS__UNLOCK_F2_bw 1 #define MSK_TOP_REGS__SYMBOL_LOCK_STATUS__UNLOCK_F2_reset 0x0 // Reg - msk_top_regs::symbol_lock_time #define MSK_TOP_REGS__SYMBOL_LOCK_TIME__F1_bm 0xffff #define MSK_TOP_REGS__SYMBOL_LOCK_TIME__F1_bp 0 #define MSK_TOP_REGS__SYMBOL_LOCK_TIME__F1_bw 16 #define MSK_TOP_REGS__SYMBOL_LOCK_TIME__F1_reset 0x0 #define MSK_TOP_REGS__SYMBOL_LOCK_TIME__F2_bm 0xffff0000 #define MSK_TOP_REGS__SYMBOL_LOCK_TIME__F2_bp 16 #define MSK_TOP_REGS__SYMBOL_LOCK_TIME__F2_bw 16 #define MSK_TOP_REGS__SYMBOL_LOCK_TIME__F2_reset 0x0 // Addrmap - msk_top_regs typedef struct __attribute__ ((__packed__)) { uint32_t Hash_ID_Low; uint32_t Hash_ID_High; uint32_t MSK_Init; uint32_t MSK_Control; uint32_t MSK_Status; uint32_t Tx_Bit_Count; uint32_t Tx_Enable_Count; uint32_t Fb_FreqWord; uint32_t TX_F1_FreqWord; uint32_t TX_F2_FreqWord; uint32_t RX_F1_FreqWord; uint32_t RX_F2_FreqWord; uint32_t LPF_Config_0; uint32_t LPF_Config_1; uint32_t Tx_Data_Width; uint32_t Rx_Data_Width; uint32_t PRBS_Control; uint32_t PRBS_Initial_State; uint32_t PRBS_Polynomial; uint32_t PRBS_Error_Mask; uint32_t PRBS_Bit_Count; uint32_t PRBS_Error_Count; uint32_t LPF_Accum_F1; uint32_t LPF_Accum_F2; uint32_t axis_xfer_count; uint32_t Rx_Sample_Discard; uint32_t LPF_Config_2; uint32_t f1_nco_adjust; uint32_t f2_nco_adjust; uint32_t f1_error; uint32_t f2_error; uint32_t Tx_Sync_Ctrl; uint32_t Tx_Sync_Cnt; uint32_t Tx_Sync_Pat; uint32_t lowpass_ema_alpha1; uint32_t lowpass_ema_alpha2; uint32_t rx_power; uint32_t tx_async_fifo_rd_wr_ptr; uint32_t rx_async_fifo_rd_wr_ptr; uint32_t rx_frame_sync_status; uint32_t symbol_lock_control; uint32_t symbol_lock_status; uint32_t symbol_lock_time; } msk_top_regs_t; static_assert(sizeof(msk_top_regs_t) == 0xac, "Packing error"); #ifdef __cplusplus } #endif #endif /* MSK_TOP_REGS_H */