SF32LB52x 1.0 SF32LB52x CM33 r0p1 little true true 3 false 8 32 0x20 0x0 0xFFFFFFFF HPSYS_RCC HPSYS_RCC 0x50000000 0x0 0x1000 registers RSTR1 RSTR1 Reset Register 1 0x00 0x20 read-write 0x0 PTC1 0 - no reset; 1 - reset 31 1 RSVD 29 2 I2C2 0 - no reset; 1 - reset 28 1 I2C1 0 - no reset; 1 - reset 27 1 RSVD2 26 1 PDM1 0 - no reset; 1 - reset 25 1 RSVD3 23 2 EXTDMA 0 - no reset; 1 - reset 22 1 SPI2 0 - no reset; 1 - reset 21 1 SPI1 0 - no reset; 1 - reset 20 1 RSVD4 19 1 BTIM2 0 - no reset; 1 - reset 18 1 BTIM1 0 - no reset; 1 - reset 17 1 GPTIM2 0 - no reset; 1 - reset 16 1 GPTIM1 0 - no reset; 1 - reset 15 1 TRNG 0 - no reset; 1 - reset 14 1 CRC1 0 - no reset; 1 - reset 13 1 AES 0 - no reset; 1 - reset 12 1 EFUSEC 0 - no reset; 1 - reset 11 1 SYSCFG1 0 - no reset; 1 - reset 10 1 RSVD5 9 1 I2S1 0 - no reset; 1 - reset 8 1 LCDC1 0 - no reset; 1 - reset 7 1 EPIC 0 - no reset; 1 - reset 6 1 EZIP1 0 - no reset; 1 - reset 5 1 USART2 0 - no reset; 1 - reset 4 1 USART1 0 - no reset; 1 - reset 3 1 PINMUX1 0 - no reset; 1 - reset 2 1 MAILBOX1 0 - no reset; 1 - reset 1 1 DMAC1 0 - no reset; 1 - reset 0 1 RSTR2 RSTR2 Reset Register 2 0x04 0x20 read-write 0x0 RSVD 26 6 I2C4 0 - no reset; 1 - reset 25 1 RSVD2 24 1 TSEN 0 - no reset; 1 - reset 23 1 GPADC 0 - no reset; 1 - reset 22 1 RSVD3 21 1 AUDPRC 0 - no reset; 1 - reset 20 1 AUDCODEC 0 - no reset; 1 - reset 19 1 RSVD4 13 6 USART3 0 - no reset; 1 - reset 12 1 RSVD5 10 2 ATIM1 0 - no reset; 1 - reset 9 1 I2C3 0 - no reset; 1 - reset 8 1 RSVD6 7 1 USBC 0 - no reset; 1 - reset 6 1 RSVD7 5 1 SDMMC1 0 - no reset; 1 - reset 4 1 RSVD8 3 1 MPI2 0 - no reset; 1 - reset 2 1 MPI1 0 - no reset; 1 - reset 1 1 GPIO1 0 - no reset; 1 - reset 0 1 ENR1 ENR1 Enable Register 1 0x08 0x20 read-write 0x0 PTC1 write 1 to set module enable, write 0 to disable module 31 1 RSVD 29 2 I2C2 write 1 to set module enable, write 0 to disable module 28 1 I2C1 write 1 to set module enable, write 0 to disable module 27 1 RSVD2 26 1 PDM1 write 1 to set module enable, write 0 to disable module 25 1 RSVD3 24 1 SECU1 write 1 to set module enable, write 0 to disable module 23 1 EXTDMA write 1 to set module enable, write 0 to disable module 22 1 SPI2 write 1 to set module enable, write 0 to disable module 21 1 SPI1 write 1 to set module enable, write 0 to disable module 20 1 RSVD4 19 1 BTIM2 write 1 to set module enable, write 0 to disable module 18 1 BTIM1 write 1 to set module enable, write 0 to disable module 17 1 GPTIM2 write 1 to set module enable, write 0 to disable module 16 1 GPTIM1 write 1 to set module enable, write 0 to disable module 15 1 TRNG write 1 to set module enable, write 0 to disable module 14 1 CRC1 write 1 to set module enable, write 0 to disable module 13 1 AES write 1 to set module enable, write 0 to disable module 12 1 EFUSEC write 1 to set module enable, write 0 to disable module 11 1 SYSCFG1 write 1 to set module enable, write 0 to disable module 10 1 RSVD5 9 1 I2S1 write 1 to set module enable, write 0 to disable module 8 1 LCDC1 write 1 to set module enable, write 0 to disable module 7 1 EPIC write 1 to set module enable, write 0 to disable module 6 1 EZIP1 write 1 to set module enable, write 0 to disable module 5 1 USART2 write 1 to set module enable, write 0 to disable module 4 1 RSVD6 3 1 PINMUX1 write 1 to set module enable, write 0 to disable module 2 1 MAILBOX1 write 1 to set module enable, write 0 to disable module 1 1 DMAC1 write 1 to set module enable, write 0 to disable module 0 1 ENR2 ENR2 Enable Register 2 0x0c 0x20 read-write 0x0 RSVD 26 6 I2C4 write 1 to set module enable, write 0 to disable module 25 1 RSVD2 24 1 TSEN write 1 to set module enable, write 0 to disable module 23 1 GPADC write 1 to set module enable, write 0 to disable module 22 1 RSVD3 21 1 AUDPRC write 1 to set module enable, write 0 to disable module 20 1 AUDCODEC write 1 to set module enable, write 0 to disable module 19 1 RSVD4 13 6 USART3 write 1 to set module enable, write 0 to disable module 12 1 RSVD5 10 2 ATIM1 write 1 to set module enable, write 0 to disable module 9 1 I2C3 write 1 to set module enable, write 0 to disable module 8 1 RSVD6 7 1 USBC write 1 to set module enable, write 0 to disable module 6 1 RSVD7 5 1 SDMMC1 write 1 to set module enable, write 0 to disable module 4 1 RSVD8 3 1 MPI2 write 1 to set module enable, write 0 to disable module 2 1 MPI1 write 1 to set module enable, write 0 to disable module 1 1 GPIO1 write 1 to set module enable, write 0 to disable module 0 1 ESR1 ESR1 Enable Set Register 1 0x10 0x20 read-write 0x0 PTC1 write 1 to set module enable, write 0 has no effect 31 1 RSVD 29 2 I2C2 write 1 to set module enable, write 0 has no effect 28 1 I2C1 write 1 to set module enable, write 0 has no effect 27 1 RSVD2 26 1 PDM1 write 1 to set module enable, write 0 has no effect 25 1 RSVD3 24 1 SECU1 write 1 to set module enable, write 0 has no effect 23 1 EXTDMA write 1 to set module enable, write 0 has no effect 22 1 SPI2 write 1 to set module enable, write 0 has no effect 21 1 SPI1 write 1 to set module enable, write 0 has no effect 20 1 RSVD4 19 1 BTIM2 write 1 to set module enable, write 0 has no effect 18 1 BTIM1 write 1 to set module enable, write 0 has no effect 17 1 GPTIM2 write 1 to set module enable, write 0 has no effect 16 1 GPTIM1 write 1 to set module enable, write 0 has no effect 15 1 TRNG write 1 to set module enable, write 0 has no effect 14 1 CRC1 write 1 to set module enable, write 0 has no effect 13 1 AES write 1 to set module enable, write 0 has no effect 12 1 EFUSEC write 1 to set module enable, write 0 has no effect 11 1 SYSCFG1 write 1 to set module enable, write 0 has no effect 10 1 RSVD5 9 1 I2S1 write 1 to set module enable, write 0 has no effect 8 1 LCDC1 write 1 to set module enable, write 0 has no effect 7 1 EPIC write 1 to set module enable, write 0 has no effect 6 1 EZIP1 write 1 to set module enable, write 0 has no effect 5 1 USART2 write 1 to set module enable, write 0 has no effect 4 1 RSVD6 3 1 PINMUX1 write 1 to set module enable, write 0 has no effect 2 1 MAILBOX1 write 1 to set module enable, write 0 has no effect 1 1 DMAC1 write 1 to set module enable, write 0 has no effect 0 1 ESR2 ESR2 Enable Set Register 2 0x14 0x20 read-write 0x0 RSVD 26 6 I2C4 write 1 to set module enable, write 0 has no effect 25 1 RSVD2 24 1 TSEN write 1 to set module enable, write 0 has no effect 23 1 GPADC write 1 to set module enable, write 0 has no effect 22 1 RSVD3 21 1 AUDPRC write 1 to set module enable, write 0 has no effect 20 1 AUDCODEC write 1 to set module enable, write 0 has no effect 19 1 RSVD4 13 6 USART3 write 1 to set module enable, write 0 has no effect 12 1 RSVD5 10 2 ATIM1 write 1 to set module enable, write 0 has no effect 9 1 I2C3 write 1 to set module enable, write 0 has no effect 8 1 RSVD6 7 1 USBC write 1 to set module enable, write 0 has no effect 6 1 RSVD7 5 1 SDMMC1 write 1 to set module enable, write 0 has no effect 4 1 RSVD8 3 1 MPI2 write 1 to set module enable, write 0 has no effect 2 1 MPI1 write 1 to set module enable, write 0 has no effect 1 1 GPIO1 write 1 to set module enable, write 0 has no effect 0 1 ECR1 ECR1 Enable Clear Register 1 0x18 0x20 read-write 0x0 PTC1 write 1 to clear module enable, write 0 has no effect 31 1 RSVD 29 2 I2C2 write 1 to clear module enable, write 0 has no effect 28 1 I2C1 write 1 to clear module enable, write 0 has no effect 27 1 RSVD2 26 1 PDM1 write 1 to clear module enable, write 0 has no effect 25 1 RSVD3 24 1 SECU1 write 1 to clear module enable, write 0 has no effect 23 1 EXTDMA write 1 to clear module enable, write 0 has no effect 22 1 SPI2 write 1 to clear module enable, write 0 has no effect 21 1 SPI1 write 1 to clear module enable, write 0 has no effect 20 1 RSVD4 19 1 BTIM2 write 1 to clear module enable, write 0 has no effect 18 1 BTIM1 write 1 to clear module enable, write 0 has no effect 17 1 GPTIM2 write 1 to clear module enable, write 0 has no effect 16 1 GPTIM1 write 1 to clear module enable, write 0 has no effect 15 1 TRNG write 1 to clear module enable, write 0 has no effect 14 1 CRC1 write 1 to clear module enable, write 0 has no effect 13 1 AES write 1 to clear module enable, write 0 has no effect 12 1 EFUSEC write 1 to clear module enable, write 0 has no effect 11 1 SYSCFG1 write 1 to clear module enable, write 0 has no effect 10 1 RSVD5 9 1 I2S1 write 1 to clear module enable, write 0 has no effect 8 1 LCDC1 write 1 to clear module enable, write 0 has no effect 7 1 EPIC write 1 to clear module enable, write 0 has no effect 6 1 EZIP1 write 1 to clear module enable, write 0 has no effect 5 1 USART2 write 1 to clear module enable, write 0 has no effect 4 1 RSVD6 3 1 PINMUX1 write 1 to clear module enable, write 0 has no effect 2 1 MAILBOX1 write 1 to clear module enable, write 0 has no effect 1 1 DMAC1 write 1 to clear module enable, write 0 has no effect 0 1 ECR2 ECR2 Enable Clear Register 2 0x1c 0x20 read-write 0x0 RSVD 26 6 I2C4 write 1 to clear module enable, write 0 has no effect 25 1 RSVD2 24 1 TSEN write 1 to clear module enable, write 0 has no effect 23 1 GPADC write 1 to clear module enable, write 0 has no effect 22 1 RSVD3 21 1 AUDPRC write 1 to clear module enable, write 0 has no effect 20 1 AUDCODEC write 1 to clear module enable, write 0 has no effect 19 1 RSVD4 13 6 USART3 write 1 to clear module enable, write 0 has no effect 12 1 RSVD5 10 2 ATIM1 write 1 to clear module enable, write 0 has no effect 9 1 I2C3 write 1 to clear module enable, write 0 has no effect 8 1 RSVD6 7 1 USBC write 1 to clear module enable, write 0 has no effect 6 1 RSVD7 5 1 SDMMC1 write 1 to clear module enable, write 0 has no effect 4 1 RSVD8 3 1 MPI2 write 1 to clear module enable, write 0 has no effect 2 1 MPI1 write 1 to clear module enable, write 0 has no effect 1 1 GPIO1 write 1 to clear module enable, write 0 has no effect 0 1 CSR CSR Clock Select Register 0x20 0x20 read-write 0x0 RSVD 16 16 SEL_USBC select USB source clock 0 - clk_hpsys; 1 - clk_dll2 15 1 SEL_TICK select clock source for systick reference 0 - clk_rtc; 1 - reserved; 2 - clk_hrc48; 3 - clk_hxt48 13 2 SEL_PERI select clk_peri_hpsys source used by USART/SPI/I2C/GPTIM2/BTIM2 0 - clk_hrc48; 1 - clk_hxt48 12 1 RSVD2 10 2 RSVD3 8 2 SEL_MPI2 selet MPI2 function clock 0 - clk_peri_hpsys; 1 - clk_dll1; 2 - clk_dll2; 3 - reserved 6 2 SEL_MPI1 selet MPI1 function clock 0 - clk_peri_hpsys; 1 - clk_dll1; 2 - clk_dll2; 3 - reserved 4 2 RSVD4 3 1 SEL_SYS_LP select clk_hpsys source 0 - selected by SEL_SYS; 1 - clk_wdt 2 1 SEL_SYS select clk_hpsys source 0 - clk_hrc48; 1 - clk_hxt48; 2 - reserved; 3 - clk_dll1 0 2 CFGR CFGR Clock Configuration Register 0x24 0x20 read-write 0x0 RSVD 22 10 TICKDIV systick reference clock is systick reference clock source (selected by SEL_TICK) devided by TICKDIV 16 6 RSVD2 15 1 PDIV2 pclk2_hpsys = hclk_hpsys / (2^PDIV2), by default divided by 16 12 3 RSVD3 11 1 PDIV1 pclk_hpsys = hclk_hpsys / (2^PDIV1), by default divided by 2 8 3 HDIV hclk_hpsys = clk_hpsys / HDIV if HDIV=0, hclk_hpsys = clk_hpsys 0 8 USBCR USBCR USBC Control Register 0x28 0x20 read-write 0x0 RSVD 3 29 DIV USB function clock is USB source clock divided by DIV. After divider, USB function clock must be 60MHz. For example, if USBC clock source is 240MHz clk_dll2, DIV should be 4. 0 3 DLL1CR DLL1CR DLL1 Control Register 0x2c 0x20 read-write 0x0 READY 0: dll not ready 1: dll ready 31 1 LOCK_DLY 28 3 PU_DLY 25 3 DTEST_TR 21 4 DTEST_EN 20 1 BYPASS 19 1 VST_SEL 18 1 PRCHG_EXT 17 1 PRCHG_EN 16 1 MCU_PRCHG 15 1 MCU_PRCHG_EN 14 1 OUT_DIV2_EN 0: dll output not divided 1: dll output divided by 2 13 1 IN_DIV2_EN 12 1 LDO_VREF 8 4 MODE48M_EN 7 1 XTALIN_EN 6 1 STG DLL lock freqency is decided by STG. DLL output frequency is (STG+1)*24MHz e.g. STG=9,DLL output is 240M 2 4 SW 1 1 EN 0: dll disabled 1: dll enabled 0 1 DLL2CR DLL2CR DLL2 Control Register 0x30 0x20 read-write 0x0 READY 0: dll not ready 1: dll ready 31 1 LOCK_DLY 28 3 PU_DLY 25 3 DTEST_TR 21 4 DTEST_EN 20 1 BYPASS 19 1 VST_SEL 18 1 PRCHG_EXT 17 1 PRCHG_EN 16 1 MCU_PRCHG 15 1 MCU_PRCHG_EN 14 1 OUT_DIV2_EN 0: dll output not divided 1: dll output divided by 2 13 1 IN_DIV2_EN 12 1 LDO_VREF 8 4 MODE48M_EN 7 1 XTALIN_EN 6 1 STG DLL lock freqency is decided by STG. DLL output frequency is (STG+1)*24MHz e.g. STG=9,DLL output is 240M 2 4 SW 1 1 EN 0: dll disabled 1: dll enabled 0 1 HRCCAL1 HRCCAL1 HRC Calibration Register 1 0x34 0x20 read-write 0x0 CAL_DONE Calibration done. After a new calibration started, results should be processed only when cal_done asserted. 31 1 CAL_EN Calibration enble. Set to 0 to clear result, then set to 1 to start a new calibration 30 1 RSVD 16 14 CAL_LENGTH Target clk_hxt48 cycles during calibration 0 16 HRCCAL2 HRCCAL2 HRC Calibration Register 2 0x38 0x20 read-write 0x0 HXT_CNT Total clk_hxt48 cycles during calibration 16 16 HRC_CNT Total clk_hrc48 cycles during calibration 0 16 DBGCLKR DBGCLKR Debug Clock Register 0x3c 0x20 read-write 0x0 RSVD 20 12 DLL2_OUT_STR for debug only 18 2 DLL2_CG_EN for debug only 17 1 DLL2_OUT_RSTB for debug only 16 1 DLL2_LOOP_EN for debug only 15 1 DLL2_OUT_EN for debug only 14 1 DLL2_LDO_EN for debug only 13 1 DLL2_DBG for debug only 12 1 DLL1_OUT_STR for debug only 10 2 DLL1_CG_EN for debug only 9 1 DLL1_OUT_RSTB for debug only 8 1 DLL1_LOOP_EN for debug only 7 1 DLL1_OUT_EN for debug only 6 1 DLL1_LDO_EN for debug only 5 1 DLL1_DBG for debug only 4 1 RSVD2 3 1 CLK_EN for debug only 2 1 CLK_SEL for debug only 0 2 DBGR DBGR Debug Register 0x40 0x20 read-write 0x0 RSVD 5 27 FORCE_HP for debug only 4 1 FORCE_GPIO for debug only 3 1 FORCE_BUS for debug only 2 1 SYSCLK_SWLP for debug only 1 1 SYSCLK_AON for debug only 0 1 DWCFGR DWCFGR Deep WFI mode Clock Configuration Register 0x44 0x20 read-write 0x0 RSVD 28 4 DLL2_OUT_RSTB for debug only 27 1 DLL2_OUT_EN for debug only 26 1 DLL1_OUT_RSTB for debug only 25 1 DLL1_OUT_EN for debug only 24 1 RSVD2 19 5 SEL_SYS_LP select clk_hpsys source during deep WFI 0 - selected by SEL_SYS; 1 - clk_wdt 18 1 SEL_SYS select clk_hpsys source during deep WFI 0 - clk_hrc48; 1 - clk_hxt48; 2 - RSVD; 3 - clk_dll1 16 2 DIV_EN enable PDIV1, PDIV2 and HDIV reconfiguration during deep wfi 15 1 PDIV2 pclk2_hpsys = hclk_hpsys / (2^PDIV2) during deep wfi 12 3 RSVD3 11 1 PDIV1 pclk_hpsys = hclk_hpsys / (2^PDIV1) during deep wfi 8 3 HDIV hclk_hpsys = clk_hpsys / HDIV during deep wfi 0 8 EXTDMA EXTDMA 0x50001000 0x0 0x1000 registers ISR ISR interrupt status register 0x00 0x20 read-write 0x00000000 RSVD 4 28 TEIF TEIF, transfer error flag 3 1 HTIF HTIF, half transfer flag 2 1 TCIF TCIF, transfer complete flag 1 1 GIF GIF, global interrupt flag 0 1 IFCR IFCR interrupt clear register 0x04 0x20 read-write 0x00000000 RSVD 4 28 CTEIF CTEIF, transfer error flag clear 3 1 CHTIF CHTIF, half transfer flag clear 2 1 CTCIF CTCIF, transfer complete flag clear 1 1 CGIF CGIF, global interrupt flag clear 0 1 CCR CCR channel control register 0x08 0x20 read-write 0x000F0AC0 RESET Software reset, will clear extdma status. Active high. Will be cleared by HW automatically 31 1 RSVD 20 11 SRCBURST source burst transfer configuration 00: single transfer 01: INCR4 (incremental burst of 4 beats) 10: INCR8 (incremental burst of 8 beats) 11: INCR16 (incremental burst of 16 beats) 18 2 DSTBURST destination burst transfer configuration 00: single transfer 01: INCR4 (incremental burst of 4 beats) 10: INCR8 (incremental burst of 8 beats) 11: INCR16 (incremental burst of 16 beats) 16 2 RSVD2 12 4 SRCSIZE source size Defines the data size of each DMA transfer to the source memory. Should be fixed to 10 (32 bits), word access allowed only. 10 2 DSTSIZE destination size Defines the data size of each DMA transfer to the destination memory. Should be fixed to 10 (32 bits), word access allowed only. 8 2 SRCINC source increment mode Defines the increment mode for each DMA transfer to the source memory. 0: disabled 1: enabled 7 1 DSTINC destination increment mode Defines the increment mode for each DMA transfer to the destination memory. 0: disabled 1: enabled 6 1 RSVD3 4 2 TEIE transfer error interrupt enable 0: disabled 1: enabled 3 1 HTIE half transfer interrupt enable 0: disabled 1: enabled 2 1 TCIE transfer complete interrupt enable 0: disabled 1: enabled 1 1 EN extdma enable. Will be cleared if ccr_reset is written 0 1 CNDTR CNDTR number of data register 0x0c 0x20 read-write 0x00000000 RSVD 20 12 NDT number of data to transfer (0 to 2^20 - 1) This field is updated by hardware when the channel is enabled: It is decremented after each transfer, indicating the remaining amount of data items to transfer. It is kept at zero when the programmed amount of data to transfer is reached. If this field is zero, no transfer can be served whatever the channel enabled or not 0 20 SRCAR SRCAR source address register 0x10 0x20 read-write 0x00000000 SRCADDR source address It contains the base address of the source data to be read. Should be word aligned 0 32 DSTAR DSTAR destination 0 address register 0x14 0x20 read-write 0x00000000 DSTADDR destination address It contains the base address of the destination data to be written. Should be word aligned 0 32 HPSYS_PINMUX HPSYS_PINMUX 0x50003000 0x0 0x1000 registers PAD_SA00 PAD_SA00 0x0 0x20 read-write 0x0 RSVD 12 20 POE Reserved. Always set to logic LOW 11 1 DS1 Drive Select 1. Used to select output drive strength 10 1 DS0 Drive Select 0. Used to select output drive strength 9 1 SR Slew Rate. Logic HIGH selects slow slew rate, logic LOW selects fast slew rate 8 1 IS Input Select. Logic LOW selects CMOS input, logic HIGH selects Schmitt input 7 1 IE Input Enable. Logic HIGH enables the input buffer 6 1 PS Pull Select. Logic HIGH selects pull-up, logic LOW select pull-down 5 1 PE Pull Enable. Logic HIGH enables week pull device 4 1 FSEL Function Select 0 4 PAD_SA01 PAD_SA01 0x4 0x20 read-write 0x0 RSVD 12 20 POE Reserved. Always set to logic LOW 11 1 DS1 Drive Select 1. Used to select output drive strength 10 1 DS0 Drive Select 0. Used to select output drive strength 9 1 SR Slew Rate. Logic HIGH selects slow slew rate, logic LOW selects fast slew rate 8 1 IS Input Select. Logic LOW selects CMOS input, logic HIGH selects Schmitt input 7 1 IE Input Enable. Logic HIGH enables the input buffer 6 1 PS Pull Select. Logic HIGH selects pull-up, logic LOW select pull-down 5 1 PE Pull Enable. Logic HIGH enables week pull device 4 1 FSEL Function Select 0 4 PAD_SA02 PAD_SA02 0x8 0x20 read-write 0x0 RSVD 12 20 POE Reserved. Always set to logic LOW 11 1 DS1 Drive Select 1. Used to select output drive strength 10 1 DS0 Drive Select 0. Used to select output drive strength 9 1 SR Slew Rate. Logic HIGH selects slow slew rate, logic LOW selects fast slew rate 8 1 IS Input Select. Logic LOW selects CMOS input, logic HIGH selects Schmitt input 7 1 IE Input Enable. Logic HIGH enables the input buffer 6 1 PS Pull Select. Logic HIGH selects pull-up, logic LOW select pull-down 5 1 PE Pull Enable. Logic HIGH enables week pull device 4 1 FSEL Function Select 0 4 PAD_SA03 PAD_SA03 0xc 0x20 read-write 0x0 RSVD 12 20 POE Reserved. Always set to logic LOW 11 1 DS1 Drive Select 1. Used to select output drive strength 10 1 DS0 Drive Select 0. Used to select output drive strength 9 1 SR Slew Rate. Logic HIGH selects slow slew rate, logic LOW selects fast slew rate 8 1 IS Input Select. Logic LOW selects CMOS input, logic HIGH selects Schmitt input 7 1 IE Input Enable. Logic HIGH enables the input buffer 6 1 PS Pull Select. Logic HIGH selects pull-up, logic LOW select pull-down 5 1 PE Pull Enable. Logic HIGH enables week pull device 4 1 FSEL Function Select 0 4 PAD_SA04 PAD_SA04 0x10 0x20 read-write 0x0 RSVD 12 20 POE Reserved. Always set to logic LOW 11 1 DS1 Drive Select 1. Used to select output drive strength 10 1 DS0 Drive Select 0. Used to select output drive strength 9 1 SR Slew Rate. Logic HIGH selects slow slew rate, logic LOW selects fast slew rate 8 1 IS Input Select. Logic LOW selects CMOS input, logic HIGH selects Schmitt input 7 1 IE Input Enable. Logic HIGH enables the input buffer 6 1 PS Pull Select. Logic HIGH selects pull-up, logic LOW select pull-down 5 1 PE Pull Enable. Logic HIGH enables week pull device 4 1 FSEL Function Select 0 4 PAD_SA05 PAD_SA05 0x14 0x20 read-write 0x0 RSVD 12 20 POE Reserved. Always set to logic LOW 11 1 DS1 Drive Select 1. Used to select output drive strength 10 1 DS0 Drive Select 0. Used to select output drive strength 9 1 SR Slew Rate. Logic HIGH selects slow slew rate, logic LOW selects fast slew rate 8 1 IS Input Select. Logic LOW selects CMOS input, logic HIGH selects Schmitt input 7 1 IE Input Enable. Logic HIGH enables the input buffer 6 1 PS Pull Select. Logic HIGH selects pull-up, logic LOW select pull-down 5 1 PE Pull Enable. Logic HIGH enables week pull device 4 1 FSEL Function Select 0 4 PAD_SA06 PAD_SA06 0x18 0x20 read-write 0x0 RSVD 12 20 POE Reserved. Always set to logic LOW 11 1 DS1 Drive Select 1. Used to select output drive strength 10 1 DS0 Drive Select 0. Used to select output drive strength 9 1 SR Slew Rate. Logic HIGH selects slow slew rate, logic LOW selects fast slew rate 8 1 IS Input Select. Logic LOW selects CMOS input, logic HIGH selects Schmitt input 7 1 IE Input Enable. Logic HIGH enables the input buffer 6 1 PS Pull Select. Logic HIGH selects pull-up, logic LOW select pull-down 5 1 PE Pull Enable. Logic HIGH enables week pull device 4 1 FSEL Function Select 0 4 PAD_SA07 PAD_SA07 0x1c 0x20 read-write 0x0 RSVD 12 20 POE Reserved. Always set to logic LOW 11 1 DS1 Drive Select 1. Used to select output drive strength 10 1 DS0 Drive Select 0. Used to select output drive strength 9 1 SR Slew Rate. Logic HIGH selects slow slew rate, logic LOW selects fast slew rate 8 1 IS Input Select. Logic LOW selects CMOS input, logic HIGH selects Schmitt input 7 1 IE Input Enable. Logic HIGH enables the input buffer 6 1 PS Pull Select. Logic HIGH selects pull-up, logic LOW select pull-down 5 1 PE Pull Enable. Logic HIGH enables week pull device 4 1 FSEL Function Select 0 4 PAD_SA08 PAD_SA08 0x20 0x20 read-write 0x0 RSVD 12 20 POE Reserved. Always set to logic LOW 11 1 DS1 Drive Select 1. Used to select output drive strength 10 1 DS0 Drive Select 0. Used to select output drive strength 9 1 SR Slew Rate. Logic HIGH selects slow slew rate, logic LOW selects fast slew rate 8 1 IS Input Select. Logic LOW selects CMOS input, logic HIGH selects Schmitt input 7 1 IE Input Enable. Logic HIGH enables the input buffer 6 1 PS Pull Select. Logic HIGH selects pull-up, logic LOW select pull-down 5 1 PE Pull Enable. Logic HIGH enables week pull device 4 1 FSEL Function Select 0 4 PAD_SA09 PAD_SA09 0x24 0x20 read-write 0x0 RSVD 12 20 POE Reserved. Always set to logic LOW 11 1 DS1 Drive Select 1. Used to select output drive strength 10 1 DS0 Drive Select 0. Used to select output drive strength 9 1 SR Slew Rate. Logic HIGH selects slow slew rate, logic LOW selects fast slew rate 8 1 IS Input Select. Logic LOW selects CMOS input, logic HIGH selects Schmitt input 7 1 IE Input Enable. Logic HIGH enables the input buffer 6 1 PS Pull Select. Logic HIGH selects pull-up, logic LOW select pull-down 5 1 PE Pull Enable. Logic HIGH enables week pull device 4 1 FSEL Function Select 0 4 PAD_SA10 PAD_SA10 0x28 0x20 read-write 0x0 RSVD 12 20 POE Reserved. Always set to logic LOW 11 1 DS1 Drive Select 1. Used to select output drive strength 10 1 DS0 Drive Select 0. Used to select output drive strength 9 1 SR Slew Rate. Logic HIGH selects slow slew rate, logic LOW selects fast slew rate 8 1 IS Input Select. Logic LOW selects CMOS input, logic HIGH selects Schmitt input 7 1 IE Input Enable. Logic HIGH enables the input buffer 6 1 PS Pull Select. Logic HIGH selects pull-up, logic LOW select pull-down 5 1 PE Pull Enable. Logic HIGH enables week pull device 4 1 FSEL Function Select 0 4 PAD_SA11 PAD_SA11 0x2c 0x20 read-write 0x0 RSVD 12 20 POE Reserved. Always set to logic LOW 11 1 DS1 Drive Select 1. Used to select output drive strength 10 1 DS0 Drive Select 0. Used to select output drive strength 9 1 SR Slew Rate. Logic HIGH selects slow slew rate, logic LOW selects fast slew rate 8 1 IS Input Select. Logic LOW selects CMOS input, logic HIGH selects Schmitt input 7 1 IE Input Enable. Logic HIGH enables the input buffer 6 1 PS Pull Select. Logic HIGH selects pull-up, logic LOW select pull-down 5 1 PE Pull Enable. Logic HIGH enables week pull device 4 1 FSEL Function Select 0 4 PAD_SA12 PAD_SA12 0x30 0x20 read-write 0x0 RSVD 12 20 POE Reserved. Always set to logic LOW 11 1 DS1 Drive Select 1. Used to select output drive strength 10 1 DS0 Drive Select 0. Used to select output drive strength 9 1 SR Slew Rate. Logic HIGH selects slow slew rate, logic LOW selects fast slew rate 8 1 IS Input Select. Logic LOW selects CMOS input, logic HIGH selects Schmitt input 7 1 IE Input Enable. Logic HIGH enables the input buffer 6 1 PS Pull Select. Logic HIGH selects pull-up, logic LOW select pull-down 5 1 PE Pull Enable. Logic HIGH enables week pull device 4 1 FSEL Function Select 0 4 PAD_PA00 PAD_PA00 0x34 0x20 read-write 0x0 RSVD 12 20 POE Reserved. Always set to logic LOW 11 1 DS1 Drive Select 1. Used to select output drive strength 10 1 DS0 Drive Select 0. Used to select output drive strength 9 1 SR Slew Rate. Logic HIGH selects slow slew rate, logic LOW selects fast slew rate 8 1 IS Input Select. Logic LOW selects CMOS input, logic HIGH selects Schmitt input 7 1 IE Input Enable. Logic HIGH enables the input buffer 6 1 PS Pull Select. Logic HIGH selects pull-up, logic LOW select pull-down 5 1 PE Pull Enable. Logic HIGH enables week pull device 4 1 FSEL Function Select 0 4 PAD_PA01 PAD_PA01 0x38 0x20 read-write 0x0 RSVD 12 20 POE Reserved. Always set to logic LOW 11 1 DS1 Drive Select 1. Used to select output drive strength 10 1 DS0 Drive Select 0. Used to select output drive strength 9 1 SR Slew Rate. Logic HIGH selects slow slew rate, logic LOW selects fast slew rate 8 1 IS Input Select. Logic LOW selects CMOS input, logic HIGH selects Schmitt input 7 1 IE Input Enable. Logic HIGH enables the input buffer 6 1 PS Pull Select. Logic HIGH selects pull-up, logic LOW select pull-down 5 1 PE Pull Enable. Logic HIGH enables week pull device 4 1 FSEL Function Select 0 4 PAD_PA02 PAD_PA02 0x3c 0x20 read-write 0x0 RSVD 12 20 POE Reserved. Always set to logic LOW 11 1 DS1 Drive Select 1. Used to select output drive strength 10 1 DS0 Drive Select 0. Used to select output drive strength 9 1 SR Slew Rate. Logic HIGH selects slow slew rate, logic LOW selects fast slew rate 8 1 IS Input Select. Logic LOW selects CMOS input, logic HIGH selects Schmitt input 7 1 IE Input Enable. Logic HIGH enables the input buffer 6 1 PS Pull Select. Logic HIGH selects pull-up, logic LOW select pull-down 5 1 PE Pull Enable. Logic HIGH enables week pull device 4 1 FSEL Function Select 0 4 PAD_PA03 PAD_PA03 0x40 0x20 read-write 0x0 RSVD 12 20 POE Reserved. Always set to logic LOW 11 1 DS1 Drive Select 1. Used to select output drive strength 10 1 DS0 Drive Select 0. Used to select output drive strength 9 1 SR Slew Rate. Logic HIGH selects slow slew rate, logic LOW selects fast slew rate 8 1 IS Input Select. Logic LOW selects CMOS input, logic HIGH selects Schmitt input 7 1 IE Input Enable. Logic HIGH enables the input buffer 6 1 PS Pull Select. Logic HIGH selects pull-up, logic LOW select pull-down 5 1 PE Pull Enable. Logic HIGH enables week pull device 4 1 FSEL Function Select 0 4 PAD_PA04 PAD_PA04 0x44 0x20 read-write 0x0 RSVD 12 20 POE Reserved. Always set to logic LOW 11 1 DS1 Drive Select 1. Used to select output drive strength 10 1 DS0 Drive Select 0. Used to select output drive strength 9 1 SR Slew Rate. Logic HIGH selects slow slew rate, logic LOW selects fast slew rate 8 1 IS Input Select. Logic LOW selects CMOS input, logic HIGH selects Schmitt input 7 1 IE Input Enable. Logic HIGH enables the input buffer 6 1 PS Pull Select. Logic HIGH selects pull-up, logic LOW select pull-down 5 1 PE Pull Enable. Logic HIGH enables week pull device 4 1 FSEL Function Select 0 4 PAD_PA05 PAD_PA05 0x48 0x20 read-write 0x0 RSVD 12 20 POE Reserved. Always set to logic LOW 11 1 DS1 Drive Select 1. Used to select output drive strength 10 1 DS0 Drive Select 0. Used to select output drive strength 9 1 SR Slew Rate. Logic HIGH selects slow slew rate, logic LOW selects fast slew rate 8 1 IS Input Select. Logic LOW selects CMOS input, logic HIGH selects Schmitt input 7 1 IE Input Enable. Logic HIGH enables the input buffer 6 1 PS Pull Select. Logic HIGH selects pull-up, logic LOW select pull-down 5 1 PE Pull Enable. Logic HIGH enables week pull device 4 1 FSEL Function Select 0 4 PAD_PA06 PAD_PA06 0x4c 0x20 read-write 0x0 RSVD 12 20 POE Reserved. Always set to logic LOW 11 1 DS1 Drive Select 1. Used to select output drive strength 10 1 DS0 Drive Select 0. Used to select output drive strength 9 1 SR Slew Rate. Logic HIGH selects slow slew rate, logic LOW selects fast slew rate 8 1 IS Input Select. Logic LOW selects CMOS input, logic HIGH selects Schmitt input 7 1 IE Input Enable. Logic HIGH enables the input buffer 6 1 PS Pull Select. Logic HIGH selects pull-up, logic LOW select pull-down 5 1 PE Pull Enable. Logic HIGH enables week pull device 4 1 FSEL Function Select 0 4 PAD_PA07 PAD_PA07 0x50 0x20 read-write 0x0 RSVD 12 20 POE Reserved. Always set to logic LOW 11 1 DS1 Drive Select 1. Used to select output drive strength 10 1 DS0 Drive Select 0. Used to select output drive strength 9 1 SR Slew Rate. Logic HIGH selects slow slew rate, logic LOW selects fast slew rate 8 1 IS Input Select. Logic LOW selects CMOS input, logic HIGH selects Schmitt input 7 1 IE Input Enable. Logic HIGH enables the input buffer 6 1 PS Pull Select. Logic HIGH selects pull-up, logic LOW select pull-down 5 1 PE Pull Enable. Logic HIGH enables week pull device 4 1 FSEL Function Select 0 4 PAD_PA08 PAD_PA08 0x54 0x20 read-write 0x0 RSVD 12 20 POE Reserved. Always set to logic LOW 11 1 DS1 Drive Select 1. Used to select output drive strength 10 1 DS0 Drive Select 0. Used to select output drive strength 9 1 SR Slew Rate. Logic HIGH selects slow slew rate, logic LOW selects fast slew rate 8 1 IS Input Select. Logic LOW selects CMOS input, logic HIGH selects Schmitt input 7 1 IE Input Enable. Logic HIGH enables the input buffer 6 1 PS Pull Select. Logic HIGH selects pull-up, logic LOW select pull-down 5 1 PE Pull Enable. Logic HIGH enables week pull device 4 1 FSEL Function Select 0 4 PAD_PA09 PAD_PA09 0x58 0x20 read-write 0x0 RSVD 12 20 POE Reserved. Always set to logic LOW 11 1 DS1 Drive Select 1. Used to select output drive strength 10 1 DS0 Drive Select 0. Used to select output drive strength 9 1 SR Slew Rate. Logic HIGH selects slow slew rate, logic LOW selects fast slew rate 8 1 IS Input Select. Logic LOW selects CMOS input, logic HIGH selects Schmitt input 7 1 IE Input Enable. Logic HIGH enables the input buffer 6 1 PS Pull Select. Logic HIGH selects pull-up, logic LOW select pull-down 5 1 PE Pull Enable. Logic HIGH enables week pull device 4 1 FSEL Function Select 0 4 PAD_PA10 PAD_PA10 0x5c 0x20 read-write 0x0 RSVD 12 20 POE Reserved. Always set to logic LOW 11 1 DS1 Drive Select 1. Used to select output drive strength 10 1 DS0 Drive Select 0. Used to select output drive strength 9 1 SR Slew Rate. Logic HIGH selects slow slew rate, logic LOW selects fast slew rate 8 1 IS Input Select. Logic LOW selects CMOS input, logic HIGH selects Schmitt input 7 1 IE Input Enable. Logic HIGH enables the input buffer 6 1 PS Pull Select. Logic HIGH selects pull-up, logic LOW select pull-down 5 1 PE Pull Enable. Logic HIGH enables week pull device 4 1 FSEL Function Select 0 4 PAD_PA11 PAD_PA11 0x60 0x20 read-write 0x0 RSVD 12 20 POE Reserved. Always set to logic LOW 11 1 DS1 Drive Select 1. Used to select output drive strength 10 1 DS0 Drive Select 0. Used to select output drive strength 9 1 SR Slew Rate. Logic HIGH selects slow slew rate, logic LOW selects fast slew rate 8 1 IS Input Select. Logic LOW selects CMOS input, logic HIGH selects Schmitt input 7 1 IE Input Enable. Logic HIGH enables the input buffer 6 1 PS Pull Select. Logic HIGH selects pull-up, logic LOW select pull-down 5 1 PE Pull Enable. Logic HIGH enables week pull device 4 1 FSEL Function Select 0 4 PAD_PA12 PAD_PA12 0x64 0x20 read-write 0x0 RSVD 12 20 POE Reserved. Always set to logic LOW 11 1 DS1 Drive Select 1. Used to select output drive strength 10 1 DS0 Drive Select 0. Used to select output drive strength 9 1 SR Slew Rate. Logic HIGH selects slow slew rate, logic LOW selects fast slew rate 8 1 IS Input Select. Logic LOW selects CMOS input, logic HIGH selects Schmitt input 7 1 IE Input Enable. Logic HIGH enables the input buffer 6 1 PS Pull Select. Logic HIGH selects pull-up, logic LOW select pull-down 5 1 PE Pull Enable. Logic HIGH enables week pull device 4 1 FSEL Function Select 0 4 PAD_PA13 PAD_PA13 0x68 0x20 read-write 0x0 RSVD 12 20 POE Reserved. Always set to logic LOW 11 1 DS1 Drive Select 1. Used to select output drive strength 10 1 DS0 Drive Select 0. Used to select output drive strength 9 1 SR Slew Rate. Logic HIGH selects slow slew rate, logic LOW selects fast slew rate 8 1 IS Input Select. Logic LOW selects CMOS input, logic HIGH selects Schmitt input 7 1 IE Input Enable. Logic HIGH enables the input buffer 6 1 PS Pull Select. Logic HIGH selects pull-up, logic LOW select pull-down 5 1 PE Pull Enable. Logic HIGH enables week pull device 4 1 FSEL Function Select 0 4 PAD_PA14 PAD_PA14 0x6c 0x20 read-write 0x0 RSVD 12 20 POE Reserved. Always set to logic LOW 11 1 DS1 Drive Select 1. Used to select output drive strength 10 1 DS0 Drive Select 0. Used to select output drive strength 9 1 SR Slew Rate. Logic HIGH selects slow slew rate, logic LOW selects fast slew rate 8 1 IS Input Select. Logic LOW selects CMOS input, logic HIGH selects Schmitt input 7 1 IE Input Enable. Logic HIGH enables the input buffer 6 1 PS Pull Select. Logic HIGH selects pull-up, logic LOW select pull-down 5 1 PE Pull Enable. Logic HIGH enables week pull device 4 1 FSEL Function Select 0 4 PAD_PA15 PAD_PA15 0x70 0x20 read-write 0x0 RSVD 12 20 POE Reserved. Always set to logic LOW 11 1 DS1 Drive Select 1. Used to select output drive strength 10 1 DS0 Drive Select 0. Used to select output drive strength 9 1 SR Slew Rate. Logic HIGH selects slow slew rate, logic LOW selects fast slew rate 8 1 IS Input Select. Logic LOW selects CMOS input, logic HIGH selects Schmitt input 7 1 IE Input Enable. Logic HIGH enables the input buffer 6 1 PS Pull Select. Logic HIGH selects pull-up, logic LOW select pull-down 5 1 PE Pull Enable. Logic HIGH enables week pull device 4 1 FSEL Function Select 0 4 PAD_PA16 PAD_PA16 0x74 0x20 read-write 0x0 RSVD 12 20 POE Reserved. Always set to logic LOW 11 1 DS1 Drive Select 1. Used to select output drive strength 10 1 DS0 Drive Select 0. Used to select output drive strength 9 1 SR Slew Rate. Logic HIGH selects slow slew rate, logic LOW selects fast slew rate 8 1 IS Input Select. Logic LOW selects CMOS input, logic HIGH selects Schmitt input 7 1 IE Input Enable. Logic HIGH enables the input buffer 6 1 PS Pull Select. Logic HIGH selects pull-up, logic LOW select pull-down 5 1 PE Pull Enable. Logic HIGH enables week pull device 4 1 FSEL Function Select 0 4 PAD_PA17 PAD_PA17 0x78 0x20 read-write 0x0 RSVD 12 20 POE Reserved. Always set to logic LOW 11 1 DS1 Drive Select 1. Used to select output drive strength 10 1 DS0 Drive Select 0. Used to select output drive strength 9 1 SR Slew Rate. Logic HIGH selects slow slew rate, logic LOW selects fast slew rate 8 1 IS Input Select. Logic LOW selects CMOS input, logic HIGH selects Schmitt input 7 1 IE Input Enable. Logic HIGH enables the input buffer 6 1 PS Pull Select. Logic HIGH selects pull-up, logic LOW select pull-down 5 1 PE Pull Enable. Logic HIGH enables week pull device 4 1 FSEL Function Select 0 4 PAD_PA18 PAD_PA18 0x7c 0x20 read-write 0x0 RSVD 12 20 POE Reserved. Always set to logic LOW 11 1 DS1 Drive Select 1. Used to select output drive strength 10 1 DS0 Drive Select 0. Used to select output drive strength 9 1 SR Slew Rate. Logic HIGH selects slow slew rate, logic LOW selects fast slew rate 8 1 IS Input Select. Logic LOW selects CMOS input, logic HIGH selects Schmitt input 7 1 IE Input Enable. Logic HIGH enables the input buffer 6 1 PS Pull Select. Logic HIGH selects pull-up, logic LOW select pull-down 5 1 PE Pull Enable. Logic HIGH enables week pull device 4 1 FSEL Function Select 0 4 PAD_PA19 PAD_PA19 0x80 0x20 read-write 0x0 RSVD 12 20 POE Reserved. Always set to logic LOW 11 1 DS1 Drive Select 1. Used to select output drive strength 10 1 DS0 Drive Select 0. Used to select output drive strength 9 1 SR Slew Rate. Logic HIGH selects slow slew rate, logic LOW selects fast slew rate 8 1 IS Input Select. Logic LOW selects CMOS input, logic HIGH selects Schmitt input 7 1 IE Input Enable. Logic HIGH enables the input buffer 6 1 PS Pull Select. Logic HIGH selects pull-up, logic LOW select pull-down 5 1 PE Pull Enable. Logic HIGH enables week pull device 4 1 FSEL Function Select 0 4 PAD_PA20 PAD_PA20 0x84 0x20 read-write 0x0 RSVD 12 20 POE Reserved. Always set to logic LOW 11 1 DS1 Drive Select 1. Used to select output drive strength 10 1 DS0 Drive Select 0. Used to select output drive strength 9 1 SR Slew Rate. Logic HIGH selects slow slew rate, logic LOW selects fast slew rate 8 1 IS Input Select. Logic LOW selects CMOS input, logic HIGH selects Schmitt input 7 1 IE Input Enable. Logic HIGH enables the input buffer 6 1 PS Pull Select. Logic HIGH selects pull-up, logic LOW select pull-down 5 1 PE Pull Enable. Logic HIGH enables week pull device 4 1 FSEL Function Select 0 4 PAD_PA21 PAD_PA21 0x88 0x20 read-write 0x0 RSVD 12 20 POE Reserved. Always set to logic LOW 11 1 DS1 Drive Select 1. Used to select output drive strength 10 1 DS0 Drive Select 0. Used to select output drive strength 9 1 SR Slew Rate. Logic HIGH selects slow slew rate, logic LOW selects fast slew rate 8 1 IS Input Select. Logic LOW selects CMOS input, logic HIGH selects Schmitt input 7 1 IE Input Enable. Logic HIGH enables the input buffer 6 1 PS Pull Select. Logic HIGH selects pull-up, logic LOW select pull-down 5 1 PE Pull Enable. Logic HIGH enables week pull device 4 1 FSEL Function Select 0 4 PAD_PA22 PAD_PA22 0x8c 0x20 read-write 0x0 RSVD 12 20 POE Reserved. Always set to logic LOW 11 1 DS1 Drive Select 1. Used to select output drive strength 10 1 DS0 Drive Select 0. Used to select output drive strength 9 1 SR Slew Rate. Logic HIGH selects slow slew rate, logic LOW selects fast slew rate 8 1 IS Input Select. Logic LOW selects CMOS input, logic HIGH selects Schmitt input 7 1 IE Input Enable. Logic HIGH enables the input buffer 6 1 PS Pull Select. Logic HIGH selects pull-up, logic LOW select pull-down 5 1 PE Pull Enable. Logic HIGH enables week pull device 4 1 FSEL Function Select 0 4 PAD_PA23 PAD_PA23 0x90 0x20 read-write 0x0 RSVD 12 20 POE Reserved. Always set to logic LOW 11 1 DS1 Drive Select 1. Used to select output drive strength 10 1 DS0 Drive Select 0. Used to select output drive strength 9 1 SR Slew Rate. Logic HIGH selects slow slew rate, logic LOW selects fast slew rate 8 1 IS Input Select. Logic LOW selects CMOS input, logic HIGH selects Schmitt input 7 1 IE Input Enable. Logic HIGH enables the input buffer 6 1 PS Pull Select. Logic HIGH selects pull-up, logic LOW select pull-down 5 1 PE Pull Enable. Logic HIGH enables week pull device 4 1 FSEL Function Select 0 4 PAD_PA24 PAD_PA24 0x94 0x20 read-write 0x0 RSVD 12 20 POE Reserved. Always set to logic LOW 11 1 DS1 Drive Select 1. Used to select output drive strength 10 1 DS0 Drive Select 0. Used to select output drive strength 9 1 SR Slew Rate. Logic HIGH selects slow slew rate, logic LOW selects fast slew rate 8 1 IS Input Select. Logic LOW selects CMOS input, logic HIGH selects Schmitt input 7 1 IE Input Enable. Logic HIGH enables the input buffer 6 1 PS Pull Select. Logic HIGH selects pull-up, logic LOW select pull-down 5 1 PE Pull Enable. Logic HIGH enables week pull device 4 1 FSEL Function Select 0 4 PAD_PA25 PAD_PA25 0x98 0x20 read-write 0x0 RSVD 12 20 POE Reserved. Always set to logic LOW 11 1 DS1 Drive Select 1. Used to select output drive strength 10 1 DS0 Drive Select 0. Used to select output drive strength 9 1 SR Slew Rate. Logic HIGH selects slow slew rate, logic LOW selects fast slew rate 8 1 IS Input Select. Logic LOW selects CMOS input, logic HIGH selects Schmitt input 7 1 IE Input Enable. Logic HIGH enables the input buffer 6 1 PS Pull Select. Logic HIGH selects pull-up, logic LOW select pull-down 5 1 PE Pull Enable. Logic HIGH enables week pull device 4 1 FSEL Function Select 0 4 PAD_PA26 PAD_PA26 0x9c 0x20 read-write 0x0 RSVD 12 20 POE Reserved. Always set to logic LOW 11 1 DS1 Drive Select 1. Used to select output drive strength 10 1 DS0 Drive Select 0. Used to select output drive strength 9 1 SR Slew Rate. Logic HIGH selects slow slew rate, logic LOW selects fast slew rate 8 1 IS Input Select. Logic LOW selects CMOS input, logic HIGH selects Schmitt input 7 1 IE Input Enable. Logic HIGH enables the input buffer 6 1 PS Pull Select. Logic HIGH selects pull-up, logic LOW select pull-down 5 1 PE Pull Enable. Logic HIGH enables week pull device 4 1 FSEL Function Select 0 4 PAD_PA27 PAD_PA27 0xa0 0x20 read-write 0x0 RSVD 12 20 POE Reserved. Always set to logic LOW 11 1 DS1 Drive Select 1. Used to select output drive strength 10 1 DS0 Drive Select 0. Used to select output drive strength 9 1 SR Slew Rate. Logic HIGH selects slow slew rate, logic LOW selects fast slew rate 8 1 IS Input Select. Logic LOW selects CMOS input, logic HIGH selects Schmitt input 7 1 IE Input Enable. Logic HIGH enables the input buffer 6 1 PS Pull Select. Logic HIGH selects pull-up, logic LOW select pull-down 5 1 PE Pull Enable. Logic HIGH enables week pull device 4 1 FSEL Function Select 0 4 PAD_PA28 PAD_PA28 0xa4 0x20 read-write 0x0 RSVD 12 20 POE Reserved. Always set to logic LOW 11 1 DS1 Drive Select 1. Used to select output drive strength 10 1 DS0 Drive Select 0. Used to select output drive strength 9 1 SR Slew Rate. Logic HIGH selects slow slew rate, logic LOW selects fast slew rate 8 1 IS Input Select. Logic LOW selects CMOS input, logic HIGH selects Schmitt input 7 1 IE Input Enable. Logic HIGH enables the input buffer 6 1 PS Pull Select. Logic HIGH selects pull-up, logic LOW select pull-down 5 1 PE Pull Enable. Logic HIGH enables week pull device 4 1 FSEL Function Select 0 4 PAD_PA29 PAD_PA29 0xa8 0x20 read-write 0x0 RSVD 12 20 POE Reserved. Always set to logic LOW 11 1 DS1 Drive Select 1. Used to select output drive strength 10 1 DS0 Drive Select 0. Used to select output drive strength 9 1 SR Slew Rate. Logic HIGH selects slow slew rate, logic LOW selects fast slew rate 8 1 IS Input Select. Logic LOW selects CMOS input, logic HIGH selects Schmitt input 7 1 IE Input Enable. Logic HIGH enables the input buffer 6 1 PS Pull Select. Logic HIGH selects pull-up, logic LOW select pull-down 5 1 PE Pull Enable. Logic HIGH enables week pull device 4 1 FSEL Function Select 0 4 PAD_PA30 PAD_PA30 0xac 0x20 read-write 0x0 RSVD 12 20 POE Reserved. Always set to logic LOW 11 1 DS1 Drive Select 1. Used to select output drive strength 10 1 DS0 Drive Select 0. Used to select output drive strength 9 1 SR Slew Rate. Logic HIGH selects slow slew rate, logic LOW selects fast slew rate 8 1 IS Input Select. Logic LOW selects CMOS input, logic HIGH selects Schmitt input 7 1 IE Input Enable. Logic HIGH enables the input buffer 6 1 PS Pull Select. Logic HIGH selects pull-up, logic LOW select pull-down 5 1 PE Pull Enable. Logic HIGH enables week pull device 4 1 FSEL Function Select 0 4 PAD_PA31 PAD_PA31 0xb0 0x20 read-write 0x0 RSVD 12 20 POE Reserved. Always set to logic LOW 11 1 DS1 Drive Select 1. Used to select output drive strength 10 1 DS0 Drive Select 0. Used to select output drive strength 9 1 SR Slew Rate. Logic HIGH selects slow slew rate, logic LOW selects fast slew rate 8 1 IS Input Select. Logic LOW selects CMOS input, logic HIGH selects Schmitt input 7 1 IE Input Enable. Logic HIGH enables the input buffer 6 1 PS Pull Select. Logic HIGH selects pull-up, logic LOW select pull-down 5 1 PE Pull Enable. Logic HIGH enables week pull device 4 1 FSEL Function Select 0 4 PAD_PA32 PAD_PA32 0xb4 0x20 read-write 0x0 RSVD 12 20 POE Reserved. Always set to logic LOW 11 1 DS1 Drive Select 1. Used to select output drive strength 10 1 DS0 Drive Select 0. Used to select output drive strength 9 1 SR Slew Rate. Logic HIGH selects slow slew rate, logic LOW selects fast slew rate 8 1 IS Input Select. Logic LOW selects CMOS input, logic HIGH selects Schmitt input 7 1 IE Input Enable. Logic HIGH enables the input buffer 6 1 PS Pull Select. Logic HIGH selects pull-up, logic LOW select pull-down 5 1 PE Pull Enable. Logic HIGH enables week pull device 4 1 FSEL Function Select 0 4 PAD_PA33 PAD_PA33 0xb8 0x20 read-write 0x0 RSVD 12 20 POE Reserved. Always set to logic LOW 11 1 DS1 Drive Select 1. Used to select output drive strength 10 1 DS0 Drive Select 0. Used to select output drive strength 9 1 SR Slew Rate. Logic HIGH selects slow slew rate, logic LOW selects fast slew rate 8 1 IS Input Select. Logic LOW selects CMOS input, logic HIGH selects Schmitt input 7 1 IE Input Enable. Logic HIGH enables the input buffer 6 1 PS Pull Select. Logic HIGH selects pull-up, logic LOW select pull-down 5 1 PE Pull Enable. Logic HIGH enables week pull device 4 1 FSEL Function Select 0 4 PAD_PA34 PAD_PA34 0xbc 0x20 read-write 0x0 RSVD 12 20 POE Reserved. Always set to logic LOW 11 1 DS1 Drive Select 1. Used to select output drive strength 10 1 DS0 Drive Select 0. Used to select output drive strength 9 1 SR Slew Rate. Logic HIGH selects slow slew rate, logic LOW selects fast slew rate 8 1 IS Input Select. Logic LOW selects CMOS input, logic HIGH selects Schmitt input 7 1 IE Input Enable. Logic HIGH enables the input buffer 6 1 PS Pull Select. Logic HIGH selects pull-up, logic LOW select pull-down 5 1 PE Pull Enable. Logic HIGH enables week pull device 4 1 FSEL Function Select 0 4 PAD_PA35 PAD_PA35 0xc0 0x20 read-write 0x0 RSVD 12 20 POE Reserved. Always set to logic LOW 11 1 DS1 Drive Select 1. Used to select output drive strength 10 1 DS0 Drive Select 0. Used to select output drive strength 9 1 SR Slew Rate. Logic HIGH selects slow slew rate, logic LOW selects fast slew rate 8 1 IS Input Select. Logic LOW selects CMOS input, logic HIGH selects Schmitt input 7 1 IE Input Enable. Logic HIGH enables the input buffer 6 1 PS Pull Select. Logic HIGH selects pull-up, logic LOW select pull-down 5 1 PE Pull Enable. Logic HIGH enables week pull device 4 1 FSEL Function Select 0 4 PAD_PA36 PAD_PA36 0xc4 0x20 read-write 0x0 RSVD 12 20 POE Reserved. Always set to logic LOW 11 1 DS1 Drive Select 1. Used to select output drive strength 10 1 DS0 Drive Select 0. Used to select output drive strength 9 1 SR Slew Rate. Logic HIGH selects slow slew rate, logic LOW selects fast slew rate 8 1 IS Input Select. Logic LOW selects CMOS input, logic HIGH selects Schmitt input 7 1 IE Input Enable. Logic HIGH enables the input buffer 6 1 PS Pull Select. Logic HIGH selects pull-up, logic LOW select pull-down 5 1 PE Pull Enable. Logic HIGH enables week pull device 4 1 FSEL Function Select 0 4 PAD_PA37 PAD_PA37 0xc8 0x20 read-write 0x0 RSVD 12 20 POE Reserved. Always set to logic LOW 11 1 DS1 Drive Select 1. Used to select output drive strength 10 1 DS0 Drive Select 0. Used to select output drive strength 9 1 SR Slew Rate. Logic HIGH selects slow slew rate, logic LOW selects fast slew rate 8 1 IS Input Select. Logic LOW selects CMOS input, logic HIGH selects Schmitt input 7 1 IE Input Enable. Logic HIGH enables the input buffer 6 1 PS Pull Select. Logic HIGH selects pull-up, logic LOW select pull-down 5 1 PE Pull Enable. Logic HIGH enables week pull device 4 1 FSEL Function Select 0 4 PAD_PA38 PAD_PA38 0xcc 0x20 read-write 0x0 RSVD 12 20 POE Reserved. Always set to logic LOW 11 1 DS1 Drive Select 1. Used to select output drive strength 10 1 DS0 Drive Select 0. Used to select output drive strength 9 1 SR Slew Rate. Logic HIGH selects slow slew rate, logic LOW selects fast slew rate 8 1 IS Input Select. Logic LOW selects CMOS input, logic HIGH selects Schmitt input 7 1 IE Input Enable. Logic HIGH enables the input buffer 6 1 PS Pull Select. Logic HIGH selects pull-up, logic LOW select pull-down 5 1 PE Pull Enable. Logic HIGH enables week pull device 4 1 FSEL Function Select 0 4 PAD_PA39 PAD_PA39 0xd0 0x20 read-write 0x0 RSVD 12 20 POE Reserved. Always set to logic LOW 11 1 DS Drive Select. Logic LOW selects 4mA drive,logic HIGH selects 20mA drive 10 1 RSVD2 9 1 MODE Mode Select. Logic LOW enables GPIO mode,logic HIGH enables I2C mode 8 1 IS Input Select. Logic LOW selects CMOS input, logic HIGH selects Schmitt input 7 1 IE Input Enable. Logic HIGH enables the input buffer 6 1 PS Pull Select. Logic HIGH selects pull-up, logic LOW select pull-down 5 1 PE Pull Enable. Logic HIGH enables week pull device 4 1 FSEL Function Select 0 4 PAD_PA40 PAD_PA40 0xd4 0x20 read-write 0x0 RSVD 12 20 POE Reserved. Always set to logic LOW 11 1 DS Drive Select. Logic LOW selects 4mA drive,logic HIGH selects 20mA drive 10 1 RSVD2 9 1 MODE Mode Select. Logic LOW enables GPIO mode,logic HIGH enables I2C mode 8 1 IS Input Select. Logic LOW selects CMOS input, logic HIGH selects Schmitt input 7 1 IE Input Enable. Logic HIGH enables the input buffer 6 1 PS Pull Select. Logic HIGH selects pull-up, logic LOW select pull-down 5 1 PE Pull Enable. Logic HIGH enables week pull device 4 1 FSEL Function Select 0 4 PAD_PA41 PAD_PA41 0xd8 0x20 read-write 0x0 RSVD 12 20 POE Reserved. Always set to logic LOW 11 1 DS Drive Select. Logic LOW selects 4mA drive,logic HIGH selects 20mA drive 10 1 RSVD2 9 1 MODE Mode Select. Logic LOW enables GPIO mode,logic HIGH enables I2C mode 8 1 IS Input Select. Logic LOW selects CMOS input, logic HIGH selects Schmitt input 7 1 IE Input Enable. Logic HIGH enables the input buffer 6 1 PS Pull Select. Logic HIGH selects pull-up, logic LOW select pull-down 5 1 PE Pull Enable. Logic HIGH enables week pull device 4 1 FSEL Function Select 0 4 PAD_PA42 PAD_PA42 0xdc 0x20 read-write 0x0 RSVD 12 20 POE Reserved. Always set to logic LOW 11 1 DS Drive Select. Logic LOW selects 4mA drive,logic HIGH selects 20mA drive 10 1 RSVD2 9 1 MODE Mode Select. Logic LOW enables GPIO mode,logic HIGH enables I2C mode 8 1 IS Input Select. Logic LOW selects CMOS input, logic HIGH selects Schmitt input 7 1 IE Input Enable. Logic HIGH enables the input buffer 6 1 PS Pull Select. Logic HIGH selects pull-up, logic LOW select pull-down 5 1 PE Pull Enable. Logic HIGH enables week pull device 4 1 FSEL Function Select 0 4 PAD_PA43 PAD_PA43 0xe0 0x20 read-write 0x0 RSVD 12 20 POE Reserved. Always set to logic LOW 11 1 DS1 Drive Select 1. Used to select output drive strength 10 1 DS0 Drive Select 0. Used to select output drive strength 9 1 SR Slew Rate. Logic HIGH selects slow slew rate, logic LOW selects fast slew rate 8 1 IS Input Select. Logic LOW selects CMOS input, logic HIGH selects Schmitt input 7 1 IE Input Enable. Logic HIGH enables the input buffer 6 1 PS Pull Select. Logic HIGH selects pull-up, logic LOW select pull-down 5 1 PE Pull Enable. Logic HIGH enables week pull device 4 1 FSEL Function Select 0 4 PAD_PA44 PAD_PA44 0xe4 0x20 read-write 0x0 RSVD 12 20 POE Reserved. Always set to logic LOW 11 1 DS1 Drive Select 1. Used to select output drive strength 10 1 DS0 Drive Select 0. Used to select output drive strength 9 1 SR Slew Rate. Logic HIGH selects slow slew rate, logic LOW selects fast slew rate 8 1 IS Input Select. Logic LOW selects CMOS input, logic HIGH selects Schmitt input 7 1 IE Input Enable. Logic HIGH enables the input buffer 6 1 PS Pull Select. Logic HIGH selects pull-up, logic LOW select pull-down 5 1 PE Pull Enable. Logic HIGH enables week pull device 4 1 FSEL Function Select 0 4 ATIM1 ATIM 0x50004000 0x0 0x1000 registers CR1 CR1 TIM control register 1 0x00 0x20 read-write 0x00000000 RSVD 12 20 UIFREMAP UIF status bit remapping 0: No remapping. UIF status bit is not copied to CNT register bit 31 1: Remapping enabled. UIF status bit is copied to CNT register bit 31. 11 1 RSVD2 8 3 ARPE Auto-reload preload enable 0: ARR register is not buffered 1: ARR register is buffered 7 1 CMS Center-aligned mode selection 00: Edge-aligned mode. The counter counts up or down depending on the direction bit (DIR). 01: Center-aligned mode 1. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in CCMRx register) are set only when the counter is counting down. 10: Center-aligned mode 2. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in CCMRx register) are set only when the counter is counting up. 11: Center-aligned mode 3. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in CCMRx register) are set both when the counter is counting up or down. 5 2 DIR Direction 0: Counter used as upcounter 1: Counter used as downcounter 4 1 OPM One-pulse mode 0: Counter is not stopped at update event 1: Counter stops counting at the next update event (clearing the bit CEN) 3 1 URS Update request source This bit is set and cleared by software to select the UEV event sources. 0: Any of the following events generate an update interrupt or DMA request if enabled. These events can be: Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller 1: Only counter overflow/underflow generates an update interrupt or DMA request if enabled. 2 1 UDIS Update disable This bit is set and cleared by software to enable/disable UEV event generation. 0: UEV enabled. The Update (UEV) event is generated by one of the following events: Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values. 1: UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller. 1 1 CEN Counter enable 0: Counter disabled 1: Counter enabled External clock, gated mode and encoder mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. CEN is cleared automatically in one-pulse mode, when an update event occurs. 0 1 CR2 CR2 TIM control register 2 0x04 0x20 read-write 0x00000000 RSVD 19 13 OIS6 Output Idle state 6 (OC6 output) 18 1 RSVD2 17 1 OIS5 Output Idle state 5 (OC5 output) 16 1 RSVD3 15 1 OIS4 Output Idle state 4 (OC4 output) 14 1 OIS3N Output Idle state 3 (OC3N output) 13 1 OIS3 Output Idle state 3 (OC3 output) 12 1 OIS2N Output Idle state 2 (OC2N output) 11 1 OIS2 Output Idle state 2 (OC2 output) 10 1 OIS1N Output Idle state 1 (OC1N output) 0: OC1N=0 after a dead-time when MOE=0 1: OC1N=1 after a dead-time when MOE=0 This bit, as well as other OISxN, can not be modified as long as LOCK level 1, 2 or 3 has been programmed 9 1 OIS1 Output Idle state 1 (OC1 output) 0: OC1=0 (after a dead-time if OC1N is implemented) when MOE=0 1: OC1=1 (after a dead-time if OC1N is implemented) when MOE=0 This bit, as well as other OISx, can not be modified as long as LOCK level 1, 2 or 3 has been programmed 8 1 TI1S TI1 selection 0: The CH1 pin is connected to TI1 input 1: The CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) 7 1 MMS Master mode selection These bits allow to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: 000: Reset - the UG bit from the EGR register is used as trigger output (TRGO). If the reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on TRGO is delayed compared to the actual reset. 001: Enable - the Counter enable signal, CNT_EN, is used as trigger output (TRGO). It is useful to start several timers at the same time or to control a window in which a slave timer is enabled. The Counter Enable signal is generated by a logic OR between CEN control bit and the trigger input when configured in gated mode. When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected. 010: Update - The update event is selected as trigger output (TRGO). For instance a master timer can then be used as a prescaler for a slave timer. 011: Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or a compare match occurred. (TRGO) 100: Compare - OC1REFC signal is used as trigger output (TRGO) 101: Compare - OC2REFC signal is used as trigger output (TRGO) 110: Compare - OC3REFC signal is used as trigger output (TRGO) 111: Compare - OC4REFC signal is used as trigger output (TRGO) 4 3 CCDS Capture/compare DMA selection 0: CCx DMA request sent when CCx event occurs 1: CCx DMA requests sent when update event occurs 3 1 CCUS Capture/compare control update selection 0: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only 1: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an edge occurs on TRGI after Trigger selection This bit acts only on channels that have a complementary output. 2 1 RSVD4 1 1 CCPC Capture/compare preloaded control 0: CCxE, CCxNE and OCxM bits are not preloaded 1: CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated only when a commutation event (COM) occurs (COMG bit set or edge detected on TRGI after Trigger selection, depending on the CCUS bit). This bit acts only on channels that have a complementary output. 0 1 SMCR SMCR TIM slave mode control register 0x08 0x20 read-write 0x00000000 RSVD 20 12 SMS Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input. 0000: Slave mode disabled. 0001: Encoder mode 1 - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level. 0010: Encoder mode 2 - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level. 0011: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. 0100: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers. 0101: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled. 0110: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled. 0111: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter. 1000: Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter. 16 4 ETP External trigger polarity This bit selects whether ETR or ETR is used for trigger operations 0: ETR is non-inverted, active at high level or rising edge 1: ETR is inverted, active at low level or falling edge 15 1 ECE External clock enable This bit enables External clock mode 2. 0: External clock mode 2 disabled 1: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal. 14 1 ETPS External trigger prescaler External trigger signal ETRP frequency must be at most 1/4 of CK_INT frequency. A prescaler can be enabled to reduce ETRP frequency. It is useful when inputting fast external clocks. 00: Prescaler OFF 01: ETRP frequency divided by 2 10: ETRP frequency divided by 4 11: ETRP frequency divided by 8 12 2 ETF External trigger filter This bit-field then defines the frequency used to sample ETRP signal and the length of the digital filter applied to ETRP. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: 0000: No filter, sampling is done at fCLK 0001: fSAMPLING=fCLK, N=2 0010: fSAMPLING=fCLK, N=4 0011: fSAMPLING=fCLK, N=8 0100: fSAMPLING=fCLK/2, N=6 0101: fSAMPLING=fCLK/2, N=8 0110: fSAMPLING=fCLK/4, N=6 0111: fSAMPLING=fCLK/4, N=8 1000: fSAMPLING=fCLK/8, N=6 1001: fSAMPLING=fCLK/8, N=8 1010: fSAMPLING=fCLK/16, N=5 1011: fSAMPLING=fCLK/16, N=6 1100: fSAMPLING=fCLK/16, N=8 1101: fSAMPLING=fCLK/32, N=5 1110: fSAMPLING=fCLK/32, N=6 1111: fSAMPLING=fCLK/32, N=8 8 4 MSM Master/Slave mode 0: No action 1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event. 7 1 TS Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. 000: Internal Trigger 0 (ITR0) 001: Internal Trigger 1 (ITR1) 010: Internal Trigger 2 (ITR2) 011: Internal Trigger 3 (ITR3) 100: TI1 Edge Detector (TI1F_ED) 101: Filtered Timer Input 1 (TI1FP1) 110: Filtered Timer Input 2 (TI2FP2) 111: External Trigger input (ETRF) 4 3 RSVD2 0 4 DIER DIER TIM DMA/Interrupt enable register 0x0c 0x20 read-write 0x00000000 RSVD 18 14 CC6IE Capture/Compare 6 interrupt enable 0: CC6 interrupt disabled. 1: CC6 interrupt enabled 17 1 CC5IE Capture/Compare 5 interrupt enable 0: CC5 interrupt disabled. 1: CC5 interrupt enabled 16 1 RSVD2 15 1 TDE Trigger DMA request enable 0: Trigger DMA request disabled. 1: Trigger DMA request enabled. 14 1 COMDE COM DMA request enable 0: COM DMA request disabled 1: COM DMA request enabled 13 1 CC4DE Capture/Compare 4 DMA request enable 0: CC4 DMA request disabled. 1: CC4 DMA request enabled 12 1 CC3DE Capture/Compare 3 DMA request enable 0: CC3 DMA request disabled. 1: CC3 DMA request enabled. 11 1 CC2DE Capture/Compare 2 DMA request enable 0: CC2 DMA request disabled. 1: CC2 DMA request enabled. 10 1 CC1DE Capture/Compare 1 DMA request enable 0: CC1 DMA request disabled. 1: CC1 DMA request enabled. 9 1 UDE Update DMA request enable 0: Update DMA request disabled. 1: Update DMA request enabled 8 1 BIE Break interrupt enable 0: Break interrupt disabled 1: Break interrupt enabled 7 1 TIE Trigger interrupt enable 0: Trigger interrupt disabled. 1: Trigger interrupt enabled 6 1 COMIE COM interrupt enable 0: COM interrupt disabled 1: COM interrupt enabled 5 1 CC4IE Capture/Compare 4 interrupt enable 0: CC4 interrupt disabled. 1: CC4 interrupt enabled 4 1 CC3IE Capture/Compare 3 interrupt enable 0: CC3 interrupt disabled. 1: CC3 interrupt enabled 3 1 CC2IE Capture/Compare 2 interrupt enable 0: CC2 interrupt disabled. 1: CC2 interrupt enabled. 2 1 CC1IE Capture/Compare 1 interrupt enable 0: CC1 interrupt disabled. 1: CC1 interrupt enabled 1 1 UIE Update interrupt enable 0: Update interrupt disabled. 1: Update interrupt enabled 0 1 SR SR TIM status register 0x10 0x20 read-write 0x00000000 RSVD 18 14 CC6IF Compare 6 interrupt flag 17 1 CC5IF Compare 5 interrupt flag 16 1 RSVD2 15 1 RSVD3 14 1 SBIF System Break interrupt flag This flag is set by hardware as soon as the system break input goes active. It can be cleared by software if the system break input is not active. This flag must be reset to re-start PWM operation. 0: No break event occurred. 1: An active level has been detected on the system break input. An interrupt is generated if BIE=1 in the DIER register. 13 1 CC4OF Capture/Compare 4 overcapture flag 12 1 CC3OF Capture/Compare 3 overcapture flag 11 1 CC2OF Capture/Compare 2 overcapture flag 10 1 CC1OF Capture/Compare 1 overcapture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing it to '0'. 0: No overcapture has been detected. 1: The counter value has been captured in CCR1 register while CC1IF flag was already set 9 1 B2IF Break 2 interrupt flag This flag is set by hardware as soon as the break 2 input goes active. It can be cleared by software if the break 2 input is not active. 0: No break event occurred. 1: An active level has been detected on the break 2 input. An interrupt is generated if BIE=1 in the DIER register. 8 1 BIF Break interrupt flag This flag is set by hardware as soon as the break input goes active. It can be cleared by software if the break input is not active. 0: No break event occurred. 1: An active level has been detected on the break input. An interrupt is generated if BIE=1 in the DIER register. 7 1 TIF Trigger interrupt flag This flag is set by hardware on trigger event. It is set when the counter starts or stops when gated mode is selected. It is cleared by software. 0: No trigger event occurred. 1: Trigger interrupt pending. 6 1 COMIF COM interrupt flag This flag is set by hardware on COM event (when Capture/compare Control bits - CCxE, CCxNE, OCxM - have been updated). It is cleared by software. 0: No COM event occurred. 1: COM interrupt pending. 5 1 CC4IF Capture/Compare 4 interrupt flag 4 1 CC3IF Capture/Compare 3 interrupt flag 3 1 CC2IF Capture/Compare 2 interrupt flag 2 1 CC1IF Capture/Compare 1 interrupt flag If channel CC1 is configured as output: This flag is set by hardware when the counter matches the compare value and in retriggerable one pulse mode. It is cleared by software. 0: No match. 1: The content of the counter CNT has matched the content of the CCR1 register. If channel CC1 is configured as input: This bit is set by hardware on a capture. It is cleared by software or by reading the CCR1 register. 0: No input capture occurred. 1: The counter value has been captured in CCR1 register. 1 1 UIF Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. 0: No update occurred 1: Update interrupt pending. This bit is set by hardware when the registers are updated: - At overflow or underflow regarding the repetition counter value (update if repetition counter = 0) and if UDIS=0 in the CR1 register. - When CNT is reinitialized by software using the UG bit in EGR register, if URS=0 and UDIS=0 in the CR1 register. - When CNT is reinitialized by a trigger event, if URS=0 and UDIS=0 in the CR1 register. 0 1 EGR EGR Event generation register 0x14 0x20 read-write 0x00000000 RSVD 9 23 B2G Break 2 generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 0: No action 1: A break 2 event is generated. MOE bit is cleared and B2IF flag is set. Related interrupt can occur if enabled. 8 1 BG Break generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 0: No action 1: A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled. 7 1 TG Trigger generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 0: No action 1: The TIF flag is set in SR register. Related interrupt or DMA transfer can occur if enabled. 6 1 COMG Capture/Compare control update generation This bit can be set by software, it is automatically cleared by hardware 0: No action 1: When CCPC bit is set, it allows to update CCxE, CCxNE and OCxM bits This bit acts only on channels having a complementary output. 5 1 CC4G Capture/compare 4 generation 4 1 CC3G Capture/compare 3 generation 3 1 CC2G Capture/compare 2 generation 2 1 CC1G Capture/compare 1 generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 0: No action 1: A capture/compare event is generated on channel 1: If channel CC1 is configured as output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If channel CC1 is configured as input: The current value of the counter is captured in CCR1 register. The CC1IF flag is set, the corresponding interrupt or DMA request is sent if enabled. The CC1OF flag is set if the CC1IF flag was already high. 1 1 UG Update generation This bit can be set by software, it is automatically cleared by hardware. 0: No action 1: Re-initialize the counter and generates an update of the registers. The prescaler counter is cleared too (anyway the prescaler ratio is not affected). The counter is cleared if the center-aligned mode is selected or if DIR=0 (upcounting), else it takes the auto-reload value (ARR) if DIR=1 (downcounting). 0 1 CCMR1 CCMR1 TIM capture/compare mode register 1 0x18 0x20 read-write 0x00000000 OC2M Output compare 2 mode 28 4 OC2PE Output compare 2 preload enable 27 1 RSVD 25 2 OC2CE Output compare 2 clear enable 24 1 OC1M Output compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits. 0000: Frozen - The comparison between the output compare register CCR1 and the counter CNT has no effect on the outputs. 0001: Set channel 1 to active level on match. OC1REF signal is forced high when the counter CNT matches the capture/compare register 1 (CCR1). 0010: Set channel 1 to inactive level on match. OC1REF signal is forced low when the counter CNT matches the capture/compare register 1 (CCR1). 0011: Toggle - OC1REF toggles when CNT=CCR1. 0100: Force inactive level - OC1REF is forced low. 0101: Force active level - OC1REF is forced high. 0110: PWM mode 1 - In upcounting, channel 1 is active as long as CNTltCCR1 else inactive. In downcounting, channel 1 is inactive (OC1REF=0) as long as CNT>CCR1 else active (OC1REF=1). 0111: PWM mode 2 - In upcounting, channel 1 is inactive as long as CNTltCCR1 else active. In downcounting, channel 1 is active as long as CNT>CCR1 else inactive. 1000: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes inactive again at the next update. In down-counting mode, the channel is inactive until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes inactive again at the next update. 1001: Retriggerable OPM mode 2 - In up-counting mode, the channel is inactive until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 2 and the channels becomes inactive again at the next update. In down-counting mode, the channel is active until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes active again at the next update. 1010: Reserved, 1011: Reserved, 1100: Combined PWM mode 1 - OC1REF has the same behavior as in PWM mode 1. OC1REFC is the logical OR between OC1REF and OC2REF. 1101: Combined PWM mode 2 - OC1REF has the same behavior as in PWM mode 2. OC1REFC is the logical AND between OC1REF and OC2REF. 1110: Asymmetric PWM mode 1 - OC1REF has the same behavior as in PWM mode 1. OC1REFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down. 1111: Asymmetric PWM mode 2 - OC1REF has the same behavior as in PWM mode 2. OC1REFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down. These bits can not be modified as long as LOCK level 3 has been programmed and CC1S=00 (the channel is configured in output). On channels having a complementary output, this bit field is preloaded. If the CCPC bit is set in the CR2 register then the OC1M active bits take the new value from the preloaded bits only when a COM event is generated. 20 4 OC1PE Output compare 1 preload enable 0: Preload register on CCR1 disabled. CCR1 can be written at anytime, the new value is taken in account immediately. 1: Preload register on CCR1 enabled. Read/Write operations access the preload register. CCR1 preload value is loaded in the active register at each update event. These bits can not be modified as long as LOCK level 3 has been programmed and CC1S='00' (the channel is configured in output). 19 1 RSVD2 17 2 OC1CE Output compare 1 clear enable 0: OC1Ref is not affected by the ETRF input 1: OC1Ref is cleared as soon as a High level is detected on ETRF input 16 1 IC2F Input capture 2 filter 12 4 IC2PSC Input capture 2 prescaler 10 2 CC2S Capture/Compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC2 channel is configured as output 01: CC2 channel is configured as input, IC2 is mapped on TI2 10: CC2 channel is configured as input, IC2 is mapped on TI1 11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if an internal trigger input is selected through the TS bit (SMCR register) 8 2 IC1F Input capture 1 filter This bit-field defines the frequency used to sample TI1 input and the length of the digital filter applied to TI1. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: 0000: No filter, sampling is done at fCLK 0001: fSAMPLING=fCLK, N=2 0010: fSAMPLING=fCLK, N=4 0011: fSAMPLING=fCLK, N=8 0100: fSAMPLING=fCLK/2, N=6 0101: fSAMPLING=fCLK/2, N=8 0110: fSAMPLING=fCLK/4, N=6 0111: fSAMPLING=fCLK/4, N=8 1000: fSAMPLING=fCLK/8, N=6 1001: fSAMPLING=fCLK/8, N=8 1010: fSAMPLING=fCLK/16, N=5 1011: fSAMPLING=fCLK/16, N=6 1100: fSAMPLING=fCLK/16, N=8 1101: fSAMPLING=fCLK/32, N=5 1110: fSAMPLING=fCLK/32, N=6 1111: fSAMPLING=fCLK/32, N=8 4 4 IC1PSC Input capture 1 prescaler This bit-field defines the ratio of the prescaler acting on CC1 input (IC1). The prescaler is reset as soon as CC1E=0 (CCER register). 00: no prescaler, capture is done each time an edge is detected on the capture input 01: capture is done once every 2 events 10: capture is done once every 4 events 11: capture is done once every 8 events 2 2 CC1S Capture/Compare 1 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC1 channel is configured as output 01: CC1 channel is configured as input, IC1 is mapped on TI1 10: CC1 channel is configured as input, IC1 is mapped on TI2 11: CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (SMCR register) 0 2 CCMR2 CCMR2 TIM capture/compare mode register 2 0x1c 0x20 read-write 0x00000000 OC4M Output compare 4 mode 28 4 OC4PE Output compare 4 preload enable 27 1 RSVD 25 2 OC4CE Output compare 4 clear enable 24 1 OC3M Output compare 3 mode 20 4 OC3PE Output compare 3 preload enable 19 1 RSVD2 17 2 OC3CE Output compare 3 clear enable 16 1 IC4F Input capture 4 filter 12 4 IC4PSC Input capture 4 prescaler 10 2 CC4S Capture/Compare 4 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC4 channel is configured as output 01: CC4 channel is configured as input, IC4 is mapped on TI4 10: CC4 channel is configured as input, IC4 is mapped on TI3 11: CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (SMCR register) 8 2 IC3F Input capture 3 filter 4 4 IC3PSC Input capture 3 prescaler 2 2 CC3S Capture/Compare 3 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC3 channel is configured as output 01: CC3 channel is configured as input, IC3 is mapped on TI3 10: CC3 channel is configured as input, IC3 is mapped on TI4 11: CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (SMCR register) 0 2 CCER CCER Capture/Compare enable register 0x20 0x20 read-write 0x00000000 RSVD 22 10 CC6P Capture/Compare 6 output Polarity. 21 1 CC6E Capture/Compare 6 output enable. 20 1 RSVD2 19 1 RSVD3 18 1 CC5P Capture/Compare 5 output Polarity. 17 1 CC5E Capture/Compare 5 output enable. 16 1 CC4NP Capture/Compare 4 complementary output polarity 15 1 RSVD4 14 1 CC4P Capture/Compare 4 output Polarity. 13 1 CC4E Capture/Compare 4 output enable. 12 1 CC3NP Capture/Compare 3 complementary output polarity 11 1 CC3NE Capture/Compare 3 complementary output enable 10 1 CC3P Capture/Compare 3 output Polarity. 9 1 CC3E Capture/Compare 3 output enable. 8 1 CC2NP Capture/Compare 2 complementary output polarity 7 1 CC2NE Capture/Compare 2 complementary output enable 6 1 CC2P Capture/Compare 2 output Polarity. 5 1 CC2E Capture/Compare 2 output enable. 4 1 CC1NP Capture/Compare 1 complementary output polarity CC1 channel configured as output: 0: OC1N active high. 1: OC1N active low. CC1 channel configured as input: This bit is used in conjunction with CC1P to define the polarity of TI1FP1 and TI2FP1. Refer to CC1P description. On channels having a complementary output, this bit is preloaded. If the CCPC bit is set in the CR2 register then the CC1NP active bit takes the new value from the preloaded bit only when a Commutation event is generated. This bit as well as other CCxNP is not writable as soon as LOCK level 2 or 3 has been programmed and CC1S=00 (channel configured as output). 3 1 CC1NE Capture/Compare 1 complementary output enable 0: Off - OC1N is not active. OC1N level is then function of MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits. 1: On - OC1N signal is output on the corresponding output pin depending on MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits. On channels having a complementary output, this bit is preloaded. If the CCPC bit is set in the CR2 register then the CC1NE active bit takes the new value from the preloaded bit only when a Commutation event is generated. 2 1 CC1P Capture/Compare 1 output Polarity. CC1 channel configured as output: 0: OC1 active high 1: OC1 active low CC1 channel configured as input: CC1NP/CC1P bits select TI1FP1 and TI2FP1 polarity for trigger or capture operations. 00: noninverted/rising edge. Circuit is sensitive to TIxFP1 rising edge (capture, trigger in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger in gated mode, encoder mode). 01: inverted/falling edge. Circuit is sensitive to TIxFP1 falling edge (capture, trigger in reset, external clock or trigger mode), TIxFP1 is inverted (trigger in gated mode, encoder mode). 10: reserved, do not use this configuration. 11: noninverted/both edges. Circuit is sensitive to both TIxFP1 rising and falling edges (capture, trigger in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger in gated mode). This configuration must not be used for encoder mode. On channels having a complementary output, this bit is preloaded. If the CCPC bit is set in the CR2 register then the CC1P active bit takes the new value from the preloaded bit only when a Commutation event is generated. This bit as well as other CCxP is not writable as soon as LOCK level 2 or 3 has been programmed. 1 1 CC1E Capture/Compare 1 output enable CC1 channel configured as output: 0: Off - OC1 is not active. OC1 level is then function of MOE, OSSI, OSSR, OIS1, OIS1N and CC1NE bits. 1: On - OC1 signal is output on the corresponding output pin depending on MOE, OSSI, OSSR, OIS1, OIS1N and CC1NE bits. CC1 channel configured as input: This bit determines if a capture of the counter value can actually be done into the input capture/compare register 1 (CCR1) or not. 0: Capture disabled. 1: Capture enabled. On channels having a complementary output, this bit is preloaded. If the CCPC bit is set in the CR2 register then the CC1E active bit takes the new value from the preloaded bit only when a Commutation event is generated. 0 1 CNT CNT Counter 0x24 0x20 read-write 0x00000000 CNT bit 30 to 0 is the lower bits of counter value bit 31 depends on IUFREMAP in CR1. If UIFREMAP = 1 this bit is a read-only copy of the UIF bit of the ISR register If UIFREMAP = 0 this bit is counter value bit 31 0 32 PSC PSC Prescaler 0x28 0x20 read-write 0x00000000 RSVD 16 16 PSC Prescaler value The counter clock frequency is fCLK/(PSC+1). PSC contains the value to be loaded in the active prescaler register at each update event (including when the counter is cleared through UG bit of EGR register or through trigger controller when configured in "reset mode"). 0 16 ARR ARR Auto-reload register 0x2c 0x20 read-write 0x00000000 ARR Auto-reload value ARR is the value to be loaded in the actual auto-reload register. 0 32 RCR RCR Repetition counter register 0x30 0x20 read-write 0x00000000 RSVD 16 16 REP Repetition counter value These bits allow the user to set-up the update rate of the compare registers when preload registers are enable, as well as the update interrupt generation rate, if this interrupt is enable. Each time the REP_CNT related downcounter reaches zero, an update event is generated and it restarts counting from REP value. As REP_CNT is reloaded with REP value only at the repetition update event, any write to the RCR register is not taken in account until the next repetition update event. It means in PWM mode (REP+1) corresponds to the number of PWM periods in edge-aligned mode or the number of half PWM period in center-aligned mode.. 0 16 CCR1 CCR1 Capture/Compare register 1 0x34 0x20 read-write 0x00000000 CCR1 Capture/Compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value).It is loaded permanently if the preload feature is not selected in the CCMR1 register (bit OC1PE). Else the preload value is copied in the active capture/compare 1 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter CNT and signaled on OC1 output. If channel CC1is configured as input: CCR1 is the counter value transferred by the last input capture 1 event (IC1). 0 32 CCR2 CCR2 Capture/Compare register 2 0x38 0x20 read-write 0x00000000 CCR2 Capture/Compare 2 value If channel CC2 is configured as output: CCR2 is the value to be loaded in the actual capture/compare 2 register (preload value).It is loaded permanently if the preload feature is not selected in the CCMR1 register (bit OC2PE). Else the preload value is copied in the active capture/compare 2 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter CNT and signalled on OC2 output. If channel CC2 is configured as input: CCR2 is the counter value transferred by the last input capture 2 event (IC2). 0 32 CCR3 CCR3 Capture/Compare register 3 0x3c 0x20 read-write 0x00000000 CCR3 Capture/Compare value If channel CC3 is configured as output: CCR3 is the value to be loaded in the actual capture/compare 3 register (preload value).It is loaded permanently if the preload feature is not selected in the CCMR2 register (bit OC3PE). Else the preload value is copied in the active capture/compare 3 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter CNT and signalled on OC3 output. If channel CC3is configured as input: CCR3 is the counter value transferred by the last input capture 3 event (IC3). 0 32 CCR4 CCR4 Capture/Compare register 4 0x40 0x20 read-write 0x00000000 CCR4 Capture/Compare value 1. if CC4 channel is configured as output (CC4S bits): CCR4 is the value to be loaded in the actual capture/compare 4 register (preload value).It is loaded permanently if the preload feature is not selected in the CCMR2 register (bit OC4PE). Else the preload value is copied in the active capture/compare 4 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter CNT and signalled on OC4 output. 2. if CC4 channel is configured as input (CC4S bits in CCMR4 register): CCR4 is the counter value transferred by the last input capture 4 event (IC4). 0 32 BDTR BDTR TIM break and dead-time register 0x44 0x20 read-write 0x00000000 OSSR Off-state selection for Run mode This bit is used when MOE=1 on channels having a complementary output which are configured as outputs. OSSR is not implemented if no complementary output is implemented in the timer. 0: When inactive, OC/OCN outputs are disabled (the timer releases the output control, forces a Hi-Z state). 1: When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 (the output is still controlled by the timer). This bit can not be modified as soon as the LOCK level 2 has been programmed. 31 1 OSSI Off-state selection for Idle mode This bit is used when MOE=0 due to a break event or by a software write, on channels configured as outputs. 0: When inactive, OC/OCN outputs are disabled (the timer releases the output control, imposes a Hi-Z state). 1: When inactive, OC/OCN outputs are first forced with their inactive level then forced to their idle level after the deadtime. The timer maintains its control over the output. This bit can not be modified as soon as the LOCK level 2 has been programmed. 30 1 BK2BID Break2 bidirectional 29 1 BKBID Break Bidirectional 0: Break input BRK in input mode 1: Break input BRK in bidirectional mode In the bidirectional mode (BKBID bit set to 1), the break input is configured both in input mode and in open drain output mode. Any active break event asserts a low logic level on the Break input to indicate an internal break event to external devices. This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits in BDTR register). 28 1 BK2DSRM Break2 Disarm 27 1 BKDSRM Break Disarm 0: Break input BRK is armed 1: Break input BRK is disarmed This bit is cleared by hardware when no break source is active. The BKDSRM bit must be set by software to release the bidirectional output control (open-drain output in Hi-Z state) and then be polled it until it is reset by hardware, indicating that the fault condition has disappeared. 26 1 BK2P BK2P: Break 2 polarity 0: Break input BRK2 is active low 1: Break input BRK2 is active high This bit cannot be modified as long as LOCK level 1 has been programmed. 25 1 BK2E Break 2 enable This bit enables the complete break 2 protection. 0: Break2 function disabled 1: Break2 function enabled This bit cannot be modified as long as LOCK level 1 has been programmed. 24 1 BK2F Break 2 filter This bit-field defines the frequency used to sample BRK2 input and the length of the digital filter applied to BRK2. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: 0000: No filter, BRK2 acts asynchronously 0001: fSAMPLING=fCLK, N=2 0010: fSAMPLING=fCLK, N=4 0011: fSAMPLING=fCLK, N=8 0100: fSAMPLING=fCLK/2, N=6 0101: fSAMPLING=fCLK/2, N=8 0110: fSAMPLING=fCLK/4, N=6 0111: fSAMPLING=fCLK/4, N=8 1000: fSAMPLING=fCLK/8, N=6 1001: fSAMPLING=fCLK/8, N=8 1010: fSAMPLING=fCLK/16, N=5 1011: fSAMPLING=fCLK/16, N=6 1100: fSAMPLING=fCLK/16, N=8 1101: fSAMPLING=fCLK/32, N=5 1110: fSAMPLING=fCLK/32, N=6 1111: fSAMPLING=fCLK/32, N=8 This bit cannot be modified as long as LOCK level 1 has been programmed. 20 4 BKF Break filter This bit-field defines the frequency used to sample BRK input and the length of the digital filter applied to BRK. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: 0000: No filter, BRK acts asynchronously 0001: fSAMPLING=fCLK, N=2 0010: fSAMPLING=fCLK, N=4 0011: fSAMPLING=fCLK, N=8 0100: fSAMPLING=fCLK/2, N=6 0101: fSAMPLING=fCLK/2, N=8 0110: fSAMPLING=fCLK/4, N=6 0111: fSAMPLING=fCLK/4, N=8 1000: fSAMPLING=fCLK/8, N=6 1001: fSAMPLING=fCLK/8, N=8 1010: fSAMPLING=fCLK/16, N=5 1011: fSAMPLING=fCLK/16, N=6 1100: fSAMPLING=fCLK/16, N=8 1101: fSAMPLING=fCLK/32, N=5 1110: fSAMPLING=fCLK/32, N=6 1111: fSAMPLING=fCLK/32, N=8 This bit cannot be modified as long as LOCK level 1 has been programmed. 16 4 MOE Main output enable This bit is cleared asynchronously by hardware as soon as one of the break inputs is active (BRK or BRK2). It is set by software or automatically depending on the AOE bit. It is acting only on the channels which are configured in output. 0: In response to a break 2 event. OC and OCN outputs are disabled In response to a break event or if MOE is written to 0: OC and OCN outputs are disabled or forced to idle state depending on the OSSI bit. 1: OC and OCN outputs are enabled if their respective enable bits are set (CCxE, CCxNE in CCER register). 15 1 AOE Automatic output enable 0: MOE can be set only by software 1: MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active) This bit cannot be modified as long as LOCK level 1 has been programmed. 14 1 BKP Break polarity 0: Break input BRK is active low 1: Break input BRK is active high This bit cannot be modified as long as LOCK level 1 has been programmed. 13 1 BKE Break enable This bit enables the complete break protection. 0: Break function disabled 1: Break function enabled This bit cannot be modified as long as LOCK level 1 has been programmed. 12 1 DTPSC Dead-time prescaler This bit-field enables dead-time prescaler. 0: dead-time is tCLK*(DTG+1) if DTG is not zero 1: dead-time is tCLK*(DTG+1)*16 if DTG is not zero This bit cannot be modified as long as LOCK level 1 has been programmed. 11 1 RSVD 10 1 DTG Dead-time generator setup This bit-field, together with DTPSC, defines the duration of the dead-time inserted between the complementary outputs. If DTG=0, dead-time is disabled. Example if tCLK=8.33ns (120MHz), dead-time possible values are: 16.67ns to 8533.33 ns by 8.33 ns steps if DTPSC=0, 266.67ns to 136.53 us by 133.33 ns steps if DTPSC=1 This bit cannot be modified as long as LOCK level 1 has been programmed. 0 10 RSVD1 RSVD1 0x48 0x20 read-write 0x0 CCMR3 CCMR3 TIM capture/compare mode register 3 0x54 0x20 read-write 0x00000000 OC6M Output compare 6 mode 28 4 OC6PE Output compare 6 preload enable 27 1 RSVD 25 2 OC6CE Output compare 6 clear enable 24 1 OC5M Output compare 5 mode 20 4 OC5PE Output compare 5 preload enable 19 1 RSVD2 17 2 OC5CE Output compare 5 clear enable 16 1 GC5C3 Group Channel 5 and Channel 3 Distortion on Channel 3 output: 0: No effect of OC5REF on OC3REFC 1: OC3REFC is the logical AND of OC3REFC and OC5REF This bit can either have immediate effect or be preloaded and taken into account after an update event (if preload feature is selected in TIMxCCMR2). 15 1 GC5C2 Group Channel 5 and Channel 2 Distortion on Channel 2 output: 0: No effect of OC5REF on OC2REFC 1: OC2REFC is the logical AND of OC2REFC and OC5REF This bit can either have immediate effect or be preloaded and taken into account after an update event (if preload feature is selected in TIMxCCMR1). 14 1 GC5C1 Group Channel 5 and Channel 1 Distortion on Channel 1 output: 0: No effect of OC5REF on OC1REFC5 1: OC1REFC is the logical AND of OC1REFC and OC5REF This bit can either have immediate effect or be preloaded and taken into account after an update event (if preload feature is selected in TIMxCCMR1). 13 1 RSVD3 0 13 CCR5 CCR5 Capture/Compare register 5 0x58 0x20 read-write 0x00000000 CCR5 Capture/Compare 5 value CCR5 is the value to be loaded in the actual capture/compare 5 register (preload value). It is loaded permanently if the preload feature is not selected in the CCMR3 register (bit OC5PE). Else the preload value is copied in the active capture/compare 5 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter CNT and signaled on OC5 output. 0 32 CCR6 CCR6 Capture/Compare register 6 0x5c 0x20 read-write 0x00000000 CCR6 Capture/Compare 6 value CCR6 is the value to be loaded in the actual capture/compare 6 register (preload value). It is loaded permanently if the preload feature is not selected in the CCMR3 register (bit OC6PE). Else the preload value is copied in the active capture/compare 6 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter CNT and signaled on OC6 output. 0 32 AF1 AF1 Alternate function option register 0x60 0x20 read-write 0x00000001 LOCK Lock configuration These bits offer a write protection against software errors. 00: LOCK OFF - No bit is write protected. 01: LOCK Level 1 = OISx and OISxN bits in CR2 register, BK2BID, BKBID, BK2DSRM, BKDSRM, BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR, DTPSC and DTG bits in BDTR register, AF1 register and AF2 register can no longer be written. 10: LOCK Level 2 = LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written. 11: LOCK Level 3 = LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written. The LOCK bits can be written to non-zero only once after reset. 30 2 RSVD 16 14 ETRSEL ETR source selection 00: ETR input is connected to I/O 01: LPCOMP output1 (if LPCOMP integrated) 10: LPCOMP output2 (if LPCOMP integrated) 11: ETR input is connected to I/O This bit cannot be modified as long as LOCK level 1 has been programmed. 14 2 RSVD2 12 2 BKCMP2P BRK LPCOMP output2 polarity This bit selects the LPCOMP output2 sensitivity (if LPCOMP integrated). It must be programmed together with the BKP polarity bit. 0: LPCOMP output2 is active high 1: LPCOMP output2 is active low This bit cannot be modified as long as LOCK level 1 has been programmed. 11 1 BKCMP1P BRK LPCOMP output1 polarity This bit selects the LPCOMP output1 sensitivity (if LPCOMP integrated). It must be programmed together with the BKP polarity bit. 0: LPCOMP output1 is active high 1: LPCOMP output1 is active low This bit cannot be modified as long as LOCK level 1 has been programmed. 10 1 BKINP BRK BKIN input polarity This bit selects the BKIN input sensitivity. It must be programmed together with the BKP polarity bit. 0: BKIN input is active high 1: BKIN input is active low This bit cannot be modified as long as LOCK level 1 has been programmed. 9 1 RSVD3 3 6 BKCMP2E BRK LPCOMP output2 enable This bit enables the LPCOMP output2 (if LPCOMP integrated) for the timer's BRK input. LPCOMP output2 is 'ORed' with the other BRK sources. 0: LPCOMP output2 disabled 1: LPCOMP output2 enabled This bit cannot be modified as long as LOCK level 1 has been programmed. 2 1 BKCMP1E BRK LPCOMP output1 enable This bit enables the LPCOMP output1 (if LPCOMP integrated) for the timer's BRK input. LPCOMP output1 is 'ORed' with the other BRK sources. 0: LPCOMP output1 disabled 1: LPCOMP output1 enabled This bit cannot be modified as long as LOCK level 1 has been programmed. 1 1 BKINE BRK BKIN input enable This bit enables the BKIN input. BKIN input is 'Ored' with the other BRK sources. 0: BKIN input disabled 1: BKIN input enabled This bit cannot be modified as long as LOCK level 1 has been programmed. 0 1 AF2 AF2 Alternate function option register 2 0x64 0x20 read-write 0x00000001 RSVD 12 20 BK2CMP2P BRK2 LPCOMP output2 polarity This bit selects the LPCOMP output2 sensitivity (if LPCOMP integrated). It must be programmed together with the BK2P polarity bit. 0: LPCOMP output2 is active high 1: LPCOMP output2 is active low This bit cannot be modified as long as LOCK level 1 has been programmed. 11 1 BK2CMP1P BRK2 LPCOMP output1 polarity This bit selects the LPCOMP output1 sensitivity (if LPCOMP integrated). It must be programmed together with the BK2P polarity bit. 0: LPCOMP output1 is active high 1: LPCOMP output1 is active low This bit cannot be modified as long as LOCK level 1 has been programmed. 10 1 BK2INP BRK2 BKIN2 input polarity This bit selects the BKIN2 input sensitivity. It must be programmed together with the BK2P polarity bit. 0: BKIN2 input is active low 1: BKIN2 input is active high This bit cannot be modified as long as LOCK level 1 has been programmed. 9 1 RSVD2 3 6 BK2CMP2E BRK2 LPCOMP output2 enable This bit enables the LPCOMP output2 (if LPCOMP integrated) for the timer's BRK2 input. LPCOMP output2 is 'ORed' with the other BRK2 sources. 0: LPCOMP output2 disabled 1: LPCOMP output2 enabled This bit cannot be modified as long as LOCK level 1 has been programmed. 2 1 BK2CMP1E BRK2 LPCOMP output1 enable This bit enables the LPCOMP output1 (if LPCOMP integrated) for the timer's BRK2 input. LPCOMP output1 is 'ORed' with the other BRK2 sources. 0: LPCOMP output1 disabled 1: LPCOMP output1 enabled This bit cannot be modified as long as LOCK level 1 has been programmed. 1 1 BK2INE BRK2 BKIN input enable This bit enables the BKIN2 input. BKIN2 input is 'Ored' with the other BRK2 sources. 0: BKIN2 input disabled 1: BKIN2 input enabled This bit cannot be modified as long as LOCK level 1 has been programmed. 0 1 AUDPRC AUDPRC 0x50005000 0x0 0x1000 registers ID ID 0x00 0x20 read-write 0x000A0000 REV revision id 0 32 CFG CFG 0x04 0x20 read-write 0x00000000 RSVD 21 11 AUDCLK_DIV_UPDATE audprc clock divider update, write 1 to update 20 1 AUDCLK_DIV audprc clock divider, 0 and 1 means divide by 1 16 4 RSVD2 10 6 STB_CLK_SEL audio strobe clock select 0: use xtal clock to generate strobe 1: use pll clock to generate strobe 9 1 AUTO_GATE_EN auto clock gating enable, high active 8 1 ADC_PATH_EN adc path enable 7 1 DAC_PATH_EN dac path enable 6 1 ADC_PATH_SRESET adc path software reset, high active 5 1 DAC_PATH_SRESET dac path software reset, high active 4 1 ADC_PATH_FLUSH adc path fifo flush, high active 3 1 DAC_PATH_FLUSH dac path fifo flush, high active 2 1 SRESET audprc software reset, high active 1 1 ENABLE audprc enable 0 1 STB STB 0x08 0x20 read-write 0x00010001 ADC_DIV adc strobe divider 16 16 DAC_DIV dac strobe divider 0 16 IRQ IRQ 0x0c 0x20 read-write 0x00000000 RSVD 26 6 TX_OUT1_FIFO_UF_MASK tx_out channel 1 fifo underflow mask, 0: mask the interrupt 25 1 TX_OUT0_FIFO_UF_MASK tx_out channel 0 fifo underflow mask, 0: mask the interrupt 24 1 RX_IN_FIFO_OF_MASK rx input fifo overflow mask, 0: mask the interrupt 23 1 TX_OUT_FIFO_UF_MASK tx output fifo underflow mask, 0: mask the interrupt 22 1 RX1_FIFO_UF_MASK rx channel 1 fifo underflow mask, 0: mask the interrupt 21 1 RX0_FIFO_UF_MASK rx channel 0 fifo underflow mask, 0: mask the interrupt 20 1 TX3_FIFO_OF_MASK tx channel 3 fifo overflow mask, 0: mask the interrupt 19 1 TX2_FIFO_OF_MASK tx channel 2 fifo overflow mask, 0: mask the interrupt 18 1 TX1_FIFO_OF_MASK tx channel 1 fifo overflow mask, 0: mask the interrupt 17 1 TX0_FIFO_OF_MASK tx channel 0 fifo overflow mask, 0: mask the interrupt 16 1 RSVD2 10 6 TX_OUT1_FIFO_UF tx_out channel 1 fifo underflow, write 1 to clear 9 1 TX_OUT0_FIFO_UF tx_out channel 0 fifo underflow, write 1 to clear 8 1 RX_IN_FIFO_OF rx input fifo overflow, write 1 to clear 7 1 TX_OUT_FIFO_UF tx output fifo underflow, write 1 to clear 6 1 RX1_FIFO_UF rx channel 1 fifo underflow, write 1 to clear 5 1 RX0_FIFO_UF rx channel 0 fifo underflow, write 1 to clear 4 1 TX3_FIFO_OF tx channel 3 fifo overflow, write 1 to clear 3 1 TX2_FIFO_OF tx channel 2 fifo overflow, write 1 to clear 2 1 TX1_FIFO_OF tx channel 1 fifo overflow, write 1 to clear 1 1 TX0_FIFO_OF tx channel 0 fifo overflow, write 1 to clear 0 1 TX_CH0_CFG TX_CH0_CFG 0x10 0x20 read-write 0x00000000 RSVD 8 24 FIFO_CNT tx fifo counter 4 4 DMA_MSK 1: mask the dma request for tx ch0 3 1 MODE tx mode 1'h0: mono mode 1'h1: stereo mode This bit is only used for 16-bit mode, in 24-bit mode, channel can only be set in mono mode. In 16-bit stereo mode, tx channel 1 is not working, both left and right audio data comes from channel 0. 2 1 FORMAT tx format 0: 16-bit mode 1: 24-bit mode 1 1 ENABLE tx channel 0 enable 0 1 TX_CH0_ENTRY TX_CH0_ENTRY 0x14 0x20 read-write 0x00000000 DATA tx channel 0 data entry 0 32 TX_CH1_CFG TX_CH1_CFG 0x18 0x20 read-write 0x00000000 RSVD 8 24 FIFO_CNT tx fifo counter 4 4 DMA_MSK 1: mask the dma request for tx ch1 3 1 RSVD2 2 1 FORMAT tx format 0: 16-bit mode 1: 24-bit mode 1 1 ENABLE tx channel 0 enable 0 1 TX_CH1_ENTRY TX_CH1_ENTRY 0x1c 0x20 read-write 0x00000000 DATA tx channel 1 data entry 0 32 TX_CH2_CFG TX_CH2_CFG 0x20 0x20 read-write 0x00000000 RSVD 8 24 FIFO_CNT tx fifo counter 4 4 DMA_MSK 1: mask the dma request for tx ch2 3 1 MODE tx mode 1'h0: mono mode 1'h1: stereo mode This bit is only used for 16-bit mode, in 24-bit mode, channel can only be set in mono mode. In 16-bit stereo mode, tx channel 3 is not working, both left and right audio data comes from channel 2. 2 1 FORMAT tx format 0: 16-bit mode 1: 24-bit mode 1 1 ENABLE tx channel 0 enable 0 1 TX_CH2_ENTRY TX_CH2_ENTRY 0x24 0x20 read-write 0x00000000 DATA tx channel 2 data entry 0 32 TX_CH3_CFG TX_CH3_CFG 0x28 0x20 read-write 0x00000000 RSVD 8 24 FIFO_CNT tx fifo counter 4 4 DMA_MSK 1: mask the dma request for tx ch3 3 1 RSVD2 2 1 FORMAT tx format 0: 16-bit mode 1: 24-bit mode 1 1 ENABLE tx channel 0 enable 0 1 TX_CH3_ENTRY TX_CH3_ENTRY 0x2c 0x20 read-write 0x00000000 DATA tx channel 3 data entry 0 32 RX_CH0_CFG RX_CH0_CFG 0x30 0x20 read-write 0x00000000 RSVD 8 24 FIFO_CNT rx fifo counter 4 4 DMA_MSK 1: mask the dma request for rx ch0 3 1 MODE rx mode 1'h0: mono mode 1'h1: stereo mode This bit is only used for 16-bit mode, in 24-bit mode, channel can only be set in mono mode. In 16-bit stereo mode, rx channel 1 is not working, both left and right audio data comes from channel 0. 2 1 FORMAT rx format 0: 16-bit mode 1: 24-bit mode 1 1 ENABLE rx channel 0 enable 0 1 RX_CH0_ENTRY RX_CH0_ENTRY 0x34 0x20 read-write 0x00000000 DATA rx channel 0 data entry 0 32 RX_CH1_CFG RX_CH1_CFG 0x38 0x20 read-write 0x00000000 RSVD 8 24 FIFO_CNT rx fifo counter 4 4 DMA_MSK 1: mask the dma request for rx ch1 3 1 RSVD2 2 1 FORMAT rx format 0: 16-bit mode 1: 24-bit mode 1 1 ENABLE rx channel 1 enable 0 1 RX_CH1_ENTRY RX_CH1_ENTRY 0x3c 0x20 read-write 0x00000000 DATA rx channel 1 data entry 0 32 TX_OUT_CH0_CFG TX_OUT_CH0_CFG 0x40 0x20 read-write 0x00000000 RSVD 8 24 FIFO_CNT tx out fifo counter 4 4 DMA_MSK 1: mask the dma request for tx out ch0 3 1 MODE tx out mode 1'h0: mono mode 1'h1: stereo mode This bit is only used for 16-bit mode, in 24-bit mode, channel can only be set in mono mode. In 16-bit stereo mode, rx channel 1 is not working, both left and right audio data comes from channel 0. 2 1 FORMAT tx out format 0: 16-bit mode 1: 24-bit mode 1 1 ENABLE tx out channel 0 enable 0 1 TX_OUT_CH0_ENTRY TX_OUT_CH0_ENTRY 0x44 0x20 read-write 0x00000000 DATA tx out channel 0 data entry 0 32 TX_OUT_CH1_CFG TX_OUT_CH1_CFG 0x48 0x20 read-write 0x00000000 RSVD 8 24 FIFO_CNT tx out fifo counter 4 4 DMA_MSK 1: mask the dma request for tx out ch1 3 1 RSVD2 2 1 FORMAT tx out format 0: 16-bit mode 1: 24-bit mode 1 1 ENABLE tx out channel 1 enable 0 1 TX_OUT_CH1_ENTRY TX_OUT_CH1_ENTRY 0x4c 0x20 read-write 0x00000000 DATA tx out channel 1 data entry 0 32 DAC_PATH_CFG0 DAC_PATH_CFG0 0x50 0x20 read-write 0x00000000 RSVD 30 2 DST_SEL dac path destination select 2'h0: select audio codec 2'h1: select external interface 2'h2: select apb interface 2'h3: reserved 28 2 MIXRSRC1 dac mixer right channel input source0 select 3'h0:tx ch0 3'h1:tx ch1 3'h2:tx ch2 3'h3:tx ch3 3'h4:mute other: mute 25 3 MIXRSRC0 dac mixer right channel input source0 select 3'h0:tx ch0 3'h1:tx ch1 3'h2:tx ch2 3'h3:tx ch3 3'h4:mute other: mute 22 3 MIXLSRC1 dac mixer left channel input source1 select 3'h0:tx ch0 3'h1:tx ch1 3'h2:tx ch2 3'h3:tx ch3 3'h4:mute other: mute 19 3 MIXLSRC0 dac mixer left channel input source0 select 3'h0:tx ch0 3'h1:tx ch1 3'h2:tx ch2 3'h3:tx ch3 3'h4:mute other: mute 16 3 FINE_VOL_R dac mixer right channel fine volume control range from 0dB to 6dB step is 0.5dB 4'h0: 0dB 4'h1: 0.5dB ...... 4'hb: 5.5dB 4'hc, 4'hd, 4'he, 4'hf: mute 12 4 ROUGH_VOL_R dac mixer right channel rough volume control range from -36dB to 54dB step is 6dB 4'h0: -36dB 4'h1: -30dB ...... 4'h6: 0dB ...... 4'he: 48dB 4'hf: 54dB 8 4 FINE_VOL_L dac mixer left channel fine volume control range from 0dB to 6dB step is 0.5dB 4'h0: 0dB 4'h1: 0.5dB ...... 4'hb: 5.5dB 4'hc, 4'hd, 4'he, 4'hf: mute 4 4 ROUGH_VOL_L dac mixer left channel rough volume control range from -36dB to 54dB step is 6dB 4'h0: -36dB 4'h1: -30dB ...... 4'h6: 0dB ...... 4'he: 48dB 4'hf: 54dB 0 4 DAC_PATH_CFG1 DAC_PATH_CFG1 0x54 0x20 read-write 0x00000000 SRC_CH_CLR clear src channal internal data 30 2 SRC_CH_CLR_DONE src channel internal data clear done 28 2 SRC_HBF3_MODE 3rd stage hbf mode: 0: upsampling 1: downsampling 27 1 SRC_HBF3_EN 3rd stage hbf enable 26 1 SRC_HBF2_MODE 2nd stage hbf mode: 0: upsampling 1: downsampling 25 1 SRC_HBF2_EN 2nd stage hbf enable 24 1 SRC_HBF1_MODE 1st stage hbf mode: 0: upsampling 1: downsampling 23 1 SRC_HBF1_EN 1st stage hbf enable 22 1 SRC_CH_EN source rate converter channel enable 20 2 EQ_CLR equalizer clear request 19 1 EQ_CLR_DONE equalizer clear done flag 18 1 EQ_STAGE set equalizer stage, max is 10. 14 4 EQ_CH_EN equalizer channel enable 2'b11: enable both channel 2'b10: enable right chanel only 2'b01: enable left channel only 2'b00: bypass equalizer 12 2 MUXRSRC1 dac mux right channel input source0 select 3'h0:tx ch0 3'h1:tx ch1 3'h2:rx ch0 3'h3:rx ch1 3'h4:mute other: mute 9 3 MUXRSRC0 dac mux right channel input source0 select 3'h0:tx ch0 3'h1:tx ch1 3'h2:rx ch0 3'h3:rx ch1 3'h4:mute other: mute 6 3 MUXLSRC1 dac mux left channel input source1 select 3'h0:tx ch0 3'h1:tx ch1 3'h2:rx ch0 3'h3:rx ch1 3'h4:mute other: mute 3 3 MUXLSRC0 dac mux left channel input source0 select 3'h0:tx ch0 3'h1:tx ch1 3'h2:rx ch0 3'h3:rx ch1 3'h4:mute other: mute 0 3 DAC_PATH_CFG2 DAC_PATH_CFG2 0x58 0x20 read-write 0x00000000 SRC_SINC_EN sinc filter enable 31 1 SINC_RATIO sinc filter ratio, s31.30 format. Range from 0~2 0 31 DAC_PATH_CFG3 DAC_PATH_CFG3 0x5c 0x20 read-write 0x00000000 RSVD 18 14 RAMP_STAT_R dac mixer right channel ramp module status 16 2 RAMP_INTERVAL_R dac mixer right channel volume ramp interval. 12 4 ZERO_ADJUST_EN_R dac mixer right channel volume adjustment during 0 volume cross enable 11 1 RAMP_MODE_R dac mixer right channel volume ramp mode: 1: slowly ramp to target volume. Step is 0.5db 0: directly ramp to target volume. 10 1 RAMP_EN_R dac mixer right channel volume ramp enable 9 1 RAMP_STAT_L dac mixer left channel ramp module status 7 2 RAMP_INTERVAL_L dac mixer left channel volume ramp interval. 3 4 ZERO_ADJUST_EN_L dac mixer left channel volume adjustment during 0 volume cross enable 2 1 RAMP_MODE_L dac mixer left channel volume ramp mode: 1: slowly ramp to target volume. Step is 0.5db 0: directly ramp to target volume. 1 1 RAMP_EN_L dac mixer left channel volume ramp enable 0 1 ADC_PATH_CFG0 ADC_PATH_CFG0 0x60 0x20 read-write 0x00000000 RSVD 19 13 RX2TX_LOOPBACK rx to tx loopback enable 18 1 DATA_SWAP swap adc path left and right channel data 17 1 SRC_SEL adc path source select 1'h0: select audio codec 1'h1: select external interface 16 1 FINE_VOL_R adc right channel fine volume control range from 0dB to 6dB step is 0.5dB 4'h0: 0dB 4'h1: 0.5dB ...... 4'hb: 5.5dB 4'hc, 4'hd, 4'he, 4'hf: mute 12 4 ROUGH_VOL_R adc right channel rough volume control range from -36dB to 54dB step is 6dB 4'h0: -36dB 4'h1: -30dB ...... 4'h6: 0dB ...... 4'he: 48dB 4'hf: 54dB 8 4 FINE_VOL_L adc left channel fine volume control range from 0dB to 6dB step is 0.5dB 4'h0: 0dB 4'h1: 0.5dB ...... 4'hb: 5.5dB 4'hc, 4'hd, 4'he, 4'hf: mute 4 4 ROUGH_VOL_L adc left channel rough volume control range from -36dB to 54dB step is 6dB 4'h0: -36dB 4'h1: -30dB ...... 4'h6: 0dB ...... 4'he: 48dB 4'hf: 54dB 0 4 RSVD1 RSVD1 0x64 0x20 read-write 0x0 DAC_EQ_CFG0 DAC_EQ_CFG0 0x70 0x20 read-write 0x00000000 RSVD 24 8 COEF 0 24 DAC_EQ_CFG1 DAC_EQ_CFG1 0x74 0x20 read-write 0x00000000 RSVD 24 8 COEF 0 24 DAC_EQ_CFG2 DAC_EQ_CFG2 0x78 0x20 read-write 0x00000000 RSVD 24 8 COEF 0 24 DAC_EQ_CFG3 DAC_EQ_CFG3 0x7c 0x20 read-write 0x00000000 RSVD 24 8 COEF 0 24 DAC_EQ_CFG4 DAC_EQ_CFG4 0x80 0x20 read-write 0x00000000 RSVD 24 8 COEF 0 24 DAC_EQ_CFG5 DAC_EQ_CFG5 0x84 0x20 read-write 0x00000000 RSVD 24 8 COEF 0 24 DAC_EQ_CFG6 DAC_EQ_CFG6 0x88 0x20 read-write 0x00000000 RSVD 24 8 COEF 0 24 DAC_EQ_CFG7 DAC_EQ_CFG7 0x8c 0x20 read-write 0x00000000 RSVD 24 8 COEF 0 24 DAC_EQ_CFG8 DAC_EQ_CFG8 0x90 0x20 read-write 0x00000000 RSVD 24 8 COEF 0 24 DAC_EQ_CFG9 DAC_EQ_CFG9 0x94 0x20 read-write 0x00000000 RSVD 24 8 COEF 0 24 DAC_EQ_CFG10 DAC_EQ_CFG10 0x98 0x20 read-write 0x00000000 RSVD 24 8 COEF 0 24 DAC_EQ_CFG11 DAC_EQ_CFG11 0x9c 0x20 read-write 0x00000000 RSVD 24 8 COEF 0 24 DAC_EQ_CFG12 DAC_EQ_CFG12 0xa0 0x20 read-write 0x00000000 RSVD 24 8 COEF 0 24 DAC_EQ_CFG13 DAC_EQ_CFG13 0xa4 0x20 read-write 0x00000000 RSVD 24 8 COEF 0 24 DAC_EQ_CFG14 DAC_EQ_CFG14 0xa8 0x20 read-write 0x00000000 RSVD 24 8 COEF 0 24 DAC_EQ_CFG15 DAC_EQ_CFG15 0xac 0x20 read-write 0x00000000 RSVD 24 8 COEF 0 24 DAC_EQ_CFG16 DAC_EQ_CFG16 0xb0 0x20 read-write 0x00000000 RSVD 24 8 COEF 0 24 DAC_EQ_CFG17 DAC_EQ_CFG17 0xb4 0x20 read-write 0x00000000 RSVD 24 8 COEF 0 24 DAC_EQ_CFG18 DAC_EQ_CFG18 0xb8 0x20 read-write 0x00000000 RSVD 24 8 COEF 0 24 DAC_EQ_CFG19 DAC_EQ_CFG19 0xbc 0x20 read-write 0x00000000 RSVD 24 8 COEF 0 24 DAC_EQ_CFG20 DAC_EQ_CFG20 0xc0 0x20 read-write 0x00000000 RSVD 24 8 COEF 0 24 DAC_EQ_CFG21 DAC_EQ_CFG21 0xc4 0x20 read-write 0x00000000 RSVD 24 8 COEF 0 24 DAC_EQ_CFG22 DAC_EQ_CFG22 0xc8 0x20 read-write 0x00000000 RSVD 24 8 COEF 0 24 DAC_EQ_CFG23 DAC_EQ_CFG23 0xcc 0x20 read-write 0x00000000 RSVD 24 8 COEF 0 24 DAC_EQ_CFG24 DAC_EQ_CFG24 0xd0 0x20 read-write 0x00000000 RSVD 24 8 COEF 0 24 DAC_EQ_CFG25 DAC_EQ_CFG25 0xd4 0x20 read-write 0x00000000 RSVD 24 8 COEF 0 24 DAC_EQ_CFG26 DAC_EQ_CFG26 0xd8 0x20 read-write 0x00000000 RSVD 24 8 COEF 0 24 DAC_EQ_CFG27 DAC_EQ_CFG27 0xdc 0x20 read-write 0x00000000 RSVD 24 8 COEF 0 24 DAC_EQ_CFG28 DAC_EQ_CFG28 0xe0 0x20 read-write 0x00000000 RSVD 24 8 COEF 0 24 DAC_EQ_CFG29 DAC_EQ_CFG29 0xe4 0x20 read-write 0x00000000 RSVD 24 8 COEF 0 24 DAC_EQ_CFG30 DAC_EQ_CFG30 0xe8 0x20 read-write 0x00000000 RSVD 24 8 COEF 0 24 DAC_EQ_CFG31 DAC_EQ_CFG31 0xec 0x20 read-write 0x00000000 RSVD 24 8 COEF 0 24 DAC_EQ_CFG32 DAC_EQ_CFG32 0xf0 0x20 read-write 0x00000000 RSVD 24 8 COEF 0 24 DAC_EQ_CFG33 DAC_EQ_CFG33 0xf4 0x20 read-write 0x00000000 RSVD 24 8 COEF 0 24 DAC_EQ_CFG34 DAC_EQ_CFG34 0xf8 0x20 read-write 0x00000000 RSVD 24 8 COEF 0 24 DAC_EQ_CFG35 DAC_EQ_CFG35 0xfc 0x20 read-write 0x00000000 RSVD 24 8 COEF 0 24 DAC_EQ_CFG36 DAC_EQ_CFG36 0x100 0x20 read-write 0x00000000 RSVD 24 8 COEF 0 24 DAC_EQ_CFG37 DAC_EQ_CFG37 0x104 0x20 read-write 0x00000000 RSVD 24 8 COEF 0 24 DAC_EQ_CFG38 DAC_EQ_CFG38 0x108 0x20 read-write 0x00000000 RSVD 24 8 COEF 0 24 DAC_EQ_CFG39 DAC_EQ_CFG39 0x10c 0x20 read-write 0x00000000 RSVD 24 8 COEF 0 24 DAC_EQ_CFG40 DAC_EQ_CFG40 0x110 0x20 read-write 0x00000000 RSVD 24 8 COEF 0 24 DAC_EQ_CFG41 DAC_EQ_CFG41 0x114 0x20 read-write 0x00000000 RSVD 24 8 COEF 0 24 DAC_EQ_CFG42 DAC_EQ_CFG42 0x118 0x20 read-write 0x00000000 RSVD 24 8 COEF 0 24 DAC_EQ_CFG43 DAC_EQ_CFG43 0x11c 0x20 read-write 0x00000000 RSVD 24 8 COEF 0 24 DAC_EQ_CFG44 DAC_EQ_CFG44 0x120 0x20 read-write 0x00000000 RSVD 24 8 COEF 0 24 DAC_EQ_CFG45 DAC_EQ_CFG45 0x124 0x20 read-write 0x00000000 RSVD 24 8 COEF 0 24 DAC_EQ_CFG46 DAC_EQ_CFG46 0x128 0x20 read-write 0x00000000 RSVD 24 8 COEF 0 24 DAC_EQ_CFG47 DAC_EQ_CFG47 0x12c 0x20 read-write 0x00000000 RSVD 24 8 COEF 0 24 DAC_EQ_CFG48 DAC_EQ_CFG48 0x130 0x20 read-write 0x00000000 RSVD 24 8 COEF 0 24 DAC_EQ_CFG49 DAC_EQ_CFG49 0x134 0x20 read-write 0x00000000 RSVD 24 8 COEF 0 24 RESERVED_IN RESERVED_IN 0x138 0x20 read-write 0x00000000 RSVD 24 8 CTRL_2 reserved control 2 16 8 CTRL_1 reserved control 1 8 8 CTRL_0 reserved control 0 0 8 RESERVED_OUT RESERVED_OUT 0x13c 0x20 read-write 0x00000000 RSVD 8 24 STAT reserved status 0 8 EZIP1 EZIP 0x50006000 0x0 0x1000 registers EZIP_CTRL EZIP_CTRL ezip/aezip_frame decoder ctrl 0x000 0x20 read-write 0x00000000 RSVD 1 31 EZIP_CTRL 1:start or run 0:stop or end 0 1 SRC_ADDR SRC_ADDR ezip decoder source address 0x004 0x20 read-write 0x00000000 SRC_ADDR ezip decoder source address 0 32 DST_ADDR DST_ADDR ezip decoder destination address 0x008 0x20 read-write 0x00000000 DST_ADDR ezip decoder destination address(ahb_out mode) 0 32 EZIP_PARA EZIP_PARA ezip decoder parameter 0x00c 0x20 read-write 0x00000000 RSVD 6 26 SPI_SEL 0:QSPI4 1:QSPI3 5 1 IN_SEL don't support ezip type2\type4. 0:ahb 1:fifo 4 1 CACHE_EN no used 3 1 MOD_SEL 0:ezip or aezip 1:gzip 2:Lz4 1 2 OUT_SEL only used in ezip decoder mode. must select ahb in gzip/lz4 decoder mode. 0:epic 1:ahb 0 1 CACHE_CLR CACHE_CLR ezip index cache clear 0x010 0x20 read-write 0x00000000 RSVD 1 31 CACHE_CLR no used 0 1 START_POINT START_POINT ezip decoder start point 0x014 0x20 read-write 0x00000000 START_COL ezip start col,count from 0 16 16 START_ROW ezip start row,count from 0 0 16 END_POINT END_POINT ezip decoder end point 0x018 0x20 read-write 0x00000000 END_COL ezip end col 16 16 END_ROW ezip end row 0 16 ROW_SIGN ROW_SIGN ezip decoder row sign 0x01c 0x20 read-write 0x00000000 RSVD 16 16 ROW_SIGN arrived row sign,ezip can generate a interrupt 0 16 INT_EN INT_EN ezip decoder _int_en 0x020 0x20 read-write 0x00000000 RSVD 6 26 AEZIP_INT_EN aezip_frame_int_en 5 1 ETYPE_ERR_EN ezip_type_err_en 4 1 BTYPE_ERR_EN btype_err_en 3 1 ROW_ERR_EN row_err_en 2 1 ROW_INT_EN row_int_en 1 1 END_INT_EN ezip_end _int_en 0 1 INT_STA INT_STA ezip decoder _int_sta 0x024 0x20 read-write 0x00000000 RSVD 6 26 AEZIP_INT_STA aezip_end_int_sta 5 1 ETYPE_ERR_STA ezip_type_err_sta 4 1 BTYPE_ERR_STA btype_err_sta 3 1 ROW_ERR_STA overflow height sta 2 1 ROW_INT_STA arrive row sign sta 1 1 END_INT_STA ezip_end _int_sta/aezip_frame_int_sta 0 1 INT_MASK INT_MASK ezip decoder int mask state 0x028 0x20 read-write 0x00000000 RSVD 6 26 AEZIP_INT_MASK aezip_end_int_mask sta 5 1 ETYPE_ERR_MASK ezip_type_err_mask sta 4 1 BTYPE_ERR_MASK btype_err_mask sta 3 1 ROW_ERR_MASK overflow height mask sta 2 1 ROW_INT_MASK arrive row sign mask sta 1 1 END_INT_MASK ezip_end _int mask sta/aezip_frame_int_mask_Sta 0 1 NAP_PARA NAP_PARA ezip decoder release bus parameter 0x02c 0x20 read-write 0x00000000 RSVD 8 24 BURST_NUM ezip decoder burst number 0000: 16 0001: 32 0010: 64 0100: 128 1000: 256 other: 16 4 4 NAP_TIM ezip decoder release bus time 0000: not nap 0001: 16 cycle 0010: 32 cycle 0100: 64 cycle 1000: 128 cycle other: not nap 0 4 SRC_LEN SRC_LEN ezip source data length 0x030 0x20 read-write 0x00000000 SRC_LEN source data byte length only in source data fifo mode 0 32 AEZIP_CTRL AEZIP_CTRL AEZIP ctrl 0x034 0x20 read-write 0x00000000 RSVD 1 31 AEZIP_CTRL AEZIP ctrl 0 1 FRAME_START FRAME_START Aezip start number of frames 0x038 0x20 read-write 0x00000000 FRAME_START start number of frames,count from 1 0 32 PLAY_START PLAY_START Aezip start number of play 0x03c 0x20 read-write 0x00000000 PLAY_START start number of times to loop this AEZIP,,count from 1 0 32 FRAME_NUM FRAME_NUM Aezip number of frames 0x040 0x20 read-write 0x00000000 FRAME_NUM number of frames 0 32 PLAY_NUM PLAY_NUM Aezip number of times to loop this AEZIP 0x044 0x20 read-write 0x00000000 PLAY_NUM number of times to loop this AEZIP,0 indicates infinite looping 0 32 SEQ_NUM SEQ_NUM Aezip sequence number 0x048 0x20 read-write 0x00000000 SEQ_NUM sequence number of the animation chunk,starting from 0 0 32 FRAME_AREA FRAME_AREA Aezip frame area 0x04c 0x20 read-write 0x00000000 FRAME_WIDTH AEZIP frame width 16 16 FRAME_HEIGHT AEZIP frame height 0 16 FRAME_OFFSET FRAME_OFFSET Aezip frame area 0x050 0x20 read-write 0x00000000 OFFSET_COL AEZIP frame offset col 16 16 OFFEST_ROW AEZIP frame offset row 0 16 FRAME_DELAY FRAME_DELAY Aezip frame delay 0x054 0x20 read-write 0x00000000 DELAY_NUM AEZIP frame delay fraction numerator 16 16 DELAY_DEN AEZIP frame delay fraction denominator 0 16 FRAME_TYPE FRAME_TYPE 0x058 0x20 read-write 0x00000000 RSVD 16 16 DISPOSE_OP AEZIP type of frame area disposal to be done after rendering this frame 8 8 BLEND_OP AEZIP type of frame area renndering for this frame 0 8 FRAME_SIZE FRAME_SIZE Aezip frame size 0x05c 0x20 read-write 0x00000000 FRAME_SIZE frame size 0 32 GREY_PARA GREY_PARA 0x060 0x20 read-write 0x00000000 RSVD 24 8 GREY_PARA fill color parameter, when send grey data to epic . [23:16]-R,[15:8]-G,[7:0]-B 0 24 DB_SEL DB_SEL ezip decoder debug sel 0x064 0x20 read-write 0x00000000 RSVD 16 16 DB_SEL bit[15] 0:line_first 1:out_buf_en[1] bit[14] 0:rd_head3 1:out_buf_en[0] bit[13] 0:rd_head2 1:inbuf_empty bit[12] 0:rd_heas1 1:inbuf_half_empty bit[11] 0:blk_restart 1: inbuf_full bit[10] 0:ezip_buf_end 1:ezip_pixel_end bit[9] 0:ezip_buf_full 1:0 bit[8] 0:ezip_buf_empty 1:0 bit[7] 0:dec_buf_empty 1:0 bit[6] 0:dec_buf_full 1:para_ok bit[5] 0:dec_on 1:ezip_fuf_push bit[4] 0:ind3_on 1:copy_on bit[3] 0:ind2_on 1:bypass_on bit[2] 0:ind1_on 1:blk_clr bit[1] 0:ezip_on 1:para_val bit[0] 0:ezip_int 1:para_req 0 16 DB_DATA0 DB_DATA0 ezip decoder debug data0 0x068 0x20 read-write 0x00000000 DB_DATA0 bit[31:24] bit_depth bit[23:16] color_type bit[15:0] block number 0 32 DB_DATA1 DB_DATA1 ezip decoder debug data1 0x06c 0x20 read-write 0x00000000 DB_DATA1 bit[31:16] width bit[15:0] height 0 32 DB_DATA2 DB_DATA2 ezip decoder debug data2 0x070 0x20 read-write 0x00000000 DB_DATA2 bit[31:0] total_len 0 32 DB_DATA3 DB_DATA3 ezip decoder debug data3 0x074 0x20 read-write 0x00000000 DB_DATA3 bit[31:24] ezip_type bit[23:20] bfinal bit[19:16] btype bit[11:8] ahb_state bit[7:4] ctrl_state bir[3:0] build_stste 0 32 DB_DATA4 DB_DATA4 ezip decoder debug data4 0x078 0x20 read-write 0x00000000 DB_DATA4 bit[9]:ezip_buf_full bit[8]:ezip_buf_empty bit[7]:dec_buf_full bit[6]:dec_buf_empty bit[5]:bypass_on bit[4]:dec_on bit[3]:ind3_on bit[2]:ind2_on bit[1]:ind1_on bit[0]:ezip_on 0 32 DB_DATA5 DB_DATA5 ezip decoder debug data5 0x07c 0x20 read-write 0x00000000 DB_DATA5 bit[31:16] width_cnt_cur bit[15:0] height_cnt_cur 0 32 DB_DATA6 DB_DATA6 ezip decoder debug data6 0x080 0x20 read-write 0x00000000 DB_DATA6 seq_num 0 32 DB_DATA7 DB_DATA7 ezip decoder debug data7 0x084 0x20 read-write 0x00000000 DB_DATA7 bit[31:16] frame_width_cur bit[15:0] frame_height_cur 0 32 DB_DATA8 DB_DATA8 ezip decoder debug data8 0x088 0x20 read-write 0x00000000 DB_DATA8 bit[31:16 ]frame_offsetx_cur bit[15:0] frame_offsety_cur 0 32 DB_DATA9 DB_DATA9 ezip decoder debug data9 0x08c 0x20 read-write 0x00000000 DB_DATA9 bit[31:16 ]delay_num_cur bit[15:0] delay_den_cur 0 32 DB_DATA10 DB_DATA10 ezip decoder debug data10 0x090 0x20 read-write 0x00000000 DB_DATA10 bit[15:8 dispos_op_cur bit[7:0] blend_op_cur 0 32 DB_DATA11 DB_DATA11 ezip decoder debug data11 0x094 0x20 read-write 0x00000000 DB_DATA11 frame_cont_cur 0 32 DB_DATA12 DB_DATA12 ezip decoder debug data12 0x098 0x20 read-write 0x00000000 DB_DATA12 paly_cont_cur 0 32 DB_DATA13 DB_DATA13 ezip decoder debug data13 0x09c 0x20 read-write 0x00000000 DB_DATA13 frame_size_cur 0 32 EPIC EPIC 0x50007000 0x0 0x1000 registers COMMAND COMMAND 0x00 0x20 read-write 0x00000000 RSVD 2 30 RESET 1: reset the whole graphics 0: release the reset 1 1 START write 1 to trigger the lcd interface block 0 1 STATUS STATUS 0x04 0x20 read-write 0x00000000 RSVD 5 27 LCD_BUSY LCD controll busy flag 4 1 RSVD2 1 3 IA_BUSY Graphics accelerator busy flag 0 1 EOF_IRQ EOF_IRQ 0x08 0x20 read-write 0x00000000 RSVD 18 14 LINE_HIT_STATUS raw status of line hit interrupt 17 1 IRQ_STATUS raw status of end of frame interrupt 16 1 RSVD2 2 14 LINE_HIT_CAUSE line hit interrupt, can be masked by LINE_IRQ_MASK 1 1 IRQ_CAUSE end of frame interrupt, can be masked by EOF_IRQ_MASK 0 1 SETTING SETTING 0x0c 0x20 read-write 0x00000000 RSVD 26 6 LINE_IRQ_NUM canvas line hit interrupt line number 16 10 RSVD2 3 13 AUTO_GATE_EN auto clock gating enable 2 1 LINE_IRQ_MASK canvas line hit interrupt mask, 0: mask the interrupt 1 1 EOF_IRQ_MASK end of frame interrupt mask, 0: mask the interrupt 0 1 CANVAS_TL_POS CANVAS_TL_POS Top-Left pixel coordinate 0x10 0x20 read-write 0x00000000 RSVD 26 6 Y0 16 10 RSVD2 10 6 X0 0 10 CANVAS_BR_POS CANVAS_BR_POS Bottom-Right pixel coordinate 0x14 0x20 read-write 0x00000000 RSVD 26 6 Y1 16 10 RSVD2 10 6 X1 0 10 CANVAS_BG CANVAS_BG Background color 0x18 0x20 read-write 0x00000000 RSVD 26 6 ALL_BLENDING_BYPASS if this bit is set, epic is in pure dma mode. No blending operation. 25 1 BG_BLENDING_BYPASS if this bit is set, the layer is not blending with background. The alpha value will be reserved to output. 24 1 RED Red color 16 8 GREEN green color 8 8 BLUE blue color 0 8 VL_CFG VL_CFG 0x1c 0x20 read-write 0x00000000 ALPHA_BLEND set 1 to enable alpha blending mode. Use layer alpha as blending factor for image with Alpha. Alpha_out = Layer_alpha * Image_alpha 31 1 ACTIVE layer active flag 30 1 PREFETCH_EN preload 64 bytes extra data when reading pixel from memory 29 1 WIDTH source image width(including padding), unit is bytes 16 13 FILTER_EN layer color filter enable 15 1 BLEND_DEPTH video layer blending depth 13 2 ALPHA layer alpha value 5 8 ALPHA_SEL alpha selection 1'b0: select alpha according to image format 1'b1: select layer alpha 4 1 FORMAT video layer input format 4'h0: RGB565 4'h1: RGB888 4'h2: ARGB8888 4'h3: ARGB8565 4'h4: A8 4'h5: A4 4'h6: L8 4'h7: A2 0 4 VL_TL_POS VL_TL_POS 0x20 0x20 read-write 0x00000000 RSVD 26 6 Y0 Coordingate Y-value 16 10 RSVD2 10 6 X0 Coordinate X-value 0 10 VL_BR_POS VL_BR_POS 0x24 0x20 read-write 0x00000000 RSVD 26 6 Y1 Coordingate Y-value 16 10 RSVD2 10 6 X1 Coordinate X-value 0 10 VL_EXTENTS VL_EXTENTS 0x28 0x20 read-write 0x00000000 RSVD 26 6 MAX_COL number of pixels of each line of source image(not including padding) 16 10 RSVD2 10 6 MAX_LINE number of pixels of each column of source image(not including padding) 0 10 VL_FILTER VL_FILTER 0x2c 0x20 read-write 0x00000000 FILTER_MASK layer color filter mask 24 8 FILTER_R filter r color 16 8 FILTER_G filter g color 8 8 FILTER_B filter b color 0 8 VL_SRC VL_SRC 0x30 0x20 read-write 0x00000000 ADDR source image RGB data address[31:0]. For RGB565 format, address should be aligned to halfword. For ARGB8888 format, address should be aligned to word. 0 32 VL_ROT VL_ROT 0x34 0x20 read-write 0x00000000 RSVD 12 20 CALC_DONE calculation done indicator 11 1 ROT_DEG rotation degree, rotation is clockwise. 2 9 CALC_CLR rot_max_col and rot_max_line calculation clear request. Write 1 to clear the result. 1 1 CALC_REQ rot_max_col and rot_max_line calculation request. Write 1 to trigger the calculation. 0 1 VL_ROT_STAT VL_ROT_STAT 0x38 0x20 read-write 0x00000000 RSVD 27 5 ROT_MAX_COL max column of rotated image 16 11 RSVD2 11 5 ROT_MAX_LINE max line of rotated image 0 11 VL_SCALE_RATIO_H VL_SCALE_RATIO_H 0x3c 0x20 read-write 0x00000000 RSVD 26 6 XPITCH x-axis rescaling ration, 10.16 fixed point number, XPITCH lt MAX_COL/(X1-X0) 0 26 VL_SCALE_RATIO_V VL_SCALE_RATIO_V 0x40 0x20 read-write 0x00000000 RSVD 26 6 YPITCH y-axis rescaling ratio, 10.16 fixed point number, YPITCH lt MAX_LINE/(Y1-Y0) 0 26 VL_FILL VL_FILL 0x44 0x20 read-write 0x00000000 RSVD 26 6 ENDIAN input 565 data format endian 0: {R[4:0], G[5:3], G[2:0], B[4:0]} 1: {G[2:0], R[4:0], B[4:0], G[5:3]} 25 1 BG_MODE Not used. 24 1 BG_R background r color 16 8 BG_G background g color 8 8 BG_B background b color 0 8 VL_MISC_CFG VL_MISC_CFG 0x48 0x20 read-write 0x00000000 RSVD 30 2 DEG_FORCE force epic use external sin and cos value, quadrant is still calculated from ROT_DEG. 29 1 SIN_FORCE_VALUE external absolute value of sin. U13.12 format. 16 13 COS_FORCE_VALUE external absolute value of cos. U13.12 format. 3 13 H_MIRROR horizontal mirror enable 2 1 V_MIRROR vertical mirror enable 1 1 CLUT_SEL VL CLUT select: 1'h1: select pallette1 1'h0: select pallette0 0 1 RSVD4 RSVD4 0x4C 0x20 read-write 0x0 L0_CFG L0_CFG 0x50 0x20 read-write 0x00000000 ALPHA_BLEND set 1 to enable alpha blending mode. Use layer alpha as blending factor for image with Alpha. Alpha_out = Layer_alpha * Image_alpha 31 1 ACTIVE layer active flag 30 1 PREFETCH_EN preload 64 bytes extra data when reading pixel from memory 29 1 WIDTH source image width(including padding), unit is bytes 16 13 FILTER_EN layer color filter enable 15 1 RSVD 13 2 ALPHA layer alpha value 5 8 ALPHA_SEL alpha selection 1'b0: select alpha according to image format 1'b1: select layer alpha 4 1 FORMAT layer input format 4'h0: RGB565 4'h1: RGB888 4'h2: ARGB8888 4'h3: ARGB8565 4'h4: A8 4'h5: A4 4'h6: L8 4'h7: A2 0 4 L0_TL_POS L0_TL_POS 0x54 0x20 read-write 0x00000000 RSVD 26 6 Y0 Coordingate Y-value 16 10 RSVD2 10 6 X0 Coordinate X-value 0 10 L0_BR_POS L0_BR_POS 0x58 0x20 read-write 0x00000000 RSVD 26 6 Y1 Coordingate Y-value 16 10 RSVD2 10 6 X1 Coordinate X-value 0 10 L0_FILTER L0_FILTER 0x5c 0x20 read-write 0x00000000 FILTER_MASK layer color filter mask 24 8 FILTER_R filter r color 16 8 FILTER_G filter g color 8 8 FILTER_B filter b color 0 8 L0_SRC L0_SRC 0x60 0x20 read-write 0x00000000 ADDR source image RGB data address[31:0]. For RGB565 format, address should be aligned to halfword. For ARGB8888 format, address should be aligned to word. 0 32 L0_FILL L0_FILL 0x64 0x20 read-write 0x00000000 RSVD 26 6 ENDIAN input 565 data format endian 0: {R[4:0], G[5:3], G[2:0], B[4:0]} 1: {G[2:0], R[4:0], B[4:0], G[5:3]} 25 1 BG_MODE Not used. 24 1 BG_R background r color 16 8 BG_G background g color 8 8 BG_B background b color 0 8 L0_MISC_CFG L0_MISC_CFG 0x68 0x20 read-write 0x00000000 RSVD 2 30 V_MIRROR vertical mirror enable 1 1 CLUT_SEL L0 CLUT select: 1'h1: select pallette1 1'h0: select pallette0 0 1 RSVD3 RSVD3 0x6C 0x20 read-write 0x0 L1_CFG L1_CFG 0x70 0x20 read-write 0x00000000 ALPHA_BLEND set 1 to enable alpha blending mode. Use layer alpha as blending factor for image with Alpha. Alpha_out = Layer_alpha * Image_alpha 31 1 ACTIVE layer active flag 30 1 PREFETCH_EN preload 64 bytes extra data when reading pixel from memory 29 1 WIDTH source image width(including padding), unit is bytes 16 13 FILTER_EN layer color filter enable 15 1 RSVD 13 2 ALPHA layer alpha value 5 8 ALPHA_SEL alpha selection 1'b0: select alpha according to image format 1'b1: select layer alpha 4 1 FORMAT layer input format 4'h0: RGB565 4'h1: RGB888 4'h2: ARGB8888 4'h3: ARGB8565 4'h4: A8 4'h5: A4 4'h6: L8 4'h7: A2 0 4 L1_TL_POS L1_TL_POS 0x74 0x20 read-write 0x00000000 RSVD 26 6 Y0 Coordingate Y-value 16 10 RSVD2 10 6 X0 Coordinate X-value 0 10 L1_BR_POS L1_BR_POS 0x78 0x20 read-write 0x00000000 RSVD 26 6 Y1 Coordingate Y-value 16 10 RSVD2 10 6 X1 Coordinate X-value 0 10 L1_FILTER L1_FILTER 0x7c 0x20 read-write 0x00000000 FILTER_MASK layer color filter mask 24 8 FILTER_R filter r color 16 8 FILTER_G filter g color 8 8 FILTER_B filter b color 0 8 L1_SRC L1_SRC 0x80 0x20 read-write 0x00000000 ADDR source image RGB data address[31:0]. For RGB565 format, address should be aligned to halfword. For ARGB8888 format, address should be aligned to word. 0 32 L1_FILL L1_FILL 0x84 0x20 read-write 0x00000000 RSVD 26 6 ENDIAN input 565 data format endian 0: {R[4:0], G[5:3], G[2:0], B[4:0]} 1: {G[2:0], R[4:0], B[4:0], G[5:3]} 25 1 BG_MODE Not used. 24 1 BG_R background r color 16 8 BG_G background g color 8 8 BG_B background b color 0 8 L1_MISC_CFG L1_MISC_CFG 0x88 0x20 read-write 0x00000000 RSVD 2 30 V_MIRROR vertical mirror enable 1 1 CLUT_SEL L1 CLUT select: 1'h1: select pallette1 1'h0: select pallette0 0 1 RSVD2 RSVD2 0x8C 0x20 read-write 0x0 L2_CFG L2_CFG 0x90 0x20 read-write 0x00000000 ALPHA_BLEND set 1 to enable alpha blending mode. Use layer alpha as blending factor for image with Alpha. Alpha_out = Layer_alpha * Image_alpha 31 1 ACTIVE layer active flag 30 1 PREFETCH_EN preload 64 bytes extra data when reading pixel from memory 29 1 WIDTH source image width(including padding), unit is bytes 16 13 FILTER_EN layer color filter enable 15 1 RSVD 13 2 ALPHA layer alpha value 5 8 ALPHA_SEL alpha selection 1'b0: select alpha according to image format 1'b1: select layer alpha 4 1 FORMAT layer input format 4'h0: RGB565 4'h1: RGB888 4'h2: ARGB8888 4'h3: ARGB8565 4'h4: A8 4'h5: A4 4'h6: L8 4'h7: A2 0 4 L2_TL_POS L2_TL_POS 0x94 0x20 read-write 0x00000000 RSVD 26 6 Y0 Coordingate Y-value 16 10 RSVD2 10 6 X0 Coordinate X-value 0 10 L2_BR_POS L2_BR_POS 0x98 0x20 read-write 0x00000000 RSVD 26 6 Y1 Coordingate Y-value 16 10 RSVD2 10 6 X1 Coordinate X-value 0 10 L2_EXTENTS L2_EXTENTS 0x9c 0x20 read-write 0x00000000 RSVD 26 6 MAX_COL number of pixels of each line of source image(not including padding) 16 10 RSVD2 10 6 MAX_LINE number of pixels of each column of source image(not including padding) 0 10 L2_FILTER L2_FILTER 0xa0 0x20 read-write 0x00000000 FILTER_MASK layer color filter mask 24 8 FILTER_R filter r color 16 8 FILTER_G filter g color 8 8 FILTER_B filter b color 0 8 L2_SRC L2_SRC 0xa4 0x20 read-write 0x00000000 ADDR source image RGB data address[31:0]. For RGB565 format, address should be aligned to halfword. For ARGB8888 format, address should be aligned to word. 0 32 L2_ROT L2_ROT 0xa8 0x20 read-write 0x00000000 RSVD 12 20 CALC_DONE calculation done indicator 11 1 ROT_DEG rotation degree, rotation is clockwise. 2 9 CALC_CLR rot_max_col and rot_max_line calculation clear request. Write 1 to clear the result. 1 1 CALC_REQ rot_max_col and rot_max_line calculation request. Write 1 to trigger the calculation. 0 1 L2_ROT_STAT L2_ROT_STAT 0xac 0x20 read-write 0x00000000 RSVD 27 5 ROT_MAX_COL max column of rotated image 16 11 RSVD2 11 5 ROT_MAX_LINE max line of rotated image 0 11 L2_SCALE_RATIO_H L2_SCALE_RATIO_H 0xb0 0x20 read-write 0x00000000 RSVD 26 6 XPITCH x-axis rescaling ration, 10.16 fixed point number, XPITCH lt MAX_COL/(X1-X0) 0 26 L2_SCALE_RATIO_V L2_SCALE_RATIO_V 0xb4 0x20 read-write 0x00000000 RSVD 26 6 YPITCH y-axis rescaling ratio, 10.16 fixed point number, YPITCH lt MAX_LINE/(Y1-Y0) 0 26 L2_FILL L2_FILL 0xb8 0x20 read-write 0x00000000 RSVD 26 6 ENDIAN input 565 data format endian 0: {R[4:0], G[5:3], G[2:0], B[4:0]} 1: {G[2:0], R[4:0], B[4:0], G[5:3]} 25 1 BG_MODE Not used. 24 1 BG_R background r color 16 8 BG_G background g color 8 8 BG_B background b color 0 8 L2_MISC_CFG L2_MISC_CFG 0xbc 0x20 read-write 0x00000000 RSVD 30 2 DEG_FORCE force epic use external sin and cos value, quadrant is still calculated from ROT_DEG. 29 1 SIN_FORCE_VALUE external absolute value of sin. U13.12 format. 16 13 COS_FORCE_VALUE external absolute value of cos. U13.12 format. 3 13 H_MIRROR horizontal mirror enable 2 1 V_MIRROR vertical mirror enable 1 1 CLUT_SEL L2 CLUT select: 1'h1: select pallette1 1'h0: select pallette0 0 1 MASK_CFG MASK_CFG 0xc0 0x20 read-write 0x00000000 RSVD 29 3 ACTIVE layer active flag 28 1 PREFETCH_EN preload 64 bytes extra data when reading pixel from memory 27 1 WIDTH source image width(including padding), unit is bytes 14 13 RSVD2 6 8 VL_MASK_EN video layer mask enable 5 1 L2_MASK_EN layer2 mask enable 4 1 L1_MASK_EN layer1 mask enable 3 1 L0_MASK_EN layer0 mask enable 2 1 MIX_MODE mask mix mode 1'h0: mult mode 1'h1: overwrite mode 1 1 FORMAT mask input format 1'h0: A8 1'h1: A4 0 1 MASK_TL_POS MASK_TL_POS 0xc4 0x20 read-write 0x00000000 RSVD 26 6 Y0 Coordingate Y-value 16 10 RSVD2 10 6 X0 Coordinate X-value 0 10 MASK_BR_POS MASK_BR_POS 0xc8 0x20 read-write 0x00000000 RSVD 26 6 Y1 Coordingate Y-value 16 10 RSVD2 10 6 X1 Coordinate X-value 0 10 MASK_SRC MASK_SRC 0xcc 0x20 read-write 0x00000000 ADDR mask data address[31:0]. This is byte address, even for A4, this address is byte aligned. 0 32 COENG_CFG COENG_CFG 0xd0 0x20 read-write 0x00000000 RSVD 6 26 YUV_CH_SEL yuv engine channel select 4 2 YUV_EN yuv enable 3 1 EZIP_CH_SEL ezip channel select 1 2 EZIP_EN ezip enable 0 1 YUV_ENG_CFG0 YUV_ENG_CFG0 0xd4 0x20 read-write 0x00000000 RSVD 30 2 RANGE_SEL yuv input range 1'h0: tv range 1'h1: pc range 29 1 FORMAT yuv format 26 3 WIDTH_Y yuv y vector line width, unit is bytes 13 13 WIDTH_U yuv u vector line width, unit is bytes 0 13 YUV_ENG_CFG1 YUV_ENG_CFG1 0xd8 0x20 read-write 0x00000000 RSVD 13 19 WIDTH_V yuv v vector line width, unit is bytes 0 13 Y_SRC Y_SRC 0xdc 0x20 read-write 0x00000000 ADDR y vector address 0 32 U_SRC U_SRC 0xe0 0x20 read-write 0x00000000 ADDR u vector address 0 32 V_SRC V_SRC 0xe4 0x20 read-write 0x00000000 ADDR v vector address 0 32 COEF0 COEF0 0xe8 0x20 read-write 0x00000000 RSVD 30 2 FY YUV Fy coef 20 10 FUG YUV Fug coef 10 10 FUB YUV Fub coef 0 10 COEF1 COEF1 0xec 0x20 read-write 0x00000000 RSVD 20 12 FVR YUV Fvr coef 10 10 FVG YUV Fvg coef 0 10 DITHER_CONF DITHER_CONF 0xf0 0x20 read-write 0x00000000 RSVD 13 19 LFSR_LOAD load lfsr init value 12 1 LFSR_LOAD_SEL select lfsr 0: none 1: red 2: green 3: blue 10 2 W_R red dither width 7 3 W_G green dither width 4 3 W_B blue dither width 1 3 EN dither enable 0 1 DITHER_LFSR DITHER_LFSR 0xf4 0x20 read-write 0x00000000 INIT_VAL lfsr init load value 0 32 AHB_CTRL AHB_CTRL 0xf8 0x20 read-write 0x00000000 RSVD 3 29 O_FORMAT AHB output format: 2'h0: RGB565 2'h1: RGB888 2'h2: ARGB8888 2'h3: ARGB8565 1 2 DESTINATION The Data can be sent to two destinations: 2'b0: AHB RAM 2'b1: AHB LCD 0 1 AHB_MEM AHB_MEM 0xfc 0x20 read-write 0x00000000 ADDR AHB RAM/AHB LCD target address 0 32 AHB_STRIDE AHB_STRIDE 0x100 0x20 read-write 0x00000000 RSVD 16 16 OFFSET 0 16 DEBUG DEBUG 0x104 0x20 read-write 0x00000000 DEBUG_INT_DATA 4'h0: RSVD 4'h1: OL0 debug info 4'h2: OL1 debug info 4'h3: OL2 debug info 4'h4: VL debug info1 4'h5: VL debug info2 4'h6: ROI debug out 4'h7: mem intfa debug out 4'h8: mem intfb debug out 4'h9: ahb ctrl debug out 4'ha: ROI XX 4'hb: ROI YY 4'hc: EPIC_EZIP debug out others: RSVD 16 16 RSVD 8 8 DEBUG_INT_SEL 4 4 DEBUG_OUT_SEL 0 4 VL_ROT_M_CFG1 VL_ROT_M_CFG1 0x108 0x20 read-write 0x00000000 M_MODE rotation mode setting 1'b0: auto mode 1'b1: manual mode 31 1 RSVD 27 4 M_ROT_MAX_COL manual mode rotation max column, unsigned value 16 11 RSVD2 11 5 M_ROT_MAX_LINE manual mode rotation max line, unsigned value 0 11 VL_ROT_M_CFG2 VL_ROT_M_CFG2 0x10c 0x20 read-write 0x00000000 RSVD 27 5 M_PIVOT_Y manual mode pivot y, signed value, -1023~1023, -1024 is not supported 16 11 RSVD2 11 5 M_PIVOT_X manual mode pivot x, signed value, -1023~1023, -1024 is not supported 0 11 VL_ROT_M_CFG3 VL_ROT_M_CFG3 0x110 0x20 read-write 0x00000000 RSVD 27 5 M_YTL manual mode top left y cordinate, signed value, -1023~1023, -1024 is not supported 16 11 RSVD2 11 5 M_XTL manual mode top left x cordinate, signed value, -1023~1023, -1024 is not supported 0 11 VL_SCALE_INIT_CFG1 VL_SCALE_INIT_CFG1 0x114 0x20 read-write 0x00000000 RSVD 26 6 X_VAL x-axis scale initial value, 10.16 format 0 26 VL_SCALE_INIT_CFG2 VL_SCALE_INIT_CFG2 0x118 0x20 read-write 0x00000000 RSVD 26 6 Y_VAL y-axis scale initial value, 10.16 format 0 26 L2_ROT_M_CFG1 L2_ROT_M_CFG1 0x11c 0x20 read-write 0x00000000 M_MODE rotation mode setting 1'b0: auto mode 1'b1: manual mode 31 1 RSVD 27 4 M_ROT_MAX_COL manual mode rotation max column, unsigned value 16 11 RSVD2 11 5 M_ROT_MAX_LINE manual mode rotation max line, unsigned value 0 11 L2_ROT_M_CFG2 L2_ROT_M_CFG2 0x120 0x20 read-write 0x00000000 RSVD 27 5 M_PIVOT_Y manual mode pivot y, signed value, -1023~1023, -1024 is not supported 16 11 RSVD2 11 5 M_PIVOT_X manual mode pivot x, signed value, -1023~1023, -1024 is not supported 0 11 L2_ROT_M_CFG3 L2_ROT_M_CFG3 0x124 0x20 read-write 0x00000000 RSVD 27 5 M_YTL manual mode top left y cordinate, signed value, -1023~1023, -1024 is not supported 16 11 RSVD2 11 5 M_XTL manual mode top left x cordinate, signed value, -1023~1023, -1024 is not supported 0 11 L2_SCALE_INIT_CFG1 L2_SCALE_INIT_CFG1 0x128 0x20 read-write 0x00000000 RSVD 26 6 X_VAL x-axis scale initial value, 10.16 format 0 26 L2_SCALE_INIT_CFG2 L2_SCALE_INIT_CFG2 0x12c 0x20 read-write 0x00000000 RSVD 26 6 Y_VAL y-axis scale initial value, 10.16 format 0 26 PERF_CNT PERF_CNT 0x130 0x20 read-write 0x00000000 VAL epic performance counter 0 32 RSVD1 RSVD1 0x134 0x20 read-write 0x0 CANVAS_STAT CANVAS_STAT 0x140 0x20 read-write 0x00000000 FETCH_STAT fetch status 29 3 PREC_STAT prec status 26 3 POSTC_STAT postc_status 23 3 FIFO_CNT pre calc fifo count 20 3 Y_COR canvas y cordinate 10 10 X_COR canvas x cordinate 0 10 EZIP_STAT EZIP_STAT 0x144 0x20 read-write 0x00000000 RSVD 31 1 RUN_STAT1 ezip engine 1 status 28 3 BUF_CNT1 ezip engine 1 buffer count 26 2 LINE_CNT1 ezip engine 1 line count 16 10 RSVD2 15 1 RUN_STAT0 ezip engine 0 status 12 3 BUF_CNT0 ezip engine 0 buffer count 10 2 LINE_CNT0 ezip engine 0 line count 0 10 OL_STAT OL_STAT 0x148 0x20 read-write 0x00000000 RSVD 28 4 PF_PR1 25 3 PF_DF1 23 2 DATA_CONV1 21 2 PREFETCH_READ1 19 2 PREFETCH_OUT1 18 1 PREFETCH_HOLD1 17 1 DONE_REQ1 16 1 RSVD2 12 4 PF_PR0 9 3 PF_DF0 7 2 DATA_CONV0 5 2 PREFETCH_READ0 3 2 PREFETCH_OUT0 2 1 PREFETCH_HOLD0 1 1 DONE_REQ0 0 1 OL2_STAT OL2_STAT 0x14c 0x20 read-write 0x00000000 RSVD 27 5 SC_LB0 25 2 SC_LB1 23 2 SC_FE 19 4 SC_BE 16 3 SC_OUT 14 2 NF_DATA_CONV 12 2 NF_DF 10 2 NF_PR 7 3 RF_ROT 3 4 PREFETCH_READ 1 2 PREFETCH_OUT 0 1 VL_STAT VL_STAT 0x150 0x20 read-write 0x00000000 RSVD 27 5 SC_LB0 25 2 SC_LB1 23 2 SC_FE 19 4 SC_BE 16 3 SC_OUT 14 2 NF_DATA_CONV 12 2 NF_DF 10 2 NF_PR 7 3 RF_ROT 3 4 PREFETCH_READ 1 2 PREFETCH_OUT 0 1 ML_STAT ML_STAT 0x154 0x20 read-write 0x00000000 RSVD 10 22 MF_PR 7 3 MF_DF 5 2 PREFETCH_READ 3 2 PREFETCH_OUT 2 1 PREFETCH_HOLD 1 1 DONE_REQ 0 1 MEM_IF_STAT MEM_IF_STAT 0x158 0x20 read-write 0x00000000 AHB_CTRL_FIFO_CNT 24 8 AHB_CTRL_EOL 23 1 AHB_CTRL 20 3 ARB_MAIN1 17 3 ARB_READ_PORT1 14 3 AHB1 10 4 ARB_MAIN0 7 3 ARB_READ_PORT0 4 3 AHB0 0 4 LCDC1 LCDC 0x50008000 0x0 0x1000 registers COMMAND COMMAND 0x00 0x20 read-write 0x00000000 RSVD 2 30 RESET 1: reset the whole graphics 0: release the reset 1 1 START write 1 to trigger the lcd interface block 0 1 STATUS STATUS 0x04 0x20 read-write 0x00000000 RSVD 3 29 JDI_PAR_RUN JDI parallel interface is running 2 1 DPI_RUN DPI interface is running 1 1 LCD_BUSY LCS controll busy flag 0 1 IRQ IRQ 0x08 0x20 read-write 0x00000000 RSVD 23 9 LINE_DONE_RAW_STAT raw_status of line process done interrupt 22 1 JDI_PAR_UDR_RAW_STAT raw_status of jdi parallel interface under run interrupt 21 1 JDI_PARL_INTR_RAW_STAT raw_status of jdi parallel interface line interrupt 20 1 DPI_UDR_RAW_STAT raw status of dpi under run interrupt 19 1 DPIL_INTR_RAW_STAT raw status of dpi line interrupt 18 1 ICB_OF_RAW_STAT raw status of icb overflow interrupt 17 1 EOF_RAW_STAT raw status of end of frame interrupt 16 1 RSVD2 7 9 LINE_DONE_STAT line process done interrupt, masked by mask register 6 1 JDI_PAR_UDR_STAT jdi parallel interface under run interrupt, masked by mask register 5 1 JDI_PARL_INTR_STAT jdi parallel interface line interrupt, masked by mask register 4 1 DPI_UDR_STAT dpi under run interrupt, masked by mask register 3 1 DPIL_INTR_STAT dpi line interrupt, masked by mask register 2 1 ICB_OF_STAT icb overflow interrupt, masked by mask register 1 1 EOF_STAT end of frame interrupt, masked by mask register 0 1 SETTING SETTING 0x0c 0x20 read-write 0x00000000 RSVD 27 5 LINE_DONE_NUM line number of line process done interrupt 16 11 RSVD2 9 7 AUTO_GATE_EN auto clock gating enable 8 1 RSVD3 7 1 LINE_DONE_MASK line process done interrupt, 0: mask the interrupt 6 1 JDI_PAR_UDR_MASK jdi parallel interface under run interrupt mask, 0: mask the interrupt 5 1 JDI_PARL_INTR_MASK jdi parallel interface line interrupt, 0: mask the interrupt 4 1 DPI_UDR_MASK dpi under run interrupt mask, 0: mask the interrupt 3 1 DPIL_INTR_MASK dpi line interrupt, 0: mask the interrupt 2 1 ICB_OF_MASK icb overflow interrupt mask, 0: mask the interrupt 1 1 EOF_MASK end of frame interrupt mask, 0: mask the interrupt 0 1 CANVAS_TL_POS CANVAS_TL_POS 0x10 0x20 read-write 0x00000000 RSVD 27 5 Y0 16 11 RSVD2 11 5 X0 0 11 CANVAS_BR_POS CANVAS_BR_POS 0x14 0x20 read-write 0x00000000 RSVD 27 5 Y1 16 11 RSVD2 11 5 X1 0 11 CANVAS_BG CANVAS_BG 0x18 0x20 read-write 0x00000000 RSVD 28 4 H_MIRROR set 1 to do horizontal mirror for output image 27 1 LB_BYPASS line buffer bypass. Set 1 to bypass line buffer. 26 1 ALL_BLENDING_BYPASS if this bit is set, lcdc is in pure dma mode. No blending operation. 25 1 BG_BLENDING_BYPASS if this bit is set, the layer is not blending with background. The alpha value will be reserved to output. 24 1 RED Red color 16 8 GREEN green color 8 8 BLUE blue color 0 8 LAYER0_CONFIG LAYER0_CONFIG 0x1c 0x20 read-write 0x00000000 RSVD 31 1 V_MIRROR set 1 to do vertical mirror for the layer 30 1 ALPHA_BLEND set 1 to enable alpha blending mode. Use layer alpha as blending factor for image with Alpha. Alpha_out = Layer_alpha * Image_alpha 29 1 ACTIVE layer active flag 28 1 LINE_FETCH_MODE line fetch mode 0: address skip every single line 1: address skip every two line 27 1 PREFETCH_EN preload 64 bytes extra data when reading pixel from memory 26 1 WIDTH source image width(including padding), unit is bytes 13 13 FILTER_EN layer color filter enable 12 1 ALPHA layer alpha value 4 8 ALPHA_SEL alpha selection 1'b0: select alpha according to image format 1'b1: select layer alpha 3 1 FORMAT overlay layer input format 3'h0: RGB565 3'h1: RGB888 3'h2: ARGB8888 3'h3: ARGB8565 3'h4: RGB332 3'h5: A8 3'h6: L8 others: reserved 0 3 LAYER0_TL_POS LAYER0_TL_POS 0x20 0x20 read-write 0x00000000 RSVD 27 5 Y0 Coordingate Y-value 16 11 RSVD2 11 5 X0 Coordinate X-value 0 11 LAYER0_BR_POS LAYER0_BR_POS 0x24 0x20 read-write 0x00000000 RSVD 27 5 Y1 Coordingate Y-value 16 11 RSVD2 11 5 X1 Coordinate X-value 0 11 LAYER0_FILTER LAYER0_FILTER 0x28 0x20 read-write 0x00000000 FILTER_MASK layer color filter mask 24 8 FILTER_R filter r color 16 8 FILTER_G filter g color 8 8 FILTER_B filter b color 0 8 LAYER0_SRC LAYER0_SRC 0x2c 0x20 read-write 0x00000000 ADDR source image RGB data address[31:0]. For RGB565 format, address should be aligned to halfword. For ARGB8888 format, address should be aligned to word. 0 32 LAYER0_FILL LAYER0_FILL 0x30 0x20 read-write 0x00000000 RSVD 26 6 ENDIAN input 565 data format endian 0: {R[4:0], G[5:3], G[2:0], B[4:0]} 1: {G[2:0], R[4:0], B[4:0], G[5:3]} 25 1 BG_MODE not used 24 1 BG_R background r color 16 8 BG_G background g color 8 8 BG_B background b color 0 8 LAYER0_DECOMP LAYER0_DECOMP 0x34 0x20 read-write 0x00000000 RSVD 24 8 COL_SIZE number of colums in a line of original image, max column size is 1024 13 11 TARGET_WORDS size of a single channel data before decompression. Unit is half word. Each line has 3 channels. So for each line, the compressed data size is target_words * 3 * 2 bytes. 1 12 ENABLE decompression enable 0 1 LAYER0_DECOMP_CFG0 LAYER0_DECOMP_CFG0 0x38 0x20 read-write 0x01055982 CFG0_RESERVED 20 12 LOSSLESS_QIDX2 condition to decrease qidx 16 4 LOSSLESS_QIDX1 up level for adjusted qidx value for low quality block 12 4 USE_LOSSLESS_QIDX condition to increase qidx 8 4 EXTRA_THRESHOLD the threshold to distinguish high/low quality block 4 4 EXTRA_HIGH extra bit for high quality bit 0 4 LAYER0_DECOMP_CFG1 LAYER0_DECOMP_CFG1 0x3c 0x20 read-write 0x80023307 EXTRA_LOW extra bit for low quality block 28 4 BLOCK_MIN_QIDX minimum qidx for block mode 24 4 LINE_MIN_QIDX minimum qidx for line mode 20 4 FAILOVER_BITS_B failover compression mode target bits(Blue) 16 4 FAILOVER_BITS_G failover compression mode target bits(Green) 12 4 FAILOVER_BITS_R failover compression mode target bits(Red) 8 4 CFG1_RESERVED 2 6 DITHER dithering function 0: off 1: on 1 1 BLOCK_WIDTH block_size in pixel unit. 0: 16 pixels 1: 32 pixels Small block size will cause more blocks and more bits to store block information. 0 1 LAYER0_DECOMP_STAT LAYER0_DECOMP_STAT 0x40 0x20 read-write 0x00000000 RSVD 7 25 BUF_MAX_DEPTH buf max usage 0 7 RSVD2 RSVD2 0x44 0x20 read-write 0x0 LAYER1_CONFIG LAYER1_CONFIG 0x60 0x20 read-write 0x00000000 RSVD 31 1 V_MIRROR set 1 to do vertical mirror for the layer 30 1 ALPHA_BLEND set 1 to enable alpha blending mode. Use layer alpha as blending factor for image with Alpha. Alpha_out = Layer_alpha * Image_alpha 29 1 ACTIVE layer active flag 28 1 LINE_FETCH_MODE line fetch mode 0: address skip every single line 1: address skip every two line 27 1 PREFETCH_EN preload 64 bytes extra data when reading pixel from memory 26 1 WIDTH source image width(including padding), unit is bytes 13 13 FILTER_EN layer color filter enable 12 1 ALPHA layer alpha value 4 8 ALPHA_SEL alpha selection 1'b0: select alpha according to image format 1'b1: select layer alpha 3 1 FORMAT overlay layer input format 3'h0: RGB565 3'h1: RGB888 3'h2: ARGB8888 3'h3: ARGB8565 3'h4: RGB332 3'h5: A8 3'h6: L8 others: reserved 0 3 LAYER1_TL_POS LAYER1_TL_POS 0x64 0x20 read-write 0x00000000 RSVD 27 5 Y0 Coordingate Y-value 16 11 RSVD2 11 5 X0 Coordinate X-value 0 11 LAYER1_BR_POS LAYER1_BR_POS 0x68 0x20 read-write 0x00000000 RSVD 27 5 Y1 Coordingate Y-value 16 11 RSVD2 11 5 X1 Coordinate X-value 0 11 LAYER1_FILTER LAYER1_FILTER 0x6c 0x20 read-write 0x00000000 FILTER_MASK layer color filter mask 24 8 FILTER_R filter r color 16 8 FILTER_G filter g color 8 8 FILTER_B filter b color 0 8 LAYER1_SRC LAYER1_SRC 0x70 0x20 read-write 0x00000000 ADDR source image RGB data address[31:0]. For RGB565 format, address should be aligned to halfword. For ARGB8888 format, address should be aligned to word. 0 32 LAYER1_FILL LAYER1_FILL 0x74 0x20 read-write 0x00000000 RSVD 26 6 ENDIAN input 565 data format endian 0: {R[4:0], G[5:3], G[2:0], B[4:0]} 1: {G[2:0], R[4:0], B[4:0], G[5:3]} 25 1 BG_MODE not used 24 1 BG_R background r color 16 8 BG_G background g color 8 8 BG_B background b color 0 8 DITHER_CONF DITHER_CONF 0x78 0x20 read-write 0x00000000 RSVD 13 19 LFSR_LOAD load lfsr init value 12 1 LFSR_LOAD_SEL select lfsr 0: none 1: red 2: green 3: blue 10 2 W_R red dither width 7 3 W_G green dither width 4 3 W_B blue dither width 1 3 EN dither enable 0 1 DITHER_LFSR DITHER_LFSR 0x7c 0x20 read-write 0x00000000 INIT_VAL lfsr init load value 0 32 LCD_CONF LCD_CONF 0x80 0x20 read-write 0x00000000 RSVD 21 11 SPI_RD_SEL spi read line select. 0: select line 0 1: select line 1 2: select line 2 3: select line 3 19 2 ENDIAN LCD 565 data format endian, this bit would affect SPI, DPI, DBI and AHB interface 565 format 0: {R[4:0], G[5:3], G[2:0], B[4:0]} 1: {G[2:0], R[4:0], B[4:0], G[5:3]} 18 1 DIRECT_INTF_EN when the target LCD is AHB LCD, this bit enable the direct interface to DSI module. Direct interface has higher bandwidth and speed than AHB interface. 17 1 JDI_SER_FORMAT JDI serial format 2'b00: 3-bit mode 2'b01: 4-bit mode 2'b10: 1-bit mode 2'b11: reserved 15 2 DPI_LCD_FORMAT DPI LCD format 3'b000: 16-bit conf1 3'b001: 16-bit conf2 3'b010: 16-bit conf3 3'b011: 18-bit conf1 3'b100: 18-bit conf2 3'b101: 24-bit others: Reserved 12 3 SPI_LCD_FORMAT SPI LCD format 2'b00: 8-bit RGB 3:3:2 2'b01: 16-bit RGB 5:6:5 2'b10: 24-bit RGB 8:8:8 2'b11: Reserved 10 2 AHB_FORMAT AHB LCD/RAM output format: 0: RGB565 1: RGB888 2: ARGB8888 3: RGB332 8 2 LCD_FORMAT LCD output format: 3'b000: 8-bit RGB 3:3:2 3'b001: 16-bit RGB 5:6:5 over 8-bit bus, 2 cycles/pixel 3'b010: 12-bit RGB 4:4:4 3'b011: 16-bit RGB 5:6:5 3'b100: 18-bit RGB 6:6:6 3'b101: 24-bit RGB 8:8:8 3'b110: 24-bit RGB 8:8:8 over 16-bit bus, 1.5 cycles/pixel 3'b111: 24-bit RGB 8:8:8 over 8-bit bus, 3cycles/pixel others: Reserved 5 3 LCD_INTF_SEL 3'b000: 8080 DBI Type B 3'b001: SPI interface 3'b010: DBI to DSI interface 3'b011: DPI interface 3'b100: JDI serial interface 3'b101: JDI parallel interface 3'b110: 8080 DBI Type A 3'b111: DPI to DSI interface 2 3 TARGET_LCD The Data can be sent to four destinations: 2'b00: LCD panel 0 2'b01: LCD panel 1 2'b10: AHB LCD 2'b11: AHB RAM 0 2 LCD_IF_CONF LCD_IF_CONF 0x84 0x20 read-write 0x00000000 RSVD 26 6 CTRL_DLY_SET if this bit is set to 1, LCD control output will be delayed for 1 lcdc clock cycle 25 1 DO_DLY_SET if this bit is set to 1, LCD data output will be delayed for 1 lcdc clock cycle 24 1 LCD_RSTB LCD RSTB pin, direct to output 23 1 RD_POL LCD RD pin polarity. RD is 0 for write operation, 1 for idle if polarity bit is set as 0. RD bit definition is opposite if polarity bit is set as 1. 22 1 WR_POL LCD WR pin polarity. WR is 0 for write operation, 1 for idle if polarity bit is set as 0. WR bit definition is opposite if polarity bit is set as 1. 21 1 RS_POL LCD RS pin polarity. RS is 1 for data access, 0 for command access if polarity bit is set as 0. RS bit definition is opposite if polarity bit is set as 1. 20 1 CS1_POL LCD0 CS pin polarity. CS is 0 for LCD chip select if polarity bit is set as 0. CS bit definition is opposite if polarity bit is set as 1. 19 1 CS0_POL LCD1 CS pin polarity. CS is 0 for LCD chip select if polarity bit is set as 0. CS bit definition is opposite if polarity bit is set as 1. 18 1 PWH inactive cycles of LCD_WR/LCD_RD for consecutive write/read operation 12 6 PWL active cycles of LCD_WR/LCD_RD 6 6 TAH hold cycles, delay from LCD_WR/LCD_RD inactive to LCD_CS inactive 3 3 TAS setup cycles, delay from LCD_CS active to LCD_WR/LCD_RD active 0 3 LCD_MEM LCD_MEM 0x88 0x20 read-write 0x00000000 ADDR address for AHB LCD/AHB RAM 0 32 LCD_O_WIDTH LCD_O_WIDTH 0x8c 0x20 read-write 0x00000000 RSVD 16 16 OFFSET AHB RAM address offset for each line 0 16 LCD_SINGLE LCD_SINGLE 0x90 0x20 read-write 0x00000000 RSVD 4 28 LCD_BUSY LCD/SPI LCD interface is busy for single access 3 1 RD_TRIG Single read operation trigger 2 1 WR_TRIG Single write operation trigger 1 1 TYPE LCD access type, this bit could affect all LCD interface including SPI, parellel and AHB 1'b0: command 1'b1: data 0 1 LCD_WR LCD_WR 0x94 0x20 read-write 0x00000000 DATA LCD write data 0 32 LCD_RD LCD_RD 0x98 0x20 read-write 0x00000000 DATA LCD read data 0 32 SPI_IF_CONF SPI_IF_CONF 0x9c 0x20 read-write 0x00000000 RSVD 31 1 SPI_CLK_INIT SPI CLK idle state value 1'h0: high 1'h1: low 30 1 SPI_CLK_POL SPI CLK polarity 1'h0: normal 1'h1: inverted 29 1 SPI_CS_POL SPI CS polarity 0: low active 1: high active 28 1 SPI_CS_AUTO_DIS 1: SPI CS is automatically disabled after data transaction 0: SPI CS is not disabled after data transaction 27 1 SPI_CS_NO_IDLE 1: SPI CS is always active during data transaction 0: SPI CS is IDLE in wait state during data transaction 26 1 SPI_CLK_AUTO_DIS 1: SPI clock auto disable in wait state during data transaction 0: SPI clock is always on in wait state during data transaction 25 1 SPI_RD_MODE SPI read mode: 1'b0: normal read. Send write request before read. 1'b1: direct read. Read data without write request. 24 1 WR_LEN SPI write data length(single access) 22 2 RD_LEN SPI read data length(single access) 20 2 LINE SPI line mode 0: 4-line 1: 4-line with 2 data line(support RGB565 and RGB888) 2: 4-line with 4 data line(support RGB565 and RGB888) 3: reserved 4: 3-line 5: 3-line with 2 data line(support RGB565 and RGB888) 6: 3-line with 4 data line(support RGB565 and RGB888) 7: reserved 17 3 DUMMY_CYCLE SPI transaction dummy cycle 14 3 CLK_DIV SPI clock divider 6 8 WAIT_CYCLE SPI line wait cycle, wait cycle is after each line and is according to SPI clock. 0 refers to no wait cycle. 0 6 TE_CONF TE_CONF 0xa0 0x20 read-write 0x00000000 RSVD 21 11 FMARK_SOURCE TE signal source 1: use TE signal from DSI 0: use TE signal from external pin 20 1 FMARK_MODE TE signal trigger mode 1: edge trigger 0: pulse trigger 19 1 VSYNC_DET_CNT vsync signal detect counter, used for mode 1 to detect vsync signal 3 16 MODE 0: vsync only TE mode 1: vsync+hsync TE mode 2 1 FMARK_POL TE signal polarity 1 1 ENABLE TE enable 0 1 TE_CONF2 TE_CONF2 0xa4 0x20 read-write 0x00000000 DLY_CNT TE delay counter 0 32 DPI_IF_CONF1 DPI_IF_CONF1 0xa8 0x20 read-write 0x00000000 RSVD 27 5 HSW dpi hsync width 16 11 RSVD2 11 5 VSH dpi vsync height 0 11 DPI_IF_CONF2 DPI_IF_CONF2 0xac 0x20 read-write 0x00000000 RSVD 27 5 HBP horizontal back porch 16 11 RSVD2 11 5 VBP vertical back porch 0 11 DPI_IF_CONF3 DPI_IF_CONF3 0xb0 0x20 read-write 0x00000000 RSVD 27 5 HFP horizontal front porch 16 11 RSVD2 11 5 VFP vertical front porch 0 11 DPI_IF_CONF4 DPI_IF_CONF4 0xb4 0x20 read-write 0x00000000 RSVD 27 5 HAW horizontal active width 16 11 RSVD2 11 5 VAH vertical active height 0 11 DPI_IF_CONF5 DPI_IF_CONF5 0xb8 0x20 read-write 0x00000000 RSVD 24 8 CLK_FORCE_ON 1: force DPI clock on 0: DPI clock is controlled by hardware 23 1 INT_LINE_NUM DPI interrupt line number 12 11 HSPOL hsync polarity 11 1 VSPOL vsync polarity 10 1 DEPOL de polarity 9 1 PCLKPOL pixel clock polarity 8 1 PCLK_DIV pixel clock divider 0 8 DPI_CTRL DPI_CTRL 0xbc 0x20 read-write 0x00000000 RSVD 4 28 DPI_UC dpi update config 3 1 DPI_SD dpi shutdown 2 1 DPI_CM dpi color mode 1 1 DPI_EN dpi interface enable 0 1 DPI_STAT DPI_STAT 0xc0 0x20 read-write 0x00000000 VPOS dpi vertical position 16 16 RSVD 14 2 HSTAT horizontal status 0: idle 1: prep 2: hsync 3: hbp 4: hact 5: hfp 6: wait 11 3 HPOS dpi horizontal position 0 11 JDI_SER_CONF1 JDI_SER_CONF1 0xc4 0x20 read-write 0x00000000 RSVD 16 16 CLK_DIV jdi serial clock divider 8 8 RSVD2 5 3 WR_LEN jdi single write bit length 0 5 JDI_SER_CONF2 JDI_SER_CONF2 0xc8 0x20 read-write 0x00000000 INIT_LINE_CNT jdi serial init line counter 16 16 WR_CMD jdi serial data transfer write command 0 16 JDI_SER_CTRL JDI_SER_CTRL 0xcc 0x20 read-write 0x00000000 RSVD 2 30 EXTCOMIN jdi serial interface extcomin control 1 1 DISP jdi serial interface disp control 0 1 JDI_PAR_CONF1 JDI_PAR_CONF1 0xd0 0x20 read-write 0x00000000 MAX_LINE jdi parallel interface max line, line number start from 0 16 16 MAX_COL jdi parallel interface max column, column number start from 0 0 16 JDI_PAR_CONF2 JDI_PAR_CONF2 0xd4 0x20 read-write 0x00000000 ST_LINE jdi parallel interface start line, line number start from 0 16 16 END_LINE jdi parallel interface end line, line number start from 0 0 16 JDI_PAR_CONF3 JDI_PAR_CONF3 0xd8 0x20 read-write 0x00000000 ST_COL jdi parallel interface start column, column number start from 0 16 16 END_COL jdi parallel interface end column, column number start from 0 0 16 JDI_PAR_CONF4 JDI_PAR_CONF4 0xdc 0x20 read-write 0x00000000 HCK_WIDTH jdi parallel interface HCK width, HSK width = lcd_ck_cycle * HCK_WIDTH 16 16 HST_WIDTH jdi parallel interface HST width, HST width = lcd_ck_cycle * HST_WIDTH 0 16 JDI_PAR_CONF5 JDI_PAR_CONF5 0xe0 0x20 read-write 0x00000000 VCK_WIDTH jdi parallel interface VCK width, VCK width = lcd_ck_cycle * VCK_WIDTH 16 16 VST_WIDTH jdi parallel interface VST width, VST width = lcd_ck_cycle * VST_WIDTH 0 16 JDI_PAR_CONF6 JDI_PAR_CONF6 0xe4 0x20 read-write 0x00000000 VCK_DLY jdi parallel interface VST to VCK delay, VST2VCK delay = lcd_ck_cycle * VCK_DLY 16 16 HST_DLY jdi parallel interface VCK to HST delay, VCK2HST delay = lcd_ck_cycle * HST_DLY 0 16 JDI_PAR_CONF7 JDI_PAR_CONF7 0xe8 0x20 read-write 0x00000000 RSVD 17 15 DP_MODE double pixel mode. Some jdi parallel screens use large pixel+small pixel structure. Set this bit to 1 to support this structure. 16 1 HCK_DLY jdi parallel interface HST to HCK delay 0 16 JDI_PAR_CTRL JDI_PAR_CTRL 0xec 0x20 read-write 0x00000000 INT_LINE_NUM jdi parallel interface interrupt line number, line number start from 0. 16 16 RSVD 10 6 VSTPOL jdi parallel vst polarity 9 1 VCKPOL jdi parallel vck polarity 8 1 HSTPOL jdi parallel hst polarity 7 1 HCKPOL jdi parallel hck polarity 6 1 ENBPOL jdi parallel enb polarity 5 1 XRST jdi parallel interface XRST 4 1 RSVD2 1 3 ENABLE jdi parallel interface enable 0 1 JDI_PAR_STAT JDI_PAR_STAT 0xf0 0x20 read-write 0x00000000 VPOS jdi parallel vertical position 16 16 HPOS jdi parallel horizontal position 0 16 JDI_PAR_EX_CTRL JDI_PAR_EX_CTRL 0xf4 0x20 read-write 0x00000000 VCOM VCOM value 31 1 FRP FRP value 30 1 XFRP XFRP value 29 1 CNT_EN VCOM/FRP/XFRP counter enable 28 1 RSVD 24 4 MAX_CNT VCOM/FRP/XFRP max counter 0 24 JDI_PAR_CONF8 JDI_PAR_CONF8 0xf8 0x20 read-write 0x00000000 ENB_ST_COL jdi parallel interface enb start column, column number start from 0 16 16 ENB_END_COL jdi parallel interface enb end column, column number start from 0 0 16 JDI_PAR_CONF9 JDI_PAR_CONF9 0xfc 0x20 read-write 0x00000000 ENB_ST_LINE jdi parallel interface enb start line, line number start from 0 16 16 ENB_END_LINE jdi parallel interface enb end line, line number start from 0 0 16 JDI_PAR_CONF10 JDI_PAR_CONF10 0x100 0x20 read-write 0x00000000 HC_ST_LINE jdi parallel interface horizontal control start line, line number start from 0 16 16 HC_END_LINE jdi parallel interface horizontal control end line, line number start from 0 0 16 RSVD1 RSVD1 0x104 0x20 read-write 0x0 CANVAS_STAT0 CANVAS_STAT0 0x110 0x20 read-write 0x00000000 RSVD 27 5 Y_COR canvas y cordinate 16 11 RSVD2 11 5 X_COR canvas x cordinate 0 11 CANVAS_STAT1 CANVAS_STAT1 0x114 0x20 read-write 0x00000000 RSVD 12 20 FETCH_STAT fetch status 9 3 PREC_STAT prec status 6 3 POSTC_STAT postc_status 3 3 FIFO_CNT pre calc fifo count 0 3 OL0_STAT OL0_STAT 0x118 0x20 read-write 0x00000000 RSVD 24 8 SC_LB0 22 2 SC_LB1 20 2 SC_FE 16 4 SC_BE 13 3 SC_OUT 11 2 PF_PR 8 3 PF_DF 6 2 DATA_CONV 4 2 PREFETCH_READ 2 2 PREFETCH_OUT 1 1 DONE_REQ 0 1 OL1_STAT OL1_STAT 0x11c 0x20 read-write 0x00000000 RSVD 11 21 PF_PR 8 3 PF_DF 6 2 DATA_CONV 4 2 PREFETCH_READ 2 2 PREFETCH_OUT 1 1 DONE_REQ 0 1 MEM_IF_STAT MEM_IF_STAT 0x120 0x20 read-write 0x00000000 RSVD 10 22 ARB_MAIN 7 3 ARB_READ_PORT 4 3 AHB 0 4 PERF_CNT PERF_CNT 0x124 0x20 read-write 0x00000000 VAL lcdc performance counter 0 32 I2S1 I2S 0x50009000 0x0 0x1000 registers RSVD41 RSVD41 0x0 0x20 read-write 0x0 TX_PCM_FORMAT TX_PCM_FORMAT 0x10 0x20 read-write 0x00000010 RSVD 6 26 TRACK_FLAG 0: stereo 1: mono 5 1 DW tx source pcm data width N(N>=8) common value is 8,13,14,16,18,20,22,24 This data width indicate the tx fifo output data width. When writing to tx fifo, please refer to following format: Mono 8 bit: fifo_data[31:0] = {L3,L2,L1,L0}, each word contains 4 samples, so four samples need read one word Stereo 8 bit: fifo_data[31:0] = { R1,L1,R0,L0 }, each word contains 2 samples, so two samples need read one word Mono 13/14/16 bit: fifo_data[31:0] = {L1,L0}, each word contains 2 samples, so two samples need read one word Stereo 13/14/16 bit: fifo_data[31:0] = {R0,L0}, each word contains 1 samples, so each sample need read one word Mono 18/20/22/24 bit: fifo_data[31:0] = L0, each word contains 1 samples, so each sample need read one word Stereo 18/20/22/24 bit: fifo_data[31:0][0] = {L0}, fifo_data[31:0][1]={R0}, each 2 words contain 1 samples, so each sample need read two word 0 5 RSVD40 RSVD40 0x14 0x20 read-write 0x0 TX_PCM_SAMPLE_CLK TX_PCM_SAMPLE_CLK 0x20 0x20 read-write 0x000000FA RSVD 13 19 FS_DUTY source PCM sample clock duty cycle(with GCLK=12MHz): 250 for 48K FS 272 for 44.1K FS 375 for 32K FS 500 for 24K FS 544 for 22.05K FS 750 for 16K FS 1000 for 12K FS 1088 for 11.025K FS 1500 for 8K FS 0 13 RSVD39 RSVD39 0x24 0x20 read-write 0x0 TX_RS_SMOOTH TX_RS_SMOOTH 0x30 0x20 read-write 0x00000000 RSVD 1 31 EN 0: Disable TX re-sample smooth filter 1: Enable TX re-sample smooth filter This function is not implemented. 0 1 RSVD38 RSVD38 0x34 0x20 read-write 0x0 TX_PCM_CH_SEL TX_PCM_CH_SEL 0x40 0x20 read-write 0x00000000 RSVD 4 28 LEFT_CHANNEL_SEL TX re-sampling module setting: 00: TX left = source left 01: TX left = source right 10,11: TX left = (source left + source right)/2 2 2 RIGHT_CHANNEL_SEL TX re-sampling module setting: 00: TX right = source right 01: TX right = source left 10,11: TX right = (source left + source right)/2 0 2 RSVD37 RSVD37 0x44 0x20 read-write 0x0 TX_VOL_CTRL TX_VOL_CTRL 0x50 0x20 read-write 0x0000000F RSVD 4 28 VOL volume control: 0000: +6dB, 0001: +4.5dB, 0010: +3dB, 0011: +1.5dB, 0100: 0dB, 0101: -1.5dB, 0110: -3.0dB, 0111: -4.5dB, 1000: -6.0dB, 1001: -7.5dB, 1010: -9dB, 1011: -10.5dB, 1100: -12dB, 1101: -13.5dB, 1110: -15dB, 1111: mute Note: 1) +1.5db = 20log(1+1/4-1/16+1/1024) 2) -1.5dB = 20log(1-1/8-1/32-1/512-1/2048) 0 4 RSVD36 RSVD36 0x54 0x20 read-write 0x0 TX_LR_BAL_CTRL TX_LR_BAL_CTRL 0x60 0x20 read-write 0x00000000 RSVD 6 26 EN LR balance enable: 00: both left and right in full volume 10: left channel balance volume adjustment enable 01: right channel balance volume adjustment enable 11: reserved, still kepp left and right in full volume 4 2 BAL_VOL Balance volume control: 0000: Reserved, 0001: -1.5dB, 0010: -3.0dB, 0011: -4.5dB, 0100: -6.0dB, 0101: -7.5dB, 0110: -9.0dB, 0111: -10.5dB, 1000: -12dB, 1001: -13.5dB, 1010: -15dB, 1011: -16.5dB, 1100: -18dB, 1101: -19.5dB, 1110: -21dB, 1111: mute Note: 1) bit[5:0] = 101111 for left mute 2) bit[5:0] = 011111 for right mute 3) bit[5:4] = 00 or 11, bit[3:0] is don't care 4) +1.5db = 20log(1+1/4-1/16+1/1024) 5) -1.5dB = 20log(1-1/8-1/32-1/512-1/2048) 0 4 RSVD35 RSVD35 0x64 0x20 read-write 0x0 AUDIO_TX_LRCK_DIV AUDIO_TX_LRCK_DIV 0x70 0x20 read-write 0x007D007D RSVD 28 4 DUTY_HIGH TX LRCK duty cycle high: 125 for 48K FS 136 for 44.1K FS 185 for 32K FS 250 for 24K FS 272 for 22.05K FS 375 for 16K FS 500 for 12K FS 544 for 11.025K FS 750 for 8K FS 16 12 RSVD2 12 4 DUTY_LOW TX LRCK duty cycle low: 125 for 48K FS 136 for 44.1K FS 190 for 32K FS 250 for 24K FS 272 for 22.05K FS 375 for 16K FS 500 for 12K FS 544 for 11.025K FS 750 for 8K FS Note: 1)duty_cycle = 12M/FS 0 12 RSVD34 RSVD34 0x74 0x20 read-write 0x0 AUDIO_TX_BCLK_DIV AUDIO_TX_BCLK_DIV 0x80 0x20 read-write 0x00000000 RSVD 6 26 DUTY TX serial bit clock duty cycle 5 for 48K FS 4 for 44.1K FS 5 for 32KFS 10 for 24K FS 8 for 22.05K FS 15 for 16K FS 20 for 12K FS 16 for 11.025K FS 30 for 8KFs 0 6 RSVD33 RSVD33 0x84 0x20 read-write 0x0 AUDIO_TX_FORMAT AUDIO_TX_FORMAT 0x90 0x20 read-write 0x00000000 RSVD 5 27 PCM_DATA_WIDTH I2S out pcm data width M >= 16, common value: 16, 18, 20, 22, 24 0 5 RSVD32 RSVD32 0x94 0x20 read-write 0x0 AUDIO_SERIAL_TIMING AUDIO_SERIAL_TIMING 0xa0 0x20 read-write 0x00000000 RSVD 4 28 LRCK_POL TX LRCK polarity control. 0: disable TX_LRCK inventor 1: enable TX_LRCK inventor for standard I2S, set tx_lrck_pol to low for Left/Right Justified, set tx_lrck_pol to hgih 3 1 SLAVE_EN audio code transmit mode select. 0: master mode, 1: slave mode 2 1 TIMING 00: I2S mode 01: Left justified 10: right justified 11: reserved 0 2 RSVD31 RSVD31 0xA4 0x20 read-write 0x0 AUDIO_TX_FUNC_EN AUDIO_TX_FUNC_EN 0xb0 0x20 read-write 0x00000000 RSVD 2 30 TX_INTF_SEL 1: select external tx interface 0: select internal apb tx interface 1 1 TX_EN 1: enable 0:disable 0 1 RSVD30 RSVD30 0xB4 0x20 read-write 0x0 AUDIO_TX_PAUSE AUDIO_TX_PAUSE 0xc0 0x20 read-write 0x00000000 RSVD 1 31 TX_PAUSE TX pause control when tx_enable = 1. 1: pause 0: TX work 0 1 RSVD29 RSVD29 0xC4 0x20 read-write 0x0 AUDIO_I2S_SL_MERGE AUDIO_I2S_SL_MERGE 0xc8 0x20 read-write 0x00000000 RSVD 1 31 SLAVE_TIMING_MERGE when work as an I2S slave, and external I2S master TX/RX share an only BCLK/LRCK, we need set this bit high. 0: I2S slave use separated timing control port. TX_BCLK_IN/TX_LRCK_IN and RX_BCLK/RX_LRCK_IN are separated. 1: I2S slave use the same BCLK/LRCK, the TX_BCLK_IN/TX_LRCK also is used for RX controller. 0 1 RSVD28 RSVD28 0xCC 0x20 read-write 0x0 AUDIO_RX_FUNC_EN AUDIO_RX_FUNC_EN 0x100 0x20 read-write 0x00000000 RSVD 2 30 RX_INTF_SEL 1: select external rx interface 0: select internal apb rx interface 1 1 RX_EN 1: enable 0: disable 0 1 RSVD27 RSVD27 0x104 0x20 read-write 0x0 AUDIO_RX_PAUSE AUDIO_RX_PAUSE 0x110 0x20 read-write 0x00000000 RSVD 1 31 RX_PAUSE RX pause control when rx_enable = 1. 1: pause 0: RX work 0 1 RSVD26 RSVD26 0x114 0x20 read-write 0x0 AUDIO_RX_SERIAL_TIMING AUDIO_RX_SERIAL_TIMING 0x120 0x20 read-write 0x00040000 RSVD 4 28 LRCK_POL RX LRCK polarity control. 0: disable RX_LRCK inventor 1: enable RX_LRCK inventor for standard I2S, set tx_lrck_pol to low for Left/Right Justified, set tx_lrck_pol to hgih 3 1 SLAVE_EN audio code receiver mode select. 0: master mode, 1: slave mode 2 1 TIMING 00: I2S 01: Left justified 10: right justified 11: reserved 0 2 RSVD25 RSVD25 0x124 0x20 read-write 0x0 AUDIO_RX_PCM_DW AUDIO_RX_PCM_DW 0x130 0x20 read-write 0x00000010 RSVD 5 27 PCM_DATA_WIDTH For I2S and left justified mode, M can be 8,13,14,16 For right justified mode, M can be 8, 13, 14, 16, 18, 20, 22, 24 0 5 RSVD24 RSVD24 0x134 0x20 read-write 0x0 AUDIO_RX_LRCK_DIV AUDIO_RX_LRCK_DIV 0x140 0x20 read-write 0x007D007D RSVD 28 4 DUTY_HIGH RX LRCK duty cycle high: 125 for 48K FS 136 for 44.1K FS 185 for 32K FS 250 for 24K FS 272 for 22.05K FS 375 for 16K FS 500 for 12K FS 544 for 11.025K FS 750 for 8K FS 16 12 RSVD2 12 4 DUTY_LOW RX LRCK duty cycle low: 125 for 48K FS 136 for 44.1K FS 190 for 32K FS 250 for 24K FS 272 for 22.05K FS 375 for 16K FS 500 for 12K FS 544 for 11.025K FS 750 for 8K FS Note: 1)duty_cycle = 12M/FS 0 12 RSVD23 RSVD23 0x144 0x20 read-write 0x0 AUDIO_RX_BCLK_DIV AUDIO_RX_BCLK_DIV 0x150 0x20 read-write 0x00000005 RSVD 10 22 DUTY RX serial bit clock duty cycle 5 for 48K FS 4 for 44.1K FS 5 for 32KFS 10 for 24K FS 8 for 22.05K FS 15 for 16K FS 20 for 12K FS 16 for 11.025K FS 30 for 8KFs 0 10 RSVD22 RSVD22 0x154 0x20 read-write 0x0 RECORD_DATA_SEL RECORD_DATA_SEL 0x160 0x20 read-write 0x00000000 RSVD 1 31 RS_DATA_SEL 0: I2S audio recording 1: BT recording 0 1 RSVD21 RSVD21 0x164 0x20 read-write 0x0 RX_RE_SAMPLE_CLK_DIV RX_RE_SAMPLE_CLK_DIV 0x170 0x20 read-write 0x0000007D RSVD 13 19 RS_DUTY source PCM sample clock duty cycle: 250 for 48K FS 272 for 44.1K FS 375 for 32K FS 500 for 24K FS 544 for 22.05K FS 750 for 16K FS 1000 for 12K FS 1088 for 11.025K FS 1500 for 8K FS Note: 1)duty_cycle = 12M/FS 0 13 RSVD20 RSVD20 0x174 0x20 read-write 0x0 RX_RE_SAMPLE RX_RE_SAMPLE 0x180 0x20 read-write 0x00000000 RSVD 1 31 SMOOTH_EN 0: Disable RX re-sample smooth filter 1: Enable RX re-sample smooth filter 0 1 RSVD19 RSVD19 0x184 0x20 read-write 0x0 RECORD_FORMAT RECORD_FORMAT 0x190 0x20 read-write 0x00000000 RSVD 2 30 TRACK 1: mono recording, 0: stereo recording 1 1 DW 0: 8bit 1: 16bit RX fifo data format: Mono 8 bit (unsigned): RX FIFO_DIN[31:0] = {L3,L2,L1,L0}, each four samples need one FIFO write operation Stereo 8 bit (unsigned): RX_FIFO_DIN[31:0] = {R1,L1,R0,L0}, each tow samples need one FIFO write operation Mono 16 bit (Signed 2's complement): RX_FIFO_DIN[31:0] = {L1,L0}, each two samples need one FIFO write operation Stereo 16 bit (Signed 2's complement): RX_FIFO_DIN[31:0] = {R0,L0}, each sample need one FIFO write operation 0 1 RSVD18 RSVD18 0x194 0x20 read-write 0x0 RX_CH_SEL RX_CH_SEL 0x1a0 0x20 read-write 0x00000000 RSVD 4 28 LEFT_CHANNEL_SEL RX re-sampling module setting: 00: RD left = RX left 01: RD left = RX right 10,11: RD left = (RX left + RX right)/2 2 2 RIGHT_CHANNEL_SEL RX re-sampling module setting: 00: RD right = RX right 01: RD right = RX left 10,11: RD right = (RX left + RX right)/2 0 2 RSVD17 RSVD17 0x1A4 0x20 read-write 0x0 BT_PHONE_CTRL BT_PHONE_CTRL 0x200 0x20 read-write 0x00000000 RSVD 6 26 BB_I2S_BPS_TO_CDC bypass baseband I2S interface to audio codec i2s interface 0: no bypass, 1: bypass 5 1 BT_PCM_IF_BPS bypass baseband PCM signals to BT VCI master: 0: no bypass, 1: bypass 4 1 BT_PATH_SEL BT path select 0: digital path, 1: analog path 3 1 BT_MIX_SMOOTH_FILTER_EN 0: disable the smooth filter for background mixer 1: enable the smooth filer for background mixer 2 1 BT_BACK_MIX_EN background mixer enable 0: disable, 1: enable 1 1 BT_PH_EN BT phone enable 0: disable, 1: enable 0 1 RSVD16 RSVD16 0x204 0x20 read-write 0x0 BB_PCM_FORMAT BB_PCM_FORMAT 0x210 0x20 read-write 0x00000000 RSVD 11 21 PCM_CLK_POL input BB pcm clock polarity: 0: rising edge for data transmitting, falling edge for data receiving 1: rising edge for data receiving, falling edge for data transmitting 10 1 I2S_LRCK_POL 0: no bb_i2s_lrck input inventor 1: enable bb_i2s_lrck input inventor for standard I2S, set tx_lrck_pol to low for Left/Right Justified, set tx_lrck_pol to high 9 1 PCM_LSB_FLAG Serial PCM data bit sequence. 0: MSB first, 1: LSB first 8 1 PCM_SYNC_FLAG 0: short sync, 1: long sync 7 1 PCM_TIM_SEL 00: I2S timing, 01: Left Justified 10: Right Justified, 11: PCM timing 5 2 PCM_DW Baseband Master PCM data width (>=8) Common value: 8, 13,14, 16, 18, 20, 22, 24. for I2S/Left Justified/Right Kistified timing, bb_pcm_dw >=16 For PCM timing, only 8, 13, 14, 16 configure value is available. 0 5 RSVD15 RSVD15 0x214 0x20 read-write 0x0 BT_PCM_DW BT_PCM_DW 0x220 0x20 read-write 0x00000010 RSVD 5 27 DW BT PCM master data width (>= 8), common value: 8, 13,14, 16 0 5 RSVD14 RSVD14 0x224 0x20 read-write 0x0 BT_PCM_TIMING BT_PCM_TIMING 0x230 0x20 read-write 0x00000000 RSVD 3 29 CLK_POL BT PCM master output pcm clock polarity: 0: rising edge for data transmitting, falling edge for data receiving 1: rising edge for data receiving, falling edge for data transmitting 2 1 SYNC_FLAG 0: short sync, 1: long sync 1 1 LSB_FLAG Serial PCM data bit sequence. 0: MSB first, 1: LSB first 0 1 RSVD13 RSVD13 0x234 0x20 read-write 0x0 BT_PCM_CLK_DUTY BT_PCM_CLK_DUTY 0x240 0x20 read-write 0x00000000 RSVD 10 22 CLK_DUTY BT_PCM_CLK duty cycle = (GCLK/(bt_pcm_sync*bt_pcm_dw)) 0 10 RSVD12 RSVD12 0x244 0x20 read-write 0x0 BT_PCM_SYNC_DUTY BT_PCM_SYNC_DUTY 0x250 0x20 read-write 0x00000000 RSVD 6 26 SYNC_DUTY PCM_SYNC duty cycle (bt_pcm_sync frequency = bt_pclk_clk/bt_pcm_sync_duty) 0 6 RSVD11 RSVD11 0x254 0x20 read-write 0x0 BT_VOL_CTRL BT_VOL_CTRL 0x260 0x20 read-write 0x00000000 RSVD 4 28 VOL_ADJ_EN BT volume adjust enable 3 1 VOL BT master volume 0 3 RSVD10 RSVD10 0x264 0x20 read-write 0x0 INT_MASK INT_MASK 0x300 0x20 read-write 0x00000003 RSVD 2 30 TX_FIFO_INT_MASK Interrupt mask for TX FIFO pop underflow, high active 1 1 RX_FIFO_INT_MASK Interrupt mask for RX FIFO push overflow, high active 0 1 RSVD9 RSVD9 0x304 0x20 read-write 0x0 INT_STATUS INT_STATUS 0x310 0x20 read-write 0x00000000 RSVD 2 30 TX_FIFO_UNDERFLOW TX FIFO pop underflow 1 1 RX_FIFO_OVERFLOW RX FIFO push overflow 0 1 RSVD8 RSVD8 0x314 0x20 read-write 0x0 TX_DMA_ENTRY TX_DMA_ENTRY 0x400 0x20 read-write 0x00000000 TX_DMA_ENTRY TX DMA entry 0 32 RSVD7 RSVD7 0x404 0x20 read-write 0x0 RX_DMA_ENTRY RX_DMA_ENTRY 0x440 0x20 read-write 0x00000000 RX_DMA_ENTRY RX DMA entry 0 32 RSVD6 RSVD6 0x444 0x20 read-write 0x0 DMA_MASK DMA_MASK 0x480 0x20 read-write 0x00000003 RSVD 2 30 TX_DMA_MASK TX DMA mask enable:1: mask0: do not mask 1 1 RX_DMA_MASK RX DMA mask enable:1: mask0: do not mask 0 1 RSVD5 RSVD5 0x484 0x20 read-write 0x0 DEBUG_LOOP DEBUG_LOOP 0x500 0x20 read-write 0x00000000 RSVD 24 8 SP_CLK_DIV sp clock divider value 16 8 RSVD2 9 7 SP_CLK_DIV_UPDATE update sp clock divider 8 1 RSVD3 3 5 SP_CLK_SEL clock select 0: xtal clock 1: pll clock 2 1 AD2DA_LOOP_BACK RX-->TX Loop debug control: 0: disable 1: enable, internally connect RX Resampled PCM to TX Resample PCM input 1 1 DA2AD_LOOP_BACK TX-->RX Loop debug control: 0: disable 1: enable, internally connect TX SDTO to RX SDTI 0 1 RSVD4 RSVD4 0x504 0x20 read-write 0x0 FIFO_STATUS FIFO_STATUS 0x600 0x20 read-write 0x00000000 RSVD 8 24 FIFO_STATUS_OUT FIFO Status output: Bit [7:0] = {tx_full,tx_empty,tx_almost_full,tx_almost_empty,rx_full,rx_empty,rx_almost_full,rx_almost_empty} 0 8 RSVD3 RSVD3 0x604 0x20 read-write 0x0 TX_EQUALIZER_EN TX_EQUALIZER_EN 0x700 0x20 read-write 0x00000000 RSVD 1 31 TX_EQUALIZER_EN 0: Disable TX equalizer 1: Enable TX equalizer equalizer is not implemented 0 1 RSVD2 RSVD2 0x704 0x20 read-write 0x0 TX_EQUALIZER_GAIN1 TX_EQUALIZER_GAIN1 0x710 0x20 read-write 0x00000000 RSVD 30 2 BAND6_GAIN 25 5 BAND5_GAIN 20 5 BAND4_GAIN 15 5 BAND3_GAIN 10 5 BAND2_GAIN 5 5 BAND1_GAIN 0 5 RSVD1 RSVD1 0x714 0x20 read-write 0x0 TX_EQUALIZER_GAIN2 TX_EQUALIZER_GAIN2 0x720 0x20 read-write 0x00000000 RSVD 20 12 BAND10_GAIN 15 5 BAND9_GAIN 10 5 BAND8_GAIN 5 5 BAND7_GAIN 0 5 HPSYS_CFG HPSYS_CFG 0x5000b000 0x0 0x1000 registers BMR BMR Boot Mode Register 0x00 0x20 read-write 0x0 RSVD 1 31 BOOT_MODE 0 - normal mode, 1 - download mode 0 1 IDR IDR ID Register 0x04 0x20 read-write 0x0 SID Series ID 24 8 CID Chip ID 16 8 PID Package ID 8 8 REVID Revision ID 0 8 SWCR SWCR SW Control Register 0x08 0x20 read-write 0x0 RSVD 1 31 SWSEL reserved for debug 0 1 SCR SCR Security Control Register 0x0c 0x20 read-write 0x0 RSVD 1 31 FKEY_MODE reserved for debug 0 1 SYSCR SYSCR System Configure Register 0x10 0x20 read-write 0x0 RSVD 3 29 LDO_VSEL select work mode 0: enhanced mode 1: base mode 2 1 SDNAND 0: MPI2 AHB space is allocated to MPI2 1: MPI2 AHB space is allocated to SDMMC1 1 1 WDT1_REBOOT If set to 1, WDT1 reset will reboot the whole chip 0 1 RTC_TR RTC_TR Mirrored RTC Time Register 0x14 0x20 read-write 0x0 PM AM/PM notation 0: AM 1: PM 31 1 HT Hour tens in BCD format 29 2 HU Hour units in BCD format 25 4 MNT Minute tens in BCD format 22 3 MNU Minute units in BCD format 18 4 ST Second tens in BCD format 15 3 SU Second units in BCD format 11 4 RSVD 10 1 SS Sub-second counter 0 10 RTC_DR RTC_DR Mirrored RTC Date Register 0x18 0x20 read-write 0x0 ERR reserved for debug 31 1 RSVD 25 6 CB Century flag 24 1 YT Year tens in BCD format 20 4 YU Year units in BCD format 16 4 WD Week day units 000: forbidden 001: Monday ... 111: Sunday 13 3 MT Month tens in BCD format 12 1 MU Month units in BCD format 8 4 RSVD2 6 2 DT Date tens in BCD format 4 2 DU Date units in BCD format 0 4 ULPMCR ULPMCR ULP Memory Control register 0x1c 0x20 read-write 0x0 FORCE_ON reserved for debug 31 1 ROM_DIS reserved for debug 30 1 RSVD 21 9 ROM_RME reserved for debug 20 1 RSVD2 18 2 ROM_RM reserved for debug 16 2 RSVD3 13 3 RAM_WPULSE reserved for debug 10 3 RAM_WA reserved for debug 7 3 RAM_RA reserved for debug 5 2 RAM_RME reserved for debug 4 1 RSVD4 2 2 RAM_RM reserved for debug 0 2 DBGR DBGR Debug Select Register 0x20 0x20 read-write 0x0 SWAP reserved for debug 31 1 LP2HP_NMIF LP2HP NMI interrupt flag 30 1 LP2HP_NMIE LP2HP NMI interrupt enable 29 1 HP2LP_NMI set 1 to send NMI interrupt to LCPU 28 1 CLK_EN reserved for debug 27 1 CLK_SEL reserved for debug 24 3 BITEN_H reserved for debug 16 8 BITEN_L reserved for debug 8 8 SEL_H reserved for debug 4 4 SEL_L reserved for debug 0 4 MDBGR MDBGR Memory Debug Register 0x24 0x20 read-write 0x0 RSVD 5 27 PD_ROM reserved for debug 4 1 LS_ROM reserved for debug 3 1 LS_RAM2 reserved for debug 2 1 LS_RAM1 reserved for debug 1 1 LS_RAM0 reserved for debug 0 1 RSVD1 RSVD1 0x28 0x20 read-write 0x0 LPIRQ LPIRQ Interrupt Selection for LCPU 0x3c 0x20 read-write 0x0 RSVD 16 16 IF1 hp2lp1 interrupt status. Write 1 to clear. 15 1 RSVD2 14 1 SEL1 select hp2lp1 interrupt source 8 6 IF0 hp2lp0 interrupt status. Write 1 to clear. 7 1 RSVD3 6 1 SEL0 select hp2lp0 interrupt source 0 6 USBCR USBCR USB Control register 0x40 0x20 read-write 0x0 RSVD1 reserved for debug 24 8 RSVD0 reserved for debug 16 8 DC_TR reserved for debug 13 3 DC_TE reserved for debug 12 1 RSVD 11 1 TX_RTUNE TX outp impedance tuning 0 = 50 Ohm, 1 = 46 Ohm, 2 = 43 Ohm, 3 = 40 Ohm, 4 = 37.5 Ohm, 5 = 35 Ohm, 6 = 33 Ohm, 7 = 31.5 Ohm 8 3 RSVD2 7 1 DP_EN 0:disable dp pull up or pull down 1:enable dp pull or pull down 6 1 DM_PD enable DM 15k Ohm pull down resistor 5 1 LDO_LP_EN 2.5V LDO low power mode enable. 0 = 240 uA, 1 = 50 uA 4 1 LDO_VSEL 2.5V LDO output voltage setting 0 = 2.40 V, 1 = 2.47 V, 2 = 2.53 V, 3 = 2.60 V, 4 = 2.60 V, 5 = 2.67 V, 6 = 2.73 V, 7 = 2.8 V 1 3 USB_EN USB PHY enable, turn on power swith, power up LDO and bias 0 1 SYS_RSVD SYS_RSVD HPSYS RSVD Register 0x44 0x20 read-write 0x0 RESERVE3 reserved for debug 24 8 RESERVE2 reserved for debug 16 8 RESERVE1 reserved for debug 8 8 RESERVE0 reserved for debug 0 8 I2C1_PINR I2C1_PINR I2C1 Pin Register 0x48 0x20 read-write 0x0 RSVD 14 18 SDA_PIN Connect function pin to selected IO(PA). 0 to 44 for PA00 to PA44. Other values for floating. 8 6 RSVD2 6 2 SCL_PIN Connect function pin to selected IO(PA). 0 to 44 for PA00 to PA44. Other values for floating. 0 6 I2C2_PINR I2C2_PINR I2C2 Pin Register 0x4c 0x20 read-write 0x0 RSVD 14 18 SDA_PIN Connect function pin to selected IO(PA). 0 to 44 for PA00 to PA44. Other values for floating. 8 6 RSVD2 6 2 SCL_PIN Connect function pin to selected IO(PA). 0 to 44 for PA00 to PA44. Other values for floating. 0 6 I2C3_PINR I2C3_PINR I2C3 Pin Register 0x50 0x20 read-write 0x0 RSVD 14 18 SDA_PIN Connect function pin to selected IO(PA). 0 to 44 for PA00 to PA44. Other values for floating. 8 6 RSVD2 6 2 SCL_PIN Connect function pin to selected IO(PA). 0 to 44 for PA00 to PA44. Other values for floating. 0 6 I2C4_PINR I2C4_PINR I2C4 Pin Register 0x54 0x20 read-write 0x0 RSVD 14 18 SDA_PIN Connect function pin to selected IO(PA). 0 to 44 for PA00 to PA44. Other values for floating. 8 6 RSVD2 6 2 SCL_PIN Connect function pin to selected IO(PA). 0 to 44 for PA00 to PA44. Other values for floating. 0 6 USART1_PINR USART1_PINR USART1 Pin Register 0x58 0x20 read-write 0x0 RSVD 30 2 CTS_PIN Connect function pin to selected IO(PA). 0 to 44 for PA00 to PA44. Other values for floating. 24 6 RSVD2 22 2 RTS_PIN Connect function pin to selected IO(PA). 0 to 44 for PA00 to PA44. Other values for floating. 16 6 RSVD3 14 2 RXD_PIN Connect function pin to selected IO(PA). 0 to 44 for PA00 to PA44. Other values for floating. 8 6 RSVD4 6 2 TXD_PIN Connect function pin to selected IO(PA). 0 to 44 for PA00 to PA44. Other values for floating. 0 6 USART2_PINR USART2_PINR USART2 Pin Register 0x5c 0x20 read-write 0x0 RSVD 30 2 CTS_PIN Connect function pin to selected IO(PA). 0 to 44 for PA00 to PA44. Other values for floating. 24 6 RSVD2 22 2 RTS_PIN Connect function pin to selected IO(PA). 0 to 44 for PA00 to PA44. Other values for floating. 16 6 RSVD3 14 2 RXD_PIN Connect function pin to selected IO(PA). 0 to 44 for PA00 to PA44. Other values for floating. 8 6 RSVD4 6 2 TXD_PIN Connect function pin to selected IO(PA). 0 to 44 for PA00 to PA44. Other values for floating. 0 6 USART3_PINR USART3_PINR USART3 Pin Register 0x60 0x20 read-write 0x0 RSVD 30 2 CTS_PIN Connect function pin to selected IO(PA). 0 to 44 for PA00 to PA44. Other values for floating. 24 6 RSVD2 22 2 RTS_PIN Connect function pin to selected IO(PA). 0 to 44 for PA00 to PA44. Other values for floating. 16 6 RSVD3 14 2 RXD_PIN Connect function pin to selected IO(PA). 0 to 44 for PA00 to PA44. Other values for floating. 8 6 RSVD4 6 2 TXD_PIN Connect function pin to selected IO(PA). 0 to 44 for PA00 to PA44. Other values for floating. 0 6 GPTIM1_PINR GPTIM1_PINR GPTIM1 Pin Register 0x64 0x20 read-write 0x0 RSVD 30 2 CH4_PIN Connect function pin to selected IO(PA). 0 to 44 for PA00 to PA44. Other values for floating. 24 6 RSVD2 22 2 CH3_PIN Connect function pin to selected IO(PA). 0 to 44 for PA00 to PA44. Other values for floating. 16 6 RSVD3 14 2 CH2_PIN Connect function pin to selected IO(PA). 0 to 44 for PA00 to PA44. Other values for floating. 8 6 RSVD4 6 2 CH1_PIN Connect function pin to selected IO(PA). 0 to 44 for PA00 to PA44. Other values for floating. 0 6 GPTIM2_PINR GPTIM2_PINR GPTIM2 Pin Register 0x68 0x20 read-write 0x0 RSVD 30 2 CH4_PIN Connect function pin to selected IO(PA). 0 to 44 for PA00 to PA44. Other values for floating. 24 6 RSVD2 22 2 CH3_PIN Connect function pin to selected IO(PA). 0 to 44 for PA00 to PA44. Other values for floating. 16 6 RSVD3 14 2 CH2_PIN Connect function pin to selected IO(PA). 0 to 44 for PA00 to PA44. Other values for floating. 8 6 RSVD4 6 2 CH1_PIN Connect function pin to selected IO(PA). 0 to 44 for PA00 to PA44. Other values for floating. 0 6 ETR_PINR ETR_PINR GPTIM ETR Pin Register 0x6c 0x20 read-write 0x0 RSVD 14 18 ETR2_PIN Connect GPTIM2_ETR to selected IO(PA). 0 to 44 for PA00 to PA44. Other values for floating. 8 6 RSVD2 6 2 ETR1_PIN Connect GPTIM1_ETR to selected IO(PA). 0 to 44 for PA00 to PA44. Other values for floating. 0 6 LPTIM1_PINR LPTIM1_PINR LPTIM1 Pin Register 0x70 0x20 read-write 0x0 RSVD 22 10 ETR_PIN Connect function pin to selected IO(PA). 0 to 44 for PA00 to PA44. Other values for floating. 16 6 RSVD2 14 2 OUT_PIN Connect function pin to selected IO(PA). 0 to 44 for PA00 to PA44. Other values for floating. 8 6 RSVD3 6 2 IN_PIN Connect function pin to selected IO(PA). 0 to 44 for PA00 to PA44. Other values for floating. 0 6 LPTIM2_PINR LPTIM2_PINR LPTIM2 Pin Register 0x74 0x20 read-write 0x0 RSVD 22 10 ETR_PIN Connect function pin to selected IO(PA). 0 to 44 for PA00 to PA44. Other values for floating. 16 6 RSVD2 14 2 OUT_PIN Connect function pin to selected IO(PA). 0 to 44 for PA00 to PA44. Other values for floating. 8 6 RSVD3 6 2 IN_PIN Connect function pin to selected IO(PA). 0 to 44 for PA00 to PA44. Other values for floating. 0 6 ATIM1_PINR1 ATIM1_PINR1 ATIM1 Pin Register 1 0x78 0x20 read-write 0x0 RSVD 30 2 CH4_PIN Connect function pin to selected IO(PA). 0 to 44 for PA00 to PA44. Other values for floating. 24 6 RSVD2 22 2 CH3_PIN Connect function pin to selected IO(PA). 0 to 44 for PA00 to PA44. Other values for floating. 16 6 RSVD3 14 2 CH2_PIN Connect function pin to selected IO(PA). 0 to 44 for PA00 to PA44. Other values for floating. 8 6 RSVD4 6 2 CH1_PIN Connect function pin to selected IO(PA). 0 to 44 for PA00 to PA44. Other values for floating. 0 6 ATIM1_PINR2 ATIM1_PINR2 ATIM1 Pin Register 2 0x7c 0x20 read-write 0x0 RSVD 22 10 CH3N_PIN Connect function pin to selected IO(PA). 0 to 44 for PA00 to PA44. Other values for floating. 16 6 RSVD2 14 2 CH2N_PIN Connect function pin to selected IO(PA). 0 to 44 for PA00 to PA44. Other values for floating. 8 6 RSVD3 6 2 CH1N_PIN Connect function pin to selected IO(PA). 0 to 44 for PA00 to PA44. Other values for floating. 0 6 ATIM1_PINR3 ATIM1_PINR3 ATIM1 Pin Register 3 0x80 0x20 read-write 0x0 RSVD 22 10 ETR_PIN Connect function pin to selected IO(PA). 0 to 44 for PA00 to PA44. Other values for floating. 16 6 RSVD2 14 2 BK2_PIN Connect function pin to selected IO(PA). 0 to 44 for PA00 to PA44. Other values for floating. 8 6 RSVD3 6 2 BK_PIN Connect function pin to selected IO(PA). 0 to 44 for PA00 to PA44. Other values for floating. 0 6 PTA_PINR PTA_PINR PTA Pin Register 0x84 0x20 read-write 0x0 RSVD 30 2 WLAN_ACTIVE Connect function pin to selected IO(PA). 0 to 44 for PA00 to PA44. Other values for floating. 24 6 RSVD2 22 2 BT_PRIORITY Connect function pin to selected IO(PA). 0 to 44 for PA00 to PA44. Other values for floating. 16 6 RSVD3 14 2 BT_COLLISION Connect function pin to selected IO(PA). 0 to 44 for PA00 to PA44. Other values for floating. 8 6 RSVD4 6 2 BT_ACTIVE Connect function pin to selected IO(PA). 0 to 44 for PA00 to PA44. Other values for floating. 0 6 ANAU_CR ANAU_CR ANAU Control Register 0x88 0x20 read-write 0x0 RSVD 7 25 DC_MR reserved for debug 4 3 EFUSE_VDD_PD reserved for debug 3 1 EFUSE_VDD_EN reserved for debug 2 1 EN_VBAT_MON reserved for debug 1 1 EN_BG reserved for debug 0 1 ANAU_RSVD ANAU_RSVD ANAU Reserve Register 0x8c 0x20 read-write 0x0 RESERVE3 reserved for debug 24 8 RESERVE2 reserved for debug 16 8 RESERVE1 reserved for debug 8 8 RESERVE0 reserved for debug 0 8 ANATR ANATR Analog Test Register 0x90 0x20 read-write 0x0 RSVD 8 24 DC_UR_ATEST1 reserved for debug 5 3 DC_TE_ATEST1 reserved for debug 4 1 DC_UR_ATEST0 reserved for debug 1 3 DC_TE_ATEST0 reserved for debug 0 1 CAU2_CR CAU2_CR CAU2 Control Register 0x94 0x20 read-write 0x0 RSVD 13 19 DC_MR reserved for debug 10 3 DC_BR reserved for debug 7 3 DC_TR reserved for debug 4 3 RSVD2 2 2 HPBG_EN reserved for debug 1 1 HPBG_VDDPSW_EN reserved for debug 0 1 CAU2_RSVD CAU2_RSVD CAU2 RSVD Register1 0x98 0x20 read-write 0x0 RSVD 24 8 RESERVE2 reserved for debug 16 8 RESERVE1 reserved for debug 8 8 RESERVE0 reserved for debug 0 8 EFUSEC EFUSEC 0x5000c000 0x0 0x1000 registers CR CR Control Register 0x00 0x20 read-write 0x00000000 RSVD 5 27 IE Interrupt enable 4 1 BANKSEL Bank select 2 2 MODE 0 - READ, 1 - PGM 1 1 EN Write 1 to enable PGM/READ. Self clear 0 1 TIMR TIMR Timer Register 0x04 0x20 read-write 0x00000000 RSVD 21 11 TCKHP SCLK high period for PGM. Recommended value ~10us 10 11 THPCK SCLK to CSB hold time into PGM mode. Recommended value > 20ns 7 3 THRCK SCLK to CSB hold time into READ mode. Recmmended value > 500ns 0 7 SR SR Status Register 0x08 0x20 read-write 0x00000000 RSVD 1 31 DONE Indicates PGM/READ done. Write 1 to clear 0 1 RSVDR RSVDR Reserved Register 0x0c 0x20 read-write 0x00000000 RSVD 0 32 PGM_DATA0 PGM_DATA0 Program Data0 0x10 0x20 read-write 0x00000000 DATA 0 32 PGM_DATA1 PGM_DATA1 Program Data1 0x14 0x20 read-write 0x00000000 DATA 0 32 PGM_DATA2 PGM_DATA2 Program Data2 0x18 0x20 read-write 0x00000000 DATA 0 32 PGM_DATA3 PGM_DATA3 Program Data3 0x1c 0x20 read-write 0x00000000 DATA 0 32 PGM_DATA4 PGM_DATA4 Program Data4 0x20 0x20 read-write 0x00000000 DATA 0 32 PGM_DATA5 PGM_DATA5 Program Data5 0x24 0x20 read-write 0x00000000 DATA 0 32 PGM_DATA6 PGM_DATA6 Program Data6 0x28 0x20 read-write 0x00000000 DATA 0 32 PGM_DATA7 PGM_DATA7 Program Data7 0x2c 0x20 read-write 0x00000000 DATA 0 32 BANK0_DATA0 BANK0_DATA0 Bank0 Data0 0x30 0x20 read-write 0x0 DATA 0 32 BANK0_DATA1 BANK0_DATA1 Bank0 Data1 0x34 0x20 read-write 0x0 DATA 0 32 BANK0_DATA2 BANK0_DATA2 Bank0 Data2 0x38 0x20 read-write 0x0 DATA 0 32 BANK0_DATA3 BANK0_DATA3 Bank0 Data3 0x3c 0x20 read-write 0x0 DATA 0 32 BANK0_DATA4 BANK0_DATA4 Bank0 Data4 0x40 0x20 read-write 0x0 DATA 0 32 BANK0_DATA5 BANK0_DATA5 Bank0 Data5 0x44 0x20 read-write 0x0 DATA 0 32 BANK0_DATA6 BANK0_DATA6 Bank0 Data6 0x48 0x20 read-write 0x0 DATA 0 32 BANK0_DATA7 BANK0_DATA7 Bank0 Data7 0x4c 0x20 read-write 0x0 DATA 0 32 BANK1_DATA0 BANK1_DATA0 Bank1 Data0 0x50 0x20 read-write 0x0 DATA 0 32 BANK1_DATA1 BANK1_DATA1 Bank1 Data1 0x54 0x20 read-write 0x0 DATA 0 32 BANK1_DATA2 BANK1_DATA2 Bank1 Data2 0x58 0x20 read-write 0x0 DATA 0 32 BANK1_DATA3 BANK1_DATA3 Bank1 Data3 0x5c 0x20 read-write 0x0 DATA 0 32 BANK1_DATA4 BANK1_DATA4 Bank1 Data4 0x60 0x20 read-write 0x0 DATA 0 32 BANK1_DATA5 BANK1_DATA5 Bank1 Data5 0x64 0x20 read-write 0x0 DATA 0 32 BANK1_DATA6 BANK1_DATA6 Bank1 Data6 0x68 0x20 read-write 0x0 DATA 0 32 BANK1_DATA7 BANK1_DATA7 Bank1 Data7 0x6c 0x20 read-write 0x0 DATA 0 32 BANK2_DATA0 BANK2_DATA0 Bank2 Data0 0x70 0x20 read-write 0x0 DATA 0 32 BANK2_DATA1 BANK2_DATA1 Bank2 Data1 0x74 0x20 read-write 0x0 DATA 0 32 BANK2_DATA2 BANK2_DATA2 Bank2 Data2 0x78 0x20 read-write 0x0 DATA 0 32 BANK2_DATA3 BANK2_DATA3 Bank2 Data3 0x7c 0x20 read-write 0x0 DATA 0 32 BANK2_DATA4 BANK2_DATA4 Bank2 Data4 0x80 0x20 read-write 0x0 DATA 0 32 BANK2_DATA5 BANK2_DATA5 Bank2 Data5 0x84 0x20 read-write 0x0 DATA 0 32 BANK2_DATA6 BANK2_DATA6 Bank2 Data6 0x88 0x20 read-write 0x0 DATA 0 32 BANK2_DATA7 BANK2_DATA7 Bank2 Data7 0x8c 0x20 read-write 0x0 DATA 0 32 BANK3_DATA0 BANK3_DATA0 Bank3 Data0 0x90 0x20 read-write 0x0 DATA 0 32 BANK3_DATA1 BANK3_DATA1 Bank3 Data1 0x94 0x20 read-write 0x0 DATA 0 32 BANK3_DATA2 BANK3_DATA2 Bank3 Data2 0x98 0x20 read-write 0x0 DATA 0 32 BANK3_DATA3 BANK3_DATA3 Bank3 Data3 0x9c 0x20 read-write 0x0 DATA 0 32 BANK3_DATA4 BANK3_DATA4 Bank3 Data4 0xa0 0x20 read-write 0x0 DATA 0 32 BANK3_DATA5 BANK3_DATA5 Bank3 Data5 0xa4 0x20 read-write 0x0 DATA 0 32 BANK3_DATA6 BANK3_DATA6 Bank3 Data6 0xa8 0x20 read-write 0x0 DATA 0 32 BANK3_DATA7 BANK3_DATA7 Bank3 Data7 0xac 0x20 read-write 0x0 DATA 0 32 ANACR ANACR Bank3 Data7 0xb0 0x20 read-write 0x0 RESERVE1 24 8 RESERVE0 16 8 RSVD 11 5 LDO_DC_TR 8 3 RSVD2 5 3 LDO_MODE 4 1 LDO_VREF_SEL 1 3 LDO_EN 0 1 DB_SEL DB_SEL debug signal select 0xb4 0x20 read-write 0x00000000 DB_SEL debug signal select 0 32 AES AES 0x5000d000 0x0 0x1000 registers COMMAND COMMAND 0x00 0x20 read-write 0x00000000 RSVD 5 27 AUTO_GATE auto clock gating 4 1 HASH_RESET HASH_ACC soft reset, 1'h1: reset the HASH_ACC block 3 1 HASH_START write 1 to trigger the HASH_ACC block 2 1 AES_ACC_RESET AES_ACC soft reset, 1'h1: reset the AES_ACC block 1 1 START write 1 to trigger the AES_ACC block 0 1 STATUS STATUS 0x04 0x20 read-write 0x00000000 RSVD 3 29 HASH_BUSY HASH_ACC block is busy 2 1 FLASH_KEY_VALID flash key valid indicator 1 1 BUSY AES_ACC block is busy 0 1 IRQ IRQ 0x08 0x20 read-write 0x00000000 RSVD 22 10 HASH_PAD_ERR_RAW_STAT HASH_ACC padding error raw status 21 1 HASH_BUS_ERR_RAW_STAT HASH_ACC bus error raw status 20 1 HASH_DONE_RAW_STAT HASH_ACC done raw status 19 1 SETUP_ERR_RAW_STAT AES_ACC setup error raw status 18 1 BUS_ERR_RAW_STAT AES_ACC bus error raw status 17 1 DONE_RAW_STAT AES_ACC done raw status 16 1 RSVD2 6 10 HASH_PAD_ERR_STAT HASH_ACC padding error status 5 1 HASH_BUS_ERR_STAT HASH_ACC bus error status 4 1 HASH_DONE_STAT HASH_ACC done status 3 1 SETUP_ERR_STAT AES_ACC setup error status 2 1 BUS_ERR_STAT AES_ACC bus error status 1 1 DONE_STAT AES_ACC done status 0 1 SETTING SETTING 0x0c 0x20 read-write 0x00000000 RSVD 6 26 HASH_PAD_ERR_MASK HASH_ACC padding error interrupt mask, 0: mask the interrupt 5 1 HASH_BUS_ERR_MASK HASH_ACC bus error interrpt mask, 0: mask the interrupt 4 1 HASH_DONE_MASK HASH_ACC done interrupt mask, 0: mask the interrupt 3 1 SETUP_ERR_IRQ_MASK AES_ACC setup error interrupt mask, 0: mask the interrupt 2 1 BUS_ERR_IRQ_MASK AES_ACC bus error interrupt mask, 0: mask the interrupt 1 1 DONE_IRQ_MASK AES_ACC done interrupt mask, 0: mask the interrupt 0 1 AES_SETTING AES_SETTING 0x10 0x20 read-write 0x00000000 RSVD 9 23 AES_BYPASS 1'h0: normal operation 1'h1: bypass 8 1 AES_OP_MODE 1'h0: decryption 1'h1: encryption 7 1 ALGO_STANDARD 1'h0: AES 1'h1: SM4 6 1 KEY_SEL 1'h0: select key from AES_ACC key registers 1'h1: use internal root key 5 1 AES_LENGTH AES Length: 2'h0: 128-bit 2'h1: 192-bit 2'h2: 256-bit 2'h3: Reserved 3 2 AES_MODE AES Mode: 3'h0: ECB 3'h1: CTR 3'h2: CBC Others: Reserved 0 3 DMA_IN DMA_IN 0x14 0x20 read-write 0x00000000 ADDR AES_ACC input data address 0 32 DMA_OUT DMA_OUT 0x18 0x20 read-write 0x00000000 ADDR AES_ACC output data address 0 32 DMA_DATA DMA_DATA 0x1c 0x20 read-write 0x00000000 RSVD 28 4 SIZE AES_ACC data block size, AES_ACC only support block aligned transaction. Each block contains 16 bytes. 0 28 IV_W0 IV_W0 0x20 0x20 read-write 0x00000000 DATA Initial Vector Word0 0 32 IV_W1 IV_W1 0x24 0x20 read-write 0x00000000 DATA Initial Vector Word1 0 32 IV_W2 IV_W2 0x28 0x20 read-write 0x00000000 DATA Initial Vector Word2 0 32 IV_W3 IV_W3 0x2c 0x20 read-write 0x00000000 DATA Initial Vector Word3 0 32 EXT_KEY_W0 EXT_KEY_W0 0x30 0x20 read-write 0x00000000 DATA External Key Word0 0 32 EXT_KEY_W1 EXT_KEY_W1 0x34 0x20 read-write 0x00000000 DATA External Key Word1 0 32 EXT_KEY_W2 EXT_KEY_W2 0x38 0x20 read-write 0x00000000 DATA External Key Word2 0 32 EXT_KEY_W3 EXT_KEY_W3 0x3c 0x20 read-write 0x00000000 DATA External Key Word3 0 32 EXT_KEY_W4 EXT_KEY_W4 0x40 0x20 read-write 0x00000000 DATA External Key Word4 0 32 EXT_KEY_W5 EXT_KEY_W5 0x44 0x20 read-write 0x00000000 DATA External Key Word5 0 32 EXT_KEY_W6 EXT_KEY_W6 0x48 0x20 read-write 0x00000000 DATA External Key Word6 0 32 EXT_KEY_W7 EXT_KEY_W7 0x4c 0x20 read-write 0x00000000 DATA External Key Word7 0 32 HASH_SETTING HASH_SETTING 0x50 0x20 read-write 0x00000000 RSVD 9 23 HASH_LEN_LOAD write 1 to load hash length 8 1 HASH_IV_LOAD write 1 to load hash iv 7 1 RESULT_ENDIAN hash result endian setting: 1'h0: little endian 1'h1: big endian 6 1 DFT_IV_SEL HASH default iv select. 1'h0: default iv according to hash mode 1'h1: default iv from HASH_IV_H* registers 5 1 BYTE_SWAP HASH byte swap option. Set 1 to swap byte order when read data from memory. 4 1 DO_PADDING HASH padding enable. Set 1 to do padding after data transfer. 3 1 HASH_MODE HASH Mode: 3'h0: SHA-1 3'h1: SHA-224 3'h2: SHA-256 3'h3: SM3 Others: Reserved 0 3 HASH_DMA_IN HASH_DMA_IN 0x54 0x20 read-write 0x00000000 ADDR input data address 0 32 HASH_DMA_DATA HASH_DMA_DATA 0x58 0x20 read-write 0x00000000 SIZE HASH input data byte size. 0 32 HASH_IV_H0 HASH_IV_H0 0x5c 0x20 read-write 0x00000000 DATA HASH IV H0 0 32 HASH_IV_H1 HASH_IV_H1 0x60 0x20 read-write 0x00000000 DATA HASH IV H1 0 32 HASH_IV_H2 HASH_IV_H2 0x64 0x20 read-write 0x00000000 DATA HASH IV H2 0 32 HASH_IV_H3 HASH_IV_H3 0x68 0x20 read-write 0x00000000 DATA HASH IV H3 0 32 HASH_IV_H4 HASH_IV_H4 0x6c 0x20 read-write 0x00000000 DATA HASH IV H4 0 32 HASH_IV_H5 HASH_IV_H5 0x70 0x20 read-write 0x00000000 DATA HASH IV H5 0 32 HASH_IV_H6 HASH_IV_H6 0x74 0x20 read-write 0x00000000 DATA HASH IV H6 0 32 HASH_IV_H7 HASH_IV_H7 0x78 0x20 read-write 0x00000000 DATA HASH IV H7 0 32 HASH_RESULT_H0 HASH_RESULT_H0 0x7c 0x20 read-write 0x00000000 DATA HASH result H0 0 32 HASH_RESULT_H1 HASH_RESULT_H1 0x80 0x20 read-write 0x00000000 DATA HASH result H1 0 32 HASH_RESULT_H2 HASH_RESULT_H2 0x84 0x20 read-write 0x00000000 DATA HASH result H2 0 32 HASH_RESULT_H3 HASH_RESULT_H3 0x88 0x20 read-write 0x00000000 DATA HASH result H3 0 32 HASH_RESULT_H4 HASH_RESULT_H4 0x8c 0x20 read-write 0x00000000 DATA HASH result H4 0 32 HASH_RESULT_H5 HASH_RESULT_H5 0x90 0x20 read-write 0x00000000 DATA HASH result H5 0 32 HASH_RESULT_H6 HASH_RESULT_H6 0x94 0x20 read-write 0x00000000 DATA HASH result H6 0 32 HASH_RESULT_H7 HASH_RESULT_H7 0x98 0x20 read-write 0x00000000 DATA HASH result H7 0 32 HASH_LEN_L HASH_LEN_L 0x9c 0x20 read-write 0x00000000 DATA HASH load length l 0 32 HASH_LEN_H HASH_LEN_H 0xa0 0x20 read-write 0x00000000 RSVD 29 3 DATA HASH load length h 0 29 HASH_RESULT_LEN_L HASH_RESULT_LEN_L 0xa4 0x20 read-write 0x00000000 DATA HASH result length l 0 32 HASH_RESULT_LEN_H HASH_RESULT_LEN_H 0xa8 0x20 read-write 0x00000000 RSVD 29 3 DATA HASH result length h 0 29 TRNG TRNG 0x5000f000 0x0 0x1000 registers CTRL CTRL 0x00 0x20 read-write 0x00000000 RSVD 5 27 GEN_RAND_NUM_SUSPEND Set 1 to suspend random number generation and update. Set 0 to recover the process. 4 1 GEN_RAND_NUM_STOP Set 1 to stop random number generation and update. This will reset the random number generation engine. After release the stop bit, user should write 1 to gen_rand_num_start to trigger the random number engine. 3 1 GEN_SEED_STOP Set 1 to stop random seed generation. This will reset the random seed generation engine. After release the stop bit, user should write 1 to gen_seed_start to trigger the random seed engine. 2 1 GEN_RAND_NUM_START write 1 to trigger the random number generation engine 1 1 GEN_SEED_START write 1 to trigger the random seed generation engine 0 1 STAT STAT 0x04 0x20 read-write 0x00000000 RSVD 4 28 RAND_NUM_VALID random number valid flag 3 1 RAND_NUM_GEN_BUSY random number engine busy flag 2 1 SEED_VALID random seed valid flag 1 1 SEED_GEN_BUSY random seed engine busy flag 0 1 CFG CFG 0x08 0x20 read-write 0x00000000 RSVD 16 16 REJECT_THRESHOLD random seed internal VN corrector check threshold 8 8 RSVD2 2 6 USE_EXT_SEED set 1 to use external seed to generate random number 1 1 AUTO_CLOCK_ENABLE auto clock gating enable 0 1 IRQ IRQ 0x0c 0x20 read-write 0x00070000 RSVD 19 13 PRNG_LOCKUP_MSK prng lockup interrupt mask 18 1 RAND_NUM_AVAIL_MSK random number available interrupt mask 17 1 SEED_GEN_DONE_MSK random seed generation done interrupt mask 16 1 RSVD2 3 13 PRNG_LOCKUP prng lockup raw interrupt 2 1 RAND_NUM_AVAIL random number available raw interrupt 1 1 SEED_GEN_DONE random seed generation done raw interrupt 0 1 RAND_SEED0 RAND_SEED0 0x10 0x20 read-write 0x00000000 VAL random seed value0. If using external random seed, write value to this register will update the random seed in use. 0 32 RAND_SEED1 RAND_SEED1 0x14 0x20 read-write 0x00000000 VAL random seed value1. If using external random seed, write value to this register will update the random seed in use. 0 32 RAND_SEED2 RAND_SEED2 0x18 0x20 read-write 0x00000000 VAL random seed value2. If using external random seed, write value to this register will update the random seed in use. 0 32 RAND_SEED3 RAND_SEED3 0x1c 0x20 read-write 0x00000000 VAL random seed value3. If using external random seed, write value to this register will update the random seed in use. 0 32 RAND_SEED4 RAND_SEED4 0x20 0x20 read-write 0x00000000 VAL random seed value4. If using external random seed, write value to this register will update the random seed in use. 0 32 RAND_SEED5 RAND_SEED5 0x24 0x20 read-write 0x00000000 VAL random seed value5. If using external random seed, write value to this register will update the random seed in use. 0 32 RAND_SEED6 RAND_SEED6 0x28 0x20 read-write 0x00000000 VAL random seed value6. If using external random seed, write value to this register will update the random seed in use. 0 32 RAND_SEED7 RAND_SEED7 0x2c 0x20 read-write 0x00000000 VAL random seed value7. If using external random seed, write value to this register will update the random seed in use. 0 32 RAND_NUM0 RAND_NUM0 0x30 0x20 read-write 0x00000000 VAL random number value0 0 32 RAND_NUM1 RAND_NUM1 0x34 0x20 read-write 0x00000000 VAL random number value1 0 32 RAND_NUM2 RAND_NUM2 0x38 0x20 read-write 0x00000000 VAL random number value2 0 32 RAND_NUM3 RAND_NUM3 0x3c 0x20 read-write 0x00000000 VAL random number value3 0 32 RAND_NUM4 RAND_NUM4 0x40 0x20 read-write 0x00000000 VAL random number value4 0 32 RAND_NUM5 RAND_NUM5 0x44 0x20 read-write 0x00000000 VAL random number value5 0 32 RAND_NUM6 RAND_NUM6 0x48 0x20 read-write 0x00000000 VAL random number value6 0 32 RAND_NUM7 RAND_NUM7 0x4c 0x20 read-write 0x00000000 VAL random number value7 0 32 CAL_CFG CAL_CFG 0x50 0x20 read-write 0x00000000 LENGTH calibration length 16 16 RSVD 6 10 DONE calibration done 5 1 ENABLE calibration enable 4 1 OSC_CLK_SEL osc clock select 1 3 OSC_CLK_FORCE_ON osc force enable 0 1 CAL_RESULT CAL_RESULT 0x54 0x20 read-write 0x00000000 OSC_CNT osc clock calibration counter result 16 16 PCLK_CNT pclk calibration counter result 0 16 MPI1 MPI 0x50041000 0x0 0x1000 registers CR CR Control Register 0x00 0x20 read-write 0x00000000 ABORT Write 1 to abort internal state machine. For debug purpose only 31 1 RSVD 26 5 AHBDIS Hold hreadyout low if AHB access 25 1 DFM Dual Flash ModeReserved-Do not modify 24 1 MX16 Mode X16Reserved-Do not modify 23 1 PREFE Prefetch enable. If enabled, MPI will prefetch at consequtive address following a read transaction. Recommend to use when reading large data in a burst manner. 0: prefetch disabled 1: prefetch enabled 22 1 OPIE OPI interface enable 0: x8 mode disabled 1: x8 mode enabled 21 1 HWIFE Hardware interface enableReserved-Do not modify 20 1 SMM Status match mode 0: AND mode 1: OR mode 19 1 SME2 Status match enable. If enabled, CMD2 will be issued repeatedly until the data match the value in SMR and SMKR 0: disabled 1: enabled 18 1 SME1 Status match enable. If enabled, CMD1 will be issued repeatedly until the data match the value in SMR and SMKR 0: disabled 1: enabled (either SME1 or SME2 can be enabled, and SME1 has high priority) 17 1 CMD2E Enable CMD2 0: disabled 1: CMD2 is enabled and will be issued after CMD1 with an interval of TI2 16 1 RSVD2 14 2 RBXIE Row boundary crossing interrupt enable 13 1 CSVIE CS max violation interrupt enable 12 1 SMIE Status match interrupt enable 11 1 RSVD3 10 1 RSVD4 9 1 TCIE Transfer complete interrupt enable 8 1 CTRM AES-CTR mode 0: AES-128 1: AES-256 7 1 CTRE AES-CTR on-the-fly decryption enable 0: disabled 1: enabled, data read from memory will be decrypted on the fly by MPI controller 6 1 DMAE DMA enable 0: disabled 1: enable DMA to read or write DR register 5 1 HOLD The value of HOLD when HOLDE is set 4 1 HOLDE Enable HOLD function on IO3. Use this only in SPI or Dual SPI mode 3 1 WP The value of WP when WPE is set 2 1 WPE Enable WP function on IO2. Use this only in SPI or Dual SPI mode 1 1 EN Enable MPI 0 1 DR DR Data Register 0x04 0x20 read-write 0x00000000 DATA The entry of internal data FIFO 0 32 DCR DCR Device Control Register 0x08 0x20 read-write 0x00000000 FIXLAT Indicate PSRAM is fixed latency or variable latency. It must be compatible to the configuration in PSRAM registers. Recommend always set to 1. 0: variable latency 1: fixed latency 31 1 TRCMIN Write/Read cycle minimum time in internal MCLK cycles. Please see MCLK frequency in PSCLR description. For example, if PSRAM clock is 120MHz (i.e. internal MCLK is 240MHz) and TRCMIN = n, then tRC time = (n+1) * 1000/240 ns which must meet minimum tRC requirement for PSRAM 26 5 CSHMIN Minimum CS high deselect time in MCLK cycles. For example, if PSRAM clock is 120MHz (i.e. internal MCLK is 240MHz) and CSHMIN = n, then CS High time = (n+1) * 1000/240 ns which must meet minimum tCPH requirement for PSRAM 22 4 CSLMIN Minimum CS low active time in MCLK cycles. For example, if PSRAM clock is 120MHz (i.e. internal MCLK is 240MHz) and CSLMIN = n, then CS Low time = (n+1) * 1000/240 ns which must meet the minimum tCEM requirement for PSRAM 18 4 CSLMAX Maximum CS low active time in MCLK cycles For example, if PSRAM clock is 120MHz (i.e. internal MCLK is 240MHz) and CSLMAX = n, then CS Low time = (n+1) * 1000/240 ns which must meet the maximum tCEM requirement for PSRAM 6 12 XLEGACY Xccela legacy protocol. Set to 1 for AP 32Mb PSRAM only, othersize always set to 0. 5 1 HYPER HyperBus protocol. Set to 1 for HyperRAM. 4 1 DQSE DQS enable. Setting to 1 indicates device provides DQS signal for Rx data latching 3 1 RBSIZE Row boundary size. 0: no row boundary 1: 2^(1+3) = 16 bytes 2: 2^(2+3) = 32 bytes … n: 2^(n+3) bytes 0 3 PSCLR PSCLR Prescaler Register 0x0c 0x20 read-write 0x00000000 RSVD 8 24 DIV Prescaler divider. 0: MCLK = FCLK/1 1: MCLK = FCLK/1 2: MCLK = FCLK/2 n: MCLK = FCLK/n Note: FLASH clock = MCLK. E.g. FCLK=192M and DIV=2, then FLASH clock = MCLK = 192/2 = 96MHz PSRAM clock = MCLK/2. E.g. FCLK=240M and DIV=1, then PSRAM clock = MCLK/2 = 240/2 = 120MHz 0 8 SR SR Status Register 0x10 0x20 read-write 0x00000006 BUSY For debug purpose only 31 1 RSVD 6 25 RBXF Row boundary crossing flag 5 1 CSVF CS max violation flag 4 1 SMF Status match flag in Polling Mode 3 1 RSVD2 2 1 RSVD3 1 1 TCF Transfer complete flag 0 1 SCR SCR Status Clear Register 0x14 0x20 read-write 0x00000000 RSVD 6 26 RBXFC Write 1 to clear RBXF 5 1 CSVFC Write 1 to clear CSVF 4 1 SMFC Write 1 to clear SMF 3 1 RSVD2 2 1 RSVD3 1 1 TCFC Write 1 to clear TCF 0 1 CMDR1 CMDR1 Command Register 0x18 0x20 read-write 0x00000000 RSVD 8 24 CMD Command. Write to this register will trigger the sequence specified in CCR1 0 8 AR1 AR1 Address Register 0x1c 0x20 read-write 0x00000000 ADDR Address 0 32 ABR1 ABR1 Alternate Byte Register 0x20 0x20 read-write 0x00000000 ABYTE Alternate byte 0 32 DLR1 DLR1 Data Length Register 0x24 0x20 read-write 0x00000000 RSVD 20 12 DLEN Data length 0: one byte 1: two bytes … n: (n+1) bytes 0 20 CCR1 CCR1 Communication Configuration Register 0x28 0x20 read-write 0x00000000 RSVD 22 10 FMODE Function Mode 0: read mode 1: write mode 21 1 DMODE Data Mode 0: no data phase 1: single line 2: dual lines 3: quad lines 4/5/6: reserved 7: quad lines DDR 18 3 DCYC Number of dummy cycles 0: no dummy cycle 1: one dummy cycle 2: two dummy cycles 13 5 ABSIZE Alternate byte size 0: one byte 1: two bytes 2: three bytes 3: four bytes 11 2 ABMODE Alternate byte mode 0: no alternate byte 1: single line 2: dual lines 3: quad lines 4/5/6: reserved 7: quad lines DDR 8 3 ADSIZE Address size 0: one byte 1: two bytes 2: three bytes 3: four bytes 6 2 ADMODE Address mode 0: no address phase 1: single line 2: dual line 3: quad line 4/5/6: reserved 7: quad line DDR 3 3 IMODE Instruction mode 0: no instruction phase 1: single line 2: dual lines 3: quad lines 4/5/6 - reserved 7 - quad lines DDR 0 3 CMDR2 CMDR2 Command Register 0x2c 0x20 read-write 0x00000000 RSVD 8 24 CMD Command 2. If CMD2E is enabled, the CMD2 sequence will be issued after CMD1 as specified in CCR2 Note: CMD2 sequence cannot be issue individually 0 8 AR2 AR2 Address Register 0x30 0x20 read-write 0x00000000 ADDR Address byte in CMD2 sequence 0 32 ABR2 ABR2 Alternate Byte Register 0x34 0x20 read-write 0x00000000 ABYTE Alternate byte in CMD2 sequence 0 32 DLR2 DLR2 Data Length Register 0x38 0x20 read-write 0x00000000 RSVD 20 12 DLEN Data length in CMD2 sequence 0 20 CCR2 CCR2 Communication Configuration Register 0x3c 0x20 read-write 0x00000000 RSVD 22 10 FMODE 21 1 DMODE 18 3 DCYC 13 5 ABSIZE 11 2 ABMODE 8 3 ADSIZE 6 2 ADMODE 3 3 IMODE This register specifies the format of CMD2 sequence. Refer to CCR1 description 0 3 HCMDR HCMDR AHB Command Register 0x40 0x20 read-write 0x00000000 RSVD 16 16 WCMD AHB write command. During XIP, the AHB write transaction will be translated into this Write Command on memory interface 8 8 RCMD AHB read command. During XIP, the AHB read transaction will be translated into this Read Command on memory interface 0 8 HRABR HRABR AHB Read Alternate Byte Register 0x44 0x20 read-write 0x00000000 ABYTE 0 32 HRCCR HRCCR AHB Read Communication Configuration Register 0x48 0x20 read-write 0x00000000 RSVD 21 11 DMODE 18 3 DCYC 13 5 ABSIZE 11 2 ABMODE 8 3 ADSIZE 6 2 ADMODE 3 3 IMODE This register specifies the format of AHB read command sequence. Refer to CCR1 description 0 3 HWABR HWABR AHB Write Alternate Byte Register 0x4c 0x20 read-write 0x00000000 ABYTE 0 32 HWCCR HWCCR AHB Write Communication Configuration Register 0x50 0x20 read-write 0x00000000 RSVD 21 11 DMODE 18 3 DCYC 13 5 ABSIZE 11 2 ABMODE 8 3 ADSIZE 6 2 ADMODE 3 3 IMODE This register specifies the format of AHB write command sequence. Refer to CCR1 description 0 3 FIFOCR FIFOCR FIFO Control Register 0x54 0x20 read-write 0x00000000 RSVD 15 17 TXSLOTS When DMA enabled, asserts DMA reqeust if TXFIFO vacant slots is greater than or equal to TXSLOTS. Note: this field should be set in accordance to the burst length in DMA. For example, if DMA employs BURST8 transction, then this filed is set to 8 10 5 TXF Tx FIFO full flag 9 1 TXCLR write 1 to clear Tx FIFO 8 1 RSVD2 2 6 RXE Rx FIFO empty 1 1 RXCLR write 1 to clear Rx FIFO 0 1 MISCR MISCR Miscelaneous Register 0x58 0x20 read-write 0x00000000 DBGSEL 28 4 RSVD 27 1 DTRPRE Enable pre-sampling for DTRReserved-Do not modify 26 1 SCKINV Invert output clock. This bit is used to align (coarse tune) the output clock to the center of output data. 25 1 RXCLKINV Invert internal Rx clock to add half-cycle delay (coarse tune) when sampling data. It is usually used for FLASH device w/ higher frequency. 24 1 DQSDLY Delay the input DQS signal to the appropriate sampling position. For device w/ DQS signal only. Note: effective 7-bit 16 8 SCKDLY Add delay on output clock to fine tune the clock position. Note: effective 7-bit 8 8 RXCLKDLY Add delay on internal Rx clock to fine tune the sampling position. Note: effective 5-bit 0 8 CTRSAR CTRSAR CTR Starting Address Register 0x5c 0x20 read-write 0x00000000 SA Starting address of the AES decryption area. Since the lowest 10 bits are zero, the address is always 1KB aligned. Together with CTREAR, the total area is [CTRSAR, CTREAR) For example, CTRSAR = 32'h0, CTREAR = 32'h200000, then the on-the-fly decryption area is 0x0 - 0x1FFFFF 10 22 RSVD 0 10 CTREAR CTREAR CTR Ending Address Register 0x60 0x20 read-write 0x00000000 EA Ending address of the AES decryption area 10 22 RSVD 0 10 NONCEA NONCEA Nonce A Register 0x64 0x20 read-write 0x00000000 NONCEA Used for on-the-fly decryption 0 32 NONCEB NONCEB Nonce B Register 0x68 0x20 read-write 0x00000000 NONCEB Used for on-the-fly decryption 0 32 AASAR AASAR Address Aliasing Start Address Register 0x6c 0x20 read-write 0x00000000 SA Starting address of the address aliasing area. Always 1KB aligned.Together with AAEAR, the aliasing area is [AASAR, AAEAR). If the address falls into this area, an offset AAOAR is added and the aliased address will be used to access external memory 10 22 RSVD 0 10 AAEAR AAEAR Address Aliasing Ending Address Register 0x70 0x20 read-write 0x00000000 EA Ending address of the address aliasing area 10 22 RSVD 0 10 AAOAR AAOAR Address Aliasing Offset Address Register 0x74 0x20 read-write 0x00000000 OA The offset to be added to the original address 10 22 RSVD 0 10 CIR CIR Command Interval Register 0x78 0x20 read-write 0x00000000 INTERVAL2 The interval between CMD1 and CMD2 (or between CMD2 itself) if CMD2E is enabled. The unit is in MCLK cycles 16 16 INTERVAL1 The interval between CMD1 itself. The unit is in MCLK cycles 0 16 SMR SMR Status Match Register 0x7c 0x20 read-write 0x00000000 STATUS If status match is enabled, this register is compared with the data read from external memory. Together with SMKR, only the bits with mask=1 will be considered to compare in AND or OR mode as configured in SMM field. 0 32 SMKR SMKR Status Mask Register 0x80 0x20 read-write 0x00000000 MASK Status mask 0: the corresponding bit is not considered to compare 1: the corresponding bit is considered to compare 0 32 TIMR TIMR Timer Register 0x84 0x20 read-write 0x00000000 RSVD 16 16 TIMEOUT After the transaction is complete, CS remains low for multiple cycles of MCLK as specified by this register. For example if TIMEOUT=n, CS remains active for n cycles, during which if a new transaction occurs and the address is consecutive, the memory access can be resumed w/o sending the command and address again. 0 16 WDTR WDTR WDT Register 0x88 0x20 read-write 0x00000000 TOF Timeout flag. Self cleared when HREADYOUT becomes ready 31 1 RSVD 17 14 EN WDT enable. This watchdog is on AHB side such that bus access will not hang in exceptional cases 16 1 TIMEOUT Set timeout value in number of clk_wdt cycles 0 16 PRSAR PRSAR Prefetch Starting Address Register 0x8c 0x20 read-write 0x00000000 SA Starting address of the prefetch area If prefetch is enabled and the read address falls into [PRSAR, PREAR), controller will prefetch the following data 10 22 RSVD 0 10 PREAR PREAR Prefetch Ending Address Register 0x90 0x20 read-write 0x00000000 EA Ending address of the prefetch area 10 22 RSVD 0 10 CALCR CALCR Calibration Clock Register 0x94 0x20 read-write 0x00000000 EN calibration enable 31 1 RSVD 9 22 DONE calibration done flag 8 1 DELAY calibration delay result 0 8 RSVD1 RSVD1 0x98 0x20 read-write 0x0 APM32CR APM32CR APM32 Control Register 0x9c 0x20 read-write 0x00000000 RSVD 8 24 TCPHW For special use by AP 32Mb PSRAM.Reserved-Do not modify 4 4 TCPHR For special use by AP 32Mb PSRAM.Reserved-Do not modify 0 4 CR2 CR2 Control Register 2 0xa0 0x20 read-write 0x00000000 RSVD 8 24 LOOP Repeat CMD1->CMD2 sequence for n times. This filed is only valid when CMD2E=1 and SME2=0. For example if LOOP=0, then the sequence is CMD1 -> CMD2. If LOOP=2, then the sequence is (CMD1->CMD2) -> (CMD1->CMD2) -> (CMD1->CMD2) 0 8 MPI2 MPI 0x50042000 0x0 0x1000 registers CR CR Control Register 0x00 0x20 read-write 0x00000000 ABORT Write 1 to abort internal state machine. For debug purpose only 31 1 RSVD 26 5 AHBDIS Hold hreadyout low if AHB access 25 1 DFM Dual Flash ModeReserved-Do not modify 24 1 MX16 Mode X16Reserved-Do not modify 23 1 PREFE Prefetch enable. If enabled, MPI will prefetch at consequtive address following a read transaction. Recommend to use when reading large data in a burst manner. 0: prefetch disabled 1: prefetch enabled 22 1 OPIE OPI interface enable 0: x8 mode disabled 1: x8 mode enabled 21 1 HWIFE Hardware interface enableReserved-Do not modify 20 1 SMM Status match mode 0: AND mode 1: OR mode 19 1 SME2 Status match enable. If enabled, CMD2 will be issued repeatedly until the data match the value in SMR and SMKR 0: disabled 1: enabled 18 1 SME1 Status match enable. If enabled, CMD1 will be issued repeatedly until the data match the value in SMR and SMKR 0: disabled 1: enabled (either SME1 or SME2 can be enabled, and SME1 has high priority) 17 1 CMD2E Enable CMD2 0: disabled 1: CMD2 is enabled and will be issued after CMD1 with an interval of TI2 16 1 RSVD2 14 2 RBXIE Row boundary crossing interrupt enable 13 1 CSVIE CS max violation interrupt enable 12 1 SMIE Status match interrupt enable 11 1 RSVD3 10 1 RSVD4 9 1 TCIE Transfer complete interrupt enable 8 1 CTRM AES-CTR mode 0: AES-128 1: AES-256 7 1 CTRE AES-CTR on-the-fly decryption enable 0: disabled 1: enabled, data read from memory will be decrypted on the fly by MPI controller 6 1 DMAE DMA enable 0: disabled 1: enable DMA to read or write DR register 5 1 HOLD The value of HOLD when HOLDE is set 4 1 HOLDE Enable HOLD function on IO3. Use this only in SPI or Dual SPI mode 3 1 WP The value of WP when WPE is set 2 1 WPE Enable WP function on IO2. Use this only in SPI or Dual SPI mode 1 1 EN Enable MPI 0 1 DR DR Data Register 0x04 0x20 read-write 0x00000000 DATA The entry of internal data FIFO 0 32 DCR DCR Device Control Register 0x08 0x20 read-write 0x00000000 FIXLAT Indicate PSRAM is fixed latency or variable latency. It must be compatible to the configuration in PSRAM registers. Recommend always set to 1. 0: variable latency 1: fixed latency 31 1 TRCMIN Write/Read cycle minimum time in internal MCLK cycles. Please see MCLK frequency in PSCLR description. For example, if PSRAM clock is 120MHz (i.e. internal MCLK is 240MHz) and TRCMIN = n, then tRC time = (n+1) * 1000/240 ns which must meet minimum tRC requirement for PSRAM 26 5 CSHMIN Minimum CS high deselect time in MCLK cycles. For example, if PSRAM clock is 120MHz (i.e. internal MCLK is 240MHz) and CSHMIN = n, then CS High time = (n+1) * 1000/240 ns which must meet minimum tCPH requirement for PSRAM 22 4 CSLMIN Minimum CS low active time in MCLK cycles. For example, if PSRAM clock is 120MHz (i.e. internal MCLK is 240MHz) and CSLMIN = n, then CS Low time = (n+1) * 1000/240 ns which must meet the minimum tCEM requirement for PSRAM 18 4 CSLMAX Maximum CS low active time in MCLK cycles For example, if PSRAM clock is 120MHz (i.e. internal MCLK is 240MHz) and CSLMAX = n, then CS Low time = (n+1) * 1000/240 ns which must meet the maximum tCEM requirement for PSRAM 6 12 XLEGACY Xccela legacy protocol. Set to 1 for AP 32Mb PSRAM only, othersize always set to 0. 5 1 HYPER HyperBus protocol. Set to 1 for HyperRAM. 4 1 DQSE DQS enable. Setting to 1 indicates device provides DQS signal for Rx data latching 3 1 RBSIZE Row boundary size. 0: no row boundary 1: 2^(1+3) = 16 bytes 2: 2^(2+3) = 32 bytes … n: 2^(n+3) bytes 0 3 PSCLR PSCLR Prescaler Register 0x0c 0x20 read-write 0x00000000 RSVD 8 24 DIV Prescaler divider. 0: MCLK = FCLK/1 1: MCLK = FCLK/1 2: MCLK = FCLK/2 n: MCLK = FCLK/n Note: FLASH clock = MCLK. E.g. FCLK=192M and DIV=2, then FLASH clock = MCLK = 192/2 = 96MHz PSRAM clock = MCLK/2. E.g. FCLK=240M and DIV=1, then PSRAM clock = MCLK/2 = 240/2 = 120MHz 0 8 SR SR Status Register 0x10 0x20 read-write 0x00000006 BUSY For debug purpose only 31 1 RSVD 6 25 RBXF Row boundary crossing flag 5 1 CSVF CS max violation flag 4 1 SMF Status match flag in Polling Mode 3 1 RSVD2 2 1 RSVD3 1 1 TCF Transfer complete flag 0 1 SCR SCR Status Clear Register 0x14 0x20 read-write 0x00000000 RSVD 6 26 RBXFC Write 1 to clear RBXF 5 1 CSVFC Write 1 to clear CSVF 4 1 SMFC Write 1 to clear SMF 3 1 RSVD2 2 1 RSVD3 1 1 TCFC Write 1 to clear TCF 0 1 CMDR1 CMDR1 Command Register 0x18 0x20 read-write 0x00000000 RSVD 8 24 CMD Command. Write to this register will trigger the sequence specified in CCR1 0 8 AR1 AR1 Address Register 0x1c 0x20 read-write 0x00000000 ADDR Address 0 32 ABR1 ABR1 Alternate Byte Register 0x20 0x20 read-write 0x00000000 ABYTE Alternate byte 0 32 DLR1 DLR1 Data Length Register 0x24 0x20 read-write 0x00000000 RSVD 20 12 DLEN Data length 0: one byte 1: two bytes … n: (n+1) bytes 0 20 CCR1 CCR1 Communication Configuration Register 0x28 0x20 read-write 0x00000000 RSVD 22 10 FMODE Function Mode 0: read mode 1: write mode 21 1 DMODE Data Mode 0: no data phase 1: single line 2: dual lines 3: quad lines 4/5/6: reserved 7: quad lines DDR 18 3 DCYC Number of dummy cycles 0: no dummy cycle 1: one dummy cycle 2: two dummy cycles 13 5 ABSIZE Alternate byte size 0: one byte 1: two bytes 2: three bytes 3: four bytes 11 2 ABMODE Alternate byte mode 0: no alternate byte 1: single line 2: dual lines 3: quad lines 4/5/6: reserved 7: quad lines DDR 8 3 ADSIZE Address size 0: one byte 1: two bytes 2: three bytes 3: four bytes 6 2 ADMODE Address mode 0: no address phase 1: single line 2: dual line 3: quad line 4/5/6: reserved 7: quad line DDR 3 3 IMODE Instruction mode 0: no instruction phase 1: single line 2: dual lines 3: quad lines 4/5/6 - reserved 7 - quad lines DDR 0 3 CMDR2 CMDR2 Command Register 0x2c 0x20 read-write 0x00000000 RSVD 8 24 CMD Command 2. If CMD2E is enabled, the CMD2 sequence will be issued after CMD1 as specified in CCR2 Note: CMD2 sequence cannot be issue individually 0 8 AR2 AR2 Address Register 0x30 0x20 read-write 0x00000000 ADDR Address byte in CMD2 sequence 0 32 ABR2 ABR2 Alternate Byte Register 0x34 0x20 read-write 0x00000000 ABYTE Alternate byte in CMD2 sequence 0 32 DLR2 DLR2 Data Length Register 0x38 0x20 read-write 0x00000000 RSVD 20 12 DLEN Data length in CMD2 sequence 0 20 CCR2 CCR2 Communication Configuration Register 0x3c 0x20 read-write 0x00000000 RSVD 22 10 FMODE 21 1 DMODE 18 3 DCYC 13 5 ABSIZE 11 2 ABMODE 8 3 ADSIZE 6 2 ADMODE 3 3 IMODE This register specifies the format of CMD2 sequence. Refer to CCR1 description 0 3 HCMDR HCMDR AHB Command Register 0x40 0x20 read-write 0x00000000 RSVD 16 16 WCMD AHB write command. During XIP, the AHB write transaction will be translated into this Write Command on memory interface 8 8 RCMD AHB read command. During XIP, the AHB read transaction will be translated into this Read Command on memory interface 0 8 HRABR HRABR AHB Read Alternate Byte Register 0x44 0x20 read-write 0x00000000 ABYTE 0 32 HRCCR HRCCR AHB Read Communication Configuration Register 0x48 0x20 read-write 0x00000000 RSVD 21 11 DMODE 18 3 DCYC 13 5 ABSIZE 11 2 ABMODE 8 3 ADSIZE 6 2 ADMODE 3 3 IMODE This register specifies the format of AHB read command sequence. Refer to CCR1 description 0 3 HWABR HWABR AHB Write Alternate Byte Register 0x4c 0x20 read-write 0x00000000 ABYTE 0 32 HWCCR HWCCR AHB Write Communication Configuration Register 0x50 0x20 read-write 0x00000000 RSVD 21 11 DMODE 18 3 DCYC 13 5 ABSIZE 11 2 ABMODE 8 3 ADSIZE 6 2 ADMODE 3 3 IMODE This register specifies the format of AHB write command sequence. Refer to CCR1 description 0 3 FIFOCR FIFOCR FIFO Control Register 0x54 0x20 read-write 0x00000000 RSVD 15 17 TXSLOTS When DMA enabled, asserts DMA reqeust if TXFIFO vacant slots is greater than or equal to TXSLOTS. Note: this field should be set in accordance to the burst length in DMA. For example, if DMA employs BURST8 transction, then this filed is set to 8 10 5 TXF Tx FIFO full flag 9 1 TXCLR write 1 to clear Tx FIFO 8 1 RSVD2 2 6 RXE Rx FIFO empty 1 1 RXCLR write 1 to clear Rx FIFO 0 1 MISCR MISCR Miscelaneous Register 0x58 0x20 read-write 0x00000000 DBGSEL 28 4 RSVD 27 1 DTRPRE Enable pre-sampling for DTRReserved-Do not modify 26 1 SCKINV Invert output clock. This bit is used to align (coarse tune) the output clock to the center of output data. 25 1 RXCLKINV Invert internal Rx clock to add half-cycle delay (coarse tune) when sampling data. It is usually used for FLASH device w/ higher frequency. 24 1 DQSDLY Delay the input DQS signal to the appropriate sampling position. For device w/ DQS signal only. Note: effective 7-bit 16 8 SCKDLY Add delay on output clock to fine tune the clock position. Note: effective 7-bit 8 8 RXCLKDLY Add delay on internal Rx clock to fine tune the sampling position. Note: effective 5-bit 0 8 CTRSAR CTRSAR CTR Starting Address Register 0x5c 0x20 read-write 0x00000000 SA Starting address of the AES decryption area. Since the lowest 10 bits are zero, the address is always 1KB aligned. Together with CTREAR, the total area is [CTRSAR, CTREAR) For example, CTRSAR = 32'h0, CTREAR = 32'h200000, then the on-the-fly decryption area is 0x0 - 0x1FFFFF 10 22 RSVD 0 10 CTREAR CTREAR CTR Ending Address Register 0x60 0x20 read-write 0x00000000 EA Ending address of the AES decryption area 10 22 RSVD 0 10 NONCEA NONCEA Nonce A Register 0x64 0x20 read-write 0x00000000 NONCEA Used for on-the-fly decryption 0 32 NONCEB NONCEB Nonce B Register 0x68 0x20 read-write 0x00000000 NONCEB Used for on-the-fly decryption 0 32 AASAR AASAR Address Aliasing Start Address Register 0x6c 0x20 read-write 0x00000000 SA Starting address of the address aliasing area. Always 1KB aligned.Together with AAEAR, the aliasing area is [AASAR, AAEAR). If the address falls into this area, an offset AAOAR is added and the aliased address will be used to access external memory 10 22 RSVD 0 10 AAEAR AAEAR Address Aliasing Ending Address Register 0x70 0x20 read-write 0x00000000 EA Ending address of the address aliasing area 10 22 RSVD 0 10 AAOAR AAOAR Address Aliasing Offset Address Register 0x74 0x20 read-write 0x00000000 OA The offset to be added to the original address 10 22 RSVD 0 10 CIR CIR Command Interval Register 0x78 0x20 read-write 0x00000000 INTERVAL2 The interval between CMD1 and CMD2 (or between CMD2 itself) if CMD2E is enabled. The unit is in MCLK cycles 16 16 INTERVAL1 The interval between CMD1 itself. The unit is in MCLK cycles 0 16 SMR SMR Status Match Register 0x7c 0x20 read-write 0x00000000 STATUS If status match is enabled, this register is compared with the data read from external memory. Together with SMKR, only the bits with mask=1 will be considered to compare in AND or OR mode as configured in SMM field. 0 32 SMKR SMKR Status Mask Register 0x80 0x20 read-write 0x00000000 MASK Status mask 0: the corresponding bit is not considered to compare 1: the corresponding bit is considered to compare 0 32 TIMR TIMR Timer Register 0x84 0x20 read-write 0x00000000 RSVD 16 16 TIMEOUT After the transaction is complete, CS remains low for multiple cycles of MCLK as specified by this register. For example if TIMEOUT=n, CS remains active for n cycles, during which if a new transaction occurs and the address is consecutive, the memory access can be resumed w/o sending the command and address again. 0 16 WDTR WDTR WDT Register 0x88 0x20 read-write 0x00000000 TOF Timeout flag. Self cleared when HREADYOUT becomes ready 31 1 RSVD 17 14 EN WDT enable. This watchdog is on AHB side such that bus access will not hang in exceptional cases 16 1 TIMEOUT Set timeout value in number of clk_wdt cycles 0 16 PRSAR PRSAR Prefetch Starting Address Register 0x8c 0x20 read-write 0x00000000 SA Starting address of the prefetch area If prefetch is enabled and the read address falls into [PRSAR, PREAR), controller will prefetch the following data 10 22 RSVD 0 10 PREAR PREAR Prefetch Ending Address Register 0x90 0x20 read-write 0x00000000 EA Ending address of the prefetch area 10 22 RSVD 0 10 CALCR CALCR Calibration Clock Register 0x94 0x20 read-write 0x00000000 EN calibration enable 31 1 RSVD 9 22 DONE calibration done flag 8 1 DELAY calibration delay result 0 8 RSVD1 RSVD1 0x98 0x20 read-write 0x0 APM32CR APM32CR APM32 Control Register 0x9c 0x20 read-write 0x00000000 RSVD 8 24 TCPHW For special use by AP 32Mb PSRAM.Reserved-Do not modify 4 4 TCPHR For special use by AP 32Mb PSRAM.Reserved-Do not modify 0 4 CR2 CR2 Control Register 2 0xa0 0x20 read-write 0x00000000 RSVD 8 24 LOOP Repeat CMD1->CMD2 sequence for n times. This filed is only valid when CMD2E=1 and SME2=0. For example if LOOP=0, then the sequence is CMD1 -> CMD2. If LOOP=2, then the sequence is (CMD1->CMD2) -> (CMD1->CMD2) -> (CMD1->CMD2) 0 8 SDMMC1 SDMMC 0x50045000 0x0 0x1000 registers SR SR command and data status register 0x00 0x20 read-write 0x0 RSVD 18 14 CACHE_ERR Detect cache error Read 1: cache error occur Read 0: no cache error Write 1: clear the bit Write 0: no any influence to the bit 17 1 SDIO Detect SDIO Card Interrupt Read 1: detect sdio card generating interrupt Read 0: no interrupt Write 1: clear the bit Write 0: no any influence to the bit 16 1 CARD_EXIST Card exist status Read 1: card exist Read 0: no card exist This bit will be valid after enable detect card. 15 1 CARD_REMOVE Detect card removed Read 1: detect card removed. When detect card inserted bit is set, the bit will also be back to 0 Read 0: no meaning Write 1: clear the bit Write 0: no any influence to the bit 14 1 CARD_INSERT Detect card inserted Read 1: detect card inserted. When detect card removed bit is set, the bit will also be back to 0 Read 0: no meaning Write 1: clear the bit Write 0: no any influence to the bit 13 1 CMD_SENT Command sent (perhaps no response back yet) Read 1: command sent. When command start bit is set, the bit will also be back to 0 Read 0: command transferring or others Write 1: clear the bit Write 0: no any influence to the bit 12 1 RSVD2 11 1 FIFO_OVERRUN FIFO overrun Read 1: FIFO overrun error Read 0: no FIFO overrun error Write 1: clear the bit Write 0: no any influence to the bit 10 1 FIFO_UNDERRUN FIFO underrun Read 1: FIFO underrun error Read 0: no FIFO underrun error Write 1: clear the bit Write 0: no any influence to the bit 9 1 STARTBIT_ERROR Wide bus start bits error Didn't detect all start bits in data bus Read 1: start bits error Read 0: no start bits error Write 1: clear the bit Write 0: no any influence to the bit 8 1 DATA_TIMEOUT Data timeout Read 1: timeout Read 0: no timeout Write 1: clear the bit Write 0: no any influence to the bit 7 1 DATA_CRC Data CRC error Read 1: data CRC error Read 0: data CRC right Write 1: clear the bit Write 0: no any influence to the bit 6 1 DATA_DONE Data transfer done Read 1: transfer data done, and start a new transfer will take the bit into 0 Read 0: data transferring or idle Write 1: clear the bit Write 0: no any influence to the bit 5 1 DATA_BUSY Transfer Data busy 1: busy, and when busy, start transfer data bit is no usage and you should not modify the relative register. If want to do this, first disable transfer data enable bit, then the busy bit will be back to 0, and this transfer will also be cancelled. 0: data idle 4 1 CMD_TIMEOUT Command timeout (response timeout) Read 1: timeout Read 0: no timeout Write 1: clear the bit Write 0: no any influence to the bit 3 1 CMD_RSP_CRC Command response CRC error status Read 1: response CRC error Read 0: response CRC right Write 1: clear the bit Write 0: no any influence to the bit 2 1 CMD_DONE Command done Read 1: transfer command done, and start a new transfer will take the bit into 0 Read 0: command transferring or idle Write 1: clear the bit Write 0: no any influence to the bit 1 1 CMD_BUSY Command busy 1: busy, and when busy, start TX command bit is no usage and should not modify the relative register 0: command idle 0 1 CCR CCR command control register 0x04 0x20 read-write 0x0 RSVD 24 8 CMD_INDEX Command index 18 6 CMD_LONG_RSP 1: Response will be 136-bit, long response 0: Response will be 48-bit, normal response 17 1 CMD_HAS_RSP 1: Response expected after command 0: No response expected after command 16 1 RSVD2 10 6 CMD_PEND Command pending enable When prepare to send stop command, this bit should be set. Controller will calculate a proper time point to send out the command to guarantee all the data have been transferred. And this is mainly used in stream mode. Recommend using set_block_count (SD/MMC basis command) to control transferring data for block mode. If send stop command for canceling this transfer (such as CRC error in multi-block), no need to set the bit. 9 1 CMD_TX_EN TX command enable 1: enable TX command 0: disable TX command 8 1 RSVD3 1 7 CMD_START Command start write 1 to start command TX, and when begin to TX command, the bit will return into 0. 0 1 CAR CAR command argument register 0x08 0x20 read-write 0x0 CMD_ARG Command argument 0 32 RIR RIR response command index register 0x0c 0x20 read-write 0x0 RSVD 6 26 RSP_INDEX Response command index 0 6 RAR1 RAR1 response command argument1 register 0x10 0x20 read-write 0x0 RSP_ARG1 Response command content If long response, it is rsp_arg[39:8] 0 32 RAR2 RAR2 response command argument2 register 0x14 0x20 read-write 0x0 RSP_ARG2 Long response, it is rsp_arg[71:40] 0 32 RAR3 RAR3 response command argument3 register 0x18 0x20 read-write 0x0 RSP_ARG3 Long response, it is rsp_arg[103:72] 0 32 RAR4 RAR4 response command argument4 register 0x1c 0x20 read-write 0x0 RSVD 24 8 RSP_ARG4 Long response, it is rsp_arg[127:104] 0 24 TOR TOR timeout count register 0x20 0x20 read-write 0x0 TIMEOUT_CNT Used to determine how much time waiting response or data bus busy is timeout, and decreased under card clock. Set to 400000 for 1s timeout if interface clock is 400KHz. 0 32 DCR DCR data control register 0x24 0x20 read-write 0x0 RSVD 27 5 BLOCK_SIZE Data block size is block_size+1 (max 2048 bytes) 0: 1 byte 0x1ff: 512 bytes 16 11 RSVD2 13 3 WIRE_MODE Wide data bus mode 00: 1 wire bus 01: 4 wires wide bus 1X: reserved 11 2 STREAM_MODE Data transfer mode 0: block 1: stream 10 1 R_WN Write or read 0: write data into card 1: read data from card 9 1 TRAN_DATA_EN Transfer data enable 0: disable transfer data. After disable data transfer, stop command should be sent to card 1: enable data transfer 8 1 RSVD3 1 7 DATA_START Start transfer data set 1 to let the controller begin to transfer data (in fact, go into wait write or wait read state). After begin to transfer, this bit will be back to 0. 0 1 DLR DLR data length register 0x28 0x20 read-write 0x0 BLOCK_TRAN_NUM The number of blocks which have been transferred successfully 1 = 1 block transferred It is cleared when start transfer data bit is set. 16 16 DATA_LEN Data length value. The number of data bytes is data_len+1. The number of data bytes should be a multiple of data block size. 0 is 1 byte. 0x1ff is 512 bytes. Max is 63.5KB. 0 16 IER IER command and data interrupt mask register 0x2c 0x20 read-write 0x0 RSVD 18 14 CACHE_ERR_MASK cache error mask for interrupt 17 1 SDIO_MASK Detect SDIO interrupt(data[1]) mask for interrupt 16 1 RSVD2 15 1 CARD_REMOVE_MASK Detect card remove mask for interrupt 14 1 CARD_INSERT_MASK Detect card insert mask for interrupt 13 1 CMD_SENT_MASK Command sent mask for interrupt 12 1 RSVD3 11 1 FIFO_OVERRUN_MASK FIFO overrun bit mask for interrupt 10 1 FIFO_UNDERRUN_MASK FIFO underrun bit mask for interrupt 9 1 STARTBIT_ERROR_MASK Wide bus start bits error bit mask for interrupt 8 1 DATA_TIMEOUT_MASK Data timeout bit mask for interrupt 7 1 DATA_CRC_MASK Data CRC error bit mask for interrupt 6 1 DATA_DONE_MASK Data transfer done bit mask for interrupt 5 1 RSVD4 4 1 CMD_TIMEOUT_MASK Command timeout bit mask for interrupt 3 1 CMD_RSP_CRC_MASK Command CRC error bit mask for interrupt 2 1 CMD_DONE_MASK Command done bit mask for interrupt 1 1 RSVD5 0 1 CLKCR CLKCR clock control register 0x30 0x20 read-write 0x0 RSVD 21 11 DIV Divide card clock counter. 0 is illegal. sd_clock = hclk/(div + 1) If hclk is 240M and div is 599, 400KHz SD clock will be generated. 8 13 RSVD2 4 4 CLK_TUNE_SEL select clock delay for rx sample 0: no delay 1: delay level 1 (~1.5ns typical) 2: delay level 2 (~3ns typical) 3: delay level 3 (~5ns typical) 2 2 VOID_FIFO_ERROR Void FIFO error 0: close the function 1: open the function If open it, when FIFO will be overrun or underrun soon, the SD_CLK and the clock enable of this module will be closed, and wait to host to read or write FIFO. Note: this function needs to be supported by card. 1 1 STOP_CLK Disable SD card clock 1: stop SD card clock 0: SD card clock generated 0 1 RSVD3 RSVD3 0x34 0x20 read-write 0x0 CDR CDR card interface control and card detect register 0x3c 0x20 read-write 0x0 OTIMING define output timing 19 13 ITIMING define input timing 6 13 CMD_OD Open Drain mode for cmd line (for eMMC identification mode) 0: cmd line is push-pull 1: cmd line is open-drain 5 1 CD_HVALID Card detect high level valid 0: detect low level means card exist 1: detect high level means card exist (default) 4 1 EN_CD Enable card detect Only when the bit is valid, controller does card detect. If use sd_data[3] to do card detect, the bit should be cleared when transfer valid data. 3 1 OTIMING_SEL select output timing (according to otiming config) 2 1 ITIMING_SEL select input sample timing (according to itiming config) 1 1 SD_DATA3_CD Use sd_data[3] to do card detect 0: use special pin to do card detect / write protect. (Currently not supported) 1: use sd_data[3] to do card detect (default) 0 1 DBGR1 DBGR1 card debug port1 register 0x40 0x20 read-write 0x0 RSVD 31 1 DATA_ST data state for debug only 16 15 CMD_ST command state for debug only 0 16 DBGR2 DBGR2 card debug port2 register 0x44 0x20 read-write 0x0 DBG_SEL for debug only 30 2 RSVD 26 4 VALID_DATA_COU for debug only 16 10 RSVD2 14 2 HOST_WORD_COUNTER for debug only 0 14 CEATA CEATA CE-ATA/SDIO mode register 0x48 0x20 read-write 0x0 RSVD 4 28 SDIO_4WIRES_MULTI_IRQ Select the sdio host 4 wires interrupt on multi-block support 0: host not support 4 wires interrupt on multi-block data transfers 1: host support 4 wires interrupt on multi-block data transfers 3 1 SDIO_4WIRES_IRQ Select the sdio host 4 wires interrupt support 0: host not support 4 wires interrupt on single-block data transfers 1: host support 4 wires interrupt on single-block data transfers 2 1 ENABLE_SDIO_IRQ Select the sdio card mode, default is sd card 0: sd card mode , no sdio card interrupt 1: sdio card mode , enable sdio card interrupt 1 1 ATA_MODE Select the card type, default is sd card 0: sd card mode 1: CE-ATA device mode 0 1 RSVD2 RSVD2 0x4C 0x20 read-write 0x0 DSR DSR data status register 0x54 0x20 read-write 0x00000000 RSVD 8 24 SD_DATA_I_LL The status of each sd data pad status 0 8 CDCR CDCR clock duty cycle register 0x58 0x20 read-write 0x00000001 RSVD 1 31 CLK_CONFIG 1: the sd clock is 50% duty cycle 0: the high level of the sd clock is 1 hclk cycle 0 1 CASR CASR cache status register 0x5c 0x20 read-write 0x00000000 RSVD 4 28 CACHE_FLUSH Set 1 to flush cache. Should set when cache not busy. 3 1 CACHE_BUSY Indicates cache is working 2 1 SD_BUSY Read 1 indicates sd is ready for normal access. Ahb access will be hold during sd_busy asserted. After sd normal access done, write 1 to clear, and ahb access will continue 1 1 SD_REQ Set 1 to request sd normal access. sd_req will be cleared automatically after sd_busy asserted 0 1 CACR CACR cache control register 0x60 0x20 read-write 0xd0844c52 CACHE_EN enable cache 1: ahb read will return cached data 0: ahb read always return dummy data with no error response 31 1 CACHE_TO_EN enable ahb read timeout recover 30 1 CACHE_FORCE_READ force cache read done 1: start new fetch for miss access only after cache read done 0: start new fetch for miss access even when cache is still filling (read will be breaked by cmd12) 29 1 CACHE_SDSC select card version 1: card size (=2GB, address of cmd18 is in byte 0: card size >2GB, address of cmd18 is in block 28 1 CACHE_NOCRC 1: return ahb data without crc check 0: return ahb data after block crc pass 27 1 CACHE_HRESP 1: generate ahb error response when error occur 0: no ahb error response generated. Could check cache_err interrupt 26 1 RSVD 24 2 CACHE_PREF_BLOCK cache prefetch depth is cache_pref_block blocks. Should be no less than cache_block 20 4 RSVD2 19 1 CACHE_BLOCK cache depth is cache_block blocks 16 3 STOP_LONG_RSP Stop response is 136-bit, long response 15 1 STOP_HAS_RSP Stop command have a response 14 1 STOP_INDEX Command index for stop. CMD12 by default 8 6 READ_LONG_RSP Read response is 136-bit, long response 7 1 READ_HAS_RSP Read command have a response 6 1 READ_INDEX Command index for cache read. CMD18 by default 0 6 CACNT CACNT cache counter register 0x64 0x20 read-write 0xffff0020 CACHE_TOR timeout count register for ahb read 16 16 CACHE_NDC data-cmd interval counter in hclk cycles 8 8 CACHE_NCC cmd-cmd interval counter in hclk cycles 0 8 CAOFF CAOFF cache offset register 0x68 0x20 read-write 0x00000000 CACHE_OFFSET offset to map ahb address to sd address for ahb access 0 32 RSVD1 RSVD1 0x6C 0x20 read-write 0x0 FIFO FIFO FIFO entry 0x200 0x20 read-write 0x00000000 DATA Entry to access internal FIFO. Access should be word-aligned, ranging from 0x200 to 0x3fc. Inside the range, write to any address will push the data into the FIFO, and read any address will pop a word from the FIFO. 0 32 CRC1 CRC 0x50048000 0x0 0x1000 registers DR DR Data register 0x00 0x20 read-write 0x0 DR Data register bits. This register is used to write new data to the CRC calculator. It holds the previous CRC calculation result when it is read. If the data size is less than 32 bits, the least significant bits are used to write/read the correct value. 0 32 SR SR Status register 0x04 0x20 read-write 0x0 RSVD 2 30 OVERFLOW Overflow when new data arrive while last calculation not done yet 1 1 DONE Done flag. When DR written, done flag will be cleared automatically. The flag will assert after CRC operation of current DR finished. 0 1 CR CR Control register 0x08 0x20 read-write 0x0 RSVD 8 24 REV_OUT Reverse output data This bit controls the reversal of the bit order of the output data. 0: Bit order not affected 1: Bit-reversed output format 7 1 REV_IN Reverse input data These bits control the reversal of the bit order of the input data 00: Bit order not affected 01: Bit reversal done by byte 10: Bit reversal done by half-word 11: Bit reversal done by word 5 2 POLYSIZE Polynomial size These bits control the size of the polynomial. 00: 32 bit polynomial 01: 16 bit polynomial 10: 8 bit polynomial 11: 7 bit polynomial 3 2 DATASIZE Valid input data size These bits control the valid size of the input data. 00: lower 8-bit 01: lower 16-bit 10: lower 24-bit 11: all 32-bit 1 2 RESET This bit is set by software to reset the CRC calculation unit and set the data register to the value stored in the CRC_INIT register. This bit can only be set, it is automatically cleared by hardware 0 1 RSVD1 RSVD1 0xC 0x20 read-write 0x0 INIT INIT Initial CRC value 0x10 0x20 read-write 0x0 INIT Programmable initial CRC value 0 32 POL POL CRC polynomial 0x14 0x20 read-write 0x0 POL Programmable polynomial This register is used to write the coefficients of the polynomial to be used for CRC calculation. If the polynomial size is less than 32 bits, the least significant bits have to be used to program the correct value. 0 32 PTC1 PTC 0x50080000 0x0 0x1000 registers ISR ISR interrupt status register 0x00 0x20 read-write 0x00000000 RSVD 24 8 TEIF8 transfer error flag for task 8 23 1 TEIF7 transfer error flag for task 7 22 1 TEIF6 transfer error flag for task 6 21 1 TEIF5 transfer error flag for task 5 20 1 TEIF4 transfer error flag for task 4 19 1 TEIF3 transfer error flag for task 3 18 1 TEIF2 transfer error flag for task 2 17 1 TEIF1 transfer error flag for task 1 16 1 RSVD2 8 8 TCIF8 task complete interrupt flag for task 8 7 1 TCIF7 task complete interrupt flag for task 7 6 1 TCIF6 task complete interrupt flag for task 6 5 1 TCIF5 task complete interrupt flag for task 5 4 1 TCIF4 task complete interrupt flag for task 4 3 1 TCIF3 task complete interrupt flag for task 3 2 1 TCIF2 task complete interrupt flag for task 2 1 1 TCIF1 task complete interrupt flag for task 1 0 1 ICR ICR interrupt clear register 0x04 0x20 read-write 0x00000000 RSVD 17 15 CTEIF clear transfer error flag 16 1 RSVD2 8 8 CTCIF8 clear task complete interrupt flag for task 8 7 1 CTCIF7 clear task complete interrupt flag for task 7 6 1 CTCIF6 clear task complete interrupt flag for task 6 5 1 CTCIF5 clear task complete interrupt flag for task 5 4 1 CTCIF4 clear task complete interrupt flag for task 4 3 1 CTCIF3 clear task complete interrupt flag for task 3 2 1 CTCIF2 clear task complete interrupt flag for task 2 1 1 CTCIF1 clear task complete interrupt flag for task 1 0 1 IER IER interrupt enable register 0x08 0x20 read-write 0x00000000 RSVD 17 15 TEIE enable transfer error flag 16 1 RSVD2 8 8 TCIE8 enable task complete interrupt for task 8 7 1 TCIE7 enable task complete interrupt for task 7 6 1 TCIE6 enable task complete interrupt for task 6 5 1 TCIE5 enable task complete interrupt for task 5 4 1 TCIE4 enable task complete interrupt for task 4 3 1 TCIE3 enable task complete interrupt for task 3 2 1 TCIE2 enable task complete interrupt for task 2 1 1 TCIE1 enable task complete interrupt for task 1 0 1 RSVD2 RSVD2 0xC 0x20 read-write 0x0 TCR1 TCR1 task 1 control register 0x10 0x20 read-write 0x00000000 RSVD 24 8 REPIRQ repetition interrupt 0: interrupt will be generated after each operation 1: interrupt will be generated after operation for REP times 23 1 REPTRIG repetition trigger 0: ptc trigger will be generated after each operation 1: ptc trigger will be generated after operation for REP times 22 1 REPEN repetition enable 0: task will be triggerd no matter what value REP is 1: task will only be triggerd when REP is not 0 21 1 SWTRIG software trigger task will be triggerd at once after SWTRIG set. SWTRIG will be cleared automatically. 20 1 TRIGPOL trigger polarity 0: select positive edge of trigger 1: select negative edge of trigger 19 1 OP task operation 3'b000: direct write data 3'b100: read then XOR with data and write back 3'b101: read then OR with data and write back 3'b110: read then AND with data and write back 3'b111: read then add with data and write back 16 3 RSVD2 8 8 TRIGSEL select trigger source 0: task will only be triggered by SWTRIG others: task will be triggered by selected source or SWTRIG 0 8 TAR1 TAR1 task 1 address register 0x14 0x20 read-write 0x00000000 ADDR peripheral address to access to 0 32 TDR1 TDR1 task 1 data register 0x18 0x20 read-write 0x00000000 DATA data value for task operation 0 32 RCR1 RCR1 task 1 repetition and delay counter register 0x1c 0x20 read-write 0x00000000 DLY Delay time before task operation after triggered 0: no delay others: delay DLY HCLK cycles before task operation DLY is read as left delay time. DLY will be reloaded automatically after each operation. 16 16 RSVD 10 6 REP Repetition counter value if REPEN is 1, task will only be triggerd when REP is not 0. when REP is larger than 0, it will be decrease by 1 automatically each time task triggered. 0 10 TCR2 TCR2 0x20 0x20 read-write 0x00000000 RSVD 24 8 REPIRQ repetition interrupt 0: interrupt will be generated after each operation 1: interrupt will be generated after operation for REP times 23 1 REPTRIG repetition trigger 0: ptc trigger will be generated after each operation 1: ptc trigger will be generated after operation for REP times 22 1 REPEN repetition enable 0: task will be triggerd no matter what value REP is 1: task will only be triggerd when REP is not 0 21 1 SWTRIG software trigger task will be triggerd at once after SWTRIG set. SWTRIG will be cleared automatically. 20 1 TRIGPOL trigger polarity 0: select positive edge of trigger 1: select negative edge of trigger 19 1 OP task operation 3'b000: direct write data 3'b100: read then XOR with data and write back 3'b101: read then OR with data and write back 3'b110: read then AND with data and write back 3'b111: read then add with data and write back 16 3 RSVD2 8 8 TRIGSEL select trigger source 0 8 TAR2 TAR2 0x24 0x20 read-write 0x00000000 ADDR peripheral address to access to 0 32 TDR2 TDR2 0x28 0x20 read-write 0x00000000 DATA data value for task operation 0 32 RCR2 RCR2 task 2 repetition and delay counter register 0x2c 0x20 read-write 0x00000000 DLY Delay time before task operation after triggered 0: no delay others: delay DLY HCLK cycles before task operation DLY is read as left delay time. DLY will be reloaded automatically after each operation. 16 16 RSVD 10 6 REP Repetition counter value if REPEN is 1, task will only be triggerd when REP is not 0. when REP is larger than 0, it will be decrease by 1 automatically each time task triggered. 0 10 TCR3 TCR3 0x30 0x20 read-write 0x00000000 RSVD 24 8 REPIRQ repetition interrupt 0: interrupt will be generated after each operation 1: interrupt will be generated after operation for REP times 23 1 REPTRIG repetition trigger 0: ptc trigger will be generated after each operation 1: ptc trigger will be generated after operation for REP times 22 1 REPEN repetition enable 0: task will be triggerd no matter what value REP is 1: task will only be triggerd when REP is not 0 21 1 SWTRIG software trigger task will be triggerd at once after SWTRIG set. SWTRIG will be cleared automatically. 20 1 TRIGPOL trigger polarity 0: select positive edge of trigger 1: select negative edge of trigger 19 1 OP task operation 3'b000: direct write data 3'b100: read then XOR with data and write back 3'b101: read then OR with data and write back 3'b110: read then AND with data and write back 3'b111: read then add with data and write back 16 3 RSVD2 8 8 TRIGSEL select trigger source 0 8 TAR3 TAR3 0x34 0x20 read-write 0x00000000 ADDR peripheral address to access to 0 32 TDR3 TDR3 0x38 0x20 read-write 0x00000000 DATA data value for task operation 0 32 RCR3 RCR3 task 3 repetition and delay counter register 0x3c 0x20 read-write 0x00000000 DLY Delay time before task operation after triggered 0: no delay others: delay DLY HCLK cycles before task operation DLY is read as left delay time. DLY will be reloaded automatically after each operation. 16 16 RSVD 10 6 REP Repetition counter value if REPEN is 1, task will only be triggerd when REP is not 0. when REP is larger than 0, it will be decrease by 1 automatically each time task triggered. 0 10 TCR4 TCR4 0x40 0x20 read-write 0x00000000 RSVD 24 8 REPIRQ repetition interrupt 0: interrupt will be generated after each operation 1: interrupt will be generated after operation for REP times 23 1 REPTRIG repetition trigger 0: ptc trigger will be generated after each operation 1: ptc trigger will be generated after operation for REP times 22 1 REPEN repetition enable 0: task will be triggerd no matter what value REP is 1: task will only be triggerd when REP is not 0 21 1 SWTRIG software trigger task will be triggerd at once after SWTRIG set. SWTRIG will be cleared automatically. 20 1 TRIGPOL trigger polarity 0: select positive edge of trigger 1: select negative edge of trigger 19 1 OP task operation 3'b000: direct write data 3'b100: read then XOR with data and write back 3'b101: read then OR with data and write back 3'b110: read then AND with data and write back 3'b111: read then add with data and write back 16 3 RSVD2 8 8 TRIGSEL select trigger source 0 8 TAR4 TAR4 0x44 0x20 read-write 0x00000000 ADDR peripheral address to access to 0 32 TDR4 TDR4 0x48 0x20 read-write 0x00000000 DATA data value for task operation 0 32 RCR4 RCR4 task 4 repetition and delay counter register 0x4c 0x20 read-write 0x00000000 DLY Delay time before task operation after triggered 0: no delay others: delay DLY HCLK cycles before task operation DLY is read as left delay time. DLY will be reloaded automatically after each operation. 16 16 RSVD 10 6 REP Repetition counter value if REPEN is 1, task will only be triggerd when REP is not 0. when REP is larger than 0, it will be decrease by 1 automatically each time task triggered. 0 10 TCR5 TCR5 0x50 0x20 read-write 0x00000000 RSVD 24 8 REPIRQ repetition interrupt 0: interrupt will be generated after each operation 1: interrupt will be generated after operation for REP times 23 1 REPTRIG repetition trigger 0: ptc trigger will be generated after each operation 1: ptc trigger will be generated after operation for REP times 22 1 REPEN repetition enable 0: task will be triggerd no matter what value REP is 1: task will only be triggerd when REP is not 0 21 1 SWTRIG software trigger task will be triggerd at once after SWTRIG set. SWTRIG will be cleared automatically. 20 1 TRIGPOL trigger polarity 0: select positive edge of trigger 1: select negative edge of trigger 19 1 OP task operation 3'b000: direct write data 3'b100: read then XOR with data and write back 3'b101: read then OR with data and write back 3'b110: read then AND with data and write back 3'b111: read then add with data and write back 16 3 RSVD2 8 8 TRIGSEL select trigger source 0 8 TAR5 TAR5 0x54 0x20 read-write 0x00000000 ADDR peripheral address to access to 0 32 TDR5 TDR5 0x58 0x20 read-write 0x00000000 DATA data value for task operation 0 32 RCR5 RCR5 task 5 repetition counter register 0x5c 0x20 read-write 0x00000000 RSVD 10 22 REP Repetition counter value if REPEN is 1, task will only be triggerd when REP is not 0. when REP is larger than 0, it will be decrease by 1 automatically each time task triggered. 0 10 TCR6 TCR6 0x60 0x20 read-write 0x00000000 RSVD 24 8 REPIRQ repetition interrupt 0: interrupt will be generated after each operation 1: interrupt will be generated after operation for REP times 23 1 REPTRIG repetition trigger 0: ptc trigger will be generated after each operation 1: ptc trigger will be generated after operation for REP times 22 1 REPEN repetition enable 0: task will be triggerd no matter what value REP is 1: task will only be triggerd when REP is not 0 21 1 SWTRIG software trigger task will be triggerd at once after SWTRIG set. SWTRIG will be cleared automatically. 20 1 TRIGPOL trigger polarity 0: select positive edge of trigger 1: select negative edge of trigger 19 1 OP task operation 3'b000: direct write data 3'b100: read then XOR with data and write back 3'b101: read then OR with data and write back 3'b110: read then AND with data and write back 3'b111: read then add with data and write back 16 3 RSVD2 8 8 TRIGSEL select trigger source 0 8 TAR6 TAR6 0x64 0x20 read-write 0x00000000 ADDR peripheral address to access to 0 32 TDR6 TDR6 0x68 0x20 read-write 0x00000000 DATA data value for task operation 0 32 RCR6 RCR6 task 6 repetition counter register 0x6c 0x20 read-write 0x00000000 RSVD 10 22 REP Repetition counter value if REPEN is 1, task will only be triggerd when REP is not 0. when REP is larger than 0, it will be decrease by 1 automatically each time task triggered. 0 10 TCR7 TCR7 0x70 0x20 read-write 0x00000000 RSVD 24 8 REPIRQ repetition interrupt 0: interrupt will be generated after each operation 1: interrupt will be generated after operation for REP times 23 1 REPTRIG repetition trigger 0: ptc trigger will be generated after each operation 1: ptc trigger will be generated after operation for REP times 22 1 REPEN repetition enable 0: task will be triggerd no matter what value REP is 1: task will only be triggerd when REP is not 0 21 1 SWTRIG software trigger task will be triggerd at once after SWTRIG set. SWTRIG will be cleared automatically. 20 1 TRIGPOL trigger polarity 0: select positive edge of trigger 1: select negative edge of trigger 19 1 OP task operation 3'b000: direct write data 3'b100: read then XOR with data and write back 3'b101: read then OR with data and write back 3'b110: read then AND with data and write back 3'b111: read then add with data and write back 16 3 RSVD2 8 8 TRIGSEL select trigger source 0 8 TAR7 TAR7 0x74 0x20 read-write 0x00000000 ADDR peripheral address to access to 0 32 TDR7 TDR7 0x78 0x20 read-write 0x00000000 DATA data value for task operation 0 32 RCR7 RCR7 task 7 repetition counter register 0x7c 0x20 read-write 0x00000000 RSVD 10 22 REP Repetition counter value if REPEN is 1, task will only be triggerd when REP is not 0. when REP is larger than 0, it will be decrease by 1 automatically each time task triggered. 0 10 TCR8 TCR8 0x80 0x20 read-write 0x00000000 RSVD 24 8 REPIRQ repetition interrupt 0: interrupt will be generated after each operation 1: interrupt will be generated after operation for REP times 23 1 REPTRIG repetition trigger 0: ptc trigger will be generated after each operation 1: ptc trigger will be generated after operation for REP times 22 1 REPEN repetition enable 0: task will be triggerd no matter what value REP is 1: task will only be triggerd when REP is not 0 21 1 SWTRIG software trigger task will be triggerd at once after SWTRIG set. SWTRIG will be cleared automatically. 20 1 TRIGPOL trigger polarity 0: select positive edge of trigger 1: select negative edge of trigger 19 1 OP task operation 3'b000: direct write data 3'b100: read then XOR with data and write back 3'b101: read then OR with data and write back 3'b110: read then AND with data and write back 3'b111: read then add with data and write back 16 3 RSVD2 8 8 TRIGSEL select trigger source 0 8 TAR8 TAR8 0x84 0x20 read-write 0x00000000 ADDR peripheral address to access to 0 32 TDR8 TDR8 0x88 0x20 read-write 0x00000000 DATA data value for task operation 0 32 RCR8 RCR8 task 8 repetition counter register 0x8c 0x20 read-write 0x00000000 RSVD 10 22 REP Repetition counter value if REPEN is 1, task will only be triggerd when REP is not 0. when REP is larger than 0, it will be decrease by 1 automatically each time task triggered. 0 10 RSVD1 RSVD1 0x90 0x20 read-write 0x0 MEM1 MEM1 temporary memory 1 0xd0 0x20 read-write 0x00000000 DATA memory to store temporary variables 0 32 MEM2 MEM2 temporary memory 2 0xd4 0x20 read-write 0x00000000 DATA memory to store temporary variables 0 32 MEM3 MEM3 temporary memory 3 0xd8 0x20 read-write 0x00000000 DATA memory to store temporary variables 0 32 MEM4 MEM4 temporary memory 4 0xdc 0x20 read-write 0x00000000 DATA memory to store temporary variables 0 32 GPIO31_0 GPIO31_0 0xe0 0x20 read-write 0x00000000 RSVD 29 3 SELD select trigger D of GPIO 31~0 24 5 RSVD2 21 3 SELC select trigger C of GPIO 31~0 16 5 RSVD3 13 3 SELB select trigger B of GPIO 31~0 8 5 RSVD4 5 3 SELA select trigger A of GPIO 31~0 0: select GPIO 0 1: select GPIO 1 ...... 31: select GPIO 31 0 5 GPIO63_32 GPIO63_32 0xe4 0x20 read-write 0x00000000 RSVD 29 3 SELD select trigger D of GPIO 63~32 24 5 RSVD2 21 3 SELC select trigger C of GPIO 63~32 16 5 RSVD3 13 3 SELB select trigger B of GPIO 63~32 8 5 RSVD4 5 3 SELA select trigger A of GPIO 63~32 0: select GPIO 32 1: select GPIO 33 ...... 31: select GPIO 63 0 5 GPIO95_64 GPIO95_64 0xe8 0x20 read-write 0x00000000 RSVD 29 3 SELD select trigger D of GPIO 95~64 24 5 RSVD2 21 3 SELC select trigger C of GPIO 95~64 16 5 RSVD3 13 3 SELB select trigger B of GPIO 95~64 8 5 RSVD4 5 3 SELA select trigger A of GPIO 95~64 0: select GPIO 64 1: select GPIO 65 ...... 31: select GPIO 95 0 5 DMAC1 DMAC 0x50081000 0x0 0x1000 registers ISR ISR 0x00 0x20 read-write 0x00000000 TEIF8 channel transfer error flag 31 1 HTIF8 channel half transfer flag 30 1 TCIF8 channel transfer complete flag 29 1 GIF8 channel global interrupt flag 28 1 TEIF7 channel transfer error flag 27 1 HTIF7 channel half transfer flag 26 1 TCIF7 channel transfer complete flag 25 1 GIF7 channel global interrupt flag 24 1 TEIF6 channel transfer error flag 23 1 HTIF6 channel half transfer flag 22 1 TCIF6 channel transfer complete flag 21 1 GIF6 channel global interrupt flag 20 1 TEIF5 channel transfer error flag 19 1 HTIF5 channel half transfer flag 18 1 TCIF5 channel transfer complete flag 17 1 GIF5 channel global interrupt flag 16 1 TEIF4 channel transfer error flag 15 1 HTIF4 channel half transfer flag 14 1 TCIF4 channel transfer complete flag 13 1 GIF4 channel global interrupt flag 12 1 TEIF3 channel transfer error flag 11 1 HTIF3 channel half transfer flag 10 1 TCIF3 channel transfer complete flag 9 1 GIF3 channel global interrupt flag 8 1 TEIF2 channel transfer error flag 7 1 HTIF2 channel half transfer flag 6 1 TCIF2 channel transfer complete flag 5 1 GIF2 channel global interrupt flag 4 1 TEIF1 channel transfer error flag. Set when bus error detected. Cleared when write 1 to CTEIF or CGIF. 3 1 HTIF1 channel half transfer flag. Set when half NDT are transferred. Cleared when write 1 to CHTIF or CGIF. 2 1 TCIF1 channel transfer complete flag. Set when all NDT are transferred. Cleared when write 1 to CTCIF or CGIF. 1 1 GIF1 channel global interrupt flag. Set when any of TEIF/HTIF/TCIF asserted. Cleared when TEIF/HTIF/TCIF all cleared. 0 1 IFCR IFCR 0x04 0x20 read-write 0x00000000 CTEIF8 CTEIF, transfer error flag clear 31 1 CHTIF8 CHTIF, half transfer flag clear 30 1 CTCIF8 CTCIF, transfer complete flag clear 29 1 CGIF8 CGIF, global interrupt flag clear 28 1 CTEIF7 CTEIF, transfer error flag clear 27 1 CHTIF7 CHTIF, half transfer flag clear 26 1 CTCIF7 CTCIF, transfer complete flag clear 25 1 CGIF7 CGIF, global interrupt flag clear 24 1 CTEIF6 CTEIF, transfer error flag clear 23 1 CHTIF6 CHTIF, half transfer flag clear 22 1 CTCIF6 CTCIF, transfer complete flag clear 21 1 CGIF6 CGIF, global interrupt flag clear 20 1 CTEIF5 CTEIF, transfer error flag clear 19 1 CHTIF5 CHTIF, half transfer flag clear 18 1 CTCIF5 CTCIF, transfer complete flag clear 17 1 CGIF5 CGIF, global interrupt flag clear 16 1 CTEIF4 CTEIF, transfer error flag clear 15 1 CHTIF4 CHTIF, half transfer flag clear 14 1 CTCIF4 CTCIF, transfer complete flag clear 13 1 CGIF4 CGIF, global interrupt flag clear 12 1 CTEIF3 CTEIF, transfer error flag clear 11 1 CHTIF3 CHTIF, half transfer flag clear 10 1 CTCIF3 CTCIF, transfer complete flag clear 9 1 CGIF3 CGIF, global interrupt flag clear 8 1 CTEIF2 CTEIF, transfer error flag clear 7 1 CHTIF2 CHTIF, half transfer flag clear 6 1 CTCIF2 CTCIF, transfer complete flag clear 5 1 CGIF2 CGIF, global interrupt flag clear 4 1 CTEIF1 CTEIF, transfer error flag clear. Write 1 to clear TEIF. 3 1 CHTIF1 CHTIF, half transfer flag clear. Write 1 to clear HTIF. 2 1 CTCIF1 CTCIF, transfer complete flag clear. Write 1 to clear TCIF. 1 1 CGIF1 CGIF, global interrupt flag clear. Write 1 to clear all TEIF/HTIF/TCIF. 0 1 CCR1 CCR1 0x08 0x20 read-write 0x00000000 RSVD 15 17 MEM2MEM memory-to-memory mode 0: disabled 1: enabled 14 1 PL priority level 00: low 01: medium 10: high 11: very high 12 2 MSIZE memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved 10 2 PSIZE peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved 8 2 MINC memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 0: disabled 1: enabled 7 1 PINC peripheral increment mode Defines the increment mode for each DMA transfer to the identified peripheral. n memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 0: disabled 1: enabled 6 1 CIRC circular mode 0: disabled 1: enabled 5 1 DIR data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. 0: read from peripheral Source attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. Destination attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode. 1: read from memory Destination attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. Source attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode. 4 1 TEIE transfer error interrupt enable 0: disabled 1: enabled 3 1 HTIE half transfer interrupt enable 0: disabled 1: enabled 2 1 TCIE transfer complete interrupt enable 0: disabled 1: enabled 1 1 EN channel enable When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the ISR register is cleared (by setting the CTEIFx bit of the IFCR register). 0: disabled 1: enabled 0 1 CNDTR1 CNDTR1 0x0c 0x20 read-write 0x00000000 RSVD 16 16 NDT number of data to transfer (0 to 2^16 - 1) This field is updated by hardware when the channel is enabled: It is decremented after each single DMA 'read followed by write' transfer, indicating the remaining amount of data items to transfer. It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC = 0 in the CCRx register). It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC = 1). If this field is zero, no transfer can be served whatever the channel status (enabled or not). 0 16 CPAR1 CPAR1 0x10 0x20 read-write 0x00000000 PA peripheral address It contains the base address of the peripheral data register from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory destination address if DIR = 1 and the memory source address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral destination address DIR = 1 and the peripheral source address if DIR = 0. 0 32 CM0AR1 CM0AR1 0x14 0x20 read-write 0x00000000 MA memory address It contains the base address of the memory from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory source address if DIR = 1 and the memory destination address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral source address DIR = 1 and the peripheral destination address if DIR = 0. 0 32 CBSR1 CBSR1 0x18 0x20 read-write 0x00000000 RSVD 8 24 BS burst size in non-m2m mode When BS>1, DMA will transfer for BS times for each request if left NDT is larger than BS, or else transfer for left NDT times. When BS=0 or 1, DMA will always do single transfer for each request. In memory-to-memory mode, BS is ignored. 0 8 CCR2 CCR2 0x1c 0x20 read-write 0x00000000 RSVD 15 17 MEM2MEM memory-to-memory mode 0: disabled 1: enabled 14 1 PL priority level 00: low 01: medium 10: high 11: very high 12 2 MSIZE memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved 10 2 PSIZE peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved 8 2 MINC memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 0: disabled 1: enabled 7 1 PINC peripheral increment mode Defines the increment mode for each DMA transfer to the identified peripheral. n memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 0: disabled 1: enabled 6 1 CIRC circular mode 0: disabled 1: enabled 5 1 DIR data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. 0: read from peripheral Source attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. Destination attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode. 1: read from memory Destination attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. Source attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode. 4 1 TEIE transfer error interrupt enable 0: disabled 1: enabled 3 1 HTIE half transfer interrupt enable 0: disabled 1: enabled 2 1 TCIE transfer complete interrupt enable 0: disabled 1: enabled 1 1 EN channel enable When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the ISR register is cleared (by setting the CTEIFx bit of the IFCR register). 0: disabled 1: enabled 0 1 CNDTR2 CNDTR2 0x20 0x20 read-write 0x00000000 RSVD 16 16 NDT number of data to transfer (0 to 2^16 - 1) This field is updated by hardware when the channel is enabled: It is decremented after each single DMA 'read followed by write' transfer, indicating the remaining amount of data items to transfer. It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC = 0 in the CCRx register). It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC = 1). If this field is zero, no transfer can be served whatever the channel status (enabled or not). 0 16 CPAR2 CPAR2 0x24 0x20 read-write 0x00000000 PA peripheral address It contains the base address of the peripheral data register from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory destination address if DIR = 1 and the memory source address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral destination address DIR = 1 and the peripheral source address if DIR = 0. 0 32 CM0AR2 CM0AR2 0x28 0x20 read-write 0x00000000 MA peripheral address It contains the base address of the memory from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory source address if DIR = 1 and the memory destination address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral source address DIR = 1 and the peripheral destination address if DIR = 0. 0 32 CBSR2 CBSR2 0x2c 0x20 read-write 0x00000000 RSVD 8 24 BS burst size in non-m2m mode When BS>1, DMA will transfer for BS times for each request if left NDT is larger than BS, or else transfer for left NDT times. When BS=0 or 1, DMA will always do single transfer for each request. In memory-to-memory mode, BS is ignored. 0 8 CCR3 CCR3 0x30 0x20 read-write 0x00000000 RSVD 15 17 MEM2MEM memory-to-memory mode 0: disabled 1: enabled 14 1 PL priority level 00: low 01: medium 10: high 11: very high 12 2 MSIZE memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved 10 2 PSIZE peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved 8 2 MINC memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 0: disabled 1: enabled 7 1 PINC peripheral increment mode Defines the increment mode for each DMA transfer to the identified peripheral. n memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 0: disabled 1: enabled 6 1 CIRC circular mode 0: disabled 1: enabled 5 1 DIR data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. 0: read from peripheral Source attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. Destination attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode. 1: read from memory Destination attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. Source attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode. 4 1 TEIE transfer error interrupt enable 0: disabled 1: enabled 3 1 HTIE half transfer interrupt enable 0: disabled 1: enabled 2 1 TCIE transfer complete interrupt enable 0: disabled 1: enabled 1 1 EN channel enable When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the ISR register is cleared (by setting the CTEIFx bit of the IFCR register). 0: disabled 1: enabled 0 1 CNDTR3 CNDTR3 0x34 0x20 read-write 0x00000000 RSVD 16 16 NDT number of data to transfer (0 to 2^16 - 1) This field is updated by hardware when the channel is enabled: It is decremented after each single DMA 'read followed by write' transfer, indicating the remaining amount of data items to transfer. It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC = 0 in the CCRx register). It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC = 1). If this field is zero, no transfer can be served whatever the channel status (enabled or not). 0 16 CPAR3 CPAR3 0x38 0x20 read-write 0x00000000 PA peripheral address It contains the base address of the peripheral data register from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory destination address if DIR = 1 and the memory source address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral destination address DIR = 1 and the peripheral source address if DIR = 0. 0 32 CM0AR3 CM0AR3 0x3c 0x20 read-write 0x00000000 MA peripheral address It contains the base address of the memory from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory source address if DIR = 1 and the memory destination address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral source address DIR = 1 and the peripheral destination address if DIR = 0. 0 32 CBSR3 CBSR3 0x40 0x20 read-write 0x00000000 RSVD 8 24 BS burst size in non-m2m mode When BS>1, DMA will transfer for BS times for each request if left NDT is larger than BS, or else transfer for left NDT times. When BS=0 or 1, DMA will always do single transfer for each request. In memory-to-memory mode, BS is ignored. 0 8 CCR4 CCR4 0x44 0x20 read-write 0x00000000 RSVD 15 17 MEM2MEM memory-to-memory mode 0: disabled 1: enabled 14 1 PL priority level 00: low 01: medium 10: high 11: very high 12 2 MSIZE memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved 10 2 PSIZE peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved 8 2 MINC memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 0: disabled 1: enabled 7 1 PINC peripheral increment mode Defines the increment mode for each DMA transfer to the identified peripheral. n memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 0: disabled 1: enabled 6 1 CIRC circular mode 0: disabled 1: enabled 5 1 DIR data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. 0: read from peripheral Source attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. Destination attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode. 1: read from memory Destination attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. Source attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode. 4 1 TEIE transfer error interrupt enable 0: disabled 1: enabled 3 1 HTIE half transfer interrupt enable 0: disabled 1: enabled 2 1 TCIE transfer complete interrupt enable 0: disabled 1: enabled 1 1 EN channel enable When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the ISR register is cleared (by setting the CTEIFx bit of the IFCR register). 0: disabled 1: enabled 0 1 CNDTR4 CNDTR4 0x48 0x20 read-write 0x00000000 RSVD 16 16 NDT number of data to transfer (0 to 2^16 - 1) This field is updated by hardware when the channel is enabled: It is decremented after each single DMA 'read followed by write' transfer, indicating the remaining amount of data items to transfer. It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC = 0 in the CCRx register). It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC = 1). If this field is zero, no transfer can be served whatever the channel status (enabled or not). 0 16 CPAR4 CPAR4 0x4c 0x20 read-write 0x00000000 PA peripheral address It contains the base address of the peripheral data register from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory destination address if DIR = 1 and the memory source address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral destination address DIR = 1 and the peripheral source address if DIR = 0. 0 32 CM0AR4 CM0AR4 0x50 0x20 read-write 0x00000000 MA peripheral address It contains the base address of the memory from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory source address if DIR = 1 and the memory destination address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral source address DIR = 1 and the peripheral destination address if DIR = 0. 0 32 CBSR4 CBSR4 0x54 0x20 read-write 0x00000000 RSVD 8 24 BS burst size in non-m2m mode When BS>1, DMA will transfer for BS times for each request if left NDT is larger than BS, or else transfer for left NDT times. When BS=0 or 1, DMA will always do single transfer for each request. In memory-to-memory mode, BS is ignored. 0 8 CCR5 CCR5 0x58 0x20 read-write 0x00000000 RSVD 15 17 MEM2MEM memory-to-memory mode 0: disabled 1: enabled 14 1 PL priority level 00: low 01: medium 10: high 11: very high 12 2 MSIZE memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved 10 2 PSIZE peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved 8 2 MINC memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 0: disabled 1: enabled 7 1 PINC peripheral increment mode Defines the increment mode for each DMA transfer to the identified peripheral. n memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 0: disabled 1: enabled 6 1 CIRC circular mode 0: disabled 1: enabled 5 1 DIR data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. 0: read from peripheral Source attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. Destination attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode. 1: read from memory Destination attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. Source attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode. 4 1 TEIE transfer error interrupt enable 0: disabled 1: enabled 3 1 HTIE half transfer interrupt enable 0: disabled 1: enabled 2 1 TCIE transfer complete interrupt enable 0: disabled 1: enabled 1 1 EN channel enable When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the ISR register is cleared (by setting the CTEIFx bit of the IFCR register). 0: disabled 1: enabled 0 1 CNDTR5 CNDTR5 0x5c 0x20 read-write 0x00000000 RSVD 16 16 NDT number of data to transfer (0 to 2^16 - 1) This field is updated by hardware when the channel is enabled: It is decremented after each single DMA 'read followed by write' transfer, indicating the remaining amount of data items to transfer. It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC = 0 in the CCRx register). It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC = 1). If this field is zero, no transfer can be served whatever the channel status (enabled or not). 0 16 CPAR5 CPAR5 0x60 0x20 read-write 0x00000000 PA peripheral address It contains the base address of the peripheral data register from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory destination address if DIR = 1 and the memory source address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral destination address DIR = 1 and the peripheral source address if DIR = 0. 0 32 CM0AR5 CM0AR5 0x64 0x20 read-write 0x00000000 MA peripheral address It contains the base address of the memory from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory source address if DIR = 1 and the memory destination address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral source address DIR = 1 and the peripheral destination address if DIR = 0. 0 32 CBSR5 CBSR5 0x68 0x20 read-write 0x00000000 RSVD 8 24 BS burst size in non-m2m mode When BS>1, DMA will transfer for BS times for each request if left NDT is larger than BS, or else transfer for left NDT times. When BS=0 or 1, DMA will always do single transfer for each request. In memory-to-memory mode, BS is ignored. 0 8 CCR6 CCR6 0x6c 0x20 read-write 0x00000000 RSVD 15 17 MEM2MEM memory-to-memory mode 0: disabled 1: enabled 14 1 PL priority level 00: low 01: medium 10: high 11: very high 12 2 MSIZE memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved 10 2 PSIZE peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved 8 2 MINC memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 0: disabled 1: enabled 7 1 PINC peripheral increment mode Defines the increment mode for each DMA transfer to the identified peripheral. n memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 0: disabled 1: enabled 6 1 CIRC circular mode 0: disabled 1: enabled 5 1 DIR data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. 0: read from peripheral Source attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. Destination attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode. 1: read from memory Destination attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. Source attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode. 4 1 TEIE transfer error interrupt enable 0: disabled 1: enabled 3 1 HTIE half transfer interrupt enable 0: disabled 1: enabled 2 1 TCIE transfer complete interrupt enable 0: disabled 1: enabled 1 1 EN channel enable When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the ISR register is cleared (by setting the CTEIFx bit of the IFCR register). 0: disabled 1: enabled 0 1 CNDTR6 CNDTR6 0x70 0x20 read-write 0x00000000 RSVD 16 16 NDT number of data to transfer (0 to 2^16 - 1) This field is updated by hardware when the channel is enabled: It is decremented after each single DMA 'read followed by write' transfer, indicating the remaining amount of data items to transfer. It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC = 0 in the CCRx register). It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC = 1). If this field is zero, no transfer can be served whatever the channel status (enabled or not). 0 16 CPAR6 CPAR6 0x74 0x20 read-write 0x00000000 PA peripheral address It contains the base address of the peripheral data register from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory destination address if DIR = 1 and the memory source address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral destination address DIR = 1 and the peripheral source address if DIR = 0. 0 32 CM0AR6 CM0AR6 0x78 0x20 read-write 0x00000000 MA peripheral address It contains the base address of the memory from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory source address if DIR = 1 and the memory destination address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral source address DIR = 1 and the peripheral destination address if DIR = 0. 0 32 CBSR6 CBSR6 0x7c 0x20 read-write 0x00000000 RSVD 8 24 BS burst size in non-m2m mode When BS>1, DMA will transfer for BS times for each request if left NDT is larger than BS, or else transfer for left NDT times. When BS=0 or 1, DMA will always do single transfer for each request. In memory-to-memory mode, BS is ignored. 0 8 CCR7 CCR7 0x80 0x20 read-write 0x00000000 RSVD 15 17 MEM2MEM memory-to-memory mode 0: disabled 1: enabled 14 1 PL priority level 00: low 01: medium 10: high 11: very high 12 2 MSIZE memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved 10 2 PSIZE peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved 8 2 MINC memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 0: disabled 1: enabled 7 1 PINC peripheral increment mode Defines the increment mode for each DMA transfer to the identified peripheral. n memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 0: disabled 1: enabled 6 1 CIRC circular mode 0: disabled 1: enabled 5 1 DIR data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. 0: read from peripheral Source attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. Destination attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode. 1: read from memory Destination attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. Source attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode. 4 1 TEIE transfer error interrupt enable 0: disabled 1: enabled 3 1 HTIE half transfer interrupt enable 0: disabled 1: enabled 2 1 TCIE transfer complete interrupt enable 0: disabled 1: enabled 1 1 EN channel enable When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the ISR register is cleared (by setting the CTEIFx bit of the IFCR register). 0: disabled 1: enabled 0 1 CNDTR7 CNDTR7 0x84 0x20 read-write 0x00000000 RSVD 16 16 NDT number of data to transfer (0 to 2^16 - 1) This field is updated by hardware when the channel is enabled: It is decremented after each single DMA 'read followed by write' transfer, indicating the remaining amount of data items to transfer. It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC = 0 in the CCRx register). It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC = 1). If this field is zero, no transfer can be served whatever the channel status (enabled or not). 0 16 CPAR7 CPAR7 0x88 0x20 read-write 0x00000000 PA peripheral address It contains the base address of the peripheral data register from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory destination address if DIR = 1 and the memory source address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral destination address DIR = 1 and the peripheral source address if DIR = 0. 0 32 CM0AR7 CM0AR7 0x8c 0x20 read-write 0x00000000 MA peripheral address It contains the base address of the memory from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory source address if DIR = 1 and the memory destination address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral source address DIR = 1 and the peripheral destination address if DIR = 0. 0 32 CBSR7 CBSR7 0x90 0x20 read-write 0x00000000 RSVD 8 24 BS burst size in non memory-to-memory mode When BS>1, DMA will transfer for BS times for each request if left NDT is larger than BS, or else transfer for left NDT times. When BS=0 or 1, DMA will always do single transfer for each request. In memory-to-memory mode, BS is ignored. 0 8 CCR8 CCR8 0x94 0x20 read-write 0x00000000 RSVD 15 17 MEM2MEM memory-to-memory mode 0: disabled 1: enabled 14 1 PL priority level 00: low 01: medium 10: high 11: very high 12 2 MSIZE memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved 10 2 PSIZE peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved 8 2 MINC memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 0: disabled 1: enabled 7 1 PINC peripheral increment mode Defines the increment mode for each DMA transfer to the identified peripheral. n memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 0: disabled 1: enabled 6 1 CIRC circular mode 0: disabled 1: enabled 5 1 DIR data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. 0: read from peripheral Source attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. Destination attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode. 1: read from memory Destination attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. Source attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode. 4 1 TEIE transfer error interrupt enable 0: disabled 1: enabled 3 1 HTIE half transfer interrupt enable 0: disabled 1: enabled 2 1 TCIE transfer complete interrupt enable 0: disabled 1: enabled 1 1 EN channel enable When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the ISR register is cleared (by setting the CTEIFx bit of the IFCR register). 0: disabled 1: enabled 0 1 CNDTR8 CNDTR8 0x98 0x20 read-write 0x00000000 RSVD 16 16 NDT number of data to transfer (0 to 2^16 - 1) This field is updated by hardware when the channel is enabled: It is decremented after each single DMA 'read followed by write' transfer, indicating the remaining amount of data items to transfer. It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC = 0 in the CCRx register). It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC = 1). If this field is zero, no transfer can be served whatever the channel status (enabled or not). 0 16 CPAR8 CPAR8 0x9c 0x20 read-write 0x00000000 PA peripheral address It contains the base address of the peripheral data register from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory destination address if DIR = 1 and the memory source address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral destination address DIR = 1 and the peripheral source address if DIR = 0. 0 32 CM0AR8 CM0AR8 0xa0 0x20 read-write 0x00000000 MA peripheral address It contains the base address of the memory from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory source address if DIR = 1 and the memory destination address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral source address DIR = 1 and the peripheral destination address if DIR = 0. 0 32 CBSR8 CBSR8 0xa4 0x20 read-write 0x00000000 RSVD 8 24 BS burst size in non-m2m mode When BS>1, DMA will transfer for BS times for each request if left NDT is larger than BS, or else transfer for left NDT times. When BS=0 or 1, DMA will always do single transfer for each request. In memory-to-memory mode, BS is ignored. 0 8 CSELR1 CSELR1 0xa8 0x20 read-write 0x00000000 RSVD 30 2 C4S DMA channel 4 selection 24 6 RSVD2 22 2 C3S DMA channel 3 selection 16 6 RSVD3 14 2 C2S DMA channel 2 selection 8 6 RSVD4 6 2 C1S DMA channel 1 selection 0 6 CSELR2 CSELR2 0xac 0x20 read-write 0x00000000 RSVD 30 2 C8S DMA channel 8 selection 24 6 RSVD2 22 2 C7S DMA channel 7 selection 16 6 RSVD3 14 2 C6S DMA channel 6 selection 8 6 RSVD4 6 2 C5S DMA channel 5 selection 0 6 USART1 USART 0x50084000 0x0 0x1000 registers CR1 CR1 Control Register 1 0x00 0x20 read-write 0x00000000 RSVD 29 3 M Mode bit indicates the length of the packet, including data bits and parity. Stop bits not included. 0: 6 bits (e.g. 6 data bits + no parity bit) 1: 7 bits (e.g. 6 data bits + 1 parity bit) 2: 8 bits (e.g. 7 data bits + 1 parity bit, or 6 data bits + 2 parity bits) 3: 9 bits (e.g. 8 data bits + 1 parity bit, or 7 data bits + 2 parity bits) 27 2 RSVD2 26 1 RSVD3 25 1 RSVD4 20 5 RSVD5 15 5 OVER8 Oversampling mode 0: Oversampling by 16 1: Oversampling by 8 14 1 RSVD6 13 1 RSVD7 12 1 RSVD8 11 1 PCE Parity check enable. If enabled, parity bit is inserted at the MSB position 0: parity check disabled 1: parity check enabled 10 1 PS Parity select 0: even parity 1: odd parity 9 1 PEIE Parity error interrupt enable 0: interrupt disabled 1: interrupt is generated whenever PE=1 in the ISR register 8 1 TXEIE Tx empty interrupt enable 0: interrupt disabled 1: interrupt is generated whenver TXE=1 in the ISR register 7 1 TCIE Transfer compelete interrupt enable 0: interrupt disabled 1: interrupt is generated whenever TC=1 in the ISR register 6 1 RXNEIE Rx not empty interrupt enable 0: interrupt disabled 1: interrupt is generated whenever RXNE=1 in the ISR register 5 1 IDLEIE Idle line interrupt enable 0: interrupt disabled 1: interrupt is generated whenever IDLE=1 in the ISR register 4 1 TE Transmitter enable 0: transmitter is disabled 1: transmitter is enabled 3 1 RE Receiver enable 0: receiver is disabled 1: receiver is enabled 2 1 RSVD9 1 1 UE USART enable 0: disabled 1: enabled 0 1 CR2 CR2 Control Register 2 0x04 0x20 read-write 0x00000000 RSVD 24 8 RSVD2 23 1 RSVD3 21 2 RSVD4 20 1 RSVD5 19 1 RSVD6 18 1 RSVD7 17 1 RSVD8 16 1 RSVD9 15 1 RSVD10 14 1 STOP Stop bits 0/1: 1 stop bit 2/3: 2 stop bits 12 2 RSVD11 11 1 RSVD12 10 1 RSVD13 9 1 RSVD14 8 1 RSVD15 7 1 RSVD16 6 1 RSVD17 5 1 RSVD18 4 1 RSVD19 0 4 CR3 CR3 Control Register 3 0x08 0x20 read-write 0x00000000 RSVD 25 7 RSVD2 24 1 RSVD3 23 1 RSVD4 22 1 RSVD5 20 2 RSVD6 17 3 RSVD7 16 1 RSVD8 15 1 RSVD9 14 1 RSVD10 13 1 OVRDIS Overrun disable 0: overrun error flag (ORE) will be set if new data received but previous data not read. New data will not overwrite the content in RDR register. 1: overrun disabled. If new data is received before previous data is read, the new data will overwrite the content in RDR register and ORE flag remains unset. 12 1 ONEBIT One bit sampling mode 0: 3-bit sampling mode, the sampling value is determined by the voted result out of 3 bits 1: 1-bit sampling mode 11 1 CTSIE CTS interrupt enable 0: interrupt disabled 1: interrupt is generated whenever CTSIF=1 in the ISR register 10 1 CTSE CTS enable 0: CTS hardware flow control disabled 1: CTS hardware flow control enabled, data is transmitted only when CTS input is asserted low 9 1 RTSE RTS enable 0: RTS hardware flow control disabled 1: RTS hardware flow control enabled, RTS output is asserted low when new data can be received 8 1 DMAT Transmitter DMA enable 0: DMA mode disabled for transmission 1: DMA mode enabled for transmission 7 1 DMAR Receiver DMA enable 0: DMA mode disabled for reception 1: DMA mode enabled for reception 6 1 RSVD11 5 1 RSVD12 4 1 RSVD13 3 1 RSVD14 2 1 RSVD15 1 1 EIE Error interrupt enable 0: interrupt disabled 1: interrupt is generated whenever FE=1 or ORE=1 or NF=1 in the ISR register 0 1 BRR BRR Baud Rate Register 0x0c 0x20 read-write 0x00000000 RSVD 16 16 INT Integer part of baud rate prescaler If OVER8 = 0, Baud Rate = 48000000 / (INT + FRAC/16) / 16 If OVER8 = 1, Baud Rate = 48000000 / (INT + FRAC/16) / 8 For example: OVER=0, INT=3, FRAC=0, Baud Rate = 48000000/(3+0)/16 = 1Mbps OVER=0, INT=3, FRAC=4, Baud Rate = 48000000/(3+4/16)/16 = 923077 = 921600 + 1.6‰ OVER=1, INT=52, FRAC=1, Baud Rate = 48000000/(52+1/16)/8 = 115246 = 115200 + 0.4‰ 4 12 FRAC Fractional part of baud rate prescaler 0 4 RSVD1 RSVD1 0x10 0x20 read-write 0x0 RQR RQR Request Register 0x18 0x20 read-write 0x00000000 RSVD 5 27 TXFRQ Tx data flush requestReserved-Do not modify 4 1 RXFRQ Rx data flush request. Write 1 to clear the RXNE flag and discard the current data in RDR 3 1 RSVD2 2 1 RSVD3 1 1 RSVD4 0 1 ISR ISR Interrupt and Status Register 0x1c 0x20 read-write 0x020000C0 RSVD 26 6 RSVD2 25 1 RSVD3 23 2 RSVD4 22 1 RSVD5 21 1 RSVD6 20 1 RSVD7 19 1 RSVD8 18 1 RSVD9 17 1 RSVD10 16 1 RSVD11 15 1 RSVD12 14 1 RSVD13 13 1 RSVD14 12 1 RSVD15 11 1 CTS CTS input. Read this bit to get the raw status of the CTS line. 10 1 CTSIF CTS interrupt flag. This bit is set by hardware whenever CTS input toggles. 0: no change on the CTS line 1: there is a change on the CTS line 9 1 RSVD16 8 1 TXE Tx data empty 0: data is ready in TDR 1: data is already transferred to shift register, i.e. transmission is in progress or complete 7 1 TC transmission complete. This bit is set by hardware if the transmission is complete 0: transmission is not complete 1: transmission is complete 6 1 RXNE Rx data not empty. This bit is set by hardware when the received data is transferred into RDR register. 0: data is not received 1: data is ready in RDR to be read 5 1 IDLE Idle line detected 0: no idle line is detected 1: idle line is detected 4 1 ORE Overrun error. When new data is received but Rx buffer is not empty (i.e. previous data is not read yet), ORE is asserted and current RDR content is not lost. This feature can be disabled by set CR3_OVRDIS to 1. 0: no overrun error 1: overrun error is detected 3 1 NF Noise flag. Noise means the samping values in the 3-bit sampling mode are not the same. 0: no noise is detected 1: noise is detected 2 1 FE Framing error. This bit is set by hardware when stop bit is not correctly received 0: no framing error is detected 1: framing error is detected 1 1 PE Parity error. This bit is set when a parity error is detected in the received packet. 0: no parity error 1: parity error detected 0 1 ICR ICR Interrupt flag Clear Register 0x20 0x20 read-write 0x00000000 RSVD 21 11 RSVD2 20 1 RSVD3 18 2 RSVD4 17 1 RSVD5 13 4 RSVD6 12 1 RSVD7 11 1 RSVD8 10 1 CTSCF CTS clear flag. Writing 1 to this bit clears the CTSIF flag in the ISR register. 9 1 RSVD9 8 1 RSVD10 7 1 TCCF Transmission complete clear flag. Writing 1 to this bit clears the TC flag in the ISR register. 6 1 RSVD11 5 1 IDLECF Idle line detected clear flag. Writing 1 to this bit clears the IDLECF flag in the ISR register. 4 1 ORECF Overrun error clear flag. Writing 1 to this bit clears the ORE flag in the ISR register. 3 1 NCF Noise detected clear flag. Writing 1 to this bit clears the NF flag in the ISR register. 2 1 FECF Framing error clear flag. Writing 1 to this bit clears the FE flag in the ISR register. 1 1 PECF Parity error clear flag. Wriring 1 to this bit clears the PE flag in the ISR register. 0 1 RDR RDR Receive Data Register 0x24 0x20 read-write 0x00000000 RSVD 9 23 RDR Received data 0 9 TDR TDR Transmit Data Register 0x28 0x20 read-write 0x00000000 RSVD 9 23 TDR Transmit data 0 9 MISCR MISCR Miscellaneous Register 0x2c 0x20 read-write 0x00000000 AUTOCAL 31 1 RSVD 8 23 RTSBIT assert RTS ahead of the frame completion (in number of bits)Reserved-Do not modify 4 4 SMPLINI initial sample count, count down from this value to zero to reach the middle of the start bit in RxReserved-Do not modify 0 4 DRDR DRDR Debug Receive Data Register 0x30 0x20 read-write 0x00000000 DATA 0 32 DTDR DTDR Debug Receive Data Register 0x34 0x20 read-write 0x00000000 DATA 0 32 EXR EXR Mutual Exclusive Register 0x38 0x20 read-write 0x00000001 RSVD 5 27 ID 4 1 RSVD2 1 3 BUSY 0 1 USART2 USART 0x50085000 0x0 0x1000 registers CR1 CR1 Control Register 1 0x00 0x20 read-write 0x00000000 RSVD 29 3 M Mode bit indicates the length of the packet, including data bits and parity. Stop bits not included. 0: 6 bits (e.g. 6 data bits + no parity bit) 1: 7 bits (e.g. 6 data bits + 1 parity bit) 2: 8 bits (e.g. 7 data bits + 1 parity bit, or 6 data bits + 2 parity bits) 3: 9 bits (e.g. 8 data bits + 1 parity bit, or 7 data bits + 2 parity bits) 27 2 RSVD2 26 1 RSVD3 25 1 RSVD4 20 5 RSVD5 15 5 OVER8 Oversampling mode 0: Oversampling by 16 1: Oversampling by 8 14 1 RSVD6 13 1 RSVD7 12 1 RSVD8 11 1 PCE Parity check enable. If enabled, parity bit is inserted at the MSB position 0: parity check disabled 1: parity check enabled 10 1 PS Parity select 0: even parity 1: odd parity 9 1 PEIE Parity error interrupt enable 0: interrupt disabled 1: interrupt is generated whenever PE=1 in the ISR register 8 1 TXEIE Tx empty interrupt enable 0: interrupt disabled 1: interrupt is generated whenver TXE=1 in the ISR register 7 1 TCIE Transfer compelete interrupt enable 0: interrupt disabled 1: interrupt is generated whenever TC=1 in the ISR register 6 1 RXNEIE Rx not empty interrupt enable 0: interrupt disabled 1: interrupt is generated whenever RXNE=1 in the ISR register 5 1 IDLEIE Idle line interrupt enable 0: interrupt disabled 1: interrupt is generated whenever IDLE=1 in the ISR register 4 1 TE Transmitter enable 0: transmitter is disabled 1: transmitter is enabled 3 1 RE Receiver enable 0: receiver is disabled 1: receiver is enabled 2 1 RSVD9 1 1 UE USART enable 0: disabled 1: enabled 0 1 CR2 CR2 Control Register 2 0x04 0x20 read-write 0x00000000 RSVD 24 8 RSVD2 23 1 RSVD3 21 2 RSVD4 20 1 RSVD5 19 1 RSVD6 18 1 RSVD7 17 1 RSVD8 16 1 RSVD9 15 1 RSVD10 14 1 STOP Stop bits 0/1: 1 stop bit 2/3: 2 stop bits 12 2 RSVD11 11 1 RSVD12 10 1 RSVD13 9 1 RSVD14 8 1 RSVD15 7 1 RSVD16 6 1 RSVD17 5 1 RSVD18 4 1 RSVD19 0 4 CR3 CR3 Control Register 3 0x08 0x20 read-write 0x00000000 RSVD 25 7 RSVD2 24 1 RSVD3 23 1 RSVD4 22 1 RSVD5 20 2 RSVD6 17 3 RSVD7 16 1 RSVD8 15 1 RSVD9 14 1 RSVD10 13 1 OVRDIS Overrun disable 0: overrun error flag (ORE) will be set if new data received but previous data not read. New data will not overwrite the content in RDR register. 1: overrun disabled. If new data is received before previous data is read, the new data will overwrite the content in RDR register and ORE flag remains unset. 12 1 ONEBIT One bit sampling mode 0: 3-bit sampling mode, the sampling value is determined by the voted result out of 3 bits 1: 1-bit sampling mode 11 1 CTSIE CTS interrupt enable 0: interrupt disabled 1: interrupt is generated whenever CTSIF=1 in the ISR register 10 1 CTSE CTS enable 0: CTS hardware flow control disabled 1: CTS hardware flow control enabled, data is transmitted only when CTS input is asserted low 9 1 RTSE RTS enable 0: RTS hardware flow control disabled 1: RTS hardware flow control enabled, RTS output is asserted low when new data can be received 8 1 DMAT Transmitter DMA enable 0: DMA mode disabled for transmission 1: DMA mode enabled for transmission 7 1 DMAR Receiver DMA enable 0: DMA mode disabled for reception 1: DMA mode enabled for reception 6 1 RSVD11 5 1 RSVD12 4 1 RSVD13 3 1 RSVD14 2 1 RSVD15 1 1 EIE Error interrupt enable 0: interrupt disabled 1: interrupt is generated whenever FE=1 or ORE=1 or NF=1 in the ISR register 0 1 BRR BRR Baud Rate Register 0x0c 0x20 read-write 0x00000000 RSVD 16 16 INT Integer part of baud rate prescaler If OVER8 = 0, Baud Rate = 48000000 / (INT + FRAC/16) / 16 If OVER8 = 1, Baud Rate = 48000000 / (INT + FRAC/16) / 8 For example: OVER=0, INT=3, FRAC=0, Baud Rate = 48000000/(3+0)/16 = 1Mbps OVER=0, INT=3, FRAC=4, Baud Rate = 48000000/(3+4/16)/16 = 923077 = 921600 + 1.6‰ OVER=1, INT=52, FRAC=1, Baud Rate = 48000000/(52+1/16)/8 = 115246 = 115200 + 0.4‰ 4 12 FRAC Fractional part of baud rate prescaler 0 4 RSVD1 RSVD1 0x10 0x20 read-write 0x0 RQR RQR Request Register 0x18 0x20 read-write 0x00000000 RSVD 5 27 TXFRQ Tx data flush requestReserved-Do not modify 4 1 RXFRQ Rx data flush request. Write 1 to clear the RXNE flag and discard the current data in RDR 3 1 RSVD2 2 1 RSVD3 1 1 RSVD4 0 1 ISR ISR Interrupt and Status Register 0x1c 0x20 read-write 0x020000C0 RSVD 26 6 RSVD2 25 1 RSVD3 23 2 RSVD4 22 1 RSVD5 21 1 RSVD6 20 1 RSVD7 19 1 RSVD8 18 1 RSVD9 17 1 RSVD10 16 1 RSVD11 15 1 RSVD12 14 1 RSVD13 13 1 RSVD14 12 1 RSVD15 11 1 CTS CTS input. Read this bit to get the raw status of the CTS line. 10 1 CTSIF CTS interrupt flag. This bit is set by hardware whenever CTS input toggles. 0: no change on the CTS line 1: there is a change on the CTS line 9 1 RSVD16 8 1 TXE Tx data empty 0: data is ready in TDR 1: data is already transferred to shift register, i.e. transmission is in progress or complete 7 1 TC transmission complete. This bit is set by hardware if the transmission is complete 0: transmission is not complete 1: transmission is complete 6 1 RXNE Rx data not empty. This bit is set by hardware when the received data is transferred into RDR register. 0: data is not received 1: data is ready in RDR to be read 5 1 IDLE Idle line detected 0: no idle line is detected 1: idle line is detected 4 1 ORE Overrun error. When new data is received but Rx buffer is not empty (i.e. previous data is not read yet), ORE is asserted and current RDR content is not lost. This feature can be disabled by set CR3_OVRDIS to 1. 0: no overrun error 1: overrun error is detected 3 1 NF Noise flag. Noise means the samping values in the 3-bit sampling mode are not the same. 0: no noise is detected 1: noise is detected 2 1 FE Framing error. This bit is set by hardware when stop bit is not correctly received 0: no framing error is detected 1: framing error is detected 1 1 PE Parity error. This bit is set when a parity error is detected in the received packet. 0: no parity error 1: parity error detected 0 1 ICR ICR Interrupt flag Clear Register 0x20 0x20 read-write 0x00000000 RSVD 21 11 RSVD2 20 1 RSVD3 18 2 RSVD4 17 1 RSVD5 13 4 RSVD6 12 1 RSVD7 11 1 RSVD8 10 1 CTSCF CTS clear flag. Writing 1 to this bit clears the CTSIF flag in the ISR register. 9 1 RSVD9 8 1 RSVD10 7 1 TCCF Transmission complete clear flag. Writing 1 to this bit clears the TC flag in the ISR register. 6 1 RSVD11 5 1 IDLECF Idle line detected clear flag. Writing 1 to this bit clears the IDLECF flag in the ISR register. 4 1 ORECF Overrun error clear flag. Writing 1 to this bit clears the ORE flag in the ISR register. 3 1 NCF Noise detected clear flag. Writing 1 to this bit clears the NF flag in the ISR register. 2 1 FECF Framing error clear flag. Writing 1 to this bit clears the FE flag in the ISR register. 1 1 PECF Parity error clear flag. Wriring 1 to this bit clears the PE flag in the ISR register. 0 1 RDR RDR Receive Data Register 0x24 0x20 read-write 0x00000000 RSVD 9 23 RDR Received data 0 9 TDR TDR Transmit Data Register 0x28 0x20 read-write 0x00000000 RSVD 9 23 TDR Transmit data 0 9 MISCR MISCR Miscellaneous Register 0x2c 0x20 read-write 0x00000000 AUTOCAL 31 1 RSVD 8 23 RTSBIT assert RTS ahead of the frame completion (in number of bits)Reserved-Do not modify 4 4 SMPLINI initial sample count, count down from this value to zero to reach the middle of the start bit in RxReserved-Do not modify 0 4 DRDR DRDR Debug Receive Data Register 0x30 0x20 read-write 0x00000000 DATA 0 32 DTDR DTDR Debug Receive Data Register 0x34 0x20 read-write 0x00000000 DATA 0 32 EXR EXR Mutual Exclusive Register 0x38 0x20 read-write 0x00000001 RSVD 5 27 ID 4 1 RSVD2 1 3 BUSY 0 1 USART3 USART 0x50086000 0x0 0x1000 registers CR1 CR1 Control Register 1 0x00 0x20 read-write 0x00000000 RSVD 29 3 M Mode bit indicates the length of the packet, including data bits and parity. Stop bits not included. 0: 6 bits (e.g. 6 data bits + no parity bit) 1: 7 bits (e.g. 6 data bits + 1 parity bit) 2: 8 bits (e.g. 7 data bits + 1 parity bit, or 6 data bits + 2 parity bits) 3: 9 bits (e.g. 8 data bits + 1 parity bit, or 7 data bits + 2 parity bits) 27 2 RSVD2 26 1 RSVD3 25 1 RSVD4 20 5 RSVD5 15 5 OVER8 Oversampling mode 0: Oversampling by 16 1: Oversampling by 8 14 1 RSVD6 13 1 RSVD7 12 1 RSVD8 11 1 PCE Parity check enable. If enabled, parity bit is inserted at the MSB position 0: parity check disabled 1: parity check enabled 10 1 PS Parity select 0: even parity 1: odd parity 9 1 PEIE Parity error interrupt enable 0: interrupt disabled 1: interrupt is generated whenever PE=1 in the ISR register 8 1 TXEIE Tx empty interrupt enable 0: interrupt disabled 1: interrupt is generated whenver TXE=1 in the ISR register 7 1 TCIE Transfer compelete interrupt enable 0: interrupt disabled 1: interrupt is generated whenever TC=1 in the ISR register 6 1 RXNEIE Rx not empty interrupt enable 0: interrupt disabled 1: interrupt is generated whenever RXNE=1 in the ISR register 5 1 IDLEIE Idle line interrupt enable 0: interrupt disabled 1: interrupt is generated whenever IDLE=1 in the ISR register 4 1 TE Transmitter enable 0: transmitter is disabled 1: transmitter is enabled 3 1 RE Receiver enable 0: receiver is disabled 1: receiver is enabled 2 1 RSVD9 1 1 UE USART enable 0: disabled 1: enabled 0 1 CR2 CR2 Control Register 2 0x04 0x20 read-write 0x00000000 RSVD 24 8 RSVD2 23 1 RSVD3 21 2 RSVD4 20 1 RSVD5 19 1 RSVD6 18 1 RSVD7 17 1 RSVD8 16 1 RSVD9 15 1 RSVD10 14 1 STOP Stop bits 0/1: 1 stop bit 2/3: 2 stop bits 12 2 RSVD11 11 1 RSVD12 10 1 RSVD13 9 1 RSVD14 8 1 RSVD15 7 1 RSVD16 6 1 RSVD17 5 1 RSVD18 4 1 RSVD19 0 4 CR3 CR3 Control Register 3 0x08 0x20 read-write 0x00000000 RSVD 25 7 RSVD2 24 1 RSVD3 23 1 RSVD4 22 1 RSVD5 20 2 RSVD6 17 3 RSVD7 16 1 RSVD8 15 1 RSVD9 14 1 RSVD10 13 1 OVRDIS Overrun disable 0: overrun error flag (ORE) will be set if new data received but previous data not read. New data will not overwrite the content in RDR register. 1: overrun disabled. If new data is received before previous data is read, the new data will overwrite the content in RDR register and ORE flag remains unset. 12 1 ONEBIT One bit sampling mode 0: 3-bit sampling mode, the sampling value is determined by the voted result out of 3 bits 1: 1-bit sampling mode 11 1 CTSIE CTS interrupt enable 0: interrupt disabled 1: interrupt is generated whenever CTSIF=1 in the ISR register 10 1 CTSE CTS enable 0: CTS hardware flow control disabled 1: CTS hardware flow control enabled, data is transmitted only when CTS input is asserted low 9 1 RTSE RTS enable 0: RTS hardware flow control disabled 1: RTS hardware flow control enabled, RTS output is asserted low when new data can be received 8 1 DMAT Transmitter DMA enable 0: DMA mode disabled for transmission 1: DMA mode enabled for transmission 7 1 DMAR Receiver DMA enable 0: DMA mode disabled for reception 1: DMA mode enabled for reception 6 1 RSVD11 5 1 RSVD12 4 1 RSVD13 3 1 RSVD14 2 1 RSVD15 1 1 EIE Error interrupt enable 0: interrupt disabled 1: interrupt is generated whenever FE=1 or ORE=1 or NF=1 in the ISR register 0 1 BRR BRR Baud Rate Register 0x0c 0x20 read-write 0x00000000 RSVD 16 16 INT Integer part of baud rate prescaler If OVER8 = 0, Baud Rate = 48000000 / (INT + FRAC/16) / 16 If OVER8 = 1, Baud Rate = 48000000 / (INT + FRAC/16) / 8 For example: OVER=0, INT=3, FRAC=0, Baud Rate = 48000000/(3+0)/16 = 1Mbps OVER=0, INT=3, FRAC=4, Baud Rate = 48000000/(3+4/16)/16 = 923077 = 921600 + 1.6‰ OVER=1, INT=52, FRAC=1, Baud Rate = 48000000/(52+1/16)/8 = 115246 = 115200 + 0.4‰ 4 12 FRAC Fractional part of baud rate prescaler 0 4 RSVD1 RSVD1 0x10 0x20 read-write 0x0 RQR RQR Request Register 0x18 0x20 read-write 0x00000000 RSVD 5 27 TXFRQ Tx data flush requestReserved-Do not modify 4 1 RXFRQ Rx data flush request. Write 1 to clear the RXNE flag and discard the current data in RDR 3 1 RSVD2 2 1 RSVD3 1 1 RSVD4 0 1 ISR ISR Interrupt and Status Register 0x1c 0x20 read-write 0x020000C0 RSVD 26 6 RSVD2 25 1 RSVD3 23 2 RSVD4 22 1 RSVD5 21 1 RSVD6 20 1 RSVD7 19 1 RSVD8 18 1 RSVD9 17 1 RSVD10 16 1 RSVD11 15 1 RSVD12 14 1 RSVD13 13 1 RSVD14 12 1 RSVD15 11 1 CTS CTS input. Read this bit to get the raw status of the CTS line. 10 1 CTSIF CTS interrupt flag. This bit is set by hardware whenever CTS input toggles. 0: no change on the CTS line 1: there is a change on the CTS line 9 1 RSVD16 8 1 TXE Tx data empty 0: data is ready in TDR 1: data is already transferred to shift register, i.e. transmission is in progress or complete 7 1 TC transmission complete. This bit is set by hardware if the transmission is complete 0: transmission is not complete 1: transmission is complete 6 1 RXNE Rx data not empty. This bit is set by hardware when the received data is transferred into RDR register. 0: data is not received 1: data is ready in RDR to be read 5 1 IDLE Idle line detected 0: no idle line is detected 1: idle line is detected 4 1 ORE Overrun error. When new data is received but Rx buffer is not empty (i.e. previous data is not read yet), ORE is asserted and current RDR content is not lost. This feature can be disabled by set CR3_OVRDIS to 1. 0: no overrun error 1: overrun error is detected 3 1 NF Noise flag. Noise means the samping values in the 3-bit sampling mode are not the same. 0: no noise is detected 1: noise is detected 2 1 FE Framing error. This bit is set by hardware when stop bit is not correctly received 0: no framing error is detected 1: framing error is detected 1 1 PE Parity error. This bit is set when a parity error is detected in the received packet. 0: no parity error 1: parity error detected 0 1 ICR ICR Interrupt flag Clear Register 0x20 0x20 read-write 0x00000000 RSVD 21 11 RSVD2 20 1 RSVD3 18 2 RSVD4 17 1 RSVD5 13 4 RSVD6 12 1 RSVD7 11 1 RSVD8 10 1 CTSCF CTS clear flag. Writing 1 to this bit clears the CTSIF flag in the ISR register. 9 1 RSVD9 8 1 RSVD10 7 1 TCCF Transmission complete clear flag. Writing 1 to this bit clears the TC flag in the ISR register. 6 1 RSVD11 5 1 IDLECF Idle line detected clear flag. Writing 1 to this bit clears the IDLECF flag in the ISR register. 4 1 ORECF Overrun error clear flag. Writing 1 to this bit clears the ORE flag in the ISR register. 3 1 NCF Noise detected clear flag. Writing 1 to this bit clears the NF flag in the ISR register. 2 1 FECF Framing error clear flag. Writing 1 to this bit clears the FE flag in the ISR register. 1 1 PECF Parity error clear flag. Wriring 1 to this bit clears the PE flag in the ISR register. 0 1 RDR RDR Receive Data Register 0x24 0x20 read-write 0x00000000 RSVD 9 23 RDR Received data 0 9 TDR TDR Transmit Data Register 0x28 0x20 read-write 0x00000000 RSVD 9 23 TDR Transmit data 0 9 MISCR MISCR Miscellaneous Register 0x2c 0x20 read-write 0x00000000 AUTOCAL 31 1 RSVD 8 23 RTSBIT assert RTS ahead of the frame completion (in number of bits)Reserved-Do not modify 4 4 SMPLINI initial sample count, count down from this value to zero to reach the middle of the start bit in RxReserved-Do not modify 0 4 DRDR DRDR Debug Receive Data Register 0x30 0x20 read-write 0x00000000 DATA 0 32 DTDR DTDR Debug Receive Data Register 0x34 0x20 read-write 0x00000000 DATA 0 32 EXR EXR Mutual Exclusive Register 0x38 0x20 read-write 0x00000001 RSVD 5 27 ID 4 1 RSVD2 1 3 BUSY 0 1 GPADC GPADC 0x50087000 0x0 0x1000 registers ADC_CFG_REG1 ADC_CFG_REG1 ADC Analog Config Register 1 0x00 0x20 read-write 0x04714A44 RSVD 30 2 ANAU_GPADC_CMM Tune CDAC CM voltage 375mV range (increasing) / 25mV step, 8: for 0.5V Vcm,in 25 5 ANAU_GPADC_CMPCL Tune ADC comparator CL= 3: 40f, range: 10fF (0) ~ 80fF (7) / 10fF step 22 3 ANAU_GPADC_VSP Set comparator input CM in sampling phase, 0.539V (0) / 0.578V (1) / 0.642V (2) / 0.784V (3) 20 2 ANAU_GPADC_LDOREF_EN Enable LDORF for ADC VREF 19 1 ANAU_GPADC_LDOVREF_SEL Set reference voltage for LDOREF, range = 0.35V(0) ~ 0.65V(15), step = 20mV 15 4 ANAU_GPADC_SEL_PCH Select P-side input channel for GPADC, 0 for channel 0, 7 for channel 7, effective when force on 12 3 ANAU_GPADC_SEL_NCH Select N-side input channel for GPADC, 0 for channel 0, 7 for channel 7, effective when force on 9 3 ANAU_GPADC_MUTE Short GPADC P and N input to CMREF, i.e., VREF/2 8 1 ANAU_GPADC_SE Set GPADC in single-ended mode, signal range at P-input: 0 ~ VREF 7 1 ANAU_GPADC_EN_V18 6 1 ANAU_GPADC_CL_DLY 3 3 ANAU_GPADC_P_INT_EN 2 1 RSVD2 1 1 ANAU_GPADC_CMREF_FAST_EN 0 1 ADC_SLOT0_REG ADC_SLOT0_REG ADC Slot0 Config Register 0x04 0x20 read-write 0x00020801 RSVD 14 18 NCHNL_SEL 11 3 PCHNL_SEL 8 3 RSVD2 1 7 SLOT_EN 0 1 ADC_SLOT1_REG ADC_SLOT1_REG ADC Slot1 Config Register 0x08 0x20 read-write 0x00020801 RSVD 14 18 NCHNL_SEL 11 3 PCHNL_SEL 8 3 RSVD2 1 7 SLOT_EN 0 1 ADC_SLOT2_REG ADC_SLOT2_REG ADC Slot2 Config Register 0x0c 0x20 read-write 0x00020801 RSVD 14 18 NCHNL_SEL 11 3 PCHNL_SEL 8 3 RSVD2 1 7 SLOT_EN 0 1 ADC_SLOT3_REG ADC_SLOT3_REG ADC Slot3 Config Register 0x10 0x20 read-write 0x00020801 RSVD 14 18 NCHNL_SEL 11 3 PCHNL_SEL 8 3 RSVD2 1 7 SLOT_EN 0 1 ADC_SLOT4_REG ADC_SLOT4_REG ADC Slot4 Config Register 0x14 0x20 read-write 0x00020801 RSVD 14 18 NCHNL_SEL 11 3 PCHNL_SEL 8 3 RSVD2 1 7 SLOT_EN 0 1 ADC_SLOT5_REG ADC_SLOT5_REG ADC Slot5 Config Register 0x18 0x20 read-write 0x00020801 RSVD 14 18 NCHNL_SEL 11 3 PCHNL_SEL 8 3 RSVD2 1 7 SLOT_EN 0 1 ADC_SLOT6_REG ADC_SLOT6_REG ADC Slot6 Config Register 0x1c 0x20 read-write 0x00020801 RSVD 14 18 NCHNL_SEL 11 3 PCHNL_SEL 8 3 RSVD2 1 7 SLOT_EN 0 1 ADC_SLOT7_REG ADC_SLOT7_REG ADC Slot7 Config Register 0x20 0x20 read-write 0x00020801 RSVD 14 18 NCHNL_SEL 11 3 PCHNL_SEL 8 3 RSVD2 1 7 SLOT_EN 0 1 ADC_RDATA0 ADC_RDATA0 ADC Read Data0 0x24 0x20 read-write 0x00000000 RSVD 28 4 SLOT1_RDATA 16 12 RSVD2 12 4 SLOT0_RDATA 0 12 ADC_RDATA1 ADC_RDATA1 ADC Read Data1 0x28 0x20 read-write 0x00000000 RSVD 28 4 SLOT3_RDATA 16 12 RSVD2 12 4 SLOT2_RDATA 0 12 ADC_RDATA2 ADC_RDATA2 ADC Read Data2 0x2c 0x20 read-write 0x00000000 RSVD 28 4 SLOT5_RDATA 16 12 RSVD2 12 4 SLOT4_RDATA 0 12 ADC_RDATA3 ADC_RDATA3 ADC Read Data3 0x30 0x20 read-write 0x00000000 RSVD 28 4 SLOT7_RDATA 16 12 RSVD2 12 4 SLOT6_RDATA 0 12 ADC_DMA_RDATA ADC_DMA_RDATA ADC Read Data For DMA 0x34 0x20 read-write 0x00000000 RSVD 29 3 DMA_RDATA_RAW 16 13 RSVD2 13 3 DMA_RDATA 0 13 ADC_CTRL_REG ADC_CTRL_REG ADC Control Register 0x38 0x20 read-write 0x00000130 RSVD 21 11 DATA_SAMP_DLY 17 4 DMA_DATA_SEL 0: combined data 1: raw data 16 1 TIMER_TRIG_TYP 0: pulse no edge detect needed 1: level,need edge detect 15 1 TIMER_TRIG_SRC_SEL Timer trigger source select 12 3 FRC_EN_ADC Enable GPADC core 11 1 CHNL_SEL_FRC_EN Enable input channel setting in ADC_CFG_REG1 10 1 TIMER_TRIG_EN Enable timer trigger function 9 1 RSVD2 8 1 DMA_EN Enable DMA interface 7 1 INIT_TIME GPADC will wait INIT_TIME ADCCLK cycles to start sample/conversion after being trigged 3 4 ADC_STOP Write 1 to stop GPADC in continuous mode(need write 0 to clear) 2 1 ADC_START Write 1 to start GPADC,(don't need clear ) 1 1 ADC_OP_MODE 0: single conversion mode 1: continuous conversion mode 0 1 ADC_CTRL_REG2 ADC_CTRL_REG2 ADC Control Register2 0x3c 0x20 read-write 0x00000130 CONV_WIDTH 24 8 SAMP_WIDTH 0 24 GPADC_STATUS GPADC_STATUS GPADC Status Register 0x40 0x20 read-write 0x00000000 RSVD 12 20 CUR_SLOT 9 3 SLOT_DONE 1 8 ADC_DONE 0 1 GPADC_IRQ GPADC_IRQ GPADC IRQ Register 0x44 0x20 read-write 0x00000000 RSVD 4 28 GPADC_ISR 3 1 GPADC_IRSR 2 1 GPADC_IMR 1 1 GPADC_ICR 0 1 AUDCODEC AUDCODEC 0x50088000 0x0 0x1000 registers ID ID 0x00 0x20 read-write 0xC0DEC000 FUNC function id 0 32 CFG CFG 0x04 0x20 read-write 0x00000000 RSVD 5 27 ADC_EN_DLY_SEL codec adc enable delay count 0: no delay 1: 32 pclk 2: 64 pclk 3: 128 pclk 3 2 DAC_1K_MODE codec dac sine 1k mode 2 1 DAC_ENABLE dac codec enable 1 1 ADC_ENABLE adc codec enable 0 1 IRQ IRQ 0x08 0x20 read-write 0x00000000 RSVD 22 10 ADC_CH1_SAT adc ch1 saturation interrupt 21 1 ADC_CH1_APB_UF adc ch1 apb fifo underflow interrupt status. Write 1 to clear. 20 1 ADC_CH1_APB_OF adc ch1 apb fifo overflow interrupt status. Write 1 to clear. 19 1 ADC_CH0_SAT adc ch0 saturation interrupt 18 1 ADC_CH0_APB_UF adc ch0 apb fifo underflow interrupt status. Write 1 to clear. 17 1 ADC_CH0_APB_OF adc ch0 apb fifo overflow interrupt status. Write 1 to clear. 16 1 RSVD2 6 10 DAC_CH1_STB_OF dac ch1 input stb fifo overflow interrupt status. Write 1 to clear. 5 1 DAC_CH1_OUT_UF dac ch1 output fifo underflow interrupt status. Write 1 to clear. 4 1 DAC_CH1_APB_OF dac ch1 apb fifo overflow interrupt status. Write 1 to clear. 3 1 DAC_CH0_STB_OF dac ch0 input stb fifo overflow interrupt status. Write 1 to clear. 2 1 DAC_CH0_OUT_UF dac ch0 output fifo underflow interrupt status. Write 1 to clear. 1 1 DAC_CH0_APB_OF dac ch0 apb fifo overflow interrupt status. Write 1 to clear. 0 1 IRQ_MSK IRQ_MSK 0x0c 0x20 read-write 0x00000000 RSVD 22 10 ADC_CH1_SAT interrupt mask. 0: mask the interrupt. 21 1 ADC_CH1_APB_UF interrupt mask. 0: mask the interrupt. 20 1 ADC_CH1_APB_OF interrupt mask. 0: mask the interrupt. 19 1 ADC_CH0_SAT interrupt mask. 0: mask the interrupt. 18 1 ADC_CH0_APB_UF interrupt mask. 0: mask the interrupt. 17 1 ADC_CH0_APB_OF interrupt mask. 0: mask the interrupt. 16 1 RSVD2 6 10 DAC_CH1_STB_OF interrupt mask. 0: mask the interrupt. 5 1 DAC_CH1_OUT_UF interrupt mask. 0: mask the interrupt. 4 1 DAC_CH1_APB_OF interrupt mask. 0: mask the interrupt. 3 1 DAC_CH0_STB_OF interrupt mask. 0: mask the interrupt. 2 1 DAC_CH0_OUT_UF interrupt mask. 0: mask the interrupt. 1 1 DAC_CH0_APB_OF interrupt mask. 0: mask the interrupt. 0 1 DAC_CFG DAC_CFG 0x10 0x20 read-write 0x00000000 RSVD 27 5 SDM_OSR_SEL_M 0:100 1:150 2:300 3:256 25 2 SINC_RATE_SEL_M 0:25 1:50 2:16 3:32 4:64 22 3 INTERP3_BYPASS_M 21 1 HBF4_BYPASS_M 20 1 HBF3_BYPASS_M 19 1 HBF2_BYPASS_M 18 1 HBF1_BYPASS_M 17 1 MANUAL_OSR_MODE set 1 to manually set hbf, interp3, sinc and sdm module 16 1 CLK_DIV dac clock divider 8 8 CLK_SRC_SEL dac clock source select 1: pll 0: xtal 7 1 PATH_RESET dac path reset, set 1 to reset dac path 6 1 OP_MODE dac operation mode 2'h0: normal mode: send dac data through tx interface 2'h1: apb mode: send dac data out through apb interface 2'h2, 2'h3: reserved 4 2 OSR_SEL DAC oversample rate 4'b0000: 100 4'b0001: 150 4'b0010: 200 4'b0011: 300(sdm osr = 150) 4'b0100: 300(sdm osr = 300) 4'b0101: 400 4'b0110: 600 4'b0111: 800 4'b1000: 1200 4'b1001: 256 4'b1010: 512 4'b1011: 1024 other: reserved 0 4 ADC_CFG ADC_CFG 0x14 0x20 read-write 0x00000000 RSVD 16 16 CLK_DIV adc clock divider 8 8 RSVD2 7 1 CLK_SRC_SEL adc clock source select 1: pll 0: xtal 6 1 PATH_RESET adc path reset, set 1 to reset adc path 5 1 OP_MODE adc operation mode 2'h0: normal mode: send adc data out through rx interface 2'h1: apb mode: send adc data out through apb interface 2'h2: raw data apb mode: send adc raw data out through apb interface 2'h3: reserved 3 2 OSR_SEL ADC oversample rate 3'b000: 200 3'b001: 300 3'b010: 400 3'b011: 600 other: reserved 0 3 APB_STAT APB_STAT 0x18 0x20 read-write 0x00000000 RSVD 24 8 ADC_CH1_FIFO_CNT 20 4 ADC_CH0_FIFO_CNT 16 4 RSVD2 8 8 DAC_CH1_FIFO_CNT 4 4 DAC_CH0_FIFO_CNT 0 4 RSVD5 RSVD5 0x1C 0x20 read-write 0x0 ADC_CH0_CFG ADC_CH0_CFG 0x20 0x20 read-write 0x00000000 RSVD 20 12 SAT_DET_LEN adc saturation detect pattern length 2'b00: 16 2'b01: 24 2'b10: 32 2'b11: 48 18 2 SAT_DET_EN adc saturation detect 17 1 DATA_FORMAT adc data format 1: 16-bit 0: 24-bit this bit only affect the data format accessed by apb interface. For 24-bit, every 24-bit data occupied 32-bit word. Bit[31:24] are zeros. For 16-bit mode, every 32-bit word contains two 16-bit audio data{D1, D0} 16 1 FINE_VOL adc fine volume control range from 0dB to 6dB step is 0.5dB 4'h0: 0dB 4'h1: 0.5dB ...... 4'hb: 5.5dB 4'hc, 4'hd, 4'he, 4'hf: mute 12 4 ROUGH_VOL adc rough volume control range from -60dB to 30dB step is 6dB 4'h0: -60dB 4'h1: -54dB ...... 4'ha: 0dB ...... 4'he: 24dB 4'hf: 30dB 8 4 DMA_EN dma interface enable in apb mode and raw data apb mode 1: enable adc ch0 dma request interface 0: disable adc ch0 dma request interface 7 1 STB_INV adc strobe inverter 6 1 HPF_COEF high-pass filter coefficient 2 4 HPF_BYPASS high-pass filter bypass 1 1 ENABLE adc channel enable 0 1 ADC_CH1_CFG ADC_CH1_CFG 0x24 0x20 read-write 0x00000000 RSVD 20 12 SAT_DET_LEN adc saturation detect pattern length 2'b00: 16 2'b01: 24 2'b10: 32 2'b11: 48 18 2 SAT_DET_EN adc saturation detect 17 1 DATA_FORMAT adc data format 1: 16-bit 0: 24-bit this bit only affect the data format accessed by apb interface. For 24-bit, every 24-bit data occupied 32-bit word. Bit[31:24] are zeros. For 16-bit mode, every 32-bit word contains two 16-bit audio data{D1, D0} 16 1 FINE_VOL adc fine volume control range from 0dB to 6dB step is 0.5dB 4'h0: 0dB 4'h1: 0.5dB ...... 4'hb: 5.5dB 4'hc, 4'hd, 4'he, 4'hf: mute 12 4 ROUGH_VOL adc rough volume control range from -60dB to 30dB step is 6dB 4'h0: -60dB 4'h1: -54dB ...... 4'ha: 0dB ...... 4'he: 24dB 4'hf: 30dB 8 4 DMA_EN dma interface enable in apb mode and raw data apb mode 1: enable adc ch0 dma request interface 0: disable adc ch0 dma request interface 7 1 STB_INV adc strobe inverter 6 1 HPF_COEF high-pass filter coefficient 2 4 HPF_BYPASS high-pass filter bypass 1 1 ENABLE adc channel enable 0 1 RSVD4 RSVD4 0x28 0x20 read-write 0x0 DAC_CH0_CFG DAC_CH0_CFG 0x30 0x20 read-write 0x00000000 RSVD 31 1 CLK_ANA_POL analog dac clock polarity 30 1 DITHER_EN sdm dither enable 29 1 DITHER_GAIN sdm dither gain 26 3 SINC_GAIN dac sinc filter gain 17 9 DATA_FORMAT dac data format 1: 16-bit 0: 24-bit this bit only affect the data format accessed by apb interface. For 24-bit, every 24-bit data occupied 32-bit word. Bit[31:24] are zeros. For 16-bit mode, every 32-bit word contains two 16-bit audio data{D1, D0} 16 1 FINE_VOL dac fine volume control range from 0dB to 6dB step is 0.5dB 4'h0: 0dB 4'h1: 0.5dB ...... 4'hb: 5.5dB 4'hc, 4'hd, 4'he, 4'hf: mute 12 4 ROUGH_VOL dac rough volume control range from -36dB to 54dB step is 6dB 4'h0: -36dB 4'h1: -30dB ...... 4'h6: 0dB ...... 4'he: 48dB 4'hf: 54dB 8 4 DMA_EN dma interface enable in apb mode 1: enable dac ch0 dma request interface 0: disable dac ch0 dma request interface 7 1 STB_FIFO_CNT dac input stb fifo cnt 4 3 DEM_MODE dem output mode 2'h0: no shift for dem output 2'h1: shift dem output incrementally 2'h2: shift dem output according to input 2'h3: reserved 2 2 DOUT_MUTE dac output mute, set 1 to mute the output 1 1 ENABLE dac channel enable 0 1 DAC_CH0_CFG_EXT DAC_CH0_CFG_EXT 0x34 0x20 read-write 0x00000000 RSVD 9 23 RAMP_STAT ramp module status 7 2 RAMP_INTERVAL volume ramp interval. 3 4 ZERO_ADJUST_EN enable volume adjustment during 0 volume cross. 2 1 RAMP_MODE volume ramp mode: 1: slowly ramp to target volume. Step is 0.5db 0: directly ramp to target volume. 1 1 RAMP_EN volume ramp enable 0 1 DAC_CH1_CFG DAC_CH1_CFG 0x38 0x20 read-write 0x00000000 RSVD 31 1 CLK_ANA_POL analog dac clock polarity 30 1 DITHER_EN sdm dither enable 29 1 DITHER_GAIN sdm dither gain 26 3 SINC_GAIN dac sinc filter gain 17 9 DATA_FORMAT dac data format 1: 16-bit 0: 24-bit this bit only affect the data format accessed by apb interface. For 24-bit, every 24-bit data occupied 32-bit word. Bit[31:24] are zeros. For 16-bit mode, every 32-bit word contains two 16-bit audio data{D1, D0} 16 1 FINE_VOL dac fine volume control range from 0dB to 6dB step is 0.5dB 4'h0: 0dB 4'h1: 0.5dB ...... 4'hb: 5.5dB 4'hc, 4'hd, 4'he, 4'hf: mute 12 4 ROUGH_VOL dac rough volume control range from -36dB to 54dB step is 6dB 4'h0: -36dB 4'h1: -30dB ...... 4'h6: 0dB ...... 4'he: 48dB 4'hf: 54dB 8 4 DMA_EN dma interface enable in apb mode 1: enable dac ch0 dma request interface 0: disable dac ch0 dma request interface 7 1 STB_FIFO_CNT dac input stb fifo cnt 4 3 DEM_MODE dem output mode 2'h0: no shift for dem output 2'h1: shift dem output incrementally 2'h2: shift dem output according to input 2'h3: reserved 2 2 DOUT_MUTE dac output mute, set 1 to mute the output 1 1 ENABLE dac channel enable 0 1 DAC_CH1_CFG_EXT DAC_CH1_CFG_EXT 0x3c 0x20 read-write 0x00000000 RSVD 9 23 RAMP_STAT ramp module status 7 2 RAMP_INTERVAL volume ramp interval. 3 4 ZERO_ADJUST_EN enable volume adjustment during 0 volume cross. 2 1 RAMP_MODE volume ramp mode: 1: slowly ramp to target volume. Step is 0.5db 0: directly ramp to target volume. 1 1 RAMP_EN volume ramp enable 0 1 ADC_CH0_ENTRY ADC_CH0_ENTRY 0x40 0x20 read-write 0x00000000 DATA adc channel0 data output 0 32 ADC_CH1_ENTRY ADC_CH1_ENTRY 0x44 0x20 read-write 0x00000000 DATA adc channel1 data output 0 32 RSVD3 RSVD3 0x48 0x20 read-write 0x0 DAC_CH0_ENTRY DAC_CH0_ENTRY 0x50 0x20 read-write 0x00000000 DATA dac channel0 data input 0 32 DAC_CH1_ENTRY DAC_CH1_ENTRY 0x54 0x20 read-write 0x00000000 DATA dac channel0 data input 0 32 DAC_CH0_DEBUG DAC_CH0_DEBUG 0x58 0x20 read-write 0x00000000 RSVD 17 15 BYPASS debug bypass mode 16 1 DATA_OUT debug dac output 0 16 DAC_CH1_DEBUG DAC_CH1_DEBUG 0x5c 0x20 read-write 0x00000000 RSVD 17 15 BYPASS debug bypass mode 16 1 DATA_OUT debug dac output 0 16 DAC_CH0_DC DAC_CH0_DC 0x60 0x20 read-write 0x00000000 RSVD 24 8 OFFSET dac ch0 dc offset 0 24 DAC_CH1_DC DAC_CH1_DC 0x64 0x20 read-write 0x00000000 RSVD 24 8 OFFSET dac ch1 dc offset 0 24 RSVD2 RSVD2 0x68 0x20 read-write 0x0 COMMON_CFG COMMON_CFG 0x70 0x20 read-write 0x00000000 RSVD 9 23 DC_MR DC test Macro select 6 3 DC_BR DC test Block select 3 3 DC_TR DC test point select 0 3 BG_CFG0 BG_CFG0 0x74 0x20 read-write 0x00000000 RSVD 14 18 SET_VC set vc 13 1 EN_AMP enable bg opamp 12 1 MIC_VREF_SEL select mic vref 9 3 EN_RCFLT enable bandgap rc filter 8 1 EN_SMPL enable bandgap sample 7 1 EN_CHOP enable bandgap chop 6 1 VREF_SEL set vref, 12: 2.2V 2 4 LP_MODE 1: bandgap lp mode 1 1 EN enable bandgap 0 1 BG_CFG1 BG_CFG1 0x78 0x20 read-write 0x00000000 SAMPCLK_HI bg sample clock high cycle width, based on 0: stop bg sample clock 0 32 BG_CFG2 BG_CFG2 0x7c 0x20 read-write 0x00000000 SAMPCLK_LO bg sample clock low cycle width. 0: stop bg sample clock 0 32 REFGEN_CFG REFGEN_CFG 0x80 0x20 read-write 0x00000000 RSVD 9 23 DISCHG discharge vref 8 1 RZSEL sel Rz, 0: 1uF cap 6 2 LV_MODE low vol mode 5 1 LP_MODE 1: lpmode(adc), 0:dac 4 1 BM bias mode 2 2 EN_CHOP enable ref gen chop 1 1 EN enable ref gen 0 1 PLL_CFG0 PLL_CFG0 0x84 0x20 read-write 0x00000000 RSVD 31 1 SEL_CKREF select ref clock, 2: 24MHz 29 2 EN_IARY enable I array 28 1 EN_VCO enable vco 27 1 SEL_VREF_VCO ldo vref, 7:1.1V 23 4 EN_VCO_FLT vco bais filter 22 1 FC_VCO VCO Fcode 17 5 VCO_LP_MODE 1: lp mode 16 1 EN_ANA enable ana block 15 1 SEL_VREF_ANA ldo vref, 7:1.1V 11 4 ICP_SEL select Icp, 1:1.25u 6 5 OPEN 1: pll open 5 1 ICP_OS_SEL Icp os 0 5 PLL_CFG1 PLL_CFG1 0x88 0x20 read-write 0x00000000 RSVD 16 16 CSD_EN enable CSD 15 1 CSD_RST reset CSD, high active 14 1 CZ_SEL select Cz 11 3 C2_SEL select C2 8 3 RZ_SEL select Rz 4 4 R3_SEL select R3 0 4 PLL_CFG2 PLL_CFG2 0x8c 0x20 read-write 0x00000000 RSVD 19 13 EN_LF_VCIN enable vcin for vco 18 1 SEL_LF_VCIN select vcin, 4: 550mV 15 3 EN_LF_TSTBUF enable vctrl buf 14 1 EN_DIG enable dig block 13 1 SEL_VREF_DIG ldo vref, 7:1.1V 9 4 RSTB resetb 8 1 RSTB_SYNC_EN resetb sync 7 1 TE_DTEST enable dtest 6 1 TR_DTEST select dtest 2 4 MMD_STG mmd stg 0 2 PLL_CFG3 PLL_CFG3 0x90 0x20 read-write 0x00000000 SDMCLK_POL sdm dig clk polarity 31 1 EN_SDM enable sdm 30 1 SDM_DITHER sdm dither 29 1 EN_SDM_DITHER enable sdm dither 28 1 SDM_MODE sdm mode 27 1 SDMIN_BYPASS 1: bypass FCW and SDIN sdm control signal 26 1 SDM_UPDATE write 1 to update FCW and SDIN value 25 1 FCW FCW 20 5 SDIN sdm input 0 20 PLL_CFG4 PLL_CFG4 0x94 0x20 read-write 0x00000000 RSVD 24 8 EN_CLK_DIG enable dig clk 23 1 DIVA_CLK_DIG DIVA dig clk 18 5 CLK_DIG_STR strength 16 2 SEL_CLK_DIG select dig clk 0: pll 1: 24MHz from xtal 15 1 SEL_CLK_DAC_SOURCE 0: xtal 1: pll 13 2 SEL_CLK_DAC 1: select 9.6MHz as DAC clock 12 1 EN_CLK_DAC enable dac clk 11 1 DIVA_CLK_DAC DIVA dac clk 6 5 EN_CLK_CHOP_DAC enable dac chop clk 5 1 DIVA_CLK_CHOP_DAC DIVA dac chop clk 2 3 DIVB_CLK_CHOP_DAC DIVB dac chop clk 0 2 PLL_CFG5 PLL_CFG5 0x98 0x20 read-write 0x00000000 RSVD 29 3 SEL_CLK_DAC2 1: select 9.6MHz as DAC clock 28 1 EN_CLK_DAC2 enable dac2 clk 27 1 DIVA_CLK_DAC2 DIVA dac2 clk 22 5 EN_CLK_CHOP_DAC2 enable dac2 chop clk 21 1 DIVA_CLK_CHOP_DAC2 DIVA dac2 chop clk 18 3 DIVB_CLK_CHOP_DAC2 DIVB dac2 chop clk 16 2 EN_CLK_CHOP_REFGEN enable ref chop clk 15 1 DIVA_CLK_CHOP_REFGEN DIVA ref chop clk 10 5 DIVB_CLK_CHOP_REFGEN DIVB ref chop clk 8 2 EN_CLK_CHOP_BG enable bg chop clk 7 1 DIVA_CLK_CHOP_BG DIVA bg chop clk 2 5 DIVB_CLK_CHOP_BG DIVB bg chop clk 0 2 PLL_CFG6 PLL_CFG6 0x9c 0x20 read-write 0x00000000 RSVD 26 6 SEL_CLK_ADC_SOURCE 0: xtal, 1: pll 24 2 EN_CLK_ADC0 enable adc0 clk 23 1 DIVA_CLK_ADC0 DIVA adc0 clk 20 3 SEL_CLK_ADC0 select adc0 clk 19 1 EN_CLK_ADC1 enable adc1 clk 18 1 DIVA_CLK_ADC1 DIVA adc1 clk 15 3 SEL_CLK_ADC1 select adc1 clk 14 1 EN_CLK_ADC2 enable adc2 clk 13 1 DIVA_CLK_ADC2 DIVA adc2 clk 10 3 SEL_CLK_ADC2 select adc2 clk 9 1 EN_CLK_CHOP_MICBIAS enable micbias chop clk 8 1 SEL_CLK_CHOP_MICBIAS select micbias chop clk 6 2 EN_CLK_RCCAL enable RC CAL clk 5 1 EN_TST_CLK enable test clk 4 1 SEL_TST_CLK select clk to test 0 4 PLL_STAT PLL_STAT 0xa0 0x20 read-write 0x00000000 RSVD 3 29 SLIPPED_DN slip dn 2 1 SLIPPED_UP slip up 1 1 UNLOCK 1:pll unlock 0 1 PLL_CAL_CFG PLL_CAL_CFG 0xa4 0x20 read-write 0x00000000 LEN calibration length 16 16 RSVD 2 14 DONE calibration done 1 1 EN calibration enable 0 1 PLL_CAL_RESULT PLL_CAL_RESULT 0xa8 0x20 read-write 0x00000000 PLL_CNT pll calibration counter result 16 16 XTAL_CNT xtal calibration counter result 0 16 ADC_ANA_CFG ADC_ANA_CFG 0xac 0x20 read-write 0x00000000 RSVD 7 25 CAPCODE ADC cap code 2 5 MICBIAS_EN micbias enable 1 1 MICBIAS_CHOP_EN micbias chopping enable 0 1 ADC1_CFG1 ADC1_CFG1 0xb0 0x20 read-write 0x00000000 RSVD 25 7 FSP sampling frequency: 0x0:9.6M 0x1:8.82M 0x2:4.8M 0x3:4.41M 23 2 DIFF_EN enable differential input mode 22 1 DACN_EN enable negative DAC1 21 1 GC gaincode: 0x0:-6dB 0x1:0dB ... 0x4:18dB 18 3 VST_SEL start voltage 0x0:VCM+200mV 0x7:VCM+550mV 15 3 BM_INT1 bias mode of first opamp 12 3 BM_INT2 bias mode of 2nd and 3rd opamp 9 3 VREF_SEL vref code from proper vcm in flash7 0x0:1.2V 0x1:1.4V 0x7:2.6V 6 3 FCHOP_SEL chopping frequncy 0x0:÷8 0x1:÷16 0x2:÷32 0x3:÷64 4 2 VCMST VCM quick settling 3 1 CLKOUT_INV inverse output clock 2 1 PERI_BM peripheral circuits biasmode 0 2 ADC1_CFG2 ADC1_CFG2 0xb4 0x20 read-write 0x00000000 RSVD 4 28 EN enable adc 3 1 RSTB reset adc 2 1 CHOP_EN chopping enable 1 1 CLEAR clear adc 0 1 ADC2_CFG1 ADC2_CFG1 0xb8 0x20 read-write 0x00000000 RSVD 25 7 FSP sampling frequency: 0x0:9.6M 0x1:8.82M 0x2:4.8M 0x3:4.41M 23 2 GC gaincode: 0x0:-10dB 0xa:0dB 0x1e:20dB 18 5 VST_SEL start voltage 0x0:VCM+200mV 0x7:VCM+550mV 15 3 BM_INT1 bias mode of first opamp 12 3 BM_INT2 bias mode of 2nd and 3rd opamp 9 3 VREF_SEL vref code from proper vcm in flash7 0x0:1.2V 0x1:1.4V 0x7:2.6V 6 3 FCHOP_SEL chopping frequncy 0x0:÷8 0x1:÷16 0x2:÷32 0x3:÷64 4 2 VCMST VCM quick settling 3 1 CLKOUT_INV inverse output clock 2 1 PERI_BM peripheral circuits biasmode 0 2 ADC2_CFG2 ADC2_CFG2 0xbc 0x20 read-write 0x00000000 RSVD 4 28 EN enable adc 3 1 RSTB reset adc 2 1 CHOP_EN chopping enable 1 1 CLEAR clear adc 0 1 DAC1_CFG DAC1_CFG 0xc0 0x20 read-write 0x00000000 RSVD 26 6 SEL_VSTART select Vstart 24 2 EN_DAC enable dac 23 1 EN_VCM enable vcm 22 1 EN_AMP enable amp 21 1 EN_CHOP enable chop 20 1 BM bias mode 18 2 SEL_VCM select vcm 15 3 LP_MODE 0: 3.3V sup, 1: 1.8V supply 14 1 POL_CLK dac clk polarity 13 1 SR dac short switch 12 1 GAIN dac gain 8 4 OS_DAC os dac 1 7 EN_OS_DAC enable os dac 0 1 DAC2_CFG DAC2_CFG 0xc4 0x20 read-write 0x00000000 RSVD 26 6 SEL_VSTART select Vstart 24 2 EN_DAC enable dac 23 1 EN_VCM enable vcm 22 1 EN_AMP enable amp 21 1 EN_CHOP enable chop 20 1 BM bias mode 18 2 SEL_VCM select vcm 15 3 LP_MODE 0: 3.3V sup, 1: 1.8V supply 14 1 POL_CLK dac clk polarity 13 1 SR dac short switch 12 1 GAIN dac gain 8 4 OS_DAC os dac 1 7 EN_OS_DAC enable os dac 0 1 RSVD1 RSVD1 0xC8 0x20 read-write 0x0 RESERVED_IN0 RESERVED_IN0 0xd0 0x20 read-write 0x00000000 CTRL3 reserved control 3 24 8 CTRL2 reserved control 2 16 8 CTRL1 reserved control 1 8 8 CTRL0 reserved control 0 0 8 RESERVED_IN1 RESERVED_IN1 0xd4 0x20 read-write 0x00000000 RSVD 16 16 CTRL5 reserved control 5 8 8 CTRL4 reserved control 4 0 8 RESERVED_OUT RESERVED_OUT 0xd8 0x20 read-write 0x00000000 RSVD 16 16 STAT1 reserved status1 8 8 STAT0 reserved status0 0 8 TSEN TSEN 0x50089000 0x0 0x1000 registers TSEN_CTRL_REG TSEN_CTRL_REG TSEN Analog Control Register 0x00 0x20 read-write 0x04714A44 RSVD 18 14 ANAU_TSEN_CLK_DIV gen tsen clk by divide hclk by anau_tsen_clk_div 12 6 ANAU_TSEN_EN Enable tsen digital module 11 1 ANAU_TSEN_RDY tsen ready 10 1 ANAU_TSEN_SER_PAR_SEL serial-parallel output selection 9 1 ANAU_TSEN_SGN_EN signature-mode enable 8 1 ANAU_TSEN_FCK_SEL select internal clock frequency 6 2 ANAU_TSEN_IG_VBE bias current selection to tune vba 3 3 ANAU_TSEN_RUN enable tsen run 2 1 ANAU_TSEN_RSTB resetb for tsen 1 1 ANAU_TSEN_PU power up tsen 0 1 TSEN_RDATA TSEN_RDATA Tsen Read Data 0x04 0x20 read-write 0x00000000 RSVD 12 20 TSEN_RDATA 0 12 TSEN_IRQ TSEN_IRQ Tsen IRQ Register 0x08 0x20 read-write 0x00000000 RSVD 4 28 TSEN_ISR 3 1 TSEN_IRSR 2 1 TSEN_IMR 1 1 TSEN_ICR 0 1 GPTIM1 GPTIM 0x50090000 0x0 0x1000 registers CR1 CR1 TIM control register 1 0x00 0x20 read-write 0x00000000 RSVD 12 20 UIFREMAP UIF status bit remapping 0: No remapping. UIF status bit is not copied to CNT register bit 31 1: Remapping enabled. UIF status bit is copied to CNT register bit 31 11 1 RSVD2 8 3 ARPE Auto-reload preload enable 0: ARR register is not buffered 1: ARR register is buffered 7 1 CMS Center-aligned mode selection 00: Edge-aligned mode. The counter counts up or down depending on the direction bit (DIR). 01: Center-aligned mode 1. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in CCMRx register) are set only when the counter is counting down. 10: Center-aligned mode 2. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in CCMRx register) are set only when the counter is counting up. 11: Center-aligned mode 3. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in CCMRx register) are set both when the counter is counting up or down. 5 2 DIR Direction 0: Counter used as upcounter 1: Counter used as downcounter 4 1 OPM One-pulse mode 0: Counter is not stopped at update event 1: Counter stops counting at the next update event (clearing the bit CEN) 3 1 URS Update request source This bit is set and cleared by software to select the UEV event sources. 0: Any of the following events generate an update interrupt or DMA request if enabled. These events can be: Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller 1: Only counter overflow/underflow generates an update interrupt or DMA request if enabled. 2 1 UDIS Update disable This bit is set and cleared by software to enable/disable UEV event generation. 0: UEV enabled. The Update (UEV) event is generated by one of the following events: Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values. 1: UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller. 1 1 CEN Counter enable 0: Counter disabled 1: Counter enabled Note: External clock, gated mode and encoder mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. CEN is cleared automatically in one-pulse mode, when an update event occurs. 0 1 CR2 CR2 TIM control register 2 0x04 0x20 read-write 0x00000000 RSVD 8 24 TI1S TI1 selection 0: The CH1 pin is connected to TI1 input 1: The CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) 7 1 MMS Master mode selection These bits allow to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: 000: Reset - the UG bit from the EGR register is used as trigger output (TRGO). If the reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on TRGO is delayed compared to the actual reset. 001: Enable - the Counter enable signal is used as trigger output (TRGO). It is useful to start several timers at the same time or to control a window in which a slave timer is enabled. The Counter Enable signal is generated by a logic OR between CEN control bit and the trigger input when configured in gated mode. When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected. 010: Update - The update event is selected as trigger output (TRGO). For instance a master timer can then be used as a prescaler for a slave timer. 011: Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or a compare match occurred. (TRGO) 100: Compare - OC1REF signal is used as trigger output (TRGO) 101: Compare - OC2REF signal is used as trigger output (TRGO) 110: Compare - OC3REF signal is used as trigger output (TRGO) 111: Compare - OC4REF signal is used as trigger output (TRGO) 4 3 CCDS Capture/compare DMA selection 0: CCx DMA request sent when CCx event occurs 1: CCx DMA requests sent when update event occurs 3 1 RSVD2 0 3 SMCR SMCR TIM slave mode control register 0x08 0x20 read-write 0x00000000 RSVD 20 12 SMS Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input. 0000: Slave mode disabled. 0001: Encoder mode 1 - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level. 0010: Encoder mode 2 - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level. 0011: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. 0100: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers. 0101: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled. 0110: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled. 0111: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter. 1000: Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter. 16 4 ETP External trigger polarity 0: ETR is non-inverted, active at high level or rising edge 1: ETR is inverted, active at low level or falling edge 15 1 ECE External clock enable This bit enables External clock mode 2. 0: External clock mode 2 disabled 1: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal. 14 1 ETPS External trigger prescaler External trigger signal ETRP frequency must be at most 1/4 of CK_INT frequency. A prescaler can be enabled to reduce ETRP frequency. It is useful when inputting fast external clocks. 00: Prescaler OFF 01: ETRP frequency divided by 2 10: ETRP frequency divided by 4 11: ETRP frequency divided by 8 12 2 ETF External trigger filter This bit-field then defines the frequency used to sample ETRP signal and the length of the digital filter applied to ETRP. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: 0000: No filter 0001: fSAMPLING=fCLK, N=2 0010: fSAMPLING=fCLK, N=4 0011: fSAMPLING=fCLK, N=8 0100: fSAMPLING=fCLK/2, N=6 0101: fSAMPLING=fCLK/2, N=8 0110: fSAMPLING=fCLK/4, N=6 0111: fSAMPLING=fCLK/4, N=8 1000: fSAMPLING=fCLK/8, N=6 1001: fSAMPLING=fCLK/8, N=8 1010: fSAMPLING=fCLK/16, N=5 1011: fSAMPLING=fCLK/16, N=6 1100: fSAMPLING=fCLK/16, N=8 1101: fSAMPLING=fCLK/32, N=5 1110: fSAMPLING=fCLK/32, N=6 1111: fSAMPLING=fCLK/32, N=8 8 4 MSM Master/Slave mode 0: No action 1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event. 7 1 TS Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. 000: Internal Trigger 0 (ITR0) 001: Internal Trigger 1 (ITR1) 010: Internal Trigger 2 (ITR2) 011: Internal Trigger 3 (ITR3) 100: TI1 Edge Detector (TI1F_ED) 101: Filtered Timer Input 1 (TI1FP1) 110: Filtered Timer Input 2 (TI2FP2) 111: External Trigger input (ETRF) 4 3 RSVD2 0 4 DIER DIER TIM DMA/Interrupt enable register 0x0c 0x20 read-write 0x00000000 RSVD 15 17 TDE Trigger DMA request enable 0: Trigger DMA request disabled. 1: Trigger DMA request enabled. 14 1 RSVD2 13 1 CC4DE Capture/Compare 4 DMA request enable 0: CC4 DMA request disabled. 1: CC4 DMA request enabled 12 1 CC3DE Capture/Compare 3 DMA request enable 0: CC3 DMA request disabled. 1: CC3 DMA request enabled. 11 1 CC2DE Capture/Compare 2 DMA request enable 0: CC2 DMA request disabled. 1: CC2 DMA request enabled. 10 1 CC1DE Capture/Compare 1 DMA request enable 0: CC1 DMA request disabled. 1: CC1 DMA request enabled. 9 1 UDE Update DMA request enable 0: Update DMA request disabled. 1: Update DMA request enabled 8 1 RSVD3 7 1 TIE Trigger interrupt enable 0: Trigger interrupt disabled. 1: Trigger interrupt enabled 6 1 RSVD4 5 1 CC4IE Capture/Compare 4 interrupt enable 0: CC4 interrupt disabled. 1: CC4 interrupt enabled 4 1 CC3IE Capture/Compare 3 interrupt enable 0: CC3 interrupt disabled. 1: CC3 interrupt enabled 3 1 CC2IE Capture/Compare 2 interrupt enable 0: CC2 interrupt disabled. 1: CC2 interrupt enabled. 2 1 CC1IE Capture/Compare 1 interrupt enable 0: CC1 interrupt disabled. 1: CC1 interrupt enabled 1 1 UIE Update interrupt enable 0: Update interrupt disabled. 1: Update interrupt enabled 0 1 SR SR TIM status register 0x10 0x20 read-write 0x00000000 RSVD 13 19 CC4OF Capture/Compare 4 overcapture flag 12 1 CC3OF Capture/Compare 3 overcapture flag 11 1 CC2OF Capture/Compare 2 overcapture flag 10 1 CC1OF Capture/Compare 1 overcapture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing it to '0'. 0: No overcapture has been detected. 1: The counter value has been captured in CCR1 register while CC1IF flag was already set 9 1 RSVD2 7 2 TIF Trigger interrupt flag This flag is set by hardware on trigger event (active edge detected on TRGI input when the slave mode controller is enabled in all modes but gated mode). It is set when the counter starts or stops when gated mode is selected. It is cleared by software. 0: No trigger event occurred. 1: Trigger interrupt pending. 6 1 RSVD3 5 1 CC4IF Capture/Compare 4 interrupt flag 4 1 CC3IF Capture/Compare 3 interrupt flag 3 1 CC2IF Capture/Compare 2 interrupt flag 2 1 CC1IF Capture/Compare 1 interrupt flag If channel CC1 is configured as output: This flag is set by hardware when the counter matches the compare value. It is cleared by software. 0: No match. 1: The content of the counter CNT has matched the content of the CCR1 register. If channel CC1 is configured as input: This bit is set by hardware on a capture. It is cleared by software or by reading the CCR1 register. 0: No input capture occurred. 1: The counter value has been captured in CCR1 register (An edge has been detected on IC1 which matches the selected polarity). 1 1 UIF Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. 0: No update occurred 1: Update interrupt pending. This bit is set by hardware when the registers are updated: At overflow or underflow and if UDIS=0 in the CR1 register. When CNT is reinitialized by software using the UG bit in EGR register, if URS=0 and UDIS=0 in the CR1 register. When CNT is reinitialized by a trigger event, if URS=0 and UDIS=0 in the CR1 register. 0 1 EGR EGR Event generation register 0x14 0x20 read-write 0x00000000 RSVD 7 25 TG Trigger generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 0: No action 1: The TIF flag is set in SR register. Related interrupt or DMA transfer can occur if enabled. 6 1 RSVD2 5 1 CC4G Capture/compare 4 generation 4 1 CC3G Capture/compare 3 generation 3 1 CC2G Capture/compare 2 generation 2 1 CC1G Capture/compare 1 generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 0: No action 1: A capture/compare event is generated on channel 1: If channel CC1 is configured as output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If channel CC1 is configured as input: The current value of the counter is captured in CCR1 register. The CC1IF flag is set, the corresponding interrupt or DMA request is sent if enabled. The CC1OF flag is set if the CC1IF flag was already high. 1 1 UG Update generation This bit can be set by software, it is automatically cleared by hardware. 0: No action 1: Re-initialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected). The counter is cleared if the center-aligned mode is selected or if DIR=0 (upcounting), else it takes the auto-reload value (ARR) if DIR=1 (downcounting). 0 1 CCMR1 CCMR1 TIM capture/compare mode register 1 0x18 0x20 read-write 0x00000000 OC2M Output compare 2 mode 28 4 OC2PE Output compare 2 preload enable 27 1 RSVD 25 2 OC2CE Output compare 2 clear enable 24 1 OC1M Output compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits. 0000: Frozen - The comparison between the output compare register CCR1 and the counter CNT has no effect on the outputs.(this mode is used to generate a timing base). 0001: Set channel 1 to active level on match. OC1REF signal is forced high when the counter CNT matches the capture/compare register 1 (CCR1). 0010: Set channel 1 to inactive level on match. OC1REF signal is forced low when the counter CNT matches the capture/compare register 1 (CCR1). 0011: Toggle - OC1REF toggles when CNT=CCR1. 0100: Force inactive level - OC1REF is forced low. 0101: Force active level - OC1REF is forced high. 0110: PWM mode 1 - In upcounting, channel 1 is active as long as CNT(CCR1 else inactive. In downcounting, channel 1 is inactive (OC1REF='0) as long as CNT>CCR1 else active (OC1REF=1). 0111: PWM mode 2 - In upcounting, channel 1 is inactive as long as CNT(CCR1 else active. In downcounting, channel 1 is active as long as CNT>CCR1 else inactive. 1000: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes inactive again at the next update. In down-counting mode, the channel is inactive until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes inactive again at the next update. 1001: Retriggerable OPM mode 2 - In up-counting mode, the channel is inactive until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 2 and the channels becomes inactive again at the next update. In down-counting mode, the channel is active until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes active again at the next update. 1010: Reserved, 1011: Reserved, 1100: Combined PWM mode 1 - OC1REF has the same behavior as in PWM mode 1. OC1REFC is the logical OR between OC1REF and OC2REF. 1101: Combined PWM mode 2 - OC1REF has the same behavior as in PWM mode 2. OC1REFC is the logical AND between OC1REF and OC2REF. 1110: Asymmetric PWM mode 1 - OC1REF has the same behavior as in PWM mode 1. OC1REFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down. 1111: Asymmetric PWM mode 2 - OC1REF has the same behavior as in PWM mode 2. OC1REFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down. 20 4 OC1PE Output compare 1 preload enable 0: Preload register on CCR1 disabled. CCR1 can be written at anytime, the new value is taken in account immediately. 1: Preload register on CCR1 enabled. Read/Write operations access the preload register. CCR1 preload value is loaded in the active register at each update event. 19 1 RSVD2 17 2 OC1CE Output compare 1 clear enable 0: OC1Ref is not affected by the ETRF input 1: OC1Ref is cleared as soon as a High level is detected on ETRF input 16 1 IC2F Input capture 2 filter 12 4 IC2PSC Input capture 2 prescaler 10 2 CC2S Capture/Compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC2 channel is configured as output 01: CC2 channel is configured as input, IC2 is mapped on TI2 10: CC2 channel is configured as input, IC2 is mapped on TI1 11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if an internal trigger input is selected through the TS bit (SMCR register) 8 2 IC1F Input capture 1 filter This bit-field defines the frequency used to sample TI1 input and the length of the digital filter applied to TI1. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: 0000: No filter, sampling is done at fCLK 0001: fSAMPLING=fCLK, N=2 0010: fSAMPLING=fCLK, N=4 0011: fSAMPLING=fCLK, N=8 0100: fSAMPLING=fCLK/2, N=6 0101: fSAMPLING=fCLK/2, N=8 0110: fSAMPLING=fCLK/4, N=6 0111: fSAMPLING=fCLK/4, N=8 1000: fSAMPLING=fCLK/8, N=6 1001: fSAMPLING=fCLK/8, N=8 1010: fSAMPLING=fCLK/16, N=5 1011: fSAMPLING=fCLK/16, N=6 1100: fSAMPLING=fCLK/16, N=8 1101: fSAMPLING=fCLK/32, N=5 1110: fSAMPLING=fCLK/32, N=6 1111: fSAMPLING=fCLK/32, N=8 4 4 IC1PSC Input capture 1 prescaler This bit-field defines the ratio of the prescaler acting on CC1 input (IC1). The prescaler is reset as soon as CC1E=0. 00: no prescaler, capture is done each time an edge is detected on the capture input 01: capture is done once every 2 events 10: capture is done once every 4 events 11: capture is done once every 8 events 2 2 CC1S Capture/Compare 1 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC1 channel is configured as output 01: CC1 channel is configured as input, IC1 is mapped on TI1 10: CC1 channel is configured as input, IC1 is mapped on TI2 11: CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (SMCR register) 0 2 CCMR2 CCMR2 TIM capture/compare mode register 2 0x1c 0x20 read-write 0x00000000 OC4M Output compare 4 mode 28 4 OC4PE Output compare 4 preload enable 27 1 RSVD 25 2 OC4CE Output compare 4 clear enable 24 1 OC3M Output compare 3 mode 20 4 OC3PE Output compare 3 preload enable 19 1 RSVD2 17 2 OC3CE Output compare 3 clear enable 16 1 IC4F Input capture 4 filter 12 4 IC4PSC Input capture 4 prescaler 10 2 CC4S Capture/Compare 4 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC4 channel is configured as output 01: CC4 channel is configured as input, IC4 is mapped on TI4 10: CC4 channel is configured as input, IC4 is mapped on TI3 11: CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (SMCR register) 8 2 IC3F Input capture 3 filter 4 4 IC3PSC Input capture 3 prescaler 2 2 CC3S Capture/Compare 3 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC3 channel is configured as output 01: CC3 channel is configured as input, IC3 is mapped on TI3 10: CC3 channel is configured as input, IC3 is mapped on TI4 11: CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (SMCR register) 0 2 CCER CCER Capture/Compare enable register 0x20 0x20 read-write 0x00000000 RSVD 16 16 CC4NP Capture/Compare 4 output Polarity. 15 1 RSVD2 14 1 CC4P Capture/Compare 4 output Polarity. 13 1 CC4E Capture/Compare 4 output enable. 12 1 CC3NP Capture/Compare 3 output Polarity. 11 1 RSVD3 10 1 CC3P Capture/Compare 3 output Polarity. 9 1 CC3E Capture/Compare 3 output enable. 8 1 CC2NP Capture/Compare 2 output Polarity. 7 1 RSVD4 6 1 CC2P Capture/Compare 2 output Polarity. 5 1 CC2E Capture/Compare 2 output enable. 4 1 CC1NP Capture/Compare 1 output Polarity. CC1 channel configured as output: CC1NP must be kept cleared in this case. CC1 channel configured as input: This bit is used in conjunction with CC1P to define TI1FP1/TI2FP1 polarity. refer to CC1P description. 3 1 RSVD5 2 1 CC1P Capture/Compare 1 output Polarity. CC1 channel configured as output: 0: OC1 active high 1: OC1 active low CC1 channel configured as input: CC1NP/CC1P bits select TI1FP1 and TI2FP1 polarity for trigger or capture operations. 00: noninverted/rising edge Circuit is sensitive to TIxFP1 rising edge (capture, trigger in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger in gated mode, encoder mode). 01: inverted/falling edge Circuit is sensitive to TIxFP1 falling edge (capture, trigger in reset, external clock or trigger mode), TIxFP1 is inverted (trigger in gated mode, encoder mode). 10: reserved, do not use this configuration. 11: noninverted/both edges Circuit is sensitive to both TIxFP1 rising and falling edges (capture, trigger in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger in gated mode). This configuration must not be used for encoder mode. 1 1 CC1E Capture/Compare 1 output enable. CC1 channel configured as output: 0: Off - OC1 is not active 1: On - OC1 signal is output on the corresponding output pin CC1 channel configured as input: This bit determines if a capture of the counter value can actually be done into the input capture/compare register 1 (CCR1) or not. 0: Capture disabled 1: Capture enabled 0 1 CNT CNT Counter 0x24 0x20 read-write 0x00000000 UIFCPY Value depends on IUFREMAP in CR1. If UIFREMAP = 1 UIFCPY: UIF Copy This bit is a read-only copy of the UIF bit of the ISR register 31 1 RSVD 16 15 CNT counter value 0 16 PSC PSC Prescaler 0x28 0x20 read-write 0x00000000 RSVD 16 16 PSC Prescaler value The counter clock frequency is equal to fCLK / (PSC[15:0] + 1). PSC contains the value to be loaded in the active prescaler register at each update event (including when the counter is cleared through UG bit of EGR register or through trigger controller when configured in 'reset mode'). 0 16 ARR ARR Auto-reload register 0x2c 0x20 read-write 0x00000000 RSVD 16 16 ARR Auto-reload value ARR is the value to be loaded in the actual auto-reload register. 0 16 RCR RCR Repetition counter register 0x30 0x20 read-write 0x00000000 RSVD 8 24 REP Repetition counter value These bits allow the user to set-up the update rate of the compare registers (i.e. periodic transfers from preload to active registers) when preload registers are enable, as well as the update interrupt generation rate, if this interrupt is enable. Each time the REP_CNT related downcounter reaches zero, an update event is generated and it restarts counting from REP value. As REP_CNT is reloaded with REP value only at the repetition update event, any write to the RCR register is not taken in account until the next repetition update event. It means in PWM mode (REP+1) corresponds to the number of PWM periods in edge-aligned mode. 0 8 CCR1 CCR1 Capture/Compare register 1 0x34 0x20 read-write 0x00000000 RSVD 16 16 CCR1 Capture/Compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value).It is loaded permanently if the preload feature is not selected in the CCMR1 register (bit OC1PE). Else the preload value is copied in the active capture/compare 1 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter CNT and signaled on OC1 output. If channel CC1is configured as input: CCR1 is the counter value transferred by the last input capture 1 event (IC1). The CCR1 register is read-only and cannot be programmed. 0 16 CCR2 CCR2 Capture/Compare register 2 0x38 0x20 read-write 0x00000000 RSVD 16 16 CCR2 Capture/Compare 2 value If channel CC2 is configured as output: CCR2 is the value to be loaded in the actual capture/compare 2 register (preload value).It is loaded permanently if the preload feature is not selected in the CCMR1 register (bit OC2PE). Else the preload value is copied in the active capture/compare 2 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter CNT and signalled on OC2 output. If channel CC2 is configured as input: CCR2 is the counter value transferred by the last input capture 2 event (IC2). The CCR2 register is read-only and cannot be programmed. 0 16 CCR3 CCR3 Capture/Compare register 3 0x3c 0x20 read-write 0x00000000 RSVD 16 16 CCR3 Capture/Compare value If channel CC3 is configured as output: CCR3 is the value to be loaded in the actual capture/compare 3 register (preload value).It is loaded permanently if the preload feature is not selected in the CCMR2 register (bit OC3PE). Else the preload value is copied in the active capture/compare 3 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter CNT and signalled on OC3 output. If channel CC3is configured as input: CCR3 is the counter value transferred by the last input capture 3 event (IC3). The CCR3 register is read-only and cannot be programmed. 0 16 CCR4 CCR4 Capture/Compare register 4 0x40 0x20 read-write 0x00000000 RSVD 16 16 CCR4 Capture/Compare value 1. if CC4 channel is configured as output: CCR4 is the value to be loaded in the actual capture/compare 4 register (preload value).It is loaded permanently if the preload feature is not selected in the CCMR2 register (bit OC4PE). Else the preload value is copied in the active capture/compare 4 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter CNT and signalled on OC4 output. 2. if CC4 channel is configured as input: CCR4 is the counter value transferred by the last input capture 4 event (IC4). The CCR4 register is read-only and cannot be programmed. 0 16 BTIM1 BTIM 0x50092000 0x0 0x1000 registers CR1 CR1 TIM control register 1 0x00 0x20 read-write 0x00000000 RSVD 8 24 ARPE Auto-reload preload enable 0: ARR register is not buffered 1: ARR register is buffered 7 1 RSVD2 4 3 OPM One-pulse mode 0: Counter is not stopped at update event 1: Counter stops counting at the next update event (clearing the bit CEN) 3 1 URS Update request source This bit is set and cleared by software to select the UEV event sources. 0: Any of the following events generate an update interrupt or DMA request if enabled. These events can be: Counter overflow Setting the UG bit Update generation through the slave mode controller 1: Only counter overflow generates an update interrupt or DMA request if enabled. 2 1 UDIS Update disable This bit is set and cleared by software to enable/disable UEV event generation. 0: UEV enabled. The Update (UEV) event is generated by one of the following events: Counter overflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values. 1: UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller. 1 1 CEN Counter enable 0: Counter disabled 1: Counter enabled Note: Gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. CEN is cleared automatically in one-pulse mode, when an update event occurs. 0 1 CR2 CR2 TIM control register 2 0x04 0x20 read-write 0x00000000 RSVD 6 26 MMS Master mode selection These bits allow to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: 00: Reset:the UG bit from the EGR register is used as trigger output (TRGO). If the reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on TRGO is delayed compared to the actual reset. 01: Enable :the Counter enable signal, CNT_EN, is used as trigger output (TRGO). It is useful to start several timers at the same time or to control a window in which a slave timer is enabled. The Counter Enable signal is generated by a logic OR between CEN control bit and the trigger input when configured in gated mode. When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in SMCR register). 10: Update:The update event is selected as trigger output (TRGO). For instance a master timer can then be used as a prescaler for a slave timer. 11: Gating:The delayed gating trigger is selected as trigger output (TRGO). 4 2 RSVD2 0 4 SMCR SMCR TIM slave mode control register 0x08 0x20 read-write 0x00000000 RSVD 24 8 GM Gated Mode. The counter clock is enabled when the selected trigger input (TRGI) is active (according to gating trigger polarity). The counter stops (but is not reset) as soon as the trigger becomes inactive. Both start and stop of the counter are controlled. Gated mode and slave mode can be enabled simutanuously with different trigger selection. 23 1 GTP Gating trigger polarity invert 0: active at high level 1: active at low level 22 1 GTS Gating trigger selection in gated mode This bit-field selects the trigger input to be used to enable the counter gating. 00: Internal Trigger 0 (ITR0) 01: Internal Trigger 1 (ITR1) 10: Internal Trigger 2 (ITR2) 11: Internal Trigger 3 (ITR3) 20 2 RSVD2 19 1 SMS Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input. 000: Slave mode disabled. 001: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers. 010: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled. 011: Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter. 100: External Clock Mode - Rising edges of the selected trigger (TRGI) clock the counter. 16 3 RSVD3 8 8 MSM Master/Slave mode. This bit should be asserted on master timer if synchronization if needed. 0: No action 1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event. 7 1 RSVD4 6 1 TS Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. 00: Internal Trigger 0 (ITR0) 01: Internal Trigger 1 (ITR1) 10: Internal Trigger 2 (ITR2) 11: Internal Trigger 3 (ITR3) 4 2 RSVD5 0 4 DIER DIER TIM DMA/Interrupt enable register 0x0c 0x20 read-write 0x00000000 RSVD 9 23 UDE Update DMA request enable 0: Update DMA request disabled. 1: Update DMA request enabled 8 1 RSVD2 1 7 UIE Update interrupt enable 0: Update interrupt disabled. 1: Update interrupt enabled 0 1 SR SR TIM status register 0x10 0x20 read-write 0x00000000 RSVD 1 31 UIF Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. 0: No update occurred 1: Update interrupt pending. This bit is set by hardware when the registers are updated: At overflow and if UDIS=0 in the CR1 register. When CNT is reinitialized by software using the UG bit in EGR register, if URS=0 and UDIS=0 in the CR1 register. When CNT is reinitialized by a trigger event (refer to the synchro control register description), if URS=0 and UDIS=0 in the CR1 register. 0 1 EGR EGR Event generation register 0x14 0x20 read-write 0x00000000 RSVD 1 31 UG Update generation This bit can be set by software, it is automatically cleared by hardware. 0: No action 1: Re-initialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected). The counter is cleared if the center-aligned mode is selected or if DIR=0 (upcounting), else it takes the auto-reload value (ARR) if DIR=1 (downcounting). 0 1 RSVD1 RSVD1 0x18 0x20 read-write 0x0 CNT CNT Counter 0x24 0x20 read-write 0x00000000 CNT counter value 0 32 PSC PSC Prescaler 0x28 0x20 read-write 0x00000000 RSVD 16 16 PSC Prescaler value The counter clock frequency is equal to fCLK / (PSC[15:0] + 1). PSC contains the value to be loaded in the active prescaler register at each update event (including when the counter is cleared through UG bit of EGR register or through trigger controller when configured in "reset mode"). 0 16 ARR ARR Auto-reload register 0x2c 0x20 read-write 0x00000000 ARR Auto-reload value ARR is the value to be loaded in the actual auto-reload register. The counter is blocked while the auto-reload value is null. 0 32 WDT1 WDT 0x50094000 0x0 0x1000 registers WDT_CVR0 WDT_CVR0 WatchDog Counter Value 0 0x00 0x20 read-write 0x0 RSVD 24 8 COUNT_VALUE_0 Count Value for 1st TimeOut 0 24 WDT_CVR1 WDT_CVR1 WatchDog Counter Value 1 0x04 0x20 read-write 0x0 RSVD 24 8 COUNT_VALUE_1 Count Value for 2nd TimeOut 0 24 WDT_CR WDT_CR WatchDog Control Register 0x08 0x20 read-write 0x0 RSVD 5 27 RESPONSE_MODE 0:reset only, 1:interrupt and reset 4 1 RSVD2 3 1 RESET_LENGTH reset pulse length in number of wdt clock cycles 0 3 WDT_CCR WDT_CCR WatchDog Counter Control Register 0x0c 0x20 read-write 0x0 RSVD 8 24 COUNTER_CONTROL SinglePulse /Write 8'h76 to restart, write8'h34 to stop, else do nothing 0 8 WDT_ICR WDT_ICR WatchDog Interrupt Clear Register 0x10 0x20 read-write 0x0 RSVD 1 31 INT_CLR SinglePulse /A pulse to clear interrupt 0 1 WDT_SR WDT_SR WatchDog Status Register 0x14 0x20 read-write 0x0 RSVD 2 30 WDT_ACTIVE Watchdog runs when 1, else 0 1 1 INT_ASSERT Interrupt assert when 1 0 1 WDT_WP WDT_WP WatchDog Write Protect Register 0x18 0x20 read-write 0x0 WRPT_ST 1 indicates write protect is active 31 1 WRPT write 0x58ab99fc generate write_protect, write 0x51ff8621 to release 0 31 WDT_FG WDT_FG WatchDog Flag Register 0x1c 0x20 read-write 0x0 RSVD 4 28 SYNC_FG 1 indicates one transition from system clk to wdt clk has complicated 3 1 SYNC_FG_CLR SinglePulse/A pulse to clear sync flag 2 1 RST_FG 1 indicates wdt has already reset system 1 1 RST_FG_CLR SinglePulse/A pulse to clear reset flag 0 1 SPI1 SPI 0x50095000 0x0 0x1000 registers TOP_CTRL TOP_CTRL Top Control Register 0x00 0x20 read-write 0x00000000 RSVD 19 13 TTELP SPI_DO Three-state Enable On Last Phase (can be set only when TI-SSP) 0: SPI_DO is three-stated 1/2 clock cycle after the beginning of the LSB 1: SPI_DO output signal is three-stated on the clock edge that ends the LSB 18 1 TTE SPI_DO Three-State Enable 0: SPI_DO output signal is not three-stated 1: SPI_DO is three-stated when not transmitting data 17 1 RSVD2 16 1 IFS Invert Frame Signal 0: SPI_CS polarity is as defined in protocol 1: SPI_CS will be inverted from normal-SPI_CS 15 1 HOLD_FRAME_LOW Hold Frame Low Control 0:After this field is set to 1 and the SPI controller is operating in master mode,the output frame signal SPI_CS will be determined by control FSM. 1:After this field is set to 1 and the SPI controller is operating in master mode, the output frame signal SPI_CS will hold low. 14 1 TRAIL Trailing Byte 0: Trailing bytes are handled by CPU 1: Trailing bytes are handled by DMA bursts 13 1 RSVD3 12 1 SPH Motorola SPI SPI_CLK phase setting 0: SPI_CLK is inactive until one cycle after the start of a frame and active until 1/2 cycle before the end of a frame 1: SPI_CLK is inactive until 1/2 cycle after the start of a frame and active until one cycle before the end of a frame 11 1 SPO Motorola SPI SPI_CLK Polarity Setting 0: The inactive or idle state of SPI_CLK is low 1: The inactive or idle state of SPI_CLK is high 10 1 DSS SPI controller Work data size, register bits value 0~31 indicated data size 1~32 bits, usually use data size 8bits, 16bits, 24bits, 32bits 5 5 SFRMDIR SPI_CS Direction 0: Master mode, SPI controller drives SPI_CS 1: Slave mode, SPI controller receives SPI_CS 4 1 SCLKDIR SPI_CLK Direction 0: Master mode, SPI controller drives SPI_CLK 1: Slave mode, SPI controller receives SPI_CLK 3 1 FRF Frame Format 0x0: Motorola* Serial Peripheral Interface (SPI) 0x1: Texas Instruments* Synchronous Serial Protocol (SSP) 0x2: National Semiconductor Microwire* 0x3: RSVD 1 2 SSE SPI controller Enable 0: SPI controller is disabled 1: SPI controller is enabled 0 1 FIFO_CTRL FIFO_CTRL FIFO Control Register 0x04 0x20 read-write 0x00000000 RSVD 18 14 RXFIFO_AUTO_FULL_CTRL Rx FIFO Auto Full Control: After this field is set to 1 and the SPI controller is operating in master mode, the controller FSM returns to IDLE state and stops the SPI_CLK. When Rx FIFO is full, the controller FSM continues transferring data after the RxFIFO is not full. This field is used to avoid an RxFIFO overrun issue. 1: Enable Rx FIFO auto full control 17 1 FPCKE FIFO Packing Enable 0: FIFO packing mode disabled 1: FIFO packing mode enabled 16 1 TXFIFO_WR_ENDIAN apb_pwdata Write to TxFIFO Endian 0x0: txfifo_wdata[31:0] = apb_pwdata[31:0] 0x1: fifo_wdata[31:0] = {apb_pwdata[15:0], apb_pwdata[31:16]} 0x2: txfifo_wdata[31:0] = {apb_pwdata[7:0], apb_pwdata[15:8], apb_pwdata[23:16], apb_pwdata[31:24]} 0x3: txfifo_wdata[31:0] = {apb_pwdata[23:16], apb_pwdata[31:24], apb_pwdata[7:0], apb_pwdata[15:8]} 14 2 RXFIFO_RD_ENDIAN apb_prdata Read from Rx FIFO Endian 0x0 = apb_prdata[31:0] = rxfifo_wdata[31:0] 0x1 = apb_prdata[31:0] = {rxfifo_wdata[15:0], rxfifo_wdata[31:16]} 0x2 = apb_prdata[31:0]= {rxfifo_wdata[7:0], rxfifo_wdata[15:8], rxfifo_wdata[23:16], rxfifo_wdata[31:24]} 0x3 = apb_prdata[31:0]= {rxfifo_wdata[23:16], rxfifo_wdata[31:24], rxfifo_wdata[7:0], rxfifo_wdata[15:8]} 12 2 RSRE Receive Service Request Enable 0: RxFIFO DMA service request is disabled 1: RxFIFO DMA service request is enabled 11 1 TSRE Transmit Service Request Enable 0: TxFIFO DMA service request is disabled 1: TxFIFO DMA service request is enabled 10 1 RFT RXFIFO Trigger Threshold This field sets the threshold level at which RXFIFO asserts interrupt. The level should be set to the preferred threshold value minus 1. 5 5 TFT TXFIFO Trigger Threshold This field sets the threshold level at which TXFIFO asserts interrupt. The level should be set to the preferred threshold value minus 1. 0 5 INTE INTE Interrupt Enable Register 0x08 0x20 read-write 0x00000000 RSVD 6 26 TIM Transmit FIFO Underrun Interrupt Mask 0 : TUR events generate an SPI interrupt 1 : TUR events do NOT generate an SPI interrupt 5 1 RIM Receive FIFO Overrun Interrupt Mask 0: ROR events generate an SPI interrupt 1: ROR events do NOT generate an SPI interrupt 4 1 TIE Transmit FIFO Interrupt Enable 0: TxFIFO threshold-level-reached interrupt is disabled 1: TxFIFO threshold-level-reached interrupt is enabled 3 1 RIE Receive FIFO Interrupt Enable 0: RxFIFO threshold-level-reached interrupt is disabled 1: RxFIFO threshold-level-reached interrupt is enabled 2 1 TINTE Receiver Time-out Interrupt Enable 0: Receiver time-out interrupt is disabled 1: Receiver time-out interrupt is enabled 1 1 RSVD2 0 1 TO TO SPI Time Out Register 0x0c 0x20 read-write 0x00000000 RSVD 24 8 TIMEOUT Timeout Value TIMEOUT value is the value (0 to 2^24-1) that defines the time-out interval. The time-out interval is given by the equation shown in the TIMEOUT Interval Equation. 0 24 DATA DATA SPI DATA Register 0x10 0x20 read-write 0x00000000 DATA DATA This field is used for data to be written to the TXFIFO read from the RXFIFO. 0 32 STATUS STATUS Status Register 0x14 0x20 read-write 0x00000000 RSVD 24 8 OSS Odd Sample Status 0: RxFIFO entry has two samples 1: RxFIFO entry has one sample Note that this bit needs to be looked at only when FIFO Packing is enabled (FPCKE field in FIFO Control Register is set). Otherwise, this bit is zero. When SPI controller is in Packed mode and the CPU is used instead of DMA to read the RxFIFO, the CPU should make sure that [Receive FIFO Not Empty] = 1 AND this field = 0 before it attempts to read the RxFIFO. 23 1 TX_OSS TX FIFO Odd Sample Status When SPI controller is in packed mode, the number of samples in the TX FIFO is: ([Transmit FIFO Level]*2 + this field), when [Transmit FIFO Not Full] = 1 32, when [Transmit FIFO Not Full] = 0. The TX FIFO cannot accept new data when [Transmit FIFO Not Full] = 1 and [Transmit FIFO Level] = 15 and this field = 1. (The TX FIFO has 31 samples). 0: TxFIFO entry has an even number of samples 1: TxFIFO entry has an odd number of samples Note that this bit needs to be read only when FIFO Packing is enabled ([FIFO Packing Enable] in the FIFO Control Register is set). Otherwise, this bit is zero. 22 1 RSVD2 21 1 ROR Receive FIFO Overrun 0: RXFIFO has not experienced an overrun 1: Attempted data write to full RXFIFO, causes an interrupt request 20 1 RSVD3 19 1 RFL Receive FIFO Level This field is the number of entries minus one in RXFIFO. When the value 0xF is read, the RXFIFO is either empty or full, and software should read the [Receive FIFO Not Empty] field. 15 4 RNE Receive FIFO Not Empty 0: RXFIFO is empty 1: RXFIFO is not empty 14 1 RFS Receive FIFO Service Request 0: RXFIFO level is at or below RFT threshold (RFT) or SPI controller is disabled 1: RXFIFO level exceeds RFT threshold (RFT), causes an interrupt request 13 1 TUR Transmit FIFO Underrun 0: The TXFIFO has not experienced an underrun 1: A read from the TXFIFO was attempted when the TXFIFO was empty, causes an interrupt if it is enabled ([Transmit FIFO Underrun Interrupt Mask] in the INT EN Register is 0) 12 1 RSVD4 11 1 TFL Transmit FIFO Level This field is the number of entries in TXFIFO.When the value 0x0 is read, the TXFIFO is either empty or full, and software should read the [Transmit FIFO Not Full] field. 7 4 TNF Transmit FIFO Not Full 0: TXFIFO is full 1: TXFIFO is not full 6 1 TFS Transmit FIFO Service Request 0: TX FIFO level exceeds the TFT threshold (TFT + 1) or SPI controller is disabled 1: TXFIFO level is at or below TFT threshold (TFT + 1), causes an interrupt request 5 1 RSVD5 4 1 TINT Receiver Time-out Interrupt 0: No receiver time-out is pending 1: Receiver time-out pending, causes an interrupt request 3 1 RSVD6 2 1 CSS Clock Synchronization Status 0: SPI controller is ready for slave clock operations 1: SPI controller is currently busy synchronizing slave mode signals 1 1 BSY SPI controller Busy 0: SPI controller is idle or disabled 1: SPI controller is currently transmitting or receiving framed data 0 1 RSVD3 RSVD3 0x18 0x20 read-write 0x0 RWOT_CTRL RWOT_CTRL RWOT Control Register 0x24 0x20 read-write 0x00000000 RSVD 5 27 MASK_RWOT_LAST_SAMPLE Mask last_sample_flag in RWOT Mode 1: Mask 0: Unmask 4 1 CLR_RWOT_CYCLE Clear Internal rwot_counter This field clears the rwot_counter to 0. This field is self cleared after SSE = 1. 1: Clear rwot_counter 3 1 SET_RWOT_CYCLE Set RWOT Cycle This field is used to set the value of the RWOT_CCM register to the internal rwot_counter. This field is self-cleared after SSE = 1. 1: Set rwot_counter 2 1 CYCLE_RWOT_EN Enable RWOT Cycle Counter Mode 1: Enable 1 1 RWOT Receive Without Transmit 0: Transmit/receive mode 1: Receive without transmit mode 0 1 RWOT_CCM RWOT_CCM RWOT Counter Cycles Match Register 0x28 0x20 read-write 0x00000000 RWOTCCM It's just total SPI_CLK Cycles. The value of this register defines the total number of SPI_CLK cycles when SPI controller works in master and RWOT mode. When the rwot_counter matches this value, SPI controller returns to IDLE state and does not output SPI_CLK anymore. 0 32 RWOT_CVWRN RWOT_CVWRN RWOT Counter Value Write for Red Request Register 0x2c 0x20 read-write 0x00000000 RWOTCVWR RWOTCVWR This register prevents the risk of instability on rwot_counter value reading, it's only valid after SPI controller has been enabled Write 0 = No effect Write 1 = Capture value of rwot_counter Read: Returns the captured value of rwot_counter 0 32 RSVD2 RSVD2 0x30 0x20 read-write 0x0 CLK_CTRL CLK_CTRL CLK Control Register 0x3c 0x20 read-write 0x00000000 RSVD 10 22 SPI_DI_SEL Select spi_di source. 0: from port SPI_DI. 1: from port SPI_DIO. 9 1 CLK_EN enable clk for internal logic 8 1 CLK_SEL 0: select clk_div as clk for SPI controller 1: select clk_sys as clk for SPI controller 7 1 CLK_DIV div ratio from clk_sys 0 7 RSVD1 RSVD1 0x40 0x20 read-write 0x0 TRIWIRE_CTRL TRIWIRE_CTRL Three Wire Mode Control Register 0x54 0x20 read-write 0x00000000 RSVD 3 29 WORK_WIDTH_DYN_CHANGE WORK_WIDTH_DYN_CHNAGE 1: SW can dynamicly change TOP_CTRL[9:5] without disabling TOP_CTRL[0] and re-enabling TOP_CTRL[0] 2 1 TXD_OEN TXD_OEN control when TRI-WIRE mode 1: SPI_DIO is input 0: SPI_DIO is output 1 1 SPI_TRI_WIRE_EN SPI_THREE_WIRE_MODE_EN 0: normal mode 1: enable TRI-WIRE mode 0 1 SPI2 SPI 0x50096000 0x0 0x1000 registers TOP_CTRL TOP_CTRL Top Control Register 0x00 0x20 read-write 0x00000000 RSVD 19 13 TTELP SPI_DO Three-state Enable On Last Phase (can be set only when TI-SSP) 0: SPI_DO is three-stated 1/2 clock cycle after the beginning of the LSB 1: SPI_DO output signal is three-stated on the clock edge that ends the LSB 18 1 TTE SPI_DO Three-State Enable 0: SPI_DO output signal is not three-stated 1: SPI_DO is three-stated when not transmitting data 17 1 RSVD2 16 1 IFS Invert Frame Signal 0: SPI_CS polarity is as defined in protocol 1: SPI_CS will be inverted from normal-SPI_CS 15 1 HOLD_FRAME_LOW Hold Frame Low Control 0:After this field is set to 1 and the SPI controller is operating in master mode,the output frame signal SPI_CS will be determined by control FSM. 1:After this field is set to 1 and the SPI controller is operating in master mode, the output frame signal SPI_CS will hold low. 14 1 TRAIL Trailing Byte 0: Trailing bytes are handled by CPU 1: Trailing bytes are handled by DMA bursts 13 1 RSVD3 12 1 SPH Motorola SPI SPI_CLK phase setting 0: SPI_CLK is inactive until one cycle after the start of a frame and active until 1/2 cycle before the end of a frame 1: SPI_CLK is inactive until 1/2 cycle after the start of a frame and active until one cycle before the end of a frame 11 1 SPO Motorola SPI SPI_CLK Polarity Setting 0: The inactive or idle state of SPI_CLK is low 1: The inactive or idle state of SPI_CLK is high 10 1 DSS SPI controller Work data size, register bits value 0~31 indicated data size 1~32 bits, usually use data size 8bits, 16bits, 24bits, 32bits 5 5 SFRMDIR SPI_CS Direction 0: Master mode, SPI controller drives SPI_CS 1: Slave mode, SPI controller receives SPI_CS 4 1 SCLKDIR SPI_CLK Direction 0: Master mode, SPI controller drives SPI_CLK 1: Slave mode, SPI controller receives SPI_CLK 3 1 FRF Frame Format 0x0: Motorola* Serial Peripheral Interface (SPI) 0x1: Texas Instruments* Synchronous Serial Protocol (SSP) 0x2: National Semiconductor Microwire* 0x3: RSVD 1 2 SSE SPI controller Enable 0: SPI controller is disabled 1: SPI controller is enabled 0 1 FIFO_CTRL FIFO_CTRL FIFO Control Register 0x04 0x20 read-write 0x00000000 RSVD 18 14 RXFIFO_AUTO_FULL_CTRL Rx FIFO Auto Full Control: After this field is set to 1 and the SPI controller is operating in master mode, the controller FSM returns to IDLE state and stops the SPI_CLK. When Rx FIFO is full, the controller FSM continues transferring data after the RxFIFO is not full. This field is used to avoid an RxFIFO overrun issue. 1: Enable Rx FIFO auto full control 17 1 FPCKE FIFO Packing Enable 0: FIFO packing mode disabled 1: FIFO packing mode enabled 16 1 TXFIFO_WR_ENDIAN apb_pwdata Write to TxFIFO Endian 0x0: txfifo_wdata[31:0] = apb_pwdata[31:0] 0x1: fifo_wdata[31:0] = {apb_pwdata[15:0], apb_pwdata[31:16]} 0x2: txfifo_wdata[31:0] = {apb_pwdata[7:0], apb_pwdata[15:8], apb_pwdata[23:16], apb_pwdata[31:24]} 0x3: txfifo_wdata[31:0] = {apb_pwdata[23:16], apb_pwdata[31:24], apb_pwdata[7:0], apb_pwdata[15:8]} 14 2 RXFIFO_RD_ENDIAN apb_prdata Read from Rx FIFO Endian 0x0 = apb_prdata[31:0] = rxfifo_wdata[31:0] 0x1 = apb_prdata[31:0] = {rxfifo_wdata[15:0], rxfifo_wdata[31:16]} 0x2 = apb_prdata[31:0]= {rxfifo_wdata[7:0], rxfifo_wdata[15:8], rxfifo_wdata[23:16], rxfifo_wdata[31:24]} 0x3 = apb_prdata[31:0]= {rxfifo_wdata[23:16], rxfifo_wdata[31:24], rxfifo_wdata[7:0], rxfifo_wdata[15:8]} 12 2 RSRE Receive Service Request Enable 0: RxFIFO DMA service request is disabled 1: RxFIFO DMA service request is enabled 11 1 TSRE Transmit Service Request Enable 0: TxFIFO DMA service request is disabled 1: TxFIFO DMA service request is enabled 10 1 RFT RXFIFO Trigger Threshold This field sets the threshold level at which RXFIFO asserts interrupt. The level should be set to the preferred threshold value minus 1. 5 5 TFT TXFIFO Trigger Threshold This field sets the threshold level at which TXFIFO asserts interrupt. The level should be set to the preferred threshold value minus 1. 0 5 INTE INTE Interrupt Enable Register 0x08 0x20 read-write 0x00000000 RSVD 6 26 TIM Transmit FIFO Underrun Interrupt Mask 0 : TUR events generate an SPI interrupt 1 : TUR events do NOT generate an SPI interrupt 5 1 RIM Receive FIFO Overrun Interrupt Mask 0: ROR events generate an SPI interrupt 1: ROR events do NOT generate an SPI interrupt 4 1 TIE Transmit FIFO Interrupt Enable 0: TxFIFO threshold-level-reached interrupt is disabled 1: TxFIFO threshold-level-reached interrupt is enabled 3 1 RIE Receive FIFO Interrupt Enable 0: RxFIFO threshold-level-reached interrupt is disabled 1: RxFIFO threshold-level-reached interrupt is enabled 2 1 TINTE Receiver Time-out Interrupt Enable 0: Receiver time-out interrupt is disabled 1: Receiver time-out interrupt is enabled 1 1 RSVD2 0 1 TO TO SPI Time Out Register 0x0c 0x20 read-write 0x00000000 RSVD 24 8 TIMEOUT Timeout Value TIMEOUT value is the value (0 to 2^24-1) that defines the time-out interval. The time-out interval is given by the equation shown in the TIMEOUT Interval Equation. 0 24 DATA DATA SPI DATA Register 0x10 0x20 read-write 0x00000000 DATA DATA This field is used for data to be written to the TXFIFO read from the RXFIFO. 0 32 STATUS STATUS Status Register 0x14 0x20 read-write 0x00000000 RSVD 24 8 OSS Odd Sample Status 0: RxFIFO entry has two samples 1: RxFIFO entry has one sample Note that this bit needs to be looked at only when FIFO Packing is enabled (FPCKE field in FIFO Control Register is set). Otherwise, this bit is zero. When SPI controller is in Packed mode and the CPU is used instead of DMA to read the RxFIFO, the CPU should make sure that [Receive FIFO Not Empty] = 1 AND this field = 0 before it attempts to read the RxFIFO. 23 1 TX_OSS TX FIFO Odd Sample Status When SPI controller is in packed mode, the number of samples in the TX FIFO is: ([Transmit FIFO Level]*2 + this field), when [Transmit FIFO Not Full] = 1 32, when [Transmit FIFO Not Full] = 0. The TX FIFO cannot accept new data when [Transmit FIFO Not Full] = 1 and [Transmit FIFO Level] = 15 and this field = 1. (The TX FIFO has 31 samples). 0: TxFIFO entry has an even number of samples 1: TxFIFO entry has an odd number of samples Note that this bit needs to be read only when FIFO Packing is enabled ([FIFO Packing Enable] in the FIFO Control Register is set). Otherwise, this bit is zero. 22 1 RSVD2 21 1 ROR Receive FIFO Overrun 0: RXFIFO has not experienced an overrun 1: Attempted data write to full RXFIFO, causes an interrupt request 20 1 RSVD3 19 1 RFL Receive FIFO Level This field is the number of entries minus one in RXFIFO. When the value 0xF is read, the RXFIFO is either empty or full, and software should read the [Receive FIFO Not Empty] field. 15 4 RNE Receive FIFO Not Empty 0: RXFIFO is empty 1: RXFIFO is not empty 14 1 RFS Receive FIFO Service Request 0: RXFIFO level is at or below RFT threshold (RFT) or SPI controller is disabled 1: RXFIFO level exceeds RFT threshold (RFT), causes an interrupt request 13 1 TUR Transmit FIFO Underrun 0: The TXFIFO has not experienced an underrun 1: A read from the TXFIFO was attempted when the TXFIFO was empty, causes an interrupt if it is enabled ([Transmit FIFO Underrun Interrupt Mask] in the INT EN Register is 0) 12 1 RSVD4 11 1 TFL Transmit FIFO Level This field is the number of entries in TXFIFO.When the value 0x0 is read, the TXFIFO is either empty or full, and software should read the [Transmit FIFO Not Full] field. 7 4 TNF Transmit FIFO Not Full 0: TXFIFO is full 1: TXFIFO is not full 6 1 TFS Transmit FIFO Service Request 0: TX FIFO level exceeds the TFT threshold (TFT + 1) or SPI controller is disabled 1: TXFIFO level is at or below TFT threshold (TFT + 1), causes an interrupt request 5 1 RSVD5 4 1 TINT Receiver Time-out Interrupt 0: No receiver time-out is pending 1: Receiver time-out pending, causes an interrupt request 3 1 RSVD6 2 1 CSS Clock Synchronization Status 0: SPI controller is ready for slave clock operations 1: SPI controller is currently busy synchronizing slave mode signals 1 1 BSY SPI controller Busy 0: SPI controller is idle or disabled 1: SPI controller is currently transmitting or receiving framed data 0 1 RSVD3 RSVD3 0x18 0x20 read-write 0x0 RWOT_CTRL RWOT_CTRL RWOT Control Register 0x24 0x20 read-write 0x00000000 RSVD 5 27 MASK_RWOT_LAST_SAMPLE Mask last_sample_flag in RWOT Mode 1: Mask 0: Unmask 4 1 CLR_RWOT_CYCLE Clear Internal rwot_counter This field clears the rwot_counter to 0. This field is self cleared after SSE = 1. 1: Clear rwot_counter 3 1 SET_RWOT_CYCLE Set RWOT Cycle This field is used to set the value of the RWOT_CCM register to the internal rwot_counter. This field is self-cleared after SSE = 1. 1: Set rwot_counter 2 1 CYCLE_RWOT_EN Enable RWOT Cycle Counter Mode 1: Enable 1 1 RWOT Receive Without Transmit 0: Transmit/receive mode 1: Receive without transmit mode 0 1 RWOT_CCM RWOT_CCM RWOT Counter Cycles Match Register 0x28 0x20 read-write 0x00000000 RWOTCCM It's just total SPI_CLK Cycles. The value of this register defines the total number of SPI_CLK cycles when SPI controller works in master and RWOT mode. When the rwot_counter matches this value, SPI controller returns to IDLE state and does not output SPI_CLK anymore. 0 32 RWOT_CVWRN RWOT_CVWRN RWOT Counter Value Write for Red Request Register 0x2c 0x20 read-write 0x00000000 RWOTCVWR RWOTCVWR This register prevents the risk of instability on rwot_counter value reading, it's only valid after SPI controller has been enabled Write 0 = No effect Write 1 = Capture value of rwot_counter Read: Returns the captured value of rwot_counter 0 32 RSVD2 RSVD2 0x30 0x20 read-write 0x0 CLK_CTRL CLK_CTRL CLK Control Register 0x3c 0x20 read-write 0x00000000 RSVD 10 22 SPI_DI_SEL Select spi_di source. 0: from port SPI_DI. 1: from port SPI_DIO. 9 1 CLK_EN enable clk for internal logic 8 1 CLK_SEL 0: select clk_div as clk for SPI controller 1: select clk_sys as clk for SPI controller 7 1 CLK_DIV div ratio from clk_sys 0 7 RSVD1 RSVD1 0x40 0x20 read-write 0x0 TRIWIRE_CTRL TRIWIRE_CTRL Three Wire Mode Control Register 0x54 0x20 read-write 0x00000000 RSVD 3 29 WORK_WIDTH_DYN_CHANGE WORK_WIDTH_DYN_CHNAGE 1: SW can dynamicly change TOP_CTRL[9:5] without disabling TOP_CTRL[0] and re-enabling TOP_CTRL[0] 2 1 TXD_OEN TXD_OEN control when TRI-WIRE mode 1: SPI_DIO is input 0: SPI_DIO is output 1 1 SPI_TRI_WIRE_EN SPI_THREE_WIRE_MODE_EN 0: normal mode 1: enable TRI-WIRE mode 0 1 PDM1 PDM 0x5009a000 0x0 0x1000 registers CFG0 CFG0 0x00 0x20 read-write 0x0 RSVD 10 22 SWAP_EN 1: Swap right channel and left channel pdm data; 0: Not swap right channel and left channel pdm data 9 1 STEREO_EN 1:Enable double channels pdm data sampling; 0: Disable double channels pdm data sampling 8 1 RIGHT_EN 1: Enable right channel pdm data sampling; 0: Disable right channel pdm data sampling 7 1 LEFT_EN 1: Enable left channel pdm data sampling; 0: Disable left channel pdm data sampling 6 1 CLK_DIV Clock frequency division ratio of 3.072MHz or 9.6MHz according to register clk_sel 2 4 CLK_SEL 1:Clk select dll 3.072MHz; 0: Clk selct xtal 9.6MHz 1 1 PDMCOREEN 1:Enable pdm module; 0: Disable pdm module 0 1 CFG1 CFG1 0x04 0x20 read-write 0x0 RSVD 11 21 SAMPLE_DLY_R The number of delay dff before the right data stream in processing 8 3 SAMPLE_DLY_L The number of delay dff before the left data stream in processing 5 3 RSVD2 0 5 SINC_CFG SINC_CFG 0x08 0x20 read-write 0x0 RSVD 9 23 SINC_ORDER_SEL 1:select four differentiators in sinc filter; 0:select three differentiators in sinc filter 8 1 SINC_RATE dowmsampling rate of sinc filter 0 8 RSVD3 RSVD3 0xC 0x20 read-write 0x0 HPF_CFG HPF_CFG 0x14 0x20 read-write 0x0 RSVD 6 26 HPF_RST 1:high-pass filter normal operation ; 0:reset high-pass filter 5 1 HPF_BYPASS 1:bypass-high pass filter ; 0: enable high-pass filter 4 1 HPF_COEFF coefficient of high-pass filter 0 4 PGA_CFG PGA_CFG 0x18 0x20 read-write 0x0 RSVD 14 18 PGA_GAIN_R right channel gain control , the range is -15dB~45dB. Resolution is 0.5dB/LSB 7 7 PGA_GAIN_L left channel gain control , the range is -15dB~45dB. Resolution is 0.5dB/LSB 0 7 RSVD2 RSVD2 0x1C 0x20 read-write 0x0 LPF_CFG6 LPF_CFG6 0x34 0x20 read-write 0x0 RSVD 14 18 LPF_BYPASS 1:bypass low-pass filter ; 0: enable low-pass filter 13 1 LPF_DS 1:downsampling rate of low pass filter is two;0:No downsampling of low pass filter 12 1 RSVD2 0 12 FIFO_CFG FIFO_CFG 0x38 0x20 read-write 0x0 RSVD 9 23 LR_CHG 1:exchange storage location of left and right channel; 0: don't exchange storage location of left and right channel 8 1 RX_DMA_MSK_L 1:disable left channel dma request; 0: enable left channel dma request 7 1 RX_DMA_MSK_R 1:disable right channel dma request; 0: enable right channel dma request 6 1 PDM_SHIFT the number of data left shift for higher data accuracy 3 3 BYTE_TRUNC 1: 16bits output ; 0: 24bits output ;2: 8bits output ; 3: 32bits output 1 2 BYTE_CON 1: combine left channel and right channel; 0: not combine left channel and right channel 0 1 RSVD1 RSVD1 0x3C 0x20 read-write 0x0 FIFO_ST FIFO_ST 0x44 0x20 read-write 0x0 RSVD 8 24 FULL_L 1 indicates left channel fifo is full 7 1 EMPTY_L 1 indicates left channel fifo is empty 6 1 ALMOST_FULL_L 1 indicates left channel fifo is less than two full 5 1 ALMOST_EMPTY_L 1 indicates left channel fifo is less than two datas left 4 1 FULL_R 1 indicates right channel fifo is full 3 1 EMPTY_R 1 indicates right channel fifo is empty 2 1 ALMOST_FULL_R 1 indicates right channel fifo is less than two full 1 1 ALMOST_EMPTY_R 1 indicates right channel fifo is less than two datas left 0 1 INT_ST INT_ST 0x48 0x20 read-write 0x0 RSVD 2 30 OVERFLOW_L 1 indicates left channel fifo has already overflowed and as irq at same time 1 1 OVERFLOW_R 1 indicates right channel fifo has already overflowed and as irq at same time 0 1 INT_MSK INT_MSK 0x4c 0x20 read-write 0x0 RSVD 2 30 INT_MASK_L 1:disable left channel irq to system; 0: enable left channel irq to system 1 1 INT_MASK_R 1:disable right channel irq to system; 0: enable right channel irq to system 0 1 INT_CLR INT_CLR 0x50 0x20 read-write 0x0 RSVD 2 30 INT_CLR_L clear left channel irq 1 1 INT_CLR_R clear right channel irq 0 1 I2C1 I2C 0x5009c000 0x0 0x1000 registers CR CR Control register 0x00 0x20 read-write 0x00000000 UR Unit Reset. Software need first assert to reset then deassert to release. 0 = No reset. 1 = Reset I2C module. 31 1 RSTREQ I2C will do bus reset upon this bit set. Will be cleared by HW automatically after RSTCYC cycles of SCL generated. 1 = request for i2c bus reset 0 = bus reset finished 30 1 BRGRST Reset bus related state machine and signals. Will be cleared by HW automatically 1 = request for reset 0 = reset finished 29 1 RSVD 15 14 DNF Digital noise filter These bits are used to configure the digital noise filter on SDA and SCL input. The digital filter will filter spikes with a length of up to DNF*Tfclk. 0: Digital filter disabled 1: Digital filter enabled and filtering capability up to 1 Tfclk ... 7: digital filter enabled and filtering capability up to 7 Tfclk Digital filter is added to analog filter. Digital filter will introduce delay on SCL and SDA processing, which is essential in hs-mode. 12 3 SLVEN Slave mode Enable for SCL. 0 = Disable slave mode. Will not monitor slave address on I2C bus. 1 = Enable slave mode. Will monitor slave address on I2C bus. 11 1 RSVD2 10 1 SCLPP Push-pull mode Enable for SCL. 0 = open drain output for SCL. 1 = Push-pull output for SCL 9 1 MSDE Master Stop Detected Enable: 0 = Master Stop Detect (MSD) status is not enabled. 1 = Master Stop Detect (MSD) status is enabled. 8 1 RSVD3 7 1 LASTSTOP Generate STOP for last DMA transfer 6 1 LASTNACK Generate NACK for last DMA Read transfer 5 1 DMAEN DMA Enable for both TX and RX 0 = DMA mode is NOT enabled 1 = DMA mode enabled 4 1 SCLE SCL Enable: 0 = Disables the I2C from driving the SCL line. 1 = Enables the I2C clock output for master-mode operation. 3 1 IUE I2C Unit Enable: 0 = Disables the unit and does not master any transactions or respond to any slave transactions. 1 = Enables the I2C (defaults to slave-receive mode). Software must guarantee the I2C bus is idle before setting this bit. 2 1 MODE Bus Mode (Master operation): 2'b00: standard-mode 2'b01: fast-mode and fast-mode plus 2'b10: HS-mode (standard mode when not doing a high speed transfer) 2'b11: HS-mode (fast mode when not doing a high speed transfer) Bus Mode (Slave operation): 2'b0x: HS-mode is disabled. I2C unit uses Standard/Fast mode timing on the SDA pin. 2'b1x: HS-mode is enabled. I2C unit uses HS-mode timing on the SDA pin when a master code is received. 0 2 TCR TCR Transfer Control register 0x04 0x20 read-write 0x00000000 RSVD 8 24 ABORTDMA Abort DMA operation. Will be cleared by HW automatically 7 1 RXREQ Request DMA RX. Will be cleared by HW automatically 6 1 TXREQ Request DMA TX. Will be cleared by HW automatically 5 1 MA Master Abort: Used by the I2C in master mode to generate a Stop without transmitting another data byte: 0 = The I2C transmits Stop on if TCR[STOP] is set. 1 = The I2C sends Stop without data transmission. When in master-transmit mode, after transmitting a data byte, the TCR[TB] bit is cleared. When no more data bytes need to be sent, setting master abort bit sends the Stop. The TCR[TB] bit must remain clear. In master-receive mode, when a NAK is sent without a Stop (TCR[STOP] bit was not set) and CPU does not send a repeated Start, setting this bit sends the Stop. Once again, the TCR[TB] bit must remain clear. Master Abort can be done immediately after the address phase (Master Transmit mode only). 4 1 NACK The positive/negative acknowledge control bit, defines the type of acknowledge pulse sent by the I2C when in master receive mode: 0 = Send a positive acknowledge (ACK) pulse after receiving a data byte. 1 = Send a negative acknowledge (NACK) pulse after receiving a data byte. The I2C automatically sends an ACK pulse when responding to its slave address or when responding in slave-receive mode, regardless of the NACK control-bit setting. 3 1 STOP Stop: Used to initiate a Stop condition after transferring the next data byte on the I2C bus when in master mode. In master-receive mode, the NACK control bit must be set in conjunction with the STOP bit. 0 = Do not send a Stop. 1 = Send a Stop. 2 1 START Start: Used to initiate a Start condition to the I2C unit when in master mode. 0 = Do not send a Start pulse. 1 = Send a Start pulse. 1 1 TB Transfer Byte: Used to send or receive a byte on the I2C bus: 0 = Cleared by I2C when the byte is sent/received. 1 = Send/receive a byte. CPU can monitor this bit to determine when the byte transfer has completed. In master or slave mode, after each byte transfer including acknowledge pulse, the I2C holds the SCL line low (inserting wait states) until TB is set. 0 1 IER IER Interrupt Enable register 0x08 0x20 read-write 0x00000000 RSVD 16 16 UFIE FIFO Underflow Interrupt Enable 0 = FIFO Underflow interrupt is not enabled 1 = FIFO Underflow interrupt is enabled 15 1 OFIE FIFO Overflow Interrupt Enable 0 = FIFO Overflow interrupt is not enabled 1 = FIFO Overflow interrupt is enabled 14 1 DMADONEIE DMA Transaction Done Interrupt Enable 0 = DMA Transaction done interrupt is not enabled. 1 = DMA Transaction done interrupt is enabled. 13 1 MSDIE Master Stop Detected Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C unit to interrupt upon detecting a Master Stop sent by the I2C unit. 12 1 RSVD2 11 1 BEDIE Bus Error Detected Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C to interrupt for the following I2C bus errors: As a master transmitter, no ACK was detected after a byte was sent. As a slave receiver, the I2C generated a NACK pulse. Software is responsible for guaranteeing that misplaced Start and Stop conditions do not occur. 10 1 SADIE Slave Address Detected Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C to interrupt upon detecting a slave address match or a general call address. 9 1 RSVD3 8 1 RFIE DBR Receive Full Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C to interrupt when the DBR has received a data byte from the I2C bus. 7 1 TEIE DBR Transmit Empty Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C to interrupt after transmitting a byte onto the I2C bus. 6 1 ALDIE Arbitration Loss Detected Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C to interrupt upon losing arbitration while in master mode. 5 1 SSDIE Slave Stop Detected Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C to interrupt when it detects a Stop condition while in slave mode. 4 1 RSVD4 0 4 SR SR Status register 0x0c 0x20 read-write 0x00000000 RSVD 16 16 UF FIFO Underflow Flag. Asserted when FIFO is empty and a POP request generated without a PUSH. Cleared if write 1 15 1 OF FIFO Overflow Flag. Asserted when FIFO is full and a PUSH request generated without a POP. Cleared if write 1 14 1 DMADONE DMA Transaction Done. Asserted when both APB and I2C bus have finished transfer. Cleared if write 1 13 1 MSD Master Stop Detected: 0 = No Master Stop Detected. 1 = This bit is set by the I2C unit when all of the following are true: This bit is enabled (CR[MSDE] = 1); I2C unit is configured as a master; I2C transmits a STOP signal 12 1 EBB Early Bus Busy 0 = I2C bus is idle or the I2C is using the bus (that is, unit busy). 1 = Set when the unit detects that the SCL or SDA line is low without a START condition. Bit will remain set until the I2C unit detects the bus is idle by detecting a STOP condition. Bit will also be set whenever the IBB bit is set. 11 1 BED Bus Error Detected: 0 = No error detected. 1 = The I2C sets this bit when it detects one of the following error conditions: As a master transmitter, no ACK was detected on the interface after a byte was sent. As a slave receiver, the I2C generates a NACK pulse. When an error occurs, I2C bus transactions continue. Software must guarantee that misplaced Start and Stop conditions do not occur. Cleared if write 1 10 1 SAD Slave Address Detected: 0 = No slave address was detected. 1 = The I2C detected a seven-bit address that matches the general call address or SAR. An interrupt is signalled when enabled in the CR. Cleared if write 1 9 1 RSVD2 8 1 RF DBR Receive Full: 0 = The DBR has not received a new data byte or the I2C is idle. 1 = The DBR register received a new data byte from the I2C bus. An interrupt is signalled when enabled in the CR. Cleared if write 1 7 1 TE DBR Transmit Empty: 0 = The data byte is still being transmitted. 1 = The I2C has finished transmitting a data byte on the I2C bus. An interrupt is signalled when enabled in the CR. Cleared if write 1 6 1 ALD Arbitration Loss Detected: Used during multi-master operation: 0 = Cleared when arbitration is won or never took place. 1 = Set when the I2C loses arbitration. Cleared if write 1 5 1 SSD Slave Stop Detected: 0 = No Stop detected. 1 = Set when the I2C detects a Stop while in slave-receive or slave-transmit mode. Cleared if write 1 4 1 IBB I2C Bus Busy: 0 = I2C bus is idle or the I2C is using the bus (that is, unit busy). 1 = Set when the I2C bus is busy but local I2C is not involved in the transaction. 3 1 UB Unit Busy: 0 = I2C not busy. 1 = Set when local I2C is busy. This is defined as the time between the first Start and Stop. 2 1 NACK ACK/NACK Status: 0 = The I2C received or sent an ACK on the bus. 1 = The I2C received or sent a NACK.on the bus. This bit is used in slave-transmit mode to determine when the byte transferred is the last one. This bit is updated after each byte and ACK/NACK information is received. 1 1 RWM Read/write Mode: 0 = The I2C is in master-transmit or slave-receive mode. 1 = The I2C is in master-receive or slave-transmit mode. This is the R/nW bit of the slave address. It is cleared automatically by hardware after a Stop state. 0 1 DBR DBR Data Buffer register 0x10 0x20 read-write 0x00000000 RSVD 8 24 DATA use the I2C Data Buffer register to transmit and receive data from the I2C bus. The DBR is accessed by software on one Side and by the I2C Shift register on the other. The DBR receives data coming into the I2C unit after a full byte is received and acknowledged. CPU writes data going out of the I2C to the DBR and sends it to the serial bus. When the I2C is in transmit mode (master or slave), CPU writes data to the DBR over the internal bus. CPU write data to the DBR when a master transaction is initiated or when the DBR transmit-empty interrupt is signalled. Data moves from the DBR to the Shift register when the transfer byte bit is set. The DBR transmit-empty interrupt is signalled (if enabled) when a byte is transferred on the I2C bus and the acknowledge cycle is complete. If the DBR is not written, and a Stop condition is not in place before the I2C bus is ready to transfer the next byte packet, the I2C unit inserts wait states until CPU writes the DBR and sets the transfer byte bit. When the I2C is in receive mode (master or slave), CPU reads DBR data over the internal bus. CPU reads data from the DBR when the DBR receive-full interrupt is signalled. The data moves from the Shift register to the DBR when the acknowledge cycle is complete. The I2C inserts wait states until the DBR is read. After the software reads the DBR, CR[NACK] are written by the software, allowing the next byte transfer to proceed to the I2C bus. In DMA mode, DBR is automatically filled from FIFO in master transmit mode, or fetched and stored in FIFO in master receive mode until DMA done or aborted. 0 8 SAR SAR Slave Address Register 0x14 0x20 read-write 0x00000047 RSVD 7 25 ADDR The seven-bit address to which the I2C responds when in slave-receive mode 0 7 LCR LCR Load Count Register 0x18 0x20 read-write 0x081C72ED HLVH Decrementer Load value for High Speed Mode SCL (master mode) for high phase. Thigh=Tfclk*(HLVH+4+DNF) 27 5 HLVL Decrementer Load value for High Speed Mode SCL (master mode) for low phase. Tlow=Tfclk*(HLVL+3+DNF). Data rate is generated as 1/(Thigh+Tlow), or Ffclk/(HLVH+HLVL+7+2*DNF). 3.2Mbps data rate is generated by default if fclk is 48MHz. HLVL also controls setup time and hold time for START and STOP condition in High Speed Mode(master mode). Thdsta=Tsusta=Tsusto=Tfclk*(HLVL+1) 18 9 FLV Decrementer Load value for Fast Mode (or Fast Mode Plus) SCL (master mode) for both high and low phase. Data rate is generated as Ffclk/(FLV+max(FLV,CNT*2+6)+7+DNF) approximately. 400kbps data rate is generated by default if fclk is 48MHz. FLV also controls setup time and hold time for START and STOP condition in Fast Mode(master mode). Thdsta=Tsusta=Tsusto=Tfclk*FLV 9 9 SLV Decrementer Load value for Standard Mode SCL (master mode) for both high and low phase. Data rate is generated as Ffclk/(SLV+max(SLV,CNT*2+6)+7+DNF) approximately. 100kbps data rate is generated by default if fclk is 48MHz. SLV also controls setup time and hold time for START and STOP condition in Standard Mode(master mode). Thdsta=Tsusta=Tsusto=Tfclk*SLV 0 9 WCR WCR Wait Count Register 0x1c 0x20 read-write 0x0000000A RSVD 8 24 CNT Controls the counter values defining the setup and hold times in standard and fast mode Tvddat=Thddat=Tfclk*(CNT+2) Tsudat=max(Tlow-Thddat,Thddat) Lower counter values may violate setup and hold times. 0 8 RCCR RCCR Bus Reset Cycle Counter Register 0x20 0x20 read-write 0x00000009 RSVD 4 28 RSTCYC The cycles of SCL during bus reset 0 4 BMR BMR Bus Monitor Register 0x24 0x20 read-write 0x00000003 RSVD 2 30 SCL value of the SCL pin. Software can check bus level when the I2C bus is hung and the I2C unit must be reset. 1 1 SDA value of the SDA pin. 0 1 DNR DNR DMA number register 0x28 0x20 read-write 0x00000000 RSVD 9 23 NDT Write as number of data to transfer in byte. Read as left data number to transfer 0 9 RSVD1 RSVD1 0x2C 0x20 read-write 0x0 FIFO FIFO FIFO Register 0x30 0x20 read-write 0x00000000 RSVD 8 24 DATA Write to push send data into FIFO. Read to pop received data from FIFO 0 8 I2C2 I2C 0x5009d000 0x0 0x1000 registers CR CR Control register 0x00 0x20 read-write 0x00000000 UR Unit Reset. Software need first assert to reset then deassert to release. 0 = No reset. 1 = Reset I2C module. 31 1 RSTREQ I2C will do bus reset upon this bit set. Will be cleared by HW automatically after RSTCYC cycles of SCL generated. 1 = request for i2c bus reset 0 = bus reset finished 30 1 BRGRST Reset bus related state machine and signals. Will be cleared by HW automatically 1 = request for reset 0 = reset finished 29 1 RSVD 15 14 DNF Digital noise filter These bits are used to configure the digital noise filter on SDA and SCL input. The digital filter will filter spikes with a length of up to DNF*Tfclk. 0: Digital filter disabled 1: Digital filter enabled and filtering capability up to 1 Tfclk ... 7: digital filter enabled and filtering capability up to 7 Tfclk Digital filter is added to analog filter. Digital filter will introduce delay on SCL and SDA processing, which is essential in hs-mode. 12 3 SLVEN Slave mode Enable for SCL. 0 = Disable slave mode. Will not monitor slave address on I2C bus. 1 = Enable slave mode. Will monitor slave address on I2C bus. 11 1 RSVD2 10 1 SCLPP Push-pull mode Enable for SCL. 0 = open drain output for SCL. 1 = Push-pull output for SCL 9 1 MSDE Master Stop Detected Enable: 0 = Master Stop Detect (MSD) status is not enabled. 1 = Master Stop Detect (MSD) status is enabled. 8 1 RSVD3 7 1 LASTSTOP Generate STOP for last DMA transfer 6 1 LASTNACK Generate NACK for last DMA Read transfer 5 1 DMAEN DMA Enable for both TX and RX 0 = DMA mode is NOT enabled 1 = DMA mode enabled 4 1 SCLE SCL Enable: 0 = Disables the I2C from driving the SCL line. 1 = Enables the I2C clock output for master-mode operation. 3 1 IUE I2C Unit Enable: 0 = Disables the unit and does not master any transactions or respond to any slave transactions. 1 = Enables the I2C (defaults to slave-receive mode). Software must guarantee the I2C bus is idle before setting this bit. 2 1 MODE Bus Mode (Master operation): 2'b00: standard-mode 2'b01: fast-mode and fast-mode plus 2'b10: HS-mode (standard mode when not doing a high speed transfer) 2'b11: HS-mode (fast mode when not doing a high speed transfer) Bus Mode (Slave operation): 2'b0x: HS-mode is disabled. I2C unit uses Standard/Fast mode timing on the SDA pin. 2'b1x: HS-mode is enabled. I2C unit uses HS-mode timing on the SDA pin when a master code is received. 0 2 TCR TCR Transfer Control register 0x04 0x20 read-write 0x00000000 RSVD 8 24 ABORTDMA Abort DMA operation. Will be cleared by HW automatically 7 1 RXREQ Request DMA RX. Will be cleared by HW automatically 6 1 TXREQ Request DMA TX. Will be cleared by HW automatically 5 1 MA Master Abort: Used by the I2C in master mode to generate a Stop without transmitting another data byte: 0 = The I2C transmits Stop on if TCR[STOP] is set. 1 = The I2C sends Stop without data transmission. When in master-transmit mode, after transmitting a data byte, the TCR[TB] bit is cleared. When no more data bytes need to be sent, setting master abort bit sends the Stop. The TCR[TB] bit must remain clear. In master-receive mode, when a NAK is sent without a Stop (TCR[STOP] bit was not set) and CPU does not send a repeated Start, setting this bit sends the Stop. Once again, the TCR[TB] bit must remain clear. Master Abort can be done immediately after the address phase (Master Transmit mode only). 4 1 NACK The positive/negative acknowledge control bit, defines the type of acknowledge pulse sent by the I2C when in master receive mode: 0 = Send a positive acknowledge (ACK) pulse after receiving a data byte. 1 = Send a negative acknowledge (NACK) pulse after receiving a data byte. The I2C automatically sends an ACK pulse when responding to its slave address or when responding in slave-receive mode, regardless of the NACK control-bit setting. 3 1 STOP Stop: Used to initiate a Stop condition after transferring the next data byte on the I2C bus when in master mode. In master-receive mode, the NACK control bit must be set in conjunction with the STOP bit. 0 = Do not send a Stop. 1 = Send a Stop. 2 1 START Start: Used to initiate a Start condition to the I2C unit when in master mode. 0 = Do not send a Start pulse. 1 = Send a Start pulse. 1 1 TB Transfer Byte: Used to send or receive a byte on the I2C bus: 0 = Cleared by I2C when the byte is sent/received. 1 = Send/receive a byte. CPU can monitor this bit to determine when the byte transfer has completed. In master or slave mode, after each byte transfer including acknowledge pulse, the I2C holds the SCL line low (inserting wait states) until TB is set. 0 1 IER IER Interrupt Enable register 0x08 0x20 read-write 0x00000000 RSVD 16 16 UFIE FIFO Underflow Interrupt Enable 0 = FIFO Underflow interrupt is not enabled 1 = FIFO Underflow interrupt is enabled 15 1 OFIE FIFO Overflow Interrupt Enable 0 = FIFO Overflow interrupt is not enabled 1 = FIFO Overflow interrupt is enabled 14 1 DMADONEIE DMA Transaction Done Interrupt Enable 0 = DMA Transaction done interrupt is not enabled. 1 = DMA Transaction done interrupt is enabled. 13 1 MSDIE Master Stop Detected Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C unit to interrupt upon detecting a Master Stop sent by the I2C unit. 12 1 RSVD2 11 1 BEDIE Bus Error Detected Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C to interrupt for the following I2C bus errors: As a master transmitter, no ACK was detected after a byte was sent. As a slave receiver, the I2C generated a NACK pulse. Software is responsible for guaranteeing that misplaced Start and Stop conditions do not occur. 10 1 SADIE Slave Address Detected Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C to interrupt upon detecting a slave address match or a general call address. 9 1 RSVD3 8 1 RFIE DBR Receive Full Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C to interrupt when the DBR has received a data byte from the I2C bus. 7 1 TEIE DBR Transmit Empty Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C to interrupt after transmitting a byte onto the I2C bus. 6 1 ALDIE Arbitration Loss Detected Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C to interrupt upon losing arbitration while in master mode. 5 1 SSDIE Slave Stop Detected Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C to interrupt when it detects a Stop condition while in slave mode. 4 1 RSVD4 0 4 SR SR Status register 0x0c 0x20 read-write 0x00000000 RSVD 16 16 UF FIFO Underflow Flag. Asserted when FIFO is empty and a POP request generated without a PUSH. Cleared if write 1 15 1 OF FIFO Overflow Flag. Asserted when FIFO is full and a PUSH request generated without a POP. Cleared if write 1 14 1 DMADONE DMA Transaction Done. Asserted when both APB and I2C bus have finished transfer. Cleared if write 1 13 1 MSD Master Stop Detected: 0 = No Master Stop Detected. 1 = This bit is set by the I2C unit when all of the following are true: This bit is enabled (CR[MSDE] = 1); I2C unit is configured as a master; I2C transmits a STOP signal 12 1 EBB Early Bus Busy 0 = I2C bus is idle or the I2C is using the bus (that is, unit busy). 1 = Set when the unit detects that the SCL or SDA line is low without a START condition. Bit will remain set until the I2C unit detects the bus is idle by detecting a STOP condition. Bit will also be set whenever the IBB bit is set. 11 1 BED Bus Error Detected: 0 = No error detected. 1 = The I2C sets this bit when it detects one of the following error conditions: As a master transmitter, no ACK was detected on the interface after a byte was sent. As a slave receiver, the I2C generates a NACK pulse. When an error occurs, I2C bus transactions continue. Software must guarantee that misplaced Start and Stop conditions do not occur. Cleared if write 1 10 1 SAD Slave Address Detected: 0 = No slave address was detected. 1 = The I2C detected a seven-bit address that matches the general call address or SAR. An interrupt is signalled when enabled in the CR. Cleared if write 1 9 1 RSVD2 8 1 RF DBR Receive Full: 0 = The DBR has not received a new data byte or the I2C is idle. 1 = The DBR register received a new data byte from the I2C bus. An interrupt is signalled when enabled in the CR. Cleared if write 1 7 1 TE DBR Transmit Empty: 0 = The data byte is still being transmitted. 1 = The I2C has finished transmitting a data byte on the I2C bus. An interrupt is signalled when enabled in the CR. Cleared if write 1 6 1 ALD Arbitration Loss Detected: Used during multi-master operation: 0 = Cleared when arbitration is won or never took place. 1 = Set when the I2C loses arbitration. Cleared if write 1 5 1 SSD Slave Stop Detected: 0 = No Stop detected. 1 = Set when the I2C detects a Stop while in slave-receive or slave-transmit mode. Cleared if write 1 4 1 IBB I2C Bus Busy: 0 = I2C bus is idle or the I2C is using the bus (that is, unit busy). 1 = Set when the I2C bus is busy but local I2C is not involved in the transaction. 3 1 UB Unit Busy: 0 = I2C not busy. 1 = Set when local I2C is busy. This is defined as the time between the first Start and Stop. 2 1 NACK ACK/NACK Status: 0 = The I2C received or sent an ACK on the bus. 1 = The I2C received or sent a NACK.on the bus. This bit is used in slave-transmit mode to determine when the byte transferred is the last one. This bit is updated after each byte and ACK/NACK information is received. 1 1 RWM Read/write Mode: 0 = The I2C is in master-transmit or slave-receive mode. 1 = The I2C is in master-receive or slave-transmit mode. This is the R/nW bit of the slave address. It is cleared automatically by hardware after a Stop state. 0 1 DBR DBR Data Buffer register 0x10 0x20 read-write 0x00000000 RSVD 8 24 DATA use the I2C Data Buffer register to transmit and receive data from the I2C bus. The DBR is accessed by software on one Side and by the I2C Shift register on the other. The DBR receives data coming into the I2C unit after a full byte is received and acknowledged. CPU writes data going out of the I2C to the DBR and sends it to the serial bus. When the I2C is in transmit mode (master or slave), CPU writes data to the DBR over the internal bus. CPU write data to the DBR when a master transaction is initiated or when the DBR transmit-empty interrupt is signalled. Data moves from the DBR to the Shift register when the transfer byte bit is set. The DBR transmit-empty interrupt is signalled (if enabled) when a byte is transferred on the I2C bus and the acknowledge cycle is complete. If the DBR is not written, and a Stop condition is not in place before the I2C bus is ready to transfer the next byte packet, the I2C unit inserts wait states until CPU writes the DBR and sets the transfer byte bit. When the I2C is in receive mode (master or slave), CPU reads DBR data over the internal bus. CPU reads data from the DBR when the DBR receive-full interrupt is signalled. The data moves from the Shift register to the DBR when the acknowledge cycle is complete. The I2C inserts wait states until the DBR is read. After the software reads the DBR, CR[NACK] are written by the software, allowing the next byte transfer to proceed to the I2C bus. In DMA mode, DBR is automatically filled from FIFO in master transmit mode, or fetched and stored in FIFO in master receive mode until DMA done or aborted. 0 8 SAR SAR Slave Address Register 0x14 0x20 read-write 0x00000047 RSVD 7 25 ADDR The seven-bit address to which the I2C responds when in slave-receive mode 0 7 LCR LCR Load Count Register 0x18 0x20 read-write 0x081C72ED HLVH Decrementer Load value for High Speed Mode SCL (master mode) for high phase. Thigh=Tfclk*(HLVH+4+DNF) 27 5 HLVL Decrementer Load value for High Speed Mode SCL (master mode) for low phase. Tlow=Tfclk*(HLVL+3+DNF). Data rate is generated as 1/(Thigh+Tlow), or Ffclk/(HLVH+HLVL+7+2*DNF). 3.2Mbps data rate is generated by default if fclk is 48MHz. HLVL also controls setup time and hold time for START and STOP condition in High Speed Mode(master mode). Thdsta=Tsusta=Tsusto=Tfclk*(HLVL+1) 18 9 FLV Decrementer Load value for Fast Mode (or Fast Mode Plus) SCL (master mode) for both high and low phase. Data rate is generated as Ffclk/(FLV+max(FLV,CNT*2+6)+7+DNF) approximately. 400kbps data rate is generated by default if fclk is 48MHz. FLV also controls setup time and hold time for START and STOP condition in Fast Mode(master mode). Thdsta=Tsusta=Tsusto=Tfclk*FLV 9 9 SLV Decrementer Load value for Standard Mode SCL (master mode) for both high and low phase. Data rate is generated as Ffclk/(SLV+max(SLV,CNT*2+6)+7+DNF) approximately. 100kbps data rate is generated by default if fclk is 48MHz. SLV also controls setup time and hold time for START and STOP condition in Standard Mode(master mode). Thdsta=Tsusta=Tsusto=Tfclk*SLV 0 9 WCR WCR Wait Count Register 0x1c 0x20 read-write 0x0000000A RSVD 8 24 CNT Controls the counter values defining the setup and hold times in standard and fast mode Tvddat=Thddat=Tfclk*(CNT+2) Tsudat=max(Tlow-Thddat,Thddat) Lower counter values may violate setup and hold times. 0 8 RCCR RCCR Bus Reset Cycle Counter Register 0x20 0x20 read-write 0x00000009 RSVD 4 28 RSTCYC The cycles of SCL during bus reset 0 4 BMR BMR Bus Monitor Register 0x24 0x20 read-write 0x00000003 RSVD 2 30 SCL value of the SCL pin. Software can check bus level when the I2C bus is hung and the I2C unit must be reset. 1 1 SDA value of the SDA pin. 0 1 DNR DNR DMA number register 0x28 0x20 read-write 0x00000000 RSVD 9 23 NDT Write as number of data to transfer in byte. Read as left data number to transfer 0 9 RSVD1 RSVD1 0x2C 0x20 read-write 0x0 FIFO FIFO FIFO Register 0x30 0x20 read-write 0x00000000 RSVD 8 24 DATA Write to push send data into FIFO. Read to pop received data from FIFO 0 8 I2C3 I2C 0x5009e000 0x0 0x1000 registers CR CR Control register 0x00 0x20 read-write 0x00000000 UR Unit Reset. Software need first assert to reset then deassert to release. 0 = No reset. 1 = Reset I2C module. 31 1 RSTREQ I2C will do bus reset upon this bit set. Will be cleared by HW automatically after RSTCYC cycles of SCL generated. 1 = request for i2c bus reset 0 = bus reset finished 30 1 BRGRST Reset bus related state machine and signals. Will be cleared by HW automatically 1 = request for reset 0 = reset finished 29 1 RSVD 15 14 DNF Digital noise filter These bits are used to configure the digital noise filter on SDA and SCL input. The digital filter will filter spikes with a length of up to DNF*Tfclk. 0: Digital filter disabled 1: Digital filter enabled and filtering capability up to 1 Tfclk ... 7: digital filter enabled and filtering capability up to 7 Tfclk Digital filter is added to analog filter. Digital filter will introduce delay on SCL and SDA processing, which is essential in hs-mode. 12 3 SLVEN Slave mode Enable for SCL. 0 = Disable slave mode. Will not monitor slave address on I2C bus. 1 = Enable slave mode. Will monitor slave address on I2C bus. 11 1 RSVD2 10 1 SCLPP Push-pull mode Enable for SCL. 0 = open drain output for SCL. 1 = Push-pull output for SCL 9 1 MSDE Master Stop Detected Enable: 0 = Master Stop Detect (MSD) status is not enabled. 1 = Master Stop Detect (MSD) status is enabled. 8 1 RSVD3 7 1 LASTSTOP Generate STOP for last DMA transfer 6 1 LASTNACK Generate NACK for last DMA Read transfer 5 1 DMAEN DMA Enable for both TX and RX 0 = DMA mode is NOT enabled 1 = DMA mode enabled 4 1 SCLE SCL Enable: 0 = Disables the I2C from driving the SCL line. 1 = Enables the I2C clock output for master-mode operation. 3 1 IUE I2C Unit Enable: 0 = Disables the unit and does not master any transactions or respond to any slave transactions. 1 = Enables the I2C (defaults to slave-receive mode). Software must guarantee the I2C bus is idle before setting this bit. 2 1 MODE Bus Mode (Master operation): 2'b00: standard-mode 2'b01: fast-mode and fast-mode plus 2'b10: HS-mode (standard mode when not doing a high speed transfer) 2'b11: HS-mode (fast mode when not doing a high speed transfer) Bus Mode (Slave operation): 2'b0x: HS-mode is disabled. I2C unit uses Standard/Fast mode timing on the SDA pin. 2'b1x: HS-mode is enabled. I2C unit uses HS-mode timing on the SDA pin when a master code is received. 0 2 TCR TCR Transfer Control register 0x04 0x20 read-write 0x00000000 RSVD 8 24 ABORTDMA Abort DMA operation. Will be cleared by HW automatically 7 1 RXREQ Request DMA RX. Will be cleared by HW automatically 6 1 TXREQ Request DMA TX. Will be cleared by HW automatically 5 1 MA Master Abort: Used by the I2C in master mode to generate a Stop without transmitting another data byte: 0 = The I2C transmits Stop on if TCR[STOP] is set. 1 = The I2C sends Stop without data transmission. When in master-transmit mode, after transmitting a data byte, the TCR[TB] bit is cleared. When no more data bytes need to be sent, setting master abort bit sends the Stop. The TCR[TB] bit must remain clear. In master-receive mode, when a NAK is sent without a Stop (TCR[STOP] bit was not set) and CPU does not send a repeated Start, setting this bit sends the Stop. Once again, the TCR[TB] bit must remain clear. Master Abort can be done immediately after the address phase (Master Transmit mode only). 4 1 NACK The positive/negative acknowledge control bit, defines the type of acknowledge pulse sent by the I2C when in master receive mode: 0 = Send a positive acknowledge (ACK) pulse after receiving a data byte. 1 = Send a negative acknowledge (NACK) pulse after receiving a data byte. The I2C automatically sends an ACK pulse when responding to its slave address or when responding in slave-receive mode, regardless of the NACK control-bit setting. 3 1 STOP Stop: Used to initiate a Stop condition after transferring the next data byte on the I2C bus when in master mode. In master-receive mode, the NACK control bit must be set in conjunction with the STOP bit. 0 = Do not send a Stop. 1 = Send a Stop. 2 1 START Start: Used to initiate a Start condition to the I2C unit when in master mode. 0 = Do not send a Start pulse. 1 = Send a Start pulse. 1 1 TB Transfer Byte: Used to send or receive a byte on the I2C bus: 0 = Cleared by I2C when the byte is sent/received. 1 = Send/receive a byte. CPU can monitor this bit to determine when the byte transfer has completed. In master or slave mode, after each byte transfer including acknowledge pulse, the I2C holds the SCL line low (inserting wait states) until TB is set. 0 1 IER IER Interrupt Enable register 0x08 0x20 read-write 0x00000000 RSVD 16 16 UFIE FIFO Underflow Interrupt Enable 0 = FIFO Underflow interrupt is not enabled 1 = FIFO Underflow interrupt is enabled 15 1 OFIE FIFO Overflow Interrupt Enable 0 = FIFO Overflow interrupt is not enabled 1 = FIFO Overflow interrupt is enabled 14 1 DMADONEIE DMA Transaction Done Interrupt Enable 0 = DMA Transaction done interrupt is not enabled. 1 = DMA Transaction done interrupt is enabled. 13 1 MSDIE Master Stop Detected Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C unit to interrupt upon detecting a Master Stop sent by the I2C unit. 12 1 RSVD2 11 1 BEDIE Bus Error Detected Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C to interrupt for the following I2C bus errors: As a master transmitter, no ACK was detected after a byte was sent. As a slave receiver, the I2C generated a NACK pulse. Software is responsible for guaranteeing that misplaced Start and Stop conditions do not occur. 10 1 SADIE Slave Address Detected Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C to interrupt upon detecting a slave address match or a general call address. 9 1 RSVD3 8 1 RFIE DBR Receive Full Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C to interrupt when the DBR has received a data byte from the I2C bus. 7 1 TEIE DBR Transmit Empty Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C to interrupt after transmitting a byte onto the I2C bus. 6 1 ALDIE Arbitration Loss Detected Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C to interrupt upon losing arbitration while in master mode. 5 1 SSDIE Slave Stop Detected Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C to interrupt when it detects a Stop condition while in slave mode. 4 1 RSVD4 0 4 SR SR Status register 0x0c 0x20 read-write 0x00000000 RSVD 16 16 UF FIFO Underflow Flag. Asserted when FIFO is empty and a POP request generated without a PUSH. Cleared if write 1 15 1 OF FIFO Overflow Flag. Asserted when FIFO is full and a PUSH request generated without a POP. Cleared if write 1 14 1 DMADONE DMA Transaction Done. Asserted when both APB and I2C bus have finished transfer. Cleared if write 1 13 1 MSD Master Stop Detected: 0 = No Master Stop Detected. 1 = This bit is set by the I2C unit when all of the following are true: This bit is enabled (CR[MSDE] = 1); I2C unit is configured as a master; I2C transmits a STOP signal 12 1 EBB Early Bus Busy 0 = I2C bus is idle or the I2C is using the bus (that is, unit busy). 1 = Set when the unit detects that the SCL or SDA line is low without a START condition. Bit will remain set until the I2C unit detects the bus is idle by detecting a STOP condition. Bit will also be set whenever the IBB bit is set. 11 1 BED Bus Error Detected: 0 = No error detected. 1 = The I2C sets this bit when it detects one of the following error conditions: As a master transmitter, no ACK was detected on the interface after a byte was sent. As a slave receiver, the I2C generates a NACK pulse. When an error occurs, I2C bus transactions continue. Software must guarantee that misplaced Start and Stop conditions do not occur. Cleared if write 1 10 1 SAD Slave Address Detected: 0 = No slave address was detected. 1 = The I2C detected a seven-bit address that matches the general call address or SAR. An interrupt is signalled when enabled in the CR. Cleared if write 1 9 1 RSVD2 8 1 RF DBR Receive Full: 0 = The DBR has not received a new data byte or the I2C is idle. 1 = The DBR register received a new data byte from the I2C bus. An interrupt is signalled when enabled in the CR. Cleared if write 1 7 1 TE DBR Transmit Empty: 0 = The data byte is still being transmitted. 1 = The I2C has finished transmitting a data byte on the I2C bus. An interrupt is signalled when enabled in the CR. Cleared if write 1 6 1 ALD Arbitration Loss Detected: Used during multi-master operation: 0 = Cleared when arbitration is won or never took place. 1 = Set when the I2C loses arbitration. Cleared if write 1 5 1 SSD Slave Stop Detected: 0 = No Stop detected. 1 = Set when the I2C detects a Stop while in slave-receive or slave-transmit mode. Cleared if write 1 4 1 IBB I2C Bus Busy: 0 = I2C bus is idle or the I2C is using the bus (that is, unit busy). 1 = Set when the I2C bus is busy but local I2C is not involved in the transaction. 3 1 UB Unit Busy: 0 = I2C not busy. 1 = Set when local I2C is busy. This is defined as the time between the first Start and Stop. 2 1 NACK ACK/NACK Status: 0 = The I2C received or sent an ACK on the bus. 1 = The I2C received or sent a NACK.on the bus. This bit is used in slave-transmit mode to determine when the byte transferred is the last one. This bit is updated after each byte and ACK/NACK information is received. 1 1 RWM Read/write Mode: 0 = The I2C is in master-transmit or slave-receive mode. 1 = The I2C is in master-receive or slave-transmit mode. This is the R/nW bit of the slave address. It is cleared automatically by hardware after a Stop state. 0 1 DBR DBR Data Buffer register 0x10 0x20 read-write 0x00000000 RSVD 8 24 DATA use the I2C Data Buffer register to transmit and receive data from the I2C bus. The DBR is accessed by software on one Side and by the I2C Shift register on the other. The DBR receives data coming into the I2C unit after a full byte is received and acknowledged. CPU writes data going out of the I2C to the DBR and sends it to the serial bus. When the I2C is in transmit mode (master or slave), CPU writes data to the DBR over the internal bus. CPU write data to the DBR when a master transaction is initiated or when the DBR transmit-empty interrupt is signalled. Data moves from the DBR to the Shift register when the transfer byte bit is set. The DBR transmit-empty interrupt is signalled (if enabled) when a byte is transferred on the I2C bus and the acknowledge cycle is complete. If the DBR is not written, and a Stop condition is not in place before the I2C bus is ready to transfer the next byte packet, the I2C unit inserts wait states until CPU writes the DBR and sets the transfer byte bit. When the I2C is in receive mode (master or slave), CPU reads DBR data over the internal bus. CPU reads data from the DBR when the DBR receive-full interrupt is signalled. The data moves from the Shift register to the DBR when the acknowledge cycle is complete. The I2C inserts wait states until the DBR is read. After the software reads the DBR, CR[NACK] are written by the software, allowing the next byte transfer to proceed to the I2C bus. In DMA mode, DBR is automatically filled from FIFO in master transmit mode, or fetched and stored in FIFO in master receive mode until DMA done or aborted. 0 8 SAR SAR Slave Address Register 0x14 0x20 read-write 0x00000047 RSVD 7 25 ADDR The seven-bit address to which the I2C responds when in slave-receive mode 0 7 LCR LCR Load Count Register 0x18 0x20 read-write 0x081C72ED HLVH Decrementer Load value for High Speed Mode SCL (master mode) for high phase. Thigh=Tfclk*(HLVH+4+DNF) 27 5 HLVL Decrementer Load value for High Speed Mode SCL (master mode) for low phase. Tlow=Tfclk*(HLVL+3+DNF). Data rate is generated as 1/(Thigh+Tlow), or Ffclk/(HLVH+HLVL+7+2*DNF). 3.2Mbps data rate is generated by default if fclk is 48MHz. HLVL also controls setup time and hold time for START and STOP condition in High Speed Mode(master mode). Thdsta=Tsusta=Tsusto=Tfclk*(HLVL+1) 18 9 FLV Decrementer Load value for Fast Mode (or Fast Mode Plus) SCL (master mode) for both high and low phase. Data rate is generated as Ffclk/(FLV+max(FLV,CNT*2+6)+7+DNF) approximately. 400kbps data rate is generated by default if fclk is 48MHz. FLV also controls setup time and hold time for START and STOP condition in Fast Mode(master mode). Thdsta=Tsusta=Tsusto=Tfclk*FLV 9 9 SLV Decrementer Load value for Standard Mode SCL (master mode) for both high and low phase. Data rate is generated as Ffclk/(SLV+max(SLV,CNT*2+6)+7+DNF) approximately. 100kbps data rate is generated by default if fclk is 48MHz. SLV also controls setup time and hold time for START and STOP condition in Standard Mode(master mode). Thdsta=Tsusta=Tsusto=Tfclk*SLV 0 9 WCR WCR Wait Count Register 0x1c 0x20 read-write 0x0000000A RSVD 8 24 CNT Controls the counter values defining the setup and hold times in standard and fast mode Tvddat=Thddat=Tfclk*(CNT+2) Tsudat=max(Tlow-Thddat,Thddat) Lower counter values may violate setup and hold times. 0 8 RCCR RCCR Bus Reset Cycle Counter Register 0x20 0x20 read-write 0x00000009 RSVD 4 28 RSTCYC The cycles of SCL during bus reset 0 4 BMR BMR Bus Monitor Register 0x24 0x20 read-write 0x00000003 RSVD 2 30 SCL value of the SCL pin. Software can check bus level when the I2C bus is hung and the I2C unit must be reset. 1 1 SDA value of the SDA pin. 0 1 DNR DNR DMA number register 0x28 0x20 read-write 0x00000000 RSVD 9 23 NDT Write as number of data to transfer in byte. Read as left data number to transfer 0 9 RSVD1 RSVD1 0x2C 0x20 read-write 0x0 FIFO FIFO FIFO Register 0x30 0x20 read-write 0x00000000 RSVD 8 24 DATA Write to push send data into FIFO. Read to pop received data from FIFO 0 8 I2C4 I2C 0x5009f000 0x0 0x1000 registers CR CR Control register 0x00 0x20 read-write 0x00000000 UR Unit Reset. Software need first assert to reset then deassert to release. 0 = No reset. 1 = Reset I2C module. 31 1 RSTREQ I2C will do bus reset upon this bit set. Will be cleared by HW automatically after RSTCYC cycles of SCL generated. 1 = request for i2c bus reset 0 = bus reset finished 30 1 BRGRST Reset bus related state machine and signals. Will be cleared by HW automatically 1 = request for reset 0 = reset finished 29 1 RSVD 15 14 DNF Digital noise filter These bits are used to configure the digital noise filter on SDA and SCL input. The digital filter will filter spikes with a length of up to DNF*Tfclk. 0: Digital filter disabled 1: Digital filter enabled and filtering capability up to 1 Tfclk ... 7: digital filter enabled and filtering capability up to 7 Tfclk Digital filter is added to analog filter. Digital filter will introduce delay on SCL and SDA processing, which is essential in hs-mode. 12 3 SLVEN Slave mode Enable for SCL. 0 = Disable slave mode. Will not monitor slave address on I2C bus. 1 = Enable slave mode. Will monitor slave address on I2C bus. 11 1 RSVD2 10 1 SCLPP Push-pull mode Enable for SCL. 0 = open drain output for SCL. 1 = Push-pull output for SCL 9 1 MSDE Master Stop Detected Enable: 0 = Master Stop Detect (MSD) status is not enabled. 1 = Master Stop Detect (MSD) status is enabled. 8 1 RSVD3 7 1 LASTSTOP Generate STOP for last DMA transfer 6 1 LASTNACK Generate NACK for last DMA Read transfer 5 1 DMAEN DMA Enable for both TX and RX 0 = DMA mode is NOT enabled 1 = DMA mode enabled 4 1 SCLE SCL Enable: 0 = Disables the I2C from driving the SCL line. 1 = Enables the I2C clock output for master-mode operation. 3 1 IUE I2C Unit Enable: 0 = Disables the unit and does not master any transactions or respond to any slave transactions. 1 = Enables the I2C (defaults to slave-receive mode). Software must guarantee the I2C bus is idle before setting this bit. 2 1 MODE Bus Mode (Master operation): 2'b00: standard-mode 2'b01: fast-mode and fast-mode plus 2'b10: HS-mode (standard mode when not doing a high speed transfer) 2'b11: HS-mode (fast mode when not doing a high speed transfer) Bus Mode (Slave operation): 2'b0x: HS-mode is disabled. I2C unit uses Standard/Fast mode timing on the SDA pin. 2'b1x: HS-mode is enabled. I2C unit uses HS-mode timing on the SDA pin when a master code is received. 0 2 TCR TCR Transfer Control register 0x04 0x20 read-write 0x00000000 RSVD 8 24 ABORTDMA Abort DMA operation. Will be cleared by HW automatically 7 1 RXREQ Request DMA RX. Will be cleared by HW automatically 6 1 TXREQ Request DMA TX. Will be cleared by HW automatically 5 1 MA Master Abort: Used by the I2C in master mode to generate a Stop without transmitting another data byte: 0 = The I2C transmits Stop on if TCR[STOP] is set. 1 = The I2C sends Stop without data transmission. When in master-transmit mode, after transmitting a data byte, the TCR[TB] bit is cleared. When no more data bytes need to be sent, setting master abort bit sends the Stop. The TCR[TB] bit must remain clear. In master-receive mode, when a NAK is sent without a Stop (TCR[STOP] bit was not set) and CPU does not send a repeated Start, setting this bit sends the Stop. Once again, the TCR[TB] bit must remain clear. Master Abort can be done immediately after the address phase (Master Transmit mode only). 4 1 NACK The positive/negative acknowledge control bit, defines the type of acknowledge pulse sent by the I2C when in master receive mode: 0 = Send a positive acknowledge (ACK) pulse after receiving a data byte. 1 = Send a negative acknowledge (NACK) pulse after receiving a data byte. The I2C automatically sends an ACK pulse when responding to its slave address or when responding in slave-receive mode, regardless of the NACK control-bit setting. 3 1 STOP Stop: Used to initiate a Stop condition after transferring the next data byte on the I2C bus when in master mode. In master-receive mode, the NACK control bit must be set in conjunction with the STOP bit. 0 = Do not send a Stop. 1 = Send a Stop. 2 1 START Start: Used to initiate a Start condition to the I2C unit when in master mode. 0 = Do not send a Start pulse. 1 = Send a Start pulse. 1 1 TB Transfer Byte: Used to send or receive a byte on the I2C bus: 0 = Cleared by I2C when the byte is sent/received. 1 = Send/receive a byte. CPU can monitor this bit to determine when the byte transfer has completed. In master or slave mode, after each byte transfer including acknowledge pulse, the I2C holds the SCL line low (inserting wait states) until TB is set. 0 1 IER IER Interrupt Enable register 0x08 0x20 read-write 0x00000000 RSVD 16 16 UFIE FIFO Underflow Interrupt Enable 0 = FIFO Underflow interrupt is not enabled 1 = FIFO Underflow interrupt is enabled 15 1 OFIE FIFO Overflow Interrupt Enable 0 = FIFO Overflow interrupt is not enabled 1 = FIFO Overflow interrupt is enabled 14 1 DMADONEIE DMA Transaction Done Interrupt Enable 0 = DMA Transaction done interrupt is not enabled. 1 = DMA Transaction done interrupt is enabled. 13 1 MSDIE Master Stop Detected Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C unit to interrupt upon detecting a Master Stop sent by the I2C unit. 12 1 RSVD2 11 1 BEDIE Bus Error Detected Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C to interrupt for the following I2C bus errors: As a master transmitter, no ACK was detected after a byte was sent. As a slave receiver, the I2C generated a NACK pulse. Software is responsible for guaranteeing that misplaced Start and Stop conditions do not occur. 10 1 SADIE Slave Address Detected Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C to interrupt upon detecting a slave address match or a general call address. 9 1 RSVD3 8 1 RFIE DBR Receive Full Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C to interrupt when the DBR has received a data byte from the I2C bus. 7 1 TEIE DBR Transmit Empty Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C to interrupt after transmitting a byte onto the I2C bus. 6 1 ALDIE Arbitration Loss Detected Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C to interrupt upon losing arbitration while in master mode. 5 1 SSDIE Slave Stop Detected Interrupt Enable: 0 = Disable interrupt. 1 = Enables the I2C to interrupt when it detects a Stop condition while in slave mode. 4 1 RSVD4 0 4 SR SR Status register 0x0c 0x20 read-write 0x00000000 RSVD 16 16 UF FIFO Underflow Flag. Asserted when FIFO is empty and a POP request generated without a PUSH. Cleared if write 1 15 1 OF FIFO Overflow Flag. Asserted when FIFO is full and a PUSH request generated without a POP. Cleared if write 1 14 1 DMADONE DMA Transaction Done. Asserted when both APB and I2C bus have finished transfer. Cleared if write 1 13 1 MSD Master Stop Detected: 0 = No Master Stop Detected. 1 = This bit is set by the I2C unit when all of the following are true: This bit is enabled (CR[MSDE] = 1); I2C unit is configured as a master; I2C transmits a STOP signal 12 1 EBB Early Bus Busy 0 = I2C bus is idle or the I2C is using the bus (that is, unit busy). 1 = Set when the unit detects that the SCL or SDA line is low without a START condition. Bit will remain set until the I2C unit detects the bus is idle by detecting a STOP condition. Bit will also be set whenever the IBB bit is set. 11 1 BED Bus Error Detected: 0 = No error detected. 1 = The I2C sets this bit when it detects one of the following error conditions: As a master transmitter, no ACK was detected on the interface after a byte was sent. As a slave receiver, the I2C generates a NACK pulse. When an error occurs, I2C bus transactions continue. Software must guarantee that misplaced Start and Stop conditions do not occur. Cleared if write 1 10 1 SAD Slave Address Detected: 0 = No slave address was detected. 1 = The I2C detected a seven-bit address that matches the general call address or SAR. An interrupt is signalled when enabled in the CR. Cleared if write 1 9 1 RSVD2 8 1 RF DBR Receive Full: 0 = The DBR has not received a new data byte or the I2C is idle. 1 = The DBR register received a new data byte from the I2C bus. An interrupt is signalled when enabled in the CR. Cleared if write 1 7 1 TE DBR Transmit Empty: 0 = The data byte is still being transmitted. 1 = The I2C has finished transmitting a data byte on the I2C bus. An interrupt is signalled when enabled in the CR. Cleared if write 1 6 1 ALD Arbitration Loss Detected: Used during multi-master operation: 0 = Cleared when arbitration is won or never took place. 1 = Set when the I2C loses arbitration. Cleared if write 1 5 1 SSD Slave Stop Detected: 0 = No Stop detected. 1 = Set when the I2C detects a Stop while in slave-receive or slave-transmit mode. Cleared if write 1 4 1 IBB I2C Bus Busy: 0 = I2C bus is idle or the I2C is using the bus (that is, unit busy). 1 = Set when the I2C bus is busy but local I2C is not involved in the transaction. 3 1 UB Unit Busy: 0 = I2C not busy. 1 = Set when local I2C is busy. This is defined as the time between the first Start and Stop. 2 1 NACK ACK/NACK Status: 0 = The I2C received or sent an ACK on the bus. 1 = The I2C received or sent a NACK.on the bus. This bit is used in slave-transmit mode to determine when the byte transferred is the last one. This bit is updated after each byte and ACK/NACK information is received. 1 1 RWM Read/write Mode: 0 = The I2C is in master-transmit or slave-receive mode. 1 = The I2C is in master-receive or slave-transmit mode. This is the R/nW bit of the slave address. It is cleared automatically by hardware after a Stop state. 0 1 DBR DBR Data Buffer register 0x10 0x20 read-write 0x00000000 RSVD 8 24 DATA use the I2C Data Buffer register to transmit and receive data from the I2C bus. The DBR is accessed by software on one Side and by the I2C Shift register on the other. The DBR receives data coming into the I2C unit after a full byte is received and acknowledged. CPU writes data going out of the I2C to the DBR and sends it to the serial bus. When the I2C is in transmit mode (master or slave), CPU writes data to the DBR over the internal bus. CPU write data to the DBR when a master transaction is initiated or when the DBR transmit-empty interrupt is signalled. Data moves from the DBR to the Shift register when the transfer byte bit is set. The DBR transmit-empty interrupt is signalled (if enabled) when a byte is transferred on the I2C bus and the acknowledge cycle is complete. If the DBR is not written, and a Stop condition is not in place before the I2C bus is ready to transfer the next byte packet, the I2C unit inserts wait states until CPU writes the DBR and sets the transfer byte bit. When the I2C is in receive mode (master or slave), CPU reads DBR data over the internal bus. CPU reads data from the DBR when the DBR receive-full interrupt is signalled. The data moves from the Shift register to the DBR when the acknowledge cycle is complete. The I2C inserts wait states until the DBR is read. After the software reads the DBR, CR[NACK] are written by the software, allowing the next byte transfer to proceed to the I2C bus. In DMA mode, DBR is automatically filled from FIFO in master transmit mode, or fetched and stored in FIFO in master receive mode until DMA done or aborted. 0 8 SAR SAR Slave Address Register 0x14 0x20 read-write 0x00000047 RSVD 7 25 ADDR The seven-bit address to which the I2C responds when in slave-receive mode 0 7 LCR LCR Load Count Register 0x18 0x20 read-write 0x081C72ED HLVH Decrementer Load value for High Speed Mode SCL (master mode) for high phase. Thigh=Tfclk*(HLVH+4+DNF) 27 5 HLVL Decrementer Load value for High Speed Mode SCL (master mode) for low phase. Tlow=Tfclk*(HLVL+3+DNF). Data rate is generated as 1/(Thigh+Tlow), or Ffclk/(HLVH+HLVL+7+2*DNF). 3.2Mbps data rate is generated by default if fclk is 48MHz. HLVL also controls setup time and hold time for START and STOP condition in High Speed Mode(master mode). Thdsta=Tsusta=Tsusto=Tfclk*(HLVL+1) 18 9 FLV Decrementer Load value for Fast Mode (or Fast Mode Plus) SCL (master mode) for both high and low phase. Data rate is generated as Ffclk/(FLV+max(FLV,CNT*2+6)+7+DNF) approximately. 400kbps data rate is generated by default if fclk is 48MHz. FLV also controls setup time and hold time for START and STOP condition in Fast Mode(master mode). Thdsta=Tsusta=Tsusto=Tfclk*FLV 9 9 SLV Decrementer Load value for Standard Mode SCL (master mode) for both high and low phase. Data rate is generated as Ffclk/(SLV+max(SLV,CNT*2+6)+7+DNF) approximately. 100kbps data rate is generated by default if fclk is 48MHz. SLV also controls setup time and hold time for START and STOP condition in Standard Mode(master mode). Thdsta=Tsusta=Tsusto=Tfclk*SLV 0 9 WCR WCR Wait Count Register 0x1c 0x20 read-write 0x0000000A RSVD 8 24 CNT Controls the counter values defining the setup and hold times in standard and fast mode Tvddat=Thddat=Tfclk*(CNT+2) Tsudat=max(Tlow-Thddat,Thddat) Lower counter values may violate setup and hold times. 0 8 RCCR RCCR Bus Reset Cycle Counter Register 0x20 0x20 read-write 0x00000009 RSVD 4 28 RSTCYC The cycles of SCL during bus reset 0 4 BMR BMR Bus Monitor Register 0x24 0x20 read-write 0x00000003 RSVD 2 30 SCL value of the SCL pin. Software can check bus level when the I2C bus is hung and the I2C unit must be reset. 1 1 SDA value of the SDA pin. 0 1 DNR DNR DMA number register 0x28 0x20 read-write 0x00000000 RSVD 9 23 NDT Write as number of data to transfer in byte. Read as left data number to transfer 0 9 RSVD1 RSVD1 0x2C 0x20 read-write 0x0 FIFO FIFO FIFO Register 0x30 0x20 read-write 0x00000000 RSVD 8 24 DATA Write to push send data into FIFO. Read to pop received data from FIFO 0 8 HPSYS_GPIO HPSYS_GPIO 0x500a0000 0x0 0x1000 registers DIR0 DIR0 Data Input Register 0x00 0x20 read-write 0x0 IN GPIO[31:0] input value 0 32 DOR0 DOR0 Data Output Register 0x04 0x20 read-write 0x0 OUT GPIO[31:0] output value if output enabled 0 32 DOSR0 DOSR0 Data Output Set Register 0x08 0x20 read-write 0x0 DOS set 1 to pull up output of corresponding GPIO[31:0] 0 32 DOCR0 DOCR0 Data Output Clear Register 0x0c 0x20 read-write 0x0 DOC set 1 to pull down output of corresponding GPIO[31:0] 0 32 DOER0 DOER0 Data Output Enable Register 0x10 0x20 read-write 0x0 DOE GPIO[31:0] output enable 0 32 DOESR0 DOESR0 Data Output Enable Set Register 0x14 0x20 read-write 0x0 DOES set 1 to enable output of corresponding GPIO[31:0] 0 32 DOECR0 DOECR0 Data Output Enable Clear Register 0x18 0x20 read-write 0x0 DOEC set 1 to disable output of corresponding GPIO[31:0] 0 32 IER0 IER0 Interrupt Enable Register 0x1c 0x20 read-write 0x0 IER GPIO[31:0] interrupt enable 0 32 IESR0 IESR0 Interrupt Enable Set Register 0x20 0x20 read-write 0x0 IES set 1 to enable interrupt of corresponding GPIO[31:0] 0 32 IECR0 IECR0 Interrupt Enable Clear Register 0x24 0x20 read-write 0x0 IEC set 1 to disable interrupt of corresponding GPIO[31:0] 0 32 ITR0 ITR0 Interrupt Type Register 0x28 0x20 read-write 0x0 ITR GPIO[31:0] interrupt type 0 32 ITSR0 ITSR0 Interrupt Type Set Register 0x2c 0x20 read-write 0x0 ITS set 1 for edge-sensitive interrupt mode of corresponding GPIO[31:0] 0 32 ITCR0 ITCR0 Interrupt Type Clear Register 0x30 0x20 read-write 0x0 ITC set 1 for level-sensitive interrupt mode of corresponding GPIO[31:0] 0 32 IPHR0 IPHR0 Interrupt Polarity High Register 0x34 0x20 read-write 0x0 IPH rising edge in edge mode, or high level in level mode of corresponding GPIO[31:0] 0 32 IPHSR0 IPHSR0 Interrupt Polarity High Set Register 0x38 0x20 read-write 0x0 IPHS set 1 for rising edge in edge mode, or high level in level mode of corresponding GPIO[31:0] 0 32 IPHCR0 IPHCR0 Interrupt Polarity High Clear Register 0x3c 0x20 read-write 0x0 IPHC set 1 for disable rising edge in edge mode, or high level in level mode of corresponding GPIO[31:0] 0 32 IPLR0 IPLR0 Interrupt Polarity Low Register 0x40 0x20 read-write 0x0 IPL falling edge in edge mode, or low level in level mode of corresponding GPIO[31:0] 0 32 IPLSR0 IPLSR0 Interrupt Polarity Low Set Register 0x44 0x20 read-write 0x0 IPLS set 1 for falling edge in edge mode, or low level in level mode of corresponding GPIO[31:0] 0 32 IPLCR0 IPLCR0 Interrupt Polarity Low Clear Register 0x48 0x20 read-write 0x0 IPLC set 1 for disable falling edge in edge mode, or low level in level mode of corresponding GPIO[31:0] 0 32 ISR0 ISR0 Interrupt Status Register 0x4c 0x20 read-write 0x0 IS Interrupt status. Write 1 will clear interrupt status of corresponding GPIO[31:0] 0 32 RSVD3 RSVD3 0x50 0x20 read-write 0x0 OEMR0 OEMR0 output mode Register 0x60 0x20 read-write 0x0 OEM output mode of corresponding GPIO[31:0] 0 32 OEMSR0 OEMSR0 output mode Set Register 0x64 0x20 read-write 0x0 OEMS output mode Set of corresponding GPIO[31:0] 0 32 OEMCR0 OEMCR0 output mode Clear Register 0x68 0x20 read-write 0x0 OEMC output mode Clear of corresponding GPIO[31:0] 0 32 RSVD2 RSVD2 0x6C 0x20 read-write 0x0 DIR1 DIR1 Data Input Register 0x80 0x20 read-write 0x0 RSVD 13 19 IN GPIO[44:32] input value 0 13 DOR1 DOR1 Data Output Register 0x84 0x20 read-write 0x0 RSVD 13 19 OUT GPIO[44:32] output value if output enabled 0 13 DOSR1 DOSR1 Data Output Set Register 0x88 0x20 read-write 0x0 RSVD 13 19 DOS set 1 to pull up output of corresponding GPIO[44:32] 0 13 DOCR1 DOCR1 Data Output Clear Register 0x8c 0x20 read-write 0x0 RSVD 13 19 DOC set 1 to pull down output of corresponding GPIO[44:32] 0 13 DOER1 DOER1 Data Output Enable Register 0x90 0x20 read-write 0x0 RSVD 13 19 DOE GPIO[44:32] output enable 0 13 DOESR1 DOESR1 Data Output Enable Set Register 0x94 0x20 read-write 0x0 RSVD 13 19 DOES set 1 to enable output of corresponding GPIO[44:32] 0 13 DOECR1 DOECR1 Data Output Enable Clear Register 0x98 0x20 read-write 0x0 RSVD 13 19 DOEC set 1 to disable output of corresponding GPIO[44:32] 0 13 IER1 IER1 Interrupt Enable Register 0x9c 0x20 read-write 0x0 RSVD 13 19 IER GPIO[44:32] interrupt enable 0 13 IESR1 IESR1 Interrupt Enable Set Register 0xa0 0x20 read-write 0x0 RSVD 13 19 IES set 1 to enable interrupt of corresponding GPIO[44:32] 0 13 IECR1 IECR1 Interrupt Enable Clear Register 0xa4 0x20 read-write 0x0 RSVD 13 19 IEC set 1 to disable interrupt of corresponding GPIO[44:32] 0 13 ITR1 ITR1 Interrupt Type Register 0xa8 0x20 read-write 0x0 RSVD 13 19 ITR GPIO[44:32] interrupt type 0 13 ITSR1 ITSR1 Interrupt Type Set Register 0xac 0x20 read-write 0x0 RSVD 13 19 ITS set 1 for edge-sensitive interrupt mode of corresponding GPIO[44:32] 0 13 ITCR1 ITCR1 Interrupt Type Clear Register 0xb0 0x20 read-write 0x0 RSVD 13 19 ITC set 1 for level-sensitive interrupt mode of corresponding GPIO[44:32] 0 13 IPHR1 IPHR1 Interrupt Polarity High Register 0xb4 0x20 read-write 0x0 RSVD 13 19 IPH rising edge in edge mode, or high level in level mode of corresponding GPIO[44:32] 0 13 IPHSR1 IPHSR1 Interrupt Polarity High Set Register 0xb8 0x20 read-write 0x0 RSVD 13 19 IPHS set 1 for rising edge in edge mode, or high level in level mode of corresponding GPIO[44:32] 0 13 IPHCR1 IPHCR1 Interrupt Polarity High Clear Register 0xbc 0x20 read-write 0x0 RSVD 13 19 IPHC set 1 for disable rising edge in edge mode, or high level in level mode of corresponding GPIO[44:32] 0 13 IPLR1 IPLR1 Interrupt Polarity Low Register 0xc0 0x20 read-write 0x0 RSVD 13 19 IPL falling edge in edge mode, or low level in level mode of corresponding GPIO[44:32] 0 13 IPLSR1 IPLSR1 Interrupt Polarity Low Set Register 0xc4 0x20 read-write 0x0 RSVD 13 19 IPLS set 1 for falling edge in edge mode, or low level in level mode of corresponding GPIO[44:32] 0 13 IPLCR1 IPLCR1 Interrupt Polarity Low Clear Register 0xc8 0x20 read-write 0x0 RSVD 13 19 IPLC set 1 for disable falling edge in edge mode, or low level in level mode of corresponding GPIO[44:32] 0 13 ISR1 ISR1 Interrupt Status Register 0xcc 0x20 read-write 0x0 RSVD 13 19 IS Interrupt status. Write 1 will clear interrupt status of corresponding GPIO[44:32] 0 13 RSVD1 RSVD1 0xD0 0x20 read-write 0x0 OEMR1 OEMR1 output mode Register 0xe0 0x20 read-write 0x0 RSVD 13 19 OEM output mode of corresponding GPIO[44:32] 0 13 OEMSR1 OEMSR1 output mode Set Register 0xe4 0x20 read-write 0x0 RSVD 13 19 OEMS output mode Set of corresponding GPIO[44:32] 0 13 OEMCR1 OEMCR1 output mode Clear Register 0xe8 0x20 read-write 0x0 RSVD 13 19 OEMC output mode Clear of corresponding GPIO[44:32] 0 13 GPTIM2 GPTIM 0x500b0000 0x0 0x1000 registers CR1 CR1 TIM control register 1 0x00 0x20 read-write 0x00000000 RSVD 12 20 UIFREMAP UIF status bit remapping 0: No remapping. UIF status bit is not copied to CNT register bit 31 1: Remapping enabled. UIF status bit is copied to CNT register bit 31 11 1 RSVD2 8 3 ARPE Auto-reload preload enable 0: ARR register is not buffered 1: ARR register is buffered 7 1 CMS Center-aligned mode selection 00: Edge-aligned mode. The counter counts up or down depending on the direction bit (DIR). 01: Center-aligned mode 1. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in CCMRx register) are set only when the counter is counting down. 10: Center-aligned mode 2. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in CCMRx register) are set only when the counter is counting up. 11: Center-aligned mode 3. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in CCMRx register) are set both when the counter is counting up or down. 5 2 DIR Direction 0: Counter used as upcounter 1: Counter used as downcounter 4 1 OPM One-pulse mode 0: Counter is not stopped at update event 1: Counter stops counting at the next update event (clearing the bit CEN) 3 1 URS Update request source This bit is set and cleared by software to select the UEV event sources. 0: Any of the following events generate an update interrupt or DMA request if enabled. These events can be: Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller 1: Only counter overflow/underflow generates an update interrupt or DMA request if enabled. 2 1 UDIS Update disable This bit is set and cleared by software to enable/disable UEV event generation. 0: UEV enabled. The Update (UEV) event is generated by one of the following events: Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values. 1: UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller. 1 1 CEN Counter enable 0: Counter disabled 1: Counter enabled Note: External clock, gated mode and encoder mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. CEN is cleared automatically in one-pulse mode, when an update event occurs. 0 1 CR2 CR2 TIM control register 2 0x04 0x20 read-write 0x00000000 RSVD 8 24 TI1S TI1 selection 0: The CH1 pin is connected to TI1 input 1: The CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) 7 1 MMS Master mode selection These bits allow to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: 000: Reset - the UG bit from the EGR register is used as trigger output (TRGO). If the reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on TRGO is delayed compared to the actual reset. 001: Enable - the Counter enable signal is used as trigger output (TRGO). It is useful to start several timers at the same time or to control a window in which a slave timer is enabled. The Counter Enable signal is generated by a logic OR between CEN control bit and the trigger input when configured in gated mode. When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected. 010: Update - The update event is selected as trigger output (TRGO). For instance a master timer can then be used as a prescaler for a slave timer. 011: Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or a compare match occurred. (TRGO) 100: Compare - OC1REF signal is used as trigger output (TRGO) 101: Compare - OC2REF signal is used as trigger output (TRGO) 110: Compare - OC3REF signal is used as trigger output (TRGO) 111: Compare - OC4REF signal is used as trigger output (TRGO) 4 3 CCDS Capture/compare DMA selection 0: CCx DMA request sent when CCx event occurs 1: CCx DMA requests sent when update event occurs 3 1 RSVD2 0 3 SMCR SMCR TIM slave mode control register 0x08 0x20 read-write 0x00000000 RSVD 20 12 SMS Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input. 0000: Slave mode disabled. 0001: Encoder mode 1 - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level. 0010: Encoder mode 2 - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level. 0011: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. 0100: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers. 0101: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled. 0110: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled. 0111: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter. 1000: Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter. 16 4 ETP External trigger polarity 0: ETR is non-inverted, active at high level or rising edge 1: ETR is inverted, active at low level or falling edge 15 1 ECE External clock enable This bit enables External clock mode 2. 0: External clock mode 2 disabled 1: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal. 14 1 ETPS External trigger prescaler External trigger signal ETRP frequency must be at most 1/4 of CK_INT frequency. A prescaler can be enabled to reduce ETRP frequency. It is useful when inputting fast external clocks. 00: Prescaler OFF 01: ETRP frequency divided by 2 10: ETRP frequency divided by 4 11: ETRP frequency divided by 8 12 2 ETF External trigger filter This bit-field then defines the frequency used to sample ETRP signal and the length of the digital filter applied to ETRP. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: 0000: No filter 0001: fSAMPLING=fCLK, N=2 0010: fSAMPLING=fCLK, N=4 0011: fSAMPLING=fCLK, N=8 0100: fSAMPLING=fCLK/2, N=6 0101: fSAMPLING=fCLK/2, N=8 0110: fSAMPLING=fCLK/4, N=6 0111: fSAMPLING=fCLK/4, N=8 1000: fSAMPLING=fCLK/8, N=6 1001: fSAMPLING=fCLK/8, N=8 1010: fSAMPLING=fCLK/16, N=5 1011: fSAMPLING=fCLK/16, N=6 1100: fSAMPLING=fCLK/16, N=8 1101: fSAMPLING=fCLK/32, N=5 1110: fSAMPLING=fCLK/32, N=6 1111: fSAMPLING=fCLK/32, N=8 8 4 MSM Master/Slave mode 0: No action 1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event. 7 1 TS Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. 000: Internal Trigger 0 (ITR0) 001: Internal Trigger 1 (ITR1) 010: Internal Trigger 2 (ITR2) 011: Internal Trigger 3 (ITR3) 100: TI1 Edge Detector (TI1F_ED) 101: Filtered Timer Input 1 (TI1FP1) 110: Filtered Timer Input 2 (TI2FP2) 111: External Trigger input (ETRF) 4 3 RSVD2 0 4 DIER DIER TIM DMA/Interrupt enable register 0x0c 0x20 read-write 0x00000000 RSVD 15 17 TDE Trigger DMA request enable 0: Trigger DMA request disabled. 1: Trigger DMA request enabled. 14 1 RSVD2 13 1 CC4DE Capture/Compare 4 DMA request enable 0: CC4 DMA request disabled. 1: CC4 DMA request enabled 12 1 CC3DE Capture/Compare 3 DMA request enable 0: CC3 DMA request disabled. 1: CC3 DMA request enabled. 11 1 CC2DE Capture/Compare 2 DMA request enable 0: CC2 DMA request disabled. 1: CC2 DMA request enabled. 10 1 CC1DE Capture/Compare 1 DMA request enable 0: CC1 DMA request disabled. 1: CC1 DMA request enabled. 9 1 UDE Update DMA request enable 0: Update DMA request disabled. 1: Update DMA request enabled 8 1 RSVD3 7 1 TIE Trigger interrupt enable 0: Trigger interrupt disabled. 1: Trigger interrupt enabled 6 1 RSVD4 5 1 CC4IE Capture/Compare 4 interrupt enable 0: CC4 interrupt disabled. 1: CC4 interrupt enabled 4 1 CC3IE Capture/Compare 3 interrupt enable 0: CC3 interrupt disabled. 1: CC3 interrupt enabled 3 1 CC2IE Capture/Compare 2 interrupt enable 0: CC2 interrupt disabled. 1: CC2 interrupt enabled. 2 1 CC1IE Capture/Compare 1 interrupt enable 0: CC1 interrupt disabled. 1: CC1 interrupt enabled 1 1 UIE Update interrupt enable 0: Update interrupt disabled. 1: Update interrupt enabled 0 1 SR SR TIM status register 0x10 0x20 read-write 0x00000000 RSVD 13 19 CC4OF Capture/Compare 4 overcapture flag 12 1 CC3OF Capture/Compare 3 overcapture flag 11 1 CC2OF Capture/Compare 2 overcapture flag 10 1 CC1OF Capture/Compare 1 overcapture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing it to '0'. 0: No overcapture has been detected. 1: The counter value has been captured in CCR1 register while CC1IF flag was already set 9 1 RSVD2 7 2 TIF Trigger interrupt flag This flag is set by hardware on trigger event (active edge detected on TRGI input when the slave mode controller is enabled in all modes but gated mode). It is set when the counter starts or stops when gated mode is selected. It is cleared by software. 0: No trigger event occurred. 1: Trigger interrupt pending. 6 1 RSVD3 5 1 CC4IF Capture/Compare 4 interrupt flag 4 1 CC3IF Capture/Compare 3 interrupt flag 3 1 CC2IF Capture/Compare 2 interrupt flag 2 1 CC1IF Capture/Compare 1 interrupt flag If channel CC1 is configured as output: This flag is set by hardware when the counter matches the compare value. It is cleared by software. 0: No match. 1: The content of the counter CNT has matched the content of the CCR1 register. If channel CC1 is configured as input: This bit is set by hardware on a capture. It is cleared by software or by reading the CCR1 register. 0: No input capture occurred. 1: The counter value has been captured in CCR1 register (An edge has been detected on IC1 which matches the selected polarity). 1 1 UIF Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. 0: No update occurred 1: Update interrupt pending. This bit is set by hardware when the registers are updated: At overflow or underflow and if UDIS=0 in the CR1 register. When CNT is reinitialized by software using the UG bit in EGR register, if URS=0 and UDIS=0 in the CR1 register. When CNT is reinitialized by a trigger event, if URS=0 and UDIS=0 in the CR1 register. 0 1 EGR EGR Event generation register 0x14 0x20 read-write 0x00000000 RSVD 7 25 TG Trigger generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 0: No action 1: The TIF flag is set in SR register. Related interrupt or DMA transfer can occur if enabled. 6 1 RSVD2 5 1 CC4G Capture/compare 4 generation 4 1 CC3G Capture/compare 3 generation 3 1 CC2G Capture/compare 2 generation 2 1 CC1G Capture/compare 1 generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 0: No action 1: A capture/compare event is generated on channel 1: If channel CC1 is configured as output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If channel CC1 is configured as input: The current value of the counter is captured in CCR1 register. The CC1IF flag is set, the corresponding interrupt or DMA request is sent if enabled. The CC1OF flag is set if the CC1IF flag was already high. 1 1 UG Update generation This bit can be set by software, it is automatically cleared by hardware. 0: No action 1: Re-initialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected). The counter is cleared if the center-aligned mode is selected or if DIR=0 (upcounting), else it takes the auto-reload value (ARR) if DIR=1 (downcounting). 0 1 CCMR1 CCMR1 TIM capture/compare mode register 1 0x18 0x20 read-write 0x00000000 OC2M Output compare 2 mode 28 4 OC2PE Output compare 2 preload enable 27 1 RSVD 25 2 OC2CE Output compare 2 clear enable 24 1 OC1M Output compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits. 0000: Frozen - The comparison between the output compare register CCR1 and the counter CNT has no effect on the outputs.(this mode is used to generate a timing base). 0001: Set channel 1 to active level on match. OC1REF signal is forced high when the counter CNT matches the capture/compare register 1 (CCR1). 0010: Set channel 1 to inactive level on match. OC1REF signal is forced low when the counter CNT matches the capture/compare register 1 (CCR1). 0011: Toggle - OC1REF toggles when CNT=CCR1. 0100: Force inactive level - OC1REF is forced low. 0101: Force active level - OC1REF is forced high. 0110: PWM mode 1 - In upcounting, channel 1 is active as long as CNT(CCR1 else inactive. In downcounting, channel 1 is inactive (OC1REF='0) as long as CNT>CCR1 else active (OC1REF=1). 0111: PWM mode 2 - In upcounting, channel 1 is inactive as long as CNT(CCR1 else active. In downcounting, channel 1 is active as long as CNT>CCR1 else inactive. 1000: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes inactive again at the next update. In down-counting mode, the channel is inactive until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes inactive again at the next update. 1001: Retriggerable OPM mode 2 - In up-counting mode, the channel is inactive until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 2 and the channels becomes inactive again at the next update. In down-counting mode, the channel is active until a trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes active again at the next update. 1010: Reserved, 1011: Reserved, 1100: Combined PWM mode 1 - OC1REF has the same behavior as in PWM mode 1. OC1REFC is the logical OR between OC1REF and OC2REF. 1101: Combined PWM mode 2 - OC1REF has the same behavior as in PWM mode 2. OC1REFC is the logical AND between OC1REF and OC2REF. 1110: Asymmetric PWM mode 1 - OC1REF has the same behavior as in PWM mode 1. OC1REFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down. 1111: Asymmetric PWM mode 2 - OC1REF has the same behavior as in PWM mode 2. OC1REFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down. 20 4 OC1PE Output compare 1 preload enable 0: Preload register on CCR1 disabled. CCR1 can be written at anytime, the new value is taken in account immediately. 1: Preload register on CCR1 enabled. Read/Write operations access the preload register. CCR1 preload value is loaded in the active register at each update event. 19 1 RSVD2 17 2 OC1CE Output compare 1 clear enable 0: OC1Ref is not affected by the ETRF input 1: OC1Ref is cleared as soon as a High level is detected on ETRF input 16 1 IC2F Input capture 2 filter 12 4 IC2PSC Input capture 2 prescaler 10 2 CC2S Capture/Compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC2 channel is configured as output 01: CC2 channel is configured as input, IC2 is mapped on TI2 10: CC2 channel is configured as input, IC2 is mapped on TI1 11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if an internal trigger input is selected through the TS bit (SMCR register) 8 2 IC1F Input capture 1 filter This bit-field defines the frequency used to sample TI1 input and the length of the digital filter applied to TI1. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: 0000: No filter, sampling is done at fCLK 0001: fSAMPLING=fCLK, N=2 0010: fSAMPLING=fCLK, N=4 0011: fSAMPLING=fCLK, N=8 0100: fSAMPLING=fCLK/2, N=6 0101: fSAMPLING=fCLK/2, N=8 0110: fSAMPLING=fCLK/4, N=6 0111: fSAMPLING=fCLK/4, N=8 1000: fSAMPLING=fCLK/8, N=6 1001: fSAMPLING=fCLK/8, N=8 1010: fSAMPLING=fCLK/16, N=5 1011: fSAMPLING=fCLK/16, N=6 1100: fSAMPLING=fCLK/16, N=8 1101: fSAMPLING=fCLK/32, N=5 1110: fSAMPLING=fCLK/32, N=6 1111: fSAMPLING=fCLK/32, N=8 4 4 IC1PSC Input capture 1 prescaler This bit-field defines the ratio of the prescaler acting on CC1 input (IC1). The prescaler is reset as soon as CC1E=0. 00: no prescaler, capture is done each time an edge is detected on the capture input 01: capture is done once every 2 events 10: capture is done once every 4 events 11: capture is done once every 8 events 2 2 CC1S Capture/Compare 1 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC1 channel is configured as output 01: CC1 channel is configured as input, IC1 is mapped on TI1 10: CC1 channel is configured as input, IC1 is mapped on TI2 11: CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (SMCR register) 0 2 CCMR2 CCMR2 TIM capture/compare mode register 2 0x1c 0x20 read-write 0x00000000 OC4M Output compare 4 mode 28 4 OC4PE Output compare 4 preload enable 27 1 RSVD 25 2 OC4CE Output compare 4 clear enable 24 1 OC3M Output compare 3 mode 20 4 OC3PE Output compare 3 preload enable 19 1 RSVD2 17 2 OC3CE Output compare 3 clear enable 16 1 IC4F Input capture 4 filter 12 4 IC4PSC Input capture 4 prescaler 10 2 CC4S Capture/Compare 4 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC4 channel is configured as output 01: CC4 channel is configured as input, IC4 is mapped on TI4 10: CC4 channel is configured as input, IC4 is mapped on TI3 11: CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (SMCR register) 8 2 IC3F Input capture 3 filter 4 4 IC3PSC Input capture 3 prescaler 2 2 CC3S Capture/Compare 3 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC3 channel is configured as output 01: CC3 channel is configured as input, IC3 is mapped on TI3 10: CC3 channel is configured as input, IC3 is mapped on TI4 11: CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (SMCR register) 0 2 CCER CCER Capture/Compare enable register 0x20 0x20 read-write 0x00000000 RSVD 16 16 CC4NP Capture/Compare 4 output Polarity. 15 1 RSVD2 14 1 CC4P Capture/Compare 4 output Polarity. 13 1 CC4E Capture/Compare 4 output enable. 12 1 CC3NP Capture/Compare 3 output Polarity. 11 1 RSVD3 10 1 CC3P Capture/Compare 3 output Polarity. 9 1 CC3E Capture/Compare 3 output enable. 8 1 CC2NP Capture/Compare 2 output Polarity. 7 1 RSVD4 6 1 CC2P Capture/Compare 2 output Polarity. 5 1 CC2E Capture/Compare 2 output enable. 4 1 CC1NP Capture/Compare 1 output Polarity. CC1 channel configured as output: CC1NP must be kept cleared in this case. CC1 channel configured as input: This bit is used in conjunction with CC1P to define TI1FP1/TI2FP1 polarity. refer to CC1P description. 3 1 RSVD5 2 1 CC1P Capture/Compare 1 output Polarity. CC1 channel configured as output: 0: OC1 active high 1: OC1 active low CC1 channel configured as input: CC1NP/CC1P bits select TI1FP1 and TI2FP1 polarity for trigger or capture operations. 00: noninverted/rising edge Circuit is sensitive to TIxFP1 rising edge (capture, trigger in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger in gated mode, encoder mode). 01: inverted/falling edge Circuit is sensitive to TIxFP1 falling edge (capture, trigger in reset, external clock or trigger mode), TIxFP1 is inverted (trigger in gated mode, encoder mode). 10: reserved, do not use this configuration. 11: noninverted/both edges Circuit is sensitive to both TIxFP1 rising and falling edges (capture, trigger in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger in gated mode). This configuration must not be used for encoder mode. 1 1 CC1E Capture/Compare 1 output enable. CC1 channel configured as output: 0: Off - OC1 is not active 1: On - OC1 signal is output on the corresponding output pin CC1 channel configured as input: This bit determines if a capture of the counter value can actually be done into the input capture/compare register 1 (CCR1) or not. 0: Capture disabled 1: Capture enabled 0 1 CNT CNT Counter 0x24 0x20 read-write 0x00000000 UIFCPY Value depends on IUFREMAP in CR1. If UIFREMAP = 1 UIFCPY: UIF Copy This bit is a read-only copy of the UIF bit of the ISR register 31 1 RSVD 16 15 CNT counter value 0 16 PSC PSC Prescaler 0x28 0x20 read-write 0x00000000 RSVD 16 16 PSC Prescaler value The counter clock frequency is equal to fCLK / (PSC[15:0] + 1). PSC contains the value to be loaded in the active prescaler register at each update event (including when the counter is cleared through UG bit of EGR register or through trigger controller when configured in 'reset mode'). 0 16 ARR ARR Auto-reload register 0x2c 0x20 read-write 0x00000000 RSVD 16 16 ARR Auto-reload value ARR is the value to be loaded in the actual auto-reload register. 0 16 RCR RCR Repetition counter register 0x30 0x20 read-write 0x00000000 RSVD 8 24 REP Repetition counter value These bits allow the user to set-up the update rate of the compare registers (i.e. periodic transfers from preload to active registers) when preload registers are enable, as well as the update interrupt generation rate, if this interrupt is enable. Each time the REP_CNT related downcounter reaches zero, an update event is generated and it restarts counting from REP value. As REP_CNT is reloaded with REP value only at the repetition update event, any write to the RCR register is not taken in account until the next repetition update event. It means in PWM mode (REP+1) corresponds to the number of PWM periods in edge-aligned mode. 0 8 CCR1 CCR1 Capture/Compare register 1 0x34 0x20 read-write 0x00000000 RSVD 16 16 CCR1 Capture/Compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value).It is loaded permanently if the preload feature is not selected in the CCMR1 register (bit OC1PE). Else the preload value is copied in the active capture/compare 1 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter CNT and signaled on OC1 output. If channel CC1is configured as input: CCR1 is the counter value transferred by the last input capture 1 event (IC1). The CCR1 register is read-only and cannot be programmed. 0 16 CCR2 CCR2 Capture/Compare register 2 0x38 0x20 read-write 0x00000000 RSVD 16 16 CCR2 Capture/Compare 2 value If channel CC2 is configured as output: CCR2 is the value to be loaded in the actual capture/compare 2 register (preload value).It is loaded permanently if the preload feature is not selected in the CCMR1 register (bit OC2PE). Else the preload value is copied in the active capture/compare 2 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter CNT and signalled on OC2 output. If channel CC2 is configured as input: CCR2 is the counter value transferred by the last input capture 2 event (IC2). The CCR2 register is read-only and cannot be programmed. 0 16 CCR3 CCR3 Capture/Compare register 3 0x3c 0x20 read-write 0x00000000 RSVD 16 16 CCR3 Capture/Compare value If channel CC3 is configured as output: CCR3 is the value to be loaded in the actual capture/compare 3 register (preload value).It is loaded permanently if the preload feature is not selected in the CCMR2 register (bit OC3PE). Else the preload value is copied in the active capture/compare 3 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter CNT and signalled on OC3 output. If channel CC3is configured as input: CCR3 is the counter value transferred by the last input capture 3 event (IC3). The CCR3 register is read-only and cannot be programmed. 0 16 CCR4 CCR4 Capture/Compare register 4 0x40 0x20 read-write 0x00000000 RSVD 16 16 CCR4 Capture/Compare value 1. if CC4 channel is configured as output: CCR4 is the value to be loaded in the actual capture/compare 4 register (preload value).It is loaded permanently if the preload feature is not selected in the CCMR2 register (bit OC4PE). Else the preload value is copied in the active capture/compare 4 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter CNT and signalled on OC4 output. 2. if CC4 channel is configured as input: CCR4 is the counter value transferred by the last input capture 4 event (IC4). The CCR4 register is read-only and cannot be programmed. 0 16 BTIM2 BTIM 0x500b1000 0x0 0x1000 registers CR1 CR1 TIM control register 1 0x00 0x20 read-write 0x00000000 RSVD 8 24 ARPE Auto-reload preload enable 0: ARR register is not buffered 1: ARR register is buffered 7 1 RSVD2 4 3 OPM One-pulse mode 0: Counter is not stopped at update event 1: Counter stops counting at the next update event (clearing the bit CEN) 3 1 URS Update request source This bit is set and cleared by software to select the UEV event sources. 0: Any of the following events generate an update interrupt or DMA request if enabled. These events can be: Counter overflow Setting the UG bit Update generation through the slave mode controller 1: Only counter overflow generates an update interrupt or DMA request if enabled. 2 1 UDIS Update disable This bit is set and cleared by software to enable/disable UEV event generation. 0: UEV enabled. The Update (UEV) event is generated by one of the following events: Counter overflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values. 1: UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller. 1 1 CEN Counter enable 0: Counter disabled 1: Counter enabled Note: Gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. CEN is cleared automatically in one-pulse mode, when an update event occurs. 0 1 CR2 CR2 TIM control register 2 0x04 0x20 read-write 0x00000000 RSVD 6 26 MMS Master mode selection These bits allow to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: 00: Reset:the UG bit from the EGR register is used as trigger output (TRGO). If the reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on TRGO is delayed compared to the actual reset. 01: Enable :the Counter enable signal, CNT_EN, is used as trigger output (TRGO). It is useful to start several timers at the same time or to control a window in which a slave timer is enabled. The Counter Enable signal is generated by a logic OR between CEN control bit and the trigger input when configured in gated mode. When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in SMCR register). 10: Update:The update event is selected as trigger output (TRGO). For instance a master timer can then be used as a prescaler for a slave timer. 11: Gating:The delayed gating trigger is selected as trigger output (TRGO). 4 2 RSVD2 0 4 SMCR SMCR TIM slave mode control register 0x08 0x20 read-write 0x00000000 RSVD 24 8 GM Gated Mode. The counter clock is enabled when the selected trigger input (TRGI) is active (according to gating trigger polarity). The counter stops (but is not reset) as soon as the trigger becomes inactive. Both start and stop of the counter are controlled. Gated mode and slave mode can be enabled simutanuously with different trigger selection. 23 1 GTP Gating trigger polarity invert 0: active at high level 1: active at low level 22 1 GTS Gating trigger selection in gated mode This bit-field selects the trigger input to be used to enable the counter gating. 00: Internal Trigger 0 (ITR0) 01: Internal Trigger 1 (ITR1) 10: Internal Trigger 2 (ITR2) 11: Internal Trigger 3 (ITR3) 20 2 RSVD2 19 1 SMS Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input. 000: Slave mode disabled. 001: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers. 010: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled. 011: Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter. 100: External Clock Mode - Rising edges of the selected trigger (TRGI) clock the counter. 16 3 RSVD3 8 8 MSM Master/Slave mode. This bit should be asserted on master timer if synchronization if needed. 0: No action 1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event. 7 1 RSVD4 6 1 TS Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. 00: Internal Trigger 0 (ITR0) 01: Internal Trigger 1 (ITR1) 10: Internal Trigger 2 (ITR2) 11: Internal Trigger 3 (ITR3) 4 2 RSVD5 0 4 DIER DIER TIM DMA/Interrupt enable register 0x0c 0x20 read-write 0x00000000 RSVD 9 23 UDE Update DMA request enable 0: Update DMA request disabled. 1: Update DMA request enabled 8 1 RSVD2 1 7 UIE Update interrupt enable 0: Update interrupt disabled. 1: Update interrupt enabled 0 1 SR SR TIM status register 0x10 0x20 read-write 0x00000000 RSVD 1 31 UIF Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. 0: No update occurred 1: Update interrupt pending. This bit is set by hardware when the registers are updated: At overflow and if UDIS=0 in the CR1 register. When CNT is reinitialized by software using the UG bit in EGR register, if URS=0 and UDIS=0 in the CR1 register. When CNT is reinitialized by a trigger event (refer to the synchro control register description), if URS=0 and UDIS=0 in the CR1 register. 0 1 EGR EGR Event generation register 0x14 0x20 read-write 0x00000000 RSVD 1 31 UG Update generation This bit can be set by software, it is automatically cleared by hardware. 0: No action 1: Re-initialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected). The counter is cleared if the center-aligned mode is selected or if DIR=0 (upcounting), else it takes the auto-reload value (ARR) if DIR=1 (downcounting). 0 1 RSVD1 RSVD1 0x18 0x20 read-write 0x0 CNT CNT Counter 0x24 0x20 read-write 0x00000000 CNT counter value 0 32 PSC PSC Prescaler 0x28 0x20 read-write 0x00000000 RSVD 16 16 PSC Prescaler value The counter clock frequency is equal to fCLK / (PSC[15:0] + 1). PSC contains the value to be loaded in the active prescaler register at each update event (including when the counter is cleared through UG bit of EGR register or through trigger controller when configured in "reset mode"). 0 16 ARR ARR Auto-reload register 0x2c 0x20 read-write 0x00000000 ARR Auto-reload value ARR is the value to be loaded in the actual auto-reload register. The counter is blocked while the auto-reload value is null. 0 32 HPSYS_AON HPSYS_AON 0x500c0000 0x0 0x1000 registers PMR PMR Power Mode Register 0x00 0x20 read-write 0x0 FORCE_SLEEP Set 1 to force enter low power mode. Will be cleared automatically 31 1 FORCE_LCPU for debug only 30 1 RSVD 2 28 MODE Power Mode: 2'h0 - active; 2'h1 - light sleep; 2'h2 - deep sleep; 2'h3 - standby 0 2 CR1 CR1 Control Register 1 0x04 0x20 read-write 0x0 GTIM_EN Enable global timer 31 1 PINOUT_SEL1 for debug only 28 3 PINOUT_SEL0 for debug only 25 3 RSVD 12 13 PIN3_MODE mode for wakeup PIN3 (PA27) 9 3 PIN2_MODE mode for wakeup PIN2 (PA26) 6 3 PIN1_MODE mode for wakeup PIN1 (PA25) 3 3 PIN0_MODE mode for wakeup PIN0 (PA24) 0 - high level, 1 - low level, 2 - pos edge, 3 - neg edge, 4/5/6/7: pos or neg edge 0 3 CR2 CR2 Control Register 2 0x08 0x20 read-write 0x0 RSVD 24 8 PIN15_MODE mode for wakeup PIN15 (PA39) 21 3 PIN14_MODE mode for wakeup PIN14 (PA38) 18 3 PIN13_MODE mode for wakeup PIN13 (PA37) 15 3 PIN12_MODE mode for wakeup PIN12 (PA36) 12 3 PIN11_MODE mode for wakeup PIN11 (PA35) 9 3 PIN10_MODE mode for wakeup PIN10 (PA34) 0 - high level, 1 - low level, 2 - pos edge, 3 - neg edge, 4/5/6/7: pos or neg edge 6 3 RSVD2 0 6 CR3 CR3 Control Register 3 0x0c 0x20 read-write 0x0 RSVD 15 17 PIN20_MODE mode for wakeup PIN20 (PA44) 12 3 PIN19_MODE mode for wakeup PIN19 (PA43) 9 3 PIN18_MODE mode for wakeup PIN18 (PA42) 6 3 PIN17_MODE mode for wakeup PIN17 (PA41) 3 3 PIN16_MODE mode for wakeup PIN16 (PA40) 0 - high level, 1 - low level, 2 - pos edge, 3 - neg edge, 4/5/6/7: pos or neg edge 0 3 ACR ACR Active Mode Control register 0x10 0x20 read-write 0x0 HXT48_RDY Indicate hxt48 is ready 31 1 HRC48_RDY Indicate hrc48 is ready 30 1 RSVD 4 26 EXTPWR_REQ for debug only 3 1 PWR_REQ Request power during Active mode 2 1 HXT48_REQ Request hxt48 in active mode 1 1 HRC48_REQ Request hrc48 in active mode 0 1 LSCR LSCR Light Sleep Ctrl Register 0x14 0x20 read-write 0x0 RSVD 4 28 EXTPWR_REQ for debug only 3 1 PWR_REQ Request power during Light Sleep mode 2 1 HXT48_REQ Request hxt48 in Light Sleep mode 1 1 HRC48_REQ Request hrc48 in Light Sleep mode 0 1 DSCR DSCR Deep Sleep Ctrl Register 0x18 0x20 read-write 0x0 RSVD 4 28 EXTPWR_REQ for debug only 3 1 PWR_REQ Request power during Deep Sleep mode 2 1 HXT48_REQ Request hxt48 in Deep Sleep mode 1 1 HRC48_REQ Request hrc48 in Deep Sleep mode 0 1 SBCR SBCR Standby Mode Ctrl Register 0x1c 0x20 read-write 0x0 RSVD 9 23 PD_RAM2 for debug only 8 1 PD_RAM1 for debug only 7 1 PD_RAM0 for debug only 6 1 RSVD2 4 2 EXTPWR_REQ for debug only 3 1 PWR_REQ Request power during Standby mode 2 1 HXT48_REQ Request hxt48 in Standby mode 1 1 HRC48_REQ Request hrc48 in Standby mode 0 1 WER WER Wakeup Enable register 0x20 0x20 read-write 0x0 RSVD 29 3 PIN20 Set 1 to enable PA44 as wakeup source 28 1 PIN19 Set 1 to enable PA43 as wakeup source 27 1 PIN18 Set 1 to enable PA42 as wakeup source 26 1 PIN17 Set 1 to enable PA41 as wakeup source 25 1 PIN16 Set 1 to enable PA40 as wakeup source 24 1 PIN15 Set 1 to enable PA39 as wakeup source 23 1 PIN14 Set 1 to enable PA38 as wakeup source 22 1 PIN13 Set 1 to enable PA37 as wakeup source 21 1 PIN12 Set 1 to enable PA36 as wakeup source 20 1 PIN11 Set 1 to enable PA35 as wakeup source 19 1 PIN10 Set 1 to enable PA34 as wakeup source 18 1 RSVD2 12 6 PIN3 Set 1 to enable PA27 as wakeup source 11 1 PIN2 Set 1 to enable PA26 as wakeup source 10 1 PIN1 Set 1 to enable PA25 as wakeup source 9 1 PIN0 Set 1 to enable PA24 as wakeup source 8 1 LP2HP_IRQ Set 1 to enable MAILBOX2 as wakeup source 7 1 LP2HP_REQ Set 1 to enable LPSYS request as wakeup source 6 1 RSVD3 4 2 PMUC Set 1 to enable PMUC as wakeup source 3 1 LPTIM1 Set 1 to enable LPTIM1 as wakeup source 2 1 GPIO1 Set 1 to enable IO(PA) as wakeup source 1 1 RTC Set 1 to enable RTC as wakeup source 0 1 WSR WSR Wakeup Status register 0x24 0x20 read-write 0x0 RSVD 29 3 PIN20 Indicates the wakeup status from PA44 request. Note: the status is masked by WER 28 1 PIN19 Indicates the wakeup status from PA43 request. Note: the status is masked by WER 27 1 PIN18 Indicates the wakeup status from PA42 request. Note: the status is masked by WER 26 1 PIN17 Indicates the wakeup status from PA41 request. Note: the status is masked by WER 25 1 PIN16 Indicates the wakeup status from PA40 request. Note: the status is masked by WER 24 1 PIN15 Indicates the wakeup status from PA39 request. Note: the status is masked by WER 23 1 PIN14 Indicates the wakeup status from PA38 request. Note: the status is masked by WER 22 1 PIN13 Indicates the wakeup status from PA37 request. Note: the status is masked by WER 21 1 PIN12 Indicates the wakeup status from PA36 request. Note: the status is masked by WER 20 1 PIN11 Indicates the wakeup status from PA35 request. Note: the status is masked by WER 19 1 PIN10 Indicates the wakeup status from PA34 request. Note: the status is masked by WER 18 1 RSVD2 12 6 PIN3 Indicates the wakeup status from PA27 request. Note: the status is masked by WER 11 1 PIN2 Indicates the wakeup status from PA26 request. Note: the status is masked by WER 10 1 PIN1 Indicates the wakeup status from PA25 request. Note: the status is masked by WER 9 1 PIN0 Indicates the wakeup status from PA24 request. Note: the status is masked by WER 8 1 LP2HP_IRQ Indicates the wakeup status from MAILBOX2. Note: the status is masked by WER 7 1 LP2HP_REQ Indicates the wakeup status from LPSYS request. Note: the status is masked by WER 6 1 RSVD3 4 2 PMUC Indicates the wakeup status from PMUC. Note: the status is masked by WER 3 1 LPTIM1 Indicates the wakeup status from LPTIM1. Note: the status is masked by WER 2 1 GPIO1 Indicates the wakeup status from IO(PA). Note: the status is masked by WER 1 1 RTC Indicates the wakeup status from RTC. Note: the status is masked by WER 0 1 WCR WCR Wakeup Clear register 0x28 0x20 read-write 0x0 AON Write 1 to clear the AON wakeup IRQ status 31 1 RSVD 29 2 PIN20 Write 1 to clear PA44 wakeup source. Only valid if PIN wakeup is configured as edge trigger 28 1 PIN19 Write 1 to clear PA43 wakeup source. Only valid if PIN wakeup is configured as edge trigger 27 1 PIN18 Write 1 to clear PA42 wakeup source. Only valid if PIN wakeup is configured as edge trigger 26 1 PIN17 Write 1 to clear PA41 wakeup source. Only valid if PIN wakeup is configured as edge trigger 25 1 PIN16 Write 1 to clear PA40 wakeup source. Only valid if PIN wakeup is configured as edge trigger 24 1 PIN15 Write 1 to clear PA39 wakeup source. Only valid if PIN wakeup is configured as edge trigger 23 1 PIN14 Write 1 to clear PA38 wakeup source. Only valid if PIN wakeup is configured as edge trigger 22 1 PIN13 Write 1 to clear PA37 wakeup source. Only valid if PIN wakeup is configured as edge trigger 21 1 PIN12 Write 1 to clear PA36 wakeup source. Only valid if PIN wakeup is configured as edge trigger 20 1 PIN11 Write 1 to clear PA35 wakeup source. Only valid if PIN wakeup is configured as edge trigger 19 1 PIN10 Write 1 to clear PA34 wakeup source. Only valid if PIN wakeup is configured as edge trigger 18 1 RSVD2 12 6 PIN3 Write 1 to clear PA27 wakeup source. Only valid if PIN wakeup is configured as edge trigger 11 1 PIN2 Write 1 to clear PA26 wakeup source. Only valid if PIN wakeup is configured as edge trigger 10 1 PIN1 Write 1 to clear PA25 wakeup source. Only valid if PIN wakeup is configured as edge trigger 9 1 PIN0 Write 1 to clear PA24 wakeup source. Only valid if PIN wakeup is configured as edge trigger 8 1 RSVD3 Note: for RTC/IO(PA)/LPTIM/PMUC, clear the wakeup status directly in the orignal module 0 8 ISSR ISSR Inter System Wakeup Register 0x2c 0x20 read-write 0x0 RSVD 6 26 LP_ACTIVE Read 1 indicates LPSYS is active 5 1 HP_ACTIVE Write 1 to indicates HPSYS is active 4 1 RSVD2 2 2 LP2HP_REQ Indicate LPSYS request exists 1 1 HP2LP_REQ Write 1 to request LPSYS to stay in active mode 0 1 ANACR ANACR Analog Control Register 0x30 0x20 read-write 0x0 RSVD 2 30 VHP_ISO Set 1 to force off all HPSYS related analog modules 1 1 PA_ISO Set 1 to force IO(PA) into retention mode 0 1 GTIMR GTIMR Global Timer Register 0x34 0x20 read-write 0x0 CNT Global timer value 0 32 RESERVE0 RESERVE0 Reserved Register 0 0x38 0x20 read-write 0x0 DATA for debug only 0 32 RESERVE1 RESERVE1 Reserved Register 1 0x3c 0x20 read-write 0x0 DATA for debug only 0 32 LPTIM1 LPTIM 0x500c1000 0x0 0x1000 registers ISR ISR LPTIM interrupt and status register 0x00 0x20 read-write 0x00000000 RSVD 11 21 OCWKUP Indicates output compare wakeup occurred The OCWKUP bit is set by hardware when LPTIM_CNT register value reached the LPTIM_CMP register’s value. To clear OCWKUP, first write 0 to the OCWE bit in the LPTIM_IER register to disable, then write 1 to the WKUPCLR bit in the LPTIM_ICR register. 10 1 OFWKUP Indicates overflow wakeup occurred OFWKUP is set by hardware when LPTIM_CNT register’s value reached the LPTIM_ARR register’s value and count from zero again. To clear OFWKUP, first write 0 to the OFWE bit in the LPTIM_IER register to disable, then write 1 to the WKUPCLR bit in the LPTIM_ICR register. 9 1 UEWKUP Indicates update event wakeup occurred UEWKUP is set by hardware when an update event was generated (overflow occurred while repetition counter reached zero). To clear UEWKUP, first write 0 to the UEWE bit in the LPTIM_IER register to disable, then write 1 to the WKUPCLR bit in the LPTIM_ICR register. 8 1 RSVD2 4 4 ET External trigger edge event ET is set by hardware to inform application that a valid edge on the selected external trigger input has occurred. If the trigger is ignored because the timer has already started, then this flag is not set. ET flag can be cleared by writing 1 to the ETCLR bit in the LPTIM_ICR register. 3 1 OC Output compare match The OC bit is set by hardware to inform application that LPTIM_CNT register value reached the LPTIM_CMP register’s value. OC flag can be cleared by writing 1 to the OCCLR bit in the LPTIM_ICR register. 2 1 OF Overflow occurred OF is set by hardware to inform application that LPTIM_CNT register’s value reached the LPTIM_ARR register’s value and count from zero again. OF flag can be cleared by writing 1 to the OFCLR bit in the LPTIM_ICR register. 1 1 UE LPTIM update event occurred UE is set by hardware to inform application that an update event was generated when overflow occurred while repetition counter reached zero. UE flag can be cleared by writing 1 to the UECLR bit in the LPTIM_ICR register. 0 1 ICR ICR LPTIM interrupt and status clear register 0x04 0x20 read-write 0x00000000 RSVD 9 23 WKUPCLR wakeup status clear flag Writing 1 to this bit clears all wakeup status flags in the LPTIM_ISR register. 8 1 RSVD2 4 4 ETCLR External trigger valid edge clear flag Writing 1 to this bit clears the ET flag in the LPTIM_ISR register 3 1 OCCLR Output compare clear flag Writing 1 to this bit clears the OC flag in the LPTIM_ISR register 2 1 OFCLR Overflow clear flag Writing 1 to this bit clears the OF flag in the LPTIM_ISR register 1 1 UECLR Update event clear flag Writing 1 to this bit clear the UE flag in the LPTIM_ISR register. 0 1 IER IER LPTIM interrupt and wakeup enable register 0x08 0x20 read-write 0x00000000 RSVD 11 21 OCWE Output compare Wakeup Enable 0: Output compare wakeup disabled 1: Output compare wakeup enabled 10 1 OFWE Overflow Wakeup Enable 0: Overflow Wakeup disabled 1: Overflow Wakeup enabled 9 1 UEWE Update event Wakeup enable 0: Update event Wakeup disabled 1: Update event Wakeup enabled 8 1 RSVD2 4 4 ETIE External trigger valid edge Interrupt Enable 0: External trigger interrupt disabled 1: External trigger interrupt enabled 3 1 OCIE Output compare Interrupt Enable 0: Output compare interrupt disabled 1: Output compare interrupt enabled 2 1 OFIE Overflow Interrupt Enable 0: Overflow interrupt disabled 1: Overflow interrupt enabled 1 1 UEIE Update event interrupt enable 0: Update event interrupt disabled 1: Update event interrupt enabled 0 1 CFGR CFGR LPTIM configuration register 0x0c 0x20 read-write 0x00000000 RSVD 24 8 COUNTMODE counter mode in internal clock source mode (CKSEL=0). If CKSEL=1, this bit has no effect. 0: the counter is incremented following each internal clock pulse 1: the counter is incremented following each valid pulse on the external clock 23 1 RSVD2 22 1 WAVPOL Waveform shape polarity The WAVEPOL bit controls the output polarity 0: The LPTIM output reflects the compare results between LPTIM_ARR and LPTIM_CMP registers 1: The LPTIM output reflects the inverse of the compare results between LPTIM_ARR and LPTIM_CMP registers 21 1 WAVE Waveform shape The WAVE bit controls the output shape 0: Deactivate Set-once mode 1: Activate the Set-once mode 20 1 TIMOUT Timeout enable The TIMOUT bit controls the Timeout feature 0: A trigger event arriving when the timer is already started will be ignored 1: A trigger event arriving when the timer is already started will reset and restart the LPTIM counter and the repetition counter 19 1 TRIGEN Trigger enable and polarity The TRIGEN bits controls whether the LPTIM counter is started by an external trigger or not. If the external trigger option is selected, three configurations are possible for the trigger active edge: 00: software trigger (counting start is initiated by software) 01: rising edge is the active edge 10: falling edge is the active edge 11: both edges are active edges 17 2 RSVD3 16 1 TRIGSEL Trigger selector The TRIGSEL bits select the trigger source that will serve as a trigger event for the LPTIM among the below 8 available sources: 000: lptim_ext0 001: lptim_ext1 010: lptim_ext2 011: lptim_ext3 100: lptim_ext4 101: lptim_ext5 110: lptim_ext6 111: lptim_ext7 13 3 RSVD4 12 1 PRESC Clock prescaler The PRESC bits configure the prescaler division factor. It can be one among the following division factors: 000: /1 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128 9 3 EXTCKSEL External clock source selector 0: external clock source is from lptim_in 1: external clock source is from LPCOMP (if LPCOMP integrated) 8 1 TRGFLT Configurable digital filter for trigger The TRGFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an internal trigger before it is considered as a valid level transition. An internal clock source must be present to use this feature 00: any trigger active level change is considered as a valid trigger 01: trigger active level change must be stable for at least 2 clock periods before it is considered as valid trigger. 10: trigger active level change must be stable for at least 4 clock periods before it is considered as valid trigger. 11: trigger active level change must be stable for at least 8 clock periods before it is considered as valid trigger. 6 2 INTCKSEL Internal clock source selector 0: internal clock source is clk_lp 1: internal clock source is pclk2 5 1 CKFLT Configurable digital filter for external clock The CKFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an external clock signal before it is considered as a valid level transition. An internal clock source must be present to use this feature 00: any external clock signal level change is considered as a valid transition 01: external clock signal level change must be stable for at least 2 clock periods before it is considered as valid transition. 10: external clock signal level change must be stable for at least 4 clock periods before it is considered as valid transition. 11: external clock signal level change must be stable for at least 8 clock periods before it is considered as valid transition. 3 2 CKPOL Clock Polarity If LPTIM is clocked by an external clock source, CKPOL bits is used to configure the active edge or edges used by the counter: 00: the rising edge is the active edge used for counting 01: the falling edge is the active edge used for counting 10: both edges are active edges. When both external clock signal edges are considered active ones, the LPTIM must also be clocked by an internal clock source with a frequency equal to at least four time the external clock frequency. 11: not allowed 1 2 CKSEL Clock selector The CKSEL bit selects which clock source the LPTIM will use: 0: LPTIM is clocked by internal clock source, according to INTCKSEL 1: LPTIM is clocked by external clock source, according to EXTCKSEL 0 1 CR CR LPTIM control register 0x10 0x20 read-write 0x00000000 RSVD 4 28 COUNTRST Counter reset This bit is set by software and cleared by hardware. When set to 1 this bit will trigger a synchronous reset of the CNT register. Due to the synchronous nature of this reset, it only takes place after a synchronization delay. COUNTRST must never be set to 1 by software before it is already cleared to 0 by hardware. Software should consequently check that COUNTRST bit is already cleared to 0 before attempting to set it to 1. 3 1 CNTSTRT Timer start in Continuous mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = 00), setting this bit starts the LPTIM in Continuous mode. If the software start is disabled (TRIGEN[1:0] different than 00), setting this bit starts the timer in Continuous mode as soon as an external trigger is detected. If this bit is set when a single pulse mode counting is ongoing, then the timer will not stop at the next match between ARR and CNT registers and the LPTIM counter keeps counting in Continuous mode. 2 1 SNGSTRT LPTIM start in Single mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = 00), setting this bit starts the LPTIM in single pulse mode. If the software start is disabled (TRIGEN[1:0] different than 00), setting this bit starts the LPTIM in single pulse mode as soon as an external trigger is detected. If this bit is set when the LPTIM is in continuous counting mode, then the LPTIM will stop at the following match between ARR and CNT registers. If this bit is set simultaneously with CNTSTRT, then LPTIM will be in continuous counting mode. 1 1 ENABLE LPTIM enable The ENABLE bit is set and cleared by software. 0:LPTIM is disabled 1:LPTIM is enabled 0 1 CMP CMP LPTIM compare register 0x14 0x20 read-write 0x00000000 RSVD 24 8 CMP Compare value CMP is the compare value used by the LPTIM. 0 24 ARR ARR LPTIM autoreload register 0x18 0x20 read-write 0x00000000 RSVD 24 8 ARR Auto reload value ARR is the autoreload value for the LPTIM. This value must be strictly greater than the CMP[15:0] value. 0 24 CNT CNT LPTIM counter register 0x1c 0x20 read-write 0x00000000 RSVD 24 8 CNT Counter value When the LPTIM is running with an asynchronous clock, reading the CNT register may return unreliable values. So in this case it is necessary to perform two consecutive read accesses and verify that the two returned values are identical. 0 24 RCR RCR LPTIM repetition register 0x20 0x20 read-write 0x00000000 RSVD 8 24 REP Repetition register value REP is the repetition value for the LPTIM. Read REP will return left repetition times. It should be noted that for a reliable REP register read access, two consecutive read accesses must be performed and compared. A read access can be considered reliable when the values of the two consecutive read accesses are equal. 0 8 LPTIM2 LPTIM 0x500c2000 0x0 0x1000 registers ISR ISR LPTIM interrupt and status register 0x00 0x20 read-write 0x00000000 RSVD 11 21 OCWKUP Indicates output compare wakeup occurred The OCWKUP bit is set by hardware when LPTIM_CNT register value reached the LPTIM_CMP register’s value. To clear OCWKUP, first write 0 to the OCWE bit in the LPTIM_IER register to disable, then write 1 to the WKUPCLR bit in the LPTIM_ICR register. 10 1 OFWKUP Indicates overflow wakeup occurred OFWKUP is set by hardware when LPTIM_CNT register’s value reached the LPTIM_ARR register’s value and count from zero again. To clear OFWKUP, first write 0 to the OFWE bit in the LPTIM_IER register to disable, then write 1 to the WKUPCLR bit in the LPTIM_ICR register. 9 1 UEWKUP Indicates update event wakeup occurred UEWKUP is set by hardware when an update event was generated (overflow occurred while repetition counter reached zero). To clear UEWKUP, first write 0 to the UEWE bit in the LPTIM_IER register to disable, then write 1 to the WKUPCLR bit in the LPTIM_ICR register. 8 1 RSVD2 4 4 ET External trigger edge event ET is set by hardware to inform application that a valid edge on the selected external trigger input has occurred. If the trigger is ignored because the timer has already started, then this flag is not set. ET flag can be cleared by writing 1 to the ETCLR bit in the LPTIM_ICR register. 3 1 OC Output compare match The OC bit is set by hardware to inform application that LPTIM_CNT register value reached the LPTIM_CMP register’s value. OC flag can be cleared by writing 1 to the OCCLR bit in the LPTIM_ICR register. 2 1 OF Overflow occurred OF is set by hardware to inform application that LPTIM_CNT register’s value reached the LPTIM_ARR register’s value and count from zero again. OF flag can be cleared by writing 1 to the OFCLR bit in the LPTIM_ICR register. 1 1 UE LPTIM update event occurred UE is set by hardware to inform application that an update event was generated when overflow occurred while repetition counter reached zero. UE flag can be cleared by writing 1 to the UECLR bit in the LPTIM_ICR register. 0 1 ICR ICR LPTIM interrupt and status clear register 0x04 0x20 read-write 0x00000000 RSVD 9 23 WKUPCLR wakeup status clear flag Writing 1 to this bit clears all wakeup status flags in the LPTIM_ISR register. 8 1 RSVD2 4 4 ETCLR External trigger valid edge clear flag Writing 1 to this bit clears the ET flag in the LPTIM_ISR register 3 1 OCCLR Output compare clear flag Writing 1 to this bit clears the OC flag in the LPTIM_ISR register 2 1 OFCLR Overflow clear flag Writing 1 to this bit clears the OF flag in the LPTIM_ISR register 1 1 UECLR Update event clear flag Writing 1 to this bit clear the UE flag in the LPTIM_ISR register. 0 1 IER IER LPTIM interrupt and wakeup enable register 0x08 0x20 read-write 0x00000000 RSVD 11 21 OCWE Output compare Wakeup Enable 0: Output compare wakeup disabled 1: Output compare wakeup enabled 10 1 OFWE Overflow Wakeup Enable 0: Overflow Wakeup disabled 1: Overflow Wakeup enabled 9 1 UEWE Update event Wakeup enable 0: Update event Wakeup disabled 1: Update event Wakeup enabled 8 1 RSVD2 4 4 ETIE External trigger valid edge Interrupt Enable 0: External trigger interrupt disabled 1: External trigger interrupt enabled 3 1 OCIE Output compare Interrupt Enable 0: Output compare interrupt disabled 1: Output compare interrupt enabled 2 1 OFIE Overflow Interrupt Enable 0: Overflow interrupt disabled 1: Overflow interrupt enabled 1 1 UEIE Update event interrupt enable 0: Update event interrupt disabled 1: Update event interrupt enabled 0 1 CFGR CFGR LPTIM configuration register 0x0c 0x20 read-write 0x00000000 RSVD 24 8 COUNTMODE counter mode in internal clock source mode (CKSEL=0). If CKSEL=1, this bit has no effect. 0: the counter is incremented following each internal clock pulse 1: the counter is incremented following each valid pulse on the external clock 23 1 RSVD2 22 1 WAVPOL Waveform shape polarity The WAVEPOL bit controls the output polarity 0: The LPTIM output reflects the compare results between LPTIM_ARR and LPTIM_CMP registers 1: The LPTIM output reflects the inverse of the compare results between LPTIM_ARR and LPTIM_CMP registers 21 1 WAVE Waveform shape The WAVE bit controls the output shape 0: Deactivate Set-once mode 1: Activate the Set-once mode 20 1 TIMOUT Timeout enable The TIMOUT bit controls the Timeout feature 0: A trigger event arriving when the timer is already started will be ignored 1: A trigger event arriving when the timer is already started will reset and restart the LPTIM counter and the repetition counter 19 1 TRIGEN Trigger enable and polarity The TRIGEN bits controls whether the LPTIM counter is started by an external trigger or not. If the external trigger option is selected, three configurations are possible for the trigger active edge: 00: software trigger (counting start is initiated by software) 01: rising edge is the active edge 10: falling edge is the active edge 11: both edges are active edges 17 2 RSVD3 16 1 TRIGSEL Trigger selector The TRIGSEL bits select the trigger source that will serve as a trigger event for the LPTIM among the below 8 available sources: 000: lptim_ext0 001: lptim_ext1 010: lptim_ext2 011: lptim_ext3 100: lptim_ext4 101: lptim_ext5 110: lptim_ext6 111: lptim_ext7 13 3 RSVD4 12 1 PRESC Clock prescaler The PRESC bits configure the prescaler division factor. It can be one among the following division factors: 000: /1 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128 9 3 EXTCKSEL External clock source selector 0: external clock source is from lptim_in 1: external clock source is from LPCOMP (if LPCOMP integrated) 8 1 TRGFLT Configurable digital filter for trigger The TRGFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an internal trigger before it is considered as a valid level transition. An internal clock source must be present to use this feature 00: any trigger active level change is considered as a valid trigger 01: trigger active level change must be stable for at least 2 clock periods before it is considered as valid trigger. 10: trigger active level change must be stable for at least 4 clock periods before it is considered as valid trigger. 11: trigger active level change must be stable for at least 8 clock periods before it is considered as valid trigger. 6 2 INTCKSEL Internal clock source selector 0: internal clock source is clk_lp 1: internal clock source is pclk2 5 1 CKFLT Configurable digital filter for external clock The CKFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an external clock signal before it is considered as a valid level transition. An internal clock source must be present to use this feature 00: any external clock signal level change is considered as a valid transition 01: external clock signal level change must be stable for at least 2 clock periods before it is considered as valid transition. 10: external clock signal level change must be stable for at least 4 clock periods before it is considered as valid transition. 11: external clock signal level change must be stable for at least 8 clock periods before it is considered as valid transition. 3 2 CKPOL Clock Polarity If LPTIM is clocked by an external clock source, CKPOL bits is used to configure the active edge or edges used by the counter: 00: the rising edge is the active edge used for counting 01: the falling edge is the active edge used for counting 10: both edges are active edges. When both external clock signal edges are considered active ones, the LPTIM must also be clocked by an internal clock source with a frequency equal to at least four time the external clock frequency. 11: not allowed 1 2 CKSEL Clock selector The CKSEL bit selects which clock source the LPTIM will use: 0: LPTIM is clocked by internal clock source, according to INTCKSEL 1: LPTIM is clocked by external clock source, according to EXTCKSEL 0 1 CR CR LPTIM control register 0x10 0x20 read-write 0x00000000 RSVD 4 28 COUNTRST Counter reset This bit is set by software and cleared by hardware. When set to 1 this bit will trigger a synchronous reset of the CNT register. Due to the synchronous nature of this reset, it only takes place after a synchronization delay. COUNTRST must never be set to 1 by software before it is already cleared to 0 by hardware. Software should consequently check that COUNTRST bit is already cleared to 0 before attempting to set it to 1. 3 1 CNTSTRT Timer start in Continuous mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = 00), setting this bit starts the LPTIM in Continuous mode. If the software start is disabled (TRIGEN[1:0] different than 00), setting this bit starts the timer in Continuous mode as soon as an external trigger is detected. If this bit is set when a single pulse mode counting is ongoing, then the timer will not stop at the next match between ARR and CNT registers and the LPTIM counter keeps counting in Continuous mode. 2 1 SNGSTRT LPTIM start in Single mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = 00), setting this bit starts the LPTIM in single pulse mode. If the software start is disabled (TRIGEN[1:0] different than 00), setting this bit starts the LPTIM in single pulse mode as soon as an external trigger is detected. If this bit is set when the LPTIM is in continuous counting mode, then the LPTIM will stop at the following match between ARR and CNT registers. If this bit is set simultaneously with CNTSTRT, then LPTIM will be in continuous counting mode. 1 1 ENABLE LPTIM enable The ENABLE bit is set and cleared by software. 0:LPTIM is disabled 1:LPTIM is enabled 0 1 CMP CMP LPTIM compare register 0x14 0x20 read-write 0x00000000 RSVD 24 8 CMP Compare value CMP is the compare value used by the LPTIM. 0 24 ARR ARR LPTIM autoreload register 0x18 0x20 read-write 0x00000000 RSVD 24 8 ARR Auto reload value ARR is the autoreload value for the LPTIM. This value must be strictly greater than the CMP[15:0] value. 0 24 CNT CNT LPTIM counter register 0x1c 0x20 read-write 0x00000000 RSVD 24 8 CNT Counter value When the LPTIM is running with an asynchronous clock, reading the CNT register may return unreliable values. So in this case it is necessary to perform two consecutive read accesses and verify that the two returned values are identical. 0 24 RCR RCR LPTIM repetition register 0x20 0x20 read-write 0x00000000 RSVD 8 24 REP Repetition register value REP is the repetition value for the LPTIM. Read REP will return left repetition times. It should be noted that for a reliable REP register read access, two consecutive read accesses must be performed and compared. A read access can be considered reliable when the values of the two consecutive read accesses are equal. 0 8 PMUC PMUC 0x500ca000 0x0 0x1000 registers CR CR Control Register 0x00 0x20 read-write 0x00000000 RSVD 20 12 PIN1_SEL 15 5 PIN0_SEL select one out of PA[44:24]. 0 - PA24, 1 - PA25, 20 - PA44, etc. 10 5 PIN1_MODE 0 - high level, 1 - low level, 2 - pos edge, 3 - neg edge 7 3 PIN0_MODE 4/6 - both edge (high-active detection), 5/7 - both edge (low-active detection) 4 3 PIN_RET If set to 1, IO retained during hibernate mode; otherwise, high-Z 3 1 REBOOT Write 1 to reboot; write 0 to clear after boot up 2 1 HIBER_EN Write 1 to enter hibernate mode; write 0 to clear when exit from hibernate 1 1 SEL_LPCLK LP clock for watchdog and FSM. 0 - LRC10, 1 - LRC32 0 1 WER WER Wakeup Enable register 0x04 0x20 read-write 0x00000000 RSVD 9 23 CHG 8 1 LOWBAT If enabled, auto shut down upon battery low; and will power up if battery ready 7 1 RSVD2 5 2 PIN1 Set 1 to enable PIN1 as wakeup source 4 1 PIN0 Set 1 to enable PIN0 as wakeup source 3 1 WDT2 Set 1 to enable WDT2 as reboot cause 2 1 WDT1 Set 1 to enable WDT1 as reboot cause 1 1 RTC Set 1 to enable RTC as wakeup source 0 1 WSR WSR Wakeup Status register 0x08 0x20 read-write 0x00000000 RSVD 9 23 CHG 8 1 LOWBAT Indicates auto reboot due to battery low 7 1 PWRKEY 6 1 IWDT 5 1 PIN1 4 1 PIN0 3 1 WDT2 Indicates reboot by WDT2 2 1 WDT1 Indicates reboot by WDT1 1 1 RTC Indicates the wakeup status from RTC. Note: the status is masked by WER 0 1 WCR WCR Wakeup Clear register 0x0c 0x20 read-write 0x00000000 AON Write 1 to clear the AON wakeup IRQ status 31 1 RSVD 8 23 LOWBAT Write 1 to clear LOWBAT flag 7 1 PWRKEY Write 1 to clear PWRKEY reset flag 6 1 RSVD2 Clear status in IWDT 5 1 PIN1 Write 1 to clear PIN1 wakeup flag. 4 1 PIN0 Write 1 to clear PIN0 wakeup flag. Only valid if PIN wakeup is configured as edge trigger 3 1 WDT2 Write 1 to clear WDT2 reboot flag 2 1 WDT1 Write 1 to clear WDT1 reboot flag 1 1 RSVD3 Clear status in RTC 0 1 VRTC_CR VRTC_CR VRTC Control Register 0x10 0x20 read-write 0x00000000 RSVD 13 19 BOR_VT_TRIM 9 4 BOR_EN Brownout Reset Enable 8 1 VRTC_TRIM 4 4 VRTC_VBIT 0 4 VRET_CR VRET_CR VRET Control Register 0x14 0x20 read-write 0x00000000 RDY 31 1 RSVD 22 9 DLY VRET_LDO power up delay in number of CLK_LP cycles 16 6 RSVD2 14 2 TRIM 10 4 RSVD3 6 4 VBIT 2 4 BM 1 1 EN 0 1 LRC10_CR LRC10_CR RC10K Control Register 0x18 0x20 read-write 0x00000000 RDY 31 1 RSVD 9 22 REFRES 8 1 CHGCAP 6 2 CHGCRT 4 2 CMPBM2 3 1 CMPBM1 1 2 EN Enabled by default 0 1 LRC32_CR LRC32_CR RC32K Control Register 0x1c 0x20 read-write 0x00000000 RDY 31 1 RSVD 10 21 RSEL 6 4 CHGCRT 4 2 CMPBM2 3 1 CMPBM1 1 2 EN Disabled by default 0 1 LXT_CR LXT_CR XTAL32K Control Register 0x20 0x20 read-write 0x00000000 RDY 31 1 RSVD 16 15 EXT_EN use external 32K from Pin 15 1 CAP_SEL 14 1 BMSTART 10 4 BMSEL 9 1 AMPCTRL_ENB 8 1 AMP_BM 6 2 BM 2 4 RSN 1 1 EN 0 1 AON_BG AON_BG AON Bandgap Register 0x24 0x20 read-write 0x00000000 RSVD 6 26 BUF_VOS_POLAR 5 1 BUF_VOS_STEP 3 2 BUF_VOS_TRIM 0 3 AON_LDO AON_LDO AON LDO Register 0x28 0x20 read-write 0x00000000 RSVD 7 25 VBAT_POR_TH 4 3 VBAT_LDO_SET_VOUT 0 4 BUCK_CR1 BUCK_CR1 BUCK Control Register 1 0x2c 0x20 read-write 0x00000000 SS_DONE 31 1 BG_BUF_VOS_POLAR 30 1 BG_BUF_VOS_STEP 28 2 BG_BUF_VOS_TRIM 25 3 UVLO_X_BIAS 24 1 ZCD_AON 23 1 OCP_AON 22 1 SEL_LX22 21 1 SEL_IOCP_HI 20 1 IOCP_TUNE 17 3 COMP_IDYN_TUNE 15 2 COMP_IQ_TUNE 13 2 COMP_BM_AHI 12 1 COT_CTUNE 9 3 MOT_CTUNE 6 3 RSVD 2 4 CTRL 1 1 EN 0 1 BUCK_CR2 BUCK_CR2 BUCK Control Register 2 0x30 0x20 read-write 0x00000000 TDIS Discharge for TDIS*4 LP clock cycles during reboot 28 4 SET_VOUT_L 0.75V 24 4 SET_VOUT_M 1.1V 20 4 FORCE_RDY 19 1 BYPASS_UVLO 18 1 BYPASS_OCP 17 1 BYPASS_PG 16 1 L2M_CNT 12 4 L2H_CNT 8 4 M2H_CNT 4 4 L2M_EN 3 1 M2L_EN 2 1 H2L_EN 1 1 H2M_EN 0 1 CHG_CR1 CHG_CR1 Charger Control Register 1 0x34 0x20 read-write 0x00000000 CV_VCTRL 26 6 CC_RANGE 24 2 CC_MN 19 5 CC_MP 14 5 CC_VCTRL 8 6 CC_ICTRL 2 6 LOOP_EN only available when CR3 FORCE_CTRL bit is set 1 1 EN only available when CR3 FORCE_CTRL bit is set 0 1 CHG_CR2 CHG_CR2 Charger Control Register 2 0x38 0x20 read-write 0x00000000 VBAT_RANGE 28 4 RANGE_EOC 27 1 BM_EOC 24 3 HIGH_VCTRL 18 6 REP_VCTRL 12 6 PRECC_ICTRL 6 6 PRECC_RANGE 4 2 BG_PROG_V1P2 0 4 CHG_CR3 CHG_CR3 Charger Control Register 3 0x3c 0x20 read-write 0x00000000 FORCE_CTRL When charger plugged out, this bit will auto reset 31 1 FORCE_RST When charger plugged out, this bit will auto reset 30 1 RSVD 11 19 DLY2 6 5 DLY1 0 6 CHG_CR4 CHG_CR4 Charger Control Register 4 0x40 0x20 read-write 0x00000000 IM_EOC_MODE 29 3 IM_CV_MODE 26 3 IM_CC_MODE 23 3 IM_ABOVE_CC 20 3 IM_ABOVE_REP 17 3 IM_VBAT_HIGH 14 3 IM_VBUS_RDY 0 - high level, 1 - low level, 2 - pos edge, 3 - neg edge, others - both edge 11 3 RSVD 8 3 IE_EOC 7 1 IE_EOC_MODE 6 1 IE_CV_MODE 5 1 IE_CC_MODE 4 1 IE_ABOVE_CC 3 1 IE_ABOVE_REP 2 1 IE_VBAT_HIGH 1 1 IE_VBUS_RDY 0 1 CHG_CR5 CHG_CR5 Charger Control Register 5 0x44 0x20 read-write 0x00000000 RSVD 24 8 IS_EOC 23 1 IS_EOC_MODE 22 1 IS_CV_MODE 21 1 IS_CC_MODE 20 1 IS_ABOVE_CC 19 1 IS_ABOVE_REP 18 1 IS_VBAT_HIGH 17 1 IS_VBUS_RDY 16 1 RSVD2 8 8 IC_EOC 7 1 IC_EOC_MODE 6 1 IC_CV_MODE 5 1 IC_CC_MODE 4 1 IC_ABOVE_CC 3 1 IC_ABOVE_REP 2 1 IC_VBAT_HIGH 1 1 IC_VBUS_RDY 0 1 CHG_SR CHG_SR Charger Status Register 0x48 0x20 read-write 0x00000000 RSVD 15 17 CHG_STATE Charger finite state machine 8 7 RSVD2 7 1 EOC_MODE 6 1 CV_MODE 5 1 CC_MODE 4 1 VBAT_ABOVE_CC_OUT 3 1 VBAT_ABOVE_REP_OUT 2 1 VBAT_HIGH_OUT 1 1 VBUS_RDY_OUT 0 1 HPSYS_LDO HPSYS_LDO HPSYS LDO Control Register 0x4c 0x20 read-write 0x00000000 RSVD 17 15 RDY 16 1 DLY HPSYS_LDO power up delay in CLK_LP cycles 10 6 VREF2 Lower voltage for deep sleep mode (0.6V) 6 4 VREF optional voltage (0.9V) 2 4 BP 1 1 EN 0 1 LPSYS_LDO LPSYS_LDO LPSYS LDO Control Register 0x50 0x20 read-write 0x00000000 RSVD 17 15 RDY 16 1 DLY LPSYS_LDO power up delay in CLK_LP cycles 10 6 VREF2 Lower voltage for deep sleep mode (0.6V) 6 4 VREF optional voltage (1.0V) 2 4 BP 1 1 EN 0 1 HPSYS_SWR HPSYS_SWR HPSYS Switch Register 0x54 0x20 read-write 0x00000000 RDY 31 1 RSVD 8 23 NORET Cut off VHPMEM entirely during standby. No retention 7 1 DLY wait for N cycles before asserting RDY 4 3 PSW_RET PSW value during DS/SB 2 2 PSW [0] - RET_LDO; [1] - HPSYS_LDO 0 2 LPSYS_SWR LPSYS_SWR LPSYS Switch Register 0x58 0x20 read-write 0x00000000 RDY 31 1 RSVD 8 23 NORET Cut off VLPMEM entirely during standby. No retention 7 1 DLY wait for N cycles before asserting RDY 4 3 PSW_RET PSW value during DS/SB 2 2 PSW [0] - RET_LDO; [1] - LPSYS_LDO 0 2 PERI_LDO PERI_LDO Peripherals LDO 0x5c 0x20 read-write 0x00000000 RSVD 22 10 VDD33_LDO3_PD 21 1 VDD33_LDO3_SET_VOUT 17 4 EN_VDD33_LDO3 16 1 RSVD2 14 2 VDD33_LDO2_PD 13 1 VDD33_LDO2_SET_VOUT 9 4 EN_VDD33_LDO2 8 1 RSVD3 6 2 LDO18_PD 5 1 LDO18_VREF_SEL 1 4 EN_LDO18 0 1 PMU_TR PMU_TR PMU Test Register 0x60 0x20 read-write 0x00000000 RSVD 6 26 PMU_DC_MR macro select 3 3 PMU_DC_TR test point select 0 3 PMU_RSVD PMU_RSVD PMU Reserved Register 0x64 0x20 read-write 0x00000000 RESERVE3 24 8 RESERVE2 16 8 RESERVE1 8 8 RESERVE0 0 8 HXT_CR1 HXT_CR1 HXT48 Control Register 1 0x68 0x20 read-write 0x00000000 RSVD 30 2 CBANK_SEL 20 10 GM_EN 19 1 LDO_FLT_RSEL 17 2 LDO_VREF 13 4 BUF_RF_STR 11 2 BUF_AUD_STR 9 2 BUF_AUD_EN 8 1 BUF_DLL_STR 6 2 BUF_DLL_EN 5 1 BUF_DIG_STR 3 2 BUF_DIG_EN 2 1 BUF_EN 1 1 EN 0 1 HXT_CR2 HXT_CR2 HXT48 Control Register 2 0x6c 0x20 read-write 0x00000000 SLEEP_EN 31 1 SDADC_CLKDIV2_SEL 29 2 SDADC_CLKDIV1_SEL 27 2 SDADC_CLKIN_EN 26 1 IDAC 16 10 IDAC_EN 15 1 BUF_SEL3 13 2 BUF_SEL2 11 2 ACBUF_RSEL 10 1 ACBUF_SEL 8 2 AGC_VINDC 6 2 AGC_VTH 2 4 AGC_ISTART_SEL 1 1 AGC_EN 0 1 HXT_CR3 HXT_CR3 HXT48 Control Register 3 0x70 0x20 read-write 0x00000000 RSVD 10 22 DLY 4 6 BUF_OSLO_STR 2 2 BUF_DAC_STR 0 2 HRC_CR HRC_CR HRC48 Control Register 0x74 0x20 read-write 0x00000000 DLY number of cycles for BG ready. 0 - one cycle of CLK_LP; 1 - two cycles of CLK_LP 31 1 RSVD 30 1 CLKLP_STR 28 2 CLKLP_SEL 26 2 CLKLP_EN 25 1 CLKHP_STR 23 2 CLKHP_SEL 21 2 CLKHP_EN 20 1 RSVD2 19 1 CLK96M_EN 18 1 TEMP_TRIM 15 3 FREQ_TRIM 5 10 LDO_VREF 1 4 EN 0 1 DBL96_CR DBL96_CR DBL96 Control Register 0x78 0x20 read-write 0x00000000 RSVD 29 3 DLY_SEL_EXT 18 11 DLY_SEL_EXT_EN 17 1 DLY_EXT_EN 16 1 DLY_EN 12 4 PH_EN 8 4 LOOP_RSTB 7 1 TOOSLO_EN 6 1 TORF_EN 5 1 TODIG_STR 3 2 TODIG_EN 2 1 OUT_EN 1 1 EN 0 1 DBL96_CALR DBL96_CALR DBL96 Calibration Register 0x7c 0x20 read-write 0x00000000 RSVD 14 18 CAL_LOCK 13 1 CAL_OP 2 11 CAL_CLOSE_EXT_EN 1 1 CAL_EN 0 1 CAU_BGR CAU_BGR CAU Bandgap Register 0x80 0x20 read-write 0x00000000 RSVD 11 21 LPBG_VREF12 7 4 LPBG_VREF06 3 4 LPBG_EN 2 1 HPBG_EN 1 1 HPBG_VDDPSW_EN 0 1 CAU_TR CAU_TR CAU Test Register 0x84 0x20 read-write 0x00000000 RSVD 9 23 CAU_DC_MR 6 3 CAU_DC_BR 3 3 CAU_DC_TR 0 3 CAU_RSVD CAU_RSVD CAU Reserved Register 0x88 0x20 read-write 0x00000000 RSVD 24 8 RESERVE2 16 8 RESERVE1 8 8 RESERVE0 0 8 WKUP_CNT WKUP_CNT Wakeup Count Register 0x8c 0x20 read-write 0x00000000 PIN1_CNT 16 16 PIN0_CNT 0 16 PWRKEY_CNT PWRKEY_CNT PowerKey Count Register 0x90 0x20 read-write 0x00000000 RSVD 20 12 RST_CNT press high for RST_CNT*16 CLK_WDT cycles to reset the whole chip 4 16 RSVD2 0 4 HPSYS_VOUT HPSYS_VOUT 0x94 0x20 read-write 0x00000000 RSVD 4 28 VOUT 0xD - 1.2V, 0xA - 1.1V, 0x8 - 1.0V, 0x5 - 0.9V 0 4 LPSYS_VOUT LPSYS_VOUT 0x98 0x20 read-write 0x00000000 RSVD 4 28 VOUT 0x8 - 1.0V, 0x5 - 0.9V 0 4 BUCK_VOUT BUCK_VOUT 0x9c 0x20 read-write 0x00000000 RSVD 4 28 VOUT 0xF - 1.35V, 0xD - 1.25V, 0x9 - 1.05V, 0x6 - 0.9V, 0x2 - 0.7V 0 4 IWDT WDT 0x500cc000 0x0 0x1000 registers WDT_CVR0 WDT_CVR0 WatchDog Counter Value 0 0x00 0x20 read-write 0x0 RSVD 24 8 COUNT_VALUE_0 Count Value for 1st TimeOut 0 24 WDT_CVR1 WDT_CVR1 WatchDog Counter Value 1 0x04 0x20 read-write 0x0 RSVD 24 8 COUNT_VALUE_1 Count Value for 2nd TimeOut 0 24 WDT_CR WDT_CR WatchDog Control Register 0x08 0x20 read-write 0x0 RSVD 5 27 RESPONSE_MODE 0:reset only, 1:interrupt and reset 4 1 RSVD2 3 1 RESET_LENGTH reset pulse length in number of wdt clock cycles 0 3 WDT_CCR WDT_CCR WatchDog Counter Control Register 0x0c 0x20 read-write 0x0 RSVD 8 24 COUNTER_CONTROL SinglePulse /Write 8'h76 to restart, write8'h34 to stop, else do nothing 0 8 WDT_ICR WDT_ICR WatchDog Interrupt Clear Register 0x10 0x20 read-write 0x0 RSVD 1 31 INT_CLR SinglePulse /A pulse to clear interrupt 0 1 WDT_SR WDT_SR WatchDog Status Register 0x14 0x20 read-write 0x0 RSVD 2 30 WDT_ACTIVE Watchdog runs when 1, else 0 1 1 INT_ASSERT Interrupt assert when 1 0 1 WDT_WP WDT_WP WatchDog Write Protect Register 0x18 0x20 read-write 0x0 WRPT_ST 1 indicates write protect is active 31 1 WRPT write 0x58ab99fc generate write_protect, write 0x51ff8621 to release 0 31 WDT_FG WDT_FG WatchDog Flag Register 0x1c 0x20 read-write 0x0 RSVD 4 28 SYNC_FG 1 indicates one transition from system clk to wdt clk has complicated 3 1 SYNC_FG_CLR SinglePulse/A pulse to clear sync flag 2 1 RST_FG 1 indicates wdt has already reset system 1 1 RST_FG_CLR SinglePulse/A pulse to clear reset flag 0 1 LPSYS_RCC LPSYS_RCC 0x40000000 0x0 0x1000 registers RSTR1 RSTR1 Reset Register 1 0x00 0x20 read-write 0x0 RSVD 22 10 CRC2 0 - no reset; 1 - reset 21 1 MAC 0 - no reset; 1 - reset 20 1 PHY 0 - no reset; 1 - reset 19 1 RFC 0 - no reset; 1 - reset 18 1 RSVD2 17 1 GPIO2 0 - no reset; 1 - reset 16 1 SYSCFG2 0 - no reset; 1 - reset 15 1 RSVD3 11 4 BTIM4 0 - no reset; 1 - reset 10 1 BTIM3 0 - no reset; 1 - reset 9 1 PTC2 0 - no reset; 1 - reset 8 1 RSVD4 7 1 USART5 0 - no reset; 1 - reset 6 1 USART4 0 - no reset; 1 - reset 5 1 PATCH 0 - no reset; 1 - reset 4 1 PINMUX2 0 - no reset; 1 - reset 3 1 MAILBOX2 0 - no reset; 1 - reset 2 1 DMAC2 0 - no reset; 1 - reset 1 1 LCPU 0 - no reset; 1 - reset 0 1 ENR1 ENR1 Enable Register 1 0x04 0x20 read-write 0x0 RSVD 22 10 CRC2 0 - disabled; 1 - enabled 21 1 MAC 0 - disabled; 1 - enabled 20 1 PHY 0 - disabled; 1 - enabled 19 1 RFC 0 - disabled; 1 - enabled 18 1 RSVD2 17 1 GPIO2 0 - disabled; 1 - enabled 16 1 SYSCFG2 0 - disabled; 1 - enabled 15 1 RSVD3 11 4 BTIM4 0 - disabled; 1 - enabled 10 1 BTIM3 0 - disabled; 1 - enabled 9 1 PTC2 0 - disabled; 1 - enabled 8 1 SECU2 0 - disabled; 1 - enabled 7 1 USART5 0 - disabled; 1 - enabled 6 1 USART4 0 - disabled; 1 - enabled 5 1 PATCH 0 - disabled; 1 - enabled 4 1 PINMUX2 0 - disabled; 1 - enabled 3 1 MAILBOX2 0 - disabled; 1 - enabled 2 1 DMAC2 0 - disabled; 1 - enabled 1 1 RSVD4 0 1 ESR1 ESR1 Enable Set Register 1 0x08 0x20 read-write 0x0 RSVD 22 10 CRC2 write 1 to set module enable, write 0 has no effect 21 1 MAC write 1 to set module enable, write 0 has no effect 20 1 PHY write 1 to set module enable, write 0 has no effect 19 1 RFC write 1 to set module enable, write 0 has no effect 18 1 RSVD2 17 1 GPIO2 write 1 to set module enable, write 0 has no effect 16 1 SYSCFG2 write 1 to set module enable, write 0 has no effect 15 1 RSVD3 11 4 BTIM4 write 1 to set module enable, write 0 has no effect 10 1 BTIM3 write 1 to set module enable, write 0 has no effect 9 1 PTC2 write 1 to set module enable, write 0 has no effect 8 1 SECU2 write 1 to set module enable, write 0 has no effect 7 1 USART5 write 1 to set module enable, write 0 has no effect 6 1 USART4 write 1 to set module enable, write 0 has no effect 5 1 PATCH write 1 to set module enable, write 0 has no effect 4 1 PINMUX2 write 1 to set module enable, write 0 has no effect 3 1 MAILBOX2 write 1 to set module enable, write 0 has no effect 2 1 DMAC2 write 1 to set module enable, write 0 has no effect 1 1 RSVD4 0 1 ECR1 ECR1 Enable Clear Register 1 0x0c 0x20 read-write 0x0 RSVD 22 10 CRC2 write 1 to clear module enable, write 0 has no effect 21 1 MAC write 1 to clear module enable, write 0 has no effect 20 1 PHY write 1 to clear module enable, write 0 has no effect 19 1 RFC write 1 to clear module enable, write 0 has no effect 18 1 RSVD2 17 1 GPIO2 write 1 to clear module enable, write 0 has no effect 16 1 SYSCFG2 write 1 to clear module enable, write 0 has no effect 15 1 RSVD3 11 4 BTIM4 write 1 to clear module enable, write 0 has no effect 10 1 BTIM3 write 1 to clear module enable, write 0 has no effect 9 1 PTC2 write 1 to clear module enable, write 0 has no effect 8 1 SECU2 write 1 to clear module enable, write 0 has no effect 7 1 USART5 write 1 to clear module enable, write 0 has no effect 6 1 USART4 write 1 to clear module enable, write 0 has no effect 5 1 PATCH write 1 to clear module enable, write 0 has no effect 4 1 PINMUX2 write 1 to clear module enable, write 0 has no effect 3 1 MAILBOX2 write 1 to clear module enable, write 0 has no effect 2 1 DMAC2 write 1 to clear module enable, write 0 has no effect 1 1 RSVD4 0 1 CSR CSR Clock Select Register 0x10 0x20 read-write 0x0 RSVD 7 25 SEL_TICK select clock source for systick reference 0 - clk_rtc; 1 - reserved; 2 - clk_hrc48; 3 - clk_hxt48 5 2 SEL_PERI select clk_peri_lpsys source 0 - clk_hrc48; 1 - clk_hxt48 4 1 RSVD2 3 1 SEL_SYS_LP select clk_lpsys source 0 - selected by SEL_SYS; 1 - clk_wdt 2 1 RSVD3 1 1 SEL_SYS select clk_lpsys source 0 - clk_hrc48; 1 - clk_hxt48 0 1 CFGR CFGR Clock Configuration Register 0x14 0x20 read-write 0x0 RSVD 31 1 TICKDIV systick reference clock is systick reference clock source (selected by SEL_TICK) devided by TICKDIV 25 6 MACFREQ clock frequency of MAC clock 20 5 MACDIV MAC clock divider MACCLK = hclk_lpsys / MACDIV 16 4 RSVD2 15 1 PDIV2 pclk2_lpsys = hclk_lpsys / (2^PDIV2), by default divided by 32 12 3 RSVD3 11 1 PDIV1 pclk1_lpsys = hclk_lpsys / (2^PDIV1), by default divided by 2 8 3 RSVD4 6 2 HDIV1 hclk_lpsys = clk_lpsys / HDIV if HDIV=0, hclk_lpsys = clk_lpsys 0 6 DBGR DBGR Debug Register 0x18 0x20 read-write 0x0 RSVD 6 26 SYSCLK_SWBT If set to 1, clk_lpsys will: switch from clk_hrc48 to clk_hxt48 when MAC active; switch from clk_hxt48 to clk_hrc48 when MAC sleep; 5 1 FORCE_GPIO for debug only 4 1 FORCE_MAC for debug only 3 1 FORCE_BUS for debug only 2 1 SYSCLK_SWLP for debug only 1 1 SYSCLK_AON for debug only 0 1 DMAC2 DMAC 0x40001000 0x0 0x1000 registers ISR ISR 0x00 0x20 read-write 0x00000000 TEIF8 channel transfer error flag 31 1 HTIF8 channel half transfer flag 30 1 TCIF8 channel transfer complete flag 29 1 GIF8 channel global interrupt flag 28 1 TEIF7 channel transfer error flag 27 1 HTIF7 channel half transfer flag 26 1 TCIF7 channel transfer complete flag 25 1 GIF7 channel global interrupt flag 24 1 TEIF6 channel transfer error flag 23 1 HTIF6 channel half transfer flag 22 1 TCIF6 channel transfer complete flag 21 1 GIF6 channel global interrupt flag 20 1 TEIF5 channel transfer error flag 19 1 HTIF5 channel half transfer flag 18 1 TCIF5 channel transfer complete flag 17 1 GIF5 channel global interrupt flag 16 1 TEIF4 channel transfer error flag 15 1 HTIF4 channel half transfer flag 14 1 TCIF4 channel transfer complete flag 13 1 GIF4 channel global interrupt flag 12 1 TEIF3 channel transfer error flag 11 1 HTIF3 channel half transfer flag 10 1 TCIF3 channel transfer complete flag 9 1 GIF3 channel global interrupt flag 8 1 TEIF2 channel transfer error flag 7 1 HTIF2 channel half transfer flag 6 1 TCIF2 channel transfer complete flag 5 1 GIF2 channel global interrupt flag 4 1 TEIF1 channel transfer error flag. Set when bus error detected. Cleared when write 1 to CTEIF or CGIF. 3 1 HTIF1 channel half transfer flag. Set when half NDT are transferred. Cleared when write 1 to CHTIF or CGIF. 2 1 TCIF1 channel transfer complete flag. Set when all NDT are transferred. Cleared when write 1 to CTCIF or CGIF. 1 1 GIF1 channel global interrupt flag. Set when any of TEIF/HTIF/TCIF asserted. Cleared when TEIF/HTIF/TCIF all cleared. 0 1 IFCR IFCR 0x04 0x20 read-write 0x00000000 CTEIF8 CTEIF, transfer error flag clear 31 1 CHTIF8 CHTIF, half transfer flag clear 30 1 CTCIF8 CTCIF, transfer complete flag clear 29 1 CGIF8 CGIF, global interrupt flag clear 28 1 CTEIF7 CTEIF, transfer error flag clear 27 1 CHTIF7 CHTIF, half transfer flag clear 26 1 CTCIF7 CTCIF, transfer complete flag clear 25 1 CGIF7 CGIF, global interrupt flag clear 24 1 CTEIF6 CTEIF, transfer error flag clear 23 1 CHTIF6 CHTIF, half transfer flag clear 22 1 CTCIF6 CTCIF, transfer complete flag clear 21 1 CGIF6 CGIF, global interrupt flag clear 20 1 CTEIF5 CTEIF, transfer error flag clear 19 1 CHTIF5 CHTIF, half transfer flag clear 18 1 CTCIF5 CTCIF, transfer complete flag clear 17 1 CGIF5 CGIF, global interrupt flag clear 16 1 CTEIF4 CTEIF, transfer error flag clear 15 1 CHTIF4 CHTIF, half transfer flag clear 14 1 CTCIF4 CTCIF, transfer complete flag clear 13 1 CGIF4 CGIF, global interrupt flag clear 12 1 CTEIF3 CTEIF, transfer error flag clear 11 1 CHTIF3 CHTIF, half transfer flag clear 10 1 CTCIF3 CTCIF, transfer complete flag clear 9 1 CGIF3 CGIF, global interrupt flag clear 8 1 CTEIF2 CTEIF, transfer error flag clear 7 1 CHTIF2 CHTIF, half transfer flag clear 6 1 CTCIF2 CTCIF, transfer complete flag clear 5 1 CGIF2 CGIF, global interrupt flag clear 4 1 CTEIF1 CTEIF, transfer error flag clear. Write 1 to clear TEIF. 3 1 CHTIF1 CHTIF, half transfer flag clear. Write 1 to clear HTIF. 2 1 CTCIF1 CTCIF, transfer complete flag clear. Write 1 to clear TCIF. 1 1 CGIF1 CGIF, global interrupt flag clear. Write 1 to clear all TEIF/HTIF/TCIF. 0 1 CCR1 CCR1 0x08 0x20 read-write 0x00000000 RSVD 15 17 MEM2MEM memory-to-memory mode 0: disabled 1: enabled 14 1 PL priority level 00: low 01: medium 10: high 11: very high 12 2 MSIZE memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved 10 2 PSIZE peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved 8 2 MINC memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 0: disabled 1: enabled 7 1 PINC peripheral increment mode Defines the increment mode for each DMA transfer to the identified peripheral. n memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 0: disabled 1: enabled 6 1 CIRC circular mode 0: disabled 1: enabled 5 1 DIR data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. 0: read from peripheral Source attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. Destination attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode. 1: read from memory Destination attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. Source attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode. 4 1 TEIE transfer error interrupt enable 0: disabled 1: enabled 3 1 HTIE half transfer interrupt enable 0: disabled 1: enabled 2 1 TCIE transfer complete interrupt enable 0: disabled 1: enabled 1 1 EN channel enable When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the ISR register is cleared (by setting the CTEIFx bit of the IFCR register). 0: disabled 1: enabled 0 1 CNDTR1 CNDTR1 0x0c 0x20 read-write 0x00000000 RSVD 16 16 NDT number of data to transfer (0 to 2^16 - 1) This field is updated by hardware when the channel is enabled: It is decremented after each single DMA 'read followed by write' transfer, indicating the remaining amount of data items to transfer. It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC = 0 in the CCRx register). It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC = 1). If this field is zero, no transfer can be served whatever the channel status (enabled or not). 0 16 CPAR1 CPAR1 0x10 0x20 read-write 0x00000000 PA peripheral address It contains the base address of the peripheral data register from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory destination address if DIR = 1 and the memory source address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral destination address DIR = 1 and the peripheral source address if DIR = 0. 0 32 CM0AR1 CM0AR1 0x14 0x20 read-write 0x00000000 MA memory address It contains the base address of the memory from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory source address if DIR = 1 and the memory destination address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral source address DIR = 1 and the peripheral destination address if DIR = 0. 0 32 CBSR1 CBSR1 0x18 0x20 read-write 0x00000000 RSVD 8 24 BS burst size in non-m2m mode When BS>1, DMA will transfer for BS times for each request if left NDT is larger than BS, or else transfer for left NDT times. When BS=0 or 1, DMA will always do single transfer for each request. In memory-to-memory mode, BS is ignored. 0 8 CCR2 CCR2 0x1c 0x20 read-write 0x00000000 RSVD 15 17 MEM2MEM memory-to-memory mode 0: disabled 1: enabled 14 1 PL priority level 00: low 01: medium 10: high 11: very high 12 2 MSIZE memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved 10 2 PSIZE peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved 8 2 MINC memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 0: disabled 1: enabled 7 1 PINC peripheral increment mode Defines the increment mode for each DMA transfer to the identified peripheral. n memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 0: disabled 1: enabled 6 1 CIRC circular mode 0: disabled 1: enabled 5 1 DIR data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. 0: read from peripheral Source attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. Destination attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode. 1: read from memory Destination attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. Source attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode. 4 1 TEIE transfer error interrupt enable 0: disabled 1: enabled 3 1 HTIE half transfer interrupt enable 0: disabled 1: enabled 2 1 TCIE transfer complete interrupt enable 0: disabled 1: enabled 1 1 EN channel enable When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the ISR register is cleared (by setting the CTEIFx bit of the IFCR register). 0: disabled 1: enabled 0 1 CNDTR2 CNDTR2 0x20 0x20 read-write 0x00000000 RSVD 16 16 NDT number of data to transfer (0 to 2^16 - 1) This field is updated by hardware when the channel is enabled: It is decremented after each single DMA 'read followed by write' transfer, indicating the remaining amount of data items to transfer. It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC = 0 in the CCRx register). It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC = 1). If this field is zero, no transfer can be served whatever the channel status (enabled or not). 0 16 CPAR2 CPAR2 0x24 0x20 read-write 0x00000000 PA peripheral address It contains the base address of the peripheral data register from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory destination address if DIR = 1 and the memory source address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral destination address DIR = 1 and the peripheral source address if DIR = 0. 0 32 CM0AR2 CM0AR2 0x28 0x20 read-write 0x00000000 MA peripheral address It contains the base address of the memory from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory source address if DIR = 1 and the memory destination address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral source address DIR = 1 and the peripheral destination address if DIR = 0. 0 32 CBSR2 CBSR2 0x2c 0x20 read-write 0x00000000 RSVD 8 24 BS burst size in non-m2m mode When BS>1, DMA will transfer for BS times for each request if left NDT is larger than BS, or else transfer for left NDT times. When BS=0 or 1, DMA will always do single transfer for each request. In memory-to-memory mode, BS is ignored. 0 8 CCR3 CCR3 0x30 0x20 read-write 0x00000000 RSVD 15 17 MEM2MEM memory-to-memory mode 0: disabled 1: enabled 14 1 PL priority level 00: low 01: medium 10: high 11: very high 12 2 MSIZE memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved 10 2 PSIZE peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved 8 2 MINC memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 0: disabled 1: enabled 7 1 PINC peripheral increment mode Defines the increment mode for each DMA transfer to the identified peripheral. n memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 0: disabled 1: enabled 6 1 CIRC circular mode 0: disabled 1: enabled 5 1 DIR data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. 0: read from peripheral Source attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. Destination attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode. 1: read from memory Destination attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. Source attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode. 4 1 TEIE transfer error interrupt enable 0: disabled 1: enabled 3 1 HTIE half transfer interrupt enable 0: disabled 1: enabled 2 1 TCIE transfer complete interrupt enable 0: disabled 1: enabled 1 1 EN channel enable When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the ISR register is cleared (by setting the CTEIFx bit of the IFCR register). 0: disabled 1: enabled 0 1 CNDTR3 CNDTR3 0x34 0x20 read-write 0x00000000 RSVD 16 16 NDT number of data to transfer (0 to 2^16 - 1) This field is updated by hardware when the channel is enabled: It is decremented after each single DMA 'read followed by write' transfer, indicating the remaining amount of data items to transfer. It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC = 0 in the CCRx register). It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC = 1). If this field is zero, no transfer can be served whatever the channel status (enabled or not). 0 16 CPAR3 CPAR3 0x38 0x20 read-write 0x00000000 PA peripheral address It contains the base address of the peripheral data register from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory destination address if DIR = 1 and the memory source address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral destination address DIR = 1 and the peripheral source address if DIR = 0. 0 32 CM0AR3 CM0AR3 0x3c 0x20 read-write 0x00000000 MA peripheral address It contains the base address of the memory from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory source address if DIR = 1 and the memory destination address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral source address DIR = 1 and the peripheral destination address if DIR = 0. 0 32 CBSR3 CBSR3 0x40 0x20 read-write 0x00000000 RSVD 8 24 BS burst size in non-m2m mode When BS>1, DMA will transfer for BS times for each request if left NDT is larger than BS, or else transfer for left NDT times. When BS=0 or 1, DMA will always do single transfer for each request. In memory-to-memory mode, BS is ignored. 0 8 CCR4 CCR4 0x44 0x20 read-write 0x00000000 RSVD 15 17 MEM2MEM memory-to-memory mode 0: disabled 1: enabled 14 1 PL priority level 00: low 01: medium 10: high 11: very high 12 2 MSIZE memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved 10 2 PSIZE peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved 8 2 MINC memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 0: disabled 1: enabled 7 1 PINC peripheral increment mode Defines the increment mode for each DMA transfer to the identified peripheral. n memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 0: disabled 1: enabled 6 1 CIRC circular mode 0: disabled 1: enabled 5 1 DIR data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. 0: read from peripheral Source attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. Destination attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode. 1: read from memory Destination attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. Source attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode. 4 1 TEIE transfer error interrupt enable 0: disabled 1: enabled 3 1 HTIE half transfer interrupt enable 0: disabled 1: enabled 2 1 TCIE transfer complete interrupt enable 0: disabled 1: enabled 1 1 EN channel enable When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the ISR register is cleared (by setting the CTEIFx bit of the IFCR register). 0: disabled 1: enabled 0 1 CNDTR4 CNDTR4 0x48 0x20 read-write 0x00000000 RSVD 16 16 NDT number of data to transfer (0 to 2^16 - 1) This field is updated by hardware when the channel is enabled: It is decremented after each single DMA 'read followed by write' transfer, indicating the remaining amount of data items to transfer. It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC = 0 in the CCRx register). It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC = 1). If this field is zero, no transfer can be served whatever the channel status (enabled or not). 0 16 CPAR4 CPAR4 0x4c 0x20 read-write 0x00000000 PA peripheral address It contains the base address of the peripheral data register from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory destination address if DIR = 1 and the memory source address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral destination address DIR = 1 and the peripheral source address if DIR = 0. 0 32 CM0AR4 CM0AR4 0x50 0x20 read-write 0x00000000 MA peripheral address It contains the base address of the memory from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory source address if DIR = 1 and the memory destination address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral source address DIR = 1 and the peripheral destination address if DIR = 0. 0 32 CBSR4 CBSR4 0x54 0x20 read-write 0x00000000 RSVD 8 24 BS burst size in non-m2m mode When BS>1, DMA will transfer for BS times for each request if left NDT is larger than BS, or else transfer for left NDT times. When BS=0 or 1, DMA will always do single transfer for each request. In memory-to-memory mode, BS is ignored. 0 8 CCR5 CCR5 0x58 0x20 read-write 0x00000000 RSVD 15 17 MEM2MEM memory-to-memory mode 0: disabled 1: enabled 14 1 PL priority level 00: low 01: medium 10: high 11: very high 12 2 MSIZE memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved 10 2 PSIZE peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved 8 2 MINC memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 0: disabled 1: enabled 7 1 PINC peripheral increment mode Defines the increment mode for each DMA transfer to the identified peripheral. n memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 0: disabled 1: enabled 6 1 CIRC circular mode 0: disabled 1: enabled 5 1 DIR data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. 0: read from peripheral Source attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. Destination attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode. 1: read from memory Destination attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. Source attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode. 4 1 TEIE transfer error interrupt enable 0: disabled 1: enabled 3 1 HTIE half transfer interrupt enable 0: disabled 1: enabled 2 1 TCIE transfer complete interrupt enable 0: disabled 1: enabled 1 1 EN channel enable When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the ISR register is cleared (by setting the CTEIFx bit of the IFCR register). 0: disabled 1: enabled 0 1 CNDTR5 CNDTR5 0x5c 0x20 read-write 0x00000000 RSVD 16 16 NDT number of data to transfer (0 to 2^16 - 1) This field is updated by hardware when the channel is enabled: It is decremented after each single DMA 'read followed by write' transfer, indicating the remaining amount of data items to transfer. It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC = 0 in the CCRx register). It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC = 1). If this field is zero, no transfer can be served whatever the channel status (enabled or not). 0 16 CPAR5 CPAR5 0x60 0x20 read-write 0x00000000 PA peripheral address It contains the base address of the peripheral data register from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory destination address if DIR = 1 and the memory source address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral destination address DIR = 1 and the peripheral source address if DIR = 0. 0 32 CM0AR5 CM0AR5 0x64 0x20 read-write 0x00000000 MA peripheral address It contains the base address of the memory from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory source address if DIR = 1 and the memory destination address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral source address DIR = 1 and the peripheral destination address if DIR = 0. 0 32 CBSR5 CBSR5 0x68 0x20 read-write 0x00000000 RSVD 8 24 BS burst size in non-m2m mode When BS>1, DMA will transfer for BS times for each request if left NDT is larger than BS, or else transfer for left NDT times. When BS=0 or 1, DMA will always do single transfer for each request. In memory-to-memory mode, BS is ignored. 0 8 CCR6 CCR6 0x6c 0x20 read-write 0x00000000 RSVD 15 17 MEM2MEM memory-to-memory mode 0: disabled 1: enabled 14 1 PL priority level 00: low 01: medium 10: high 11: very high 12 2 MSIZE memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved 10 2 PSIZE peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved 8 2 MINC memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 0: disabled 1: enabled 7 1 PINC peripheral increment mode Defines the increment mode for each DMA transfer to the identified peripheral. n memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 0: disabled 1: enabled 6 1 CIRC circular mode 0: disabled 1: enabled 5 1 DIR data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. 0: read from peripheral Source attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. Destination attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode. 1: read from memory Destination attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. Source attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode. 4 1 TEIE transfer error interrupt enable 0: disabled 1: enabled 3 1 HTIE half transfer interrupt enable 0: disabled 1: enabled 2 1 TCIE transfer complete interrupt enable 0: disabled 1: enabled 1 1 EN channel enable When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the ISR register is cleared (by setting the CTEIFx bit of the IFCR register). 0: disabled 1: enabled 0 1 CNDTR6 CNDTR6 0x70 0x20 read-write 0x00000000 RSVD 16 16 NDT number of data to transfer (0 to 2^16 - 1) This field is updated by hardware when the channel is enabled: It is decremented after each single DMA 'read followed by write' transfer, indicating the remaining amount of data items to transfer. It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC = 0 in the CCRx register). It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC = 1). If this field is zero, no transfer can be served whatever the channel status (enabled or not). 0 16 CPAR6 CPAR6 0x74 0x20 read-write 0x00000000 PA peripheral address It contains the base address of the peripheral data register from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory destination address if DIR = 1 and the memory source address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral destination address DIR = 1 and the peripheral source address if DIR = 0. 0 32 CM0AR6 CM0AR6 0x78 0x20 read-write 0x00000000 MA peripheral address It contains the base address of the memory from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory source address if DIR = 1 and the memory destination address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral source address DIR = 1 and the peripheral destination address if DIR = 0. 0 32 CBSR6 CBSR6 0x7c 0x20 read-write 0x00000000 RSVD 8 24 BS burst size in non-m2m mode When BS>1, DMA will transfer for BS times for each request if left NDT is larger than BS, or else transfer for left NDT times. When BS=0 or 1, DMA will always do single transfer for each request. In memory-to-memory mode, BS is ignored. 0 8 CCR7 CCR7 0x80 0x20 read-write 0x00000000 RSVD 15 17 MEM2MEM memory-to-memory mode 0: disabled 1: enabled 14 1 PL priority level 00: low 01: medium 10: high 11: very high 12 2 MSIZE memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved 10 2 PSIZE peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved 8 2 MINC memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 0: disabled 1: enabled 7 1 PINC peripheral increment mode Defines the increment mode for each DMA transfer to the identified peripheral. n memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 0: disabled 1: enabled 6 1 CIRC circular mode 0: disabled 1: enabled 5 1 DIR data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. 0: read from peripheral Source attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. Destination attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode. 1: read from memory Destination attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. Source attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode. 4 1 TEIE transfer error interrupt enable 0: disabled 1: enabled 3 1 HTIE half transfer interrupt enable 0: disabled 1: enabled 2 1 TCIE transfer complete interrupt enable 0: disabled 1: enabled 1 1 EN channel enable When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the ISR register is cleared (by setting the CTEIFx bit of the IFCR register). 0: disabled 1: enabled 0 1 CNDTR7 CNDTR7 0x84 0x20 read-write 0x00000000 RSVD 16 16 NDT number of data to transfer (0 to 2^16 - 1) This field is updated by hardware when the channel is enabled: It is decremented after each single DMA 'read followed by write' transfer, indicating the remaining amount of data items to transfer. It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC = 0 in the CCRx register). It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC = 1). If this field is zero, no transfer can be served whatever the channel status (enabled or not). 0 16 CPAR7 CPAR7 0x88 0x20 read-write 0x00000000 PA peripheral address It contains the base address of the peripheral data register from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory destination address if DIR = 1 and the memory source address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral destination address DIR = 1 and the peripheral source address if DIR = 0. 0 32 CM0AR7 CM0AR7 0x8c 0x20 read-write 0x00000000 MA peripheral address It contains the base address of the memory from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory source address if DIR = 1 and the memory destination address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral source address DIR = 1 and the peripheral destination address if DIR = 0. 0 32 CBSR7 CBSR7 0x90 0x20 read-write 0x00000000 RSVD 8 24 BS burst size in non memory-to-memory mode When BS>1, DMA will transfer for BS times for each request if left NDT is larger than BS, or else transfer for left NDT times. When BS=0 or 1, DMA will always do single transfer for each request. In memory-to-memory mode, BS is ignored. 0 8 CCR8 CCR8 0x94 0x20 read-write 0x00000000 RSVD 15 17 MEM2MEM memory-to-memory mode 0: disabled 1: enabled 14 1 PL priority level 00: low 01: medium 10: high 11: very high 12 2 MSIZE memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved 10 2 PSIZE peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved 8 2 MINC memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. 0: disabled 1: enabled 7 1 PINC peripheral increment mode Defines the increment mode for each DMA transfer to the identified peripheral. n memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. 0: disabled 1: enabled 6 1 CIRC circular mode 0: disabled 1: enabled 5 1 DIR data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. 0: read from peripheral Source attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. Destination attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode. 1: read from memory Destination attributes are defined by PSIZE and PINC, plus the CPARx register. This is still valid in a memory-to-memory mode. Source attributes are defined by MSIZE and MINC, plus the CM0ARx register. This is still valid in a peripheral-to-peripheral mode. 4 1 TEIE transfer error interrupt enable 0: disabled 1: enabled 3 1 HTIE half transfer interrupt enable 0: disabled 1: enabled 2 1 TCIE transfer complete interrupt enable 0: disabled 1: enabled 1 1 EN channel enable When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the ISR register is cleared (by setting the CTEIFx bit of the IFCR register). 0: disabled 1: enabled 0 1 CNDTR8 CNDTR8 0x98 0x20 read-write 0x00000000 RSVD 16 16 NDT number of data to transfer (0 to 2^16 - 1) This field is updated by hardware when the channel is enabled: It is decremented after each single DMA 'read followed by write' transfer, indicating the remaining amount of data items to transfer. It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC = 0 in the CCRx register). It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC = 1). If this field is zero, no transfer can be served whatever the channel status (enabled or not). 0 16 CPAR8 CPAR8 0x9c 0x20 read-write 0x00000000 PA peripheral address It contains the base address of the peripheral data register from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory destination address if DIR = 1 and the memory source address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral destination address DIR = 1 and the peripheral source address if DIR = 0. 0 32 CM0AR8 CM0AR8 0xa0 0x20 read-write 0x00000000 MA peripheral address It contains the base address of the memory from/to which the data will be read/written. In memory-to-memory mode, this register identifies the memory source address if DIR = 1 and the memory destination address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral source address DIR = 1 and the peripheral destination address if DIR = 0. 0 32 CBSR8 CBSR8 0xa4 0x20 read-write 0x00000000 RSVD 8 24 BS burst size in non-m2m mode When BS>1, DMA will transfer for BS times for each request if left NDT is larger than BS, or else transfer for left NDT times. When BS=0 or 1, DMA will always do single transfer for each request. In memory-to-memory mode, BS is ignored. 0 8 CSELR1 CSELR1 0xa8 0x20 read-write 0x00000000 RSVD 30 2 C4S DMA channel 4 selection 24 6 RSVD2 22 2 C3S DMA channel 3 selection 16 6 RSVD3 14 2 C2S DMA channel 2 selection 8 6 RSVD4 6 2 C1S DMA channel 1 selection 0 6 CSELR2 CSELR2 0xac 0x20 read-write 0x00000000 RSVD 30 2 C8S DMA channel 8 selection 24 6 RSVD2 22 2 C7S DMA channel 7 selection 16 6 RSVD3 14 2 C6S DMA channel 6 selection 8 6 RSVD4 6 2 C5S DMA channel 5 selection 0 6 LPSYS_PINMUX LPSYS_PINMUX 0x40003000 0x0 0x1000 registers PAD_PB00 PAD_PB00 0x0 0x20 read-write 0x0 RSVD 12 20 POE Reserved. Always set to logic LOW 11 1 DS1 Drive Select 1. Used to select output drive strength 10 1 DS0 Drive Select 0. Used to select output drive strength 9 1 SR Slew Rate. Logic HIGH selects slow slew rate, logic LOW selects fast slew rate 8 1 IS Input Select. Logic LOW selects CMOS input, logic HIGH selects Schmitt input 7 1 IE Input Enable. Logic HIGH enables the input buffer 6 1 PS Pull Select. Logic HIGH selects pull-up, logic LOW select pull-down 5 1 PE Pull Enable. Logic HIGH enables week pull device 4 1 RSVD2 3 1 FSEL Function Select 0 3 PAD_PB01 PAD_PB01 0x4 0x20 read-write 0x0 RSVD 12 20 POE Reserved. Always set to logic LOW 11 1 DS1 Drive Select 1. Used to select output drive strength 10 1 DS0 Drive Select 0. Used to select output drive strength 9 1 SR Slew Rate. Logic HIGH selects slow slew rate, logic LOW selects fast slew rate 8 1 IS Input Select. Logic LOW selects CMOS input, logic HIGH selects Schmitt input 7 1 IE Input Enable. Logic HIGH enables the input buffer 6 1 PS Pull Select. Logic HIGH selects pull-up, logic LOW select pull-down 5 1 PE Pull Enable. Logic HIGH enables week pull device 4 1 RSVD2 3 1 FSEL Function Select 0 3 PAD_PB02 PAD_PB02 0x8 0x20 read-write 0x0 RSVD 12 20 POE Reserved. Always set to logic LOW 11 1 DS1 Drive Select 1. Used to select output drive strength 10 1 DS0 Drive Select 0. Used to select output drive strength 9 1 SR Slew Rate. Logic HIGH selects slow slew rate, logic LOW selects fast slew rate 8 1 IS Input Select. Logic LOW selects CMOS input, logic HIGH selects Schmitt input 7 1 IE Input Enable. Logic HIGH enables the input buffer 6 1 PS Pull Select. Logic HIGH selects pull-up, logic LOW select pull-down 5 1 PE Pull Enable. Logic HIGH enables week pull device 4 1 RSVD2 3 1 FSEL Function Select 0 3 PAD_PB03 PAD_PB03 0xc 0x20 read-write 0x0 RSVD 12 20 POE Reserved. Always set to logic LOW 11 1 DS1 Drive Select 1. Used to select output drive strength 10 1 DS0 Drive Select 0. Used to select output drive strength 9 1 SR Slew Rate. Logic HIGH selects slow slew rate, logic LOW selects fast slew rate 8 1 IS Input Select. Logic LOW selects CMOS input, logic HIGH selects Schmitt input 7 1 IE Input Enable. Logic HIGH enables the input buffer 6 1 PS Pull Select. Logic HIGH selects pull-up, logic LOW select pull-down 5 1 PE Pull Enable. Logic HIGH enables week pull device 4 1 RSVD2 3 1 FSEL Function Select 0 3 USART4 USART 0x40005000 0x0 0x1000 registers CR1 CR1 Control Register 1 0x00 0x20 read-write 0x00000000 RSVD 29 3 M Mode bit indicates the length of the packet, including data bits and parity. Stop bits not included. 0: 6 bits (e.g. 6 data bits + no parity bit) 1: 7 bits (e.g. 6 data bits + 1 parity bit) 2: 8 bits (e.g. 7 data bits + 1 parity bit, or 6 data bits + 2 parity bits) 3: 9 bits (e.g. 8 data bits + 1 parity bit, or 7 data bits + 2 parity bits) 27 2 RSVD2 26 1 RSVD3 25 1 RSVD4 20 5 RSVD5 15 5 OVER8 Oversampling mode 0: Oversampling by 16 1: Oversampling by 8 14 1 RSVD6 13 1 RSVD7 12 1 RSVD8 11 1 PCE Parity check enable. If enabled, parity bit is inserted at the MSB position 0: parity check disabled 1: parity check enabled 10 1 PS Parity select 0: even parity 1: odd parity 9 1 PEIE Parity error interrupt enable 0: interrupt disabled 1: interrupt is generated whenever PE=1 in the ISR register 8 1 TXEIE Tx empty interrupt enable 0: interrupt disabled 1: interrupt is generated whenver TXE=1 in the ISR register 7 1 TCIE Transfer compelete interrupt enable 0: interrupt disabled 1: interrupt is generated whenever TC=1 in the ISR register 6 1 RXNEIE Rx not empty interrupt enable 0: interrupt disabled 1: interrupt is generated whenever RXNE=1 in the ISR register 5 1 IDLEIE Idle line interrupt enable 0: interrupt disabled 1: interrupt is generated whenever IDLE=1 in the ISR register 4 1 TE Transmitter enable 0: transmitter is disabled 1: transmitter is enabled 3 1 RE Receiver enable 0: receiver is disabled 1: receiver is enabled 2 1 RSVD9 1 1 UE USART enable 0: disabled 1: enabled 0 1 CR2 CR2 Control Register 2 0x04 0x20 read-write 0x00000000 RSVD 24 8 RSVD2 23 1 RSVD3 21 2 RSVD4 20 1 RSVD5 19 1 RSVD6 18 1 RSVD7 17 1 RSVD8 16 1 RSVD9 15 1 RSVD10 14 1 STOP Stop bits 0/1: 1 stop bit 2/3: 2 stop bits 12 2 RSVD11 11 1 RSVD12 10 1 RSVD13 9 1 RSVD14 8 1 RSVD15 7 1 RSVD16 6 1 RSVD17 5 1 RSVD18 4 1 RSVD19 0 4 CR3 CR3 Control Register 3 0x08 0x20 read-write 0x00000000 RSVD 25 7 RSVD2 24 1 RSVD3 23 1 RSVD4 22 1 RSVD5 20 2 RSVD6 17 3 RSVD7 16 1 RSVD8 15 1 RSVD9 14 1 RSVD10 13 1 OVRDIS Overrun disable 0: overrun error flag (ORE) will be set if new data received but previous data not read. New data will not overwrite the content in RDR register. 1: overrun disabled. If new data is received before previous data is read, the new data will overwrite the content in RDR register and ORE flag remains unset. 12 1 ONEBIT One bit sampling mode 0: 3-bit sampling mode, the sampling value is determined by the voted result out of 3 bits 1: 1-bit sampling mode 11 1 CTSIE CTS interrupt enable 0: interrupt disabled 1: interrupt is generated whenever CTSIF=1 in the ISR register 10 1 CTSE CTS enable 0: CTS hardware flow control disabled 1: CTS hardware flow control enabled, data is transmitted only when CTS input is asserted low 9 1 RTSE RTS enable 0: RTS hardware flow control disabled 1: RTS hardware flow control enabled, RTS output is asserted low when new data can be received 8 1 DMAT Transmitter DMA enable 0: DMA mode disabled for transmission 1: DMA mode enabled for transmission 7 1 DMAR Receiver DMA enable 0: DMA mode disabled for reception 1: DMA mode enabled for reception 6 1 RSVD11 5 1 RSVD12 4 1 RSVD13 3 1 RSVD14 2 1 RSVD15 1 1 EIE Error interrupt enable 0: interrupt disabled 1: interrupt is generated whenever FE=1 or ORE=1 or NF=1 in the ISR register 0 1 BRR BRR Baud Rate Register 0x0c 0x20 read-write 0x00000000 RSVD 16 16 INT Integer part of baud rate prescaler If OVER8 = 0, Baud Rate = 48000000 / (INT + FRAC/16) / 16 If OVER8 = 1, Baud Rate = 48000000 / (INT + FRAC/16) / 8 For example: OVER=0, INT=3, FRAC=0, Baud Rate = 48000000/(3+0)/16 = 1Mbps OVER=0, INT=3, FRAC=4, Baud Rate = 48000000/(3+4/16)/16 = 923077 = 921600 + 1.6‰ OVER=1, INT=52, FRAC=1, Baud Rate = 48000000/(52+1/16)/8 = 115246 = 115200 + 0.4‰ 4 12 FRAC Fractional part of baud rate prescaler 0 4 RSVD1 RSVD1 0x10 0x20 read-write 0x0 RQR RQR Request Register 0x18 0x20 read-write 0x00000000 RSVD 5 27 TXFRQ Tx data flush requestReserved-Do not modify 4 1 RXFRQ Rx data flush request. Write 1 to clear the RXNE flag and discard the current data in RDR 3 1 RSVD2 2 1 RSVD3 1 1 RSVD4 0 1 ISR ISR Interrupt and Status Register 0x1c 0x20 read-write 0x020000C0 RSVD 26 6 RSVD2 25 1 RSVD3 23 2 RSVD4 22 1 RSVD5 21 1 RSVD6 20 1 RSVD7 19 1 RSVD8 18 1 RSVD9 17 1 RSVD10 16 1 RSVD11 15 1 RSVD12 14 1 RSVD13 13 1 RSVD14 12 1 RSVD15 11 1 CTS CTS input. Read this bit to get the raw status of the CTS line. 10 1 CTSIF CTS interrupt flag. This bit is set by hardware whenever CTS input toggles. 0: no change on the CTS line 1: there is a change on the CTS line 9 1 RSVD16 8 1 TXE Tx data empty 0: data is ready in TDR 1: data is already transferred to shift register, i.e. transmission is in progress or complete 7 1 TC transmission complete. This bit is set by hardware if the transmission is complete 0: transmission is not complete 1: transmission is complete 6 1 RXNE Rx data not empty. This bit is set by hardware when the received data is transferred into RDR register. 0: data is not received 1: data is ready in RDR to be read 5 1 IDLE Idle line detected 0: no idle line is detected 1: idle line is detected 4 1 ORE Overrun error. When new data is received but Rx buffer is not empty (i.e. previous data is not read yet), ORE is asserted and current RDR content is not lost. This feature can be disabled by set CR3_OVRDIS to 1. 0: no overrun error 1: overrun error is detected 3 1 NF Noise flag. Noise means the samping values in the 3-bit sampling mode are not the same. 0: no noise is detected 1: noise is detected 2 1 FE Framing error. This bit is set by hardware when stop bit is not correctly received 0: no framing error is detected 1: framing error is detected 1 1 PE Parity error. This bit is set when a parity error is detected in the received packet. 0: no parity error 1: parity error detected 0 1 ICR ICR Interrupt flag Clear Register 0x20 0x20 read-write 0x00000000 RSVD 21 11 RSVD2 20 1 RSVD3 18 2 RSVD4 17 1 RSVD5 13 4 RSVD6 12 1 RSVD7 11 1 RSVD8 10 1 CTSCF CTS clear flag. Writing 1 to this bit clears the CTSIF flag in the ISR register. 9 1 RSVD9 8 1 RSVD10 7 1 TCCF Transmission complete clear flag. Writing 1 to this bit clears the TC flag in the ISR register. 6 1 RSVD11 5 1 IDLECF Idle line detected clear flag. Writing 1 to this bit clears the IDLECF flag in the ISR register. 4 1 ORECF Overrun error clear flag. Writing 1 to this bit clears the ORE flag in the ISR register. 3 1 NCF Noise detected clear flag. Writing 1 to this bit clears the NF flag in the ISR register. 2 1 FECF Framing error clear flag. Writing 1 to this bit clears the FE flag in the ISR register. 1 1 PECF Parity error clear flag. Wriring 1 to this bit clears the PE flag in the ISR register. 0 1 RDR RDR Receive Data Register 0x24 0x20 read-write 0x00000000 RSVD 9 23 RDR Received data 0 9 TDR TDR Transmit Data Register 0x28 0x20 read-write 0x00000000 RSVD 9 23 TDR Transmit data 0 9 MISCR MISCR Miscellaneous Register 0x2c 0x20 read-write 0x00000000 AUTOCAL 31 1 RSVD 8 23 RTSBIT assert RTS ahead of the frame completion (in number of bits)Reserved-Do not modify 4 4 SMPLINI initial sample count, count down from this value to zero to reach the middle of the start bit in RxReserved-Do not modify 0 4 DRDR DRDR Debug Receive Data Register 0x30 0x20 read-write 0x00000000 DATA 0 32 DTDR DTDR Debug Receive Data Register 0x34 0x20 read-write 0x00000000 DATA 0 32 EXR EXR Mutual Exclusive Register 0x38 0x20 read-write 0x00000001 RSVD 5 27 ID 4 1 RSVD2 1 3 BUSY 0 1 USART5 USART 0x40006000 0x0 0x1000 registers CR1 CR1 Control Register 1 0x00 0x20 read-write 0x00000000 RSVD 29 3 M Mode bit indicates the length of the packet, including data bits and parity. Stop bits not included. 0: 6 bits (e.g. 6 data bits + no parity bit) 1: 7 bits (e.g. 6 data bits + 1 parity bit) 2: 8 bits (e.g. 7 data bits + 1 parity bit, or 6 data bits + 2 parity bits) 3: 9 bits (e.g. 8 data bits + 1 parity bit, or 7 data bits + 2 parity bits) 27 2 RSVD2 26 1 RSVD3 25 1 RSVD4 20 5 RSVD5 15 5 OVER8 Oversampling mode 0: Oversampling by 16 1: Oversampling by 8 14 1 RSVD6 13 1 RSVD7 12 1 RSVD8 11 1 PCE Parity check enable. If enabled, parity bit is inserted at the MSB position 0: parity check disabled 1: parity check enabled 10 1 PS Parity select 0: even parity 1: odd parity 9 1 PEIE Parity error interrupt enable 0: interrupt disabled 1: interrupt is generated whenever PE=1 in the ISR register 8 1 TXEIE Tx empty interrupt enable 0: interrupt disabled 1: interrupt is generated whenver TXE=1 in the ISR register 7 1 TCIE Transfer compelete interrupt enable 0: interrupt disabled 1: interrupt is generated whenever TC=1 in the ISR register 6 1 RXNEIE Rx not empty interrupt enable 0: interrupt disabled 1: interrupt is generated whenever RXNE=1 in the ISR register 5 1 IDLEIE Idle line interrupt enable 0: interrupt disabled 1: interrupt is generated whenever IDLE=1 in the ISR register 4 1 TE Transmitter enable 0: transmitter is disabled 1: transmitter is enabled 3 1 RE Receiver enable 0: receiver is disabled 1: receiver is enabled 2 1 RSVD9 1 1 UE USART enable 0: disabled 1: enabled 0 1 CR2 CR2 Control Register 2 0x04 0x20 read-write 0x00000000 RSVD 24 8 RSVD2 23 1 RSVD3 21 2 RSVD4 20 1 RSVD5 19 1 RSVD6 18 1 RSVD7 17 1 RSVD8 16 1 RSVD9 15 1 RSVD10 14 1 STOP Stop bits 0/1: 1 stop bit 2/3: 2 stop bits 12 2 RSVD11 11 1 RSVD12 10 1 RSVD13 9 1 RSVD14 8 1 RSVD15 7 1 RSVD16 6 1 RSVD17 5 1 RSVD18 4 1 RSVD19 0 4 CR3 CR3 Control Register 3 0x08 0x20 read-write 0x00000000 RSVD 25 7 RSVD2 24 1 RSVD3 23 1 RSVD4 22 1 RSVD5 20 2 RSVD6 17 3 RSVD7 16 1 RSVD8 15 1 RSVD9 14 1 RSVD10 13 1 OVRDIS Overrun disable 0: overrun error flag (ORE) will be set if new data received but previous data not read. New data will not overwrite the content in RDR register. 1: overrun disabled. If new data is received before previous data is read, the new data will overwrite the content in RDR register and ORE flag remains unset. 12 1 ONEBIT One bit sampling mode 0: 3-bit sampling mode, the sampling value is determined by the voted result out of 3 bits 1: 1-bit sampling mode 11 1 CTSIE CTS interrupt enable 0: interrupt disabled 1: interrupt is generated whenever CTSIF=1 in the ISR register 10 1 CTSE CTS enable 0: CTS hardware flow control disabled 1: CTS hardware flow control enabled, data is transmitted only when CTS input is asserted low 9 1 RTSE RTS enable 0: RTS hardware flow control disabled 1: RTS hardware flow control enabled, RTS output is asserted low when new data can be received 8 1 DMAT Transmitter DMA enable 0: DMA mode disabled for transmission 1: DMA mode enabled for transmission 7 1 DMAR Receiver DMA enable 0: DMA mode disabled for reception 1: DMA mode enabled for reception 6 1 RSVD11 5 1 RSVD12 4 1 RSVD13 3 1 RSVD14 2 1 RSVD15 1 1 EIE Error interrupt enable 0: interrupt disabled 1: interrupt is generated whenever FE=1 or ORE=1 or NF=1 in the ISR register 0 1 BRR BRR Baud Rate Register 0x0c 0x20 read-write 0x00000000 RSVD 16 16 INT Integer part of baud rate prescaler If OVER8 = 0, Baud Rate = 48000000 / (INT + FRAC/16) / 16 If OVER8 = 1, Baud Rate = 48000000 / (INT + FRAC/16) / 8 For example: OVER=0, INT=3, FRAC=0, Baud Rate = 48000000/(3+0)/16 = 1Mbps OVER=0, INT=3, FRAC=4, Baud Rate = 48000000/(3+4/16)/16 = 923077 = 921600 + 1.6‰ OVER=1, INT=52, FRAC=1, Baud Rate = 48000000/(52+1/16)/8 = 115246 = 115200 + 0.4‰ 4 12 FRAC Fractional part of baud rate prescaler 0 4 RSVD1 RSVD1 0x10 0x20 read-write 0x0 RQR RQR Request Register 0x18 0x20 read-write 0x00000000 RSVD 5 27 TXFRQ Tx data flush requestReserved-Do not modify 4 1 RXFRQ Rx data flush request. Write 1 to clear the RXNE flag and discard the current data in RDR 3 1 RSVD2 2 1 RSVD3 1 1 RSVD4 0 1 ISR ISR Interrupt and Status Register 0x1c 0x20 read-write 0x020000C0 RSVD 26 6 RSVD2 25 1 RSVD3 23 2 RSVD4 22 1 RSVD5 21 1 RSVD6 20 1 RSVD7 19 1 RSVD8 18 1 RSVD9 17 1 RSVD10 16 1 RSVD11 15 1 RSVD12 14 1 RSVD13 13 1 RSVD14 12 1 RSVD15 11 1 CTS CTS input. Read this bit to get the raw status of the CTS line. 10 1 CTSIF CTS interrupt flag. This bit is set by hardware whenever CTS input toggles. 0: no change on the CTS line 1: there is a change on the CTS line 9 1 RSVD16 8 1 TXE Tx data empty 0: data is ready in TDR 1: data is already transferred to shift register, i.e. transmission is in progress or complete 7 1 TC transmission complete. This bit is set by hardware if the transmission is complete 0: transmission is not complete 1: transmission is complete 6 1 RXNE Rx data not empty. This bit is set by hardware when the received data is transferred into RDR register. 0: data is not received 1: data is ready in RDR to be read 5 1 IDLE Idle line detected 0: no idle line is detected 1: idle line is detected 4 1 ORE Overrun error. When new data is received but Rx buffer is not empty (i.e. previous data is not read yet), ORE is asserted and current RDR content is not lost. This feature can be disabled by set CR3_OVRDIS to 1. 0: no overrun error 1: overrun error is detected 3 1 NF Noise flag. Noise means the samping values in the 3-bit sampling mode are not the same. 0: no noise is detected 1: noise is detected 2 1 FE Framing error. This bit is set by hardware when stop bit is not correctly received 0: no framing error is detected 1: framing error is detected 1 1 PE Parity error. This bit is set when a parity error is detected in the received packet. 0: no parity error 1: parity error detected 0 1 ICR ICR Interrupt flag Clear Register 0x20 0x20 read-write 0x00000000 RSVD 21 11 RSVD2 20 1 RSVD3 18 2 RSVD4 17 1 RSVD5 13 4 RSVD6 12 1 RSVD7 11 1 RSVD8 10 1 CTSCF CTS clear flag. Writing 1 to this bit clears the CTSIF flag in the ISR register. 9 1 RSVD9 8 1 RSVD10 7 1 TCCF Transmission complete clear flag. Writing 1 to this bit clears the TC flag in the ISR register. 6 1 RSVD11 5 1 IDLECF Idle line detected clear flag. Writing 1 to this bit clears the IDLECF flag in the ISR register. 4 1 ORECF Overrun error clear flag. Writing 1 to this bit clears the ORE flag in the ISR register. 3 1 NCF Noise detected clear flag. Writing 1 to this bit clears the NF flag in the ISR register. 2 1 FECF Framing error clear flag. Writing 1 to this bit clears the FE flag in the ISR register. 1 1 PECF Parity error clear flag. Wriring 1 to this bit clears the PE flag in the ISR register. 0 1 RDR RDR Receive Data Register 0x24 0x20 read-write 0x00000000 RSVD 9 23 RDR Received data 0 9 TDR TDR Transmit Data Register 0x28 0x20 read-write 0x00000000 RSVD 9 23 TDR Transmit data 0 9 MISCR MISCR Miscellaneous Register 0x2c 0x20 read-write 0x00000000 AUTOCAL 31 1 RSVD 8 23 RTSBIT assert RTS ahead of the frame completion (in number of bits)Reserved-Do not modify 4 4 SMPLINI initial sample count, count down from this value to zero to reach the middle of the start bit in RxReserved-Do not modify 0 4 DRDR DRDR Debug Receive Data Register 0x30 0x20 read-write 0x00000000 DATA 0 32 DTDR DTDR Debug Receive Data Register 0x34 0x20 read-write 0x00000000 DATA 0 32 EXR EXR Mutual Exclusive Register 0x38 0x20 read-write 0x00000001 RSVD 5 27 ID 4 1 RSVD2 1 3 BUSY 0 1 BTIM3 BTIM 0x40009000 0x0 0x1000 registers CR1 CR1 TIM control register 1 0x00 0x20 read-write 0x00000000 RSVD 8 24 ARPE Auto-reload preload enable 0: ARR register is not buffered 1: ARR register is buffered 7 1 RSVD2 4 3 OPM One-pulse mode 0: Counter is not stopped at update event 1: Counter stops counting at the next update event (clearing the bit CEN) 3 1 URS Update request source This bit is set and cleared by software to select the UEV event sources. 0: Any of the following events generate an update interrupt or DMA request if enabled. These events can be: Counter overflow Setting the UG bit Update generation through the slave mode controller 1: Only counter overflow generates an update interrupt or DMA request if enabled. 2 1 UDIS Update disable This bit is set and cleared by software to enable/disable UEV event generation. 0: UEV enabled. The Update (UEV) event is generated by one of the following events: Counter overflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values. 1: UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller. 1 1 CEN Counter enable 0: Counter disabled 1: Counter enabled Note: Gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. CEN is cleared automatically in one-pulse mode, when an update event occurs. 0 1 CR2 CR2 TIM control register 2 0x04 0x20 read-write 0x00000000 RSVD 6 26 MMS Master mode selection These bits allow to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: 00: Reset:the UG bit from the EGR register is used as trigger output (TRGO). If the reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on TRGO is delayed compared to the actual reset. 01: Enable :the Counter enable signal, CNT_EN, is used as trigger output (TRGO). It is useful to start several timers at the same time or to control a window in which a slave timer is enabled. The Counter Enable signal is generated by a logic OR between CEN control bit and the trigger input when configured in gated mode. When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in SMCR register). 10: Update:The update event is selected as trigger output (TRGO). For instance a master timer can then be used as a prescaler for a slave timer. 11: Gating:The delayed gating trigger is selected as trigger output (TRGO). 4 2 RSVD2 0 4 SMCR SMCR TIM slave mode control register 0x08 0x20 read-write 0x00000000 RSVD 24 8 GM Gated Mode. The counter clock is enabled when the selected trigger input (TRGI) is active (according to gating trigger polarity). The counter stops (but is not reset) as soon as the trigger becomes inactive. Both start and stop of the counter are controlled. Gated mode and slave mode can be enabled simutanuously with different trigger selection. 23 1 GTP Gating trigger polarity invert 0: active at high level 1: active at low level 22 1 GTS Gating trigger selection in gated mode This bit-field selects the trigger input to be used to enable the counter gating. 00: Internal Trigger 0 (ITR0) 01: Internal Trigger 1 (ITR1) 10: Internal Trigger 2 (ITR2) 11: Internal Trigger 3 (ITR3) 20 2 RSVD2 19 1 SMS Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input. 000: Slave mode disabled. 001: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers. 010: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled. 011: Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter. 100: External Clock Mode - Rising edges of the selected trigger (TRGI) clock the counter. 16 3 RSVD3 8 8 MSM Master/Slave mode. This bit should be asserted on master timer if synchronization if needed. 0: No action 1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event. 7 1 RSVD4 6 1 TS Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. 00: Internal Trigger 0 (ITR0) 01: Internal Trigger 1 (ITR1) 10: Internal Trigger 2 (ITR2) 11: Internal Trigger 3 (ITR3) 4 2 RSVD5 0 4 DIER DIER TIM DMA/Interrupt enable register 0x0c 0x20 read-write 0x00000000 RSVD 9 23 UDE Update DMA request enable 0: Update DMA request disabled. 1: Update DMA request enabled 8 1 RSVD2 1 7 UIE Update interrupt enable 0: Update interrupt disabled. 1: Update interrupt enabled 0 1 SR SR TIM status register 0x10 0x20 read-write 0x00000000 RSVD 1 31 UIF Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. 0: No update occurred 1: Update interrupt pending. This bit is set by hardware when the registers are updated: At overflow and if UDIS=0 in the CR1 register. When CNT is reinitialized by software using the UG bit in EGR register, if URS=0 and UDIS=0 in the CR1 register. When CNT is reinitialized by a trigger event (refer to the synchro control register description), if URS=0 and UDIS=0 in the CR1 register. 0 1 EGR EGR Event generation register 0x14 0x20 read-write 0x00000000 RSVD 1 31 UG Update generation This bit can be set by software, it is automatically cleared by hardware. 0: No action 1: Re-initialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected). The counter is cleared if the center-aligned mode is selected or if DIR=0 (upcounting), else it takes the auto-reload value (ARR) if DIR=1 (downcounting). 0 1 RSVD1 RSVD1 0x18 0x20 read-write 0x0 CNT CNT Counter 0x24 0x20 read-write 0x00000000 CNT counter value 0 32 PSC PSC Prescaler 0x28 0x20 read-write 0x00000000 RSVD 16 16 PSC Prescaler value The counter clock frequency is equal to fCLK / (PSC[15:0] + 1). PSC contains the value to be loaded in the active prescaler register at each update event (including when the counter is cleared through UG bit of EGR register or through trigger controller when configured in "reset mode"). 0 16 ARR ARR Auto-reload register 0x2c 0x20 read-write 0x00000000 ARR Auto-reload value ARR is the value to be loaded in the actual auto-reload register. The counter is blocked while the auto-reload value is null. 0 32 BTIM4 BTIM 0x4000a000 0x0 0x1000 registers CR1 CR1 TIM control register 1 0x00 0x20 read-write 0x00000000 RSVD 8 24 ARPE Auto-reload preload enable 0: ARR register is not buffered 1: ARR register is buffered 7 1 RSVD2 4 3 OPM One-pulse mode 0: Counter is not stopped at update event 1: Counter stops counting at the next update event (clearing the bit CEN) 3 1 URS Update request source This bit is set and cleared by software to select the UEV event sources. 0: Any of the following events generate an update interrupt or DMA request if enabled. These events can be: Counter overflow Setting the UG bit Update generation through the slave mode controller 1: Only counter overflow generates an update interrupt or DMA request if enabled. 2 1 UDIS Update disable This bit is set and cleared by software to enable/disable UEV event generation. 0: UEV enabled. The Update (UEV) event is generated by one of the following events: Counter overflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values. 1: UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller. 1 1 CEN Counter enable 0: Counter disabled 1: Counter enabled Note: Gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. CEN is cleared automatically in one-pulse mode, when an update event occurs. 0 1 CR2 CR2 TIM control register 2 0x04 0x20 read-write 0x00000000 RSVD 6 26 MMS Master mode selection These bits allow to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: 00: Reset:the UG bit from the EGR register is used as trigger output (TRGO). If the reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on TRGO is delayed compared to the actual reset. 01: Enable :the Counter enable signal, CNT_EN, is used as trigger output (TRGO). It is useful to start several timers at the same time or to control a window in which a slave timer is enabled. The Counter Enable signal is generated by a logic OR between CEN control bit and the trigger input when configured in gated mode. When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in SMCR register). 10: Update:The update event is selected as trigger output (TRGO). For instance a master timer can then be used as a prescaler for a slave timer. 11: Gating:The delayed gating trigger is selected as trigger output (TRGO). 4 2 RSVD2 0 4 SMCR SMCR TIM slave mode control register 0x08 0x20 read-write 0x00000000 RSVD 24 8 GM Gated Mode. The counter clock is enabled when the selected trigger input (TRGI) is active (according to gating trigger polarity). The counter stops (but is not reset) as soon as the trigger becomes inactive. Both start and stop of the counter are controlled. Gated mode and slave mode can be enabled simutanuously with different trigger selection. 23 1 GTP Gating trigger polarity invert 0: active at high level 1: active at low level 22 1 GTS Gating trigger selection in gated mode This bit-field selects the trigger input to be used to enable the counter gating. 00: Internal Trigger 0 (ITR0) 01: Internal Trigger 1 (ITR1) 10: Internal Trigger 2 (ITR2) 11: Internal Trigger 3 (ITR3) 20 2 RSVD2 19 1 SMS Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input. 000: Slave mode disabled. 001: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers. 010: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled. 011: Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter. 100: External Clock Mode - Rising edges of the selected trigger (TRGI) clock the counter. 16 3 RSVD3 8 8 MSM Master/Slave mode. This bit should be asserted on master timer if synchronization if needed. 0: No action 1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event. 7 1 RSVD4 6 1 TS Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. 00: Internal Trigger 0 (ITR0) 01: Internal Trigger 1 (ITR1) 10: Internal Trigger 2 (ITR2) 11: Internal Trigger 3 (ITR3) 4 2 RSVD5 0 4 DIER DIER TIM DMA/Interrupt enable register 0x0c 0x20 read-write 0x00000000 RSVD 9 23 UDE Update DMA request enable 0: Update DMA request disabled. 1: Update DMA request enabled 8 1 RSVD2 1 7 UIE Update interrupt enable 0: Update interrupt disabled. 1: Update interrupt enabled 0 1 SR SR TIM status register 0x10 0x20 read-write 0x00000000 RSVD 1 31 UIF Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. 0: No update occurred 1: Update interrupt pending. This bit is set by hardware when the registers are updated: At overflow and if UDIS=0 in the CR1 register. When CNT is reinitialized by software using the UG bit in EGR register, if URS=0 and UDIS=0 in the CR1 register. When CNT is reinitialized by a trigger event (refer to the synchro control register description), if URS=0 and UDIS=0 in the CR1 register. 0 1 EGR EGR Event generation register 0x14 0x20 read-write 0x00000000 RSVD 1 31 UG Update generation This bit can be set by software, it is automatically cleared by hardware. 0: No action 1: Re-initialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected). The counter is cleared if the center-aligned mode is selected or if DIR=0 (upcounting), else it takes the auto-reload value (ARR) if DIR=1 (downcounting). 0 1 RSVD1 RSVD1 0x18 0x20 read-write 0x0 CNT CNT Counter 0x24 0x20 read-write 0x00000000 CNT counter value 0 32 PSC PSC Prescaler 0x28 0x20 read-write 0x00000000 RSVD 16 16 PSC Prescaler value The counter clock frequency is equal to fCLK / (PSC[15:0] + 1). PSC contains the value to be loaded in the active prescaler register at each update event (including when the counter is cleared through UG bit of EGR register or through trigger controller when configured in "reset mode"). 0 16 ARR ARR Auto-reload register 0x2c 0x20 read-write 0x00000000 ARR Auto-reload value ARR is the value to be loaded in the actual auto-reload register. The counter is blocked while the auto-reload value is null. 0 32 WDT2 WDT 0x4000b000 0x0 0x1000 registers WDT_CVR0 WDT_CVR0 WatchDog Counter Value 0 0x00 0x20 read-write 0x0 RSVD 24 8 COUNT_VALUE_0 Count Value for 1st TimeOut 0 24 WDT_CVR1 WDT_CVR1 WatchDog Counter Value 1 0x04 0x20 read-write 0x0 RSVD 24 8 COUNT_VALUE_1 Count Value for 2nd TimeOut 0 24 WDT_CR WDT_CR WatchDog Control Register 0x08 0x20 read-write 0x0 RSVD 5 27 RESPONSE_MODE 0:reset only, 1:interrupt and reset 4 1 RSVD2 3 1 RESET_LENGTH reset pulse length in number of wdt clock cycles 0 3 WDT_CCR WDT_CCR WatchDog Counter Control Register 0x0c 0x20 read-write 0x0 RSVD 8 24 COUNTER_CONTROL SinglePulse /Write 8'h76 to restart, write8'h34 to stop, else do nothing 0 8 WDT_ICR WDT_ICR WatchDog Interrupt Clear Register 0x10 0x20 read-write 0x0 RSVD 1 31 INT_CLR SinglePulse /A pulse to clear interrupt 0 1 WDT_SR WDT_SR WatchDog Status Register 0x14 0x20 read-write 0x0 RSVD 2 30 WDT_ACTIVE Watchdog runs when 1, else 0 1 1 INT_ASSERT Interrupt assert when 1 0 1 WDT_WP WDT_WP WatchDog Write Protect Register 0x18 0x20 read-write 0x0 WRPT_ST 1 indicates write protect is active 31 1 WRPT write 0x58ab99fc generate write_protect, write 0x51ff8621 to release 0 31 WDT_FG WDT_FG WatchDog Flag Register 0x1c 0x20 read-write 0x0 RSVD 4 28 SYNC_FG 1 indicates one transition from system clk to wdt clk has complicated 3 1 SYNC_FG_CLR SinglePulse/A pulse to clear sync flag 2 1 RST_FG 1 indicates wdt has already reset system 1 1 RST_FG_CLR SinglePulse/A pulse to clear reset flag 0 1 PTC2 PTC 0x4000c000 0x0 0x1000 registers ISR ISR interrupt status register 0x00 0x20 read-write 0x00000000 RSVD 24 8 TEIF8 transfer error flag for task 8 23 1 TEIF7 transfer error flag for task 7 22 1 TEIF6 transfer error flag for task 6 21 1 TEIF5 transfer error flag for task 5 20 1 TEIF4 transfer error flag for task 4 19 1 TEIF3 transfer error flag for task 3 18 1 TEIF2 transfer error flag for task 2 17 1 TEIF1 transfer error flag for task 1 16 1 RSVD2 8 8 TCIF8 task complete interrupt flag for task 8 7 1 TCIF7 task complete interrupt flag for task 7 6 1 TCIF6 task complete interrupt flag for task 6 5 1 TCIF5 task complete interrupt flag for task 5 4 1 TCIF4 task complete interrupt flag for task 4 3 1 TCIF3 task complete interrupt flag for task 3 2 1 TCIF2 task complete interrupt flag for task 2 1 1 TCIF1 task complete interrupt flag for task 1 0 1 ICR ICR interrupt clear register 0x04 0x20 read-write 0x00000000 RSVD 17 15 CTEIF clear transfer error flag 16 1 RSVD2 8 8 CTCIF8 clear task complete interrupt flag for task 8 7 1 CTCIF7 clear task complete interrupt flag for task 7 6 1 CTCIF6 clear task complete interrupt flag for task 6 5 1 CTCIF5 clear task complete interrupt flag for task 5 4 1 CTCIF4 clear task complete interrupt flag for task 4 3 1 CTCIF3 clear task complete interrupt flag for task 3 2 1 CTCIF2 clear task complete interrupt flag for task 2 1 1 CTCIF1 clear task complete interrupt flag for task 1 0 1 IER IER interrupt enable register 0x08 0x20 read-write 0x00000000 RSVD 17 15 TEIE enable transfer error flag 16 1 RSVD2 8 8 TCIE8 enable task complete interrupt for task 8 7 1 TCIE7 enable task complete interrupt for task 7 6 1 TCIE6 enable task complete interrupt for task 6 5 1 TCIE5 enable task complete interrupt for task 5 4 1 TCIE4 enable task complete interrupt for task 4 3 1 TCIE3 enable task complete interrupt for task 3 2 1 TCIE2 enable task complete interrupt for task 2 1 1 TCIE1 enable task complete interrupt for task 1 0 1 RSVD2 RSVD2 0xC 0x20 read-write 0x0 TCR1 TCR1 task 1 control register 0x10 0x20 read-write 0x00000000 RSVD 24 8 REPIRQ repetition interrupt 0: interrupt will be generated after each operation 1: interrupt will be generated after operation for REP times 23 1 REPTRIG repetition trigger 0: ptc trigger will be generated after each operation 1: ptc trigger will be generated after operation for REP times 22 1 REPEN repetition enable 0: task will be triggerd no matter what value REP is 1: task will only be triggerd when REP is not 0 21 1 SWTRIG software trigger task will be triggerd at once after SWTRIG set. SWTRIG will be cleared automatically. 20 1 TRIGPOL trigger polarity 0: select positive edge of trigger 1: select negative edge of trigger 19 1 OP task operation 3'b000: direct write data 3'b100: read then XOR with data and write back 3'b101: read then OR with data and write back 3'b110: read then AND with data and write back 3'b111: read then add with data and write back 16 3 RSVD2 8 8 TRIGSEL select trigger source 0: task will only be triggered by SWTRIG others: task will be triggered by selected source or SWTRIG 0 8 TAR1 TAR1 task 1 address register 0x14 0x20 read-write 0x00000000 ADDR peripheral address to access to 0 32 TDR1 TDR1 task 1 data register 0x18 0x20 read-write 0x00000000 DATA data value for task operation 0 32 RCR1 RCR1 task 1 repetition and delay counter register 0x1c 0x20 read-write 0x00000000 DLY Delay time before task operation after triggered 0: no delay others: delay DLY HCLK cycles before task operation DLY is read as left delay time. DLY will be reloaded automatically after each operation. 16 16 RSVD 10 6 REP Repetition counter value if REPEN is 1, task will only be triggerd when REP is not 0. when REP is larger than 0, it will be decrease by 1 automatically each time task triggered. 0 10 TCR2 TCR2 0x20 0x20 read-write 0x00000000 RSVD 24 8 REPIRQ repetition interrupt 0: interrupt will be generated after each operation 1: interrupt will be generated after operation for REP times 23 1 REPTRIG repetition trigger 0: ptc trigger will be generated after each operation 1: ptc trigger will be generated after operation for REP times 22 1 REPEN repetition enable 0: task will be triggerd no matter what value REP is 1: task will only be triggerd when REP is not 0 21 1 SWTRIG software trigger task will be triggerd at once after SWTRIG set. SWTRIG will be cleared automatically. 20 1 TRIGPOL trigger polarity 0: select positive edge of trigger 1: select negative edge of trigger 19 1 OP task operation 3'b000: direct write data 3'b100: read then XOR with data and write back 3'b101: read then OR with data and write back 3'b110: read then AND with data and write back 3'b111: read then add with data and write back 16 3 RSVD2 8 8 TRIGSEL select trigger source 0 8 TAR2 TAR2 0x24 0x20 read-write 0x00000000 ADDR peripheral address to access to 0 32 TDR2 TDR2 0x28 0x20 read-write 0x00000000 DATA data value for task operation 0 32 RCR2 RCR2 task 2 repetition and delay counter register 0x2c 0x20 read-write 0x00000000 DLY Delay time before task operation after triggered 0: no delay others: delay DLY HCLK cycles before task operation DLY is read as left delay time. DLY will be reloaded automatically after each operation. 16 16 RSVD 10 6 REP Repetition counter value if REPEN is 1, task will only be triggerd when REP is not 0. when REP is larger than 0, it will be decrease by 1 automatically each time task triggered. 0 10 TCR3 TCR3 0x30 0x20 read-write 0x00000000 RSVD 24 8 REPIRQ repetition interrupt 0: interrupt will be generated after each operation 1: interrupt will be generated after operation for REP times 23 1 REPTRIG repetition trigger 0: ptc trigger will be generated after each operation 1: ptc trigger will be generated after operation for REP times 22 1 REPEN repetition enable 0: task will be triggerd no matter what value REP is 1: task will only be triggerd when REP is not 0 21 1 SWTRIG software trigger task will be triggerd at once after SWTRIG set. SWTRIG will be cleared automatically. 20 1 TRIGPOL trigger polarity 0: select positive edge of trigger 1: select negative edge of trigger 19 1 OP task operation 3'b000: direct write data 3'b100: read then XOR with data and write back 3'b101: read then OR with data and write back 3'b110: read then AND with data and write back 3'b111: read then add with data and write back 16 3 RSVD2 8 8 TRIGSEL select trigger source 0 8 TAR3 TAR3 0x34 0x20 read-write 0x00000000 ADDR peripheral address to access to 0 32 TDR3 TDR3 0x38 0x20 read-write 0x00000000 DATA data value for task operation 0 32 RCR3 RCR3 task 3 repetition and delay counter register 0x3c 0x20 read-write 0x00000000 DLY Delay time before task operation after triggered 0: no delay others: delay DLY HCLK cycles before task operation DLY is read as left delay time. DLY will be reloaded automatically after each operation. 16 16 RSVD 10 6 REP Repetition counter value if REPEN is 1, task will only be triggerd when REP is not 0. when REP is larger than 0, it will be decrease by 1 automatically each time task triggered. 0 10 TCR4 TCR4 0x40 0x20 read-write 0x00000000 RSVD 24 8 REPIRQ repetition interrupt 0: interrupt will be generated after each operation 1: interrupt will be generated after operation for REP times 23 1 REPTRIG repetition trigger 0: ptc trigger will be generated after each operation 1: ptc trigger will be generated after operation for REP times 22 1 REPEN repetition enable 0: task will be triggerd no matter what value REP is 1: task will only be triggerd when REP is not 0 21 1 SWTRIG software trigger task will be triggerd at once after SWTRIG set. SWTRIG will be cleared automatically. 20 1 TRIGPOL trigger polarity 0: select positive edge of trigger 1: select negative edge of trigger 19 1 OP task operation 3'b000: direct write data 3'b100: read then XOR with data and write back 3'b101: read then OR with data and write back 3'b110: read then AND with data and write back 3'b111: read then add with data and write back 16 3 RSVD2 8 8 TRIGSEL select trigger source 0 8 TAR4 TAR4 0x44 0x20 read-write 0x00000000 ADDR peripheral address to access to 0 32 TDR4 TDR4 0x48 0x20 read-write 0x00000000 DATA data value for task operation 0 32 RCR4 RCR4 task 4 repetition and delay counter register 0x4c 0x20 read-write 0x00000000 DLY Delay time before task operation after triggered 0: no delay others: delay DLY HCLK cycles before task operation DLY is read as left delay time. DLY will be reloaded automatically after each operation. 16 16 RSVD 10 6 REP Repetition counter value if REPEN is 1, task will only be triggerd when REP is not 0. when REP is larger than 0, it will be decrease by 1 automatically each time task triggered. 0 10 TCR5 TCR5 0x50 0x20 read-write 0x00000000 RSVD 24 8 REPIRQ repetition interrupt 0: interrupt will be generated after each operation 1: interrupt will be generated after operation for REP times 23 1 REPTRIG repetition trigger 0: ptc trigger will be generated after each operation 1: ptc trigger will be generated after operation for REP times 22 1 REPEN repetition enable 0: task will be triggerd no matter what value REP is 1: task will only be triggerd when REP is not 0 21 1 SWTRIG software trigger task will be triggerd at once after SWTRIG set. SWTRIG will be cleared automatically. 20 1 TRIGPOL trigger polarity 0: select positive edge of trigger 1: select negative edge of trigger 19 1 OP task operation 3'b000: direct write data 3'b100: read then XOR with data and write back 3'b101: read then OR with data and write back 3'b110: read then AND with data and write back 3'b111: read then add with data and write back 16 3 RSVD2 8 8 TRIGSEL select trigger source 0 8 TAR5 TAR5 0x54 0x20 read-write 0x00000000 ADDR peripheral address to access to 0 32 TDR5 TDR5 0x58 0x20 read-write 0x00000000 DATA data value for task operation 0 32 RCR5 RCR5 task 5 repetition counter register 0x5c 0x20 read-write 0x00000000 RSVD 10 22 REP Repetition counter value if REPEN is 1, task will only be triggerd when REP is not 0. when REP is larger than 0, it will be decrease by 1 automatically each time task triggered. 0 10 TCR6 TCR6 0x60 0x20 read-write 0x00000000 RSVD 24 8 REPIRQ repetition interrupt 0: interrupt will be generated after each operation 1: interrupt will be generated after operation for REP times 23 1 REPTRIG repetition trigger 0: ptc trigger will be generated after each operation 1: ptc trigger will be generated after operation for REP times 22 1 REPEN repetition enable 0: task will be triggerd no matter what value REP is 1: task will only be triggerd when REP is not 0 21 1 SWTRIG software trigger task will be triggerd at once after SWTRIG set. SWTRIG will be cleared automatically. 20 1 TRIGPOL trigger polarity 0: select positive edge of trigger 1: select negative edge of trigger 19 1 OP task operation 3'b000: direct write data 3'b100: read then XOR with data and write back 3'b101: read then OR with data and write back 3'b110: read then AND with data and write back 3'b111: read then add with data and write back 16 3 RSVD2 8 8 TRIGSEL select trigger source 0 8 TAR6 TAR6 0x64 0x20 read-write 0x00000000 ADDR peripheral address to access to 0 32 TDR6 TDR6 0x68 0x20 read-write 0x00000000 DATA data value for task operation 0 32 RCR6 RCR6 task 6 repetition counter register 0x6c 0x20 read-write 0x00000000 RSVD 10 22 REP Repetition counter value if REPEN is 1, task will only be triggerd when REP is not 0. when REP is larger than 0, it will be decrease by 1 automatically each time task triggered. 0 10 TCR7 TCR7 0x70 0x20 read-write 0x00000000 RSVD 24 8 REPIRQ repetition interrupt 0: interrupt will be generated after each operation 1: interrupt will be generated after operation for REP times 23 1 REPTRIG repetition trigger 0: ptc trigger will be generated after each operation 1: ptc trigger will be generated after operation for REP times 22 1 REPEN repetition enable 0: task will be triggerd no matter what value REP is 1: task will only be triggerd when REP is not 0 21 1 SWTRIG software trigger task will be triggerd at once after SWTRIG set. SWTRIG will be cleared automatically. 20 1 TRIGPOL trigger polarity 0: select positive edge of trigger 1: select negative edge of trigger 19 1 OP task operation 3'b000: direct write data 3'b100: read then XOR with data and write back 3'b101: read then OR with data and write back 3'b110: read then AND with data and write back 3'b111: read then add with data and write back 16 3 RSVD2 8 8 TRIGSEL select trigger source 0 8 TAR7 TAR7 0x74 0x20 read-write 0x00000000 ADDR peripheral address to access to 0 32 TDR7 TDR7 0x78 0x20 read-write 0x00000000 DATA data value for task operation 0 32 RCR7 RCR7 task 7 repetition counter register 0x7c 0x20 read-write 0x00000000 RSVD 10 22 REP Repetition counter value if REPEN is 1, task will only be triggerd when REP is not 0. when REP is larger than 0, it will be decrease by 1 automatically each time task triggered. 0 10 TCR8 TCR8 0x80 0x20 read-write 0x00000000 RSVD 24 8 REPIRQ repetition interrupt 0: interrupt will be generated after each operation 1: interrupt will be generated after operation for REP times 23 1 REPTRIG repetition trigger 0: ptc trigger will be generated after each operation 1: ptc trigger will be generated after operation for REP times 22 1 REPEN repetition enable 0: task will be triggerd no matter what value REP is 1: task will only be triggerd when REP is not 0 21 1 SWTRIG software trigger task will be triggerd at once after SWTRIG set. SWTRIG will be cleared automatically. 20 1 TRIGPOL trigger polarity 0: select positive edge of trigger 1: select negative edge of trigger 19 1 OP task operation 3'b000: direct write data 3'b100: read then XOR with data and write back 3'b101: read then OR with data and write back 3'b110: read then AND with data and write back 3'b111: read then add with data and write back 16 3 RSVD2 8 8 TRIGSEL select trigger source 0 8 TAR8 TAR8 0x84 0x20 read-write 0x00000000 ADDR peripheral address to access to 0 32 TDR8 TDR8 0x88 0x20 read-write 0x00000000 DATA data value for task operation 0 32 RCR8 RCR8 task 8 repetition counter register 0x8c 0x20 read-write 0x00000000 RSVD 10 22 REP Repetition counter value if REPEN is 1, task will only be triggerd when REP is not 0. when REP is larger than 0, it will be decrease by 1 automatically each time task triggered. 0 10 RSVD1 RSVD1 0x90 0x20 read-write 0x0 MEM1 MEM1 temporary memory 1 0xd0 0x20 read-write 0x00000000 DATA memory to store temporary variables 0 32 MEM2 MEM2 temporary memory 2 0xd4 0x20 read-write 0x00000000 DATA memory to store temporary variables 0 32 MEM3 MEM3 temporary memory 3 0xd8 0x20 read-write 0x00000000 DATA memory to store temporary variables 0 32 MEM4 MEM4 temporary memory 4 0xdc 0x20 read-write 0x00000000 DATA memory to store temporary variables 0 32 GPIO31_0 GPIO31_0 0xe0 0x20 read-write 0x00000000 RSVD 29 3 SELD select trigger D of GPIO 31~0 24 5 RSVD2 21 3 SELC select trigger C of GPIO 31~0 16 5 RSVD3 13 3 SELB select trigger B of GPIO 31~0 8 5 RSVD4 5 3 SELA select trigger A of GPIO 31~0 0: select GPIO 0 1: select GPIO 1 ...... 31: select GPIO 31 0 5 GPIO63_32 GPIO63_32 0xe4 0x20 read-write 0x00000000 RSVD 29 3 SELD select trigger D of GPIO 63~32 24 5 RSVD2 21 3 SELC select trigger C of GPIO 63~32 16 5 RSVD3 13 3 SELB select trigger B of GPIO 63~32 8 5 RSVD4 5 3 SELA select trigger A of GPIO 63~32 0: select GPIO 32 1: select GPIO 33 ...... 31: select GPIO 63 0 5 GPIO95_64 GPIO95_64 0xe8 0x20 read-write 0x00000000 RSVD 29 3 SELD select trigger D of GPIO 95~64 24 5 RSVD2 21 3 SELC select trigger C of GPIO 95~64 16 5 RSVD3 13 3 SELB select trigger B of GPIO 95~64 8 5 RSVD4 5 3 SELA select trigger A of GPIO 95~64 0: select GPIO 64 1: select GPIO 65 ...... 31: select GPIO 95 0 5 LPSYS_CFG LPSYS_CFG 0x4000f000 0x0 0x1000 registers SYSCR SYSCR System Configure Register 0x00 0x20 read-write 0x0 RSVD 4 28 LDO_VSEL select work mode 0: D 1: S 3 1 DBG_SWAP reserved for debug 1 2 WDT2_REBOOT If set to 1, WDT2 reset will reboot the whole chip 0 1 RTC_TR RTC_TR Mirrored RTC Time Register 0x04 0x20 read-write 0x0 PM AM/PM notation 0: AM 1: PM 31 1 HT Hour tens in BCD format 29 2 HU Hour units in BCD format 25 4 MNT Minute tens in BCD format 22 3 MNU Minute units in BCD format 18 4 ST Second tens in BCD format 15 3 SU Second units in BCD format 11 4 RSVD 10 1 SS Sub-second counter 0 10 RTC_DR RTC_DR Mirrored RTC Date Register 0x08 0x20 read-write 0x0 ERR reserved for debug 31 1 RSVD 25 6 CB Century flag 24 1 YT Year tens in BCD format 20 4 YU Year units in BCD format 16 4 WD Week day units 000: forbidden 001: Monday ... 111: Sunday 13 3 MT Month tens in BCD format 12 1 MU Month units in BCD format 8 4 RSVD2 6 2 DT Date tens in BCD format 4 2 DU Date units in BCD format 0 4 ULPMCR ULPMCR ULP Memory Control register 0x0c 0x20 read-write 0x0 FORCE_ON reserved for debug 31 1 ROM_DIS reserved for debug 30 1 RSVD 21 9 ROM_RME reserved for debug 20 1 RSVD2 18 2 ROM_RM reserved for debug 16 2 RAM_RDY reserved for debug 15 1 RSVD3 13 2 RAM_WPULSE reserved for debug 10 3 RAM_WA reserved for debug 7 3 RAM_RA reserved for debug 5 2 RAM_RME reserved for debug 4 1 RSVD4 2 2 RAM_RM reserved for debug 0 2 DBGR DBGR Debug Register 0x10 0x20 read-write 0x0 READY reserved for debug 31 1 HP2LP_NMIF HP2LP NMI interrupt flag 30 1 HP2LP_NMIE HP2LP NMI interrupt enable 29 1 LP2HP_NMI set 1 to send NMI interrupt to HCPU 28 1 CLK_EN reserved for debug 27 1 CLK_SEL reserved for debug 24 3 BITEN_H reserved for debug 16 8 BITEN_L reserved for debug 8 8 SEL_H reserved for debug 4 4 SEL_L reserved for debug 0 4 MDBGR MDBGR Memory Debug Register 0x14 0x20 read-write 0x0 RSVD 4 28 PD_ROM reserved for debug 3 1 LS_ROM reserved for debug 2 1 LS_RAM1 reserved for debug 1 1 LS_RAM0 reserved for debug 0 1 RSVD1 RSVD1 0x18 0x20 read-write 0x0 USART4_PINR USART4_PINR USART4 Pin Register 0x38 0x20 read-write 0x0 RSVD 27 5 CTS_PIN Connect function pin to selected IO(PB). 0 to 3 for PB00 to PB03. Other values for floating. 24 3 RSVD2 19 5 RTS_PIN Connect function pin to selected IO(PB). 0 to 3 for PB00 to PB03. Other values for floating. 16 3 RSVD3 11 5 RXD_PIN Connect function pin to selected IO(PB). 0 to 3 for PB00 to PB03. Other values for floating. 8 3 RSVD4 3 5 TXD_PIN Connect function pin to selected IO(PB). 0 to 3 for PB00 to PB03. Other values for floating. 0 3 USART5_PINR USART5_PINR USART5 Pin Register 0x3c 0x20 read-write 0x0 RSVD 27 5 CTS_PIN Connect function pin to selected IO(PB). 0 to 3 for PB00 to PB03. Other values for floating. 24 3 RSVD2 19 5 RTS_PIN Connect function pin to selected IO(PB). 0 to 3 for PB00 to PB03. Other values for floating. 16 3 RSVD3 11 5 RXD_PIN Connect function pin to selected IO(PB). 0 to 3 for PB00 to PB03. Other values for floating. 8 3 RSVD4 3 5 TXD_PIN Connect function pin to selected IO(PB). 0 to 3 for PB00 to PB03. Other values for floating. 0 3 PTA_PINR PTA_PINR PTA Pin Register 0x40 0x20 read-write 0x0 RSVD 27 5 WLAN_ACTIVE Connect function pin to selected IO(PB). 0 to 3 for PB00 to PB03. Other values for floating. 24 3 RSVD2 19 5 BT_PRIORITY Connect function pin to selected IO(PB). 0 to 3 for PB00 to PB03. Other values for floating. 16 3 RSVD3 11 5 BT_COLLISION Connect function pin to selected IO(PB). 0 to 3 for PB00 to PB03. Other values for floating. 8 3 RSVD4 3 5 BT_ACTIVE Connect function pin to selected IO(PB). 0 to 3 for PB00 to PB03. Other values for floating. 0 3 LPSYS_AON LPSYS_AON 0x40040000 0x0 0x1000 registers PMR PMR Power Mode Register 0x00 0x20 read-write 0x0 FORCE_SLEEP Set 1 to force enter low power mode. Will be cleared automatically 31 1 RSVD 3 28 CPUWAIT Stall CPU out of reset. Should be cleared before LCPU run 2 1 MODE Power Mode: 2'h0 - active/idle; 2'h1 - light sleep; 2'h2 - deep sleep; 2'h3 - standby 0 2 CR1 CR1 Control Register 1 0x04 0x20 read-write 0x0 GTIM_EN Enable global timer 31 1 PINOUT_SEL1 for debug only 28 3 PINOUT_SEL0 for debug only 25 3 RSVD 12 13 PIN3_MODE mode for wakeup PIN3 (PA27) 9 3 PIN2_MODE mode for wakeup PIN2 (PA26) 6 3 PIN1_MODE mode for wakeup PIN1 (PA25) 3 3 PIN0_MODE mode for wakeup PIN0 (PA24) 0 - high level, 1 - low level, 2 - pos edge, 3 - neg edge, 4/5/6/7: pos or neg edge 0 3 CR2 CR2 Control Register 2 0x08 0x20 read-write 0x0 RSVD 24 8 PIN15_MODE mode for wakeup PIN15 (PA39) 21 3 PIN14_MODE mode for wakeup PIN14 (PA38) 18 3 PIN13_MODE mode for wakeup PIN13 (PA37) 15 3 PIN12_MODE mode for wakeup PIN12 (PA36) 12 3 PIN11_MODE mode for wakeup PIN11 (PA35) 9 3 PIN10_MODE mode for wakeup PIN10 (PA34) 0 - high level, 1 - low level, 2 - pos edge, 3 - neg edge, 4/5/6/7: pos or neg edge 6 3 RSVD2 0 6 CR3 CR3 Control Register 3 0x0c 0x20 read-write 0x0 RSVD 15 17 PIN20_MODE mode for wakeup PIN20 (PA44) 12 3 PIN19_MODE mode for wakeup PIN19 (PA43) 9 3 PIN18_MODE mode for wakeup PIN18 (PA42) 6 3 PIN17_MODE mode for wakeup PIN17 (PA41) 3 3 PIN16_MODE mode for wakeup PIN16 (PA40) 0 - high level, 1 - low level, 2 - pos edge, 3 - neg edge, 4/5/6/7: pos or neg edge 0 3 ACR ACR Active Mode Control register 0x10 0x20 read-write 0x0 HXT48_RDY Indicate hxt48 is ready 31 1 HRC48_RDY Indicate hrc48 is ready 30 1 RSVD 4 26 EXTPWR_REQ for debug only 3 1 PWR_REQ Request power during Active mode 2 1 HXT48_REQ Request hxt48 in active mode 1 1 HRC48_REQ Request hrc48 in active mode 0 1 LSCR LSCR Light Sleep Ctrl Register 0x14 0x20 read-write 0x0 RSVD 4 28 EXTPWR_REQ for debug only 3 1 PWR_REQ Request power during Light Sleep mode 2 1 HXT48_REQ Request hxt48 in Light Sleep mode 1 1 HRC48_REQ Request hrc48 in Light Sleep mode 0 1 DSCR DSCR Deep Sleep Ctrl Register 0x18 0x20 read-write 0x0 RSVD 4 28 EXTPWR_REQ for debug only 3 1 PWR_REQ Request power during Deep Sleep mode 2 1 HXT48_REQ Request hxt48 in Deep Sleep mode 1 1 HRC48_REQ Request hrc48 in Deep Sleep mode 0 1 SBCR SBCR Standby Mode Ctrl Register 0x1c 0x20 read-write 0x0 RSVD 8 24 PD_RAM1 for debug only 7 1 PD_RAM0 for debug only 6 1 RSVD2 4 2 EXTPWR_REQ for debug only 3 1 PWR_REQ Request power during Standby mode 2 1 HXT48_REQ Request hxt48 in Standby mode 1 1 HRC48_REQ Request hrc48 in Standby mode 0 1 WER WER Wakeup Enable register 0x20 0x20 read-write 0x0 RSVD 29 3 PIN20 Set 1 to enable PA44 as wakeup source 28 1 PIN19 Set 1 to enable PA43 as wakeup source 27 1 PIN18 Set 1 to enable PA42 as wakeup source 26 1 PIN17 Set 1 to enable PA41 as wakeup source 25 1 PIN16 Set 1 to enable PA40 as wakeup source 24 1 PIN15 Set 1 to enable PA39 as wakeup source 23 1 PIN14 Set 1 to enable PA38 as wakeup source 22 1 PIN13 Set 1 to enable PA37 as wakeup source 21 1 PIN12 Set 1 to enable PA36 as wakeup source 20 1 PIN11 Set 1 to enable PA35 as wakeup source 19 1 PIN10 Set 1 to enable PA34 as wakeup source 18 1 RSVD2 12 6 PIN3 Set 1 to enable PA27 as wakeup source 11 1 PIN2 Set 1 to enable PA26 as wakeup source 10 1 PIN1 Set 1 to enable PA25 as wakeup source 9 1 PIN0 Set 1 to enable PA24 as wakeup source 8 1 HP2LP_IRQ Set 1 to enable MAILBOX1 as wakeup source 7 1 HP2LP_REQ Set 1 to enable HPSYS request as wakeup source 6 1 BT Set 1 to enable BT as wakeup source 5 1 RSVD3 3 2 LPTIM3 Set 1 to enable LPTIM3 as wakeup source 2 1 GPIO2 Set 1 to enable IO(PB) as wakeup source 1 1 RTC Set 1 to enable RTC as wakeup source 0 1 WSR WSR Wakeup Status register 0x24 0x20 read-write 0x0 RSVD 29 3 PIN20 Indicates the wakeup status from PA44 request. Note: the status is masked by WER 28 1 PIN19 Indicates the wakeup status from PA43 request. Note: the status is masked by WER 27 1 PIN18 Indicates the wakeup status from PA42 request. Note: the status is masked by WER 26 1 PIN17 Indicates the wakeup status from PA41 request. Note: the status is masked by WER 25 1 PIN16 Indicates the wakeup status from PA40 request. Note: the status is masked by WER 24 1 PIN15 Indicates the wakeup status from PA39 request. Note: the status is masked by WER 23 1 PIN14 Indicates the wakeup status from PA38 request. Note: the status is masked by WER 22 1 PIN13 Indicates the wakeup status from PA37 request. Note: the status is masked by WER 21 1 PIN12 Indicates the wakeup status from PA36 request. Note: the status is masked by WER 20 1 PIN11 Indicates the wakeup status from PA35 request. Note: the status is masked by WER 19 1 PIN10 Indicates the wakeup status from PA34 request. Note: the status is masked by WER 18 1 RSVD2 12 6 PIN3 Indicates the wakeup status from PA27 request. Note: the status is masked by WER 11 1 PIN2 Indicates the wakeup status from PA26 request. Note: the status is masked by WER 10 1 PIN1 Indicates the wakeup status from PA25 request. Note: the status is masked by WER 9 1 PIN0 Indicates the wakeup status from PA24 request. Note: the status is masked by WER 8 1 HP2LP_IRQ Indicates the wakeup status from MAILBOX1. Note: the status is masked by WER 7 1 HP2LP_REQ Indicates the wakeup status from HPSYS request. Note: the status is masked by WER 6 1 BT Indicates the wakeup status from BT. Note: the status is masked by WER 5 1 RSVD3 3 2 LPTIM3 Indicates the wakeup status from LPTIM3. Note: the status is masked by WER 2 1 GPIO2 Indicates the wakeup status from IO(PB). Note: the status is masked by WER 1 1 RTC Indicates the wakeup status from RTC. Note: the status is masked by WER 0 1 WCR WCR Wakeup Clear register 0x28 0x20 read-write 0x0 AON Write 1 to clear the AON wakeup IRQ status 31 1 RSVD 29 2 PIN20 Write 1 to clear PA44 wakeup source. Only valid if PIN wakeup is configured as edge trigger 28 1 PIN19 Write 1 to clear PA43 wakeup source. Only valid if PIN wakeup is configured as edge trigger 27 1 PIN18 Write 1 to clear PA42 wakeup source. Only valid if PIN wakeup is configured as edge trigger 26 1 PIN17 Write 1 to clear PA41 wakeup source. Only valid if PIN wakeup is configured as edge trigger 25 1 PIN16 Write 1 to clear PA40 wakeup source. Only valid if PIN wakeup is configured as edge trigger 24 1 PIN15 Write 1 to clear PA39 wakeup source. Only valid if PIN wakeup is configured as edge trigger 23 1 PIN14 Write 1 to clear PA38 wakeup source. Only valid if PIN wakeup is configured as edge trigger 22 1 PIN13 Write 1 to clear PA37 wakeup source. Only valid if PIN wakeup is configured as edge trigger 21 1 PIN12 Write 1 to clear PA36 wakeup source. Only valid if PIN wakeup is configured as edge trigger 20 1 PIN11 Write 1 to clear PA35 wakeup source. Only valid if PIN wakeup is configured as edge trigger 19 1 PIN10 Write 1 to clear PA34 wakeup source. Only valid if PIN wakeup is configured as edge trigger 18 1 RSVD2 12 6 PIN3 Write 1 to clear PA27 wakeup source. Only valid if PIN wakeup is configured as edge trigger 11 1 PIN2 Write 1 to clear PA26 wakeup source. Only valid if PIN wakeup is configured as edge trigger 10 1 PIN1 Write 1 to clear PA25 wakeup source. Only valid if PIN wakeup is configured as edge trigger 9 1 PIN0 Write 1 to clear PA24 wakeup source. Only valid if PIN wakeup is configured as edge trigger 8 1 RSVD3 Note: for RTC/GPIO/LPTIM/BT, clear the wakeup status directly in the corresponding module 0 8 ISSR ISSR Inter System Status Register 0x2c 0x20 read-write 0x0 RSVD 6 26 HP_ACTIVE read 1 indicates HPSYS is active 5 1 LP_ACTIVE write 1 to indicates LPSYS is active 4 1 RSVD2 2 2 HP2LP_REQ indicate HPSYS request exists 1 1 LP2HP_REQ write 1 to request HPSYS to stay in active mode 0 1 TARGET TARGET BT sleep time target 0x30 0x20 read-write 0x0 RSVD 28 4 SLEEP_TARGET bt sleep time target in cycles of clk_rtc 0 28 ACTUAL ACTUAL BT actual sleep time 0x34 0x20 read-write 0x0 RSVD 28 4 SLEEP_CNT bt actual sleep time in cycles of clk_rtc. If not woken up by software or external interrupt, sleep_cnt counts up every clk_rtc cycle, until reaches sleep_target 0 28 PRE_WKUP PRE_WKUP time before bt awake 0x38 0x20 read-write 0x0 RSVD 26 6 WKUP_TIME cycles of clk_rtc for LPSYS ready before bt awake. 16 10 RSVD2 10 6 XTAL_TIME cycles of clk_rtc for hxt48 ready before bt awake. 0 10 SLP_CFG SLP_CFG BT sleep configuration 0x3c 0x20 read-write 0x0 RSVD 4 28 XTAL_FORCE_OFF for debug only 3 1 XTAL_ALWAYS_ON for debug only 2 1 RSVD2 0 2 SLP_CTRL SLP_CTRL BT sleep control 0x40 0x20 read-write 0x0 RSVD 7 25 BT_WKUP bt wakeup source. 1 means bt has not enter sleep or has enter wakeup procedure 6 1 XTAL_REQ xtal request status. 1 means bt is requiring xtal. 5 1 SLEEP_STATUS bt sleep status. 1 means bt is sleeping and sleep_cnt is counting up 4 1 RSVD2 2 2 WKUP_REQ software request to wakeup bt. Will be cleared automatically 1 1 SLEEP_REQ bt sleep request. Will be cleared automatically 0 1 ANACR ANACR Analog Control Register 0x44 0x20 read-write 0x0 RSVD 2 30 VLP_ISO Set 1 to force off all LPSYS related analog modules 1 1 PB_ISO Set 1 to force IO(PB) into retention mode 0 1 GTIMR GTIMR Global Timer Register 0x48 0x20 read-write 0x0 CNT Global timer value 0 32 RESERVE0 RESERVE0 Reserved Register 0 0x4c 0x20 read-write 0x0 DATA for debug only 0 32 RESERVE1 RESERVE1 Reserved Register 1 0x50 0x20 read-write 0x0 DATA for debug only 0 32 RSVD1 RSVD1 0x54 0x20 read-write 0x0 SPR SPR Stack Pointer Register 0x100 0x20 read-write 0x0 SP LCPU stack pointer address 0 32 PCR PCR Pointer Counter Register 0x104 0x20 read-write 0x0 PC LCPU PC pointer address 0 32 LPTIM3 LPTIM 0x40042000 0x0 0x1000 registers ISR ISR LPTIM interrupt and status register 0x00 0x20 read-write 0x00000000 RSVD 11 21 OCWKUP Indicates output compare wakeup occurred The OCWKUP bit is set by hardware when LPTIM_CNT register value reached the LPTIM_CMP register’s value. To clear OCWKUP, first write 0 to the OCWE bit in the LPTIM_IER register to disable, then write 1 to the WKUPCLR bit in the LPTIM_ICR register. 10 1 OFWKUP Indicates overflow wakeup occurred OFWKUP is set by hardware when LPTIM_CNT register’s value reached the LPTIM_ARR register’s value and count from zero again. To clear OFWKUP, first write 0 to the OFWE bit in the LPTIM_IER register to disable, then write 1 to the WKUPCLR bit in the LPTIM_ICR register. 9 1 UEWKUP Indicates update event wakeup occurred UEWKUP is set by hardware when an update event was generated (overflow occurred while repetition counter reached zero). To clear UEWKUP, first write 0 to the UEWE bit in the LPTIM_IER register to disable, then write 1 to the WKUPCLR bit in the LPTIM_ICR register. 8 1 RSVD2 4 4 ET External trigger edge event ET is set by hardware to inform application that a valid edge on the selected external trigger input has occurred. If the trigger is ignored because the timer has already started, then this flag is not set. ET flag can be cleared by writing 1 to the ETCLR bit in the LPTIM_ICR register. 3 1 OC Output compare match The OC bit is set by hardware to inform application that LPTIM_CNT register value reached the LPTIM_CMP register’s value. OC flag can be cleared by writing 1 to the OCCLR bit in the LPTIM_ICR register. 2 1 OF Overflow occurred OF is set by hardware to inform application that LPTIM_CNT register’s value reached the LPTIM_ARR register’s value and count from zero again. OF flag can be cleared by writing 1 to the OFCLR bit in the LPTIM_ICR register. 1 1 UE LPTIM update event occurred UE is set by hardware to inform application that an update event was generated when overflow occurred while repetition counter reached zero. UE flag can be cleared by writing 1 to the UECLR bit in the LPTIM_ICR register. 0 1 ICR ICR LPTIM interrupt and status clear register 0x04 0x20 read-write 0x00000000 RSVD 9 23 WKUPCLR wakeup status clear flag Writing 1 to this bit clears all wakeup status flags in the LPTIM_ISR register. 8 1 RSVD2 4 4 ETCLR External trigger valid edge clear flag Writing 1 to this bit clears the ET flag in the LPTIM_ISR register 3 1 OCCLR Output compare clear flag Writing 1 to this bit clears the OC flag in the LPTIM_ISR register 2 1 OFCLR Overflow clear flag Writing 1 to this bit clears the OF flag in the LPTIM_ISR register 1 1 UECLR Update event clear flag Writing 1 to this bit clear the UE flag in the LPTIM_ISR register. 0 1 IER IER LPTIM interrupt and wakeup enable register 0x08 0x20 read-write 0x00000000 RSVD 11 21 OCWE Output compare Wakeup Enable 0: Output compare wakeup disabled 1: Output compare wakeup enabled 10 1 OFWE Overflow Wakeup Enable 0: Overflow Wakeup disabled 1: Overflow Wakeup enabled 9 1 UEWE Update event Wakeup enable 0: Update event Wakeup disabled 1: Update event Wakeup enabled 8 1 RSVD2 4 4 ETIE External trigger valid edge Interrupt Enable 0: External trigger interrupt disabled 1: External trigger interrupt enabled 3 1 OCIE Output compare Interrupt Enable 0: Output compare interrupt disabled 1: Output compare interrupt enabled 2 1 OFIE Overflow Interrupt Enable 0: Overflow interrupt disabled 1: Overflow interrupt enabled 1 1 UEIE Update event interrupt enable 0: Update event interrupt disabled 1: Update event interrupt enabled 0 1 CFGR CFGR LPTIM configuration register 0x0c 0x20 read-write 0x00000000 RSVD 24 8 COUNTMODE counter mode in internal clock source mode (CKSEL=0). If CKSEL=1, this bit has no effect. 0: the counter is incremented following each internal clock pulse 1: the counter is incremented following each valid pulse on the external clock 23 1 RSVD2 22 1 WAVPOL Waveform shape polarity The WAVEPOL bit controls the output polarity 0: The LPTIM output reflects the compare results between LPTIM_ARR and LPTIM_CMP registers 1: The LPTIM output reflects the inverse of the compare results between LPTIM_ARR and LPTIM_CMP registers 21 1 WAVE Waveform shape The WAVE bit controls the output shape 0: Deactivate Set-once mode 1: Activate the Set-once mode 20 1 TIMOUT Timeout enable The TIMOUT bit controls the Timeout feature 0: A trigger event arriving when the timer is already started will be ignored 1: A trigger event arriving when the timer is already started will reset and restart the LPTIM counter and the repetition counter 19 1 TRIGEN Trigger enable and polarity The TRIGEN bits controls whether the LPTIM counter is started by an external trigger or not. If the external trigger option is selected, three configurations are possible for the trigger active edge: 00: software trigger (counting start is initiated by software) 01: rising edge is the active edge 10: falling edge is the active edge 11: both edges are active edges 17 2 RSVD3 16 1 TRIGSEL Trigger selector The TRIGSEL bits select the trigger source that will serve as a trigger event for the LPTIM among the below 8 available sources: 000: lptim_ext0 001: lptim_ext1 010: lptim_ext2 011: lptim_ext3 100: lptim_ext4 101: lptim_ext5 110: lptim_ext6 111: lptim_ext7 13 3 RSVD4 12 1 PRESC Clock prescaler The PRESC bits configure the prescaler division factor. It can be one among the following division factors: 000: /1 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128 9 3 EXTCKSEL External clock source selector 0: external clock source is from lptim_in 1: external clock source is from LPCOMP (if LPCOMP integrated) 8 1 TRGFLT Configurable digital filter for trigger The TRGFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an internal trigger before it is considered as a valid level transition. An internal clock source must be present to use this feature 00: any trigger active level change is considered as a valid trigger 01: trigger active level change must be stable for at least 2 clock periods before it is considered as valid trigger. 10: trigger active level change must be stable for at least 4 clock periods before it is considered as valid trigger. 11: trigger active level change must be stable for at least 8 clock periods before it is considered as valid trigger. 6 2 INTCKSEL Internal clock source selector 0: internal clock source is clk_lp 1: internal clock source is pclk2 5 1 CKFLT Configurable digital filter for external clock The CKFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an external clock signal before it is considered as a valid level transition. An internal clock source must be present to use this feature 00: any external clock signal level change is considered as a valid transition 01: external clock signal level change must be stable for at least 2 clock periods before it is considered as valid transition. 10: external clock signal level change must be stable for at least 4 clock periods before it is considered as valid transition. 11: external clock signal level change must be stable for at least 8 clock periods before it is considered as valid transition. 3 2 CKPOL Clock Polarity If LPTIM is clocked by an external clock source, CKPOL bits is used to configure the active edge or edges used by the counter: 00: the rising edge is the active edge used for counting 01: the falling edge is the active edge used for counting 10: both edges are active edges. When both external clock signal edges are considered active ones, the LPTIM must also be clocked by an internal clock source with a frequency equal to at least four time the external clock frequency. 11: not allowed 1 2 CKSEL Clock selector The CKSEL bit selects which clock source the LPTIM will use: 0: LPTIM is clocked by internal clock source, according to INTCKSEL 1: LPTIM is clocked by external clock source, according to EXTCKSEL 0 1 CR CR LPTIM control register 0x10 0x20 read-write 0x00000000 RSVD 4 28 COUNTRST Counter reset This bit is set by software and cleared by hardware. When set to 1 this bit will trigger a synchronous reset of the CNT register. Due to the synchronous nature of this reset, it only takes place after a synchronization delay. COUNTRST must never be set to 1 by software before it is already cleared to 0 by hardware. Software should consequently check that COUNTRST bit is already cleared to 0 before attempting to set it to 1. 3 1 CNTSTRT Timer start in Continuous mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = 00), setting this bit starts the LPTIM in Continuous mode. If the software start is disabled (TRIGEN[1:0] different than 00), setting this bit starts the timer in Continuous mode as soon as an external trigger is detected. If this bit is set when a single pulse mode counting is ongoing, then the timer will not stop at the next match between ARR and CNT registers and the LPTIM counter keeps counting in Continuous mode. 2 1 SNGSTRT LPTIM start in Single mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = 00), setting this bit starts the LPTIM in single pulse mode. If the software start is disabled (TRIGEN[1:0] different than 00), setting this bit starts the LPTIM in single pulse mode as soon as an external trigger is detected. If this bit is set when the LPTIM is in continuous counting mode, then the LPTIM will stop at the following match between ARR and CNT registers. If this bit is set simultaneously with CNTSTRT, then LPTIM will be in continuous counting mode. 1 1 ENABLE LPTIM enable The ENABLE bit is set and cleared by software. 0:LPTIM is disabled 1:LPTIM is enabled 0 1 CMP CMP LPTIM compare register 0x14 0x20 read-write 0x00000000 RSVD 24 8 CMP Compare value CMP is the compare value used by the LPTIM. 0 24 ARR ARR LPTIM autoreload register 0x18 0x20 read-write 0x00000000 RSVD 24 8 ARR Auto reload value ARR is the autoreload value for the LPTIM. This value must be strictly greater than the CMP[15:0] value. 0 24 CNT CNT LPTIM counter register 0x1c 0x20 read-write 0x00000000 RSVD 24 8 CNT Counter value When the LPTIM is running with an asynchronous clock, reading the CNT register may return unreliable values. So in this case it is necessary to perform two consecutive read accesses and verify that the two returned values are identical. 0 24 RCR RCR LPTIM repetition register 0x20 0x20 read-write 0x00000000 RSVD 8 24 REP Repetition register value REP is the repetition value for the LPTIM. Read REP will return left repetition times. It should be noted that for a reliable REP register read access, two consecutive read accesses must be performed and compared. A read access can be considered reliable when the values of the two consecutive read accesses are equal. 0 8 CRC2 CRC 0x40085000 0x0 0x1000 registers DR DR Data register 0x00 0x20 read-write 0x0 DR Data register bits. This register is used to write new data to the CRC calculator. It holds the previous CRC calculation result when it is read. If the data size is less than 32 bits, the least significant bits are used to write/read the correct value. 0 32 SR SR Status register 0x04 0x20 read-write 0x0 RSVD 2 30 OVERFLOW Overflow when new data arrive while last calculation not done yet 1 1 DONE Done flag. When DR written, done flag will be cleared automatically. The flag will assert after CRC operation of current DR finished. 0 1 CR CR Control register 0x08 0x20 read-write 0x0 RSVD 8 24 REV_OUT Reverse output data This bit controls the reversal of the bit order of the output data. 0: Bit order not affected 1: Bit-reversed output format 7 1 REV_IN Reverse input data These bits control the reversal of the bit order of the input data 00: Bit order not affected 01: Bit reversal done by byte 10: Bit reversal done by half-word 11: Bit reversal done by word 5 2 POLYSIZE Polynomial size These bits control the size of the polynomial. 00: 32 bit polynomial 01: 16 bit polynomial 10: 8 bit polynomial 11: 7 bit polynomial 3 2 DATASIZE Valid input data size These bits control the valid size of the input data. 00: lower 8-bit 01: lower 16-bit 10: lower 24-bit 11: all 32-bit 1 2 RESET This bit is set by software to reset the CRC calculation unit and set the data register to the value stored in the CRC_INIT register. This bit can only be set, it is automatically cleared by hardware 0 1 RSVD1 RSVD1 0xC 0x20 read-write 0x0 INIT INIT Initial CRC value 0x10 0x20 read-write 0x0 INIT Programmable initial CRC value 0 32 POL POL CRC polynomial 0x14 0x20 read-write 0x0 POL Programmable polynomial This register is used to write the coefficients of the polynomial to be used for CRC calculation. If the polynomial size is less than 32 bits, the least significant bits have to be used to program the correct value. 0 32