Subject: Re: [PATCH v1 2/9] riscv: dts: starfive: Add VisionFive 2 Lite board device tree

From: E Shattow <[email-masked]>
Date: Fri, 24 Oct 2025 03:58:06 -0700

Hi Hal, this is very good, I have some suggestion to improve more.

On 10/24/25 01:59, Hal Feng wrote:
> /****************************************************************/
> This patch picked from [1] is just for test and can be ignored.
> dts/upstream should be synced regularly with devicetree-rebasing.
> 
> [1] https://lore.kernel.org/all/[email-masked]/
> /****************************************************************/
> 
> VisionFive 2 Lite is a mini SBC based on the StarFive JH7110S SoC.
> 
> Board features:
> - JH7110S SoC
> - 2/4/8 GiB LPDDR4 DRAM
> - AXP15060 PMIC
> - 40 pin GPIO header
> - 1x USB 3.0 host port
> - 3x USB 2.0 host port
> - 1x M.2 M-Key (size: 2242)
> - 1x MicroSD slot (optional non-removable eMMC)
> - 1x QSPI Flash
> - 1x I2C EEPROM
> - 1x 1Gbps Ethernet port
> - SDIO-based Wi-Fi & UART-based Bluetooth
> - 1x HDMI port
> - 1x 2-lane DSI
> - 1x 2-lane CSI
> 
> Signed-off-by: Hal Feng <[email-masked]>
> ---
>  .../jh7110s-starfive-visionfive-2-lite.dts    | 159 ++++++++++++++++++
>  1 file changed, 159 insertions(+)
>  create mode 100644 dts/upstream/src/riscv/starfive/jh7110s-starfive-visionfive-2-lite.dts
> 
> diff --git a/dts/upstream/src/riscv/starfive/jh7110s-starfive-visionfive-2-lite.dts b/dts/upstream/src/riscv/starfive/jh7110s-starfive-visionfive-2-lite.dts
> new file mode 100644
> index 00000000000..30842b0cd1f
> --- /dev/null
> +++ b/dts/upstream/src/riscv/starfive/jh7110s-starfive-visionfive-2-lite.dts
> @@ -0,0 +1,159 @@
> +// SPDX-License-Identifier: GPL-2.0 OR MIT
> +/*
> + * Copyright (C) 2025 StarFive Technology Co., Ltd.
> + * Copyright (C) 2025 Hal Feng <[email-masked]>
> + */
> +
> +/dts-v1/;
> +#include "jh7110-common.dtsi"
> +
> +/ {
> +	model = "StarFive VisionFive 2 Lite";
> +	compatible = "starfive,visionfive-2-lite", "starfive,jh7110s";
> +};
...

FYI as a follow-up to my earlier comments about modifying the dts
subtree I have now a working recommendation:

1). Return to using "RFC" subject prefix for the series while any
modification exists to dts subtree. The comment said about this is do
not post any "DO NOT MERGE" type patches that touch dts subtree, however...

2). Additions to CONFIG_OF_LIST will cause a build error if there is not
any corresponding file in the dts subtree. Use a workaround:

git mv
dts/upstream/src/riscv/starfive/jh7110s-starfive-visionfive-2-lite.dts
arch/riscv/dts/jh7110s-starfive-visionfive-2-lite-u-boot.dtsi
touch dts/upstream/src/riscv/starfive/jh7110s-starfive-visionfive-2-lite.dts
git add
dts/upstream/src/riscv/starfive/jh7110s-starfive-visionfive-2-lite.dts
arch/riscv/dts/jh7110s-starfive-visionfive-2-lite-u-boot.dtsi

Alternatively for your local development environment:

echo '#include
"/path/to/linux.git/arch/riscv/boot/dts/starfive/jh7110s-starfive-visionfive-2-lite-u-boot.dtsi"'
> arch/riscv/dts/jh7110s-starfive-visionfive-2-lite-u-boot.dtsi

This "-u-boot.dtsi" suffix file will get picked up by the build system
automatically when there is a corresponding file (empty file is okay) in
dts subtree. The empty file in dts subtree is a simple git file
operation with no actual content. It is not perfect as an answer but it
is better for the review now, and for anyone else reading this that may
want to do the same.

You can see this in the working example of RFC v1 series for Milk-V Mars
CM re-introduction:

https://lore.kernel.org/u-boot/[email-masked]/

and the follow-up as v2 series as this lands in devicetree-rebasing:

https://lore.kernel.org/u-boot/[email-masked]/

I hope that is a good example to follow for v3, v4 of your series

3). If you follow RFC -> PATCH -> RFC the version does increment (RFC
v1, PATCH v2, RFC v3, ...)

Thanks,

-E

---

From: E Shattow <[email-masked]>
Date: Fri, 24 Oct 2025 04:17:38 -0700

Hi Hal, this is more complex change, I will have to think more about
what suggestion to make so this can avoid changes in dts subtree.
Anyways we know it is to be ignored in review as you said, and all the
information is very clear in meaning, thank you!

On 10/24/25 01:59, Hal Feng wrote:
> Some node in this file are not used by the upcoming VisionFive 2 Lite
> board. Move them to the board dts to prepare for adding the new
> VisionFive 2 Lite device tree.
> 
>  .../src/riscv/starfive/jh7110-common.dtsi     | 22 ---------
>  .../jh7110-deepcomputing-fml13v01.dts         | 49 +++++++++++++++++++
>  .../src/riscv/starfive/jh7110-milkv-mars.dts  | 49 +++++++++++++++++++
>  .../riscv/starfive/jh7110-pine64-star64.dts   | 49 +++++++++++++++++++
>  .../jh7110-starfive-visionfive-2.dtsi         | 46 +++++++++++++++++
>  dts/upstream/src/riscv/starfive/jh7110.dtsi   | 16 ------
>  6 files changed, 193 insertions(+), 38 deletions(-)
> 
> diff --git a/dts/upstream/src/riscv/starfive/jh7110-common.dtsi b/dts/upstream/src/riscv/starfive/jh7110-common.dtsi
> index 2eaf01775ef..8332622420c 100644
> --- a/dts/upstream/src/riscv/starfive/jh7110-common.dtsi
> +++ b/dts/upstream/src/riscv/starfive/jh7110-common.dtsi
> @@ -281,15 +281,9 @@
...

I did send a series to cherry-pick into U-Boot from v6.18-rc1 which
should help with some of these overrides, particularly the no-sdio
no-mmc properties.

https://lore.kernel.org/u-boot/[email-masked]/

Also there's a commit in riscv-dt-for-next for the mmc0 pins changes:

https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/commit/?h=riscv-dt-for-next&id=fa939a287224de705c825c093f3d9d34ae977b0b

>  	assigned-clock-rates = <50000000>;
>  	bus-width = <8>;
>  	bootph-pre-ram;
> -	cap-mmc-highspeed;
> -	mmc-ddr-1_8v;
> -	mmc-hs200-1_8v;
> -	cap-mmc-hw-reset;
>  	post-power-on-delay-ms = <200>;
>  	pinctrl-names = "default";
>  	pinctrl-0 = <&mmc0_pins>;
> -	vmmc-supply = <&vcc_3v3>;
> -	vqmmc-supply = <&emmc_vdd>;
>  	status = "okay";
>  };
>  
> @@ -299,12 +293,7 @@
>  	assigned-clock-rates = <50000000>;
>  	bus-width = <4>;
>  	bootph-pre-ram;
> -	no-sdio;
> -	no-mmc;
> -	cd-gpios = <&sysgpio 41 GPIO_ACTIVE_LOW>;
> -	disable-wp;
>  	cap-sd-highspeed;
> -	post-power-on-delay-ms = <200>;
>  	pinctrl-names = "default";
>  	pinctrl-0 = <&mmc1_pins>;
>  	status = "okay";
> @@ -448,17 +437,6 @@
>  	};
>  
>  	mmc0_pins: mmc0-0 {
> -		 rst-pins {
> -			pinmux = <GPIOMUX(62, GPOUT_SYS_SDIO0_RST,
> -					      GPOEN_ENABLE,
> -					      GPI_NONE)>;
> -			bias-pull-up;
> -			drive-strength = <12>;
> -			input-disable;
> -			input-schmitt-disable;
> -			slew-rate = <0>;
> -		};
> -
>  		mmc-pins {
>  			pinmux = <PINMUX(PAD_SD0_CLK, 0)>,
>  				 <PINMUX(PAD_SD0_CMD, 0)>,
> diff --git a/dts/upstream/src/riscv/starfive/jh7110-deepcomputing-fml13v01.dts b/dts/upstream/src/riscv/starfive/jh7110-deepcomputing-fml13v01.dts
> index f2857d021d6..5a2a41a7e8c 100644
> --- a/dts/upstream/src/riscv/starfive/jh7110-deepcomputing-fml13v01.dts
> +++ b/dts/upstream/src/riscv/starfive/jh7110-deepcomputing-fml13v01.dts
> @@ -11,6 +11,55 @@
>  	compatible = "deepcomputing,fml13v01", "starfive,jh7110";
...> diff --git a/dts/upstream/src/riscv/starfive/jh7110-milkv-mars.dts
b/dts/upstream/src/riscv/starfive/jh7110-milkv-mars.dts
> index fdaf6b4557d..96f6b2f072d 100644
> --- a/dts/upstream/src/riscv/starfive/jh7110-milkv-mars.dts
> +++ b/dts/upstream/src/riscv/starfive/jh7110-milkv-mars.dts
> @@ -11,6 +11,25 @@
>  	compatible = "milkv,mars", "starfive,jh7110";
...> diff --git
a/dts/upstream/src/riscv/starfive/jh7110-pine64-star64.dts
b/dts/upstream/src/riscv/starfive/jh7110-pine64-star64.dts
> index 31e825be206..c9677aef9ff 100644
> --- a/dts/upstream/src/riscv/starfive/jh7110-pine64-star64.dts
> +++ b/dts/upstream/src/riscv/starfive/jh7110-pine64-star64.dts
...> diff --git
a/dts/upstream/src/riscv/starfive/jh7110-starfive-visionfive-2.dtsi
b/dts/upstream/src/riscv/starfive/jh7110-starfive-visionfive-2.dtsi
> index 5f14afb2c24..d1e4206f125 100644
> --- a/dts/upstream/src/riscv/starfive/jh7110-starfive-visionfive-2.dtsi
> +++ b/dts/upstream/src/riscv/starfive/jh7110-starfive-visionfive-2.dtsi
> @@ -13,6 +13,25 @@
...> diff --git a/dts/upstream/src/riscv/starfive/jh7110.dtsi
b/dts/upstream/src/riscv/starfive/jh7110.dtsi
> index 0ba74ef0467..d2463399b95 100644
> --- a/dts/upstream/src/riscv/starfive/jh7110.dtsi
> +++ b/dts/upstream/src/riscv/starfive/jh7110.dtsi
> @@ -200,22 +200,6 @@
>  	cpu_opp: opp-table-0 {
>  			compatible = "operating-points-v2";
>  			opp-shared;
> -			opp-375000000 {
> -					opp-hz = /bits/ 64 <375000000>;
> -					opp-microvolt = <800000>;
> -			};
> -			opp-500000000 {
> -					opp-hz = /bits/ 64 <500000000>;
> -					opp-microvolt = <800000>;
> -			};
> -			opp-750000000 {
> -					opp-hz = /bits/ 64 <750000000>;
> -					opp-microvolt = <800000>;
> -			};
> -			opp-1500000000 {
> -					opp-hz = /bits/ 64 <1500000000>;
> -					opp-microvolt = <1040000>;
> -			};
>  	};
>  
>  	thermal-zones {

I've suggested (for you? and Emil?) the idea that we split out the OPP
tables from the common dtsi to a separate dtsi for JH7110 and JH7110S:

https://lore.kernel.org/lkml/[email-masked]/

Also to cut out the mmc0 mmc1 properties into a separate common dtsi.

FYI for anyone following along with this subject for discussion upstream
in Linux mailing list.

-E

---

From: E Shattow <[email-masked]>
Date: Fri, 24 Oct 2025 04:24:05 -0700

On 10/24/25 01:59, Hal Feng wrote:
> Directly return the DDR size instead of the field of 'DxxxExxx'.
> Move the function description to the header file.
> Return 0 instead of 0xFF if read_eeprom() fails.
> 
> Reviewed-by: Heinrich Schuchardt <[email-masked]>
> Fixes: aea1bd95b61e ("eeprom: starfive: Enable ID EEPROM configuration")
>  arch/riscv/cpu/jh7110/spl.c                     |  2 +-
>  arch/riscv/include/asm/arch-jh7110/eeprom.h     |  8 +++++++-
>  .../visionfive2/visionfive2-i2c-eeprom.c        | 17 +++--------------
>  3 files changed, 11 insertions(+), 16 deletions(-)
> 
> diff --git a/arch/riscv/cpu/jh7110/spl.c b/arch/riscv/cpu/jh7110/spl.c
> index 87aaf865246..3aece7d995b 100644
> --- a/arch/riscv/cpu/jh7110/spl.c
> +++ b/arch/riscv/cpu/jh7110/spl.c
> @@ -41,7 +41,7 @@ int spl_dram_init(void)
>  	/* Read the definition of the DDR size from eeprom, and if not,
>  	 * use the definition in DT
>  	 */
> -	size = (get_ddr_size_from_eeprom() >> 16) & 0xFF;
> +	size = get_ddr_size_from_eeprom();
>  	if (check_ddr_size(size))
>  		gd->ram_size = size << 30;
>  
> diff --git a/arch/riscv/include/asm/arch-jh7110/eeprom.h b/arch/riscv/include/asm/arch-jh7110/eeprom.h
> index 45ad2a5f7bc..1ae9f2b840a 100644
> --- a/arch/riscv/include/asm/arch-jh7110/eeprom.h
> +++ b/arch/riscv/include/asm/arch-jh7110/eeprom.h
> @@ -10,7 +10,13 @@
>  #include <linux/types.h>
>  
>  u8 get_pcb_revision_from_eeprom(void);
> -u32 get_ddr_size_from_eeprom(void);
> +
> +/**
> + * get_ddr_size_from_eeprom() - read DDR size from EEPROM
> + *
> + * @return: size in GiB or 0 on error.
> + */
> +u8 get_ddr_size_from_eeprom(void);
>  
>  /**
>   * get_mmc_size_from_eeprom() - read eMMC size from EEPROM
> diff --git a/board/starfive/visionfive2/visionfive2-i2c-eeprom.c b/board/starfive/visionfive2/visionfive2-i2c-eeprom.c
> index 17a44020bcf..ca5039ee433 100644
> --- a/board/starfive/visionfive2/visionfive2-i2c-eeprom.c
> +++ b/board/starfive/visionfive2/visionfive2-i2c-eeprom.c
> @@ -550,23 +550,12 @@ u8 get_pcb_revision_from_eeprom(void)
>  	return pbuf.eeprom.atom1.data.pstr[6];
>  }
>  
> -/**
> - * get_ddr_size_from_eeprom - get the DDR size
> - * pstr:  VF7110A1-2228-D008E000-00000001
> - * VF7110A1/VF7110B1 : VisionFive JH7110A /VisionFive JH7110B
> - * D008: 8GB LPDDR4
> - * E000: No emmc device, ECxx: include emmc device, xx: Capacity size[GB]
> - * return: the field of 'D008E000'
> - */
> -
> -u32 get_ddr_size_from_eeprom(void)
> +u8 get_ddr_size_from_eeprom(void)
>  {
> -	u32 pv = 0xFFFFFFFF;
> -
>  	if (read_eeprom())
> -		return pv;
> +		return 0;
>  
> -	return hextoul(&pbuf.eeprom.atom1.data.pstr[14], NULL);
> +	return (hextoul(&pbuf.eeprom.atom1.data.pstr[14], NULL) >> 16) & 0xFF;
>  }
>  
>  u32 get_mmc_size_from_eeprom(void)

LGTM

Reviewed-by: E Shattow <[email-masked]>

---

From: E Shattow <[email-masked]>
Date: Fri, 24 Oct 2025 04:30:15 -0700

On 10/24/25 01:59, Hal Feng wrote:
> pcb_revision is stored in the pcb_revision field of ATOM4. Correct it.
>  arch/riscv/include/asm/arch-jh7110/eeprom.h         |  5 +++++
>  board/starfive/visionfive2/visionfive2-i2c-eeprom.c | 11 ++---------
>  2 files changed, 7 insertions(+), 9 deletions(-)
> 
> index 1ae9f2b840a..8b689a75013 100644
> @@ -9,6 +9,11 @@
> + * get_pcb_revision_from_eeprom() - get the PCB revision
> + *
> + * @return: the PCB revision or 0 on error.
> + */
> index ca5039ee433..986dcc94992 100644
> @@ -535,19 +535,12 @@ int mac_read_from_eeprom(void)
>  	return 0;
>  }
>  
> -/**
> - * get_pcb_revision_from_eeprom - get the PCB revision
> - *
> - * 1.2A return 'A'/'a', 1.3B return 'B'/'b',other values are illegal
> - */
>  u8 get_pcb_revision_from_eeprom(void)
>  {
> -	u8 pv = 0xFF;
> -
>  	if (read_eeprom())
> -		return pv;
> +		return 0;
>  
> -	return pbuf.eeprom.atom1.data.pstr[6];
> +	return pbuf.eeprom.atom4.data.pcb_revision;
>  }
>  
>  u8 get_ddr_size_from_eeprom(void)

LGTM

---

From: E Shattow <[email-masked]>
Date: Fri, 24 Oct 2025 05:41:03 -0700

On 10/24/25 01:59, Hal Feng wrote:
> Add eeprom data format v3 support. Add onboard_module field in
> ATOM4 and add "mac onboard_module <?>" command to modify it.
> 
> The onboard module field marks the additional modules compared
> with VisionFive 2 board. Now we define
> 
> bit7-1: reserved, bit0: WIFI/BT
> 
>  .../visionfive2/visionfive2-i2c-eeprom.c      | 36 +++++++++++++++++--
>  1 file changed, 34 insertions(+), 2 deletions(-)
> 
> index 986dcc94992..b9197cdd34f 100644
> @@ -105,7 +105,8 @@ struct eeprom_atom4_data {
>  	u8 bom_revision;		/* BOM version */
>  	u8 mac0_addr[MAC_ADDR_BYTES];	/* Ethernet0 MAC */
>  	u8 mac1_addr[MAC_ADDR_BYTES];	/* Ethernet1 MAC */
> -	u8 reserved[2];
> +	u8 onboard_module;	/* Onboard module flag: bit7-1: reserved, bit0: WIFI/BT */
> +	u8 reserved;
>  };
>  
>  struct starfive_eeprom_atom4 {
> @@ -176,7 +177,7 @@ static void show_eeprom(void)
>  	printf("Vendor : %s\n", pbuf.eeprom.atom1.data.vstr);
>  	printf("Product full SN: %s\n", pbuf.eeprom.atom1.data.pstr);
>  	printf("data version: 0x%x\n", pbuf.eeprom.atom4.data.version);
> -	if (pbuf.eeprom.atom4.data.version == 2) {
> +	if (pbuf.eeprom.atom4.data.version == 2 || pbuf.eeprom.atom4.data.version == 3) {

small nit, maybe as two lines:

        if (pbuf.eeprom.atom4.data.version == 2 ||
            pbuf.eeprom.atom4.data.version == 3) {

>  		printf("PCB revision: 0x%x\n", pbuf.eeprom.atom4.data.pcb_revision);
>  		printf("BOM revision: %c\n", pbuf.eeprom.atom4.data.bom_revision);
>  		printf("Ethernet MAC0 address: %02x:%02x:%02x:%02x:%02x:%02x\n",
> @@ -187,6 +188,14 @@ static void show_eeprom(void)
>  		       pbuf.eeprom.atom4.data.mac1_addr[0], pbuf.eeprom.atom4.data.mac1_addr[1],
>  		       pbuf.eeprom.atom4.data.mac1_addr[2], pbuf.eeprom.atom4.data.mac1_addr[3],
>  		       pbuf.eeprom.atom4.data.mac1_addr[4], pbuf.eeprom.atom4.data.mac1_addr[5]);

I guess that the previous author must have 100col (?) not 80col for
editing. It is readable in 100col but just a little unusual on a
collaborative project in git repo to write code this way. It is not
anything you are the author for, so ignore my review comment here.

> +		if (pbuf.eeprom.atom4.data.version == 3) {
> +			char str[25] = "Onboard module: ";
> +
> +			if (pbuf.eeprom.atom4.data.onboard_module & BIT(0))
> +				strcat(str, "WIFI/BT");
> +
> +			printf("%s\n", str);
> +		}

I am concerned about a memory safety code mistake in future with this.
Let the compiler do our work for us. Avoid strcat or requirement that
the programmer knows buffer length for a scoped string allocation and
several other actions, as:

if (pbuf.eeprom.atom4.data.version == 3) {
	printf("Onboard module: %s\n",
	       (pbuf.eeprom.atom4.data.onboard_module & BIT(0) ?
	       "WIFI/BT" :
	       "None"));
}

>  	} else {
>  		printf("Custom data v%d is not Supported\n", pbuf.eeprom.atom4.data.version);
>  		dump_raw_eeprom();
> @@ -260,6 +269,7 @@ static void init_local_copy(void)
>  	pbuf.eeprom.atom4.data.bom_revision = BOM_VERSION;
>  	set_mac_address(STARFIVE_DEFAULT_MAC0, 0);
>  	set_mac_address(STARFIVE_DEFAULT_MAC1, 1);
> +	pbuf.eeprom.atom4.data.onboard_module = 0;
>  }
>  
>  /**
> @@ -385,6 +395,23 @@ static void set_bom_revision(char *string)
>  	update_crc();
>  }
>  
> +/**
> + * set_onboard_module() - stores a StarFive onboard module flag into the local EEPROM copy
> + *
> + * Takes a pointer to a string representing the numeric onboard module flag in
> + * Hexadecimal ("0" - "FF"), stores it in the onboard_module field of the
> + * EEPROM local copy, and updates the CRC of the local copy.
> + */
> +static void set_onboard_module(char *string)
> +{
> +	u8 onboard_module;
> +
> +	onboard_module = simple_strtoul(string, &string, 16);
> +	pbuf.eeprom.atom4.data.onboard_module = onboard_module;
> +
> +	update_crc();
> +}
> +
>  /**
>   * set_product_id() - stores a StarFive product ID into the local EEPROM copy
>   *
> @@ -478,6 +505,9 @@ int do_mac(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
>  	} else if (!strcmp(cmd, "bom_revision")) {
>  		set_bom_revision(argv[2]);
>  		return 0;
> +	} else if (!strcmp(cmd, "onboard_module")) {
> +		set_onboard_module(argv[2]);
> +		return 0;
>  	} else if (!strcmp(cmd, "product_id")) {
>  		set_product_id(argv[2]);
>  		return 0;
> @@ -585,6 +615,8 @@ U_BOOT_LONGHELP(mac,
>  	"    - stores a StarFive PCB revision into the local EEPROM copy\n"
>  	"mac bom_revision <A>\n"
>  	"    - stores a StarFive BOM revision into the local EEPROM copy\n"
> +	"mac onboard_module <?>\n"

Seeing the example of product_id would this onboard_module flag be
described as <xx> and not <?> ?

I understand that pcb_revision is stated as <?> however a pcb_revision
of zero value is not a sensible value because of the error handling, so
that can be different.

> +	"    - stores a StarFive onboard module flag into the local EEPROM copy\n"
>  	"mac product_id <VF7110A1-2228-D008E000-xxxxxxxx>\n"
>  	"    - stores a StarFive product ID into the local EEPROM copy\n"
>  	"mac vendor <Vendor Name>\n"

Looks good to me with only some nits about style choices. With that,

---

From: E Shattow <[email-masked]>
Date: Fri, 24 Oct 2025 06:09:40 -0700

On 10/24/25 01:59, Hal Feng wrote:
> Get and enable a optional power gpio. This feature is ported
> from the jh7110 pcie driver in Linux. VisionFive 2 Lite needs
> this gpio to enable the PCI bus device (M.2 M-Key) power.
> 

That's alright. Good.

>  drivers/pci/pcie_starfive_jh7110.c | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/drivers/pci/pcie_starfive_jh7110.c b/drivers/pci/pcie_starfive_jh7110.c
> index 0908ae16b67..04088b48ddc 100644
> --- a/drivers/pci/pcie_starfive_jh7110.c
> +++ b/drivers/pci/pcie_starfive_jh7110.c
> @@ -45,6 +45,7 @@ struct starfive_pcie {
>  	struct pcie_plda plda;
>  	struct clk_bulk	clks;
>  	struct reset_ctl_bulk	rsts;
> +	struct gpio_desc	power_gpio;
>  	struct gpio_desc	reset_gpio;
>  	struct regmap *regmap;
>  	unsigned int stg_pcie_base;
> @@ -184,6 +185,10 @@ static int starfive_pcie_parse_dt(struct udevice *dev)
>  		dev_err(dev, "reset-gpio is not valid\n");
>  		return -EINVAL;
>  	}
> +
> +	gpio_request_by_name(dev, "enable-gpios", 0, &priv->power_gpio,
> +			     GPIOD_IS_OUT);
> +

Are we missing some error handling here? I don't know, everything else
above in the function is verbose with the dev_err() reporting.

>  	return 0;
>  }
>  
> @@ -205,6 +210,9 @@ static int starfive_pcie_init_port(struct udevice *dev)
>  		goto err_deassert_clk;
>  	}
>  
> +	if (dm_gpio_is_valid(&priv->power_gpio))
> +		dm_gpio_set_value(&priv->power_gpio, 1);
> +
>  	dm_gpio_set_value(&priv->reset_gpio, 1);
>  	/* Disable physical functions except #0 */
>  	for (i = 1; i < PLDA_FUNC_NUM; i++) {

With that,

---

From: Hal Feng <[email-masked]>
Date: Fri, 24 Oct 2025 16:59:23 +0800

VisionFive 2 Lite is a mini SBC based on the StarFive JH7110S industrial
SoC which can run at -40~85 degrees centigrade and up to 1.25GHz.

Board features:
- JH7110S SoC
- 4/8 GiB LPDDR4 DRAM
- AXP15060 PMIC
- 40 pin GPIO header
- 1x USB 3.0 host port
- 3x USB 2.0 host port
- 1x M.2 M-Key (size: 2242)
- 1x MicroSD slot (optional non-removable 64GiB eMMC)
- 1x QSPI Flash
- 1x I2C EEPROM
- 1x 1Gbps Ethernet port
- SDIO-based Wi-Fi & UART-based Bluetooth
- 1x HDMI port
- 1x 2-lane DSI
- 1x 2-lane CSI

VisionFive 2 Lite schematics: https://doc-en.rvspace.org/VisionFive2Lite/PDF/VF2_LITE_V1.10_TF_20250818_SCH.pdf
VisionFive 2 Lite Quick Start Guide: https://doc-en.rvspace.org/VisionFive2Lite/VisionFive2LiteQSG/index.html
More documents: https://doc-en.rvspace.org/Doc_Center/visionfive_2_lite.html

Note: Patch 1 and 2 are the kernel device tree picked from [1]. They are
just for test and please ignore them because dts/upstream should be synced
with devicetree-rebasing.

Changes since RFC:
- Rebase on the latest mainline.
- Improve the commit messages.
- Drop patch 7.
patch 3, 4:
- Return 0 instead of 0xFF if read_eeprom() fails.
patch 5:
- Keep default FORMAT_VERSION 0x2.
- Change wifi_bt field to onboard_module field and use bit 0 to mark
  WIFI/BT.
- Drop all "no_eth0", "no_eth1" configuration.

History:
RFC: https://lore.kernel.org/all/[email-masked]/

Hal Feng (9):
  riscv: dts: starfive: jh7110-common: Move out some nodes to the board
    dts
  riscv: dts: starfive: Add VisionFive 2 Lite board device tree
  eeprom: starfive: Simplify get_ddr_size_from_eeprom()
  eeprom: starfive: Correct get_pcb_revision_from_eeprom()
  eeprom: starfive: Support eeprom data format v3
  pcie: starfive: Add a optional power gpio support
  configs: visionfive2: Add VisionFive 2 Lite DT to OF_LIST
  board: starfive: spl: Support VisionFive 2 Lite
  board: starfive: visionfive2: Add VisionFive 2 Lite fdt selection

 arch/riscv/cpu/jh7110/spl.c                   |   2 +-
 arch/riscv/include/asm/arch-jh7110/eeprom.h   |  13 +-
 board/starfive/visionfive2/spl.c              |   3 +
 .../visionfive2/starfive_visionfive2.c        |   2 +
 .../visionfive2/visionfive2-i2c-eeprom.c      |  64 ++++---
 configs/starfive_visionfive2_defconfig        |   2 +-
 drivers/pci/pcie_starfive_jh7110.c            |   8 +
 .../src/riscv/starfive/jh7110-common.dtsi     |  22 ---
 .../jh7110-deepcomputing-fml13v01.dts         |  49 ++++++
 .../src/riscv/starfive/jh7110-milkv-mars.dts  |  49 ++++++
 .../riscv/starfive/jh7110-pine64-star64.dts   |  49 ++++++
 .../jh7110-starfive-visionfive-2.dtsi         |  46 +++++
 dts/upstream/src/riscv/starfive/jh7110.dtsi   |  16 --
 .../jh7110s-starfive-visionfive-2-lite.dts    | 159 ++++++++++++++++++
 14 files changed, 418 insertions(+), 66 deletions(-)
 create mode 100644 dts/upstream/src/riscv/starfive/jh7110s-starfive-visionfive-2-lite.dts

base-commit: b10c055d4e1b5153a331a61ef82a5b01b5bb4c45
-- 
2.43.2

---

From: Hal Feng <[email-masked]>
Date: Fri, 24 Oct 2025 16:59:24 +0800

@@ -299,12 +293,7 @@
 
 	mmc0_pins: mmc0-0 {
-		 rst-pins {
 
+&cpu_opp {
+	opp-375000000 {
+		opp-hz = /bits/ 64 <375000000>;
+		opp-microvolt = <800000>;
+	};
+	opp-500000000 {
+		opp-hz = /bits/ 64 <500000000>;
+		opp-microvolt = <800000>;
+	};
+	opp-750000000 {
+		opp-hz = /bits/ 64 <750000000>;
+		opp-microvolt = <800000>;
+	};
+	opp-1500000000 {
+		opp-hz = /bits/ 64 <1500000000>;
+		opp-microvolt = <1040000>;
+	};
+};
+
+&mmc0 {
+	cap-mmc-highspeed;
+	cap-mmc-hw-reset;
+	mmc-ddr-1_8v;
+	mmc-hs200-1_8v;
+	vmmc-supply = <&vcc_3v3>;
+	vqmmc-supply = <&emmc_vdd>;
+};
+
+&mmc0_pins {
+	rst-pins {
+		pinmux = <GPIOMUX(62, GPOUT_SYS_SDIO0_RST,
+				      GPOEN_ENABLE,
+				      GPI_NONE)>;
+		bias-pull-up;
+		drive-strength = <12>;
+		input-disable;
+		input-schmitt-disable;
+		slew-rate = <0>;
+	};
+};
+
+&mmc1 {
+	no-sdio;
+	no-mmc;
+	cd-gpios = <&sysgpio 41 GPIO_ACTIVE_LOW>;
+	disable-wp;
+	post-power-on-delay-ms = <200>;
+};
+
 &pcie1 {
 	perst-gpios = <&sysgpio 21 GPIO_ACTIVE_LOW>;
 	phys = <&pciephy1>;
diff --git a/dts/upstream/src/riscv/starfive/jh7110-milkv-mars.dts b/dts/upstream/src/riscv/starfive/jh7110-milkv-mars.dts
index fdaf6b4557d..96f6b2f072d 100644
--- a/dts/upstream/src/riscv/starfive/jh7110-milkv-mars.dts
+++ b/dts/upstream/src/riscv/starfive/jh7110-milkv-mars.dts
@@ -11,6 +11,25 @@
 	compatible = "milkv,mars", "starfive,jh7110";
 };
 
+&cpu_opp {
+	opp-375000000 {
+		opp-hz = /bits/ 64 <375000000>;
+		opp-microvolt = <800000>;
+	};
+	opp-500000000 {
+		opp-hz = /bits/ 64 <500000000>;
+		opp-microvolt = <800000>;
+	};
+	opp-750000000 {
+		opp-hz = /bits/ 64 <750000000>;
+		opp-microvolt = <800000>;
+	};
+	opp-1500000000 {
+		opp-hz = /bits/ 64 <1500000000>;
+		opp-microvolt = <1040000>;
+	};
+};
+
 &gmac0 {
 	assigned-clocks = <&aoncrg JH7110_AONCLK_GMAC0_TX>;
 	assigned-clock-parents = <&aoncrg JH7110_AONCLK_GMAC0_RMII_RTX>;
@@ -22,6 +41,36 @@
 	status = "okay";
 };
 
+&mmc0 {
+	cap-mmc-highspeed;
+	cap-mmc-hw-reset;
+	mmc-ddr-1_8v;
+	mmc-hs200-1_8v;
+	vmmc-supply = <&vcc_3v3>;
+	vqmmc-supply = <&emmc_vdd>;
+};
+
+&mmc0_pins {
+	rst-pins {
+		pinmux = <GPIOMUX(62, GPOUT_SYS_SDIO0_RST,
+				      GPOEN_ENABLE,
+				      GPI_NONE)>;
+		bias-pull-up;
+		drive-strength = <12>;
+		input-disable;
+		input-schmitt-disable;
+		slew-rate = <0>;
+	};
+};
+
+&mmc1 {
+	no-sdio;
+	no-mmc;
+	cd-gpios = <&sysgpio 41 GPIO_ACTIVE_LOW>;
+	disable-wp;
+	post-power-on-delay-ms = <200>;
+};
+
 &pcie0 {
 	status = "okay";
 };
diff --git a/dts/upstream/src/riscv/starfive/jh7110-pine64-star64.dts b/dts/upstream/src/riscv/starfive/jh7110-pine64-star64.dts
index 31e825be206..c9677aef9ff 100644
--- a/dts/upstream/src/riscv/starfive/jh7110-pine64-star64.dts
+++ b/dts/upstream/src/riscv/starfive/jh7110-pine64-star64.dts
@@ -14,6 +14,25 @@
 	};
 };
 
+&cpu_opp {
+	opp-375000000 {
+		opp-hz = /bits/ 64 <375000000>;
+		opp-microvolt = <800000>;
+	};
+	opp-500000000 {
+		opp-hz = /bits/ 64 <500000000>;
+		opp-microvolt = <800000>;
+	};
+	opp-750000000 {
+		opp-hz = /bits/ 64 <750000000>;
+		opp-microvolt = <800000>;
+	};
+	opp-1500000000 {
+		opp-hz = /bits/ 64 <1500000000>;
+		opp-microvolt = <1040000>;
+	};
+};
+
 &gmac0 {
 	starfive,tx-use-rgmii-clk;
 	assigned-clocks = <&aoncrg JH7110_AONCLK_GMAC0_TX>;
@@ -44,6 +63,36 @@
 	status = "okay";
 };
 
+&mmc0 {
+	cap-mmc-highspeed;
+	cap-mmc-hw-reset;
+	mmc-ddr-1_8v;
+	mmc-hs200-1_8v;
+	vmmc-supply = <&vcc_3v3>;
+	vqmmc-supply = <&emmc_vdd>;
+};
+
+&mmc0_pins {
+	rst-pins {
+		pinmux = <GPIOMUX(62, GPOUT_SYS_SDIO0_RST,
+				      GPOEN_ENABLE,
+				      GPI_NONE)>;
+		bias-pull-up;
+		drive-strength = <12>;
+		input-disable;
+		input-schmitt-disable;
+		slew-rate = <0>;
+	};
+};
+
+&mmc1 {
+	no-sdio;
+	no-mmc;
+	cd-gpios = <&sysgpio 41 GPIO_ACTIVE_LOW>;
+	disable-wp;
+	post-power-on-delay-ms = <200>;
+};
+
 &pcie1 {
 	status = "okay";
 };
diff --git a/dts/upstream/src/riscv/starfive/jh7110-starfive-visionfive-2.dtsi b/dts/upstream/src/riscv/starfive/jh7110-starfive-visionfive-2.dtsi
index 5f14afb2c24..d1e4206f125 100644
--- a/dts/upstream/src/riscv/starfive/jh7110-starfive-visionfive-2.dtsi
+++ b/dts/upstream/src/riscv/starfive/jh7110-starfive-visionfive-2.dtsi
@@ -13,6 +13,25 @@
 	};
 };
 
+&cpu_opp {
+	opp-375000000 {
+		opp-hz = /bits/ 64 <375000000>;
+		opp-microvolt = <800000>;
+	};
+	opp-500000000 {
+		opp-hz = /bits/ 64 <500000000>;
+		opp-microvolt = <800000>;
+	};
+	opp-750000000 {
+		opp-hz = /bits/ 64 <750000000>;
+		opp-microvolt = <800000>;
+	};
+	opp-1500000000 {
+		opp-hz = /bits/ 64 <1500000000>;
+		opp-microvolt = <1040000>;
+	};
+};
+
 &gmac0 {
 	status = "okay";
 };
@@ -38,9 +57,36 @@
 };
 
 &mmc0 {
+	cap-mmc-highspeed;
+	cap-mmc-hw-reset;
+	mmc-ddr-1_8v;
+	mmc-hs200-1_8v;
+	vmmc-supply = <&vcc_3v3>;
+	vqmmc-supply = <&emmc_vdd>;
 	non-removable;
 };
 
+&mmc0_pins {
+	rst-pins {
+		pinmux = <GPIOMUX(62, GPOUT_SYS_SDIO0_RST,
+				      GPOEN_ENABLE,
+				      GPI_NONE)>;
+		bias-pull-up;
+		drive-strength = <12>;
+		input-disable;
+		input-schmitt-disable;
+		slew-rate = <0>;
+	};
+};
+
+&mmc1 {
+	no-sdio;
+	no-mmc;
+	cd-gpios = <&sysgpio 41 GPIO_ACTIVE_LOW>;
+	disable-wp;
+	post-power-on-delay-ms = <200>;
+};
+
 &pcie0 {
 	status = "okay";
 };
diff --git a/dts/upstream/src/riscv/starfive/jh7110.dtsi b/dts/upstream/src/riscv/starfive/jh7110.dtsi
index 0ba74ef0467..d2463399b95 100644
--- a/dts/upstream/src/riscv/starfive/jh7110.dtsi
+++ b/dts/upstream/src/riscv/starfive/jh7110.dtsi
@@ -200,22 +200,6 @@
 	cpu_opp: opp-table-0 {
 			compatible = "operating-points-v2";
 			opp-shared;
-			opp-375000000 {
-					opp-hz = /bits/ 64 <375000000>;
-					opp-microvolt = <800000>;
-			};
-			opp-500000000 {
-					opp-hz = /bits/ 64 <500000000>;
-					opp-microvolt = <800000>;
-			};
-			opp-750000000 {
-					opp-hz = /bits/ 64 <750000000>;
-					opp-microvolt = <800000>;
-			};
-			opp-1500000000 {
-					opp-hz = /bits/ 64 <1500000000>;
-					opp-microvolt = <1040000>;
-			};
 	};
 
 	thermal-zones {
-- 
2.43.2

---

From: Hal Feng <[email-masked]>
Date: Fri, 24 Oct 2025 16:59:27 +0800

#include <linux/types.h>
 
+/**
 
 /**
 
-/**

---

From: Hal Feng <[email-masked]>
Date: Fri, 24 Oct 2025 16:59:30 +0800

So the VisionFive 2 Lite DT will be built and merged into FIT.

Reviewed-by: E Shattow <[email-masked]>
Signed-off-by: Hal Feng <[email-masked]>
---
 configs/starfive_visionfive2_defconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/configs/starfive_visionfive2_defconfig b/configs/starfive_visionfive2_defconfig
index 34ebf3b605b..005091ce1f5 100644
--- a/configs/starfive_visionfive2_defconfig
+++ b/configs/starfive_visionfive2_defconfig
@@ -79,7 +79,7 @@ CONFIG_CMD_WGET=y
 CONFIG_CMD_BOOTSTAGE=y
 CONFIG_OF_BOARD=y
 CONFIG_DEVICE_TREE_INCLUDES="starfive-visionfive2-u-boot.dtsi"
-CONFIG_OF_LIST="starfive/jh7110-deepcomputing-fml13v01 starfive/jh7110-milkv-mars starfive/jh7110-pine64-star64 starfive/jh7110-starfive-visionfive-2-v1.2a starfive/jh7110-starfive-visionfive-2-v1.3b"
+CONFIG_OF_LIST="starfive/jh7110-deepcomputing-fml13v01 starfive/jh7110-milkv-mars starfive/jh7110-pine64-star64 starfive/jh7110-starfive-visionfive-2-v1.2a starfive/jh7110-starfive-visionfive-2-v1.3b starfive/jh7110s-starfive-visionfive-2-lite"
 CONFIG_MULTI_DTB_FIT=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_SPI_FLASH=y
-- 
2.43.2

---

From: Hal Feng <[email-masked]>
Date: Fri, 24 Oct 2025 16:59:25 +0800

Board features:
- JH7110S SoC
- 2/4/8 GiB LPDDR4 DRAM
- AXP15060 PMIC
- 40 pin GPIO header
- 1x USB 3.0 host port
- 3x USB 2.0 host port

diff --git a/dts/upstream/src/riscv/starfive/jh7110s-starfive-visionfive-2-lite.dts b/dts/upstream/src/riscv/starfive/jh7110s-starfive-visionfive-2-lite.dts
new file mode 100644
index 00000000000..30842b0cd1f
--- /dev/null
+++ b/dts/upstream/src/riscv/starfive/jh7110s-starfive-visionfive-2-lite.dts
@@ -0,0 +1,159 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2025 StarFive Technology Co., Ltd.
+ * Copyright (C) 2025 Hal Feng <[email-masked]>
+ */
+
+/dts-v1/;
+#include "jh7110-common.dtsi"
+
+/ {
+	model = "StarFive VisionFive 2 Lite";
+	compatible = "starfive,visionfive-2-lite", "starfive,jh7110s";
+};
+
+&cpu_opp {
+	opp-312500000 {
+		opp-hz = /bits/ 64 <312500000>;
+		opp-microvolt = <800000>;
+	};
+	opp-417000000 {
+		opp-hz = /bits/ 64 <417000000>;
+		opp-microvolt = <800000>;
+	};
+	opp-625000000 {
+		opp-hz = /bits/ 64 <625000000>;
+		opp-microvolt = <800000>;
+	};
+	opp-1250000000 {
+		opp-hz = /bits/ 64 <1250000000>;
+		opp-microvolt = <1000000>;
+	};
+};
+
+&gmac0 {
+	starfive,tx-use-rgmii-clk;
+	assigned-clocks = <&aoncrg JH7110_AONCLK_GMAC0_TX>;
+	assigned-clock-parents = <&aoncrg JH7110_AONCLK_GMAC0_RMII_RTX>;
+	status = "okay";
+};
+
+&i2c0 {
+	status = "okay";
+};
+
+&mmc0 {
+	bus-width = <4>;
+	no-sdio;
+	no-mmc;
+	cd-gpios = <&sysgpio 41 GPIO_ACTIVE_HIGH>;
+	disable-wp;
+	cap-sd-highspeed;
+};
+
+&mmc1 {
+	max-frequency = <50000000>;
+	keep-power-in-suspend;
+	non-removable;
+};
+
+&pcie1 {
+	enable-gpios = <&sysgpio 27 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+};
+
+&phy0 {
+	motorcomm,tx-clk-adj-enabled;
+	motorcomm,tx-clk-100-inverted;
+	motorcomm,tx-clk-1000-inverted;
+	motorcomm,rx-clk-drv-microamp = <3970>;
+	motorcomm,rx-data-drv-microamp = <2910>;
+	rx-internal-delay-ps = <1500>;
+	tx-internal-delay-ps = <1500>;
+};
+
+&pwm {
+	status = "okay";
+};
+
+&spi0 {
+	status = "okay";
+};
+
+&syscrg {
+	assigned-clock-rates = <0>, <0>, <0>, <0>, <500000000>, <1250000000>;
+};
+
+&sysgpio {
+	uart1_pins: uart1-0 {
+		tx-pins {
+			pinmux = <GPIOMUX(22, GPOUT_SYS_UART1_TX,
+					      GPOEN_ENABLE,
+					      GPI_NONE)>;
+			bias-disable;
+			drive-strength = <12>;
+			input-disable;
+			input-schmitt-disable;
+			slew-rate = <0>;
+		};
+
+		rx-pins {
+			pinmux = <GPIOMUX(23, GPOUT_LOW,
+					      GPOEN_DISABLE,
+					      GPI_SYS_UART1_RX)>;
+			bias-pull-up;
+			drive-strength = <2>;
+			input-enable;
+			input-schmitt-enable;
+			slew-rate = <0>;
+		};
+
+		cts-pins {
+			pinmux = <GPIOMUX(24, GPOUT_LOW,
+					      GPOEN_DISABLE,
+					      GPI_SYS_UART1_CTS)>;
+			input-enable;
+		};
+
+		rts-pins {
+			pinmux = <GPIOMUX(25, GPOUT_SYS_UART1_RTS,
+					      GPOEN_ENABLE,
+					      GPI_NONE)>;
+			input-enable;
+		};
+	};
+
+	usb0_pins: usb0-0 {
+		power-pins {
+			pinmux = <GPIOMUX(26, GPOUT_HIGH,
+					      GPOEN_ENABLE,
+					      GPI_NONE)>;
+			input-disable;
+		};
+
+		switch-pins {
+			pinmux = <GPIOMUX(62, GPOUT_LOW,
+					      GPOEN_ENABLE,
+					      GPI_NONE)>;
+			input-disable;
+		};
+	};
+};
+
+&uart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart1_pins>;
+	status = "okay";
+};
+
+&usb0 {
+	dr_mode = "host";
+	pinctrl-names = "default";
+	pinctrl-0 = <&usb0_pins>;
+	status = "okay";
+};
+
+&usb_cdns3 {
+	phys = <&usbphy0>, <&pciephy0>;
+	phy-names = "cdns3,usb2-phy", "cdns3,usb3-phy";
+};
-- 
2.43.2

---

From: Hal Feng <[email-masked]>
Date: Fri, 24 Oct 2025 16:59:28 +0800

/**
 
+/**

---

From: Hal Feng <[email-masked]>
Date: Fri, 24 Oct 2025 16:59:29 +0800

---

From: Hal Feng <[email-masked]>
Date: Fri, 24 Oct 2025 16:59:31 +0800

Choose the matching FIT config on the VisionFive 2 Lite board.

Reviewed-by: E Shattow <[email-masked]>
Signed-off-by: Hal Feng <[email-masked]>
---
 board/starfive/visionfive2/spl.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/board/starfive/visionfive2/spl.c b/board/starfive/visionfive2/spl.c
index 48b034af305..b2eb04b3b82 100644
--- a/board/starfive/visionfive2/spl.c
+++ b/board/starfive/visionfive2/spl.c
@@ -132,6 +132,9 @@ int board_fit_config_name_match(const char *name)
 	} else if (!strcmp(name, "starfive/jh7110-starfive-visionfive-2-v1.3b") &&
 		    !strncmp(get_product_id_from_eeprom(), "VF7110B", 7)) {
 		return 0;
+	} else if (!strcmp(name, "starfive/jh7110s-starfive-visionfive-2-lite") &&
+		    !strncmp(get_product_id_from_eeprom(), "VF7110SL", 8)) {
+		return 0;
 	}
 
 	return -EINVAL;
-- 
2.43.2

---

From: Hal Feng <[email-masked]>
Date: Fri, 24 Oct 2025 16:59:32 +0800

Set $fdtfile to the VisionFive 2 Lite DTB if the board is matched.

Reviewed-by: E Shattow <[email-masked]>
Signed-off-by: Hal Feng <[email-masked]>
---
 board/starfive/visionfive2/starfive_visionfive2.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/board/starfive/visionfive2/starfive_visionfive2.c b/board/starfive/visionfive2/starfive_visionfive2.c
index 6271974b9c7..013ba63994e 100644
--- a/board/starfive/visionfive2/starfive_visionfive2.c
+++ b/board/starfive/visionfive2/starfive_visionfive2.c
@@ -63,6 +63,8 @@ static void set_fdtfile(void)
 		fdtfile = "starfive/jh7110-starfive-visionfive-2-v1.2a.dtb";
 	} else if (!strncmp(get_product_id_from_eeprom(), "VF7110B", 7)) {
 		fdtfile = "starfive/jh7110-starfive-visionfive-2-v1.3b.dtb";
+	} else if (!strncmp(get_product_id_from_eeprom(), "VF7110SL", 8)) {
+		fdtfile = "starfive/jh7110s-starfive-visionfive-2-lite.dtb";
 	} else {
 		log_err("Unknown product\n");
 		return;
-- 
2.43.2

---

From: Hal Feng <[email-masked]>
Date: Fri, 24 Oct 2025 16:59:26 +0800

/**
 
-/**

---

From: Hal Feng <[email-masked]>
Date: Mon, 27 Oct 2025 08:14:55 +0000

> On 24.10.25 18:58, E Shattow wrote:
> > [1]
> > https://lore.kernel.org/all/20250821100930.71404-1-hal.feng@starfivete
> > ch.com/
> >
> >  create mode 100644
> > diff --git
> > a/dts/upstream/src/riscv/starfive/jh7110s-starfive-visionfive-2-lite.d
> > ts
> > b/dts/upstream/src/riscv/starfive/jh7110s-starfive-visionfive-2-lite.d
> > ts
> > new file mode 100644
> > +++ b/dts/upstream/src/riscv/starfive/jh7110s-starfive-visionfive-2-li
> > +++ te.dts
> > @@ -0,0 +1,159 @@
> > + * Copyright (C) 2025 Hal Feng <[email-masked]>  */
> > +
> > +/dts-v1/;
> > +	compatible = "starfive,visionfive-2-lite", "starfive,jh7110s"; };
> ...
> 
> FYI as a follow-up to my earlier comments about modifying the dts subtree I
> have now a working recommendation:
> 
> 1). Return to using "RFC" subject prefix for the series while any modification
> exists to dts subtree. The comment said about this is do not post any "DO
> NOT MERGE" type patches that touch dts subtree, however...
> 
> 2). Additions to CONFIG_OF_LIST will cause a build error if there is not any
> corresponding file in the dts subtree. Use a workaround:
> 
> git mv

Thank you for providing another way to deal with this situation.

With your method, 
1. The situation will be more complicated in this patch, because I try to modify the
common dtsi (jh7110-common.dtsi).
2. The maintainers have to revert the temporary device trees we added in arch/riscv/dts/
after the same device trees appear in dts/upstream/src/riscv/starfive/. It will bring more
work to the OF_UPSTREAM maintainers.

I think it may be easier for maintainers to merge the u-boot patches after the
Linux device trees has already appeared in dts/upstream/.

> "/path/to/linux.git/arch/riscv/boot/dts/starfive/jh7110s-starfive-visionfive-2-

Maybe you mean "/path/to/linux.git/arch/riscv/boot/dts/starfive/jh7110s-starfive-visionfive-2-lite.dts"

> automatically when there is a corresponding file (empty file is okay) in dts
> subtree. The empty file in dts subtree is a simple git file operation with no
> actual content. It is not perfect as an answer but it is better for the review
> now, and for anyone else reading this that may want to do the same.
> 
> You can see this in the working example of RFC v1 series for Milk-V Mars CM
> re-introduction:
> 
> 3). If you follow RFC -> PATCH -> RFC the version does increment (RFC v1,
> PATCH v2, RFC v3, ...)

Thanks for your suggestions.

Best regards,
Hal

---

From: Hal Feng <[email-masked]>
Date: Mon, 27 Oct 2025 08:26:30 +0000

> On 24.10.25 21:10, E Shattow wrote:
> > Get and enable a optional power gpio. This feature is ported from the
> > jh7110 pcie driver in Linux. VisionFive 2 Lite needs this gpio to
> > enable the PCI bus device (M.2 M-Key) power.
> >
> 
> That's alright. Good.
> 

The power gpio is optional, so I did not handle the error return here.

Best regards,
Hal