{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 132 02/25/2009 SJ Full Version " "Info: Version 9.0 Build 132 02/25/2009 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Fri May 24 15:37:57 2019 " "Info: Processing started: Fri May 24 15:37:57 2019" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off test -c test " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off test -c test" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Info: Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0 "" 0 -1}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0 -1}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk1M " "Info: Assuming node \"clk1M\" is an undefined clock" {  } { { "test.vhd" "" { Text "D:/Quartus Project/test/test.vhd" 9 -1 0 } } { "d:/program files (x86)/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files (x86)/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk1M" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0 -1}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0 -1}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk1M register counter\[21\] register counter\[5\] 82.6 MHz 12.106 ns Internal " "Info: Clock \"clk1M\" has Internal fmax of 82.6 MHz between source register \"counter\[21\]\" and destination register \"counter\[5\]\" (period= 12.106 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "11.397 ns + Longest register register " "Info: + Longest register to register delay is 11.397 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns counter\[21\] 1 REG LC_X6_Y2_N5 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X6_Y2_N5; Fanout = 3; REG Node = 'counter\[21\]'" {  } { { "d:/program files (x86)/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files (x86)/quartus/bin/TimingClosureFloorplan.fld" "" "" { counter[21] } "NODE_NAME" } } { "test.vhd" "" { Text "D:/Quartus Project/test/test.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.962 ns) + CELL(0.511 ns) 1.473 ns Equal0~2 2 COMB LC_X6_Y2_N8 1 " "Info: 2: + IC(0.962 ns) + CELL(0.511 ns) = 1.473 ns; Loc. = LC_X6_Y2_N8; Fanout = 1; COMB Node = 'Equal0~2'" {  } { { "d:/program files (x86)/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files (x86)/quartus/bin/TimingClosureFloorplan.fld" "" "1.473 ns" { counter[21] Equal0~2 } "NODE_NAME" } } { "d:/program files (x86)/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/program files (x86)/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1871 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.926 ns) + CELL(0.511 ns) 3.910 ns Equal0~3 3 COMB LC_X4_Y2_N2 2 " "Info: 3: + IC(1.926 ns) + CELL(0.511 ns) = 3.910 ns; Loc. = LC_X4_Y2_N2; Fanout = 2; COMB Node = 'Equal0~3'" {  } { { "d:/program files (x86)/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files (x86)/quartus/bin/TimingClosureFloorplan.fld" "" "2.437 ns" { Equal0~2 Equal0~3 } "NODE_NAME" } } { "d:/program files (x86)/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/program files (x86)/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1871 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.702 ns) + CELL(0.200 ns) 5.812 ns Equal1~1 4 COMB LC_X2_Y2_N5 2 " "Info: 4: + IC(1.702 ns) + CELL(0.200 ns) = 5.812 ns; Loc. = LC_X2_Y2_N5; Fanout = 2; COMB Node = 'Equal1~1'" {  } { { "d:/program files (x86)/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files (x86)/quartus/bin/TimingClosureFloorplan.fld" "" "1.902 ns" { Equal0~3 Equal1~1 } "NODE_NAME" } } { "d:/program files (x86)/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/program files (x86)/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.847 ns) + CELL(0.200 ns) 7.859 ns counter\[0\]~132 5 COMB LC_X6_Y2_N7 22 " "Info: 5: + IC(1.847 ns) + CELL(0.200 ns) = 7.859 ns; Loc. = LC_X6_Y2_N7; Fanout = 22; COMB Node = 'counter\[0\]~132'" {  } { { "d:/program files (x86)/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files (x86)/quartus/bin/TimingClosureFloorplan.fld" "" "2.047 ns" { Equal1~1 counter[0]~132 } "NODE_NAME" } } { "test.vhd" "" { Text "D:/Quartus Project/test/test.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.778 ns) + CELL(1.760 ns) 11.397 ns counter\[5\] 6 REG LC_X4_Y2_N9 5 " "Info: 6: + IC(1.778 ns) + CELL(1.760 ns) = 11.397 ns; Loc. = LC_X4_Y2_N9; Fanout = 5; REG Node = 'counter\[5\]'" {  } { { "d:/program files (x86)/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files (x86)/quartus/bin/TimingClosureFloorplan.fld" "" "3.538 ns" { counter[0]~132 counter[5] } "NODE_NAME" } } { "test.vhd" "" { Text "D:/Quartus Project/test/test.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.182 ns ( 27.92 % ) " "Info: Total cell delay = 3.182 ns ( 27.92 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "8.215 ns ( 72.08 % ) " "Info: Total interconnect delay = 8.215 ns ( 72.08 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "d:/program files (x86)/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files (x86)/quartus/bin/TimingClosureFloorplan.fld" "" "11.397 ns" { counter[21] Equal0~2 Equal0~3 Equal1~1 counter[0]~132 counter[5] } "NODE_NAME" } } { "d:/program files (x86)/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files (x86)/quartus/bin/Technology_Viewer.qrui" "11.397 ns" { counter[21] {} Equal0~2 {} Equal0~3 {} Equal1~1 {} counter[0]~132 {} counter[5] {} } { 0.000ns 0.962ns 1.926ns 1.702ns 1.847ns 1.778ns } { 0.000ns 0.511ns 0.511ns 0.200ns 0.200ns 1.760ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk1M destination 5.614 ns + Shortest register " "Info: + Shortest clock path from clock \"clk1M\" to destination register is 5.614 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns clk1M 1 CLK PIN_4 27 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_4; Fanout = 27; CLK Node = 'clk1M'" {  } { { "d:/program files (x86)/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files (x86)/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk1M } "NODE_NAME" } } { "test.vhd" "" { Text "D:/Quartus Project/test/test.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(3.564 ns) + CELL(0.918 ns) 5.614 ns counter\[5\] 2 REG LC_X4_Y2_N9 5 " "Info: 2: + IC(3.564 ns) + CELL(0.918 ns) = 5.614 ns; Loc. = LC_X4_Y2_N9; Fanout = 5; REG Node = 'counter\[5\]'" {  } { { "d:/program files (x86)/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files (x86)/quartus/bin/TimingClosureFloorplan.fld" "" "4.482 ns" { clk1M counter[5] } "NODE_NAME" } } { "test.vhd" "" { Text "D:/Quartus Project/test/test.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.050 ns ( 36.52 % ) " "Info: Total cell delay = 2.050 ns ( 36.52 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "3.564 ns ( 63.48 % ) " "Info: Total interconnect delay = 3.564 ns ( 63.48 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "d:/program files (x86)/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files (x86)/quartus/bin/TimingClosureFloorplan.fld" "" "5.614 ns" { clk1M counter[5] } "NODE_NAME" } } { "d:/program files (x86)/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files (x86)/quartus/bin/Technology_Viewer.qrui" "5.614 ns" { clk1M {} clk1M~combout {} counter[5] {} } { 0.000ns 0.000ns 3.564ns } { 0.000ns 1.132ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk1M source 5.614 ns - Longest register " "Info: - Longest clock path from clock \"clk1M\" to source register is 5.614 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns clk1M 1 CLK PIN_4 27 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_4; Fanout = 27; CLK Node = 'clk1M'" {  } { { "d:/program files (x86)/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files (x86)/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk1M } "NODE_NAME" } } { "test.vhd" "" { Text "D:/Quartus Project/test/test.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(3.564 ns) + CELL(0.918 ns) 5.614 ns counter\[21\] 2 REG LC_X6_Y2_N5 3 " "Info: 2: + IC(3.564 ns) + CELL(0.918 ns) = 5.614 ns; Loc. = LC_X6_Y2_N5; Fanout = 3; REG Node = 'counter\[21\]'" {  } { { "d:/program files (x86)/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files (x86)/quartus/bin/TimingClosureFloorplan.fld" "" "4.482 ns" { clk1M counter[21] } "NODE_NAME" } } { "test.vhd" "" { Text "D:/Quartus Project/test/test.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.050 ns ( 36.52 % ) " "Info: Total cell delay = 2.050 ns ( 36.52 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "3.564 ns ( 63.48 % ) " "Info: Total interconnect delay = 3.564 ns ( 63.48 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "d:/program files (x86)/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files (x86)/quartus/bin/TimingClosureFloorplan.fld" "" "5.614 ns" { clk1M counter[21] } "NODE_NAME" } } { "d:/program files (x86)/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files (x86)/quartus/bin/Technology_Viewer.qrui" "5.614 ns" { clk1M {} clk1M~combout {} counter[21] {} } { 0.000ns 0.000ns 3.564ns } { 0.000ns 1.132ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1}  } { { "d:/program files (x86)/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files (x86)/quartus/bin/TimingClosureFloorplan.fld" "" "5.614 ns" { clk1M counter[5] } "NODE_NAME" } } { "d:/program files (x86)/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files (x86)/quartus/bin/Technology_Viewer.qrui" "5.614 ns" { clk1M {} clk1M~combout {} counter[5] {} } { 0.000ns 0.000ns 3.564ns } { 0.000ns 1.132ns 0.918ns } "" } } { "d:/program files (x86)/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files (x86)/quartus/bin/TimingClosureFloorplan.fld" "" "5.614 ns" { clk1M counter[21] } "NODE_NAME" } } { "d:/program files (x86)/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files (x86)/quartus/bin/Technology_Viewer.qrui" "5.614 ns" { clk1M {} clk1M~combout {} counter[21] {} } { 0.000ns 0.000ns 3.564ns } { 0.000ns 1.132ns 0.918ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "test.vhd" "" { Text "D:/Quartus Project/test/test.vhd" 22 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "test.vhd" "" { Text "D:/Quartus Project/test/test.vhd" 22 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 -1}  } { { "d:/program files (x86)/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files (x86)/quartus/bin/TimingClosureFloorplan.fld" "" "11.397 ns" { counter[21] Equal0~2 Equal0~3 Equal1~1 counter[0]~132 counter[5] } "NODE_NAME" } } { "d:/program files (x86)/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files (x86)/quartus/bin/Technology_Viewer.qrui" "11.397 ns" { counter[21] {} Equal0~2 {} Equal0~3 {} Equal1~1 {} counter[0]~132 {} counter[5] {} } { 0.000ns 0.962ns 1.926ns 1.702ns 1.847ns 1.778ns } { 0.000ns 0.511ns 0.511ns 0.200ns 0.200ns 1.760ns } "" } } { "d:/program files (x86)/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files (x86)/quartus/bin/TimingClosureFloorplan.fld" "" "5.614 ns" { clk1M counter[5] } "NODE_NAME" } } { "d:/program files (x86)/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files (x86)/quartus/bin/Technology_Viewer.qrui" "5.614 ns" { clk1M {} clk1M~combout {} counter[5] {} } { 0.000ns 0.000ns 3.564ns } { 0.000ns 1.132ns 0.918ns } "" } } { "d:/program files (x86)/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files (x86)/quartus/bin/TimingClosureFloorplan.fld" "" "5.614 ns" { clk1M counter[21] } "NODE_NAME" } } { "d:/program files (x86)/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files (x86)/quartus/bin/Technology_Viewer.qrui" "5.614 ns" { clk1M {} clk1M~combout {} counter[21] {} } { 0.000ns 0.000ns 3.564ns } { 0.000ns 1.132ns 0.918ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0 -1}
{ "Info" "ITDB_TSU_RESULT" "counter\[5\] rstBtn clk1M 2.139 ns register " "Info: tsu for register \"counter\[5\]\" (data pin = \"rstBtn\", clock pin = \"clk1M\") is 2.139 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.420 ns + Longest pin register " "Info: + Longest pin to register delay is 7.420 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns rstBtn 1 PIN PIN_44 7 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_44; Fanout = 7; PIN Node = 'rstBtn'" {  } { { "d:/program files (x86)/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files (x86)/quartus/bin/TimingClosureFloorplan.fld" "" "" { rstBtn } "NODE_NAME" } } { "test.vhd" "" { Text "D:/Quartus Project/test/test.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.239 ns) + CELL(0.511 ns) 3.882 ns counter\[0\]~132 2 COMB LC_X6_Y2_N7 22 " "Info: 2: + IC(2.239 ns) + CELL(0.511 ns) = 3.882 ns; Loc. = LC_X6_Y2_N7; Fanout = 22; COMB Node = 'counter\[0\]~132'" {  } { { "d:/program files (x86)/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files (x86)/quartus/bin/TimingClosureFloorplan.fld" "" "2.750 ns" { rstBtn counter[0]~132 } "NODE_NAME" } } { "test.vhd" "" { Text "D:/Quartus Project/test/test.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.778 ns) + CELL(1.760 ns) 7.420 ns counter\[5\] 3 REG LC_X4_Y2_N9 5 " "Info: 3: + IC(1.778 ns) + CELL(1.760 ns) = 7.420 ns; Loc. = LC_X4_Y2_N9; Fanout = 5; REG Node = 'counter\[5\]'" {  } { { "d:/program files (x86)/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files (x86)/quartus/bin/TimingClosureFloorplan.fld" "" "3.538 ns" { counter[0]~132 counter[5] } "NODE_NAME" } } { "test.vhd" "" { Text "D:/Quartus Project/test/test.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.403 ns ( 45.86 % ) " "Info: Total cell delay = 3.403 ns ( 45.86 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "4.017 ns ( 54.14 % ) " "Info: Total interconnect delay = 4.017 ns ( 54.14 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "d:/program files (x86)/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files (x86)/quartus/bin/TimingClosureFloorplan.fld" "" "7.420 ns" { rstBtn counter[0]~132 counter[5] } "NODE_NAME" } } { "d:/program files (x86)/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files (x86)/quartus/bin/Technology_Viewer.qrui" "7.420 ns" { rstBtn {} rstBtn~combout {} counter[0]~132 {} counter[5] {} } { 0.000ns 0.000ns 2.239ns 1.778ns } { 0.000ns 1.132ns 0.511ns 1.760ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "test.vhd" "" { Text "D:/Quartus Project/test/test.vhd" 22 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk1M destination 5.614 ns - Shortest register " "Info: - Shortest clock path from clock \"clk1M\" to destination register is 5.614 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns clk1M 1 CLK PIN_4 27 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_4; Fanout = 27; CLK Node = 'clk1M'" {  } { { "d:/program files (x86)/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files (x86)/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk1M } "NODE_NAME" } } { "test.vhd" "" { Text "D:/Quartus Project/test/test.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(3.564 ns) + CELL(0.918 ns) 5.614 ns counter\[5\] 2 REG LC_X4_Y2_N9 5 " "Info: 2: + IC(3.564 ns) + CELL(0.918 ns) = 5.614 ns; Loc. = LC_X4_Y2_N9; Fanout = 5; REG Node = 'counter\[5\]'" {  } { { "d:/program files (x86)/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files (x86)/quartus/bin/TimingClosureFloorplan.fld" "" "4.482 ns" { clk1M counter[5] } "NODE_NAME" } } { "test.vhd" "" { Text "D:/Quartus Project/test/test.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.050 ns ( 36.52 % ) " "Info: Total cell delay = 2.050 ns ( 36.52 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "3.564 ns ( 63.48 % ) " "Info: Total interconnect delay = 3.564 ns ( 63.48 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "d:/program files (x86)/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files (x86)/quartus/bin/TimingClosureFloorplan.fld" "" "5.614 ns" { clk1M counter[5] } "NODE_NAME" } } { "d:/program files (x86)/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files (x86)/quartus/bin/Technology_Viewer.qrui" "5.614 ns" { clk1M {} clk1M~combout {} counter[5] {} } { 0.000ns 0.000ns 3.564ns } { 0.000ns 1.132ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1}  } { { "d:/program files (x86)/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files (x86)/quartus/bin/TimingClosureFloorplan.fld" "" "7.420 ns" { rstBtn counter[0]~132 counter[5] } "NODE_NAME" } } { "d:/program files (x86)/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files (x86)/quartus/bin/Technology_Viewer.qrui" "7.420 ns" { rstBtn {} rstBtn~combout {} counter[0]~132 {} counter[5] {} } { 0.000ns 0.000ns 2.239ns 1.778ns } { 0.000ns 1.132ns 0.511ns 1.760ns } "" } } { "d:/program files (x86)/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files (x86)/quartus/bin/TimingClosureFloorplan.fld" "" "5.614 ns" { clk1M counter[5] } "NODE_NAME" } } { "d:/program files (x86)/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files (x86)/quartus/bin/Technology_Viewer.qrui" "5.614 ns" { clk1M {} clk1M~combout {} counter[5] {} } { 0.000ns 0.000ns 3.564ns } { 0.000ns 1.132ns 0.918ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 -1}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk1M led3 led3_xhdl3 9.124 ns register " "Info: tco from clock \"clk1M\" to destination pin \"led3\" through register \"led3_xhdl3\" is 9.124 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk1M source 5.614 ns + Longest register " "Info: + Longest clock path from clock \"clk1M\" to source register is 5.614 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns clk1M 1 CLK PIN_4 27 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_4; Fanout = 27; CLK Node = 'clk1M'" {  } { { "d:/program files (x86)/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files (x86)/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk1M } "NODE_NAME" } } { "test.vhd" "" { Text "D:/Quartus Project/test/test.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(3.564 ns) + CELL(0.918 ns) 5.614 ns led3_xhdl3 2 REG LC_X2_Y4_N3 1 " "Info: 2: + IC(3.564 ns) + CELL(0.918 ns) = 5.614 ns; Loc. = LC_X2_Y4_N3; Fanout = 1; REG Node = 'led3_xhdl3'" {  } { { "d:/program files (x86)/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files (x86)/quartus/bin/TimingClosureFloorplan.fld" "" "4.482 ns" { clk1M led3_xhdl3 } "NODE_NAME" } } { "test.vhd" "" { Text "D:/Quartus Project/test/test.vhd" 77 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.050 ns ( 36.52 % ) " "Info: Total cell delay = 2.050 ns ( 36.52 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "3.564 ns ( 63.48 % ) " "Info: Total interconnect delay = 3.564 ns ( 63.48 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "d:/program files (x86)/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files (x86)/quartus/bin/TimingClosureFloorplan.fld" "" "5.614 ns" { clk1M led3_xhdl3 } "NODE_NAME" } } { "d:/program files (x86)/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files (x86)/quartus/bin/Technology_Viewer.qrui" "5.614 ns" { clk1M {} clk1M~combout {} led3_xhdl3 {} } { 0.000ns 0.000ns 3.564ns } { 0.000ns 1.132ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "test.vhd" "" { Text "D:/Quartus Project/test/test.vhd" 77 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.134 ns + Longest register pin " "Info: + Longest register to pin delay is 3.134 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns led3_xhdl3 1 REG LC_X2_Y4_N3 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X2_Y4_N3; Fanout = 1; REG Node = 'led3_xhdl3'" {  } { { "d:/program files (x86)/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files (x86)/quartus/bin/TimingClosureFloorplan.fld" "" "" { led3_xhdl3 } "NODE_NAME" } } { "test.vhd" "" { Text "D:/Quartus Project/test/test.vhd" 77 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.812 ns) + CELL(2.322 ns) 3.134 ns led3 2 PIN PIN_3 0 " "Info: 2: + IC(0.812 ns) + CELL(2.322 ns) = 3.134 ns; Loc. = PIN_3; Fanout = 0; PIN Node = 'led3'" {  } { { "d:/program files (x86)/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files (x86)/quartus/bin/TimingClosureFloorplan.fld" "" "3.134 ns" { led3_xhdl3 led3 } "NODE_NAME" } } { "test.vhd" "" { Text "D:/Quartus Project/test/test.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.322 ns ( 74.09 % ) " "Info: Total cell delay = 2.322 ns ( 74.09 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "0.812 ns ( 25.91 % ) " "Info: Total interconnect delay = 0.812 ns ( 25.91 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "d:/program files (x86)/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files (x86)/quartus/bin/TimingClosureFloorplan.fld" "" "3.134 ns" { led3_xhdl3 led3 } "NODE_NAME" } } { "d:/program files (x86)/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files (x86)/quartus/bin/Technology_Viewer.qrui" "3.134 ns" { led3_xhdl3 {} led3 {} } { 0.000ns 0.812ns } { 0.000ns 2.322ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1}  } { { "d:/program files (x86)/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files (x86)/quartus/bin/TimingClosureFloorplan.fld" "" "5.614 ns" { clk1M led3_xhdl3 } "NODE_NAME" } } { "d:/program files (x86)/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files (x86)/quartus/bin/Technology_Viewer.qrui" "5.614 ns" { clk1M {} clk1M~combout {} led3_xhdl3 {} } { 0.000ns 0.000ns 3.564ns } { 0.000ns 1.132ns 0.918ns } "" } } { "d:/program files (x86)/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files (x86)/quartus/bin/TimingClosureFloorplan.fld" "" "3.134 ns" { led3_xhdl3 led3 } "NODE_NAME" } } { "d:/program files (x86)/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files (x86)/quartus/bin/Technology_Viewer.qrui" "3.134 ns" { led3_xhdl3 {} led3 {} } { 0.000ns 0.812ns } { 0.000ns 2.322ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0 -1}
{ "Info" "ITDB_TH_RESULT" "led1_xhdl1 rstBtn clk1M 0.436 ns register " "Info: th for register \"led1_xhdl1\" (data pin = \"rstBtn\", clock pin = \"clk1M\") is 0.436 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk1M destination 5.614 ns + Longest register " "Info: + Longest clock path from clock \"clk1M\" to destination register is 5.614 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns clk1M 1 CLK PIN_4 27 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_4; Fanout = 27; CLK Node = 'clk1M'" {  } { { "d:/program files (x86)/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files (x86)/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk1M } "NODE_NAME" } } { "test.vhd" "" { Text "D:/Quartus Project/test/test.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(3.564 ns) + CELL(0.918 ns) 5.614 ns led1_xhdl1 2 REG LC_X2_Y4_N0 7 " "Info: 2: + IC(3.564 ns) + CELL(0.918 ns) = 5.614 ns; Loc. = LC_X2_Y4_N0; Fanout = 7; REG Node = 'led1_xhdl1'" {  } { { "d:/program files (x86)/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files (x86)/quartus/bin/TimingClosureFloorplan.fld" "" "4.482 ns" { clk1M led1_xhdl1 } "NODE_NAME" } } { "test.vhd" "" { Text "D:/Quartus Project/test/test.vhd" 51 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.050 ns ( 36.52 % ) " "Info: Total cell delay = 2.050 ns ( 36.52 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "3.564 ns ( 63.48 % ) " "Info: Total interconnect delay = 3.564 ns ( 63.48 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "d:/program files (x86)/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files (x86)/quartus/bin/TimingClosureFloorplan.fld" "" "5.614 ns" { clk1M led1_xhdl1 } "NODE_NAME" } } { "d:/program files (x86)/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files (x86)/quartus/bin/Technology_Viewer.qrui" "5.614 ns" { clk1M {} clk1M~combout {} led1_xhdl1 {} } { 0.000ns 0.000ns 3.564ns } { 0.000ns 1.132ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TH_DELAY" "0.221 ns + " "Info: + Micro hold delay of destination is 0.221 ns" {  } { { "test.vhd" "" { Text "D:/Quartus Project/test/test.vhd" 51 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.399 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.399 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns rstBtn 1 PIN PIN_44 7 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_44; Fanout = 7; PIN Node = 'rstBtn'" {  } { { "d:/program files (x86)/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files (x86)/quartus/bin/TimingClosureFloorplan.fld" "" "" { rstBtn } "NODE_NAME" } } { "test.vhd" "" { Text "D:/Quartus Project/test/test.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(3.463 ns) + CELL(0.804 ns) 5.399 ns led1_xhdl1 2 REG LC_X2_Y4_N0 7 " "Info: 2: + IC(3.463 ns) + CELL(0.804 ns) = 5.399 ns; Loc. = LC_X2_Y4_N0; Fanout = 7; REG Node = 'led1_xhdl1'" {  } { { "d:/program files (x86)/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files (x86)/quartus/bin/TimingClosureFloorplan.fld" "" "4.267 ns" { rstBtn led1_xhdl1 } "NODE_NAME" } } { "test.vhd" "" { Text "D:/Quartus Project/test/test.vhd" 51 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.936 ns ( 35.86 % ) " "Info: Total cell delay = 1.936 ns ( 35.86 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "3.463 ns ( 64.14 % ) " "Info: Total interconnect delay = 3.463 ns ( 64.14 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "d:/program files (x86)/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files (x86)/quartus/bin/TimingClosureFloorplan.fld" "" "5.399 ns" { rstBtn led1_xhdl1 } "NODE_NAME" } } { "d:/program files (x86)/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files (x86)/quartus/bin/Technology_Viewer.qrui" "5.399 ns" { rstBtn {} rstBtn~combout {} led1_xhdl1 {} } { 0.000ns 0.000ns 3.463ns } { 0.000ns 1.132ns 0.804ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1}  } { { "d:/program files (x86)/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files (x86)/quartus/bin/TimingClosureFloorplan.fld" "" "5.614 ns" { clk1M led1_xhdl1 } "NODE_NAME" } } { "d:/program files (x86)/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files (x86)/quartus/bin/Technology_Viewer.qrui" "5.614 ns" { clk1M {} clk1M~combout {} led1_xhdl1 {} } { 0.000ns 0.000ns 3.564ns } { 0.000ns 1.132ns 0.918ns } "" } } { "d:/program files (x86)/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files (x86)/quartus/bin/TimingClosureFloorplan.fld" "" "5.399 ns" { rstBtn led1_xhdl1 } "NODE_NAME" } } { "d:/program files (x86)/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files (x86)/quartus/bin/Technology_Viewer.qrui" "5.399 ns" { rstBtn {} rstBtn~combout {} led1_xhdl1 {} } { 0.000ns 0.000ns 3.463ns } { 0.000ns 1.132ns 0.804ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "210 " "Info: Peak virtual memory: 210 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Fri May 24 15:37:57 2019 " "Info: Processing ended: Fri May 24 15:37:57 2019" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}