--- 
project: 
  description: "Peripherals tests for future SoC targeting Micro/Circuit Python"
  foundry: "SkyWater"
  git_url: "https://github.com/PyFive-RISC-V/caravel"
  organization: "PyFive"
  organization_url: "https://github.com/PyFive-RISC-V"
  owner: "Michael Welling / Sylvain Munaut"
  process: "SKY130"
  project_name: "Caravel"
  tags: 
    - "Open MPW"
    - "USB"
    - "RISC-V"
  category: "Test Harness"
  top_level_netlist: "verilog/gl/caravel.v"
  user_level_netlist: "verilog/gl/user_project_wrapper.v"
  version: "1.00"
  cover_image: "doc/ciic_harness.png"