Xilinx Design Summary

EX7 Partition Summary
No partition information was found.

Device Utilization Summary
Logic Utilization	Used	Available	Utilization	Note(s)
Number of Slice Flip Flops	27	9,312	1%
Number of 4 input LUTs	135	9,312	1%
Logic Distribution
Number of occupied Slices	78	4,656	1%
Number of Slices containing only related logic	78	78	100%
Number of Slices containing unrelated logic	0	78	0%
Total Number 4 input LUTs	138	9,312	1%
Number used as logic	135
Number used as a route-thru	3
Number of bonded IOBs	13	232	5%
IOB Flip Flops	1
Number of GCLKs	1	24	4%
Total equivalent gate count for design	1,103
Additional JTAG gate count for IOBs	624

Performance Summary
Final Timing Score:	0	Pinout Data:	Pinout Report
Routing Results:	All Signals Completely Routed	Clock Data:	Clock Report
Timing Constraints:	All Constraints Met