Xilinx Design Summary

EX9 Partition Summary
No partition information was found.

Device Utilization Summary
Logic Utilization	Used	Available	Utilization	Note(s)
Number of Slice Flip Flops	113	9,312	1%
Number of 4 input LUTs	221	9,312	2%
Logic Distribution
Number of occupied Slices	177	4,656	3%
Number of Slices containing only related logic	177	177	100%
Number of Slices containing unrelated logic	0	177	0%
Total Number 4 input LUTs	318	9,312	3%
Number used as logic	221
Number used as a route-thru	97
Number of bonded IOBs	15	232	6%
Number of GCLKs	2	24	8%
Total equivalent gate count for design	2,965
Additional JTAG gate count for IOBs	720

Performance Summary
Final Timing Score:	0	Pinout Data:	Pinout Report
Routing Results:	All Signals Completely Routed	Clock Data:	Clock Report
Timing Constraints:	All Constraints Met