Xilinx Design Summary

LCD_TEST Partition Summary
No partition information was found.

Device Utilization Summary
Logic Utilization	Used	Available	Utilization	Note(s)
Number of Slice Flip Flops	77	9,312	1%
Number of 4 input LUTs	162	9,312	1%
Logic Distribution
Number of occupied Slices	120	4,656	2%
Number of Slices containing only related logic	120	120	100%
Number of Slices containing unrelated logic	0	120	0%
Total Number 4 input LUTs	224	9,312	2%
Number used as logic	162
Number used as a route-thru	62
Number of bonded IOBs	14	232	6%
Number of GCLKs	1	24	4%
Total equivalent gate count for design	2,002
Additional JTAG gate count for IOBs	672

Performance Summary
Final Timing Score:	0	Pinout Data:	Pinout Report
Routing Results:	All Signals Completely Routed	Clock Data:	Clock Report
Timing Constraints:	All Constraints Met