Xilinx Design Summary

SP2_PRJ Partition Summary
No partition information was found.

Device Utilization Summary
Logic Utilization	Used	Available	Utilization	Note(s)
Number of Slice Flip Flops	16	9,312	1%
Number of 4 input LUTs	28	9,312	1%
Logic Distribution
Number of occupied Slices	26	4,656	1%
Number of Slices containing only related logic	26	26	100%
Number of Slices containing unrelated logic	0	26	0%
Total Number 4 input LUTs	29	9,312	1%
Number used as logic	28
Number used as Shift registers	1
Number of bonded IOBs	15	232	6%
IOB Flip Flops	12
Number of GCLKs	1	24	4%
Total equivalent gate count for design	468
Additional JTAG gate count for IOBs	720

Performance Summary
Final Timing Score:	0	Pinout Data:	Pinout Report
Routing Results:	All Signals Completely Routed	Clock Data:	Clock Report
Timing Constraints:	All Constraints Met