(kicad_pcb
	(version 20240108)
	(generator "pcbnew")
	(generator_version "8.0")
	(general
		(thickness 1.6)
		(legacy_teardrops no)
	)
	(paper "A4")
	(layers
		(0 "F.Cu" signal)
		(31 "B.Cu" signal)
		(36 "B.SilkS" user "B.Silkscreen")
		(37 "F.SilkS" user "F.Silkscreen")
		(38 "B.Mask" user)
		(39 "F.Mask" user)
		(40 "Dwgs.User" user "User.Drawings")
		(41 "Cmts.User" user "User.Comments")
		(42 "Eco1.User" user "User.Eco1")
		(43 "Eco2.User" user "User.Eco2")
		(44 "Edge.Cuts" user)
		(45 "Margin" user)
		(46 "B.CrtYd" user "B.Courtyard")
		(47 "F.CrtYd" user "F.Courtyard")
		(49 "F.Fab" user)
		(50 "User.1" user)
		(51 "User.2" user)
		(52 "User.3" user)
		(53 "User.4" user)
		(54 "User.5" user)
		(55 "User.6" user)
		(56 "User.7" user)
		(57 "User.8" user)
		(58 "User.9" user)
	)
	(setup
		(stackup
			(layer "F.SilkS"
				(type "Top Silk Screen")
			)
			(layer "F.Mask"
				(type "Top Solder Mask")
				(thickness 0.01)
			)
			(layer "F.Cu"
				(type "copper")
				(thickness 0.035)
			)
			(layer "dielectric 1"
				(type "core")
				(thickness 1.51)
				(material "FR4")
				(epsilon_r 4.5)
				(loss_tangent 0.02)
			)
			(layer "B.Cu"
				(type "copper")
				(thickness 0.035)
			)
			(layer "B.Mask"
				(type "Bottom Solder Mask")
				(thickness 0.01)
			)
			(layer "B.SilkS"
				(type "Bottom Silk Screen")
			)
			(copper_finish "None")
			(dielectric_constraints no)
		)
		(pad_to_mask_clearance 0)
		(allow_soldermask_bridges_in_footprints no)
		(pcbplotparams
			(layerselection 0x00010f0_ffffffff)
			(plot_on_all_layers_selection 0x0000000_00000000)
			(disableapertmacros no)
			(usegerberextensions no)
			(usegerberattributes yes)
			(usegerberadvancedattributes yes)
			(creategerberjobfile yes)
			(dashed_line_dash_ratio 12.000000)
			(dashed_line_gap_ratio 3.000000)
			(svgprecision 4)
			(plotframeref no)
			(viasonmask no)
			(mode 1)
			(useauxorigin no)
			(hpglpennumber 1)
			(hpglpenspeed 20)
			(hpglpendiameter 15.000000)
			(pdf_front_fp_property_popups yes)
			(pdf_back_fp_property_popups yes)
			(dxfpolygonmode yes)
			(dxfimperialunits yes)
			(dxfusepcbnewfont yes)
			(psnegative no)
			(psa4output no)
			(plotreference yes)
			(plotvalue yes)
			(plotfptext yes)
			(plotinvisibletext no)
			(sketchpadsonfab no)
			(subtractmaskfromsilk no)
			(outputformat 1)
			(mirror no)
			(drillshape 0)
			(scaleselection 1)
			(outputdirectory "./")
		)
	)
	(net 0 "")
	(net 1 "Net-(Q1-E)")
	(net 2 "Net-(U1-GND)")
	(net 3 "Net-(C3-Pad2)")
	(net 4 "Net-(U1-PB2)")
	(net 5 "unconnected-(J1-Pad6)")
	(net 6 "Net-(U1-AREF{slash}PB0)")
	(net 7 "unconnected-(J1-Pad2)")
	(net 8 "Net-(J2-Pin_1)")
	(net 9 "Net-(J3-Pin_1)")
	(net 10 "Net-(J4-Pin_1)")
	(net 11 "Net-(Q1-C)")
	(net 12 "Net-(Q1-B)")
	(net 13 "unconnected-(U1-XTAL1{slash}PB3-Pad2)")
	(net 14 "unconnected-(U1-~{RESET}{slash}PB5-Pad1)")
	(net 15 "unconnected-(U1-XTAL2{slash}PB4-Pad3)")
	(net 16 "unconnected-(U1-PB1-Pad6)")
	(footprint "Library:Banana-Slot"
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		(at 151 81.5)
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		(attr through_hole)
		(fp_text user "${REFERENCE}"
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		(pad "1" thru_hole oval
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			(size 9 3.5)
			(drill oval 5.2 1.2)
			(layers "*.Cu" "*.Mask")
			(remove_unused_layers no)
			(net 8 "Net-(J2-Pin_1)")
			(pinfunction "Pin_1")
			(pintype "passive")
			(uuid "4915567c-11c7-425f-a95c-f16cd249641e")
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	(footprint "Capacitor_THT:CP_Radial_D4.0mm_P2.00mm"
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		(descr "CP, Radial series, Radial, pin pitch=2.00mm, , diameter=4mm, Electrolytic Capacitor")
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