(kicad_pcb (version 4) (host pcbnew 4.0.7-e2-6376~60~ubuntu17.10.1) (general (links 476) (no_connects 34) (area 37.357145 39.935 285.247141 157.57) (thickness 0.8) (drawings 13) (tracks 1147) (zones 0) (modules 107) (nets 63) ) (page A4) (title_block (title PicoEVB) (rev D) (company "RHS Research LLC") ) (layers (0 F.Cu signal) (1 In1.Cu signal hide) (2 In2.Cu signal hide) (31 B.Cu signal hide) (34 B.Paste user hide) (35 F.Paste user hide) (36 B.SilkS user hide) (37 F.SilkS user) (38 B.Mask user hide) (39 F.Mask user hide) (41 Cmts.User user) (44 Edge.Cuts user) ) (setup (last_trace_width 0.0762) (trace_clearance 0.075946) (zone_clearance 0.0762) (zone_45_only yes) (trace_min 0.0762) (segment_width 0.2) (edge_width 0.1) (via_size 0.4064) (via_drill 0.2032) (via_min_size 0.4064) (via_min_drill 0.2032) (uvia_size 0.4064) (uvia_drill 0.2032) (uvias_allowed no) (uvia_min_size 0) (uvia_min_drill 0) (pcb_text_width 0.3) (pcb_text_size 1.5 1.5) (mod_edge_width 0.15) (mod_text_size 0.508 0.508) (mod_text_width 0.127) (pad_size 0.6 0.5842) (pad_drill 0) (pad_to_mask_clearance 0) (aux_axis_origin 66.27 84.07) (visible_elements FFFF4E7F) (pcbplotparams (layerselection 0x012fc_80000007) (usegerberextensions false) (excludeedgelayer true) (linewidth 0.100000) (plotframeref false) (viasonmask false) (mode 1) (useauxorigin false) (hpglpennumber 1) (hpglpenspeed 20) (hpglpendiameter 15) (hpglpenoverlay 2) (psnegative false) (psa4output false) (plotreference true) (plotvalue true) (plotinvisibletext false) (padsonsilk false) (subtractmaskfromsilk false) (outputformat 1) (mirror false) (drillshape 0) (scaleselection 1) (outputdirectory /home/dr/git/PicoEVB-private/board_design/out)) ) (net 0 "") (net 1 GND) (net 2 "Net-(C56-Pad1)") (net 3 "Net-(D1-Pad1)") (net 4 "Net-(D3-Pad1)") (net 5 "Net-(D4-Pad1)") (net 6 "Net-(U1-PadK16)") (net 7 "Net-(U1-PadL17)") (net 8 "Net-(U3-Pad2)") (net 9 "Net-(U6-Pad2)") (net 10 "Net-(U1-PadC3)") (net 11 "Net-(U1-PadC4)") (net 12 P1V0_MGTAVCC_B) (net 13 P1V0_VCC_FPGA_B) (net 14 P1V8_FPGA_VCCAUX_B) (net 15 P1V2_MGTAVTT_B) (net 16 MGT0_TX_B+) (net 17 MGT_REFCLK0_B+) (net 18 MGT0_TX_B-) (net 19 MGT_REFCLK0_B-) (net 20 PERST_2_L) (net 21 USB_2+) (net 22 USB_2-) (net 23 MGT0_RX_B+) (net 24 MGT0_RX_B-) (net 25 PE_CLKREQ_2_L) (net 26 FPGA_CCLK_0_B) (net 27 JTAG_TCK_B) (net 28 JTAG_TMS_B) (net 29 JTAG_TDO_B) (net 30 JTAG_TDI_B) (net 31 VCC_BANK14_B) (net 32 "/M2 edge/PETX0_2+") (net 33 "/M2 edge/PECLK_2+") (net 34 "/M2 edge/PETX0_2-") (net 35 "/M2 edge/PECLK_2-") (net 36 W_DISABLE_2) (net 37 W_DISABLE_1) (net 38 M2_LED_1) (net 39 M2_LED_2) (net 40 BUSY_LED_PU) (net 41 "Net-(D3-Pad2)") (net 42 "Net-(D4-Pad2)") (net 43 "Net-(RN3-Pad7)") (net 44 "Net-(RN3-Pad6)") (net 45 "Net-(RN3-Pad5)") (net 46 "/FPGA PCIe/UMGTCLK_0-") (net 47 "/FPGA PCIe/UMGTCLK_0+") (net 48 "/FPGA PCIe/UMGT0_TX+") (net 49 "/FPGA PCIe/UMGT0_TX-") (net 50 "/FPGA PCIe/UMGT0_RX+") (net 51 "/FPGA PCIe/UMGT0_RX-") (net 52 "Net-(D2-Pad2)") (net 53 "Net-(D2-Pad1)") (net 54 "Net-(P1-Pad4)") (net 55 "Net-(P1-Pad5)") (net 56 "Net-(P1-Pad1)") (net 57 "Net-(P1-Pad2)") (net 58 "Net-(R1-Pad1)") (net 59 "Net-(R2-Pad2)") (net 60 "Net-(R4-Pad2)") (net 61 "Net-(RN1-Pad7)") (net 62 "Net-(RN1-Pad6)") (net_class Default "This is the default net class." (clearance 0.075946) (trace_width 0.0762) (via_dia 0.4064) (via_drill 0.2032) (uvia_dia 0.4064) (uvia_drill 0.2032) (add_net "/FPGA PCIe/UMGT0_RX+") (add_net "/FPGA PCIe/UMGT0_RX-") (add_net "/FPGA PCIe/UMGT0_TX+") (add_net "/FPGA PCIe/UMGT0_TX-") (add_net "/FPGA PCIe/UMGTCLK_0+") (add_net "/FPGA PCIe/UMGTCLK_0-") (add_net "/M2 edge/PECLK_2+") (add_net "/M2 edge/PECLK_2-") (add_net "/M2 edge/PETX0_2+") (add_net "/M2 edge/PETX0_2-") (add_net BUSY_LED_PU) (add_net FPGA_CCLK_0_B) (add_net JTAG_TCK_B) (add_net JTAG_TDI_B) (add_net JTAG_TDO_B) (add_net JTAG_TMS_B) (add_net M2_LED_1) (add_net M2_LED_2) (add_net MGT0_RX_B+) (add_net MGT0_RX_B-) (add_net MGT0_TX_B+) (add_net MGT0_TX_B-) (add_net MGT_REFCLK0_B+) (add_net MGT_REFCLK0_B-) (add_net "Net-(C56-Pad1)") (add_net "Net-(D1-Pad1)") (add_net "Net-(D2-Pad1)") (add_net "Net-(D2-Pad2)") (add_net "Net-(D3-Pad1)") (add_net "Net-(D3-Pad2)") (add_net "Net-(D4-Pad1)") (add_net "Net-(D4-Pad2)") (add_net "Net-(P1-Pad1)") (add_net "Net-(P1-Pad2)") (add_net "Net-(P1-Pad4)") (add_net "Net-(P1-Pad5)") (add_net "Net-(R1-Pad1)") (add_net "Net-(R2-Pad2)") (add_net "Net-(R4-Pad2)") (add_net "Net-(RN1-Pad6)") (add_net "Net-(RN1-Pad7)") (add_net "Net-(RN3-Pad5)") (add_net "Net-(RN3-Pad6)") (add_net "Net-(RN3-Pad7)") (add_net "Net-(U1-PadC3)") (add_net "Net-(U1-PadC4)") (add_net "Net-(U1-PadK16)") (add_net "Net-(U1-PadL17)") (add_net "Net-(U3-Pad2)") (add_net "Net-(U6-Pad2)") (add_net PERST_2_L) (add_net PE_CLKREQ_2_L) (add_net USB_2+) (add_net USB_2-) (add_net W_DISABLE_1) (add_net W_DISABLE_2) ) (net_class 100OHM "" (clearance 0.075946) (trace_width 0.0762) (via_dia 0.4064) (via_drill 0.2032) (uvia_dia 0.4064) (uvia_drill 0.2032) ) (net_class PWR "" (clearance 0.075946) (trace_width 0.254) (via_dia 0.4064) (via_drill 0.2032) (uvia_dia 0.4064) (uvia_drill 0.2032) (add_net GND) (add_net P1V0_MGTAVCC_B) (add_net P1V0_VCC_FPGA_B) (add_net P1V2_MGTAVTT_B) (add_net P1V8_FPGA_VCCAUX_B) (add_net VCC_BANK14_B) ) (module M2-Board:M.2-AE-22x30 locked (layer F.Cu) (tedit 592645BE) (tstamp 5882FDE3) (at 66.27 54.07 180) (path /588189A7/58818ECE) (fp_text reference PCB1 (at 8.72 0.52 180) (layer F.SilkS) (effects (font (size 0.508 0.508) (thickness 0.127))) ) (fp_text value M.2-AE (at -23.5 8.5 180) (layer F.Fab) (effects (font (size 0.508 0.508) (thickness 0.127))) ) (fp_line (start 2.025 0) (end -9.925 0) (layer Edge.Cuts) (width 0.05)) (fp_line (start 6.025 0) (end 3.225 0) (layer Edge.Cuts) (width 0.05)) (fp_line (start 9.925 0) (end 7.225 0) (layer Edge.Cuts) (width 0.05)) (fp_line (start 2.025 0) (end 2.025 -2.9) (layer Edge.Cuts) (width 0.05)) (fp_line (start 6.025 0) (end 6.025 -2.9) (layer Edge.Cuts) (width 0.05)) (fp_arc (start 2.625 -2.9) (end 2.025 -2.9) (angle 90) (layer Edge.Cuts) (width 0.05)) (fp_arc (start 2.625 -2.9) (end 2.625 -3.5) (angle 90) (layer Edge.Cuts) (width 0.05)) (fp_line (start 7.225 0) (end 7.225 -2.9) (layer Edge.Cuts) (width 0.05)) (fp_line (start 3.225 0) (end 3.225 -2.9) (layer Edge.Cuts) (width 0.05)) (fp_arc (start 6.625 -2.9) (end 6.025 -2.9) (angle 90) (layer Edge.Cuts) (width 0.05)) (fp_arc (start 6.625 -2.9) (end 6.625 -3.5) (angle 90) (layer Edge.Cuts) (width 0.05)) (fp_line (start -9.925 0) (end -9.925 -4) (layer Edge.Cuts) (width 0.05)) (fp_line (start -9.925 -4) (end -11.25 -4) (layer Edge.Cuts) (width 0.05)) (fp_line (start -11.25 -4) (end -11.25 -30) (layer Edge.Cuts) (width 0.05)) (fp_line (start 9.925 0) (end 9.925 -4) (layer Edge.Cuts) (width 0.05)) (fp_line (start 9.925 -4) (end 11.25 -4) (layer Edge.Cuts) (width 0.05)) (fp_line (start 11.25 -4) (end 11.25 -30) (layer Edge.Cuts) (width 0.05)) (fp_arc (start 0 -30) (end 1.75 -30) (angle 90) (layer Edge.Cuts) (width 0.05)) (fp_arc (start 0 -30) (end 0 -28.25) (angle 90) (layer Edge.Cuts) (width 0.05)) (fp_line (start 11.25 -30) (end 1.75 -30) (layer Edge.Cuts) (width 0.05)) (fp_line (start -11.25 -30) (end -1.75 -30) (layer Edge.Cuts) (width 0.05)) (fp_arc (start 0 -30) (end 1.75 -30) (angle 90) (layer Cmts.User) (width 1)) (fp_arc (start 0 -30) (end 0 -28.25) (angle 90) (layer Cmts.User) (width 1)) (fp_line (start 11.25 -30) (end 1.75 -30) (layer Cmts.User) (width 1)) (fp_line (start -11.25 -30) (end -1.75 -30) (layer Cmts.User) (width 1)) (fp_line (start -11.25 -4) (end -11.25 -30) (layer Cmts.User) (width 1)) (fp_line (start 11.25 -4) (end 11.25 -30) (layer Cmts.User) (width 1)) (pad 2 smd rect (at 9 -1.55 180) (size 0.35 2.2) (layers B.Cu B.Mask) (net 31 VCC_BANK14_B)) (pad 4 smd rect (at 8.5 -1.55 180) (size 0.35 2.2) (layers B.Cu B.Mask) (net 31 VCC_BANK14_B)) (pad 6 smd rect (at 8 -1.55 180) (size 0.35 2.2) (layers B.Cu B.Mask) (net 38 M2_LED_1)) (pad 16 smd rect (at 5.5 -1.55 180) (size 0.35 2.2) (layers B.Cu B.Mask) (net 39 M2_LED_2)) (pad 18 smd rect (at 5 -1.55 180) (size 0.35 2.2) (layers B.Cu B.Mask) (net 1 GND)) (pad 20 smd rect (at 4.5 -1.55 180) (size 0.35 2.2) (layers B.Cu B.Mask)) (pad 22 smd rect (at 4 -1.55 180) (size 0.35 2.2) (layers B.Cu B.Mask)) (pad 32 smd rect (at 1.5 -1.55 180) (size 0.35 2.2) (layers B.Cu B.Mask)) (pad 34 smd rect (at 1 -1.55 180) (size 0.35 2.2) (layers B.Cu B.Mask)) (pad 36 smd rect (at 0.5 -1.55 180) (size 0.35 2.2) (layers B.Cu B.Mask)) (pad 38 smd rect (at 0 -1.55 180) (size 0.35 2.2) (layers B.Cu B.Mask)) (pad 40 smd rect (at -0.5 -1.55 180) (size 0.35 2.2) (layers B.Cu B.Mask)) (pad 42 smd rect (at -1 -1.55 180) (size 0.35 2.2) (layers B.Cu B.Mask)) (pad 44 smd rect (at -1.5 -1.55 180) (size 0.35 2.2) (layers B.Cu B.Mask)) (pad 46 smd rect (at -2 -1.55 180) (size 0.35 2.2) (layers B.Cu B.Mask)) (pad 48 smd rect (at -2.5 -1.55 180) (size 0.35 2.2) (layers B.Cu B.Mask)) (pad 50 smd rect (at -3 -1.55 180) (size 0.35 2.2) (layers B.Cu B.Mask)) (pad 52 smd rect (at -3.5 -1.55 180) (size 0.35 2.2) (layers B.Cu B.Mask) (net 20 PERST_2_L)) (pad 54 smd rect (at -4 -1.55 180) (size 0.35 2.2) (layers B.Cu B.Mask) (net 36 W_DISABLE_2)) (pad 56 smd rect (at -4.5 -1.55 180) (size 0.35 2.2) (layers B.Cu B.Mask) (net 37 W_DISABLE_1)) (pad 58 smd rect (at -5 -1.55 180) (size 0.35 2.2) (layers B.Cu B.Mask)) (pad 60 smd rect (at -5.5 -1.55 180) (size 0.35 2.2) (layers B.Cu B.Mask)) (pad 62 smd rect (at -6 -1.55 180) (size 0.35 2.2) (layers B.Cu B.Mask)) (pad 64 smd rect (at -6.5 -1.55 180) (size 0.35 2.2) (layers B.Cu B.Mask)) (pad 66 smd rect (at -7 -1.55 180) (size 0.35 2.2) (layers B.Cu B.Mask)) (pad 68 smd rect (at -7.5 -1.55 180) (size 0.35 2.2) (layers B.Cu B.Mask)) (pad 70 smd rect (at -8 -1.55 180) (size 0.35 2.2) (layers B.Cu B.Mask)) (pad 72 smd rect (at -8.5 -1.55 180) (size 0.35 2.2) (layers B.Cu B.Mask) (net 31 VCC_BANK14_B)) (pad 74 smd rect (at -9 -1.55 180) (size 0.35 2.2) (layers B.Cu B.Mask) (net 31 VCC_BANK14_B)) (pad 1 smd rect (at 9.25 -1.3 180) (size 0.35 1.7) (layers F.Cu F.Mask) (net 1 GND)) (pad 3 smd rect (at 8.75 -1.3 180) (size 0.35 1.7) (layers F.Cu F.Mask) (net 21 USB_2+)) (pad 5 smd rect (at 8.25 -1.3 180) (size 0.35 1.7) (layers F.Cu F.Mask) (net 22 USB_2-)) (pad 7 smd rect (at 7.75 -1.3 180) (size 0.35 1.7) (layers F.Cu F.Mask) (net 1 GND)) (pad 17 smd rect (at 5.25 -1.3 180) (size 0.35 1.7) (layers F.Cu F.Mask) (net 1 GND)) (pad 19 smd rect (at 4.75 -1.3 180) (size 0.35 1.7) (layers F.Cu F.Mask)) (pad 21 smd rect (at 4.25 -1.3 180) (size 0.35 1.7) (layers F.Cu F.Mask)) (pad 23 smd rect (at 3.75 -1.3 180) (size 0.35 1.7) (layers F.Cu F.Mask) (net 1 GND)) (pad 33 smd rect (at 1.25 -1.3 180) (size 0.35 1.7) (layers F.Cu F.Mask) (net 1 GND)) (pad 35 smd rect (at 0.75 -1.3 180) (size 0.35 1.7) (layers F.Cu F.Mask) (net 23 MGT0_RX_B+)) (pad 37 smd rect (at 0.25 -1.3 180) (size 0.35 1.7) (layers F.Cu F.Mask) (net 24 MGT0_RX_B-)) (pad 39 smd rect (at -0.25 -1.3 180) (size 0.35 1.7) (layers F.Cu F.Mask) (net 1 GND)) (pad 41 smd rect (at -0.75 -1.3 180) (size 0.35 1.7) (layers F.Cu F.Mask) (net 32 "/M2 edge/PETX0_2+")) (pad 43 smd rect (at -1.25 -1.3 180) (size 0.35 1.7) (layers F.Cu F.Mask) (net 34 "/M2 edge/PETX0_2-")) (pad 45 smd rect (at -1.75 -1.3 180) (size 0.35 1.7) (layers F.Cu F.Mask) (net 1 GND)) (pad 47 smd rect (at -2.25 -1.3 180) (size 0.35 1.7) (layers F.Cu F.Mask) (net 33 "/M2 edge/PECLK_2+")) (pad 49 smd rect (at -2.75 -1.3 180) (size 0.35 1.7) (layers F.Cu F.Mask) (net 35 "/M2 edge/PECLK_2-")) (pad 51 smd rect (at -3.25 -1.3 180) (size 0.35 1.7) (layers F.Cu F.Mask) (net 1 GND)) (pad 53 smd rect (at -3.75 -1.3 180) (size 0.35 1.7) (layers F.Cu F.Mask) (net 25 PE_CLKREQ_2_L)) (pad 55 smd rect (at -4.25 -1.3 180) (size 0.35 1.7) (layers F.Cu F.Mask)) (pad 57 smd rect (at -4.75 -1.3 180) (size 0.35 1.7) (layers F.Cu F.Mask) (net 1 GND)) (pad 59 smd rect (at -5.25 -1.3 180) (size 0.35 1.7) (layers F.Cu F.Mask)) (pad 61 smd rect (at -5.75 -1.3 180) (size 0.35 1.7) (layers F.Cu F.Mask)) (pad 63 smd rect (at -6.25 -1.3 180) (size 0.35 1.7) (layers F.Cu F.Mask) (net 1 GND)) (pad 65 smd rect (at -6.75 -1.3 180) (size 0.35 1.7) (layers F.Cu F.Mask)) (pad 67 smd rect (at -7.25 -1.3 180) (size 0.35 1.7) (layers F.Cu F.Mask)) (pad 69 smd rect (at -7.75 -1.3 180) (size 0.35 1.7) (layers F.Cu F.Mask) (net 1 GND)) (pad 71 smd rect (at -8.25 -1.3 180) (size 0.35 1.7) (layers F.Cu F.Mask)) (pad 73 smd rect (at -8.75 -1.3 180) (size 0.35 1.7) (layers F.Cu F.Mask)) (pad 75 smd rect (at -9.25 -1.3 180) (size 0.35 1.7) (layers F.Cu F.Mask) (net 1 GND)) ) (module SMT:U.FL-COAX (layer F.Cu) (tedit 5A13AB93) (tstamp 59ED27E7) (at 75.02 82.3 270) (path /594F3239/59EB4FDE) (attr smd) (fp_text reference J3 (at -1.79 -1.04 360) (layer F.SilkS) (effects (font (size 0.508 0.508) (thickness 0.127))) ) (fp_text value CLKIN- (at -1.78 1.91 540) (layer F.SilkS) (effects (font (size 0.508 0.508) (thickness 0.127))) ) (fp_line (start 1.1 0.3) (end 1.1 -0.3) (layer F.SilkS) (width 0.2032)) (fp_line (start 1.5 0.3) (end 1 0.3) (layer F.SilkS) (width 0.2032)) (fp_line (start 1.5 0.3) (end 1.5 -0.3) (layer F.SilkS) (width 0.2032)) (fp_line (start 1.5 -0.3) (end 1 -0.3) (layer F.SilkS) (width 0.2032)) (fp_circle (center 0 0) (end 0.2 0) (layer F.SilkS) (width 0.2032)) (fp_circle (center 0 0) (end 1 0) (layer F.SilkS) (width 0.2032)) (fp_line (start -1.3 -1.3) (end -1.3 1.3) (layer F.SilkS) (width 0.2032)) (fp_line (start -1.3 1.3) (end 1.3 1.3) (layer F.SilkS) (width 0.2032)) (fp_line (start 1.3 1.3) (end 1.3 -1.3) (layer F.SilkS) (width 0.2032)) (fp_line (start 1.3 -1.3) (end -1.3 -1.3) (layer F.SilkS) (width 0.2032)) (pad 1 smd rect (at -1.5 0 270) (size 1 1) (layers F.Cu F.Paste F.Mask) (net 46 "/FPGA PCIe/UMGTCLK_0-")) (pad 2 smd rect (at 0 -1.5 270) (size 2.2 1) (layers F.Cu F.Paste F.Mask) (net 1 GND)) (pad 2 smd rect (at 0 1.5 270) (size 2.2 1) (layers F.Cu F.Paste F.Mask) (net 1 GND)) ) (module SMT:U.FL-COAX (layer F.Cu) (tedit 5A13AB5C) (tstamp 59ED27F9) (at 74.66 77.83 90) (path /594F3239/59EB4EEE) (attr smd) (fp_text reference J4 (at -1.76 -0.94 180) (layer F.SilkS) (effects (font (size 0.508 0.508) (thickness 0.127))) ) (fp_text value CLKIN+ (at 1.74 0.016 180) (layer F.SilkS) (effects (font (size 0.508 0.508) (thickness 0.127))) ) (fp_line (start 1.1 0.3) (end 1.1 -0.3) (layer F.SilkS) (width 0.2032)) (fp_line (start 1.5 0.3) (end 1 0.3) (layer F.SilkS) (width 0.2032)) (fp_line (start 1.5 0.3) (end 1.5 -0.3) (layer F.SilkS) (width 0.2032)) (fp_line (start 1.5 -0.3) (end 1 -0.3) (layer F.SilkS) (width 0.2032)) (fp_circle (center 0 0) (end 0.2 0) (layer F.SilkS) (width 0.2032)) (fp_circle (center 0 0) (end 1 0) (layer F.SilkS) (width 0.2032)) (fp_line (start -1.3 -1.3) (end -1.3 1.3) (layer F.SilkS) (width 0.2032)) (fp_line (start -1.3 1.3) (end 1.3 1.3) (layer F.SilkS) (width 0.2032)) (fp_line (start 1.3 1.3) (end 1.3 -1.3) (layer F.SilkS) (width 0.2032)) (fp_line (start 1.3 -1.3) (end -1.3 -1.3) (layer F.SilkS) (width 0.2032)) (pad 1 smd rect (at -1.5 0 90) (size 1 1) (layers F.Cu F.Paste F.Mask) (net 47 "/FPGA PCIe/UMGTCLK_0+")) (pad 2 smd rect (at 0 -1.5 90) (size 2.2 1) (layers F.Cu F.Paste F.Mask) (net 1 GND)) (pad 2 smd rect (at 0 1.5 90) (size 2.2 1) (layers F.Cu F.Paste F.Mask) (net 1 GND)) ) (module SMT:c_0201_least (layer B.Cu) (tedit 58881732) (tstamp 588946D4) (at 73.51 81.69 270) (path /594F323A/586D021A) (attr smd) (fp_text reference C51 (at 1.08 -0.05 540) (layer B.SilkS) (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_text value 0.1uf (at -0.1 -0.5 270) (layer B.Fab) (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_line (start -0.6 -0.3) (end -0.6 0.3) (layer B.SilkS) (width 0.05)) (fp_line (start 0.6 -0.3) (end -0.6 -0.3) (layer B.SilkS) (width 0.05)) (fp_line (start 0.6 0.3) (end 0.6 -0.3) (layer B.SilkS) (width 0.05)) (fp_line (start -0.6 0.3) (end 0.6 0.3) (layer B.SilkS) (width 0.05)) (pad 1 smd rect (at -0.28 0 270) (size 0.36 0.32) (layers B.Cu B.Paste B.Mask) (net 31 VCC_BANK14_B)) (pad 2 smd rect (at 0.28 0 270) (size 0.36 0.32) (layers B.Cu B.Paste B.Mask) (net 1 GND)) (model Capacitors_SMD.3dshapes/C_0201.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 0)) ) ) (module Housings_DFN_QFN:DFN-S-8-1EP_6x5mm_Pitch1.27mm (layer B.Cu) (tedit 54130A77) (tstamp 58819106) (at 71.37 78.2475) (descr "8-Lead Plastic Dual Flat, No Lead Package (MF) - 6x5 mm Body [DFN-S] (see Microchip Packaging Specification 00000049BS.pdf)") (tags "DFN 1.27") (path /594F323A/587CA7B7) (attr smd) (fp_text reference U2 (at -3.13 3.0925) (layer B.SilkS) (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_text value S25Q (at 0 -3.575) (layer B.Fab) (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_line (start -2 2.5) (end 3 2.5) (layer B.Fab) (width 0.15)) (fp_line (start 3 2.5) (end 3 -2.5) (layer B.Fab) (width 0.15)) (fp_line (start 3 -2.5) (end -3 -2.5) (layer B.Fab) (width 0.15)) (fp_line (start -3 -2.5) (end -3 1.5) (layer B.Fab) (width 0.15)) (fp_line (start -3 1.5) (end -2 2.5) (layer B.Fab) (width 0.15)) (fp_line (start -3.6 2.85) (end -3.6 -2.85) (layer B.CrtYd) (width 0.05)) (fp_line (start 3.6 2.85) (end 3.6 -2.85) (layer B.CrtYd) (width 0.05)) (fp_line (start -3.6 2.85) (end 3.6 2.85) (layer B.CrtYd) (width 0.05)) (fp_line (start -3.6 -2.85) (end 3.6 -2.85) (layer B.CrtYd) (width 0.05)) (fp_line (start -2.25 -2.65) (end 2.25 -2.65) (layer B.SilkS) (width 0.15)) (fp_line (start -3.425 2.65) (end 2.25 2.65) (layer B.SilkS) (width 0.15)) (pad 1 smd oval (at -2.8 1.905) (size 1.1 0.45) (layers B.Cu B.Paste B.Mask) (net 45 "Net-(RN3-Pad5)")) (pad 2 smd oval (at -2.8 0.635) (size 1.1 0.45) (layers B.Cu B.Paste B.Mask) (net 7 "Net-(U1-PadL17)")) (pad 3 smd oval (at -2.8 -0.635) (size 1.1 0.45) (layers B.Cu B.Paste B.Mask) (net 44 "Net-(RN3-Pad6)")) (pad 4 smd oval (at -2.8 -1.905) (size 1.1 0.45) (layers B.Cu B.Paste B.Mask) (net 1 GND)) (pad 5 smd oval (at 2.8 -1.905) (size 1.1 0.45) (layers B.Cu B.Paste B.Mask) (net 6 "Net-(U1-PadK16)")) (pad 6 smd oval (at 2.8 -0.635) (size 1.1 0.45) (layers B.Cu B.Paste B.Mask) (net 26 FPGA_CCLK_0_B)) (pad 7 smd oval (at 2.8 0.635) (size 1.1 0.45) (layers B.Cu B.Paste B.Mask) (net 43 "Net-(RN3-Pad7)")) (pad 8 smd oval (at 2.8 1.905) (size 1.1 0.45) (layers B.Cu B.Paste B.Mask) (net 31 VCC_BANK14_B)) (pad 9 smd rect (at 0.6 -1.5375) (size 1.2 1.025) (layers B.Cu B.Paste B.Mask) (net 1 GND) (solder_paste_margin_ratio -0.2)) (pad 9 smd rect (at 0.6 -0.512499) (size 1.2 1.025) (layers B.Cu B.Paste B.Mask) (net 1 GND) (solder_paste_margin_ratio -0.2)) (pad 9 smd rect (at 0.6 0.5125) (size 1.2 1.025) (layers B.Cu B.Paste B.Mask) (net 1 GND) (solder_paste_margin_ratio -0.2)) (pad 9 smd rect (at 0.6 1.5375) (size 1.2 1.025) (layers B.Cu B.Paste B.Mask) (net 1 GND) (solder_paste_margin_ratio -0.2)) (pad 9 smd rect (at -0.6 -1.5375) (size 1.2 1.025) (layers B.Cu B.Paste B.Mask) (net 1 GND) (solder_paste_margin_ratio -0.2)) (pad 9 smd rect (at -0.6 -0.512499) (size 1.2 1.025) (layers B.Cu B.Paste B.Mask) (net 1 GND) (solder_paste_margin_ratio -0.2)) (pad 9 smd rect (at -0.6 0.5125) (size 1.2 1.025) (layers B.Cu B.Paste B.Mask) (net 1 GND) (solder_paste_margin_ratio -0.2)) (pad 9 smd rect (at -0.6 1.5375) (size 1.2 1.025) (layers B.Cu B.Paste B.Mask) (net 1 GND) (solder_paste_margin_ratio -0.2)) (model Housings_DFN_QFN.3dshapes/DFN-S-8-1EP_6x5mm_Pitch1.27mm.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 0)) ) ) (module SMT:r_0201_least (layer B.Cu) (tedit 58881732) (tstamp 58818EFD) (at 60.42 64.99 90) (path /594F323B/594F31DA) (attr smd) (fp_text reference R5 (at -0.08 0.69 270) (layer B.SilkS) (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_text value 100k (at -0.1 -0.5 90) (layer B.Fab) (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_line (start -0.6 -0.3) (end -0.6 0.3) (layer B.SilkS) (width 0.05)) (fp_line (start 0.6 -0.3) (end -0.6 -0.3) (layer B.SilkS) (width 0.05)) (fp_line (start 0.6 0.3) (end 0.6 -0.3) (layer B.SilkS) (width 0.05)) (fp_line (start -0.6 0.3) (end 0.6 0.3) (layer B.SilkS) (width 0.05)) (pad 1 smd rect (at -0.28 0 90) (size 0.36 0.32) (layers B.Cu B.Paste B.Mask) (net 60 "Net-(R4-Pad2)")) (pad 2 smd rect (at 0.28 0 90) (size 0.36 0.32) (layers B.Cu B.Paste B.Mask) (net 1 GND)) (model Resistors_SMD.3dshapes/R_0201.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 0)) ) ) (module SMT:r_0201_least (layer B.Cu) (tedit 58881732) (tstamp 58818EED) (at 60.42 66.28 90) (path /594F323B/594F31D9) (attr smd) (fp_text reference R4 (at -0.34 0.7 90) (layer B.SilkS) (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_text value 24.9k (at -0.1 -0.5 90) (layer B.Fab) (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_line (start -0.6 -0.3) (end -0.6 0.3) (layer B.SilkS) (width 0.05)) (fp_line (start 0.6 -0.3) (end -0.6 -0.3) (layer B.SilkS) (width 0.05)) (fp_line (start 0.6 0.3) (end 0.6 -0.3) (layer B.SilkS) (width 0.05)) (fp_line (start -0.6 0.3) (end 0.6 0.3) (layer B.SilkS) (width 0.05)) (pad 1 smd rect (at -0.28 0 90) (size 0.36 0.32) (layers B.Cu B.Paste B.Mask) (net 13 P1V0_VCC_FPGA_B)) (pad 2 smd rect (at 0.28 0 90) (size 0.36 0.32) (layers B.Cu B.Paste B.Mask) (net 60 "Net-(R4-Pad2)")) (model Resistors_SMD.3dshapes/R_0201.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 0)) ) ) (module LEDs:LED_0402 (layer F.Cu) (tedit 59AB4D92) (tstamp 58818C96) (at 60.14 74.96 180) (descr "LED 0402 smd package") (tags "LED led 0402 SMD smd SMT smt smdled SMDLED smtled SMTLED") (path /5881899D/587C5669) (attr smd) (fp_text reference D1 (at -0.26 -0.02 360) (layer F.SilkS) (effects (font (size 0.508 0.508) (thickness 0.127))) ) (fp_text value BUSY (at -0.03 -0.91 180) (layer F.SilkS) (effects (font (size 0.508 0.508) (thickness 0.127))) ) (fp_line (start -0.95 -0.45) (end -0.95 0.45) (layer F.SilkS) (width 0.12)) (fp_line (start -0.15 -0.2) (end -0.15 0.2) (layer F.Fab) (width 0.1)) (fp_line (start -0.15 0) (end 0.15 -0.2) (layer F.Fab) (width 0.1)) (fp_line (start 0.15 0.2) (end -0.15 0) (layer F.Fab) (width 0.1)) (fp_line (start 0.15 -0.2) (end 0.15 0.2) (layer F.Fab) (width 0.1)) (fp_line (start 0.5 0.25) (end -0.5 0.25) (layer F.Fab) (width 0.1)) (fp_line (start 0.5 -0.25) (end 0.5 0.25) (layer F.Fab) (width 0.1)) (fp_line (start -0.5 -0.25) (end 0.5 -0.25) (layer F.Fab) (width 0.1)) (fp_line (start -0.5 0.25) (end -0.5 -0.25) (layer F.Fab) (width 0.1)) (fp_line (start -0.95 0.45) (end 0.5 0.45) (layer F.SilkS) (width 0.12)) (fp_line (start -0.95 -0.45) (end 0.5 -0.45) (layer F.SilkS) (width 0.12)) (fp_line (start 1 -0.5) (end 1 0.5) (layer F.CrtYd) (width 0.05)) (fp_line (start 1 0.5) (end -1 0.5) (layer F.CrtYd) (width 0.05)) (fp_line (start -1 0.5) (end -1 -0.5) (layer F.CrtYd) (width 0.05)) (fp_line (start -1 -0.5) (end 1 -0.5) (layer F.CrtYd) (width 0.05)) (pad 2 smd rect (at 0.55 0) (size 0.6 0.7) (layers F.Cu F.Paste F.Mask) (net 40 BUSY_LED_PU)) (pad 1 smd rect (at -0.55 0) (size 0.6 0.7) (layers F.Cu F.Paste F.Mask) (net 3 "Net-(D1-Pad1)")) (model LEDs.3dshapes/LED_0402.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 180)) ) ) (module SMT:r_0201_least (layer B.Cu) (tedit 58881732) (tstamp 58818ECD) (at 60.39 60.09 90) (path /594F323B/5861CFC0) (attr smd) (fp_text reference R2 (at -1.12 0.03 90) (layer B.SilkS) (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_text value 124k (at -0.1 -0.5 90) (layer B.Fab) (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_line (start -0.6 -0.3) (end -0.6 0.3) (layer B.SilkS) (width 0.05)) (fp_line (start 0.6 -0.3) (end -0.6 -0.3) (layer B.SilkS) (width 0.05)) (fp_line (start 0.6 0.3) (end 0.6 -0.3) (layer B.SilkS) (width 0.05)) (fp_line (start -0.6 0.3) (end 0.6 0.3) (layer B.SilkS) (width 0.05)) (pad 1 smd rect (at -0.28 0 90) (size 0.36 0.32) (layers B.Cu B.Paste B.Mask) (net 2 "Net-(C56-Pad1)")) (pad 2 smd rect (at 0.28 0 90) (size 0.36 0.32) (layers B.Cu B.Paste B.Mask) (net 59 "Net-(R2-Pad2)")) (model Resistors_SMD.3dshapes/R_0201.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 0)) ) ) (module SMT:r_0201_least (layer B.Cu) (tedit 58881732) (tstamp 58818EDD) (at 60.39 58.72 90) (path /594F323B/5861CFC6) (attr smd) (fp_text reference R3 (at 1.03 0.4 180) (layer B.SilkS) (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_text value 100k (at -0.1 -0.5 90) (layer B.Fab) (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_line (start -0.6 -0.3) (end -0.6 0.3) (layer B.SilkS) (width 0.05)) (fp_line (start 0.6 -0.3) (end -0.6 -0.3) (layer B.SilkS) (width 0.05)) (fp_line (start 0.6 0.3) (end 0.6 -0.3) (layer B.SilkS) (width 0.05)) (fp_line (start -0.6 0.3) (end 0.6 0.3) (layer B.SilkS) (width 0.05)) (pad 1 smd rect (at -0.28 0 90) (size 0.36 0.32) (layers B.Cu B.Paste B.Mask) (net 59 "Net-(R2-Pad2)")) (pad 2 smd rect (at 0.28 0 90) (size 0.36 0.32) (layers B.Cu B.Paste B.Mask) (net 1 GND)) (model Resistors_SMD.3dshapes/R_0201.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 0)) ) ) (module SMT:c_0201_least (layer B.Cu) (tedit 58881732) (tstamp 588945E4) (at 75.63 74.12 270) (path /5881899D/594F3213) (attr smd) (fp_text reference C39 (at 0.02 -0.69 270) (layer B.SilkS) (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_text value 0.47uf (at -0.1 -0.5 270) (layer B.Fab) (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_line (start -0.6 -0.3) (end -0.6 0.3) (layer B.SilkS) (width 0.05)) (fp_line (start 0.6 -0.3) (end -0.6 -0.3) (layer B.SilkS) (width 0.05)) (fp_line (start 0.6 0.3) (end 0.6 -0.3) (layer B.SilkS) (width 0.05)) (fp_line (start -0.6 0.3) (end 0.6 0.3) (layer B.SilkS) (width 0.05)) (pad 1 smd rect (at -0.28 0 270) (size 0.36 0.32) (layers B.Cu B.Paste B.Mask) (net 31 VCC_BANK14_B)) (pad 2 smd rect (at 0.28 0 270) (size 0.36 0.32) (layers B.Cu B.Paste B.Mask) (net 1 GND)) (model Capacitors_SMD.3dshapes/C_0201.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 0)) ) ) (module XC7A50T-CSG325:CSG-324 locked (layer F.Cu) (tedit 5886C856) (tstamp 588190EA) (at 69.24 68.12 270) (descr "ADSP_21462W_324_CSPBGA_bsdl edit this description

Auto generated by make-symbol-device-package-bsdl.ulp Rev. 33
Source: ADSP_21462W_324_CSPBGA_bsdl.txt") (path /5881899D/586A5710) (attr smd) (fp_text reference U1 (at -8.11 -7.04 540) (layer F.SilkS) (effects (font (size 0.508 0.508) (thickness 0.127))) ) (fp_text value XC7AxxT-xCSG325 (at -5.2 8.2 270) (layer F.SilkS) hide (effects (font (size 0.508 0.508) (thickness 0.127))) ) (fp_circle (center -8 -8) (end -8.2 -8) (layer F.SilkS) (width 0.09)) (fp_line (start -7.55 7.55) (end 7.55 7.55) (layer F.SilkS) (width 0.1)) (fp_line (start 7.55 7.55) (end 7.55 -7.55) (layer F.SilkS) (width 0.1)) (fp_line (start 7.55 -7.55) (end -7.55 -7.55) (layer F.SilkS) (width 0.1)) (fp_line (start -7.55 -7.55) (end -7.55 7.55) (layer F.SilkS) (width 0.1)) (pad A1 smd circle (at -6.8 -6.8 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.03175)) (pad A2 smd circle (at -6 -6.8 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 15 P1V2_MGTAVTT_B) (solder_mask_margin 0.03175)) (pad A3 smd circle (at -5.2 -6.8 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.03175)) (pad A4 smd circle (at -4.4 -6.8 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.03175)) (pad A5 smd circle (at -3.6 -6.8 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.03175)) (pad A6 smd circle (at -2.8 -6.8 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 58 "Net-(R1-Pad1)") (solder_mask_margin 0.03175)) (pad A7 smd circle (at -2 -6.8 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.03175)) (pad A8 smd circle (at -1.2 -6.8 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.03175)) (pad A9 smd circle (at -0.4 -6.8 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 25 PE_CLKREQ_2_L) (solder_mask_margin 0.03175)) (pad A10 smd circle (at 0.4 -6.8 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 20 PERST_2_L) (solder_mask_margin 0.03175)) (pad A11 smd circle (at 1.2 -6.8 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.03175)) (pad A12 smd circle (at 2 -6.8 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 55 "Net-(P1-Pad5)") (solder_mask_margin 0.03175)) (pad A13 smd circle (at 2.8 -6.8 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 57 "Net-(P1-Pad2)") (solder_mask_margin 0.03175)) (pad A14 smd circle (at 3.6 -6.8 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 56 "Net-(P1-Pad1)") (solder_mask_margin 0.03175)) (pad A15 smd circle (at 4.4 -6.8 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (solder_mask_margin 0.03175)) (pad A16 smd circle (at 5.2 -6.8 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 31 VCC_BANK14_B) (solder_mask_margin 0.03175)) (pad A17 smd circle (at 6 -6.8 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (solder_mask_margin 0.03175)) (pad A18 smd circle (at 6.8 -6.8 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.03175)) (pad B1 smd circle (at -6.8 -6 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 18 MGT0_TX_B-) (solder_mask_margin 0.03175)) (pad B2 smd circle (at -6 -6 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 16 MGT0_TX_B+) (solder_mask_margin 0.03175)) (pad B3 smd circle (at -5.2 -6 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.03175)) (pad B4 smd circle (at -4.4 -6 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 12 P1V0_MGTAVCC_B) (solder_mask_margin 0.03175)) (pad B5 smd circle (at -3.6 -6 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 19 MGT_REFCLK0_B-) (solder_mask_margin 0.03175)) (pad B6 smd circle (at -2.8 -6 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 17 MGT_REFCLK0_B+) (solder_mask_margin 0.03175)) (pad B7 smd circle (at -2 -6 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.03175)) (pad B8 smd circle (at -1.2 -6 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.03175)) (pad B9 smd circle (at -0.4 -6 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (solder_mask_margin 0.03175)) (pad B10 smd circle (at 0.4 -6 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (solder_mask_margin 0.03175)) (pad B11 smd circle (at 1.2 -6 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (solder_mask_margin 0.03175)) (pad B12 smd circle (at 2 -6 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 54 "Net-(P1-Pad4)") (solder_mask_margin 0.03175)) (pad B13 smd circle (at 2.8 -6 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 31 VCC_BANK14_B) (solder_mask_margin 0.03175)) (pad B14 smd circle (at 3.6 -6 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (solder_mask_margin 0.03175)) (pad B15 smd circle (at 4.4 -6 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (solder_mask_margin 0.03175)) (pad B16 smd circle (at 5.2 -6 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (solder_mask_margin 0.03175)) (pad B17 smd circle (at 6 -6 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (solder_mask_margin 0.03175)) (pad B18 smd circle (at 6.8 -6 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.03175)) (pad C1 smd circle (at -6.8 -5.2 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 15 P1V2_MGTAVTT_B) (solder_mask_margin 0.03175)) (pad C2 smd circle (at -6 -5.2 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.03175)) (pad C3 smd circle (at -5.2 -5.2 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 10 "Net-(U1-PadC3)") (solder_mask_margin 0.03175)) (pad C4 smd circle (at -4.4 -5.2 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 11 "Net-(U1-PadC4)") (solder_mask_margin 0.03175)) (pad C5 smd circle (at -3.6 -5.2 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 12 P1V0_MGTAVCC_B) (solder_mask_margin 0.03175)) (pad C6 smd circle (at -2.8 -5.2 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.03175)) (pad C7 smd circle (at -2 -5.2 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.03175)) (pad C8 smd circle (at -1.2 -5.2 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (solder_mask_margin 0.03175)) (pad C9 smd circle (at -0.4 -5.2 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (solder_mask_margin 0.03175)) (pad C10 smd circle (at 0.4 -5.2 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 31 VCC_BANK14_B) (solder_mask_margin 0.03175)) (pad C11 smd circle (at 1.2 -5.2 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (solder_mask_margin 0.03175)) (pad C12 smd circle (at 2 -5.2 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (solder_mask_margin 0.03175)) (pad C13 smd circle (at 2.8 -5.2 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (solder_mask_margin 0.03175)) (pad C14 smd circle (at 3.6 -5.2 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (solder_mask_margin 0.03175)) (pad C15 smd circle (at 4.4 -5.2 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.03175)) (pad C16 smd circle (at 5.2 -5.2 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (solder_mask_margin 0.03175)) (pad C17 smd circle (at 6 -5.2 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (solder_mask_margin 0.03175)) (pad C18 smd circle (at 6.8 -5.2 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (solder_mask_margin 0.03175)) (pad D1 smd circle (at -6.8 -4.4 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 10 "Net-(U1-PadC3)") (solder_mask_margin 0.03175)) (pad D2 smd circle (at -6 -4.4 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 11 "Net-(U1-PadC4)") (solder_mask_margin 0.03175)) (pad D3 smd circle (at -5.2 -4.4 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.03175)) (pad D4 smd circle (at -4.4 -4.4 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.03175)) (pad D5 smd circle (at -3.6 -4.4 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 46 "/FPGA PCIe/UMGTCLK_0-") (solder_mask_margin 0.03175)) (pad D6 smd circle (at -2.8 -4.4 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 47 "/FPGA PCIe/UMGTCLK_0+") (solder_mask_margin 0.03175)) (pad D7 smd circle (at -2 -4.4 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.03175)) (pad D8 smd circle (at -1.2 -4.4 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (solder_mask_margin 0.03175)) (pad D9 smd circle (at -0.4 -4.4 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (solder_mask_margin 0.03175)) (pad D10 smd circle (at 0.4 -4.4 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (solder_mask_margin 0.03175)) (pad D11 smd circle (at 1.2 -4.4 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (solder_mask_margin 0.03175)) (pad D12 smd circle (at 2 -4.4 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.03175)) (pad D13 smd circle (at 2.8 -4.4 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (solder_mask_margin 0.03175)) (pad D14 smd circle (at 3.6 -4.4 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (solder_mask_margin 0.03175)) (pad D15 smd circle (at 4.4 -4.4 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (solder_mask_margin 0.03175)) (pad D16 smd circle (at 5.2 -4.4 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (solder_mask_margin 0.03175)) (pad D17 smd circle (at 6 -4.4 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 31 VCC_BANK14_B) (solder_mask_margin 0.03175)) (pad D18 smd circle (at 6.8 -4.4 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (solder_mask_margin 0.03175)) (pad E1 smd circle (at -6.8 -3.6 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 15 P1V2_MGTAVTT_B) (solder_mask_margin 0.03175)) (pad E2 smd circle (at -6 -3.6 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.03175)) (pad E3 smd circle (at -5.2 -3.6 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 51 "/FPGA PCIe/UMGT0_RX-") (solder_mask_margin 0.03175)) (pad E4 smd circle (at -4.4 -3.6 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 50 "/FPGA PCIe/UMGT0_RX+") (solder_mask_margin 0.03175)) (pad E5 smd circle (at -3.6 -3.6 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 12 P1V0_MGTAVCC_B) (solder_mask_margin 0.03175)) (pad E6 smd circle (at -2.8 -3.6 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.03175)) (pad E7 smd circle (at -2 -3.6 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.03175)) (pad E8 smd circle (at -1.2 -3.6 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 26 FPGA_CCLK_0_B) (solder_mask_margin 0.03175)) (pad E9 smd circle (at -0.4 -3.6 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.03175)) (pad E10 smd circle (at 0.4 -3.6 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 31 VCC_BANK14_B) (solder_mask_margin 0.03175)) (pad E11 smd circle (at 1.2 -3.6 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.03175)) (pad E12 smd circle (at 2 -3.6 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 31 VCC_BANK14_B) (solder_mask_margin 0.03175)) (pad E13 smd circle (at 2.8 -3.6 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (solder_mask_margin 0.03175)) (pad E14 smd circle (at 3.6 -3.6 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 31 VCC_BANK14_B) (solder_mask_margin 0.03175)) (pad E15 smd circle (at 4.4 -3.6 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (solder_mask_margin 0.03175)) (pad E16 smd circle (at 5.2 -3.6 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (solder_mask_margin 0.03175)) (pad E17 smd circle (at 6 -3.6 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (solder_mask_margin 0.03175)) (pad E18 smd circle (at 6.8 -3.6 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (solder_mask_margin 0.03175)) (pad F1 smd circle (at -6.8 -2.8 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (solder_mask_margin 0.03175)) (pad F2 smd circle (at -6 -2.8 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (solder_mask_margin 0.03175)) (pad F3 smd circle (at -5.2 -2.8 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 15 P1V2_MGTAVTT_B) (solder_mask_margin 0.03175)) (pad F4 smd circle (at -4.4 -2.8 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.03175)) (pad F5 smd circle (at -3.6 -2.8 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 12 P1V0_MGTAVCC_B) (solder_mask_margin 0.03175)) (pad F6 smd circle (at -2.8 -2.8 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.03175)) (pad F7 smd circle (at -2 -2.8 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 13 P1V0_VCC_FPGA_B) (solder_mask_margin 0.03175)) (pad F8 smd circle (at -1.2 -2.8 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 27 JTAG_TCK_B) (solder_mask_margin 0.03175)) (pad F9 smd circle (at -0.4 -2.8 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 13 P1V0_VCC_FPGA_B) (solder_mask_margin 0.03175)) (pad F10 smd circle (at 0.4 -2.8 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.03175)) (pad F11 smd circle (at 1.2 -2.8 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 13 P1V0_VCC_FPGA_B) (solder_mask_margin 0.03175)) (pad F12 smd circle (at 2 -2.8 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 3 "Net-(D1-Pad1)") (solder_mask_margin 0.03175)) (pad F13 smd circle (at 2.8 -2.8 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.03175)) (pad F14 smd circle (at 3.6 -2.8 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (solder_mask_margin 0.03175)) (pad F15 smd circle (at 4.4 -2.8 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (solder_mask_margin 0.03175)) (pad F16 smd circle (at 5.2 -2.8 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.03175)) (pad F17 smd circle (at 6 -2.8 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (solder_mask_margin 0.03175)) (pad F18 smd circle (at 6.8 -2.8 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (solder_mask_margin 0.03175)) (pad G1 smd circle (at -6.8 -2 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.03175)) (pad G2 smd circle (at -6 -2 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 15 P1V2_MGTAVTT_B) (solder_mask_margin 0.03175)) (pad G3 smd circle (at -5.2 -2 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 24 MGT0_RX_B-) (solder_mask_margin 0.03175)) (pad G4 smd circle (at -4.4 -2 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 23 MGT0_RX_B+) (solder_mask_margin 0.03175)) (pad G5 smd circle (at -3.6 -2 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.03175)) (pad G6 smd circle (at -2.8 -2 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.03175)) (pad G7 smd circle (at -2 -2 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.03175)) (pad G8 smd circle (at -1.2 -2 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 13 P1V0_VCC_FPGA_B) (solder_mask_margin 0.03175)) (pad G9 smd circle (at -0.4 -2 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.03175)) (pad G10 smd circle (at 0.4 -2 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 13 P1V0_VCC_FPGA_B) (solder_mask_margin 0.03175)) (pad G11 smd circle (at 1.2 -2 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.03175)) (pad G12 smd circle (at 2 -2 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 14 P1V8_FPGA_VCCAUX_B) (solder_mask_margin 0.03175)) (pad G13 smd circle (at 2.8 -2 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.03175)) (pad G14 smd circle (at 3.6 -2 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (solder_mask_margin 0.03175)) (pad G15 smd circle (at 4.4 -2 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (solder_mask_margin 0.03175)) (pad G16 smd circle (at 5.2 -2 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (solder_mask_margin 0.03175)) (pad G17 smd circle (at 6 -2 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (solder_mask_margin 0.03175)) (pad G18 smd circle (at 6.8 -2 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 31 VCC_BANK14_B) (solder_mask_margin 0.03175)) (pad H1 smd circle (at -6.8 -1.2 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 49 "/FPGA PCIe/UMGT0_TX-") (solder_mask_margin 0.03175)) (pad H2 smd circle (at -6 -1.2 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 48 "/FPGA PCIe/UMGT0_TX+") (solder_mask_margin 0.03175)) (pad H3 smd circle (at -5.2 -1.2 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.03175)) (pad H4 smd circle (at -4.4 -1.2 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.03175)) (pad H5 smd circle (at -3.6 -1.2 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.03175)) (pad H6 smd circle (at -2.8 -1.2 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.03175)) (pad H7 smd circle (at -2 -1.2 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 13 P1V0_VCC_FPGA_B) (solder_mask_margin 0.03175)) (pad H8 smd circle (at -1.2 -1.2 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.03175)) (pad H9 smd circle (at -0.4 -1.2 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 13 P1V0_VCC_FPGA_B) (solder_mask_margin 0.03175)) (pad H10 smd circle (at 0.4 -1.2 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.03175)) (pad H11 smd circle (at 1.2 -1.2 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 13 P1V0_VCC_FPGA_B) (solder_mask_margin 0.03175)) (pad H12 smd circle (at 2 -1.2 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.03175)) (pad H13 smd circle (at 2.8 -1.2 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 14 P1V8_FPGA_VCCAUX_B) (solder_mask_margin 0.03175)) (pad H14 smd circle (at 3.6 -1.2 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (solder_mask_margin 0.03175)) (pad H15 smd circle (at 4.4 -1.2 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 31 VCC_BANK14_B) (solder_mask_margin 0.03175)) (pad H16 smd circle (at 5.2 -1.2 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (solder_mask_margin 0.03175)) (pad H17 smd circle (at 6 -1.2 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (solder_mask_margin 0.03175)) (pad H18 smd circle (at 6.8 -1.2 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (solder_mask_margin 0.03175)) (pad J1 smd circle (at -6.8 -0.4 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.03175)) (pad J2 smd circle (at -6 -0.4 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.03175)) (pad J3 smd circle (at -5.2 -0.4 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.03175)) (pad J4 smd circle (at -4.4 -0.4 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (solder_mask_margin 0.03175)) (pad J5 smd circle (at -3.6 -0.4 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (solder_mask_margin 0.03175)) (pad J6 smd circle (at -2.8 -0.4 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (solder_mask_margin 0.03175)) (pad J7 smd circle (at -2 -0.4 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.03175)) (pad J8 smd circle (at -1.2 -0.4 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 13 P1V0_VCC_FPGA_B) (solder_mask_margin 0.03175)) (pad J9 smd circle (at -0.4 -0.4 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.03175)) (pad J10 smd circle (at 0.4 -0.4 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 14 P1V8_FPGA_VCCAUX_B) (solder_mask_margin 0.03175)) (pad J11 smd circle (at 1.2 -0.4 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.03175)) (pad J12 smd circle (at 2 -0.4 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 13 P1V0_VCC_FPGA_B) (solder_mask_margin 0.03175)) (pad J13 smd circle (at 2.8 -0.4 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.03175)) (pad J14 smd circle (at 3.6 -0.4 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (solder_mask_margin 0.03175)) (pad J15 smd circle (at 4.4 -0.4 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 44 "Net-(RN3-Pad6)") (solder_mask_margin 0.03175)) (pad J16 smd circle (at 5.2 -0.4 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 43 "Net-(RN3-Pad7)") (solder_mask_margin 0.03175)) (pad J17 smd circle (at 6 -0.4 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.03175)) (pad J18 smd circle (at 6.8 -0.4 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 31 VCC_BANK14_B) (solder_mask_margin 0.03175)) (pad K1 smd circle (at -6.8 0.4 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 36 W_DISABLE_2) (solder_mask_margin 0.03175)) (pad K2 smd circle (at -6 0.4 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 37 W_DISABLE_1) (solder_mask_margin 0.03175)) (pad K3 smd circle (at -5.2 0.4 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (solder_mask_margin 0.03175)) (pad K4 smd circle (at -4.4 0.4 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.03175)) (pad K5 smd circle (at -3.6 0.4 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (solder_mask_margin 0.03175)) (pad K6 smd circle (at -2.8 0.4 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (solder_mask_margin 0.03175)) (pad K7 smd circle (at -2 0.4 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 13 P1V0_VCC_FPGA_B) (solder_mask_margin 0.03175)) (pad K8 smd circle (at -1.2 0.4 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.03175)) (pad K9 smd circle (at -0.4 0.4 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.03175)) (pad K10 smd circle (at 0.4 0.4 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.03175)) (pad K11 smd circle (at 1.2 0.4 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 13 P1V0_VCC_FPGA_B) (solder_mask_margin 0.03175)) (pad K12 smd circle (at 2 0.4 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.03175)) (pad K13 smd circle (at 2.8 0.4 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 14 P1V8_FPGA_VCCAUX_B) (solder_mask_margin 0.03175)) (pad K14 smd circle (at 3.6 0.4 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.03175)) (pad K15 smd circle (at 4.4 0.4 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (solder_mask_margin 0.03175)) (pad K16 smd circle (at 5.2 0.4 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 6 "Net-(U1-PadK16)") (solder_mask_margin 0.03175)) (pad K17 smd circle (at 6 0.4 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (solder_mask_margin 0.03175)) (pad K18 smd circle (at 6.8 0.4 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (solder_mask_margin 0.03175)) (pad L1 smd circle (at -6.8 1.2 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.03175)) (pad L2 smd circle (at -6 1.2 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (solder_mask_margin 0.03175)) (pad L3 smd circle (at -5.2 1.2 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (solder_mask_margin 0.03175)) (pad L4 smd circle (at -4.4 1.2 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (solder_mask_margin 0.03175)) (pad L5 smd circle (at -3.6 1.2 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (solder_mask_margin 0.03175)) (pad L6 smd circle (at -2.8 1.2 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 31 VCC_BANK14_B) (solder_mask_margin 0.03175)) (pad L7 smd circle (at -2 1.2 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.03175)) (pad L8 smd circle (at -1.2 1.2 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 13 P1V0_VCC_FPGA_B) (solder_mask_margin 0.03175)) (pad L9 smd circle (at -0.4 1.2 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.03175)) (pad L10 smd circle (at 0.4 1.2 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.03175)) (pad L11 smd circle (at 1.2 1.2 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.03175)) (pad L12 smd circle (at 2 1.2 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 13 P1V0_VCC_FPGA_B) (solder_mask_margin 0.03175)) (pad L13 smd circle (at 2.8 1.2 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.03175)) (pad L14 smd circle (at 3.6 1.2 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (solder_mask_margin 0.03175)) (pad L15 smd circle (at 4.4 1.2 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 45 "Net-(RN3-Pad5)") (solder_mask_margin 0.03175)) (pad L16 smd circle (at 5.2 1.2 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 31 VCC_BANK14_B) (solder_mask_margin 0.03175)) (pad L17 smd circle (at 6 1.2 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 7 "Net-(U1-PadL17)") (solder_mask_margin 0.03175)) (pad L18 smd circle (at 6.8 1.2 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (solder_mask_margin 0.03175)) (pad M1 smd circle (at -6.8 2 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (solder_mask_margin 0.03175)) (pad M2 smd circle (at -6 2 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (solder_mask_margin 0.03175)) (pad M3 smd circle (at -5.2 2 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 31 VCC_BANK14_B) (solder_mask_margin 0.03175)) (pad M4 smd circle (at -4.4 2 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (solder_mask_margin 0.03175)) (pad M5 smd circle (at -3.6 2 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (solder_mask_margin 0.03175)) (pad M6 smd circle (at -2.8 2 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (solder_mask_margin 0.03175)) (pad M7 smd circle (at -2 2 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 13 P1V0_VCC_FPGA_B) (solder_mask_margin 0.03175)) (pad M8 smd circle (at -1.2 2 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.03175)) (pad M9 smd circle (at -0.4 2 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.03175)) (pad M10 smd circle (at 0.4 2 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.03175)) (pad M11 smd circle (at 1.2 2 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 13 P1V0_VCC_FPGA_B) (solder_mask_margin 0.03175)) (pad M12 smd circle (at 2 2 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.03175)) (pad M13 smd circle (at 2.8 2 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 14 P1V8_FPGA_VCCAUX_B) (solder_mask_margin 0.03175)) (pad M14 smd circle (at 3.6 2 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (solder_mask_margin 0.03175)) (pad M15 smd circle (at 4.4 2 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (solder_mask_margin 0.03175)) (pad M16 smd circle (at 5.2 2 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (solder_mask_margin 0.03175)) (pad M17 smd circle (at 6 2 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (solder_mask_margin 0.03175)) (pad M18 smd circle (at 6.8 2 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.03175)) (pad N1 smd circle (at -6.8 2.8 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (solder_mask_margin 0.03175)) (pad N2 smd circle (at -6 2.8 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (solder_mask_margin 0.03175)) (pad N3 smd circle (at -5.2 2.8 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (solder_mask_margin 0.03175)) (pad N4 smd circle (at -4.4 2.8 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (solder_mask_margin 0.03175)) (pad N5 smd circle (at -3.6 2.8 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.03175)) (pad N6 smd circle (at -2.8 2.8 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (solder_mask_margin 0.03175)) (pad N7 smd circle (at -2 2.8 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.03175)) (pad N8 smd circle (at -1.2 2.8 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 13 P1V0_VCC_FPGA_B) (solder_mask_margin 0.03175)) (pad N9 smd circle (at -0.4 2.8 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.03175)) (pad N10 smd circle (at 0.4 2.8 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 13 P1V0_VCC_FPGA_B) (solder_mask_margin 0.03175)) (pad N11 smd circle (at 1.2 2.8 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.03175)) (pad N12 smd circle (at 2 2.8 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 13 P1V0_VCC_FPGA_B) (solder_mask_margin 0.03175)) (pad N13 smd circle (at 2.8 2.8 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.03175)) (pad N14 smd circle (at 3.6 2.8 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (solder_mask_margin 0.03175)) (pad N15 smd circle (at 4.4 2.8 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.03175)) (pad N16 smd circle (at 5.2 2.8 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (solder_mask_margin 0.03175)) (pad N17 smd circle (at 6 2.8 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (solder_mask_margin 0.03175)) (pad N18 smd circle (at 6.8 2.8 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (solder_mask_margin 0.03175)) (pad P1 smd circle (at -6.8 3.6 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (solder_mask_margin 0.03175)) (pad P2 smd circle (at -6 3.6 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.03175)) (pad P3 smd circle (at -5.2 3.6 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (solder_mask_margin 0.03175)) (pad P4 smd circle (at -4.4 3.6 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (solder_mask_margin 0.03175)) (pad P5 smd circle (at -3.6 3.6 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (solder_mask_margin 0.03175)) (pad P6 smd circle (at -2.8 3.6 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (solder_mask_margin 0.03175)) (pad P7 smd circle (at -2 3.6 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 31 VCC_BANK14_B) (solder_mask_margin 0.03175)) (pad P8 smd circle (at -1.2 3.6 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.03175)) (pad P9 smd circle (at -0.4 3.6 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 13 P1V0_VCC_FPGA_B) (solder_mask_margin 0.03175)) (pad P10 smd circle (at 0.4 3.6 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 62 "Net-(RN1-Pad6)") (solder_mask_margin 0.03175)) (pad P11 smd circle (at 1.2 3.6 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 13 P1V0_VCC_FPGA_B) (solder_mask_margin 0.03175)) (pad P12 smd circle (at 2 3.6 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.03175)) (pad P13 smd circle (at 2.8 3.6 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 14 P1V8_FPGA_VCCAUX_B) (solder_mask_margin 0.03175)) (pad P14 smd circle (at 3.6 3.6 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (solder_mask_margin 0.03175)) (pad P15 smd circle (at 4.4 3.6 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (solder_mask_margin 0.03175)) (pad P16 smd circle (at 5.2 3.6 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (solder_mask_margin 0.03175)) (pad P17 smd circle (at 6 3.6 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 31 VCC_BANK14_B) (solder_mask_margin 0.03175)) (pad P18 smd circle (at 6.8 3.6 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (solder_mask_margin 0.03175)) (pad R1 smd circle (at -6.8 4.4 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (solder_mask_margin 0.03175)) (pad R2 smd circle (at -6 4.4 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (solder_mask_margin 0.03175)) (pad R3 smd circle (at -5.2 4.4 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (solder_mask_margin 0.03175)) (pad R4 smd circle (at -4.4 4.4 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 31 VCC_BANK14_B) (solder_mask_margin 0.03175)) (pad R5 smd circle (at -3.6 4.4 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (solder_mask_margin 0.03175)) (pad R6 smd circle (at -2.8 4.4 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (solder_mask_margin 0.03175)) (pad R7 smd circle (at -2 4.4 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (solder_mask_margin 0.03175)) (pad R8 smd circle (at -1.2 4.4 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 28 JTAG_TMS_B) (solder_mask_margin 0.03175)) (pad R9 smd circle (at -0.4 4.4 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.03175)) (pad R10 smd circle (at 0.4 4.4 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 31 VCC_BANK14_B) (solder_mask_margin 0.03175)) (pad R11 smd circle (at 1.2 4.4 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.03175)) (pad R12 smd circle (at 2 4.4 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 31 VCC_BANK14_B) (solder_mask_margin 0.03175)) (pad R13 smd circle (at 2.8 4.4 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (solder_mask_margin 0.03175)) (pad R14 smd circle (at 3.6 4.4 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 31 VCC_BANK14_B) (solder_mask_margin 0.03175)) (pad R15 smd circle (at 4.4 4.4 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (solder_mask_margin 0.03175)) (pad R16 smd circle (at 5.2 4.4 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (solder_mask_margin 0.03175)) (pad R17 smd circle (at 6 4.4 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (solder_mask_margin 0.03175)) (pad R18 smd circle (at 6.8 4.4 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (solder_mask_margin 0.03175)) (pad T1 smd circle (at -6.8 5.2 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 31 VCC_BANK14_B) (solder_mask_margin 0.03175)) (pad T2 smd circle (at -6 5.2 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (solder_mask_margin 0.03175)) (pad T3 smd circle (at -5.2 5.2 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (solder_mask_margin 0.03175)) (pad T4 smd circle (at -4.4 5.2 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (solder_mask_margin 0.03175)) (pad T5 smd circle (at -3.6 5.2 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (solder_mask_margin 0.03175)) (pad T6 smd circle (at -2.8 5.2 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.03175)) (pad T7 smd circle (at -2 5.2 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (solder_mask_margin 0.03175)) (pad T8 smd circle (at -1.2 5.2 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 29 JTAG_TDO_B) (solder_mask_margin 0.03175)) (pad T9 smd circle (at -0.4 5.2 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 30 JTAG_TDI_B) (solder_mask_margin 0.03175)) (pad T10 smd circle (at 0.4 5.2 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 61 "Net-(RN1-Pad7)") (solder_mask_margin 0.03175)) (pad T11 smd circle (at 1.2 5.2 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 31 VCC_BANK14_B) (solder_mask_margin 0.03175)) (pad T12 smd circle (at 2 5.2 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (solder_mask_margin 0.03175)) (pad T13 smd circle (at 2.8 5.2 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (solder_mask_margin 0.03175)) (pad T14 smd circle (at 3.6 5.2 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (solder_mask_margin 0.03175)) (pad T15 smd circle (at 4.4 5.2 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (solder_mask_margin 0.03175)) (pad T16 smd circle (at 5.2 5.2 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.03175)) (pad T17 smd circle (at 6 5.2 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (solder_mask_margin 0.03175)) (pad T18 smd circle (at 6.8 5.2 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (solder_mask_margin 0.03175)) (pad U1 smd circle (at -6.8 6 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (solder_mask_margin 0.03175)) (pad U2 smd circle (at -6 6 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (solder_mask_margin 0.03175)) (pad U3 smd circle (at -5.2 6 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.03175)) (pad U4 smd circle (at -4.4 6 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (solder_mask_margin 0.03175)) (pad U5 smd circle (at -3.6 6 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (solder_mask_margin 0.03175)) (pad U6 smd circle (at -2.8 6 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (solder_mask_margin 0.03175)) (pad U7 smd circle (at -2 6 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (solder_mask_margin 0.03175)) (pad U8 smd circle (at -1.2 6 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 31 VCC_BANK14_B) (solder_mask_margin 0.03175)) (pad U9 smd circle (at -0.4 6 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (solder_mask_margin 0.03175)) (pad U10 smd circle (at 0.4 6 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (solder_mask_margin 0.03175)) (pad U11 smd circle (at 1.2 6 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (solder_mask_margin 0.03175)) (pad U12 smd circle (at 2 6 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (solder_mask_margin 0.03175)) (pad U13 smd circle (at 2.8 6 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.03175)) (pad U14 smd circle (at 3.6 6 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (solder_mask_margin 0.03175)) (pad U15 smd circle (at 4.4 6 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (solder_mask_margin 0.03175)) (pad U16 smd circle (at 5.2 6 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (solder_mask_margin 0.03175)) (pad U17 smd circle (at 6 6 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (solder_mask_margin 0.03175)) (pad U18 smd circle (at 6.8 6 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 31 VCC_BANK14_B) (solder_mask_margin 0.03175)) (pad V1 smd circle (at -6.8 6.8 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.03175)) (pad V2 smd circle (at -6 6.8 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 38 M2_LED_1) (solder_mask_margin 0.03175)) (pad V3 smd circle (at -5.2 6.8 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 39 M2_LED_2) (solder_mask_margin 0.03175)) (pad V4 smd circle (at -4.4 6.8 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (solder_mask_margin 0.03175)) (pad V5 smd circle (at -3.6 6.8 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 31 VCC_BANK14_B) (solder_mask_margin 0.03175)) (pad V6 smd circle (at -2.8 6.8 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (solder_mask_margin 0.03175)) (pad V7 smd circle (at -2 6.8 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (solder_mask_margin 0.03175)) (pad V8 smd circle (at -1.2 6.8 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (solder_mask_margin 0.03175)) (pad V9 smd circle (at -0.4 6.8 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (solder_mask_margin 0.03175)) (pad V10 smd circle (at 0.4 6.8 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.03175)) (pad V11 smd circle (at 1.2 6.8 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (solder_mask_margin 0.03175)) (pad V12 smd circle (at 2 6.8 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 4 "Net-(D3-Pad1)") (solder_mask_margin 0.03175)) (pad V13 smd circle (at 2.8 6.8 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 5 "Net-(D4-Pad1)") (solder_mask_margin 0.03175)) (pad V14 smd circle (at 3.6 6.8 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 53 "Net-(D2-Pad1)") (solder_mask_margin 0.03175)) (pad V15 smd circle (at 4.4 6.8 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 31 VCC_BANK14_B) (solder_mask_margin 0.03175)) (pad V16 smd circle (at 5.2 6.8 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (solder_mask_margin 0.03175)) (pad V17 smd circle (at 6 6.8 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (solder_mask_margin 0.03175)) (pad V18 smd circle (at 6.8 6.8 270) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) (net 1 GND) (solder_mask_margin 0.03175)) (model /home/dr/Dropbox/kicad_lib/0_models/user/CSG324.wrl (at (xyz -0.295 0.295 0)) (scale (xyz 0.3937 0.3937 0.3937)) (rotate (xyz -90 0 0)) ) ) (module LEDs:LED_0402 (layer F.Cu) (tedit 5886D3F9) (tstamp 58818CFF) (at 60.15 72.64 180) (descr "LED 0402 smd package") (tags "LED led 0402 SMD smd SMT smt smdled SMDLED smtled SMTLED") (path /594F323A/587E337E) (attr smd) (fp_text reference D4 (at -0.25 0.03 180) (layer F.SilkS) (effects (font (size 0.508 0.508) (thickness 0.127))) ) (fp_text value C (at 1.21 -0.02 180) (layer F.SilkS) (effects (font (size 0.508 0.508) (thickness 0.127))) ) (fp_line (start -0.95 -0.45) (end -0.95 0.45) (layer F.SilkS) (width 0.12)) (fp_line (start -0.15 -0.2) (end -0.15 0.2) (layer F.Fab) (width 0.1)) (fp_line (start -0.15 0) (end 0.15 -0.2) (layer F.Fab) (width 0.1)) (fp_line (start 0.15 0.2) (end -0.15 0) (layer F.Fab) (width 0.1)) (fp_line (start 0.15 -0.2) (end 0.15 0.2) (layer F.Fab) (width 0.1)) (fp_line (start 0.5 0.25) (end -0.5 0.25) (layer F.Fab) (width 0.1)) (fp_line (start 0.5 -0.25) (end 0.5 0.25) (layer F.Fab) (width 0.1)) (fp_line (start -0.5 -0.25) (end 0.5 -0.25) (layer F.Fab) (width 0.1)) (fp_line (start -0.5 0.25) (end -0.5 -0.25) (layer F.Fab) (width 0.1)) (fp_line (start -0.95 0.45) (end 0.5 0.45) (layer F.SilkS) (width 0.12)) (fp_line (start -0.95 -0.45) (end 0.5 -0.45) (layer F.SilkS) (width 0.12)) (fp_line (start 1 -0.5) (end 1 0.5) (layer F.CrtYd) (width 0.05)) (fp_line (start 1 0.5) (end -1 0.5) (layer F.CrtYd) (width 0.05)) (fp_line (start -1 0.5) (end -1 -0.5) (layer F.CrtYd) (width 0.05)) (fp_line (start -1 -0.5) (end 1 -0.5) (layer F.CrtYd) (width 0.05)) (pad 2 smd rect (at 0.55 0) (size 0.6 0.7) (layers F.Cu F.Paste F.Mask) (net 42 "Net-(D4-Pad2)")) (pad 1 smd rect (at -0.55 0) (size 0.6 0.7) (layers F.Cu F.Paste F.Mask) (net 5 "Net-(D4-Pad1)")) (model LEDs.3dshapes/LED_0402.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 180)) ) ) (module LEDs:LED_0402 (layer F.Cu) (tedit 5886D3EF) (tstamp 58818CEA) (at 60.14 71.46 180) (descr "LED 0402 smd package") (tags "LED led 0402 SMD smd SMT smt smdled SMDLED smtled SMTLED") (path /594F323A/594F3235) (attr smd) (fp_text reference D3 (at -0.24 0.02 180) (layer F.SilkS) (effects (font (size 0.508 0.508) (thickness 0.127))) ) (fp_text value B (at 1.21 0 180) (layer F.SilkS) (effects (font (size 0.508 0.508) (thickness 0.127))) ) (fp_line (start -0.95 -0.45) (end -0.95 0.45) (layer F.SilkS) (width 0.12)) (fp_line (start -0.15 -0.2) (end -0.15 0.2) (layer F.Fab) (width 0.1)) (fp_line (start -0.15 0) (end 0.15 -0.2) (layer F.Fab) (width 0.1)) (fp_line (start 0.15 0.2) (end -0.15 0) (layer F.Fab) (width 0.1)) (fp_line (start 0.15 -0.2) (end 0.15 0.2) (layer F.Fab) (width 0.1)) (fp_line (start 0.5 0.25) (end -0.5 0.25) (layer F.Fab) (width 0.1)) (fp_line (start 0.5 -0.25) (end 0.5 0.25) (layer F.Fab) (width 0.1)) (fp_line (start -0.5 -0.25) (end 0.5 -0.25) (layer F.Fab) (width 0.1)) (fp_line (start -0.5 0.25) (end -0.5 -0.25) (layer F.Fab) (width 0.1)) (fp_line (start -0.95 0.45) (end 0.5 0.45) (layer F.SilkS) (width 0.12)) (fp_line (start -0.95 -0.45) (end 0.5 -0.45) (layer F.SilkS) (width 0.12)) (fp_line (start 1 -0.5) (end 1 0.5) (layer F.CrtYd) (width 0.05)) (fp_line (start 1 0.5) (end -1 0.5) (layer F.CrtYd) (width 0.05)) (fp_line (start -1 0.5) (end -1 -0.5) (layer F.CrtYd) (width 0.05)) (fp_line (start -1 -0.5) (end 1 -0.5) (layer F.CrtYd) (width 0.05)) (pad 2 smd rect (at 0.55 0) (size 0.6 0.7) (layers F.Cu F.Paste F.Mask) (net 41 "Net-(D3-Pad2)")) (pad 1 smd rect (at -0.55 0) (size 0.6 0.7) (layers F.Cu F.Paste F.Mask) (net 4 "Net-(D3-Pad1)")) (model LEDs.3dshapes/LED_0402.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 180)) ) ) (module LEDs:LED_0402 (layer F.Cu) (tedit 5886D3FD) (tstamp 58818CD5) (at 60.16 73.8 180) (descr "LED 0402 smd package") (tags "LED led 0402 SMD smd SMT smt smdled SMDLED smtled SMTLED") (path /594F323A/587E3396) (attr smd) (fp_text reference D2 (at -0.28 0.02 180) (layer F.SilkS) (effects (font (size 0.508 0.508) (thickness 0.127))) ) (fp_text value A (at 1.25 0.01 180) (layer F.SilkS) (effects (font (size 0.508 0.508) (thickness 0.127))) ) (fp_line (start -0.95 -0.45) (end -0.95 0.45) (layer F.SilkS) (width 0.12)) (fp_line (start -0.15 -0.2) (end -0.15 0.2) (layer F.Fab) (width 0.1)) (fp_line (start -0.15 0) (end 0.15 -0.2) (layer F.Fab) (width 0.1)) (fp_line (start 0.15 0.2) (end -0.15 0) (layer F.Fab) (width 0.1)) (fp_line (start 0.15 -0.2) (end 0.15 0.2) (layer F.Fab) (width 0.1)) (fp_line (start 0.5 0.25) (end -0.5 0.25) (layer F.Fab) (width 0.1)) (fp_line (start 0.5 -0.25) (end 0.5 0.25) (layer F.Fab) (width 0.1)) (fp_line (start -0.5 -0.25) (end 0.5 -0.25) (layer F.Fab) (width 0.1)) (fp_line (start -0.5 0.25) (end -0.5 -0.25) (layer F.Fab) (width 0.1)) (fp_line (start -0.95 0.45) (end 0.5 0.45) (layer F.SilkS) (width 0.12)) (fp_line (start -0.95 -0.45) (end 0.5 -0.45) (layer F.SilkS) (width 0.12)) (fp_line (start 1 -0.5) (end 1 0.5) (layer F.CrtYd) (width 0.05)) (fp_line (start 1 0.5) (end -1 0.5) (layer F.CrtYd) (width 0.05)) (fp_line (start -1 0.5) (end -1 -0.5) (layer F.CrtYd) (width 0.05)) (fp_line (start -1 -0.5) (end 1 -0.5) (layer F.CrtYd) (width 0.05)) (pad 2 smd rect (at 0.55 0) (size 0.6 0.7) (layers F.Cu F.Paste F.Mask) (net 52 "Net-(D2-Pad2)")) (pad 1 smd rect (at -0.55 0) (size 0.6 0.7) (layers F.Cu F.Paste F.Mask) (net 53 "Net-(D2-Pad1)")) (model LEDs.3dshapes/LED_0402.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 180)) ) ) (module Capacitors_SMD:C_0603 (layer B.Cu) (tedit 5415D631) (tstamp 58818B51) (at 58.47 68.1 180) (descr "Capacitor SMD 0603, reflow soldering, AVX (see smccp.pdf)") (tags "capacitor 0603") (path /594F323B/586DE91D) (attr smd) (fp_text reference C64 (at 2 0.06 180) (layer B.SilkS) (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_text value 22uf (at 0 -1.9 180) (layer B.Fab) (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_line (start -0.8 -0.4) (end -0.8 0.4) (layer B.Fab) (width 0.1)) (fp_line (start 0.8 -0.4) (end -0.8 -0.4) (layer B.Fab) (width 0.1)) (fp_line (start 0.8 0.4) (end 0.8 -0.4) (layer B.Fab) (width 0.1)) (fp_line (start -0.8 0.4) (end 0.8 0.4) (layer B.Fab) (width 0.1)) (fp_line (start -1.45 0.75) (end 1.45 0.75) (layer B.CrtYd) (width 0.05)) (fp_line (start -1.45 -0.75) (end 1.45 -0.75) (layer B.CrtYd) (width 0.05)) (fp_line (start -1.45 0.75) (end -1.45 -0.75) (layer B.CrtYd) (width 0.05)) (fp_line (start 1.45 0.75) (end 1.45 -0.75) (layer B.CrtYd) (width 0.05)) (fp_line (start -0.35 0.6) (end 0.35 0.6) (layer B.SilkS) (width 0.12)) (fp_line (start 0.35 -0.6) (end -0.35 -0.6) (layer B.SilkS) (width 0.12)) (pad 1 smd rect (at -0.75 0 180) (size 0.8 0.75) (layers B.Cu B.Paste B.Mask) (net 13 P1V0_VCC_FPGA_B)) (pad 2 smd rect (at 0.75 0 180) (size 0.8 0.75) (layers B.Cu B.Paste B.Mask) (net 1 GND)) (model Capacitors_SMD.3dshapes/C_0603.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 0)) ) ) (module Capacitors_SMD:C_0603 (layer B.Cu) (tedit 5415D631) (tstamp 58818AE1) (at 58.44 62.38 180) (descr "Capacitor SMD 0603, reflow soldering, AVX (see smccp.pdf)") (tags "capacitor 0603") (path /594F323B/594F31D2) (attr smd) (fp_text reference C56 (at -0.01 -1.05 180) (layer B.SilkS) (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_text value 22uf (at 0 -1.9 180) (layer B.Fab) (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_line (start -0.8 -0.4) (end -0.8 0.4) (layer B.Fab) (width 0.1)) (fp_line (start 0.8 -0.4) (end -0.8 -0.4) (layer B.Fab) (width 0.1)) (fp_line (start 0.8 0.4) (end 0.8 -0.4) (layer B.Fab) (width 0.1)) (fp_line (start -0.8 0.4) (end 0.8 0.4) (layer B.Fab) (width 0.1)) (fp_line (start -1.45 0.75) (end 1.45 0.75) (layer B.CrtYd) (width 0.05)) (fp_line (start -1.45 -0.75) (end 1.45 -0.75) (layer B.CrtYd) (width 0.05)) (fp_line (start -1.45 0.75) (end -1.45 -0.75) (layer B.CrtYd) (width 0.05)) (fp_line (start 1.45 0.75) (end 1.45 -0.75) (layer B.CrtYd) (width 0.05)) (fp_line (start -0.35 0.6) (end 0.35 0.6) (layer B.SilkS) (width 0.12)) (fp_line (start 0.35 -0.6) (end -0.35 -0.6) (layer B.SilkS) (width 0.12)) (pad 1 smd rect (at -0.75 0 180) (size 0.8 0.75) (layers B.Cu B.Paste B.Mask) (net 2 "Net-(C56-Pad1)")) (pad 2 smd rect (at 0.75 0 180) (size 0.8 0.75) (layers B.Cu B.Paste B.Mask) (net 1 GND)) (model Capacitors_SMD.3dshapes/C_0603.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 0)) ) ) (module Capacitors_SMD:C_0603 (layer B.Cu) (tedit 5415D631) (tstamp 588188E1) (at 75.27 67.25 90) (descr "Capacitor SMD 0603, reflow soldering, AVX (see smccp.pdf)") (tags "capacitor 0603") (path /5881899D/586B56E0) (attr smd) (fp_text reference C30 (at 0.01 1.08 90) (layer B.SilkS) (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_text value 47uf (at 0 -1.9 90) (layer B.Fab) (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_line (start -0.8 -0.4) (end -0.8 0.4) (layer B.Fab) (width 0.1)) (fp_line (start 0.8 -0.4) (end -0.8 -0.4) (layer B.Fab) (width 0.1)) (fp_line (start 0.8 0.4) (end 0.8 -0.4) (layer B.Fab) (width 0.1)) (fp_line (start -0.8 0.4) (end 0.8 0.4) (layer B.Fab) (width 0.1)) (fp_line (start -1.45 0.75) (end 1.45 0.75) (layer B.CrtYd) (width 0.05)) (fp_line (start -1.45 -0.75) (end 1.45 -0.75) (layer B.CrtYd) (width 0.05)) (fp_line (start -1.45 0.75) (end -1.45 -0.75) (layer B.CrtYd) (width 0.05)) (fp_line (start 1.45 0.75) (end 1.45 -0.75) (layer B.CrtYd) (width 0.05)) (fp_line (start -0.35 0.6) (end 0.35 0.6) (layer B.SilkS) (width 0.12)) (fp_line (start 0.35 -0.6) (end -0.35 -0.6) (layer B.SilkS) (width 0.12)) (pad 1 smd rect (at -0.75 0 90) (size 0.8 0.75) (layers B.Cu B.Paste B.Mask) (net 31 VCC_BANK14_B)) (pad 2 smd rect (at 0.75 0 90) (size 0.8 0.75) (layers B.Cu B.Paste B.Mask) (net 1 GND)) (model Capacitors_SMD.3dshapes/C_0603.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 0)) ) ) (module Capacitors_SMD:C_0603 (layer B.Cu) (tedit 5415D631) (tstamp 588188D1) (at 66.87 79.5 90) (descr "Capacitor SMD 0603, reflow soldering, AVX (see smccp.pdf)") (tags "capacitor 0603") (path /5881899D/586B50CE) (attr smd) (fp_text reference C29 (at 2.05 0.02 90) (layer B.SilkS) (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_text value 47uf (at 0 -1.9 90) (layer B.Fab) (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_line (start -0.8 -0.4) (end -0.8 0.4) (layer B.Fab) (width 0.1)) (fp_line (start 0.8 -0.4) (end -0.8 -0.4) (layer B.Fab) (width 0.1)) (fp_line (start 0.8 0.4) (end 0.8 -0.4) (layer B.Fab) (width 0.1)) (fp_line (start -0.8 0.4) (end 0.8 0.4) (layer B.Fab) (width 0.1)) (fp_line (start -1.45 0.75) (end 1.45 0.75) (layer B.CrtYd) (width 0.05)) (fp_line (start -1.45 -0.75) (end 1.45 -0.75) (layer B.CrtYd) (width 0.05)) (fp_line (start -1.45 0.75) (end -1.45 -0.75) (layer B.CrtYd) (width 0.05)) (fp_line (start 1.45 0.75) (end 1.45 -0.75) (layer B.CrtYd) (width 0.05)) (fp_line (start -0.35 0.6) (end 0.35 0.6) (layer B.SilkS) (width 0.12)) (fp_line (start 0.35 -0.6) (end -0.35 -0.6) (layer B.SilkS) (width 0.12)) (pad 1 smd rect (at -0.75 0 90) (size 0.8 0.75) (layers B.Cu B.Paste B.Mask) (net 31 VCC_BANK14_B)) (pad 2 smd rect (at 0.75 0 90) (size 0.8 0.75) (layers B.Cu B.Paste B.Mask) (net 1 GND)) (model Capacitors_SMD.3dshapes/C_0603.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 0)) ) ) (module Capacitors_SMD:C_0603 (layer B.Cu) (tedit 5415D631) (tstamp 588188C1) (at 61.86 81.97 180) (descr "Capacitor SMD 0603, reflow soldering, AVX (see smccp.pdf)") (tags "capacitor 0603") (path /5881899D/594F320C) (attr smd) (fp_text reference C28 (at -0.03 -1.12 180) (layer B.SilkS) (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_text value 47uf (at 0 -1.9 180) (layer B.Fab) (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_line (start -0.8 -0.4) (end -0.8 0.4) (layer B.Fab) (width 0.1)) (fp_line (start 0.8 -0.4) (end -0.8 -0.4) (layer B.Fab) (width 0.1)) (fp_line (start 0.8 0.4) (end 0.8 -0.4) (layer B.Fab) (width 0.1)) (fp_line (start -0.8 0.4) (end 0.8 0.4) (layer B.Fab) (width 0.1)) (fp_line (start -1.45 0.75) (end 1.45 0.75) (layer B.CrtYd) (width 0.05)) (fp_line (start -1.45 -0.75) (end 1.45 -0.75) (layer B.CrtYd) (width 0.05)) (fp_line (start -1.45 0.75) (end -1.45 -0.75) (layer B.CrtYd) (width 0.05)) (fp_line (start 1.45 0.75) (end 1.45 -0.75) (layer B.CrtYd) (width 0.05)) (fp_line (start -0.35 0.6) (end 0.35 0.6) (layer B.SilkS) (width 0.12)) (fp_line (start 0.35 -0.6) (end -0.35 -0.6) (layer B.SilkS) (width 0.12)) (pad 1 smd rect (at -0.75 0 180) (size 0.8 0.75) (layers B.Cu B.Paste B.Mask) (net 31 VCC_BANK14_B)) (pad 2 smd rect (at 0.75 0 180) (size 0.8 0.75) (layers B.Cu B.Paste B.Mask) (net 1 GND)) (model Capacitors_SMD.3dshapes/C_0603.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 0)) ) ) (module Capacitors_SMD:C_0603 (layer B.Cu) (tedit 5415D631) (tstamp 588188B1) (at 57.91 72.24) (descr "Capacitor SMD 0603, reflow soldering, AVX (see smccp.pdf)") (tags "capacitor 0603") (path /5881899D/594F31F5) (attr smd) (fp_text reference C27 (at -0.06 1.05) (layer B.SilkS) (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_text value 47uf (at 0 -1.9) (layer B.Fab) (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_line (start -0.8 -0.4) (end -0.8 0.4) (layer B.Fab) (width 0.1)) (fp_line (start 0.8 -0.4) (end -0.8 -0.4) (layer B.Fab) (width 0.1)) (fp_line (start 0.8 0.4) (end 0.8 -0.4) (layer B.Fab) (width 0.1)) (fp_line (start -0.8 0.4) (end 0.8 0.4) (layer B.Fab) (width 0.1)) (fp_line (start -1.45 0.75) (end 1.45 0.75) (layer B.CrtYd) (width 0.05)) (fp_line (start -1.45 -0.75) (end 1.45 -0.75) (layer B.CrtYd) (width 0.05)) (fp_line (start -1.45 0.75) (end -1.45 -0.75) (layer B.CrtYd) (width 0.05)) (fp_line (start 1.45 0.75) (end 1.45 -0.75) (layer B.CrtYd) (width 0.05)) (fp_line (start -0.35 0.6) (end 0.35 0.6) (layer B.SilkS) (width 0.12)) (fp_line (start 0.35 -0.6) (end -0.35 -0.6) (layer B.SilkS) (width 0.12)) (pad 1 smd rect (at -0.75 0) (size 0.8 0.75) (layers B.Cu B.Paste B.Mask) (net 31 VCC_BANK14_B)) (pad 2 smd rect (at 0.75 0) (size 0.8 0.75) (layers B.Cu B.Paste B.Mask) (net 1 GND)) (model Capacitors_SMD.3dshapes/C_0603.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 0)) ) ) (module Capacitors_SMD:C_0603 (layer F.Cu) (tedit 5415D631) (tstamp 58818791) (at 60.87 63.04 90) (descr "Capacitor SMD 0603, reflow soldering, AVX (see smccp.pdf)") (tags "capacitor 0603") (path /5881899D/5889AA19) (attr smd) (fp_text reference C4 (at -0.16 -1.1 270) (layer F.SilkS) (effects (font (size 0.508 0.508) (thickness 0.127))) ) (fp_text value 47uf (at 0 1.9 90) (layer F.Fab) (effects (font (size 0.508 0.508) (thickness 0.127))) ) (fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1)) (fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1)) (fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1)) (fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1)) (fp_line (start -1.45 -0.75) (end 1.45 -0.75) (layer F.CrtYd) (width 0.05)) (fp_line (start -1.45 0.75) (end 1.45 0.75) (layer F.CrtYd) (width 0.05)) (fp_line (start -1.45 -0.75) (end -1.45 0.75) (layer F.CrtYd) (width 0.05)) (fp_line (start 1.45 -0.75) (end 1.45 0.75) (layer F.CrtYd) (width 0.05)) (fp_line (start -0.35 -0.6) (end 0.35 -0.6) (layer F.SilkS) (width 0.12)) (fp_line (start 0.35 0.6) (end -0.35 0.6) (layer F.SilkS) (width 0.12)) (pad 1 smd rect (at -0.75 0 90) (size 0.8 0.75) (layers F.Cu F.Paste F.Mask) (net 14 P1V8_FPGA_VCCAUX_B)) (pad 2 smd rect (at 0.75 0 90) (size 0.8 0.75) (layers F.Cu F.Paste F.Mask) (net 1 GND)) (model Capacitors_SMD.3dshapes/C_0603.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 0)) ) ) (module SMT:c_0201_least (layer F.Cu) (tedit 5932E5BD) (tstamp 588947E2) (at 69.46 58.98 315) (path /588189A7/594F3244) (attr smd) (fp_text reference C71 (at 0.021213 0.700036 495) (layer F.SilkS) (effects (font (size 0.508 0.508) (thickness 0.127))) ) (fp_text value 0.1uf (at -0.1 0.5 315) (layer F.Fab) (effects (font (size 0.508 0.508) (thickness 0.127))) ) (fp_line (start -0.6 0.3) (end -0.6 -0.3) (layer F.SilkS) (width 0.05)) (fp_line (start 0.6 0.3) (end -0.6 0.3) (layer F.SilkS) (width 0.05)) (fp_line (start 0.6 -0.3) (end 0.6 0.3) (layer F.SilkS) (width 0.05)) (fp_line (start -0.6 -0.3) (end 0.6 -0.3) (layer F.SilkS) (width 0.05)) (pad 1 smd rect (at -0.28 0 315) (size 0.36 0.32) (layers F.Cu F.Paste F.Mask) (net 33 "/M2 edge/PECLK_2+")) (pad 2 smd rect (at 0.28 0 315) (size 0.36 0.32) (layers F.Cu F.Paste F.Mask) (net 17 MGT_REFCLK0_B+)) (model Capacitors_SMD.3dshapes/C_0201.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 0)) ) ) (module SMT:c_0201_least (layer B.Cu) (tedit 58881732) (tstamp 5889481E) (at 68.84 71.2 270) (path /5881899D/58898FA5) (attr smd) (fp_text reference C21 (at 0.06 0.71 270) (layer B.SilkS) (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_text value 0.47uf (at -0.1 -0.5 270) (layer B.Fab) (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_line (start -0.6 -0.3) (end -0.6 0.3) (layer B.SilkS) (width 0.05)) (fp_line (start 0.6 -0.3) (end -0.6 -0.3) (layer B.SilkS) (width 0.05)) (fp_line (start 0.6 0.3) (end 0.6 -0.3) (layer B.SilkS) (width 0.05)) (fp_line (start -0.6 0.3) (end 0.6 0.3) (layer B.SilkS) (width 0.05)) (pad 1 smd rect (at -0.28 0 270) (size 0.36 0.32) (layers B.Cu B.Paste B.Mask) (net 14 P1V8_FPGA_VCCAUX_B)) (pad 2 smd rect (at 0.28 0 270) (size 0.36 0.32) (layers B.Cu B.Paste B.Mask) (net 1 GND)) (model Capacitors_SMD.3dshapes/C_0201.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 0)) ) ) (module SMT:c_0201_least (layer F.Cu) (tedit 58881732) (tstamp 58894800) (at 69.96 58.48 315) (path /588189A7/58818F26) (attr smd) (fp_text reference C73 (at 0.014142 -0.692965 315) (layer F.SilkS) (effects (font (size 0.508 0.508) (thickness 0.127))) ) (fp_text value 0.1uf (at -0.1 0.5 315) (layer F.Fab) (effects (font (size 0.508 0.508) (thickness 0.127))) ) (fp_line (start -0.6 0.3) (end -0.6 -0.3) (layer F.SilkS) (width 0.05)) (fp_line (start 0.6 0.3) (end -0.6 0.3) (layer F.SilkS) (width 0.05)) (fp_line (start 0.6 -0.3) (end 0.6 0.3) (layer F.SilkS) (width 0.05)) (fp_line (start -0.6 -0.3) (end 0.6 -0.3) (layer F.SilkS) (width 0.05)) (pad 1 smd rect (at -0.28 0 315) (size 0.36 0.32) (layers F.Cu F.Paste F.Mask) (net 35 "/M2 edge/PECLK_2-")) (pad 2 smd rect (at 0.28 0 315) (size 0.36 0.32) (layers F.Cu F.Paste F.Mask) (net 19 MGT_REFCLK0_B-)) (model Capacitors_SMD.3dshapes/C_0201.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 0)) ) ) (module SMT:c_0201_least (layer F.Cu) (tedit 58881732) (tstamp 588947F1) (at 67.6 58.76 90) (path /588189A7/594F3242) (attr smd) (fp_text reference C72 (at 0.55 0.71 270) (layer F.SilkS) (effects (font (size 0.508 0.508) (thickness 0.127))) ) (fp_text value 0.1uf (at -0.1 0.5 90) (layer F.Fab) (effects (font (size 0.508 0.508) (thickness 0.127))) ) (fp_line (start -0.6 0.3) (end -0.6 -0.3) (layer F.SilkS) (width 0.05)) (fp_line (start 0.6 0.3) (end -0.6 0.3) (layer F.SilkS) (width 0.05)) (fp_line (start 0.6 -0.3) (end 0.6 0.3) (layer F.SilkS) (width 0.05)) (fp_line (start -0.6 -0.3) (end 0.6 -0.3) (layer F.SilkS) (width 0.05)) (pad 1 smd rect (at -0.28 0 90) (size 0.36 0.32) (layers F.Cu F.Paste F.Mask) (net 18 MGT0_TX_B-)) (pad 2 smd rect (at 0.28 0 90) (size 0.36 0.32) (layers F.Cu F.Paste F.Mask) (net 34 "/M2 edge/PETX0_2-")) (model Capacitors_SMD.3dshapes/C_0201.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 0)) ) ) (module SMT:c_0201_least (layer F.Cu) (tedit 58881732) (tstamp 588947D3) (at 66.94 58.76 90) (path /588189A7/58818F05) (attr smd) (fp_text reference C70 (at 0.52 -0.7 90) (layer F.SilkS) (effects (font (size 0.508 0.508) (thickness 0.127))) ) (fp_text value 0.1uf (at -0.1 0.5 90) (layer F.Fab) (effects (font (size 0.508 0.508) (thickness 0.127))) ) (fp_line (start -0.6 0.3) (end -0.6 -0.3) (layer F.SilkS) (width 0.05)) (fp_line (start 0.6 0.3) (end -0.6 0.3) (layer F.SilkS) (width 0.05)) (fp_line (start 0.6 -0.3) (end 0.6 0.3) (layer F.SilkS) (width 0.05)) (fp_line (start -0.6 -0.3) (end 0.6 -0.3) (layer F.SilkS) (width 0.05)) (pad 1 smd rect (at -0.28 0 90) (size 0.36 0.32) (layers F.Cu F.Paste F.Mask) (net 16 MGT0_TX_B+)) (pad 2 smd rect (at 0.28 0 90) (size 0.36 0.32) (layers F.Cu F.Paste F.Mask) (net 32 "/M2 edge/PETX0_2+")) (model Capacitors_SMD.3dshapes/C_0201.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 0)) ) ) (module SMT:c_0201_least (layer F.Cu) (tedit 58881732) (tstamp 58894788) (at 62.36 77.09 270) (path /588189A5/587DA8D6) (attr smd) (fp_text reference C69 (at -0.06 0.67 270) (layer F.SilkS) (effects (font (size 0.508 0.508) (thickness 0.127))) ) (fp_text value 0.1uf (at -0.1 0.5 270) (layer F.Fab) (effects (font (size 0.508 0.508) (thickness 0.127))) ) (fp_line (start -0.6 0.3) (end -0.6 -0.3) (layer F.SilkS) (width 0.05)) (fp_line (start 0.6 0.3) (end -0.6 0.3) (layer F.SilkS) (width 0.05)) (fp_line (start 0.6 -0.3) (end 0.6 0.3) (layer F.SilkS) (width 0.05)) (fp_line (start -0.6 -0.3) (end 0.6 -0.3) (layer F.SilkS) (width 0.05)) (pad 1 smd rect (at -0.28 0 270) (size 0.36 0.32) (layers F.Cu F.Paste F.Mask) (net 31 VCC_BANK14_B)) (pad 2 smd rect (at 0.28 0 270) (size 0.36 0.32) (layers F.Cu F.Paste F.Mask) (net 1 GND)) (model Capacitors_SMD.3dshapes/C_0201.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 0)) ) ) (module SMT:c_0201_least (layer F.Cu) (tedit 58881732) (tstamp 58894779) (at 63.67 79.63 90) (path /588189A5/587DA891) (attr smd) (fp_text reference C68 (at 1.4 0.1 90) (layer F.SilkS) (effects (font (size 0.508 0.508) (thickness 0.127))) ) (fp_text value 0.1uf (at -0.1 0.5 90) (layer F.Fab) (effects (font (size 0.508 0.508) (thickness 0.127))) ) (fp_line (start -0.6 0.3) (end -0.6 -0.3) (layer F.SilkS) (width 0.05)) (fp_line (start 0.6 0.3) (end -0.6 0.3) (layer F.SilkS) (width 0.05)) (fp_line (start 0.6 -0.3) (end 0.6 0.3) (layer F.SilkS) (width 0.05)) (fp_line (start -0.6 -0.3) (end 0.6 -0.3) (layer F.SilkS) (width 0.05)) (pad 1 smd rect (at -0.28 0 90) (size 0.36 0.32) (layers F.Cu F.Paste F.Mask) (net 31 VCC_BANK14_B)) (pad 2 smd rect (at 0.28 0 90) (size 0.36 0.32) (layers F.Cu F.Paste F.Mask) (net 1 GND)) (model Capacitors_SMD.3dshapes/C_0201.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 0)) ) ) (module SMT:c_0201_least (layer F.Cu) (tedit 58881732) (tstamp 5889476A) (at 64.65 79.31 180) (path /588189A5/587DA52B) (attr smd) (fp_text reference C67 (at -1.6 0.13 180) (layer F.SilkS) (effects (font (size 0.508 0.508) (thickness 0.127))) ) (fp_text value 0.1uf (at -0.1 0.5 180) (layer F.Fab) (effects (font (size 0.508 0.508) (thickness 0.127))) ) (fp_line (start -0.6 0.3) (end -0.6 -0.3) (layer F.SilkS) (width 0.05)) (fp_line (start 0.6 0.3) (end -0.6 0.3) (layer F.SilkS) (width 0.05)) (fp_line (start 0.6 -0.3) (end 0.6 0.3) (layer F.SilkS) (width 0.05)) (fp_line (start -0.6 -0.3) (end 0.6 -0.3) (layer F.SilkS) (width 0.05)) (pad 1 smd rect (at -0.28 0 180) (size 0.36 0.32) (layers F.Cu F.Paste F.Mask) (net 31 VCC_BANK14_B)) (pad 2 smd rect (at 0.28 0 180) (size 0.36 0.32) (layers F.Cu F.Paste F.Mask) (net 1 GND)) (model Capacitors_SMD.3dshapes/C_0201.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 0)) ) ) (module SMT:c_0201_least (layer F.Cu) (tedit 58881732) (tstamp 58894710) (at 72.84 58.77 180) (path /594F323B/586A0CBD) (attr smd) (fp_text reference C59 (at 0.55 0.71 180) (layer F.SilkS) (effects (font (size 0.508 0.508) (thickness 0.127))) ) (fp_text value 0.1uf (at -0.1 0.5 180) (layer F.Fab) (effects (font (size 0.508 0.508) (thickness 0.127))) ) (fp_line (start -0.6 0.3) (end -0.6 -0.3) (layer F.SilkS) (width 0.05)) (fp_line (start 0.6 0.3) (end -0.6 0.3) (layer F.SilkS) (width 0.05)) (fp_line (start 0.6 -0.3) (end 0.6 0.3) (layer F.SilkS) (width 0.05)) (fp_line (start -0.6 -0.3) (end 0.6 -0.3) (layer F.SilkS) (width 0.05)) (pad 1 smd rect (at -0.28 0 180) (size 0.36 0.32) (layers F.Cu F.Paste F.Mask) (net 31 VCC_BANK14_B)) (pad 2 smd rect (at 0.28 0 180) (size 0.36 0.32) (layers F.Cu F.Paste F.Mask) (net 1 GND)) (model Capacitors_SMD.3dshapes/C_0201.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 0)) ) ) (module SMT:c_0201_least (layer B.Cu) (tedit 58881732) (tstamp 58894701) (at 71.24 69.83 90) (path /5881899D/594F3263) (attr smd) (fp_text reference C19 (at -1.39 0 90) (layer B.SilkS) (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_text value 0.47uf (at -0.1 -0.5 90) (layer B.Fab) (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_line (start -0.6 -0.3) (end -0.6 0.3) (layer B.SilkS) (width 0.05)) (fp_line (start 0.6 -0.3) (end -0.6 -0.3) (layer B.SilkS) (width 0.05)) (fp_line (start 0.6 0.3) (end 0.6 -0.3) (layer B.SilkS) (width 0.05)) (fp_line (start -0.6 0.3) (end 0.6 0.3) (layer B.SilkS) (width 0.05)) (pad 1 smd rect (at -0.28 0 90) (size 0.36 0.32) (layers B.Cu B.Paste B.Mask) (net 14 P1V8_FPGA_VCCAUX_B)) (pad 2 smd rect (at 0.28 0 90) (size 0.36 0.32) (layers B.Cu B.Paste B.Mask) (net 1 GND)) (model Capacitors_SMD.3dshapes/C_0201.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 0)) ) ) (module SMT:c_0201_least (layer B.Cu) (tedit 58881732) (tstamp 588946F2) (at 71.24 68.24 90) (path /5881899D/594F3266) (attr smd) (fp_text reference C17 (at 0.53 -0.63 90) (layer B.SilkS) (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_text value 0.47uf (at -0.1 -0.5 90) (layer B.Fab) (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_line (start -0.6 -0.3) (end -0.6 0.3) (layer B.SilkS) (width 0.05)) (fp_line (start 0.6 -0.3) (end -0.6 -0.3) (layer B.SilkS) (width 0.05)) (fp_line (start 0.6 0.3) (end 0.6 -0.3) (layer B.SilkS) (width 0.05)) (fp_line (start -0.6 0.3) (end 0.6 0.3) (layer B.SilkS) (width 0.05)) (pad 1 smd rect (at -0.28 0 90) (size 0.36 0.32) (layers B.Cu B.Paste B.Mask) (net 13 P1V0_VCC_FPGA_B)) (pad 2 smd rect (at 0.28 0 90) (size 0.36 0.32) (layers B.Cu B.Paste B.Mask) (net 1 GND)) (model Capacitors_SMD.3dshapes/C_0201.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 0)) ) ) (module SMT:c_0201_least (layer B.Cu) (tedit 58881732) (tstamp 588946E3) (at 72.03 64.81 270) (path /5881899D/58897065) (attr smd) (fp_text reference C13 (at -1.35 0.05 270) (layer B.SilkS) (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_text value 0.1uf (at -0.1 -0.5 270) (layer B.Fab) (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_line (start -0.6 -0.3) (end -0.6 0.3) (layer B.SilkS) (width 0.05)) (fp_line (start 0.6 -0.3) (end -0.6 -0.3) (layer B.SilkS) (width 0.05)) (fp_line (start 0.6 0.3) (end 0.6 -0.3) (layer B.SilkS) (width 0.05)) (fp_line (start -0.6 0.3) (end 0.6 0.3) (layer B.SilkS) (width 0.05)) (pad 1 smd rect (at -0.28 0 270) (size 0.36 0.32) (layers B.Cu B.Paste B.Mask) (net 12 P1V0_MGTAVCC_B)) (pad 2 smd rect (at 0.28 0 270) (size 0.36 0.32) (layers B.Cu B.Paste B.Mask) (net 1 GND)) (model Capacitors_SMD.3dshapes/C_0201.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 0)) ) ) (module SMT:c_0201_least (layer B.Cu) (tedit 58881732) (tstamp 588946B6) (at 67.44201 63.11201 315) (path /5881899D/586B56C3) (attr smd) (fp_text reference C50 (at 0.025442 0.678823 315) (layer B.SilkS) (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_text value 0.47uf (at -0.1 -0.5 315) (layer B.Fab) (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_line (start -0.6 -0.3) (end -0.6 0.3) (layer B.SilkS) (width 0.05)) (fp_line (start 0.6 -0.3) (end -0.6 -0.3) (layer B.SilkS) (width 0.05)) (fp_line (start 0.6 0.3) (end 0.6 -0.3) (layer B.SilkS) (width 0.05)) (fp_line (start -0.6 0.3) (end 0.6 0.3) (layer B.SilkS) (width 0.05)) (pad 1 smd rect (at -0.28 0 315) (size 0.36 0.32) (layers B.Cu B.Paste B.Mask) (net 31 VCC_BANK14_B)) (pad 2 smd rect (at 0.28 0 315) (size 0.36 0.32) (layers B.Cu B.Paste B.Mask) (net 1 GND)) (model Capacitors_SMD.3dshapes/C_0201.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 0)) ) ) (module SMT:c_0201_least (layer B.Cu) (tedit 58881732) (tstamp 588946A7) (at 74.64 68.72 315) (path /5881899D/594F3216) (attr smd) (fp_text reference C49 (at -1.378858 -0.091924 315) (layer B.SilkS) (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_text value 0.47uf (at -0.1 -0.5 315) (layer B.Fab) (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_line (start -0.6 -0.3) (end -0.6 0.3) (layer B.SilkS) (width 0.05)) (fp_line (start 0.6 -0.3) (end -0.6 -0.3) (layer B.SilkS) (width 0.05)) (fp_line (start 0.6 0.3) (end 0.6 -0.3) (layer B.SilkS) (width 0.05)) (fp_line (start -0.6 0.3) (end 0.6 0.3) (layer B.SilkS) (width 0.05)) (pad 1 smd rect (at -0.28 0 315) (size 0.36 0.32) (layers B.Cu B.Paste B.Mask) (net 31 VCC_BANK14_B)) (pad 2 smd rect (at 0.28 0 315) (size 0.36 0.32) (layers B.Cu B.Paste B.Mask) (net 1 GND)) (model Capacitors_SMD.3dshapes/C_0201.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 0)) ) ) (module SMT:c_0201_least (layer B.Cu) (tedit 58881732) (tstamp 58894698) (at 62.15 72.52 180) (path /5881899D/586CB24E) (attr smd) (fp_text reference C48 (at -0.02 -0.72 180) (layer B.SilkS) (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_text value 0.47uf (at -0.1 -0.5 180) (layer B.Fab) (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_line (start -0.6 -0.3) (end -0.6 0.3) (layer B.SilkS) (width 0.05)) (fp_line (start 0.6 -0.3) (end -0.6 -0.3) (layer B.SilkS) (width 0.05)) (fp_line (start 0.6 0.3) (end 0.6 -0.3) (layer B.SilkS) (width 0.05)) (fp_line (start -0.6 0.3) (end 0.6 0.3) (layer B.SilkS) (width 0.05)) (pad 1 smd rect (at -0.28 0 180) (size 0.36 0.32) (layers B.Cu B.Paste B.Mask) (net 31 VCC_BANK14_B)) (pad 2 smd rect (at 0.28 0 180) (size 0.36 0.32) (layers B.Cu B.Paste B.Mask) (net 1 GND)) (model Capacitors_SMD.3dshapes/C_0201.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 0)) ) ) (module SMT:c_0201_least (layer B.Cu) (tedit 58881732) (tstamp 5889466B) (at 63.24 61.52 180) (path /5881899D/586B56BD) (attr smd) (fp_text reference C47 (at 0.03 -0.7 180) (layer B.SilkS) (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_text value 0.47uf (at -0.1 -0.5 180) (layer B.Fab) (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_line (start -0.6 -0.3) (end -0.6 0.3) (layer B.SilkS) (width 0.05)) (fp_line (start 0.6 -0.3) (end -0.6 -0.3) (layer B.SilkS) (width 0.05)) (fp_line (start 0.6 0.3) (end 0.6 -0.3) (layer B.SilkS) (width 0.05)) (fp_line (start -0.6 0.3) (end 0.6 0.3) (layer B.SilkS) (width 0.05)) (pad 1 smd rect (at -0.28 0 180) (size 0.36 0.32) (layers B.Cu B.Paste B.Mask) (net 31 VCC_BANK14_B)) (pad 2 smd rect (at 0.28 0 180) (size 0.36 0.32) (layers B.Cu B.Paste B.Mask) (net 1 GND)) (model Capacitors_SMD.3dshapes/C_0201.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 0)) ) ) (module SMT:c_0201_least (layer B.Cu) (tedit 58881732) (tstamp 5889465C) (at 75.04201 70.72201 135) (path /5881899D/586CC1EE) (attr smd) (fp_text reference C46 (at -0.053726 0.692965 135) (layer B.SilkS) (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_text value 0.47uf (at -0.1 -0.5 135) (layer B.Fab) (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_line (start -0.6 -0.3) (end -0.6 0.3) (layer B.SilkS) (width 0.05)) (fp_line (start 0.6 -0.3) (end -0.6 -0.3) (layer B.SilkS) (width 0.05)) (fp_line (start 0.6 0.3) (end 0.6 -0.3) (layer B.SilkS) (width 0.05)) (fp_line (start -0.6 0.3) (end 0.6 0.3) (layer B.SilkS) (width 0.05)) (pad 1 smd rect (at -0.28 0 135) (size 0.36 0.32) (layers B.Cu B.Paste B.Mask) (net 31 VCC_BANK14_B)) (pad 2 smd rect (at 0.28 0 135) (size 0.36 0.32) (layers B.Cu B.Paste B.Mask) (net 1 GND)) (model Capacitors_SMD.3dshapes/C_0201.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 0)) ) ) (module SMT:c_0201_least (layer B.Cu) (tedit 58881732) (tstamp 5889464D) (at 67.78 73.06 135) (path /5881899D/586CB193) (attr smd) (fp_text reference C45 (at -1.400071 0.070711 135) (layer B.SilkS) (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_text value 0.47uf (at -0.1 -0.5 135) (layer B.Fab) (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_line (start -0.6 -0.3) (end -0.6 0.3) (layer B.SilkS) (width 0.05)) (fp_line (start 0.6 -0.3) (end -0.6 -0.3) (layer B.SilkS) (width 0.05)) (fp_line (start 0.6 0.3) (end 0.6 -0.3) (layer B.SilkS) (width 0.05)) (fp_line (start -0.6 0.3) (end 0.6 0.3) (layer B.SilkS) (width 0.05)) (pad 1 smd rect (at -0.28 0 135) (size 0.36 0.32) (layers B.Cu B.Paste B.Mask) (net 31 VCC_BANK14_B)) (pad 2 smd rect (at 0.28 0 135) (size 0.36 0.32) (layers B.Cu B.Paste B.Mask) (net 1 GND)) (model Capacitors_SMD.3dshapes/C_0201.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 0)) ) ) (module SMT:c_0201_least (layer B.Cu) (tedit 58881732) (tstamp 5889463E) (at 64.83 68.11 90) (path /5881899D/594F3218) (attr smd) (fp_text reference C41 (at -0.02 -0.67 90) (layer B.SilkS) (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_text value 0.47uf (at -0.1 -0.5 90) (layer B.Fab) (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_line (start -0.6 -0.3) (end -0.6 0.3) (layer B.SilkS) (width 0.05)) (fp_line (start 0.6 -0.3) (end -0.6 -0.3) (layer B.SilkS) (width 0.05)) (fp_line (start 0.6 0.3) (end 0.6 -0.3) (layer B.SilkS) (width 0.05)) (fp_line (start -0.6 0.3) (end 0.6 0.3) (layer B.SilkS) (width 0.05)) (pad 1 smd rect (at -0.28 0 90) (size 0.36 0.32) (layers B.Cu B.Paste B.Mask) (net 31 VCC_BANK14_B)) (pad 2 smd rect (at 0.28 0 90) (size 0.36 0.32) (layers B.Cu B.Paste B.Mask) (net 1 GND)) (model Capacitors_SMD.3dshapes/C_0201.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 0)) ) ) (module SMT:c_0201_least (layer B.Cu) (tedit 58881732) (tstamp 5889462F) (at 62.16 64.52 180) (path /5881899D/586B56B7) (attr smd) (fp_text reference C44 (at -1.37 0.01 180) (layer B.SilkS) (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_text value 0.47uf (at -0.1 -0.5 180) (layer B.Fab) (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_line (start -0.6 -0.3) (end -0.6 0.3) (layer B.SilkS) (width 0.05)) (fp_line (start 0.6 -0.3) (end -0.6 -0.3) (layer B.SilkS) (width 0.05)) (fp_line (start 0.6 0.3) (end 0.6 -0.3) (layer B.SilkS) (width 0.05)) (fp_line (start -0.6 0.3) (end 0.6 0.3) (layer B.SilkS) (width 0.05)) (pad 1 smd rect (at -0.28 0 180) (size 0.36 0.32) (layers B.Cu B.Paste B.Mask) (net 31 VCC_BANK14_B)) (pad 2 smd rect (at 0.28 0 180) (size 0.36 0.32) (layers B.Cu B.Paste B.Mask) (net 1 GND)) (model Capacitors_SMD.3dshapes/C_0201.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 0)) ) ) (module SMT:c_0201_least (layer B.Cu) (tedit 58881732) (tstamp 58894620) (at 70.64 72.72 315) (path /5881899D/586CC1E8) (attr smd) (fp_text reference C43 (at -0.056569 0.707107 315) (layer B.SilkS) (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_text value 0.47uf (at -0.1 -0.5 315) (layer B.Fab) (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_line (start -0.6 -0.3) (end -0.6 0.3) (layer B.SilkS) (width 0.05)) (fp_line (start 0.6 -0.3) (end -0.6 -0.3) (layer B.SilkS) (width 0.05)) (fp_line (start 0.6 0.3) (end 0.6 -0.3) (layer B.SilkS) (width 0.05)) (fp_line (start -0.6 0.3) (end 0.6 0.3) (layer B.SilkS) (width 0.05)) (pad 1 smd rect (at -0.28 0 315) (size 0.36 0.32) (layers B.Cu B.Paste B.Mask) (net 31 VCC_BANK14_B)) (pad 2 smd rect (at 0.28 0 315) (size 0.36 0.32) (layers B.Cu B.Paste B.Mask) (net 1 GND)) (model Capacitors_SMD.3dshapes/C_0201.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 0)) ) ) (module SMT:c_0201_least (layer B.Cu) (tedit 58881732) (tstamp 58894611) (at 62.96 74.92 180) (path /5881899D/586CB0BF) (attr smd) (fp_text reference C42 (at 1.38 0.01 180) (layer B.SilkS) (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_text value 0.47uf (at -0.1 -0.5 180) (layer B.Fab) (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_line (start -0.6 -0.3) (end -0.6 0.3) (layer B.SilkS) (width 0.05)) (fp_line (start 0.6 -0.3) (end -0.6 -0.3) (layer B.SilkS) (width 0.05)) (fp_line (start 0.6 0.3) (end 0.6 -0.3) (layer B.SilkS) (width 0.05)) (fp_line (start -0.6 0.3) (end 0.6 0.3) (layer B.SilkS) (width 0.05)) (pad 1 smd rect (at -0.28 0 180) (size 0.36 0.32) (layers B.Cu B.Paste B.Mask) (net 31 VCC_BANK14_B)) (pad 2 smd rect (at 0.28 0 180) (size 0.36 0.32) (layers B.Cu B.Paste B.Mask) (net 1 GND)) (model Capacitors_SMD.3dshapes/C_0201.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 0)) ) ) (module SMT:c_0201_least (layer B.Cu) (tedit 58881732) (tstamp 588945F3) (at 68.04 65.6 270) (path /5881899D/586B56B1) (attr smd) (fp_text reference C40 (at -0.19 0.71 270) (layer B.SilkS) (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_text value 0.47uf (at -0.1 -0.5 270) (layer B.Fab) (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_line (start -0.6 -0.3) (end -0.6 0.3) (layer B.SilkS) (width 0.05)) (fp_line (start 0.6 -0.3) (end -0.6 -0.3) (layer B.SilkS) (width 0.05)) (fp_line (start 0.6 0.3) (end 0.6 -0.3) (layer B.SilkS) (width 0.05)) (fp_line (start -0.6 0.3) (end 0.6 0.3) (layer B.SilkS) (width 0.05)) (pad 1 smd rect (at -0.28 0 270) (size 0.36 0.32) (layers B.Cu B.Paste B.Mask) (net 31 VCC_BANK14_B)) (pad 2 smd rect (at 0.28 0 270) (size 0.36 0.32) (layers B.Cu B.Paste B.Mask) (net 1 GND)) (model Capacitors_SMD.3dshapes/C_0201.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 0)) ) ) (module SMT:c_0201_least (layer B.Cu) (tedit 58881732) (tstamp 588945D5) (at 64.32 69.32) (path /5881899D/594F320E) (attr smd) (fp_text reference C38 (at -0.06 0.69) (layer B.SilkS) (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_text value 0.47uf (at -0.1 -0.5) (layer B.Fab) (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_line (start -0.6 -0.3) (end -0.6 0.3) (layer B.SilkS) (width 0.05)) (fp_line (start 0.6 -0.3) (end -0.6 -0.3) (layer B.SilkS) (width 0.05)) (fp_line (start 0.6 0.3) (end 0.6 -0.3) (layer B.SilkS) (width 0.05)) (fp_line (start -0.6 0.3) (end 0.6 0.3) (layer B.SilkS) (width 0.05)) (pad 1 smd rect (at -0.28 0) (size 0.36 0.32) (layers B.Cu B.Paste B.Mask) (net 31 VCC_BANK14_B)) (pad 2 smd rect (at 0.28 0) (size 0.36 0.32) (layers B.Cu B.Paste B.Mask) (net 1 GND)) (model Capacitors_SMD.3dshapes/C_0201.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 0)) ) ) (module SMT:c_0201_least (layer B.Cu) (tedit 58881732) (tstamp 588945C6) (at 72.84 68.23 90) (path /5881899D/594F3217) (attr smd) (fp_text reference C37 (at -0.81 0.69 90) (layer B.SilkS) (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_text value 0.47uf (at -0.1 -0.5 90) (layer B.Fab) (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_line (start -0.6 -0.3) (end -0.6 0.3) (layer B.SilkS) (width 0.05)) (fp_line (start 0.6 -0.3) (end -0.6 -0.3) (layer B.SilkS) (width 0.05)) (fp_line (start 0.6 0.3) (end 0.6 -0.3) (layer B.SilkS) (width 0.05)) (fp_line (start -0.6 0.3) (end 0.6 0.3) (layer B.SilkS) (width 0.05)) (pad 1 smd rect (at -0.28 0 90) (size 0.36 0.32) (layers B.Cu B.Paste B.Mask) (net 31 VCC_BANK14_B)) (pad 2 smd rect (at 0.28 0 90) (size 0.36 0.32) (layers B.Cu B.Paste B.Mask) (net 1 GND)) (model Capacitors_SMD.3dshapes/C_0201.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 0)) ) ) (module SMT:c_0201_least (layer B.Cu) (tedit 58881732) (tstamp 588945B7) (at 70.35 66.5 270) (path /5881899D/594F31EF) (attr smd) (fp_text reference C25 (at 0.06 0.72 270) (layer B.SilkS) (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_text value 0.47uf (at -0.1 -0.5 270) (layer B.Fab) (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_line (start -0.6 -0.3) (end -0.6 0.3) (layer B.SilkS) (width 0.05)) (fp_line (start 0.6 -0.3) (end -0.6 -0.3) (layer B.SilkS) (width 0.05)) (fp_line (start 0.6 0.3) (end 0.6 -0.3) (layer B.SilkS) (width 0.05)) (fp_line (start -0.6 0.3) (end 0.6 0.3) (layer B.SilkS) (width 0.05)) (pad 1 smd rect (at -0.28 0 270) (size 0.36 0.32) (layers B.Cu B.Paste B.Mask) (net 13 P1V0_VCC_FPGA_B)) (pad 2 smd rect (at 0.28 0 270) (size 0.36 0.32) (layers B.Cu B.Paste B.Mask) (net 1 GND)) (model Capacitors_SMD.3dshapes/C_0201.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 0)) ) ) (module SMT:c_0201_least (layer B.Cu) (tedit 58881732) (tstamp 588945A8) (at 67.37 69.03 90) (path /5881899D/594F31EE) (attr smd) (fp_text reference C24 (at -1.37 0.01 90) (layer B.SilkS) (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_text value 0.47uf (at -0.1 -0.5 90) (layer B.Fab) (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_line (start -0.6 -0.3) (end -0.6 0.3) (layer B.SilkS) (width 0.05)) (fp_line (start 0.6 -0.3) (end -0.6 -0.3) (layer B.SilkS) (width 0.05)) (fp_line (start 0.6 0.3) (end 0.6 -0.3) (layer B.SilkS) (width 0.05)) (fp_line (start -0.6 0.3) (end 0.6 0.3) (layer B.SilkS) (width 0.05)) (pad 1 smd rect (at -0.28 0 90) (size 0.36 0.32) (layers B.Cu B.Paste B.Mask) (net 13 P1V0_VCC_FPGA_B)) (pad 2 smd rect (at 0.28 0 90) (size 0.36 0.32) (layers B.Cu B.Paste B.Mask) (net 1 GND)) (model Capacitors_SMD.3dshapes/C_0201.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 0)) ) ) (module SMT:c_0201_least (layer B.Cu) (tedit 58881732) (tstamp 58894599) (at 72.05 68 270) (path /5881899D/594F31ED) (attr smd) (fp_text reference C22 (at -0.99 0.07 360) (layer B.SilkS) (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_text value 0.47uf (at -0.1 -0.5 270) (layer B.Fab) (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_line (start -0.6 -0.3) (end -0.6 0.3) (layer B.SilkS) (width 0.05)) (fp_line (start 0.6 -0.3) (end -0.6 -0.3) (layer B.SilkS) (width 0.05)) (fp_line (start 0.6 0.3) (end 0.6 -0.3) (layer B.SilkS) (width 0.05)) (fp_line (start -0.6 0.3) (end 0.6 0.3) (layer B.SilkS) (width 0.05)) (pad 1 smd rect (at -0.28 0 270) (size 0.36 0.32) (layers B.Cu B.Paste B.Mask) (net 13 P1V0_VCC_FPGA_B)) (pad 2 smd rect (at 0.28 0 270) (size 0.36 0.32) (layers B.Cu B.Paste B.Mask) (net 1 GND)) (model Capacitors_SMD.3dshapes/C_0201.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 0)) ) ) (module SMT:c_0201_least (layer B.Cu) (tedit 58881732) (tstamp 5889458A) (at 66.44 67.2 270) (path /5881899D/594F31F3) (attr smd) (fp_text reference C20 (at 0.11 0.71 270) (layer B.SilkS) (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_text value 0.47uf (at -0.1 -0.5 270) (layer B.Fab) (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_line (start -0.6 -0.3) (end -0.6 0.3) (layer B.SilkS) (width 0.05)) (fp_line (start 0.6 -0.3) (end -0.6 -0.3) (layer B.SilkS) (width 0.05)) (fp_line (start 0.6 0.3) (end 0.6 -0.3) (layer B.SilkS) (width 0.05)) (fp_line (start -0.6 0.3) (end 0.6 0.3) (layer B.SilkS) (width 0.05)) (pad 1 smd rect (at -0.28 0 270) (size 0.36 0.32) (layers B.Cu B.Paste B.Mask) (net 13 P1V0_VCC_FPGA_B)) (pad 2 smd rect (at 0.28 0 270) (size 0.36 0.32) (layers B.Cu B.Paste B.Mask) (net 1 GND)) (model Capacitors_SMD.3dshapes/C_0201.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 0)) ) ) (module SMT:c_0201_least (layer B.Cu) (tedit 58881732) (tstamp 5889457B) (at 68.04 67.2 270) (path /5881899D/594F31F2) (attr smd) (fp_text reference C18 (at 0.06 0.71 270) (layer B.SilkS) (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_text value 0.47uf (at -0.1 -0.5 270) (layer B.Fab) (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_line (start -0.6 -0.3) (end -0.6 0.3) (layer B.SilkS) (width 0.05)) (fp_line (start 0.6 -0.3) (end -0.6 -0.3) (layer B.SilkS) (width 0.05)) (fp_line (start 0.6 0.3) (end 0.6 -0.3) (layer B.SilkS) (width 0.05)) (fp_line (start -0.6 0.3) (end 0.6 0.3) (layer B.SilkS) (width 0.05)) (pad 1 smd rect (at -0.28 0 270) (size 0.36 0.32) (layers B.Cu B.Paste B.Mask) (net 13 P1V0_VCC_FPGA_B)) (pad 2 smd rect (at 0.28 0 270) (size 0.36 0.32) (layers B.Cu B.Paste B.Mask) (net 1 GND)) (model Capacitors_SMD.3dshapes/C_0201.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 0)) ) ) (module SMT:c_0201_least (layer B.Cu) (tedit 58881732) (tstamp 5889456C) (at 72.32 69.31) (path /5881899D/594F3265) (attr smd) (fp_text reference C12 (at 0.06 0.65) (layer B.SilkS) (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_text value 0.47uf (at -0.1 -0.5) (layer B.Fab) (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_line (start -0.6 -0.3) (end -0.6 0.3) (layer B.SilkS) (width 0.05)) (fp_line (start 0.6 -0.3) (end -0.6 -0.3) (layer B.SilkS) (width 0.05)) (fp_line (start 0.6 0.3) (end 0.6 -0.3) (layer B.SilkS) (width 0.05)) (fp_line (start -0.6 0.3) (end 0.6 0.3) (layer B.SilkS) (width 0.05)) (pad 1 smd rect (at -0.28 0) (size 0.36 0.32) (layers B.Cu B.Paste B.Mask) (net 13 P1V0_VCC_FPGA_B)) (pad 2 smd rect (at 0.28 0) (size 0.36 0.32) (layers B.Cu B.Paste B.Mask) (net 1 GND)) (model Capacitors_SMD.3dshapes/C_0201.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 0)) ) ) (module SMT:c_0201_least (layer B.Cu) (tedit 58881732) (tstamp 5889455D) (at 76.26 61.6 90) (path /5881899D/586A738F) (attr smd) (fp_text reference C14 (at -0.07 0.69 90) (layer B.SilkS) (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_text value 0.1uf (at -0.1 -0.5 90) (layer B.Fab) (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_line (start -0.6 -0.3) (end -0.6 0.3) (layer B.SilkS) (width 0.05)) (fp_line (start 0.6 -0.3) (end -0.6 -0.3) (layer B.SilkS) (width 0.05)) (fp_line (start 0.6 0.3) (end 0.6 -0.3) (layer B.SilkS) (width 0.05)) (fp_line (start -0.6 0.3) (end 0.6 0.3) (layer B.SilkS) (width 0.05)) (pad 1 smd rect (at -0.28 0 90) (size 0.36 0.32) (layers B.Cu B.Paste B.Mask) (net 15 P1V2_MGTAVTT_B)) (pad 2 smd rect (at 0.28 0 90) (size 0.36 0.32) (layers B.Cu B.Paste B.Mask) (net 1 GND)) (model Capacitors_SMD.3dshapes/C_0201.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 0)) ) ) (module SMT:c_0201_least (layer B.Cu) (tedit 58881732) (tstamp 5889454E) (at 65.64 70.64 90) (path /5881899D/586AA426) (attr smd) (fp_text reference C16 (at -0.08 0.72 90) (layer B.SilkS) (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_text value 0.47uf (at -0.1 -0.5 90) (layer B.Fab) (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_line (start -0.6 -0.3) (end -0.6 0.3) (layer B.SilkS) (width 0.05)) (fp_line (start 0.6 -0.3) (end -0.6 -0.3) (layer B.SilkS) (width 0.05)) (fp_line (start 0.6 0.3) (end 0.6 -0.3) (layer B.SilkS) (width 0.05)) (fp_line (start -0.6 0.3) (end 0.6 0.3) (layer B.SilkS) (width 0.05)) (pad 1 smd rect (at -0.28 0 90) (size 0.36 0.32) (layers B.Cu B.Paste B.Mask) (net 14 P1V8_FPGA_VCCAUX_B)) (pad 2 smd rect (at 0.28 0 90) (size 0.36 0.32) (layers B.Cu B.Paste B.Mask) (net 1 GND)) (model Capacitors_SMD.3dshapes/C_0201.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 0)) ) ) (module SMT:c_0201_least (layer B.Cu) (tedit 58881732) (tstamp 58894530) (at 71.23 61.83 90) (path /5881899D/594F31E9) (attr smd) (fp_text reference C10 (at 0.07 0.65 90) (layer B.SilkS) (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_text value 0.1uf (at -0.1 -0.5 90) (layer B.Fab) (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_line (start -0.6 -0.3) (end -0.6 0.3) (layer B.SilkS) (width 0.05)) (fp_line (start 0.6 -0.3) (end -0.6 -0.3) (layer B.SilkS) (width 0.05)) (fp_line (start 0.6 0.3) (end 0.6 -0.3) (layer B.SilkS) (width 0.05)) (fp_line (start -0.6 0.3) (end 0.6 0.3) (layer B.SilkS) (width 0.05)) (pad 1 smd rect (at -0.28 0 90) (size 0.36 0.32) (layers B.Cu B.Paste B.Mask) (net 15 P1V2_MGTAVTT_B)) (pad 2 smd rect (at 0.28 0 90) (size 0.36 0.32) (layers B.Cu B.Paste B.Mask) (net 1 GND)) (model Capacitors_SMD.3dshapes/C_0201.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 0)) ) ) (module SMT:c_0201_least (layer B.Cu) (tedit 58881732) (tstamp 58894521) (at 70.44 69.05 90) (path /5881899D/594F31EB) (attr smd) (fp_text reference C7 (at -1.15 0 90) (layer B.SilkS) (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_text value 0.47uf (at -0.1 -0.5 90) (layer B.Fab) (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_line (start -0.6 -0.3) (end -0.6 0.3) (layer B.SilkS) (width 0.05)) (fp_line (start 0.6 -0.3) (end -0.6 -0.3) (layer B.SilkS) (width 0.05)) (fp_line (start 0.6 0.3) (end 0.6 -0.3) (layer B.SilkS) (width 0.05)) (fp_line (start -0.6 0.3) (end 0.6 0.3) (layer B.SilkS) (width 0.05)) (pad 1 smd rect (at -0.28 0 90) (size 0.36 0.32) (layers B.Cu B.Paste B.Mask) (net 13 P1V0_VCC_FPGA_B)) (pad 2 smd rect (at 0.28 0 90) (size 0.36 0.32) (layers B.Cu B.Paste B.Mask) (net 1 GND)) (model Capacitors_SMD.3dshapes/C_0201.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 0)) ) ) (module SMT:c_0201_least (layer B.Cu) (tedit 58881732) (tstamp 58894512) (at 75.24 63.43 90) (path /5881899D/594F325D) (attr smd) (fp_text reference C9 (at 0 0.69 90) (layer B.SilkS) (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_text value 0.1uf (at -0.1 -0.5 90) (layer B.Fab) (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_line (start -0.6 -0.3) (end -0.6 0.3) (layer B.SilkS) (width 0.05)) (fp_line (start 0.6 -0.3) (end -0.6 -0.3) (layer B.SilkS) (width 0.05)) (fp_line (start 0.6 0.3) (end 0.6 -0.3) (layer B.SilkS) (width 0.05)) (fp_line (start -0.6 0.3) (end 0.6 0.3) (layer B.SilkS) (width 0.05)) (pad 1 smd rect (at -0.28 0 90) (size 0.36 0.32) (layers B.Cu B.Paste B.Mask) (net 12 P1V0_MGTAVCC_B)) (pad 2 smd rect (at 0.28 0 90) (size 0.36 0.32) (layers B.Cu B.Paste B.Mask) (net 1 GND)) (model Capacitors_SMD.3dshapes/C_0201.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 0)) ) ) (module SMT:c_0201_least (layer B.Cu) (tedit 58881732) (tstamp 58986B51) (at 68.84 69.6 270) (path /5881899D/588A4700) (attr smd) (fp_text reference C26 (at 0.04 0.67 270) (layer B.SilkS) (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_text value 0.47uf (at -0.1 -0.5 270) (layer B.Fab) (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_line (start -0.6 -0.3) (end -0.6 0.3) (layer B.SilkS) (width 0.05)) (fp_line (start 0.6 -0.3) (end -0.6 -0.3) (layer B.SilkS) (width 0.05)) (fp_line (start 0.6 0.3) (end 0.6 -0.3) (layer B.SilkS) (width 0.05)) (fp_line (start -0.6 0.3) (end 0.6 0.3) (layer B.SilkS) (width 0.05)) (pad 1 smd rect (at -0.28 0 270) (size 0.36 0.32) (layers B.Cu B.Paste B.Mask) (net 13 P1V0_VCC_FPGA_B)) (pad 2 smd rect (at 0.28 0 270) (size 0.36 0.32) (layers B.Cu B.Paste B.Mask) (net 1 GND)) (model Capacitors_SMD.3dshapes/C_0201.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 0)) ) ) (module SMT:c_0402 (layer B.Cu) (tedit 58897D18) (tstamp 58818921) (at 65.01 62.62 90) (path /5881899D/594F31FF) (attr smd) (fp_text reference C33 (at 0.5 0.92 90) (layer B.SilkS) (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_text value 4.7uf (at -0.5 0.7 90) (layer B.Fab) hide (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_line (start -1 -0.5) (end -1 0.5) (layer B.SilkS) (width 0.05)) (fp_line (start 1 -0.5) (end -1 -0.5) (layer B.SilkS) (width 0.05)) (fp_line (start 1 0.5) (end 1 -0.5) (layer B.SilkS) (width 0.05)) (fp_line (start -1 0.5) (end 1 0.5) (layer B.SilkS) (width 0.05)) (pad 1 smd rect (at -0.5 0 90) (size 0.6 0.7) (layers B.Cu B.Paste B.Mask) (net 31 VCC_BANK14_B)) (pad 2 smd rect (at 0.5 0 90) (size 0.6 0.7) (layers B.Cu B.Paste B.Mask) (net 1 GND)) (model Capacitors_SMD.3dshapes/C_0402.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 0)) ) ) (module SMT:c_0402 (layer B.Cu) (tedit 58897D18) (tstamp 5889453F) (at 64.26 70.99 180) (path /5881899D/594F3262) (attr smd) (fp_text reference C11 (at 1.8 -0.01 180) (layer B.SilkS) (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_text value 4.7uf (at -0.5 0.7 180) (layer B.Fab) hide (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_line (start -1 -0.5) (end -1 0.5) (layer B.SilkS) (width 0.05)) (fp_line (start 1 -0.5) (end -1 -0.5) (layer B.SilkS) (width 0.05)) (fp_line (start 1 0.5) (end 1 -0.5) (layer B.SilkS) (width 0.05)) (fp_line (start -1 0.5) (end 1 0.5) (layer B.SilkS) (width 0.05)) (pad 1 smd rect (at -0.5 0 180) (size 0.6 0.7) (layers B.Cu B.Paste B.Mask) (net 14 P1V8_FPGA_VCCAUX_B)) (pad 2 smd rect (at 0.5 0 180) (size 0.6 0.7) (layers B.Cu B.Paste B.Mask) (net 1 GND)) (model Capacitors_SMD.3dshapes/C_0402.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 0)) ) ) (module SMT:c_0402 (layer B.Cu) (tedit 58897D18) (tstamp 588187A1) (at 73.65 62.42 270) (path /5881899D/594F31E8) (attr smd) (fp_text reference C2 (at 0.14 -0.89 270) (layer B.SilkS) (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_text value 4.7uf (at -0.5 0.7 270) (layer B.Fab) hide (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_line (start -1 -0.5) (end -1 0.5) (layer B.SilkS) (width 0.05)) (fp_line (start 1 -0.5) (end -1 -0.5) (layer B.SilkS) (width 0.05)) (fp_line (start 1 0.5) (end 1 -0.5) (layer B.SilkS) (width 0.05)) (fp_line (start -1 0.5) (end 1 0.5) (layer B.SilkS) (width 0.05)) (pad 1 smd rect (at -0.5 0 270) (size 0.6 0.7) (layers B.Cu B.Paste B.Mask) (net 15 P1V2_MGTAVTT_B)) (pad 2 smd rect (at 0.5 0 270) (size 0.6 0.7) (layers B.Cu B.Paste B.Mask) (net 1 GND)) (model Capacitors_SMD.3dshapes/C_0402.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 0)) ) ) (module SMT:c_0402 (layer B.Cu) (tedit 58897D18) (tstamp 588187B1) (at 69.03 64.86 90) (path /5881899D/594F3260) (attr smd) (fp_text reference C5 (at 1.5 -0.1 90) (layer B.SilkS) (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_text value 4.7uf (at -0.5 0.7 90) (layer B.Fab) hide (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_line (start -1 -0.5) (end -1 0.5) (layer B.SilkS) (width 0.05)) (fp_line (start 1 -0.5) (end -1 -0.5) (layer B.SilkS) (width 0.05)) (fp_line (start 1 0.5) (end 1 -0.5) (layer B.SilkS) (width 0.05)) (fp_line (start -1 0.5) (end 1 0.5) (layer B.SilkS) (width 0.05)) (pad 1 smd rect (at -0.5 0 90) (size 0.6 0.7) (layers B.Cu B.Paste B.Mask) (net 13 P1V0_VCC_FPGA_B)) (pad 2 smd rect (at 0.5 0 90) (size 0.6 0.7) (layers B.Cu B.Paste B.Mask) (net 1 GND)) (model Capacitors_SMD.3dshapes/C_0402.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 0)) ) ) (module SMT:c_0402 (layer B.Cu) (tedit 58897D18) (tstamp 588187E1) (at 73.2 71.08) (path /5881899D/586AC00D) (attr smd) (fp_text reference C6 (at 1.54 0.53) (layer B.SilkS) (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_text value 4.7uf (at -0.5 0.7) (layer B.Fab) hide (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_line (start -1 -0.5) (end -1 0.5) (layer B.SilkS) (width 0.05)) (fp_line (start 1 -0.5) (end -1 -0.5) (layer B.SilkS) (width 0.05)) (fp_line (start 1 0.5) (end 1 -0.5) (layer B.SilkS) (width 0.05)) (fp_line (start -1 0.5) (end 1 0.5) (layer B.SilkS) (width 0.05)) (pad 1 smd rect (at -0.5 0) (size 0.6 0.7) (layers B.Cu B.Paste B.Mask) (net 14 P1V8_FPGA_VCCAUX_B)) (pad 2 smd rect (at 0.5 0) (size 0.6 0.7) (layers B.Cu B.Paste B.Mask) (net 1 GND)) (model Capacitors_SMD.3dshapes/C_0402.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 0)) ) ) (module SMT:c_0402 (layer B.Cu) (tedit 58897D18) (tstamp 58818811) (at 66 69.32) (path /5881899D/594F31F1) (attr smd) (fp_text reference C8 (at 0.13 -0.91) (layer B.SilkS) (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_text value 4.7uf (at -0.5 0.7) (layer B.Fab) hide (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_line (start -1 -0.5) (end -1 0.5) (layer B.SilkS) (width 0.05)) (fp_line (start 1 -0.5) (end -1 -0.5) (layer B.SilkS) (width 0.05)) (fp_line (start 1 0.5) (end 1 -0.5) (layer B.SilkS) (width 0.05)) (fp_line (start -1 0.5) (end 1 0.5) (layer B.SilkS) (width 0.05)) (pad 1 smd rect (at -0.5 0) (size 0.6 0.7) (layers B.Cu B.Paste B.Mask) (net 13 P1V0_VCC_FPGA_B)) (pad 2 smd rect (at 0.5 0) (size 0.6 0.7) (layers B.Cu B.Paste B.Mask) (net 1 GND)) (model Capacitors_SMD.3dshapes/C_0402.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 0)) ) ) (module SMT:c_0402 (layer B.Cu) (tedit 58897D18) (tstamp 58818851) (at 71.69 66.12 180) (path /5881899D/594F31F0) (attr smd) (fp_text reference C15 (at 0.86 0.91 180) (layer B.SilkS) (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_text value 4.7uf (at -0.5 0.7 180) (layer B.Fab) hide (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_line (start -1 -0.5) (end -1 0.5) (layer B.SilkS) (width 0.05)) (fp_line (start 1 -0.5) (end -1 -0.5) (layer B.SilkS) (width 0.05)) (fp_line (start 1 0.5) (end 1 -0.5) (layer B.SilkS) (width 0.05)) (fp_line (start -1 0.5) (end 1 0.5) (layer B.SilkS) (width 0.05)) (pad 1 smd rect (at -0.5 0 180) (size 0.6 0.7) (layers B.Cu B.Paste B.Mask) (net 13 P1V0_VCC_FPGA_B)) (pad 2 smd rect (at 0.5 0 180) (size 0.6 0.7) (layers B.Cu B.Paste B.Mask) (net 1 GND)) (model Capacitors_SMD.3dshapes/C_0402.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 0)) ) ) (module SMT:c_0402 (layer B.Cu) (tedit 58897D18) (tstamp 58818901) (at 65.27 72.52) (path /5881899D/594F320D) (attr smd) (fp_text reference C31 (at 1.02 0.9) (layer B.SilkS) (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_text value 4.7uf (at -0.5 0.7) (layer B.Fab) hide (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_line (start -1 -0.5) (end -1 0.5) (layer B.SilkS) (width 0.05)) (fp_line (start 1 -0.5) (end -1 -0.5) (layer B.SilkS) (width 0.05)) (fp_line (start 1 0.5) (end 1 -0.5) (layer B.SilkS) (width 0.05)) (fp_line (start -1 0.5) (end 1 0.5) (layer B.SilkS) (width 0.05)) (pad 1 smd rect (at -0.5 0) (size 0.6 0.7) (layers B.Cu B.Paste B.Mask) (net 31 VCC_BANK14_B)) (pad 2 smd rect (at 0.5 0) (size 0.6 0.7) (layers B.Cu B.Paste B.Mask) (net 1 GND)) (model Capacitors_SMD.3dshapes/C_0402.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 0)) ) ) (module SMT:c_0402 (layer B.Cu) (tedit 58897D18) (tstamp 58818911) (at 72.41 74.11 180) (path /5881899D/594F31F7) (attr smd) (fp_text reference C32 (at -0.01 -0.92 180) (layer B.SilkS) (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_text value 4.7uf (at -0.5 0.7 180) (layer B.Fab) hide (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_line (start -1 -0.5) (end -1 0.5) (layer B.SilkS) (width 0.05)) (fp_line (start 1 -0.5) (end -1 -0.5) (layer B.SilkS) (width 0.05)) (fp_line (start 1 0.5) (end 1 -0.5) (layer B.SilkS) (width 0.05)) (fp_line (start -1 0.5) (end 1 0.5) (layer B.SilkS) (width 0.05)) (pad 1 smd rect (at -0.5 0 180) (size 0.6 0.7) (layers B.Cu B.Paste B.Mask) (net 31 VCC_BANK14_B)) (pad 2 smd rect (at 0.5 0 180) (size 0.6 0.7) (layers B.Cu B.Paste B.Mask) (net 1 GND)) (model Capacitors_SMD.3dshapes/C_0402.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 0)) ) ) (module SMT:c_0402 (layer B.Cu) (tedit 58897D18) (tstamp 58818941) (at 64.41 74.05 180) (path /5881899D/586CAF5C) (attr smd) (fp_text reference C34 (at -0.31 -0.94 180) (layer B.SilkS) (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_text value 4.7uf (at -0.5 0.7 180) (layer B.Fab) hide (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_line (start -1 -0.5) (end -1 0.5) (layer B.SilkS) (width 0.05)) (fp_line (start 1 -0.5) (end -1 -0.5) (layer B.SilkS) (width 0.05)) (fp_line (start 1 0.5) (end 1 -0.5) (layer B.SilkS) (width 0.05)) (fp_line (start -1 0.5) (end 1 0.5) (layer B.SilkS) (width 0.05)) (pad 1 smd rect (at -0.5 0 180) (size 0.6 0.7) (layers B.Cu B.Paste B.Mask) (net 31 VCC_BANK14_B)) (pad 2 smd rect (at 0.5 0 180) (size 0.6 0.7) (layers B.Cu B.Paste B.Mask) (net 1 GND)) (model Capacitors_SMD.3dshapes/C_0402.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 0)) ) ) (module SMT:c_0402 (layer B.Cu) (tedit 58897D18) (tstamp 58818951) (at 73.22 72.53) (path /5881899D/586B4E67) (attr smd) (fp_text reference C35 (at 1.76 0.18) (layer B.SilkS) (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_text value 4.7uf (at -0.5 0.7) (layer B.Fab) hide (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_line (start -1 -0.5) (end -1 0.5) (layer B.SilkS) (width 0.05)) (fp_line (start 1 -0.5) (end -1 -0.5) (layer B.SilkS) (width 0.05)) (fp_line (start 1 0.5) (end 1 -0.5) (layer B.SilkS) (width 0.05)) (fp_line (start -1 0.5) (end 1 0.5) (layer B.SilkS) (width 0.05)) (pad 1 smd rect (at -0.5 0) (size 0.6 0.7) (layers B.Cu B.Paste B.Mask) (net 31 VCC_BANK14_B)) (pad 2 smd rect (at 0.5 0) (size 0.6 0.7) (layers B.Cu B.Paste B.Mask) (net 1 GND)) (model Capacitors_SMD.3dshapes/C_0402.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 0)) ) ) (module SMT:c_0402 (layer B.Cu) (tedit 58897D18) (tstamp 58818961) (at 64.54 66.12 180) (path /5881899D/586B56D4) (attr smd) (fp_text reference C36 (at 0.34 -0.9 180) (layer B.SilkS) (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_text value 4.7uf (at -0.5 0.7 180) (layer B.Fab) hide (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_line (start -1 -0.5) (end -1 0.5) (layer B.SilkS) (width 0.05)) (fp_line (start 1 -0.5) (end -1 -0.5) (layer B.SilkS) (width 0.05)) (fp_line (start 1 0.5) (end 1 -0.5) (layer B.SilkS) (width 0.05)) (fp_line (start -1 0.5) (end 1 0.5) (layer B.SilkS) (width 0.05)) (pad 1 smd rect (at -0.5 0 180) (size 0.6 0.7) (layers B.Cu B.Paste B.Mask) (net 31 VCC_BANK14_B)) (pad 2 smd rect (at 0.5 0 180) (size 0.6 0.7) (layers B.Cu B.Paste B.Mask) (net 1 GND)) (model Capacitors_SMD.3dshapes/C_0402.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 0)) ) ) (module SMT:c_0402 (layer B.Cu) (tedit 58897D18) (tstamp 58818AA1) (at 55.88 59.25 270) (path /594F323B/5861CFEC) (attr smd) (fp_text reference C52 (at 1.84 -0.08 270) (layer B.SilkS) (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_text value 10uf (at -0.5 0.7 270) (layer B.Fab) hide (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_line (start -1 -0.5) (end -1 0.5) (layer B.SilkS) (width 0.05)) (fp_line (start 1 -0.5) (end -1 -0.5) (layer B.SilkS) (width 0.05)) (fp_line (start 1 0.5) (end 1 -0.5) (layer B.SilkS) (width 0.05)) (fp_line (start -1 0.5) (end 1 0.5) (layer B.SilkS) (width 0.05)) (pad 1 smd rect (at -0.5 0 270) (size 0.6 0.7) (layers B.Cu B.Paste B.Mask) (net 31 VCC_BANK14_B)) (pad 2 smd rect (at 0.5 0 270) (size 0.6 0.7) (layers B.Cu B.Paste B.Mask) (net 1 GND)) (model Capacitors_SMD.3dshapes/C_0402.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 0)) ) ) (module SMT:c_0402 (layer B.Cu) (tedit 58897D18) (tstamp 58818AF1) (at 55.97 63.98 90) (path /594F323B/594F31DC) (attr smd) (fp_text reference C58 (at -1.87 0.05 90) (layer B.SilkS) (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_text value 10uf (at -0.5 0.7 90) (layer B.Fab) hide (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_line (start -1 -0.5) (end -1 0.5) (layer B.SilkS) (width 0.05)) (fp_line (start 1 -0.5) (end -1 -0.5) (layer B.SilkS) (width 0.05)) (fp_line (start 1 0.5) (end 1 -0.5) (layer B.SilkS) (width 0.05)) (fp_line (start -1 0.5) (end 1 0.5) (layer B.SilkS) (width 0.05)) (pad 1 smd rect (at -0.5 0 90) (size 0.6 0.7) (layers B.Cu B.Paste B.Mask) (net 31 VCC_BANK14_B)) (pad 2 smd rect (at 0.5 0 90) (size 0.6 0.7) (layers B.Cu B.Paste B.Mask) (net 1 GND)) (model Capacitors_SMD.3dshapes/C_0402.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 0)) ) ) (module SMT:c_0402 (layer B.Cu) (tedit 58897D18) (tstamp 58818B31) (at 66.07 59.59 270) (path /594F323B/586DE571) (attr smd) (fp_text reference C60 (at -1.38 0.09 360) (layer B.SilkS) (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_text value 10uf (at -0.5 0.7 270) (layer B.Fab) hide (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_line (start -1 -0.5) (end -1 0.5) (layer B.SilkS) (width 0.05)) (fp_line (start 1 -0.5) (end -1 -0.5) (layer B.SilkS) (width 0.05)) (fp_line (start 1 0.5) (end 1 -0.5) (layer B.SilkS) (width 0.05)) (fp_line (start -1 0.5) (end 1 0.5) (layer B.SilkS) (width 0.05)) (pad 1 smd rect (at -0.5 0 270) (size 0.6 0.7) (layers B.Cu B.Paste B.Mask) (net 12 P1V0_MGTAVCC_B)) (pad 2 smd rect (at 0.5 0 270) (size 0.6 0.7) (layers B.Cu B.Paste B.Mask) (net 1 GND)) (model Capacitors_SMD.3dshapes/C_0402.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 0)) ) ) (module SMT:c_0402 (layer B.Cu) (tedit 58897D18) (tstamp 58818B41) (at 69.57 60.12 180) (path /594F323B/586DE77B) (attr smd) (fp_text reference C61 (at 0.01 -0.91 180) (layer B.SilkS) (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_text value 10uf (at -0.5 0.7 180) (layer B.Fab) hide (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_line (start -1 -0.5) (end -1 0.5) (layer B.SilkS) (width 0.05)) (fp_line (start 1 -0.5) (end -1 -0.5) (layer B.SilkS) (width 0.05)) (fp_line (start 1 0.5) (end 1 -0.5) (layer B.SilkS) (width 0.05)) (fp_line (start -1 0.5) (end 1 0.5) (layer B.SilkS) (width 0.05)) (pad 1 smd rect (at -0.5 0 180) (size 0.6 0.7) (layers B.Cu B.Paste B.Mask) (net 15 P1V2_MGTAVTT_B)) (pad 2 smd rect (at 0.5 0 180) (size 0.6 0.7) (layers B.Cu B.Paste B.Mask) (net 1 GND)) (model Capacitors_SMD.3dshapes/C_0402.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 0)) ) ) (module SMT:c_0402 (layer B.Cu) (tedit 58897D18) (tstamp 58894503) (at 73.62 65.06 270) (path /5881899D/594F325C) (attr smd) (fp_text reference C1 (at 1.5 -0.01 270) (layer B.SilkS) (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_text value 4.7uf (at -0.5 0.7 270) (layer B.Fab) hide (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_line (start -1 -0.5) (end -1 0.5) (layer B.SilkS) (width 0.05)) (fp_line (start 1 -0.5) (end -1 -0.5) (layer B.SilkS) (width 0.05)) (fp_line (start 1 0.5) (end 1 -0.5) (layer B.SilkS) (width 0.05)) (fp_line (start -1 0.5) (end 1 0.5) (layer B.SilkS) (width 0.05)) (pad 1 smd rect (at -0.5 0 270) (size 0.6 0.7) (layers B.Cu B.Paste B.Mask) (net 12 P1V0_MGTAVCC_B)) (pad 2 smd rect (at 0.5 0 270) (size 0.6 0.7) (layers B.Cu B.Paste B.Mask) (net 1 GND)) (model Capacitors_SMD.3dshapes/C_0402.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 0)) ) ) (module SMT:r_0402 (layer B.Cu) (tedit 58897D18) (tstamp 58818D6E) (at 60.87 63.3 90) (path /594F323B/594F3227) (attr smd) (fp_text reference L1 (at 0.49 0.9 270) (layer B.SilkS) (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_text value 330 (at -0.5 0.7 90) (layer B.Fab) hide (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_line (start -1 -0.5) (end -1 0.5) (layer B.SilkS) (width 0.05)) (fp_line (start 1 -0.5) (end -1 -0.5) (layer B.SilkS) (width 0.05)) (fp_line (start 1 0.5) (end 1 -0.5) (layer B.SilkS) (width 0.05)) (fp_line (start -1 0.5) (end 1 0.5) (layer B.SilkS) (width 0.05)) (pad 1 smd rect (at -0.5 0 90) (size 0.6 0.7) (layers B.Cu B.Paste B.Mask) (net 14 P1V8_FPGA_VCCAUX_B)) (pad 2 smd rect (at 0.5 0 90) (size 0.6 0.7) (layers B.Cu B.Paste B.Mask) (net 2 "Net-(C56-Pad1)")) (model Resistors_SMD.3dshapes/R_0402.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 0)) ) ) (module SMT:r_0201_least (layer B.Cu) (tedit 58881732) (tstamp 58818E8D) (at 76.24 65.12 45) (path /594F3239/586D129E) (attr smd) (fp_text reference R1 (at -0.141421 -0.721249 45) (layer B.SilkS) (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_text value 100 (at -0.1 -0.5 45) (layer B.Fab) (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_line (start -0.6 -0.3) (end -0.6 0.3) (layer B.SilkS) (width 0.05)) (fp_line (start 0.6 -0.3) (end -0.6 -0.3) (layer B.SilkS) (width 0.05)) (fp_line (start 0.6 0.3) (end 0.6 -0.3) (layer B.SilkS) (width 0.05)) (fp_line (start -0.6 0.3) (end 0.6 0.3) (layer B.SilkS) (width 0.05)) (pad 1 smd rect (at -0.28 0 45) (size 0.36 0.32) (layers B.Cu B.Paste B.Mask) (net 58 "Net-(R1-Pad1)")) (pad 2 smd rect (at 0.28 0 45) (size 0.36 0.32) (layers B.Cu B.Paste B.Mask) (net 15 P1V2_MGTAVTT_B)) (model Resistors_SMD.3dshapes/R_0201.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 0)) ) ) (module fp_archive:TPS82084SILR (layer B.Cu) (tedit 58EA71E5) (tstamp 5881913F) (at 58.09 59.89) (path /594F323B/5861CFAE) (fp_text reference U3 (at -1.15 -2.15) (layer B.SilkS) (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_text value TPS82085SIL (at 0.2 2.4) (layer B.SilkS) hide (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_text user "Copyright 2016 Accelerated Designs. All rights reserved." (at 0 0) (layer Cmts.User) hide (effects (font (size 0.508 0.508) (thickness 0.127))) ) (fp_line (start -1.549999 1.45) (end -1.549999 1.649999) (layer B.SilkS) (width 0.1524)) (fp_line (start -1.549999 1.649999) (end -1.000001 1.649999) (layer B.SilkS) (width 0.1524)) (fp_line (start 1.549999 1.45) (end 1.549999 1.649999) (layer B.SilkS) (width 0.1524)) (fp_line (start 1.35 1.649999) (end 1.549999 1.649999) (layer B.SilkS) (width 0.1524)) (fp_line (start 1.35 -1.649999) (end 1.549999 -1.649999) (layer B.SilkS) (width 0.1524)) (fp_line (start 1.549999 -1.649999) (end 1.549999 -1.45) (layer B.SilkS) (width 0.1524)) (fp_line (start -1.549999 -1.649999) (end -1.35 -1.649999) (layer B.SilkS) (width 0.1524)) (fp_line (start -1.549999 -1.649999) (end -1.549999 -1.45) (layer B.SilkS) (width 0.1524)) (fp_line (start -1.45 -1.549999) (end 1.45 -1.549999) (layer Dwgs.User) (width 0.1524)) (fp_line (start -1.45 1.549999) (end 1.45 1.549999) (layer Dwgs.User) (width 0.1524)) (fp_line (start 1.45 -1.549999) (end 1.45 1.549999) (layer Dwgs.User) (width 0.1524)) (fp_line (start -1.45 -1.549999) (end -1.45 1.549999) (layer Dwgs.User) (width 0.1524)) (fp_circle (center -0.950001 -0.974999) (end -0.748444 -0.974999) (layer Dwgs.User) (width 0.1524)) (pad 1 smd rect (at -1.1 0.974999) (size 0.599999 0.499999) (layers B.Cu) (net 31 VCC_BANK14_B)) (pad 1 smd rect (at -1.1 0.974999) (size 0.499999 0.399999) (layers B.Mask) (net 31 VCC_BANK14_B)) (pad 1 smd rect (at -1.1 0.974999) (size 0.499999 0.399999) (layers B.Paste) (net 31 VCC_BANK14_B)) (pad 2 smd rect (at -1.1 0.325001) (size 0.599999 0.499999) (layers B.Cu) (net 8 "Net-(U3-Pad2)")) (pad 2 smd rect (at -1.1 0.325001) (size 0.499999 0.399999) (layers B.Mask) (net 8 "Net-(U3-Pad2)")) (pad 2 smd rect (at -1.1 0.325001) (size 0.499999 0.399999) (layers B.Paste) (net 8 "Net-(U3-Pad2)")) (pad 3 smd rect (at -1.1 -0.325001) (size 0.599999 0.499999) (layers B.Cu) (net 31 VCC_BANK14_B)) (pad 3 smd rect (at -1.1 -0.325001) (size 0.499999 0.399999) (layers B.Mask) (net 31 VCC_BANK14_B)) (pad 3 smd rect (at -1.1 -0.325001) (size 0.499999 0.399999) (layers B.Paste) (net 31 VCC_BANK14_B)) (pad 4 smd rect (at -1.1 -0.974999) (size 0.599999 0.499999) (layers B.Cu) (net 31 VCC_BANK14_B)) (pad 4 smd rect (at -1.1 -0.974999) (size 0.499999 0.399999) (layers B.Mask) (net 31 VCC_BANK14_B)) (pad 4 smd rect (at -1.1 -0.974999) (size 0.499999 0.399999) (layers B.Paste) (net 31 VCC_BANK14_B)) (pad 5 smd rect (at 1.1 -0.974999) (size 0.599999 0.499999) (layers B.Cu) (net 1 GND)) (pad 5 smd rect (at 1.1 -0.974999) (size 0.499999 0.399999) (layers B.Mask) (net 1 GND)) (pad 5 smd rect (at 1.1 -0.974999) (size 0.499999 0.399999) (layers B.Paste) (net 1 GND)) (pad 6 smd rect (at 1.1 -0.325001) (size 0.599999 0.499999) (layers B.Cu) (net 1 GND)) (pad 6 smd rect (at 1.1 -0.325001) (size 0.499999 0.399999) (layers B.Mask) (net 1 GND)) (pad 6 smd rect (at 1.1 -0.325001) (size 0.499999 0.399999) (layers B.Paste) (net 1 GND)) (pad 7 smd rect (at 1.1 0.325001) (size 0.599999 0.499999) (layers B.Cu) (net 59 "Net-(R2-Pad2)")) (pad 7 smd rect (at 1.1 0.325001) (size 0.499999 0.399999) (layers B.Mask) (net 59 "Net-(R2-Pad2)")) (pad 7 smd rect (at 1.1 0.325001) (size 0.499999 0.399999) (layers B.Paste) (net 59 "Net-(R2-Pad2)")) (pad 8 smd rect (at 1.1 0.974999) (size 0.599999 0.499999) (layers B.Cu) (net 2 "Net-(C56-Pad1)")) (pad 8 smd rect (at 1.1 0.974999) (size 0.499999 0.399999) (layers B.Mask) (net 2 "Net-(C56-Pad1)")) (pad 8 smd rect (at 1.1 0.974999) (size 0.499999 0.399999) (layers B.Paste) (net 2 "Net-(C56-Pad1)")) (pad 9 smd rect (at 0 0) (size 1.2 2.000001) (layers B.Cu) (net 1 GND)) (pad 9 smd rect (at 0 0) (size 1.1 1.900001) (layers B.Paste B.Mask) (net 1 GND)) (pad 9 smd rect (at 0 0) (size 0.000003 0.800003) (layers B.Paste) (net 1 GND)) ) (module fp_archive:TPS82084SILR (layer B.Cu) (tedit 58EA71E5) (tstamp 5881919C) (at 58.12 65.66) (path /594F323B/5861D9F9) (fp_text reference U6 (at -2.22 1.52) (layer B.SilkS) (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_text value TPS82085SIL (at 0.2 2.4) (layer B.SilkS) hide (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_text user "Copyright 2016 Accelerated Designs. All rights reserved." (at 0 0) (layer Cmts.User) hide (effects (font (size 0.508 0.508) (thickness 0.127))) ) (fp_line (start -1.549999 1.45) (end -1.549999 1.649999) (layer B.SilkS) (width 0.1524)) (fp_line (start -1.549999 1.649999) (end -1.000001 1.649999) (layer B.SilkS) (width 0.1524)) (fp_line (start 1.549999 1.45) (end 1.549999 1.649999) (layer B.SilkS) (width 0.1524)) (fp_line (start 1.35 1.649999) (end 1.549999 1.649999) (layer B.SilkS) (width 0.1524)) (fp_line (start 1.35 -1.649999) (end 1.549999 -1.649999) (layer B.SilkS) (width 0.1524)) (fp_line (start 1.549999 -1.649999) (end 1.549999 -1.45) (layer B.SilkS) (width 0.1524)) (fp_line (start -1.549999 -1.649999) (end -1.35 -1.649999) (layer B.SilkS) (width 0.1524)) (fp_line (start -1.549999 -1.649999) (end -1.549999 -1.45) (layer B.SilkS) (width 0.1524)) (fp_line (start -1.45 -1.549999) (end 1.45 -1.549999) (layer Dwgs.User) (width 0.1524)) (fp_line (start -1.45 1.549999) (end 1.45 1.549999) (layer Dwgs.User) (width 0.1524)) (fp_line (start 1.45 -1.549999) (end 1.45 1.549999) (layer Dwgs.User) (width 0.1524)) (fp_line (start -1.45 -1.549999) (end -1.45 1.549999) (layer Dwgs.User) (width 0.1524)) (fp_circle (center -0.950001 -0.974999) (end -0.748444 -0.974999) (layer Dwgs.User) (width 0.1524)) (pad 1 smd rect (at -1.1 0.974999) (size 0.599999 0.499999) (layers B.Cu) (net 31 VCC_BANK14_B)) (pad 1 smd rect (at -1.1 0.974999) (size 0.499999 0.399999) (layers B.Mask) (net 31 VCC_BANK14_B)) (pad 1 smd rect (at -1.1 0.974999) (size 0.499999 0.399999) (layers B.Paste) (net 31 VCC_BANK14_B)) (pad 2 smd rect (at -1.1 0.325001) (size 0.599999 0.499999) (layers B.Cu) (net 9 "Net-(U6-Pad2)")) (pad 2 smd rect (at -1.1 0.325001) (size 0.499999 0.399999) (layers B.Mask) (net 9 "Net-(U6-Pad2)")) (pad 2 smd rect (at -1.1 0.325001) (size 0.499999 0.399999) (layers B.Paste) (net 9 "Net-(U6-Pad2)")) (pad 3 smd rect (at -1.1 -0.325001) (size 0.599999 0.499999) (layers B.Cu) (net 31 VCC_BANK14_B)) (pad 3 smd rect (at -1.1 -0.325001) (size 0.499999 0.399999) (layers B.Mask) (net 31 VCC_BANK14_B)) (pad 3 smd rect (at -1.1 -0.325001) (size 0.499999 0.399999) (layers B.Paste) (net 31 VCC_BANK14_B)) (pad 4 smd rect (at -1.1 -0.974999) (size 0.599999 0.499999) (layers B.Cu) (net 31 VCC_BANK14_B)) (pad 4 smd rect (at -1.1 -0.974999) (size 0.499999 0.399999) (layers B.Mask) (net 31 VCC_BANK14_B)) (pad 4 smd rect (at -1.1 -0.974999) (size 0.499999 0.399999) (layers B.Paste) (net 31 VCC_BANK14_B)) (pad 5 smd rect (at 1.1 -0.974999) (size 0.599999 0.499999) (layers B.Cu) (net 1 GND)) (pad 5 smd rect (at 1.1 -0.974999) (size 0.499999 0.399999) (layers B.Mask) (net 1 GND)) (pad 5 smd rect (at 1.1 -0.974999) (size 0.499999 0.399999) (layers B.Paste) (net 1 GND)) (pad 6 smd rect (at 1.1 -0.325001) (size 0.599999 0.499999) (layers B.Cu) (net 1 GND)) (pad 6 smd rect (at 1.1 -0.325001) (size 0.499999 0.399999) (layers B.Mask) (net 1 GND)) (pad 6 smd rect (at 1.1 -0.325001) (size 0.499999 0.399999) (layers B.Paste) (net 1 GND)) (pad 7 smd rect (at 1.1 0.325001) (size 0.599999 0.499999) (layers B.Cu) (net 60 "Net-(R4-Pad2)")) (pad 7 smd rect (at 1.1 0.325001) (size 0.499999 0.399999) (layers B.Mask) (net 60 "Net-(R4-Pad2)")) (pad 7 smd rect (at 1.1 0.325001) (size 0.499999 0.399999) (layers B.Paste) (net 60 "Net-(R4-Pad2)")) (pad 8 smd rect (at 1.1 0.974999) (size 0.599999 0.499999) (layers B.Cu) (net 13 P1V0_VCC_FPGA_B)) (pad 8 smd rect (at 1.1 0.974999) (size 0.499999 0.399999) (layers B.Mask) (net 13 P1V0_VCC_FPGA_B)) (pad 8 smd rect (at 1.1 0.974999) (size 0.499999 0.399999) (layers B.Paste) (net 13 P1V0_VCC_FPGA_B)) (pad 9 smd rect (at 0 0) (size 1.2 2.000001) (layers B.Cu) (net 1 GND)) (pad 9 smd rect (at 0 0) (size 1.1 1.900001) (layers B.Paste B.Mask) (net 1 GND)) (pad 9 smd rect (at 0 0) (size 0.000003 0.800003) (layers B.Paste) (net 1 GND)) ) (module Capacitors_SMD:C_0805 (layer F.Cu) (tedit 58AA8463) (tstamp 5889489E) (at 60.33 66.22 90) (descr "Capacitor SMD 0805, reflow soldering, AVX (see smccp.pdf)") (tags "capacitor 0805") (path /594F323B/588940AD) (attr smd) (fp_text reference C66 (at -1.124 -1.704 180) (layer F.SilkS) (effects (font (size 0.508 0.508) (thickness 0.127))) ) (fp_text value 100uf (at 0 1.75 90) (layer F.Fab) (effects (font (size 0.508 0.508) (thickness 0.127))) ) (fp_line (start -1.7 0.85) (end -0.65 0.85) (layer F.SilkS) (width 0.05)) (fp_line (start -1.7 0.15) (end -1.7 0.85) (layer F.SilkS) (width 0.05)) (fp_line (start -1.95 0) (end -1.7 0.15) (layer F.SilkS) (width 0.05)) (fp_line (start -1.7 -0.2) (end -1.95 0) (layer F.SilkS) (width 0.05)) (fp_line (start -1.7 -0.85) (end -1.7 -0.2) (layer F.SilkS) (width 0.05)) (fp_line (start -0.65 -0.85) (end -1.7 -0.85) (layer F.SilkS) (width 0.05)) (fp_line (start 1.7 -0.85) (end 0.65 -0.85) (layer F.SilkS) (width 0.05)) (fp_line (start 1.7 0.85) (end 1.7 -0.85) (layer F.SilkS) (width 0.05)) (fp_line (start 0.65 0.85) (end 1.7 0.85) (layer F.SilkS) (width 0.05)) (fp_text user %R (at 0 -1.5 90) (layer F.Fab) (effects (font (size 0.508 0.508) (thickness 0.127))) ) (fp_line (start -1 0.62) (end -1 -0.62) (layer F.Fab) (width 0.1)) (fp_line (start 1 0.62) (end -1 0.62) (layer F.Fab) (width 0.1)) (fp_line (start 1 -0.62) (end 1 0.62) (layer F.Fab) (width 0.1)) (fp_line (start -1 -0.62) (end 1 -0.62) (layer F.Fab) (width 0.1)) (fp_line (start 0.5 -0.85) (end -0.5 -0.85) (layer F.SilkS) (width 0.12)) (fp_line (start -0.5 0.85) (end 0.5 0.85) (layer F.SilkS) (width 0.12)) (fp_line (start -1.75 -0.88) (end 1.75 -0.88) (layer F.CrtYd) (width 0.05)) (fp_line (start -1.75 -0.88) (end -1.75 0.87) (layer F.CrtYd) (width 0.05)) (fp_line (start 1.75 0.87) (end 1.75 -0.88) (layer F.CrtYd) (width 0.05)) (fp_line (start 1.75 0.87) (end -1.75 0.87) (layer F.CrtYd) (width 0.05)) (pad 1 smd rect (at -1 0 90) (size 1 1.25) (layers F.Cu F.Paste F.Mask) (net 13 P1V0_VCC_FPGA_B)) (pad 2 smd rect (at 1 0 90) (size 1 1.25) (layers F.Cu F.Paste F.Mask) (net 1 GND)) (model Capacitors_SMD.3dshapes/C_0805.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 0)) ) ) (module Capacitors_SMD:C_0805 (layer F.Cu) (tedit 58AA8463) (tstamp 5889488E) (at 56.26 67.17 90) (descr "Capacitor SMD 0805, reflow soldering, AVX (see smccp.pdf)") (tags "capacitor 0805") (path /594F323B/588940A6) (attr smd) (fp_text reference C65 (at 2.08 -0.22 360) (layer F.SilkS) (effects (font (size 0.508 0.508) (thickness 0.127))) ) (fp_text value 100uf (at 0 1.75 90) (layer F.Fab) (effects (font (size 0.508 0.508) (thickness 0.127))) ) (fp_line (start -1.7 0.85) (end -0.65 0.85) (layer F.SilkS) (width 0.05)) (fp_line (start -1.7 0.15) (end -1.7 0.85) (layer F.SilkS) (width 0.05)) (fp_line (start -1.95 0) (end -1.7 0.15) (layer F.SilkS) (width 0.05)) (fp_line (start -1.7 -0.2) (end -1.95 0) (layer F.SilkS) (width 0.05)) (fp_line (start -1.7 -0.85) (end -1.7 -0.2) (layer F.SilkS) (width 0.05)) (fp_line (start -0.65 -0.85) (end -1.7 -0.85) (layer F.SilkS) (width 0.05)) (fp_line (start 1.7 -0.85) (end 0.65 -0.85) (layer F.SilkS) (width 0.05)) (fp_line (start 1.7 0.85) (end 1.7 -0.85) (layer F.SilkS) (width 0.05)) (fp_line (start 0.65 0.85) (end 1.7 0.85) (layer F.SilkS) (width 0.05)) (fp_text user %R (at 0 -1.5 90) (layer F.Fab) (effects (font (size 0.508 0.508) (thickness 0.127))) ) (fp_line (start -1 0.62) (end -1 -0.62) (layer F.Fab) (width 0.1)) (fp_line (start 1 0.62) (end -1 0.62) (layer F.Fab) (width 0.1)) (fp_line (start 1 -0.62) (end 1 0.62) (layer F.Fab) (width 0.1)) (fp_line (start -1 -0.62) (end 1 -0.62) (layer F.Fab) (width 0.1)) (fp_line (start 0.5 -0.85) (end -0.5 -0.85) (layer F.SilkS) (width 0.12)) (fp_line (start -0.5 0.85) (end 0.5 0.85) (layer F.SilkS) (width 0.12)) (fp_line (start -1.75 -0.88) (end 1.75 -0.88) (layer F.CrtYd) (width 0.05)) (fp_line (start -1.75 -0.88) (end -1.75 0.87) (layer F.CrtYd) (width 0.05)) (fp_line (start 1.75 0.87) (end 1.75 -0.88) (layer F.CrtYd) (width 0.05)) (fp_line (start 1.75 0.87) (end -1.75 0.87) (layer F.CrtYd) (width 0.05)) (pad 1 smd rect (at -1 0 90) (size 1 1.25) (layers F.Cu F.Paste F.Mask) (net 13 P1V0_VCC_FPGA_B)) (pad 2 smd rect (at 1 0 90) (size 1 1.25) (layers F.Cu F.Paste F.Mask) (net 1 GND)) (model Capacitors_SMD.3dshapes/C_0805.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 0)) ) ) (module Capacitors_SMD:C_0805 (layer B.Cu) (tedit 58AA8463) (tstamp 5889487E) (at 75.04 60.24 90) (descr "Capacitor SMD 0805, reflow soldering, AVX (see smccp.pdf)") (tags "capacitor 0805") (path /594F323B/58894415) (attr smd) (fp_text reference C63 (at 0.1 1.29 90) (layer B.SilkS) (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_text value 100uf (at 0 -1.75 90) (layer B.Fab) (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_line (start -1.7 -0.85) (end -0.65 -0.85) (layer B.SilkS) (width 0.05)) (fp_line (start -1.7 -0.15) (end -1.7 -0.85) (layer B.SilkS) (width 0.05)) (fp_line (start -1.95 0) (end -1.7 -0.15) (layer B.SilkS) (width 0.05)) (fp_line (start -1.7 0.2) (end -1.95 0) (layer B.SilkS) (width 0.05)) (fp_line (start -1.7 0.85) (end -1.7 0.2) (layer B.SilkS) (width 0.05)) (fp_line (start -0.65 0.85) (end -1.7 0.85) (layer B.SilkS) (width 0.05)) (fp_line (start 1.7 0.85) (end 0.65 0.85) (layer B.SilkS) (width 0.05)) (fp_line (start 1.7 -0.85) (end 1.7 0.85) (layer B.SilkS) (width 0.05)) (fp_line (start 0.65 -0.85) (end 1.7 -0.85) (layer B.SilkS) (width 0.05)) (fp_text user %R (at 0 1.5 90) (layer B.Fab) (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_line (start -1 -0.62) (end -1 0.62) (layer B.Fab) (width 0.1)) (fp_line (start 1 -0.62) (end -1 -0.62) (layer B.Fab) (width 0.1)) (fp_line (start 1 0.62) (end 1 -0.62) (layer B.Fab) (width 0.1)) (fp_line (start -1 0.62) (end 1 0.62) (layer B.Fab) (width 0.1)) (fp_line (start 0.5 0.85) (end -0.5 0.85) (layer B.SilkS) (width 0.12)) (fp_line (start -0.5 -0.85) (end 0.5 -0.85) (layer B.SilkS) (width 0.12)) (fp_line (start -1.75 0.88) (end 1.75 0.88) (layer B.CrtYd) (width 0.05)) (fp_line (start -1.75 0.88) (end -1.75 -0.87) (layer B.CrtYd) (width 0.05)) (fp_line (start 1.75 -0.87) (end 1.75 0.88) (layer B.CrtYd) (width 0.05)) (fp_line (start 1.75 -0.87) (end -1.75 -0.87) (layer B.CrtYd) (width 0.05)) (pad 1 smd rect (at -1 0 90) (size 1 1.25) (layers B.Cu B.Paste B.Mask) (net 15 P1V2_MGTAVTT_B)) (pad 2 smd rect (at 1 0 90) (size 1 1.25) (layers B.Cu B.Paste B.Mask) (net 1 GND)) (model Capacitors_SMD.3dshapes/C_0805.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 0)) ) ) (module Capacitors_SMD:C_0805 (layer B.Cu) (tedit 58AA8463) (tstamp 5889486E) (at 67.58 59.45 90) (descr "Capacitor SMD 0805, reflow soldering, AVX (see smccp.pdf)") (tags "capacitor 0805") (path /594F323B/5889464E) (attr smd) (fp_text reference C62 (at 1.08 1.29 90) (layer B.SilkS) (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_text value 100uf (at 0 -1.75 90) (layer B.Fab) (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_line (start -1.7 -0.85) (end -0.65 -0.85) (layer B.SilkS) (width 0.05)) (fp_line (start -1.7 -0.15) (end -1.7 -0.85) (layer B.SilkS) (width 0.05)) (fp_line (start -1.95 0) (end -1.7 -0.15) (layer B.SilkS) (width 0.05)) (fp_line (start -1.7 0.2) (end -1.95 0) (layer B.SilkS) (width 0.05)) (fp_line (start -1.7 0.85) (end -1.7 0.2) (layer B.SilkS) (width 0.05)) (fp_line (start -0.65 0.85) (end -1.7 0.85) (layer B.SilkS) (width 0.05)) (fp_line (start 1.7 0.85) (end 0.65 0.85) (layer B.SilkS) (width 0.05)) (fp_line (start 1.7 -0.85) (end 1.7 0.85) (layer B.SilkS) (width 0.05)) (fp_line (start 0.65 -0.85) (end 1.7 -0.85) (layer B.SilkS) (width 0.05)) (fp_text user %R (at 0 1.5 90) (layer B.Fab) (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_line (start -1 -0.62) (end -1 0.62) (layer B.Fab) (width 0.1)) (fp_line (start 1 -0.62) (end -1 -0.62) (layer B.Fab) (width 0.1)) (fp_line (start 1 0.62) (end 1 -0.62) (layer B.Fab) (width 0.1)) (fp_line (start -1 0.62) (end 1 0.62) (layer B.Fab) (width 0.1)) (fp_line (start 0.5 0.85) (end -0.5 0.85) (layer B.SilkS) (width 0.12)) (fp_line (start -0.5 -0.85) (end 0.5 -0.85) (layer B.SilkS) (width 0.12)) (fp_line (start -1.75 0.88) (end 1.75 0.88) (layer B.CrtYd) (width 0.05)) (fp_line (start -1.75 0.88) (end -1.75 -0.87) (layer B.CrtYd) (width 0.05)) (fp_line (start 1.75 -0.87) (end 1.75 0.88) (layer B.CrtYd) (width 0.05)) (fp_line (start 1.75 -0.87) (end -1.75 -0.87) (layer B.CrtYd) (width 0.05)) (pad 1 smd rect (at -1 0 90) (size 1 1.25) (layers B.Cu B.Paste B.Mask) (net 12 P1V0_MGTAVCC_B)) (pad 2 smd rect (at 1 0 90) (size 1 1.25) (layers B.Cu B.Paste B.Mask) (net 1 GND)) (model Capacitors_SMD.3dshapes/C_0805.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 0)) ) ) (module Capacitors_SMD:C_0805 (layer F.Cu) (tedit 58AA8463) (tstamp 5889485E) (at 60.37 59.89 90) (descr "Capacitor SMD 0805, reflow soldering, AVX (see smccp.pdf)") (tags "capacitor 0805") (path /594F323B/58894A59) (attr smd) (fp_text reference C57 (at 1.57 -1.68 180) (layer F.SilkS) (effects (font (size 0.508 0.508) (thickness 0.127))) ) (fp_text value 100uf (at 0 1.75 90) (layer F.Fab) (effects (font (size 0.508 0.508) (thickness 0.127))) ) (fp_line (start -1.7 0.85) (end -0.65 0.85) (layer F.SilkS) (width 0.05)) (fp_line (start -1.7 0.15) (end -1.7 0.85) (layer F.SilkS) (width 0.05)) (fp_line (start -1.95 0) (end -1.7 0.15) (layer F.SilkS) (width 0.05)) (fp_line (start -1.7 -0.2) (end -1.95 0) (layer F.SilkS) (width 0.05)) (fp_line (start -1.7 -0.85) (end -1.7 -0.2) (layer F.SilkS) (width 0.05)) (fp_line (start -0.65 -0.85) (end -1.7 -0.85) (layer F.SilkS) (width 0.05)) (fp_line (start 1.7 -0.85) (end 0.65 -0.85) (layer F.SilkS) (width 0.05)) (fp_line (start 1.7 0.85) (end 1.7 -0.85) (layer F.SilkS) (width 0.05)) (fp_line (start 0.65 0.85) (end 1.7 0.85) (layer F.SilkS) (width 0.05)) (fp_text user %R (at 0 -1.5 90) (layer F.Fab) (effects (font (size 0.508 0.508) (thickness 0.127))) ) (fp_line (start -1 0.62) (end -1 -0.62) (layer F.Fab) (width 0.1)) (fp_line (start 1 0.62) (end -1 0.62) (layer F.Fab) (width 0.1)) (fp_line (start 1 -0.62) (end 1 0.62) (layer F.Fab) (width 0.1)) (fp_line (start -1 -0.62) (end 1 -0.62) (layer F.Fab) (width 0.1)) (fp_line (start 0.5 -0.85) (end -0.5 -0.85) (layer F.SilkS) (width 0.12)) (fp_line (start -0.5 0.85) (end 0.5 0.85) (layer F.SilkS) (width 0.12)) (fp_line (start -1.75 -0.88) (end 1.75 -0.88) (layer F.CrtYd) (width 0.05)) (fp_line (start -1.75 -0.88) (end -1.75 0.87) (layer F.CrtYd) (width 0.05)) (fp_line (start 1.75 0.87) (end 1.75 -0.88) (layer F.CrtYd) (width 0.05)) (fp_line (start 1.75 0.87) (end -1.75 0.87) (layer F.CrtYd) (width 0.05)) (pad 1 smd rect (at -1 0 90) (size 1 1.25) (layers F.Cu F.Paste F.Mask) (net 2 "Net-(C56-Pad1)")) (pad 2 smd rect (at 1 0 90) (size 1 1.25) (layers F.Cu F.Paste F.Mask) (net 1 GND)) (model Capacitors_SMD.3dshapes/C_0805.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 0)) ) ) (module Capacitors_SMD:C_0805 (layer B.Cu) (tedit 58AA8463) (tstamp 5889484E) (at 57.81 70.2 180) (descr "Capacitor SMD 0805, reflow soldering, AVX (see smccp.pdf)") (tags "capacitor 0805") (path /594F323B/594F324F) (attr smd) (fp_text reference C55 (at 0.79 1.25 180) (layer B.SilkS) (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_text value 100uf (at 0 -1.75 180) (layer B.Fab) (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_line (start -1.7 -0.85) (end -0.65 -0.85) (layer B.SilkS) (width 0.05)) (fp_line (start -1.7 -0.15) (end -1.7 -0.85) (layer B.SilkS) (width 0.05)) (fp_line (start -1.95 0) (end -1.7 -0.15) (layer B.SilkS) (width 0.05)) (fp_line (start -1.7 0.2) (end -1.95 0) (layer B.SilkS) (width 0.05)) (fp_line (start -1.7 0.85) (end -1.7 0.2) (layer B.SilkS) (width 0.05)) (fp_line (start -0.65 0.85) (end -1.7 0.85) (layer B.SilkS) (width 0.05)) (fp_line (start 1.7 0.85) (end 0.65 0.85) (layer B.SilkS) (width 0.05)) (fp_line (start 1.7 -0.85) (end 1.7 0.85) (layer B.SilkS) (width 0.05)) (fp_line (start 0.65 -0.85) (end 1.7 -0.85) (layer B.SilkS) (width 0.05)) (fp_text user %R (at 0 1.5 180) (layer B.Fab) (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_line (start -1 -0.62) (end -1 0.62) (layer B.Fab) (width 0.1)) (fp_line (start 1 -0.62) (end -1 -0.62) (layer B.Fab) (width 0.1)) (fp_line (start 1 0.62) (end 1 -0.62) (layer B.Fab) (width 0.1)) (fp_line (start -1 0.62) (end 1 0.62) (layer B.Fab) (width 0.1)) (fp_line (start 0.5 0.85) (end -0.5 0.85) (layer B.SilkS) (width 0.12)) (fp_line (start -0.5 -0.85) (end 0.5 -0.85) (layer B.SilkS) (width 0.12)) (fp_line (start -1.75 0.88) (end 1.75 0.88) (layer B.CrtYd) (width 0.05)) (fp_line (start -1.75 0.88) (end -1.75 -0.87) (layer B.CrtYd) (width 0.05)) (fp_line (start 1.75 -0.87) (end 1.75 0.88) (layer B.CrtYd) (width 0.05)) (fp_line (start 1.75 -0.87) (end -1.75 -0.87) (layer B.CrtYd) (width 0.05)) (pad 1 smd rect (at -1 0 180) (size 1 1.25) (layers B.Cu B.Paste B.Mask) (net 31 VCC_BANK14_B)) (pad 2 smd rect (at 1 0 180) (size 1 1.25) (layers B.Cu B.Paste B.Mask) (net 1 GND)) (model Capacitors_SMD.3dshapes/C_0805.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 0)) ) ) (module Capacitors_SMD:C_0805 (layer B.Cu) (tedit 58AA8463) (tstamp 5889483E) (at 76.11 81.17 270) (descr "Capacitor SMD 0805, reflow soldering, AVX (see smccp.pdf)") (tags "capacitor 0805") (path /594F323B/594F324E) (attr smd) (fp_text reference C54 (at 2.1 -0.01 360) (layer B.SilkS) (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_text value 100uf (at 0 -1.75 270) (layer B.Fab) (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_line (start -1.7 -0.85) (end -0.65 -0.85) (layer B.SilkS) (width 0.05)) (fp_line (start -1.7 -0.15) (end -1.7 -0.85) (layer B.SilkS) (width 0.05)) (fp_line (start -1.95 0) (end -1.7 -0.15) (layer B.SilkS) (width 0.05)) (fp_line (start -1.7 0.2) (end -1.95 0) (layer B.SilkS) (width 0.05)) (fp_line (start -1.7 0.85) (end -1.7 0.2) (layer B.SilkS) (width 0.05)) (fp_line (start -0.65 0.85) (end -1.7 0.85) (layer B.SilkS) (width 0.05)) (fp_line (start 1.7 0.85) (end 0.65 0.85) (layer B.SilkS) (width 0.05)) (fp_line (start 1.7 -0.85) (end 1.7 0.85) (layer B.SilkS) (width 0.05)) (fp_line (start 0.65 -0.85) (end 1.7 -0.85) (layer B.SilkS) (width 0.05)) (fp_text user %R (at 0 1.5 270) (layer B.Fab) (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_line (start -1 -0.62) (end -1 0.62) (layer B.Fab) (width 0.1)) (fp_line (start 1 -0.62) (end -1 -0.62) (layer B.Fab) (width 0.1)) (fp_line (start 1 0.62) (end 1 -0.62) (layer B.Fab) (width 0.1)) (fp_line (start -1 0.62) (end 1 0.62) (layer B.Fab) (width 0.1)) (fp_line (start 0.5 0.85) (end -0.5 0.85) (layer B.SilkS) (width 0.12)) (fp_line (start -0.5 -0.85) (end 0.5 -0.85) (layer B.SilkS) (width 0.12)) (fp_line (start -1.75 0.88) (end 1.75 0.88) (layer B.CrtYd) (width 0.05)) (fp_line (start -1.75 0.88) (end -1.75 -0.87) (layer B.CrtYd) (width 0.05)) (fp_line (start 1.75 -0.87) (end 1.75 0.88) (layer B.CrtYd) (width 0.05)) (fp_line (start 1.75 -0.87) (end -1.75 -0.87) (layer B.CrtYd) (width 0.05)) (pad 1 smd rect (at -1 0 270) (size 1 1.25) (layers B.Cu B.Paste B.Mask) (net 31 VCC_BANK14_B)) (pad 2 smd rect (at 1 0 270) (size 1 1.25) (layers B.Cu B.Paste B.Mask) (net 1 GND)) (model Capacitors_SMD.3dshapes/C_0805.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 0)) ) ) (module Capacitors_SMD:C_0805 (layer F.Cu) (tedit 58AA8463) (tstamp 5889482E) (at 56.72 60.63 270) (descr "Capacitor SMD 0805, reflow soldering, AVX (see smccp.pdf)") (tags "capacitor 0805") (path /594F323B/594F324D) (attr smd) (fp_text reference C53 (at 2.08 0.09 360) (layer F.SilkS) (effects (font (size 0.508 0.508) (thickness 0.127))) ) (fp_text value 100uf (at 0 1.75 270) (layer F.Fab) (effects (font (size 0.508 0.508) (thickness 0.127))) ) (fp_line (start -1.7 0.85) (end -0.65 0.85) (layer F.SilkS) (width 0.05)) (fp_line (start -1.7 0.15) (end -1.7 0.85) (layer F.SilkS) (width 0.05)) (fp_line (start -1.95 0) (end -1.7 0.15) (layer F.SilkS) (width 0.05)) (fp_line (start -1.7 -0.2) (end -1.95 0) (layer F.SilkS) (width 0.05)) (fp_line (start -1.7 -0.85) (end -1.7 -0.2) (layer F.SilkS) (width 0.05)) (fp_line (start -0.65 -0.85) (end -1.7 -0.85) (layer F.SilkS) (width 0.05)) (fp_line (start 1.7 -0.85) (end 0.65 -0.85) (layer F.SilkS) (width 0.05)) (fp_line (start 1.7 0.85) (end 1.7 -0.85) (layer F.SilkS) (width 0.05)) (fp_line (start 0.65 0.85) (end 1.7 0.85) (layer F.SilkS) (width 0.05)) (fp_text user %R (at 0 -1.5 270) (layer F.Fab) (effects (font (size 0.508 0.508) (thickness 0.127))) ) (fp_line (start -1 0.62) (end -1 -0.62) (layer F.Fab) (width 0.1)) (fp_line (start 1 0.62) (end -1 0.62) (layer F.Fab) (width 0.1)) (fp_line (start 1 -0.62) (end 1 0.62) (layer F.Fab) (width 0.1)) (fp_line (start -1 -0.62) (end 1 -0.62) (layer F.Fab) (width 0.1)) (fp_line (start 0.5 -0.85) (end -0.5 -0.85) (layer F.SilkS) (width 0.12)) (fp_line (start -0.5 0.85) (end 0.5 0.85) (layer F.SilkS) (width 0.12)) (fp_line (start -1.75 -0.88) (end 1.75 -0.88) (layer F.CrtYd) (width 0.05)) (fp_line (start -1.75 -0.88) (end -1.75 0.87) (layer F.CrtYd) (width 0.05)) (fp_line (start 1.75 0.87) (end 1.75 -0.88) (layer F.CrtYd) (width 0.05)) (fp_line (start 1.75 0.87) (end -1.75 0.87) (layer F.CrtYd) (width 0.05)) (pad 1 smd rect (at -1 0 270) (size 1 1.25) (layers F.Cu F.Paste F.Mask) (net 31 VCC_BANK14_B)) (pad 2 smd rect (at 1 0 270) (size 1 1.25) (layers F.Cu F.Paste F.Mask) (net 1 GND)) (model Capacitors_SMD.3dshapes/C_0805.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 0)) ) ) (module Capacitors_SMD:C_0805 (layer B.Cu) (tedit 58AA8463) (tstamp 58818781) (at 60.63 69.31 270) (descr "Capacitor SMD 0805, reflow soldering, AVX (see smccp.pdf)") (tags "capacitor 0805") (path /5881899D/594F3261) (attr smd) (fp_text reference C3 (at 2.08 -0.02 540) (layer B.SilkS) (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_text value 100uf (at 0 -1.75 270) (layer B.Fab) (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_line (start -1.7 -0.85) (end -0.65 -0.85) (layer B.SilkS) (width 0.05)) (fp_line (start -1.7 -0.15) (end -1.7 -0.85) (layer B.SilkS) (width 0.05)) (fp_line (start -1.95 0) (end -1.7 -0.15) (layer B.SilkS) (width 0.05)) (fp_line (start -1.7 0.2) (end -1.95 0) (layer B.SilkS) (width 0.05)) (fp_line (start -1.7 0.85) (end -1.7 0.2) (layer B.SilkS) (width 0.05)) (fp_line (start -0.65 0.85) (end -1.7 0.85) (layer B.SilkS) (width 0.05)) (fp_line (start 1.7 0.85) (end 0.65 0.85) (layer B.SilkS) (width 0.05)) (fp_line (start 1.7 -0.85) (end 1.7 0.85) (layer B.SilkS) (width 0.05)) (fp_line (start 0.65 -0.85) (end 1.7 -0.85) (layer B.SilkS) (width 0.05)) (fp_text user %R (at 0 1.5 270) (layer B.Fab) (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_line (start -1 -0.62) (end -1 0.62) (layer B.Fab) (width 0.1)) (fp_line (start 1 -0.62) (end -1 -0.62) (layer B.Fab) (width 0.1)) (fp_line (start 1 0.62) (end 1 -0.62) (layer B.Fab) (width 0.1)) (fp_line (start -1 0.62) (end 1 0.62) (layer B.Fab) (width 0.1)) (fp_line (start 0.5 0.85) (end -0.5 0.85) (layer B.SilkS) (width 0.12)) (fp_line (start -0.5 -0.85) (end 0.5 -0.85) (layer B.SilkS) (width 0.12)) (fp_line (start -1.75 0.88) (end 1.75 0.88) (layer B.CrtYd) (width 0.05)) (fp_line (start -1.75 0.88) (end -1.75 -0.87) (layer B.CrtYd) (width 0.05)) (fp_line (start 1.75 -0.87) (end 1.75 0.88) (layer B.CrtYd) (width 0.05)) (fp_line (start 1.75 -0.87) (end -1.75 -0.87) (layer B.CrtYd) (width 0.05)) (pad 1 smd rect (at -1 0 270) (size 1 1.25) (layers B.Cu B.Paste B.Mask) (net 13 P1V0_VCC_FPGA_B)) (pad 2 smd rect (at 1 0 270) (size 1 1.25) (layers B.Cu B.Paste B.Mask) (net 1 GND)) (model Capacitors_SMD.3dshapes/C_0805.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 0)) ) ) (module SMT:c_0201_least (layer B.Cu) (tedit 58881732) (tstamp 5934BCDC) (at 69.64 68.12 90) (path /5881899D/5934D9C2) (attr smd) (fp_text reference C23 (at 0.09 -0.66 90) (layer B.SilkS) (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_text value 0.47uf (at -0.1 -0.5 90) (layer B.Fab) (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_line (start -0.6 -0.3) (end -0.6 0.3) (layer B.SilkS) (width 0.05)) (fp_line (start 0.6 -0.3) (end -0.6 -0.3) (layer B.SilkS) (width 0.05)) (fp_line (start 0.6 0.3) (end 0.6 -0.3) (layer B.SilkS) (width 0.05)) (fp_line (start -0.6 0.3) (end 0.6 0.3) (layer B.SilkS) (width 0.05)) (pad 1 smd rect (at -0.28 0 90) (size 0.36 0.32) (layers B.Cu B.Paste B.Mask) (net 14 P1V8_FPGA_VCCAUX_B)) (pad 2 smd rect (at 0.28 0 90) (size 0.36 0.32) (layers B.Cu B.Paste B.Mask) (net 1 GND)) (model Capacitors_SMD.3dshapes/C_0201.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 0)) ) ) (module Wire_Pads:SolderWirePad_single_SMD_1x1mm (layer F.Cu) (tedit 5932BE77) (tstamp 5935F0D1) (at 57.864 69.884 180) (descr "Wire Pad, Square, SMD Pad, 5mm x 10mm,") (tags "MesurementPoint Square SMDPad 5mmx10mm ") (path /594F323B/5935F747) (attr smd) (fp_text reference J7 (at 1.45 1.25 180) (layer F.SilkS) hide (effects (font (size 0.508 0.508) (thickness 0.127))) ) (fp_text value 3P3 (at -0.046 0.824 180) (layer F.SilkS) (effects (font (size 0.508 0.508) (thickness 0.127))) ) (pad 1 smd rect (at 0 0 180) (size 1 1) (layers F.Cu F.Mask) (net 31 VCC_BANK14_B)) ) (module Wire_Pads:SolderWirePad_single_SMD_1x1mm (layer F.Cu) (tedit 5932BE77) (tstamp 5935F0D6) (at 60.912 69.376 180) (descr "Wire Pad, Square, SMD Pad, 5mm x 10mm,") (tags "MesurementPoint Square SMDPad 5mmx10mm ") (path /594F323B/5935FB77) (attr smd) (fp_text reference J8 (at 1.45 1.25 180) (layer F.SilkS) hide (effects (font (size 0.508 0.508) (thickness 0.127))) ) (fp_text value 1P8 (at 0.032 -0.894 180) (layer F.SilkS) (effects (font (size 0.508 0.508) (thickness 0.127))) ) (pad 1 smd rect (at 0 0 180) (size 1 1) (layers F.Cu F.Mask) (net 14 P1V8_FPGA_VCCAUX_B)) ) (module Wire_Pads:SolderWirePad_single_SMD_1x1mm (layer F.Cu) (tedit 5932BE77) (tstamp 5935F0E5) (at 56.086 69.376 180) (descr "Wire Pad, Square, SMD Pad, 5mm x 10mm,") (tags "MesurementPoint Square SMDPad 5mmx10mm ") (path /594F323B/5935FCAA) (attr smd) (fp_text reference J11 (at 1.45 1.25 180) (layer F.SilkS) hide (effects (font (size 0.508 0.508) (thickness 0.127))) ) (fp_text value 1P0 (at -0.024 -0.894 180) (layer F.SilkS) (effects (font (size 0.508 0.508) (thickness 0.127))) ) (pad 1 smd rect (at 0 0 180) (size 1 1) (layers F.Cu F.Mask) (net 13 P1V0_VCC_FPGA_B)) ) (module Wire_Pads:SolderWirePad_single_SMD_1x1mm (layer F.Cu) (tedit 5932BE77) (tstamp 5935F0EA) (at 59.388 69.884 180) (descr "Wire Pad, Square, SMD Pad, 5mm x 10mm,") (tags "MesurementPoint Square SMDPad 5mmx10mm ") (path /594F323B/5935FD11) (attr smd) (fp_text reference J12 (at 1.45 1.25 180) (layer F.SilkS) hide (effects (font (size 0.508 0.508) (thickness 0.127))) ) (fp_text value GND (at -0.192 0.864 180) (layer F.SilkS) (effects (font (size 0.508 0.508) (thickness 0.127))) ) (pad 1 smd rect (at 0 0 180) (size 1 1) (layers F.Cu F.Mask) (net 1 GND)) ) (module Wire_Pads:Pad_SMD_0.5x0.5mm (layer F.Cu) (tedit 5935F9CB) (tstamp 5935F0E0) (at 73.33 57.64 180) (descr "Wire Pad, Square, SMD Pad, 5mm x 10mm,") (tags "MesurementPoint Square SMDPad 5mmx10mm ") (path /594F323B/5935FC42) (attr smd) (fp_text reference J10 (at 1.45 1.25 180) (layer F.SilkS) hide (effects (font (size 0.508 0.508) (thickness 0.127))) ) (fp_text value 1P2 (at -1.18 -0.04 180) (layer F.SilkS) (effects (font (size 0.508 0.508) (thickness 0.127))) ) (pad 1 smd rect (at 0 0 180) (size 0.6 0.5) (layers F.Cu F.Mask) (net 15 P1V2_MGTAVTT_B)) ) (module Wire_Pads:Pad_SMD_0.5x0.5mm (layer F.Cu) (tedit 5935F9CB) (tstamp 5935F0DB) (at 65.01 58.05 180) (descr "Wire Pad, Square, SMD Pad, 5mm x 10mm,") (tags "MesurementPoint Square SMDPad 5mmx10mm ") (path /594F323B/5935FBE1) (attr smd) (fp_text reference J9 (at 1.45 1.25 180) (layer F.SilkS) hide (effects (font (size 0.508 0.508) (thickness 0.127))) ) (fp_text value 1P0 (at 1.09 -0.02 180) (layer F.SilkS) (effects (font (size 0.508 0.508) (thickness 0.127))) ) (pad 1 smd rect (at 0 0 180) (size 0.6 0.5) (layers F.Cu F.Mask) (net 12 P1V0_MGTAVCC_B)) ) (module MIC47050:MIC47050-DFN-6-2MM (layer B.Cu) (tedit 59AC65FA) (tstamp 58819163) (at 72.05 58.87 90) (path /594F323B/594F321D) (attr smd) (fp_text reference U5 (at 1.36 -0.73 360) (layer B.SilkS) (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_text value MIC47050-1.2YML (at 0.2 1.8 90) (layer B.SilkS) hide (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_line (start -1 1.25) (end -1 -1.25) (layer B.SilkS) (width 0.03)) (fp_line (start -1 -1.25) (end 1 -1.25) (layer B.SilkS) (width 0.03)) (fp_line (start 1 -1.25) (end 1 1.25) (layer B.SilkS) (width 0.03)) (fp_line (start 1 1.25) (end -1 1.25) (layer B.SilkS) (width 0.03)) (fp_circle (center -0.51 -1.51) (end -0.451691 -1.51) (layer B.SilkS) (width 0.03)) (pad 5 smd rect (at 0 0.91) (size 0.675 0.25) (layers B.Cu B.Paste B.Mask)) (pad 6 smd rect (at -0.5 0.91) (size 0.675 0.25) (layers B.Cu B.Paste B.Mask) (net 31 VCC_BANK14_B)) (pad 4 smd rect (at 0.51 0.91) (size 0.675 0.25) (layers B.Cu B.Paste B.Mask) (net 15 P1V2_MGTAVTT_B)) (pad 1 smd rect (at -0.5 -0.91) (size 0.675 0.25) (layers B.Cu B.Paste B.Mask) (net 31 VCC_BANK14_B)) (pad 2 smd rect (at 0 -0.91) (size 0.675 0.25) (layers B.Cu B.Paste B.Mask) (net 1 GND)) (pad 3 smd rect (at 0.5 -0.91) (size 0.675 0.25) (layers B.Cu B.Paste B.Mask) (net 2 "Net-(C56-Pad1)")) (pad 7 smd rect (at 0 0) (size 0.61 1.42) (layers B.Cu B.Paste B.Mask) (net 1 GND)) ) (module conn:pico-ezmate-6 (layer B.Cu) (tedit 588E588E) (tstamp 59AB5068) (at 57.8475 79.06 270) (path /594F323A/59AB5657) (fp_text reference P1 (at -5.02 1.8375 270) (layer B.SilkS) (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_text value CONN_01X06 (at 1.075 -4.2 270) (layer B.Fab) (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_line (start 4.5 -2.5) (end -4.5 -2.5) (layer B.SilkS) (width 0.05)) (fp_line (start 4.5 2.5) (end 4.5 -2.5) (layer B.SilkS) (width 0.05)) (fp_line (start -4.5 2.5) (end 4.5 2.5) (layer B.SilkS) (width 0.05)) (fp_line (start -4.5 -2.5) (end -4.5 2.5) (layer B.SilkS) (width 0.05)) (pad 3 smd rect (at -0.6 1.8875 270) (size 0.6 0.85) (layers B.Cu B.Paste B.Mask) (net 1 GND)) (pad 4 smd rect (at 0.6 1.8875 270) (size 0.6 0.85) (layers B.Cu B.Paste B.Mask) (net 54 "Net-(P1-Pad4)")) (pad 5 smd rect (at 1.8 1.8875 270) (size 0.6 0.85) (layers B.Cu B.Paste B.Mask) (net 55 "Net-(P1-Pad5)")) (pad 1 smd rect (at -3 1.8875 270) (size 0.6 0.85) (layers B.Cu B.Paste B.Mask) (net 56 "Net-(P1-Pad1)")) (pad 2 smd rect (at -1.8 1.8875 270) (size 0.6 0.85) (layers B.Cu B.Paste B.Mask) (net 57 "Net-(P1-Pad2)")) (pad 6 smd rect (at 3 1.8875 270) (size 0.6 0.85) (layers B.Cu B.Paste B.Mask) (net 31 VCC_BANK14_B)) (pad P smd rect (at -4.15 -1.8875 270) (size 0.7 0.8) (layers B.Cu B.Paste B.Mask)) (pad P smd rect (at 4.15 -2 270) (size 0.7 0.8) (layers B.Cu B.Paste B.Mask)) ) (module Housings_DFN_QFN:QFN-16-1EP_4x4mm_Pitch0.65mm_2 (layer B.Cu) (tedit 5936092A) (tstamp 5939DDC5) (at 63.34 78.33 270) (descr "16-Lead Plastic Quad Flat, No Lead Package (ML) - 4x4x0.9 mm Body [QFN]; (see Microchip Packaging Specification 00000049BS.pdf)") (tags "QFN 0.65") (path /588189A5/59323D6A) (attr smd) (fp_text reference U7 (at 2.67 -1.85 360) (layer B.SilkS) (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_text value FT230XQ (at 0 -3.4 270) (layer B.Fab) (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_line (start -1 2) (end 2 2) (layer B.Fab) (width 0.15)) (fp_line (start 2 2) (end 2 -2) (layer B.Fab) (width 0.15)) (fp_line (start 2 -2) (end -2 -2) (layer B.Fab) (width 0.15)) (fp_line (start -2 -2) (end -2 1) (layer B.Fab) (width 0.15)) (fp_line (start -2 1) (end -1 2) (layer B.Fab) (width 0.15)) (fp_line (start -2.65 2.65) (end -2.65 -2.65) (layer B.CrtYd) (width 0.05)) (fp_line (start 2.65 2.65) (end 2.65 -2.65) (layer B.CrtYd) (width 0.05)) (fp_line (start -2.65 2.65) (end 2.65 2.65) (layer B.CrtYd) (width 0.05)) (fp_line (start -2.65 -2.65) (end 2.65 -2.65) (layer B.CrtYd) (width 0.05)) (fp_line (start 2.15 2.15) (end 2.15 1.375) (layer B.SilkS) (width 0.15)) (fp_line (start -2.15 -2.15) (end -2.15 -1.375) (layer B.SilkS) (width 0.15)) (fp_line (start 2.15 -2.15) (end 2.15 -1.375) (layer B.SilkS) (width 0.15)) (fp_line (start -2.15 2.15) (end -1.375 2.15) (layer B.SilkS) (width 0.15)) (fp_line (start -2.15 -2.15) (end -1.375 -2.15) (layer B.SilkS) (width 0.15)) (fp_line (start 2.15 -2.15) (end 1.375 -2.15) (layer B.SilkS) (width 0.15)) (fp_line (start 2.15 2.15) (end 1.375 2.15) (layer B.SilkS) (width 0.15)) (pad 1 smd rect (at -1.85 0.975 270) (size 0.8 0.35) (layers B.Cu B.Paste B.Mask) (net 31 VCC_BANK14_B)) (pad 2 smd rect (at -1.85 0.325 270) (size 0.8 0.35) (layers B.Cu B.Paste B.Mask) (net 30 JTAG_TDI_B)) (pad 3 smd rect (at -1.85 -0.325 270) (size 0.8 0.35) (layers B.Cu B.Paste B.Mask) (net 1 GND)) (pad 4 smd rect (at -1.85 -0.975 270) (size 0.8 0.35) (layers B.Cu B.Paste B.Mask) (net 28 JTAG_TMS_B)) (pad 5 smd rect (at -0.975 -1.85 180) (size 0.8 0.35) (layers B.Cu B.Paste B.Mask)) (pad 6 smd rect (at -0.325 -1.85 180) (size 0.8 0.35) (layers B.Cu B.Paste B.Mask) (net 21 USB_2+)) (pad 7 smd rect (at 0.325 -1.85 180) (size 0.8 0.35) (layers B.Cu B.Paste B.Mask) (net 22 USB_2-)) (pad 8 smd rect (at 0.975 -1.85 180) (size 0.8 0.35) (layers B.Cu B.Paste B.Mask) (net 31 VCC_BANK14_B)) (pad 9 smd rect (at 1.85 -0.975 270) (size 0.8 0.35) (layers B.Cu B.Paste B.Mask) (net 31 VCC_BANK14_B)) (pad 10 smd rect (at 1.85 -0.325 270) (size 0.8 0.35) (layers B.Cu B.Paste B.Mask) (net 31 VCC_BANK14_B)) (pad 11 smd rect (at 1.85 0.325 270) (size 0.8 0.35) (layers B.Cu B.Paste B.Mask)) (pad 12 smd rect (at 1.85 0.975 270) (size 0.8 0.35) (layers B.Cu B.Paste B.Mask)) (pad 13 smd rect (at 0.975 1.85 180) (size 0.8 0.35) (layers B.Cu B.Paste B.Mask) (net 1 GND)) (pad 14 smd rect (at 0.325 1.85 180) (size 0.8 0.35) (layers B.Cu B.Paste B.Mask)) (pad 15 smd rect (at -0.325 1.85 180) (size 0.8 0.35) (layers B.Cu B.Paste B.Mask) (net 27 JTAG_TCK_B)) (pad 16 smd rect (at -0.975 1.85 180) (size 0.8 0.35) (layers B.Cu B.Paste B.Mask) (net 29 JTAG_TDO_B)) (pad 17 smd rect (at 0.525 -0.525 270) (size 1.05 1.05) (layers B.Cu B.Paste B.Mask) (net 1 GND) (solder_paste_margin_ratio -0.2)) (pad 17 smd rect (at 0.525 0.525 270) (size 1.05 1.05) (layers B.Cu B.Paste B.Mask) (net 1 GND) (solder_paste_margin_ratio -0.2)) (pad 17 smd rect (at -0.525 -0.525 270) (size 1.05 1.05) (layers B.Cu B.Paste B.Mask) (net 1 GND) (solder_paste_margin_ratio -0.2)) (pad 17 smd rect (at -0.525 0.525 270) (size 1.05 1.05) (layers B.Cu B.Paste B.Mask) (net 1 GND) (solder_paste_margin_ratio -0.2)) (model Housings_DFN_QFN.3dshapes/QFN-16-1EP_4x4mm_Pitch0.65mm.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 0)) ) ) (module MAX1589A:MAX1589AETT100T (layer B.Cu) (tedit 59C32052) (tstamp 58819153) (at 63.1 59.48 180) (path /594F323B/586DD822) (fp_text reference U4 (at 1.58 -2.03 180) (layer B.SilkS) (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_text value MAX1589AETT100T (at 1.8 -3.6 180) (layer B.SilkS) hide (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_text user "Copyright 2016 Accelerated Designs. All rights reserved." (at 0 0 180) (layer Cmts.User) hide (effects (font (size 0.508 0.508) (thickness 0.127))) ) (fp_line (start -1.5494 -1.5494) (end 1.5494 -1.5494) (layer B.SilkS) (width 0.1524)) (fp_line (start 1.5494 1.5494) (end -1.9 1.55) (layer B.SilkS) (width 0.1524)) (fp_line (start -1.5494 -1.5494) (end 1.5494 -1.5494) (layer Dwgs.User) (width 0.1524)) (fp_line (start 1.5494 -1.5494) (end 1.5494 1.5494) (layer Dwgs.User) (width 0.1524)) (fp_line (start 1.5494 1.5494) (end -1.5494 1.5494) (layer Dwgs.User) (width 0.1524)) (fp_line (start -1.5494 1.5494) (end -1.5494 -1.5494) (layer Dwgs.User) (width 0.1524)) (fp_arc (start 0 1.5494) (end 0.3048 1.5494) (angle -180) (layer Dwgs.User) (width 0.1524)) (pad 1 smd rect (at -1.5018 0.9398 180) (size 0.7048 0.4572) (layers B.Cu B.Paste B.Mask) (net 12 P1V0_MGTAVCC_B)) (pad 2 smd rect (at -1.5018 0 180) (size 0.7048 0.4572) (layers B.Cu B.Paste B.Mask)) (pad 3 smd rect (at -1.5018 -0.9398 180) (size 0.7048 0.4572) (layers B.Cu B.Paste B.Mask)) (pad 4 smd rect (at 1.5018 -0.9398 180) (size 0.7048 0.4572) (layers B.Cu B.Paste B.Mask) (net 1 GND)) (pad 5 smd rect (at 1.5018 0 180) (size 0.7048 0.4572) (layers B.Cu B.Paste B.Mask) (net 2 "Net-(C56-Pad1)")) (pad 6 smd rect (at 1.5018 0.9398 180) (size 0.7048 0.4572) (layers B.Cu B.Paste B.Mask) (net 2 "Net-(C56-Pad1)")) (pad 7 smd rect (at 0 0 180) (size 1.6002 2.3876) (layers B.Cu B.Paste B.Mask) (net 1 GND)) (pad 7 smd rect (at 0 0 180) (size 0.0254 0.0254) (layers B.Paste) (net 1 GND)) ) (module Resistors_SMD:R_Array_Convex_4x0402 (layer F.Cu) (tedit 58AADED9) (tstamp 59EAB850) (at 57.52 72.21) (descr "Chip Resistor Network, ROHM MNR04 (see mnr_g.pdf)") (tags "resistor array") (path /594F323A/59EAB957) (attr smd) (fp_text reference RN2 (at -1.48 0.09 90) (layer F.SilkS) (effects (font (size 0.508 0.508) (thickness 0.127))) ) (fp_text value 681 (at 0 2.1) (layer F.Fab) (effects (font (size 0.508 0.508) (thickness 0.127))) ) (fp_text user %R (at 0 -2.1) (layer F.Fab) (effects (font (size 0.508 0.508) (thickness 0.127))) ) (fp_line (start -0.5 -1) (end 0.5 -1) (layer F.Fab) (width 0.1)) (fp_line (start 0.5 -1) (end 0.5 1) (layer F.Fab) (width 0.1)) (fp_line (start 0.5 1) (end -0.5 1) (layer F.Fab) (width 0.1)) (fp_line (start -0.5 1) (end -0.5 -1) (layer F.Fab) (width 0.1)) (fp_line (start 0.25 -1.18) (end -0.25 -1.18) (layer F.SilkS) (width 0.12)) (fp_line (start 0.25 1.18) (end -0.25 1.18) (layer F.SilkS) (width 0.12)) (fp_line (start -1 -1.25) (end 1 -1.25) (layer F.CrtYd) (width 0.05)) (fp_line (start -1 -1.25) (end -1 1.25) (layer F.CrtYd) (width 0.05)) (fp_line (start 1 1.25) (end 1 -1.25) (layer F.CrtYd) (width 0.05)) (fp_line (start 1 1.25) (end -1 1.25) (layer F.CrtYd) (width 0.05)) (pad 1 smd rect (at -0.5 -0.75) (size 0.5 0.4) (layers F.Cu F.Paste F.Mask) (net 31 VCC_BANK14_B)) (pad 3 smd rect (at -0.5 0.25) (size 0.5 0.3) (layers F.Cu F.Paste F.Mask) (net 31 VCC_BANK14_B)) (pad 2 smd rect (at -0.5 -0.25) (size 0.5 0.3) (layers F.Cu F.Paste F.Mask) (net 31 VCC_BANK14_B)) (pad 4 smd rect (at -0.5 0.75) (size 0.5 0.4) (layers F.Cu F.Paste F.Mask) (net 31 VCC_BANK14_B)) (pad 7 smd rect (at 0.5 -0.25) (size 0.5 0.3) (layers F.Cu F.Paste F.Mask) (net 42 "Net-(D4-Pad2)")) (pad 8 smd rect (at 0.5 -0.75) (size 0.5 0.4) (layers F.Cu F.Paste F.Mask) (net 41 "Net-(D3-Pad2)")) (pad 6 smd rect (at 0.5 0.25) (size 0.5 0.3) (layers F.Cu F.Paste F.Mask) (net 52 "Net-(D2-Pad2)")) (pad 5 smd rect (at 0.5 0.75) (size 0.5 0.4) (layers F.Cu F.Paste F.Mask) (net 40 BUSY_LED_PU)) (model Resistors_SMD.3dshapes/R_Array_Convex_4x0402.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 0)) ) ) (module Resistors_SMD:R_Array_Convex_4x0402 (layer F.Cu) (tedit 58AADED9) (tstamp 59EABC2A) (at 57.52 74.72) (descr "Chip Resistor Network, ROHM MNR04 (see mnr_g.pdf)") (tags "resistor array") (path /5881899D/59EAD81F) (attr smd) (fp_text reference RN1 (at -1.46 -0.03 90) (layer F.SilkS) (effects (font (size 0.508 0.508) (thickness 0.127))) ) (fp_text value 4.7K (at 0 2.1) (layer F.Fab) (effects (font (size 0.508 0.508) (thickness 0.127))) ) (fp_text user %R (at 0 -2.1) (layer F.Fab) (effects (font (size 0.508 0.508) (thickness 0.127))) ) (fp_line (start -0.5 -1) (end 0.5 -1) (layer F.Fab) (width 0.1)) (fp_line (start 0.5 -1) (end 0.5 1) (layer F.Fab) (width 0.1)) (fp_line (start 0.5 1) (end -0.5 1) (layer F.Fab) (width 0.1)) (fp_line (start -0.5 1) (end -0.5 -1) (layer F.Fab) (width 0.1)) (fp_line (start 0.25 -1.18) (end -0.25 -1.18) (layer F.SilkS) (width 0.12)) (fp_line (start 0.25 1.18) (end -0.25 1.18) (layer F.SilkS) (width 0.12)) (fp_line (start -1 -1.25) (end 1 -1.25) (layer F.CrtYd) (width 0.05)) (fp_line (start -1 -1.25) (end -1 1.25) (layer F.CrtYd) (width 0.05)) (fp_line (start 1 1.25) (end 1 -1.25) (layer F.CrtYd) (width 0.05)) (fp_line (start 1 1.25) (end -1 1.25) (layer F.CrtYd) (width 0.05)) (pad 1 smd rect (at -0.5 -0.75) (size 0.5 0.4) (layers F.Cu F.Paste F.Mask) (net 31 VCC_BANK14_B)) (pad 3 smd rect (at -0.5 0.25) (size 0.5 0.3) (layers F.Cu F.Paste F.Mask) (net 31 VCC_BANK14_B)) (pad 2 smd rect (at -0.5 -0.25) (size 0.5 0.3) (layers F.Cu F.Paste F.Mask) (net 31 VCC_BANK14_B)) (pad 4 smd rect (at -0.5 0.75) (size 0.5 0.4) (layers F.Cu F.Paste F.Mask) (net 31 VCC_BANK14_B)) (pad 7 smd rect (at 0.5 -0.25) (size 0.5 0.3) (layers F.Cu F.Paste F.Mask) (net 61 "Net-(RN1-Pad7)")) (pad 8 smd rect (at 0.5 -0.75) (size 0.5 0.4) (layers F.Cu F.Paste F.Mask) (net 3 "Net-(D1-Pad1)")) (pad 6 smd rect (at 0.5 0.25) (size 0.5 0.3) (layers F.Cu F.Paste F.Mask) (net 62 "Net-(RN1-Pad6)")) (pad 5 smd rect (at 0.5 0.75) (size 0.5 0.4) (layers F.Cu F.Paste F.Mask)) (model Resistors_SMD.3dshapes/R_Array_Convex_4x0402.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 0)) ) ) (module Resistors_SMD:R_Array_Convex_4x0402 (layer B.Cu) (tedit 58AADED9) (tstamp 59EAC68D) (at 70.87 82.28 90) (descr "Chip Resistor Network, ROHM MNR04 (see mnr_g.pdf)") (tags "resistor array") (path /594F323A/59EAF829) (attr smd) (fp_text reference RN3 (at -0.01 -1.56 90) (layer B.SilkS) (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_text value 4.7K (at 0 -2.1 90) (layer B.Fab) (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_text user %R (at 0 2.1 90) (layer B.Fab) (effects (font (size 0.508 0.508) (thickness 0.127)) (justify mirror)) ) (fp_line (start -0.5 1) (end 0.5 1) (layer B.Fab) (width 0.1)) (fp_line (start 0.5 1) (end 0.5 -1) (layer B.Fab) (width 0.1)) (fp_line (start 0.5 -1) (end -0.5 -1) (layer B.Fab) (width 0.1)) (fp_line (start -0.5 -1) (end -0.5 1) (layer B.Fab) (width 0.1)) (fp_line (start 0.25 1.18) (end -0.25 1.18) (layer B.SilkS) (width 0.12)) (fp_line (start 0.25 -1.18) (end -0.25 -1.18) (layer B.SilkS) (width 0.12)) (fp_line (start -1 1.25) (end 1 1.25) (layer B.CrtYd) (width 0.05)) (fp_line (start -1 1.25) (end -1 -1.25) (layer B.CrtYd) (width 0.05)) (fp_line (start 1 -1.25) (end 1 1.25) (layer B.CrtYd) (width 0.05)) (fp_line (start 1 -1.25) (end -1 -1.25) (layer B.CrtYd) (width 0.05)) (pad 1 smd rect (at -0.5 0.75 90) (size 0.5 0.4) (layers B.Cu B.Paste B.Mask) (net 31 VCC_BANK14_B)) (pad 3 smd rect (at -0.5 -0.25 90) (size 0.5 0.3) (layers B.Cu B.Paste B.Mask) (net 31 VCC_BANK14_B)) (pad 2 smd rect (at -0.5 0.25 90) (size 0.5 0.3) (layers B.Cu B.Paste B.Mask) (net 31 VCC_BANK14_B)) (pad 4 smd rect (at -0.5 -0.75 90) (size 0.5 0.4) (layers B.Cu B.Paste B.Mask) (net 31 VCC_BANK14_B)) (pad 7 smd rect (at 0.5 0.25 90) (size 0.5 0.3) (layers B.Cu B.Paste B.Mask) (net 43 "Net-(RN3-Pad7)")) (pad 8 smd rect (at 0.5 0.75 90) (size 0.5 0.4) (layers B.Cu B.Paste B.Mask)) (pad 6 smd rect (at 0.5 -0.25 90) (size 0.5 0.3) (layers B.Cu B.Paste B.Mask) (net 44 "Net-(RN3-Pad6)")) (pad 5 smd rect (at 0.5 -0.75 90) (size 0.5 0.4) (layers B.Cu B.Paste B.Mask) (net 45 "Net-(RN3-Pad5)")) (model Resistors_SMD.3dshapes/R_Array_Convex_4x0402.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 0)) ) ) (module SMT:U.FL-COAX (layer F.Cu) (tedit 5A13AB16) (tstamp 59ED2841) (at 70.21 77.8272 90) (path /594F3239/59EB4DA0) (attr smd) (fp_text reference J1 (at 1.7472 -0.86 180) (layer F.SilkS) (effects (font (size 0.508 0.508) (thickness 0.127))) ) (fp_text value RX- (at 1.7272 1.22 180) (layer F.SilkS) (effects (font (size 0.508 0.508) (thickness 0.127))) ) (fp_line (start 1.1 0.3) (end 1.1 -0.3) (layer F.SilkS) (width 0.2032)) (fp_line (start 1.5 0.3) (end 1 0.3) (layer F.SilkS) (width 0.2032)) (fp_line (start 1.5 0.3) (end 1.5 -0.3) (layer F.SilkS) (width 0.2032)) (fp_line (start 1.5 -0.3) (end 1 -0.3) (layer F.SilkS) (width 0.2032)) (fp_circle (center 0 0) (end 0.2 0) (layer F.SilkS) (width 0.2032)) (fp_circle (center 0 0) (end 1 0) (layer F.SilkS) (width 0.2032)) (fp_line (start -1.3 -1.3) (end -1.3 1.3) (layer F.SilkS) (width 0.2032)) (fp_line (start -1.3 1.3) (end 1.3 1.3) (layer F.SilkS) (width 0.2032)) (fp_line (start 1.3 1.3) (end 1.3 -1.3) (layer F.SilkS) (width 0.2032)) (fp_line (start 1.3 -1.3) (end -1.3 -1.3) (layer F.SilkS) (width 0.2032)) (pad 1 smd rect (at -1.5 0 90) (size 1 1) (layers F.Cu F.Paste F.Mask) (net 51 "/FPGA PCIe/UMGT0_RX-")) (pad 2 smd rect (at 0 -1.5 90) (size 2.2 1) (layers F.Cu F.Paste F.Mask) (net 1 GND)) (pad 2 smd rect (at 0 1.5 90) (size 2.2 1) (layers F.Cu F.Paste F.Mask) (net 1 GND)) ) (module SMT:U.FL-COAX (layer F.Cu) (tedit 5A13AB28) (tstamp 59ED282F) (at 70.78 82.29 270) (path /594F3239/59EB4CCF) (attr smd) (fp_text reference J2 (at 1.38 2.22 360) (layer F.SilkS) (effects (font (size 0.508 0.508) (thickness 0.127))) ) (fp_text value RX+ (at -1.73 1.35 540) (layer F.SilkS) (effects (font (size 0.508 0.508) (thickness 0.127))) ) (fp_line (start 1.1 0.3) (end 1.1 -0.3) (layer F.SilkS) (width 0.2032)) (fp_line (start 1.5 0.3) (end 1 0.3) (layer F.SilkS) (width 0.2032)) (fp_line (start 1.5 0.3) (end 1.5 -0.3) (layer F.SilkS) (width 0.2032)) (fp_line (start 1.5 -0.3) (end 1 -0.3) (layer F.SilkS) (width 0.2032)) (fp_circle (center 0 0) (end 0.2 0) (layer F.SilkS) (width 0.2032)) (fp_circle (center 0 0) (end 1 0) (layer F.SilkS) (width 0.2032)) (fp_line (start -1.3 -1.3) (end -1.3 1.3) (layer F.SilkS) (width 0.2032)) (fp_line (start -1.3 1.3) (end 1.3 1.3) (layer F.SilkS) (width 0.2032)) (fp_line (start 1.3 1.3) (end 1.3 -1.3) (layer F.SilkS) (width 0.2032)) (fp_line (start 1.3 -1.3) (end -1.3 -1.3) (layer F.SilkS) (width 0.2032)) (pad 1 smd rect (at -1.5 0 270) (size 1 1) (layers F.Cu F.Paste F.Mask) (net 50 "/FPGA PCIe/UMGT0_RX+")) (pad 2 smd rect (at 0 -1.5 270) (size 2.2 1) (layers F.Cu F.Paste F.Mask) (net 1 GND)) (pad 2 smd rect (at 0 1.5 270) (size 2.2 1) (layers F.Cu F.Paste F.Mask) (net 1 GND)) ) (module SMT:U.FL-COAX (layer F.Cu) (tedit 5A13AAEA) (tstamp 59ED281D) (at 58.38 77.75 90) (path /594F3239/59EB4D49) (attr smd) (fp_text reference J6 (at -1.78 -1.3 180) (layer F.SilkS) (effects (font (size 0.508 0.508) (thickness 0.127))) ) (fp_text value TX- (at -1.8 1.44 180) (layer F.SilkS) (effects (font (size 0.508 0.508) (thickness 0.127))) ) (fp_line (start 1.1 0.3) (end 1.1 -0.3) (layer F.SilkS) (width 0.2032)) (fp_line (start 1.5 0.3) (end 1 0.3) (layer F.SilkS) (width 0.2032)) (fp_line (start 1.5 0.3) (end 1.5 -0.3) (layer F.SilkS) (width 0.2032)) (fp_line (start 1.5 -0.3) (end 1 -0.3) (layer F.SilkS) (width 0.2032)) (fp_circle (center 0 0) (end 0.2 0) (layer F.SilkS) (width 0.2032)) (fp_circle (center 0 0) (end 1 0) (layer F.SilkS) (width 0.2032)) (fp_line (start -1.3 -1.3) (end -1.3 1.3) (layer F.SilkS) (width 0.2032)) (fp_line (start -1.3 1.3) (end 1.3 1.3) (layer F.SilkS) (width 0.2032)) (fp_line (start 1.3 1.3) (end 1.3 -1.3) (layer F.SilkS) (width 0.2032)) (fp_line (start 1.3 -1.3) (end -1.3 -1.3) (layer F.SilkS) (width 0.2032)) (pad 1 smd rect (at -1.5 0 90) (size 1 1) (layers F.Cu F.Paste F.Mask) (net 49 "/FPGA PCIe/UMGT0_TX-")) (pad 2 smd rect (at 0 -1.5 90) (size 2.2 1) (layers F.Cu F.Paste F.Mask) (net 1 GND)) (pad 2 smd rect (at 0 1.5 90) (size 2.2 1) (layers F.Cu F.Paste F.Mask) (net 1 GND)) ) (module SMT:U.FL-COAX (layer F.Cu) (tedit 5A13AAFC) (tstamp 59ED280B) (at 58.38 82.08 270) (path /594F3239/59EB4D73) (attr smd) (fp_text reference J5 (at -1.74 1.3 360) (layer F.SilkS) (effects (font (size 0.508 0.508) (thickness 0.127))) ) (fp_text value TX+ (at -1.73 -1.45 360) (layer F.SilkS) (effects (font (size 0.508 0.508) (thickness 0.127))) ) (fp_line (start 1.1 0.3) (end 1.1 -0.3) (layer F.SilkS) (width 0.2032)) (fp_line (start 1.5 0.3) (end 1 0.3) (layer F.SilkS) (width 0.2032)) (fp_line (start 1.5 0.3) (end 1.5 -0.3) (layer F.SilkS) (width 0.2032)) (fp_line (start 1.5 -0.3) (end 1 -0.3) (layer F.SilkS) (width 0.2032)) (fp_circle (center 0 0) (end 0.2 0) (layer F.SilkS) (width 0.2032)) (fp_circle (center 0 0) (end 1 0) (layer F.SilkS) (width 0.2032)) (fp_line (start -1.3 -1.3) (end -1.3 1.3) (layer F.SilkS) (width 0.2032)) (fp_line (start -1.3 1.3) (end 1.3 1.3) (layer F.SilkS) (width 0.2032)) (fp_line (start 1.3 1.3) (end 1.3 -1.3) (layer F.SilkS) (width 0.2032)) (fp_line (start 1.3 -1.3) (end -1.3 -1.3) (layer F.SilkS) (width 0.2032)) (pad 1 smd rect (at -1.5 0 270) (size 1 1) (layers F.Cu F.Paste F.Mask) (net 48 "/FPGA PCIe/UMGT0_TX+")) (pad 2 smd rect (at 0 -1.5 270) (size 2.2 1) (layers F.Cu F.Paste F.Mask) (net 1 GND)) (pad 2 smd rect (at 0 1.5 270) (size 2.2 1) (layers F.Cu F.Paste F.Mask) (net 1 GND)) ) (gr_text 0781715006 (at 44.5 100.5) (layer Dwgs.User) (effects (font (size 1.5 1.5) (thickness 0.3))) ) (gr_line (start 47 89.5) (end 47 98.5) (layer Dwgs.User) (width 0.2)) (gr_line (start 51.5 89.5) (end 47 89.5) (layer Dwgs.User) (width 0.2)) (gr_line (start 51.5 98.5) (end 51.5 89.5) (layer Dwgs.User) (width 0.2)) (gr_line (start 47 98.5) (end 51.5 98.5) (layer Dwgs.User) (width 0.2)) (gr_text RoHS (at 62.3 81.45 180) (layer F.SilkS) (effects (font (size 0.75 0.75) (thickness 0.1))) ) (gr_text "PicoEVB\nRev D-3" (at 62.29 82.76 180) (layer F.SilkS) (effects (font (size 0.5 0.5) (thickness 0.1))) ) (gr_text "FABRICATION NOTES\n\n0. General information: 4 layer, 3 mil trace/space, 8 mil drill, via-in-pad\n\n1. FABRICATE PCB ACCORDING TO IPC-6012, CLASS 2\n\n2. Materials \n \n Laminate and prepeg: FR4, tg170 minimum\n\n Copper foil to be in accordance with IPC-MF-150. Unless otherwise specified:\n Copper weight for inner signal layers and inner plane layers to be 0.5 oz. \n Copper weight for outer layers 0.75 oz. \n Copper weight is to be considered “finished”.\n\n3. ALL PARTS & MATERIALS SHALL MEET THE RoHS DIRECTIVE 2011/65/EU.\n\n4. OVERALL BOARD THICKNESS TO BE 0.031 INCHES +/- 0.005 INCHES. ALL LAYERS VIEWED FROM THE PRIMARY (COMPONENT) SIDE.\n\n5. UNLESS OTHERWISE NOTED ALL HOLE DIMENSIONS APPLY AFTER PLATING.\n\n6. ALL HOLES SHALL HAVE A WALL THICKNESS OF 0.0006\" MINIMUM\n\n7. All in-pad vias are to be filled with a non-conductive epoxy and plated over, or other suitable method to achieve via-in-pad\n\n8. Top layer (F.Cu) impedance controlled, differential microstrip impedance: \n Two traces, 3 mils wide, spaced 3 mils apart, shall be impedance controlled to 100 ohms differential, +-10% \n\n9. FINISH IS ENIG AS PER IPC-4552\n\n10. SOLDERMASK SHALL MEET IPC-SM-840E, CLASS T REQUIREMENTS, COLOR GREEN. APPLY OVER BARE COPPER AS PER IPC-6012, CLASS 2.\n \n11. SILKSCREEN SHALL BE WHITE, PERMANENT, ORGANIC, NON-CONDUCTIVE INK. APPLY AS SHOWN IN FILES. \n THERE SHALL BE NO SILKSCREEN ON ANY SOLDERABLE COMPONENT PAD.\n\n12. ALL BOARDS ARE TO BE 100% ELECTRICALLY TESTED USING SUPPLIED IPC-D-356 NETLIST ACCORDING TO IPC-9252, CLASS 2.\n\n13. FINISHED BOARD SHALL MEET THE REQUIREMENTS OF UL796 WITH A FLAMMABILITY RATING OF UL 94V-0 OR BETTER.\n" (at 121.39 88.31) (layer Cmts.User) (effects (font (size 1.5 1.5) (thickness 0.3)) (justify left)) ) (gr_text 0781715006 (at 79.44 156.22) (layer Dwgs.User) (effects (font (size 1.5 1.5) (thickness 0.3))) ) (gr_line (start 81.94 145.22) (end 81.94 154.22) (layer Dwgs.User) (width 0.2)) (gr_line (start 86.44 145.22) (end 81.94 145.22) (layer Dwgs.User) (width 0.2)) (gr_line (start 86.44 154.22) (end 86.44 145.22) (layer Dwgs.User) (width 0.2)) (gr_line (start 81.94 154.22) (end 86.44 154.22) (layer Dwgs.User) (width 0.2)) (segment (start 73.49 82.4) (end 73.49 81.99) (width 0.254) (layer B.Cu) (net 1)) (segment (start 73.49 81.99) (end 73.51 81.97) (width 0.254) (layer B.Cu) (net 1)) (via (at 72.91 77.83) (size 0.4064) (drill 0.2032) (layers F.Cu B.Cu) (net 1)) (via (at 61.11 81.97) (size 0.4064) (drill 0.2032) (layers F.Cu B.Cu) (net 1)) (segment (start 76.12 77.79) (end 76.16 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