# NVRAM board text file template for the ASUS RT-AC68U router. # # Copyright 2012, Broadcom Corporation # All Rights Reserved. # # THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY # KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM # SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS # FOR A SPECIFIC PURPOSE OR NON-INFRINGEMENT CONCERNING THIS SOFTWARE. # boardtype describes what type of Broadcom reference board that the design resembles # Reference Board boardtype Reference Board boardtype # --------------- --------- --------------- --------- # BCM94704agr 0x042F BCM95356ssnr 0x0505 # BCM94712ap 0x0445 BCM94718nrl 0x050D # BCM94712p 0x0446 BCM94718nrx 0x050E # BCM94712agr 0x0451 BCM947186nrh 0x052A # BCM95350gr 0x0456 BCM947186nr2 0x052B # BCM94712lgr 0x0460 BCM94718nrlfmc 0x052C # BCM95352gr 0x0467 BCM95357nr 0x053A # BCM95351agr 0x0470 BCM95357nrepa 0x053B # BCM94704mpcb 0x0472 BCM95358nr2 0x053D # BCM94712agsdio 0x047B BCM95357nr2epa 0x054C # BCM95352elgr 0x047F BCM95357nr2 0x054D # BCM94705lmp 0x0489 BCM95357cbtnr2epa 0x056A # BCM94705gmp 0x0489 BCM94706nr 0x05B2 # BCM94705gmp115 0x0489 BCM94706nrh 0x05D8 # BCM94312mcg 0x048B BCM94706Lmiih5 0x0603 # BCM94312mcag 0x048C BCM94706nr2hmc 0x0617 # BCM95354gr 0x048E BCM94708r 0x0646 # BCM94705nogig 0x0496 BCM94709r 0x0665 # BCM94703nr 0x04C0 # BCM94716nr2 0x04CD # BCM94717ap 0x04CE # BCM94718nr 0x04CF # BCM94717mii 0x04ED # BCM94717cbtnr 0x04EF # BCM94716nr2ipa 0x04FB # # set a boardtype of BCM94708r but customized for ASUS RT-AC68U boardtype=0x0646 # boardnum is set by the nvserial program. Don't edit it here. boardnum=${serno} # Board revision. # With sromrev 4 and above, the boardrev is a 16 bit number as follows: # Bits [15:12] - Board Revision Type (brt), a 4 bit number with values: # 0: Legacy (old boardrev numbering scheme) # 1: Prototype "P" board. # 2: Production "A" board. # 3-15: Reserved. # Bits [11:0] - Board revision, 12 bits which use BCD encoding to represent a decimal number between 0 and 999. # # Ex: A legacy board rev of 4.5 is 0x0045 # Ex: A P304 board rev is 0x1304 # # Board revision is P100 boardrev=0x1100 # boardflags: 32-bits (LSB on top, MSB on bottom) # 0 = no Bluetooth coexistence 1 = board supports Bluetooth coexistence # 0 = set the PA VREF LDO to 2.85V 1 = set the PA VREF LDO to 3.00V # (4360 ONLY!) # 0 = does not implement GPIO 13 radio disable (Airline mode) 1 = board implements Airline mode on GPIO 13 # 0 = enable 256QAM support 1 = disable 256QAM support # (11ac chips only!) # --- # 0 = board does not have RoboSwitch or Ethernet switch core 1 = has RoboSwitch chip or Ethernet switch core # 0 = OK to power down PLL and chip (deprecated) # 0 = no high power CCK (disables opo parameter) 1 = can do high power CCK transmission (enables opo) # 0 = board does not have ADMtek switch 1 = board has ADMtek Ethernet switch # --- # 0 = Ethernet switch does not have VLAN capability 1 = Ethernet switch has VLAN capability # 0 = no Afterburner support (depricated) # 0 = chip has it's PCI/PCIe interface connected 1 = PCI/PCIe is floating or there is no PCI/PCIe interface on the chip # 0 = board does not have a FEM 1 = board uses a FEM # (legacy SISO chips only, not used for MIMO chips) # --- # 0 = board does not have an external 2.4GHz LNA 1 = board has an external 2.4GHz LNA # 0 = board does not have a high gain PA 1 = board has a high gain PA # (legacy SISO chips only, not used for MIMO chips) # 0 = no alternate Bluetooth coexistence 1 = 2-wire BT coex on GPIOs 4 & 5 # 0 = do not use alternate IQ imbalance settings 1 = use alt IQ settings # (only applies to 4318) # --- # 0 = board has external PA(s) 1 = board does not have external PA(s) # (legacy SISO chips only, not used for MIMO chips) # 0 = board's TSSI is negative slope 1 = board's TSSI is positive slope # (legacy SISO chips only, not used for MIMO chips) # 0 = board does not use the PA voltage reference LDO 1 = board uses the PA voltage reference LDO # (only applies to the 4326, 4328, and 5354) # 0 = no triple-throw switch shared with Bluetooth 1 = has triple-throw switch shared with BT # --- # 0 = chip does not support the phase shifter for MRC 1 = chip supports the phase shifter for MRC # (applies to 4325, 4326, 4328, and 5354 only) # 0 = board power topology does not use the Buck/Boost reg 1 = board power topology uses the Buck/Boost regulator # (4325 only) # 0 = board does not share antenna with Bluetooth 1 = board has FEM and switch to share antenna with BT # 0 = board power topology uses CBUCK (core buck) 1 = board power topology does not use CBUCK (core buck) # (applies to 4325 only) # --- # 0 = normal CCK EVM and spectral mask 1 = favor CCK EVM over spectral mask # 0 = board power topology does not use PALDO 1 = board power topology use PALDO # 0 = normal LNLDO2 (low noise LDO2) 1 = select 2.5V as LNLDO2 (low noise LDO2) output voltage # (4325 only) # 0 = non 4325: no minimum power index 1 = non 4325: enforce minimum power index to avoid FEM damage # (set to "1" only for SiGe SE2559L FEMs) # 4325: no power-on-reset workaround 4325: Apply power-on-reset workaround # --- # 0 = board does not have an external 5GHz LNA 1 = board has an external 5GHz LNA # 0 = for a 1x2 design, board does not have two T/R switches 1 = for a 1x2 design, board has two T/R switches # 0 = normal operation of 5GHz T/R switch for high RF 1 = hold T/R switch in the "R" position for high RF input powers. # input power. # 0 = use normal "InitGain" 1 = backoff "InitGain" based on the elna2g/5g parameters, for external LNAs only. # boardflags=0x00000110 # boardflags2: 32-bits (LSB on top, MSB on bottom) # 0 = board uses the 2055's built-in LDOs to power the 2055 1 = board uses external rxbb regulator to power the 2055 # 0 = use normal 5GHz band PLL settings 1 = use alternate 5GHz band PLL settings # (4322x and 4716/17/18 only) # 0 = do not use H/W TX power control on 4321 1 = use H/W TX power control on 4321 # (4321 only) # 0 = board does not support the 2x4 diversity switch 1 = board supports the 2x4 diversity switch # --- # 0 = board does not support the 5GHz band TX power gain 1 = board supports the 5GHz band TX power gain # 0 = board does not override the ASPM and CLKREQ settings 1 = board overrides the ASPM and CLKREQ settings # 0 = board is not a BCM94321mc123 board 1 = board is a BCM94321mc123 board (unused by S/W) # 0 = board uses SECI Bluetooth coexistence 1 = board uses 3-wire Bluetooth coexistence # --- # 0 = BCM94321mcm93 uses SiGe FEM 1 = BCM94321mcm93 uses Skyworks FEM # (for BCM94321mcm93 and BCM94321coex boards only) # 0 = no workaround for clock harmonic spurs 1 = use the workaround for clock-harmonic spurs # 0 = use normal 2.4GHz band PLL settings 1 = use alternate 2.4GHz band PLL settings # (4322x and 4716/17/18 only) # 0 = Normal LED drive (full push-pull) 1 = Drive the LED outputs as open-drain # (43224 only) # --- # 0 = enable TX diversity for 11b frames 1 = Transmit 11b frames only on antenna 0 # 0 = no WAR to reduce/avoid clock harmonic spurs in 2G band 1 = enable WAR to reduce/avoid clock harmonic spurs in 2G band # 0 = do not transmit 11b frames using all TX cores 1 = transmit 11b frames using all TX cores # (TX diversity enabled or not by bit 12) (no TX diversity) # 0 = use normal filter settings for 2.4GHz bandedge channels 1 = use alternate filter settings for 2.4GHz bandedge channels # (4716, 4717, 4718, 5357, 5358, and 47186 internal PAs only) # --- # 0 = do not use 200kHz PLL bandwidth for 2G band 1 = use 200kHz PLL bandwidth for 2G band # 0 = GPAIO pin is not connected to 3.3V 1 = GPAIO pin is connected to 3.3V # (43226 only) # 0 = for external PAs, use external TSSI for TX IQCAL 1 = use internal envelope detector for TX IQCAL even with external PAs # (4322x and 4716/17/18 only) # 0 = can turn off the buffered crystal output from the radio 1 = keep the buffered crystal output from radio ON # --- # 0 = control 2GHz PAs with the digital PA control signals 1 = control 2GHz PAs with the analog PA VERF LDO outputs # 0 = control 5GHz PAs with the digital PA control signals 1 = control 5GHz PAs with the analog PA VERF LDO outputs # 0 = normal external LNA and TR switch controls 1 = For AZW designs, 2GHz gmode_elna_gain conrols the TR switch # (4329 only) # 0 = no antenna sharing with Bluetooth 1 = share the chain 0 antenna with Bluetooth # --- # 0 = no adjustment to the temperature threshold, "tempthresh" 1 = chip can sustain a higher tempsense threshold # add the value of parameter "tempoffset" to "tempthresh" # 0 = use standard 4-wire Bluetooth coexistance 1 = use standard 3-wire Bluetooth coexistance only. 4-wire not supported # 0 = 4331 power savings mode enabled (use for STAs) 1 = 4331 power savings mode disabled (use for routers) # (4331 only) # 0 = no ucode powersave WAR 1 = enable ucade powersave WAR # (4331 only) # --- # 0 = enable dynamic Vmid in idle TSSI calibration 1 = disable dynamic Vmid in idle TSSI calibration # # (bits 29-31 are unused) # boardflags2=0x00000000 # sromrev tells the software what "version" of NVRAM is used. This is just for the CPU chip. The wireless chips will # their own sromrev settings. sromrev=8 # For 4707/8/9: Specify ARM clock frequency (in MHz) ONLY. All other dividers are fixed ratios of this (div2, dvi4). DDR clock is set separately. clkfreq=800,666 # frequency of the crystal driving the PLL, in kHz # Even if the chip does not support any other crystal frequency, this parameter must still be specified. xtalfreq=25000 # for 4707/8/9 # Only sdram_config is used. It is a 16-bit number. # Bits Definition # ----- ----------------------------------------------------------------------------------------------------------- # 15:11 Reserved # 10:8 Column Size: 000 = 2048 columns; 001 = 1024 columns; 010 = 512 columns # 7 0 = 16 bit wide data bus; 1 = 8 bit wide data bus # 6 0 = 4 banks; 1 = 8 banks # NOTE: For 4 banks, columns can be 512, 1024, or 2048. For 8 banks, columns can only be 1024 or 2048. # 5:3 Reserved # 2:0 CAS latency: 011 = CL is 3; 100 = CL is 4; 101 = CL is 5; 110 = CL is 6; 111 = CL is 7; all others reserved # # Set 64MB (1Gbit) of DDR3 (DDR64X16), x16, 8 banks, CL=7 sdram_config=0x0149 # For 4707/8/9 - Required to set the DDR PHY clock correctly *before* the boot code is copied to DDR. Since the NVRAM # parsing is done after the execution is passed to DDR, the DDR PHY clock must be reconfigured from its default of # 333MHz. The "sdram_ncdl" parameter is stored in a fixed location in the CFE space, so the bootloader can read it while # still executing from flash. This is a limitation of the way the DDR PHY clock reconfiguration occurs on 4707/8/9 parts. # # Set DDR3 clock of 533MHz (800MT/s) for RT-AC68U #sdram_ncdl=533 # Configure the internal GMAC port to talk to the internal Ethernet switch # et0phyaddr is the PHY address of the PHY chip or the address of the MII/RvMII/GMII/RGMII port of the switch chip. et0phyaddr=30 # et0mcdport is which MDC/MDIO port is used to connect to the PHY/Switch chip. Only 4703/4704 has two MIIs, so this # parameter is nearly always "0". et0mdcport=0 # Set the MAC address of the Ethernet ports # From 9/2009 onward MAC addresses have changed from that 8/16 split to a 12/12 split, so the new macmid will be # based on MAC addresses with the following format: # 47 40 39 32 31 24 23 16 15 8 7 0 # | 00 | 90 | 4C | XX | XY | YY | # where the low 24 bits are evenly split into 4096 interface/ boardtypes and 4096 serial numbers. The low nibble of # XXX cannot be 0, since that corresponds to an old style MAC address, and macmid will correspond to bits 23:12, so # its easy to differentiate them from the old ones. # # The new "macmid" values will start at 1 and go up to 0xFFF, skipping those that have the low nibble as 0 and the # ones with the patterns 0x04Ex and 0x04Fx (These restrictions are enforced in the code). To form the mac address, # the whole OUI (00:90:4C) will be prepended to those values and 12 bits of serial number will be appended. # # A new-style macmid: # BCM947186nrh 0x008 # # For router boards, nvserial now defines a new variable: "maclo12" # so nvram text files for new boards will have to define the MAC address like this (for a macmid 0x008): # et0macaddr=00:90:4C:00:8${maclo12} # instead of the previous way: # et0macaddr=00:90:4C:FC:${maclo} # # Set the MAC address of the Ethernet ports # Reference Board macmid # --------------- --------- # BCM94704agr 4C:4E (1st MII) # BCM94704agr 4C:4F (2nd MII) # BCM94712ap 4C:68 # BCM94712agr 4C:76 # BCM95350gr 4C:7D # BCM94712lgr 4C:88 # BCM95352gr 4C:91 # BCM95352grl 4C:91 # BCM95351agr 4C:9C # BCM94704mpcb 4C:A0 (1st MII) # BCM94704mpcb 4C:A1 (2nd MII) # BCM94704nr 4C:A0 (1st MII) # BCM94704nr 4C:A1 (2nd MII) # BCM95352elgr 4C:AD # BCM94705gmp 4C:B9 # BCM95354gr 4C:C0 # BCM94703nr 4C:F0 (1st MII) # BCM94703nr 4C:F1 (2nd MII) # BCM94716nr2 4C:04 # BCM94717ap 4C:06 # BCM94718nr 4C:08 # BCM94717mii 4C:2D # BCM94717cbtnr 4C:2F # BCM95356ssnr 4C:36 # BCM94718nrl 4C:56 # BCM94718nrx 4C:57 # BCM947186nrh 00:8 # BCM95357nr 01:2 # BCM95357nrepa 01:4 # BCM95358nr2 01:6 # BCM947186nr2 01:E # BCM95357nr2epa 01:4 # BCM95357cbtnr2epa 02:8 # BCM94718nrlfmc 05:6 # BCM94706nr 08:A # BCM94706nrh 0B:4 # BCM94706Lmiih5 0C:8 # BCM94706nr2hmc 0D:B # BCM94708r 0F:F # BCM94709r 11:2 # # New style: # The value of 00:90:4C:0F:F is for a BCM94708r reference design. # The "maclo12" part is filled in by the nvserial program. et0macaddr=00:90:4C:0F:F${maclo12} # Ethernet switch config (vlan0:LAN, vlan1:WAN) # WAN is on port 0, LAN is on ports 1-4. Port 5 is the MAC interface to the external switch or switch core. # It MUST be present on all VLANs. The "*" means to enable this group for CFE use. Only one VLAN can have this, # typically the LAN. 5325E/F and all internal switch cores use "5" for the MII port. 5395, 5397, and 53115 all use # "8" for the MII/GMII/RGMII port number. # NOTE: All packets on vlan1 (LAN) are tagged as such. # vlan1 is the LAN. vlan1ports=1 2 3 4 5* vlan1hwname=et0 # vlan2 is the WAN. The "u" configures the switch to not add vlan tags for packets to/from the # WAN port. A "t" (or nothing) in place of the "u" will configure the switch to add vlan tags for packets # to/from the WAN port. Also see note under "wandevs". vlan2ports=0 5u vlan2hwname=et0 # If the board is a dual band design the second wireless interface (usually the "a" band) # will come up as a second device. But we have to tell the software to hook to this # second wireless interface named "wl1". So set "landevs=vlan1 wl0 wl1". # Else, just use the standard configuration of "landevs=vlan1 wl0". landevs=vlan1 wl0 wl1 # The WAN port is almost always on an Ethernet port so use the normal config. If the WAN # port is not an Ethernet port, then this parameter must be changed accordingly. # NOTE: If WAN packets are vlan tagged, then must use "vlan2" in place of "et0". # For the default case of no WAN vlan tags, then must use "et0". # NOTE: If the board does not have a WAN port then must use "wandevs=". # WAN port is on eth0. wandevs=et0 # Set default IP address and net mask for the router. lan_ipaddr=192.168.1.1 lan_netmask=255.255.255.0 # If the board supports WPS, then these parameters tell the software # which GPIO is used for the WPS pushbutton and which is used for the WPS LED indicator. #gpio6=wps_led gpio7=wps_button # Set a short delay on boot so the CFE delays a bit before loading Linux. Allows easier S/W updates. boot_wait=on # If boot_wait is on, then "wait_time" sets the wait time from 3 to 20 seconds. wait_time=1 # The reset button is on GPIO 11. It MUST be active low, or the software will have to be modified. reset_gpio=11 # If the board has a USB power control chip, then the parameter "gpioX=usbportY" is used to tell # the USB driver code that it needs to set that GPIO HIGH to turn on power to that USB port. # "X" is the GPIO number, 0-31. "Y" is the USB port number, starting at "1". gpio9=usbport1 #gpio10=usbport2 #gpio12=43217enable #gpio13=4352enable # Watchdog timer in ms (0 will disable), 3000ms is minimum. 5592ms is maximum. watchdog=0 #4360_2G nvram devpath0=pci/1/1 0:venid=0x14E4 0:sromrev=11 0:boardflags=0x00001000 0:boardflags2=0x00100002 0:boardflags3=0x00000003 0:xtalfreq=40000 0:devid=0x43A1 0:macaddr=00:90:4C:0E:C${maclo12} 0:aa2g=7 0:agbg0=0 0:agbg1=0 0:agbg2=0 0:txchain=7 0:rxchain=7 0:antswitch=0 0:femctrl=3 0:gainctrlsph=0 0:papdcap2g=0 0:tworangetssi2g=0 0:pdgain2g=4 0:epagain2g=0 0:tssiposslope2g=1 # 2GHz RX Gain Parameteters 0:rxgains2gelnagaina0=6 0:rxgains2gelnagaina1=6 0:rxgains2gelnagaina2=6 0:rxgains2gtrelnabypa0=1 0:rxgains2gtrelnabypa1=1 0:rxgains2gtrelnabypa2=1 0:rxgains2gtrisoa0=11 0:rxgains2gtrisoa1=11 0:rxgains2gtrisoa2=11 # 2GHz TX Parameters 0:maxp2ga0=106 0:maxp2ga1=106 0:maxp2ga2=106 0:pa2ga0=0xff4a,0x1c3c,0xfca8 0:pa2ga1=0xff49,0x1b5a,0xfcb9 0:pa2ga2=0xff4e,0x1c8d,0xfcaa # Power-Per-Rate settings: 0:cckbw202gpo=0 0:cckbw20ul2gpo=0 0:mcsbw202gpo=0x88653320 0:mcsbw402gpo=0x88653320 0:dot11agofdmhrbw202gpo=0x6533 0:ofdmlrbw202gpo=0 0:sb20in40hrpo=0 0:sb20in40lrpo=0 0:dot11agduphrpo=0 0:dot11agduplrpo=0 #2G TX beamforming parameters 0:rpcal2g=0xffff # Regulatory parameters 0:ccode=US 0:regrev=0 0:sar2g=18 #LED behavior settings 0:ledbh10=7 #0:leddc=0xFFFF #temperature setting #0:temps_period=5 #0:tempthresh=120 #0:temps_hysteresis=5 #0:phycal_tempdelta=0 #0:tempoffset=0 #4360_5G nvram devpath1=pci/2/1 1:venid=0x14E4 1:sromrev=11 1:boardflags=0x30000000 1:boardflags2=0x00300002 1:boardflags3=0x0 1:xtalfreq=40000 1:devid=0x43A2 1:macaddr=00:90:4C:11:4${maclo12} 1:aa5g=7 1:aga0=0 1:aga1=0 1:aga2=0 1:txchain=7 1:rxchain=7 1:antswitch=0 1:femctrl=3 1:subband5gver=4 1:gainctrlsph=0 1:papdcap5g=0 1:tworangetssi5g=0 1:pdgain5g=4 1:epagain5g=0 1:tssiposslope5g=1 # 5GHz RX Gain Parameteters 1:rxgains5gelnagaina0=2 1:rxgains5gtrelnabypa0=1 1:rxgains5gtrisoa0=7 1:rxgains5gmelnagaina0=2 1:rxgains5gmtrelnabypa0=1 1:rxgains5gmtrisoa0=7 1:rxgains5ghelnagaina0=3 1:rxgains5ghtrelnabypa0=1 1:rxgains5ghtrisoa0=8 1:rxgains5gelnagaina1=2 1:rxgains5gtrelnabypa1=1 1:rxgains5gtrisoa1=9 1:rxgains5gmelnagaina1=2 1:rxgains5gmtrelnabypa1=1 1:rxgains5gmtrisoa1=7 1:rxgains5ghelnagaina1=3 1:rxgains5ghtrelnabypa1=1 1:rxgains5ghtrisoa1=7 1:rxgains5gelnagaina2=2 1:rxgains5gtrelnabypa2=1 1:rxgains5gtrisoa2=8 1:rxgains5gmelnagaina2=2 1:rxgains5gmtrelnabypa2=1 1:rxgains5gmtrisoa2=7 1:rxgains5ghelnagaina2=3 1:rxgains5ghtrelnabypa2=1 1:rxgains5ghtrisoa2=8 # 5GHz TX Parameters 1:maxp5ga0=106,106,106,106 1:pa5ga0=0xff38,0x1d35,0xfc7f,0xff33,0x1d3c,0xfc75,0xff39,0x1cf4,0xfc82,0xff39,0x1ca2,0xfc89 1:maxp5ga1=106,106,106,106 1:pa5ga1=0xff3e,0x1d3e,0xfc84,0xff3d,0x1d8b,0xfc76,0xff44,0x1d9d,0xfc7c,0xff3e,0x1c72,0xfc96 1:maxp5ga2=106,106,106,106 1:pa5ga2=0xff3b,0x1dd6,0xfc6d,0xff36,0x1d95,0xfc76,0xff38,0x1d82,0xfc73,0xff41,0x1d1b,0xfc90 1:pdoffset40ma0=0x0 1:pdoffset40ma1=0x0 1:pdoffset40ma2=0x0 1:pdoffset80ma0=0x0000 1:pdoffset80ma1=0x0000 1:pdoffset80ma2=0x0000 # Power-Per-Rate settings: 1:mcsbw205glpo=0x88653320 1:mcsbw405glpo=0x88653320 1:mcsbw805glpo=0x88653320 1:mcsbw1605glpo=0 1:mcsbw205gmpo=0x88653320 1:mcsbw405gmpo=0x88653320 1:mcsbw805gmpo=0x88653320 1:mcsbw1605gmpo=0 1:mcsbw205ghpo=0x88653320 1:mcsbw405ghpo=0x88653320 1:mcsbw805ghpo=0x88653320 1:mcsbw1605ghpo=0 1:mcslr5glpo=0 1:mcslr5gmpo=0 1:mcslr5ghpo=0 1:sb20in40hrpo=0 1:sb20in80and160hr5glpo=0 1:sb40and80hr5glpo=0 1:sb20in80and160hr5gmpo=0 1:sb40and80hr5gmpo=0 1:sb20in80and160hr5ghpo=0 1:sb40and80hr5ghpo=0 1:sb20in40lrpo=0 1:sb20in80and160lr5glpo=0 1:sb40and80lr5glpo=0 1:sb20in80and160lr5gmpo=0 1:sb40and80lr5gmpo=0 1:sb20in80and160lr5ghpo=0 1:sb40and80lr5ghpo=0 1:dot11agduphrpo=0 1:dot11agduplrpo=0 #5G TX beamforming parameters 1:rpcal5gb0=0xffff 1:rpcal5gb1=0xffff 1:rpcal5gb2=0xffff 1:rpcal5gb3=0xffff # Regulatory parameters 1:ccode=US 1:regrev=0 1:sar5g=15 # LED behavior 1:ledbh10=7 #1:leddc=0xFFFF # Temperature parameters #1:temps_period=5 #1:tempthresh=120 #1:temps_hysteresis=5 #1:phycal_tempdelta=0 #1:tempoffset=0 # Bootloader version bl_version=1.0.2.2 # for NAND flash bootflags=1 # WPS AP PIN code secret_code=12345670 # ODM Product ID odmpid=ASUS # Model Name model=RT-AC68U # others ATEMODE=1 HW_ver=170 nospare=1