|music
HIGH <= F_CODE:inst2.H
CLK50MHz => pll20:inst7.inclk0
SPK_KX <= inst5.DB_MAX_OUTPUT_PORT_TYPE
LED[0] <= F_CODE:inst2.CODE[0]
LED[1] <= F_CODE:inst2.CODE[1]
LED[2] <= F_CODE:inst2.CODE[2]
LED[3] <= F_CODE:inst2.CODE[3]


|music|F_CODE:inst2
INX[0] => Decoder0.IN3
INX[0] => Decoder1.IN2
INX[1] => Decoder0.IN2
INX[1] => Decoder1.IN1
INX[2] => Decoder0.IN1
INX[3] => Decoder0.IN0
INX[3] => Decoder1.IN0
CODE[0] <= WideOr11.DB_MAX_OUTPUT_PORT_TYPE
CODE[1] <= WideOr10.DB_MAX_OUTPUT_PORT_TYPE
CODE[2] <= WideOr9.DB_MAX_OUTPUT_PORT_TYPE
CODE[3] <= <GND>
H <= WideOr12.DB_MAX_OUTPUT_PORT_TYPE
TO[0] <= WideOr8.DB_MAX_OUTPUT_PORT_TYPE
TO[1] <= WideOr7.DB_MAX_OUTPUT_PORT_TYPE
TO[2] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
TO[3] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
TO[4] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
TO[5] <= TO.DB_MAX_OUTPUT_PORT_TYPE
TO[6] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
TO[7] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
TO[8] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
TO[9] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
TO[10] <= TO.DB_MAX_OUTPUT_PORT_TYPE


|music|rom:inst1
address[0] => address[0].IN1
address[1] => address[1].IN1
address[2] => address[2].IN1
address[3] => address[3].IN1
address[4] => address[4].IN1
address[5] => address[5].IN1
address[6] => address[6].IN1
address[7] => address[7].IN1
inclock => inclock.IN1
q[0] <= altsyncram:altsyncram_component.q_a
q[1] <= altsyncram:altsyncram_component.q_a
q[2] <= altsyncram:altsyncram_component.q_a
q[3] <= altsyncram:altsyncram_component.q_a


|music|rom:inst1|altsyncram:altsyncram_component
wren_a => ~NO_FANOUT~
rden_a => ~NO_FANOUT~
wren_b => ~NO_FANOUT~
rden_b => ~NO_FANOUT~
data_a[0] => ~NO_FANOUT~
data_a[1] => ~NO_FANOUT~
data_a[2] => ~NO_FANOUT~
data_a[3] => ~NO_FANOUT~
data_b[0] => ~NO_FANOUT~
address_a[0] => altsyncram_b8b1:auto_generated.address_a[0]
address_a[1] => altsyncram_b8b1:auto_generated.address_a[1]
address_a[2] => altsyncram_b8b1:auto_generated.address_a[2]
address_a[3] => altsyncram_b8b1:auto_generated.address_a[3]
address_a[4] => altsyncram_b8b1:auto_generated.address_a[4]
address_a[5] => altsyncram_b8b1:auto_generated.address_a[5]
address_a[6] => altsyncram_b8b1:auto_generated.address_a[6]
address_a[7] => altsyncram_b8b1:auto_generated.address_a[7]
address_b[0] => ~NO_FANOUT~
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_b8b1:auto_generated.clock0
clock1 => ~NO_FANOUT~
clocken0 => ~NO_FANOUT~
clocken1 => ~NO_FANOUT~
clocken2 => ~NO_FANOUT~
clocken3 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= altsyncram_b8b1:auto_generated.q_a[0]
q_a[1] <= altsyncram_b8b1:auto_generated.q_a[1]
q_a[2] <= altsyncram_b8b1:auto_generated.q_a[2]
q_a[3] <= altsyncram_b8b1:auto_generated.q_a[3]
q_b[0] <= <GND>
eccstatus[0] <= <GND>
eccstatus[1] <= <GND>
eccstatus[2] <= <GND>


|music|rom:inst1|altsyncram:altsyncram_component|altsyncram_b8b1:auto_generated
address_a[0] => altsyncram_5oc2:altsyncram1.address_a[0]
address_a[1] => altsyncram_5oc2:altsyncram1.address_a[1]
address_a[2] => altsyncram_5oc2:altsyncram1.address_a[2]
address_a[3] => altsyncram_5oc2:altsyncram1.address_a[3]
address_a[4] => altsyncram_5oc2:altsyncram1.address_a[4]
address_a[5] => altsyncram_5oc2:altsyncram1.address_a[5]
address_a[6] => altsyncram_5oc2:altsyncram1.address_a[6]
address_a[7] => altsyncram_5oc2:altsyncram1.address_a[7]
clock0 => altsyncram_5oc2:altsyncram1.clock0
q_a[0] <= altsyncram_5oc2:altsyncram1.q_a[0]
q_a[1] <= altsyncram_5oc2:altsyncram1.q_a[1]
q_a[2] <= altsyncram_5oc2:altsyncram1.q_a[2]
q_a[3] <= altsyncram_5oc2:altsyncram1.q_a[3]


|music|rom:inst1|altsyncram:altsyncram_component|altsyncram_b8b1:auto_generated|altsyncram_5oc2:altsyncram1
address_a[0] => ram_block3a0.PORTAADDR
address_a[0] => ram_block3a1.PORTAADDR
address_a[0] => ram_block3a2.PORTAADDR
address_a[0] => ram_block3a3.PORTAADDR
address_a[1] => ram_block3a0.PORTAADDR1
address_a[1] => ram_block3a1.PORTAADDR1
address_a[1] => ram_block3a2.PORTAADDR1
address_a[1] => ram_block3a3.PORTAADDR1
address_a[2] => ram_block3a0.PORTAADDR2
address_a[2] => ram_block3a1.PORTAADDR2
address_a[2] => ram_block3a2.PORTAADDR2
address_a[2] => ram_block3a3.PORTAADDR2
address_a[3] => ram_block3a0.PORTAADDR3
address_a[3] => ram_block3a1.PORTAADDR3
address_a[3] => ram_block3a2.PORTAADDR3
address_a[3] => ram_block3a3.PORTAADDR3
address_a[4] => ram_block3a0.PORTAADDR4
address_a[4] => ram_block3a1.PORTAADDR4
address_a[4] => ram_block3a2.PORTAADDR4
address_a[4] => ram_block3a3.PORTAADDR4
address_a[5] => ram_block3a0.PORTAADDR5
address_a[5] => ram_block3a1.PORTAADDR5
address_a[5] => ram_block3a2.PORTAADDR5
address_a[5] => ram_block3a3.PORTAADDR5
address_a[6] => ram_block3a0.PORTAADDR6
address_a[6] => ram_block3a1.PORTAADDR6
address_a[6] => ram_block3a2.PORTAADDR6
address_a[6] => ram_block3a3.PORTAADDR6
address_a[7] => ram_block3a0.PORTAADDR7
address_a[7] => ram_block3a1.PORTAADDR7
address_a[7] => ram_block3a2.PORTAADDR7
address_a[7] => ram_block3a3.PORTAADDR7
address_b[0] => ram_block3a0.PORTBADDR
address_b[0] => ram_block3a1.PORTBADDR
address_b[0] => ram_block3a2.PORTBADDR
address_b[0] => ram_block3a3.PORTBADDR
address_b[1] => ram_block3a0.PORTBADDR1
address_b[1] => ram_block3a1.PORTBADDR1
address_b[1] => ram_block3a2.PORTBADDR1
address_b[1] => ram_block3a3.PORTBADDR1
address_b[2] => ram_block3a0.PORTBADDR2
address_b[2] => ram_block3a1.PORTBADDR2
address_b[2] => ram_block3a2.PORTBADDR2
address_b[2] => ram_block3a3.PORTBADDR2
address_b[3] => ram_block3a0.PORTBADDR3
address_b[3] => ram_block3a1.PORTBADDR3
address_b[3] => ram_block3a2.PORTBADDR3
address_b[3] => ram_block3a3.PORTBADDR3
address_b[4] => ram_block3a0.PORTBADDR4
address_b[4] => ram_block3a1.PORTBADDR4
address_b[4] => ram_block3a2.PORTBADDR4
address_b[4] => ram_block3a3.PORTBADDR4
address_b[5] => ram_block3a0.PORTBADDR5
address_b[5] => ram_block3a1.PORTBADDR5
address_b[5] => ram_block3a2.PORTBADDR5
address_b[5] => ram_block3a3.PORTBADDR5
address_b[6] => ram_block3a0.PORTBADDR6
address_b[6] => ram_block3a1.PORTBADDR6
address_b[6] => ram_block3a2.PORTBADDR6
address_b[6] => ram_block3a3.PORTBADDR6
address_b[7] => ram_block3a0.PORTBADDR7
address_b[7] => ram_block3a1.PORTBADDR7
address_b[7] => ram_block3a2.PORTBADDR7
address_b[7] => ram_block3a3.PORTBADDR7
clock0 => ram_block3a0.CLK0
clock0 => ram_block3a1.CLK0
clock0 => ram_block3a2.CLK0
clock0 => ram_block3a3.CLK0
clock1 => ram_block3a0.CLK1
clock1 => ram_block3a1.CLK1
clock1 => ram_block3a2.CLK1
clock1 => ram_block3a3.CLK1
data_b[0] => ram_block3a0.PORTBDATAIN
data_b[1] => ram_block3a1.PORTBDATAIN
data_b[2] => ram_block3a2.PORTBDATAIN
data_b[3] => ram_block3a3.PORTBDATAIN
q_a[0] <= ram_block3a0.PORTADATAOUT
q_a[1] <= ram_block3a1.PORTADATAOUT
q_a[2] <= ram_block3a2.PORTADATAOUT
q_a[3] <= ram_block3a3.PORTADATAOUT
q_b[0] <= ram_block3a0.PORTBDATAOUT
q_b[1] <= ram_block3a1.PORTBDATAOUT
q_b[2] <= ram_block3a2.PORTBDATAOUT
q_b[3] <= ram_block3a3.PORTBDATAOUT
wren_b => ram_block3a0.PORTBWE
wren_b => ram_block3a1.PORTBWE
wren_b => ram_block3a2.PORTBWE
wren_b => ram_block3a3.PORTBWE


|music|rom:inst1|altsyncram:altsyncram_component|altsyncram_b8b1:auto_generated|sld_mod_ram_rom:mgl_prim2
tck_usr <= sld_jtag_endpoint_adapter:jtag_signal_adapter.adapted_tck
address[0] <= ram_rom_addr_reg[0].DB_MAX_OUTPUT_PORT_TYPE
address[1] <= ram_rom_addr_reg[1].DB_MAX_OUTPUT_PORT_TYPE
address[2] <= ram_rom_addr_reg[2].DB_MAX_OUTPUT_PORT_TYPE
address[3] <= ram_rom_addr_reg[3].DB_MAX_OUTPUT_PORT_TYPE
address[4] <= ram_rom_addr_reg[4].DB_MAX_OUTPUT_PORT_TYPE
address[5] <= ram_rom_addr_reg[5].DB_MAX_OUTPUT_PORT_TYPE
address[6] <= ram_rom_addr_reg[6].DB_MAX_OUTPUT_PORT_TYPE
address[7] <= ram_rom_addr_reg[7].DB_MAX_OUTPUT_PORT_TYPE
enable_write <= enable_write.DB_MAX_OUTPUT_PORT_TYPE
data_write[0] <= ram_rom_data_reg[0].DB_MAX_OUTPUT_PORT_TYPE
data_write[1] <= ram_rom_data_reg[1].DB_MAX_OUTPUT_PORT_TYPE
data_write[2] <= ram_rom_data_reg[2].DB_MAX_OUTPUT_PORT_TYPE
data_write[3] <= ram_rom_data_reg[3].DB_MAX_OUTPUT_PORT_TYPE
data_read[0] => ram_rom_data_reg.DATAB
data_read[1] => ram_rom_data_reg.DATAB
data_read[2] => ram_rom_data_reg.DATAB
data_read[3] => ram_rom_data_reg.DATAB
adapter_ready => ~NO_FANOUT~
adapter_valid => ~NO_FANOUT~
adapter_queue_size[0] => ~NO_FANOUT~
adapter_queue_size[1] => ~NO_FANOUT~
adapter_queue_size[2] => ~NO_FANOUT~
adapter_queue_size[3] => ~NO_FANOUT~
adapter_queue_size[4] => ~NO_FANOUT~
adapter_reset <= <GND>
sld_ready <= <GND>
sld_valid <= <GND>
clr_out <= sld_jtag_endpoint_adapter:jtag_signal_adapter.adapted_clr
raw_tck => sld_jtag_endpoint_adapter:jtag_signal_adapter.raw_tck
tdi => sld_jtag_endpoint_adapter:jtag_signal_adapter.tdi
usr1 => sld_jtag_endpoint_adapter:jtag_signal_adapter.usr1
jtag_state_cdr => sld_jtag_endpoint_adapter:jtag_signal_adapter.jtag_state_cdr
jtag_state_sdr => sld_jtag_endpoint_adapter:jtag_signal_adapter.jtag_state_sdr
jtag_state_e1dr => sld_jtag_endpoint_adapter:jtag_signal_adapter.jtag_state_e1dr
jtag_state_udr => sld_jtag_endpoint_adapter:jtag_signal_adapter.jtag_state_udr
jtag_state_uir => sld_jtag_endpoint_adapter:jtag_signal_adapter.jtag_state_uir
clr => sld_jtag_endpoint_adapter:jtag_signal_adapter.clr
ena => sld_jtag_endpoint_adapter:jtag_signal_adapter.ena
ena => bypass_reg_out.ENA
ir_in[0] => sld_jtag_endpoint_adapter:jtag_signal_adapter.ir_in[0]
ir_in[1] => sld_jtag_endpoint_adapter:jtag_signal_adapter.ir_in[1]
ir_in[2] => sld_jtag_endpoint_adapter:jtag_signal_adapter.ir_in[2]
ir_in[3] => sld_jtag_endpoint_adapter:jtag_signal_adapter.ir_in[3]
ir_in[4] => sld_jtag_endpoint_adapter:jtag_signal_adapter.ir_in[4]
ir_in[5] => sld_jtag_endpoint_adapter:jtag_signal_adapter.ir_in[5]
ir_in[6] => sld_jtag_endpoint_adapter:jtag_signal_adapter.ir_in[6]
ir_in[7] => sld_jtag_endpoint_adapter:jtag_signal_adapter.ir_in[7]
ir_out[0] <= sld_jtag_endpoint_adapter:jtag_signal_adapter.ir_out[0]
ir_out[1] <= sld_jtag_endpoint_adapter:jtag_signal_adapter.ir_out[1]
ir_out[2] <= sld_jtag_endpoint_adapter:jtag_signal_adapter.ir_out[2]
ir_out[3] <= sld_jtag_endpoint_adapter:jtag_signal_adapter.ir_out[3]
ir_out[4] <= sld_jtag_endpoint_adapter:jtag_signal_adapter.ir_out[4]
ir_out[5] <= sld_jtag_endpoint_adapter:jtag_signal_adapter.ir_out[5]
ir_out[6] <= sld_jtag_endpoint_adapter:jtag_signal_adapter.ir_out[6]
ir_out[7] <= sld_jtag_endpoint_adapter:jtag_signal_adapter.ir_out[7]
tdo <= sld_jtag_endpoint_adapter:jtag_signal_adapter.tdo


|music|rom:inst1|altsyncram:altsyncram_component|altsyncram_b8b1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_jtag_endpoint_adapter:jtag_signal_adapter
raw_tck => sld_jtag_endpoint_adapter_impl:sld_jtag_endpoint_adapter_impl_inst.raw_tck
raw_tms => sld_jtag_endpoint_adapter_impl:sld_jtag_endpoint_adapter_impl_inst.raw_tms
tdi => sld_jtag_endpoint_adapter_impl:sld_jtag_endpoint_adapter_impl_inst.tdi
vir_tdi => sld_jtag_endpoint_adapter_impl:sld_jtag_endpoint_adapter_impl_inst.vir_tdi
jtag_state_tlr => sld_jtag_endpoint_adapter_impl:sld_jtag_endpoint_adapter_impl_inst.jtag_state_tlr
jtag_state_rti => sld_jtag_endpoint_adapter_impl:sld_jtag_endpoint_adapter_impl_inst.jtag_state_rti
jtag_state_sdrs => sld_jtag_endpoint_adapter_impl:sld_jtag_endpoint_adapter_impl_inst.jtag_state_sdrs
jtag_state_cdr => sld_jtag_endpoint_adapter_impl:sld_jtag_endpoint_adapter_impl_inst.jtag_state_cdr
jtag_state_sdr => sld_jtag_endpoint_adapter_impl:sld_jtag_endpoint_adapter_impl_inst.jtag_state_sdr
jtag_state_e1dr => sld_jtag_endpoint_adapter_impl:sld_jtag_endpoint_adapter_impl_inst.jtag_state_e1dr
jtag_state_pdr => sld_jtag_endpoint_adapter_impl:sld_jtag_endpoint_adapter_impl_inst.jtag_state_pdr
jtag_state_e2dr => sld_jtag_endpoint_adapter_impl:sld_jtag_endpoint_adapter_impl_inst.jtag_state_e2dr
jtag_state_udr => sld_jtag_endpoint_adapter_impl:sld_jtag_endpoint_adapter_impl_inst.jtag_state_udr
jtag_state_sirs => sld_jtag_endpoint_adapter_impl:sld_jtag_endpoint_adapter_impl_inst.jtag_state_sirs
jtag_state_cir => sld_jtag_endpoint_adapter_impl:sld_jtag_endpoint_adapter_impl_inst.jtag_state_cir
jtag_state_sir => sld_jtag_endpoint_adapter_impl:sld_jtag_endpoint_adapter_impl_inst.jtag_state_sir
jtag_state_e1ir => sld_jtag_endpoint_adapter_impl:sld_jtag_endpoint_adapter_impl_inst.jtag_state_e1ir
jtag_state_pir => sld_jtag_endpoint_adapter_impl:sld_jtag_endpoint_adapter_impl_inst.jtag_state_pir
jtag_state_e2ir => sld_jtag_endpoint_adapter_impl:sld_jtag_endpoint_adapter_impl_inst.jtag_state_e2ir
jtag_state_uir => sld_jtag_endpoint_adapter_impl:sld_jtag_endpoint_adapter_impl_inst.jtag_state_uir
usr1 => sld_jtag_endpoint_adapter_impl:sld_jtag_endpoint_adapter_impl_inst.usr1
clr => sld_jtag_endpoint_adapter_impl:sld_jtag_endpoint_adapter_impl_inst.clr
ena => sld_jtag_endpoint_adapter_impl:sld_jtag_endpoint_adapter_impl_inst.ena
ir_in[0] => sld_jtag_endpoint_adapter_impl:sld_jtag_endpoint_adapter_impl_inst.ir_in[0]
ir_in[1] => sld_jtag_endpoint_adapter_impl:sld_jtag_endpoint_adapter_impl_inst.ir_in[1]
ir_in[2] => sld_jtag_endpoint_adapter_impl:sld_jtag_endpoint_adapter_impl_inst.ir_in[2]
ir_in[3] => sld_jtag_endpoint_adapter_impl:sld_jtag_endpoint_adapter_impl_inst.ir_in[3]
ir_in[4] => sld_jtag_endpoint_adapter_impl:sld_jtag_endpoint_adapter_impl_inst.ir_in[4]
ir_in[5] => sld_jtag_endpoint_adapter_impl:sld_jtag_endpoint_adapter_impl_inst.ir_in[5]
ir_in[6] => sld_jtag_endpoint_adapter_impl:sld_jtag_endpoint_adapter_impl_inst.ir_in[6]
ir_in[7] => sld_jtag_endpoint_adapter_impl:sld_jtag_endpoint_adapter_impl_inst.ir_in[7]
tdo <= sld_jtag_endpoint_adapter_impl:sld_jtag_endpoint_adapter_impl_inst.tdo
ir_out[0] <= sld_jtag_endpoint_adapter_impl:sld_jtag_endpoint_adapter_impl_inst.ir_out[0]
ir_out[1] <= sld_jtag_endpoint_adapter_impl:sld_jtag_endpoint_adapter_impl_inst.ir_out[1]
ir_out[2] <= sld_jtag_endpoint_adapter_impl:sld_jtag_endpoint_adapter_impl_inst.ir_out[2]
ir_out[3] <= sld_jtag_endpoint_adapter_impl:sld_jtag_endpoint_adapter_impl_inst.ir_out[3]
ir_out[4] <= sld_jtag_endpoint_adapter_impl:sld_jtag_endpoint_adapter_impl_inst.ir_out[4]
ir_out[5] <= sld_jtag_endpoint_adapter_impl:sld_jtag_endpoint_adapter_impl_inst.ir_out[5]
ir_out[6] <= sld_jtag_endpoint_adapter_impl:sld_jtag_endpoint_adapter_impl_inst.ir_out[6]
ir_out[7] <= sld_jtag_endpoint_adapter_impl:sld_jtag_endpoint_adapter_impl_inst.ir_out[7]
adapted_tck <= sld_jtag_endpoint_adapter_impl:sld_jtag_endpoint_adapter_impl_inst.adapted_tck
adapted_tms <= sld_jtag_endpoint_adapter_impl:sld_jtag_endpoint_adapter_impl_inst.adapted_tms
adapted_tdi <= sld_jtag_endpoint_adapter_impl:sld_jtag_endpoint_adapter_impl_inst.adapted_tdi
adapted_vir_tdi <= sld_jtag_endpoint_adapter_impl:sld_jtag_endpoint_adapter_impl_inst.adapted_vir_tdi
adapted_jtag_state_tlr <= sld_jtag_endpoint_adapter_impl:sld_jtag_endpoint_adapter_impl_inst.adapted_jtag_state_tlr
adapted_jtag_state_rti <= sld_jtag_endpoint_adapter_impl:sld_jtag_endpoint_adapter_impl_inst.adapted_jtag_state_rti
adapted_jtag_state_sdrs <= sld_jtag_endpoint_adapter_impl:sld_jtag_endpoint_adapter_impl_inst.adapted_jtag_state_sdrs
adapted_jtag_state_cdr <= sld_jtag_endpoint_adapter_impl:sld_jtag_endpoint_adapter_impl_inst.adapted_jtag_state_cdr
adapted_jtag_state_sdr <= sld_jtag_endpoint_adapter_impl:sld_jtag_endpoint_adapter_impl_inst.adapted_jtag_state_sdr
adapted_jtag_state_e1dr <= sld_jtag_endpoint_adapter_impl:sld_jtag_endpoint_adapter_impl_inst.adapted_jtag_state_e1dr
adapted_jtag_state_pdr <= sld_jtag_endpoint_adapter_impl:sld_jtag_endpoint_adapter_impl_inst.adapted_jtag_state_pdr
adapted_jtag_state_e2dr <= sld_jtag_endpoint_adapter_impl:sld_jtag_endpoint_adapter_impl_inst.adapted_jtag_state_e2dr
adapted_jtag_state_udr <= sld_jtag_endpoint_adapter_impl:sld_jtag_endpoint_adapter_impl_inst.adapted_jtag_state_udr
adapted_jtag_state_sirs <= sld_jtag_endpoint_adapter_impl:sld_jtag_endpoint_adapter_impl_inst.adapted_jtag_state_sirs
adapted_jtag_state_cir <= sld_jtag_endpoint_adapter_impl:sld_jtag_endpoint_adapter_impl_inst.adapted_jtag_state_cir
adapted_jtag_state_sir <= sld_jtag_endpoint_adapter_impl:sld_jtag_endpoint_adapter_impl_inst.adapted_jtag_state_sir
adapted_jtag_state_e1ir <= sld_jtag_endpoint_adapter_impl:sld_jtag_endpoint_adapter_impl_inst.adapted_jtag_state_e1ir
adapted_jtag_state_pir <= sld_jtag_endpoint_adapter_impl:sld_jtag_endpoint_adapter_impl_inst.adapted_jtag_state_pir
adapted_jtag_state_e2ir <= sld_jtag_endpoint_adapter_impl:sld_jtag_endpoint_adapter_impl_inst.adapted_jtag_state_e2ir
adapted_jtag_state_uir <= sld_jtag_endpoint_adapter_impl:sld_jtag_endpoint_adapter_impl_inst.adapted_jtag_state_uir
adapted_usr1 <= sld_jtag_endpoint_adapter_impl:sld_jtag_endpoint_adapter_impl_inst.adapted_usr1
adapted_clr <= sld_jtag_endpoint_adapter_impl:sld_jtag_endpoint_adapter_impl_inst.adapted_clr
adapted_ena <= sld_jtag_endpoint_adapter_impl:sld_jtag_endpoint_adapter_impl_inst.adapted_ena
adapted_ir_in[0] <= sld_jtag_endpoint_adapter_impl:sld_jtag_endpoint_adapter_impl_inst.adapted_ir_in[0]
adapted_ir_in[1] <= sld_jtag_endpoint_adapter_impl:sld_jtag_endpoint_adapter_impl_inst.adapted_ir_in[1]
adapted_ir_in[2] <= sld_jtag_endpoint_adapter_impl:sld_jtag_endpoint_adapter_impl_inst.adapted_ir_in[2]
adapted_ir_in[3] <= sld_jtag_endpoint_adapter_impl:sld_jtag_endpoint_adapter_impl_inst.adapted_ir_in[3]
adapted_ir_in[4] <= sld_jtag_endpoint_adapter_impl:sld_jtag_endpoint_adapter_impl_inst.adapted_ir_in[4]
adapted_ir_in[5] <= sld_jtag_endpoint_adapter_impl:sld_jtag_endpoint_adapter_impl_inst.adapted_ir_in[5]
adapted_ir_in[6] <= sld_jtag_endpoint_adapter_impl:sld_jtag_endpoint_adapter_impl_inst.adapted_ir_in[6]
adapted_ir_in[7] <= sld_jtag_endpoint_adapter_impl:sld_jtag_endpoint_adapter_impl_inst.adapted_ir_in[7]
adapted_tdo => sld_jtag_endpoint_adapter_impl:sld_jtag_endpoint_adapter_impl_inst.adapted_tdo
adapted_ir_out[0] => sld_jtag_endpoint_adapter_impl:sld_jtag_endpoint_adapter_impl_inst.adapted_ir_out[0]
adapted_ir_out[1] => sld_jtag_endpoint_adapter_impl:sld_jtag_endpoint_adapter_impl_inst.adapted_ir_out[1]
adapted_ir_out[2] => sld_jtag_endpoint_adapter_impl:sld_jtag_endpoint_adapter_impl_inst.adapted_ir_out[2]
adapted_ir_out[3] => sld_jtag_endpoint_adapter_impl:sld_jtag_endpoint_adapter_impl_inst.adapted_ir_out[3]
adapted_ir_out[4] => sld_jtag_endpoint_adapter_impl:sld_jtag_endpoint_adapter_impl_inst.adapted_ir_out[4]
adapted_ir_out[5] => sld_jtag_endpoint_adapter_impl:sld_jtag_endpoint_adapter_impl_inst.adapted_ir_out[5]
adapted_ir_out[6] => sld_jtag_endpoint_adapter_impl:sld_jtag_endpoint_adapter_impl_inst.adapted_ir_out[6]
adapted_ir_out[7] => sld_jtag_endpoint_adapter_impl:sld_jtag_endpoint_adapter_impl_inst.adapted_ir_out[7]


|music|rom:inst1|altsyncram:altsyncram_component|altsyncram_b8b1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_jtag_endpoint_adapter:jtag_signal_adapter|sld_jtag_endpoint_adapter_impl:sld_jtag_endpoint_adapter_impl_inst
raw_tck => adapted_tck.DATAIN
raw_tms => adapted_tms.DATAIN
tdi => adapted_tdi.DATAIN
vir_tdi => adapted_vir_tdi.DATAIN
jtag_state_tlr => adapted_jtag_state_tlr.DATAIN
jtag_state_rti => adapted_jtag_state_rti.DATAIN
jtag_state_sdrs => adapted_jtag_state_sdrs.DATAIN
jtag_state_cdr => adapted_jtag_state_cdr.DATAIN
jtag_state_sdr => adapted_jtag_state_sdr.DATAIN
jtag_state_e1dr => adapted_jtag_state_e1dr.DATAIN
jtag_state_pdr => adapted_jtag_state_pdr.DATAIN
jtag_state_e2dr => adapted_jtag_state_e2dr.DATAIN
jtag_state_udr => adapted_jtag_state_udr.DATAIN
jtag_state_sirs => adapted_jtag_state_sirs.DATAIN
jtag_state_cir => adapted_jtag_state_cir.DATAIN
jtag_state_sir => adapted_jtag_state_sir.DATAIN
jtag_state_e1ir => adapted_jtag_state_e1ir.DATAIN
jtag_state_pir => adapted_jtag_state_pir.DATAIN
jtag_state_e2ir => adapted_jtag_state_e2ir.DATAIN
jtag_state_uir => adapted_jtag_state_uir.DATAIN
usr1 => adapted_usr1.DATAIN
clr => adapted_clr.DATAIN
ena => adapted_ena.DATAIN
ir_in[0] => adapted_ir_in[0].DATAIN
ir_in[1] => adapted_ir_in[1].DATAIN
ir_in[2] => adapted_ir_in[2].DATAIN
ir_in[3] => adapted_ir_in[3].DATAIN
ir_in[4] => adapted_ir_in[4].DATAIN
ir_in[5] => adapted_ir_in[5].DATAIN
ir_in[6] => adapted_ir_in[6].DATAIN
ir_in[7] => adapted_ir_in[7].DATAIN
tdo <= adapted_tdo.DB_MAX_OUTPUT_PORT_TYPE
ir_out[0] <= adapted_ir_out[0].DB_MAX_OUTPUT_PORT_TYPE
ir_out[1] <= adapted_ir_out[1].DB_MAX_OUTPUT_PORT_TYPE
ir_out[2] <= adapted_ir_out[2].DB_MAX_OUTPUT_PORT_TYPE
ir_out[3] <= adapted_ir_out[3].DB_MAX_OUTPUT_PORT_TYPE
ir_out[4] <= adapted_ir_out[4].DB_MAX_OUTPUT_PORT_TYPE
ir_out[5] <= adapted_ir_out[5].DB_MAX_OUTPUT_PORT_TYPE
ir_out[6] <= adapted_ir_out[6].DB_MAX_OUTPUT_PORT_TYPE
ir_out[7] <= adapted_ir_out[7].DB_MAX_OUTPUT_PORT_TYPE
adapted_tck <= raw_tck.DB_MAX_OUTPUT_PORT_TYPE
adapted_tms <= raw_tms.DB_MAX_OUTPUT_PORT_TYPE
adapted_tdi <= tdi.DB_MAX_OUTPUT_PORT_TYPE
adapted_vir_tdi <= vir_tdi.DB_MAX_OUTPUT_PORT_TYPE
adapted_jtag_state_tlr <= jtag_state_tlr.DB_MAX_OUTPUT_PORT_TYPE
adapted_jtag_state_rti <= jtag_state_rti.DB_MAX_OUTPUT_PORT_TYPE
adapted_jtag_state_sdrs <= jtag_state_sdrs.DB_MAX_OUTPUT_PORT_TYPE
adapted_jtag_state_cdr <= jtag_state_cdr.DB_MAX_OUTPUT_PORT_TYPE
adapted_jtag_state_sdr <= jtag_state_sdr.DB_MAX_OUTPUT_PORT_TYPE
adapted_jtag_state_e1dr <= jtag_state_e1dr.DB_MAX_OUTPUT_PORT_TYPE
adapted_jtag_state_pdr <= jtag_state_pdr.DB_MAX_OUTPUT_PORT_TYPE
adapted_jtag_state_e2dr <= jtag_state_e2dr.DB_MAX_OUTPUT_PORT_TYPE
adapted_jtag_state_udr <= jtag_state_udr.DB_MAX_OUTPUT_PORT_TYPE
adapted_jtag_state_sirs <= jtag_state_sirs.DB_MAX_OUTPUT_PORT_TYPE
adapted_jtag_state_cir <= jtag_state_cir.DB_MAX_OUTPUT_PORT_TYPE
adapted_jtag_state_sir <= jtag_state_sir.DB_MAX_OUTPUT_PORT_TYPE
adapted_jtag_state_e1ir <= jtag_state_e1ir.DB_MAX_OUTPUT_PORT_TYPE
adapted_jtag_state_pir <= jtag_state_pir.DB_MAX_OUTPUT_PORT_TYPE
adapted_jtag_state_e2ir <= jtag_state_e2ir.DB_MAX_OUTPUT_PORT_TYPE
adapted_jtag_state_uir <= jtag_state_uir.DB_MAX_OUTPUT_PORT_TYPE
adapted_usr1 <= usr1.DB_MAX_OUTPUT_PORT_TYPE
adapted_clr <= clr.DB_MAX_OUTPUT_PORT_TYPE
adapted_ena <= ena.DB_MAX_OUTPUT_PORT_TYPE
adapted_ir_in[0] <= ir_in[0].DB_MAX_OUTPUT_PORT_TYPE
adapted_ir_in[1] <= ir_in[1].DB_MAX_OUTPUT_PORT_TYPE
adapted_ir_in[2] <= ir_in[2].DB_MAX_OUTPUT_PORT_TYPE
adapted_ir_in[3] <= ir_in[3].DB_MAX_OUTPUT_PORT_TYPE
adapted_ir_in[4] <= ir_in[4].DB_MAX_OUTPUT_PORT_TYPE
adapted_ir_in[5] <= ir_in[5].DB_MAX_OUTPUT_PORT_TYPE
adapted_ir_in[6] <= ir_in[6].DB_MAX_OUTPUT_PORT_TYPE
adapted_ir_in[7] <= ir_in[7].DB_MAX_OUTPUT_PORT_TYPE
adapted_tdo => tdo.DATAIN
adapted_ir_out[0] => ir_out[0].DATAIN
adapted_ir_out[1] => ir_out[1].DATAIN
adapted_ir_out[2] => ir_out[2].DATAIN
adapted_ir_out[3] => ir_out[3].DATAIN
adapted_ir_out[4] => ir_out[4].DATAIN
adapted_ir_out[5] => ir_out[5].DATAIN
adapted_ir_out[6] => ir_out[6].DATAIN
adapted_ir_out[7] => ir_out[7].DATAIN


|music|rom:inst1|altsyncram:altsyncram_component|altsyncram_b8b1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:name_gen:info_rom_sr
ROM_DATA[0] => Mux3.IN131
ROM_DATA[1] => Mux2.IN131
ROM_DATA[2] => Mux1.IN131
ROM_DATA[3] => Mux0.IN131
ROM_DATA[4] => Mux3.IN127
ROM_DATA[5] => Mux2.IN127
ROM_DATA[6] => Mux1.IN127
ROM_DATA[7] => Mux0.IN127
ROM_DATA[8] => Mux3.IN123
ROM_DATA[9] => Mux2.IN123
ROM_DATA[10] => Mux1.IN123
ROM_DATA[11] => Mux0.IN123
ROM_DATA[12] => Mux3.IN119
ROM_DATA[13] => Mux2.IN119
ROM_DATA[14] => Mux1.IN119
ROM_DATA[15] => Mux0.IN119
ROM_DATA[16] => Mux3.IN115
ROM_DATA[17] => Mux2.IN115
ROM_DATA[18] => Mux1.IN115
ROM_DATA[19] => Mux0.IN115
ROM_DATA[20] => Mux3.IN111
ROM_DATA[21] => Mux2.IN111
ROM_DATA[22] => Mux1.IN111
ROM_DATA[23] => Mux0.IN111
ROM_DATA[24] => Mux3.IN107
ROM_DATA[25] => Mux2.IN107
ROM_DATA[26] => Mux1.IN107
ROM_DATA[27] => Mux0.IN107
ROM_DATA[28] => Mux3.IN103
ROM_DATA[29] => Mux2.IN103
ROM_DATA[30] => Mux1.IN103
ROM_DATA[31] => Mux0.IN103
ROM_DATA[32] => Mux3.IN99
ROM_DATA[33] => Mux2.IN99
ROM_DATA[34] => Mux1.IN99
ROM_DATA[35] => Mux0.IN99
ROM_DATA[36] => Mux3.IN95
ROM_DATA[37] => Mux2.IN95
ROM_DATA[38] => Mux1.IN95
ROM_DATA[39] => Mux0.IN95
ROM_DATA[40] => Mux3.IN91
ROM_DATA[41] => Mux2.IN91
ROM_DATA[42] => Mux1.IN91
ROM_DATA[43] => Mux0.IN91
ROM_DATA[44] => Mux3.IN87
ROM_DATA[45] => Mux2.IN87
ROM_DATA[46] => Mux1.IN87
ROM_DATA[47] => Mux0.IN87
ROM_DATA[48] => Mux3.IN83
ROM_DATA[49] => Mux2.IN83
ROM_DATA[50] => Mux1.IN83
ROM_DATA[51] => Mux0.IN83
ROM_DATA[52] => Mux3.IN79
ROM_DATA[53] => Mux2.IN79
ROM_DATA[54] => Mux1.IN79
ROM_DATA[55] => Mux0.IN79
ROM_DATA[56] => Mux3.IN75
ROM_DATA[57] => Mux2.IN75
ROM_DATA[58] => Mux1.IN75
ROM_DATA[59] => Mux0.IN75
ROM_DATA[60] => Mux3.IN71
ROM_DATA[61] => Mux2.IN71
ROM_DATA[62] => Mux1.IN71
ROM_DATA[63] => Mux0.IN71
ROM_DATA[64] => Mux3.IN67
ROM_DATA[65] => Mux2.IN67
ROM_DATA[66] => Mux1.IN67
ROM_DATA[67] => Mux0.IN67
ROM_DATA[68] => Mux3.IN63
ROM_DATA[69] => Mux2.IN63
ROM_DATA[70] => Mux1.IN63
ROM_DATA[71] => Mux0.IN63
ROM_DATA[72] => Mux3.IN59
ROM_DATA[73] => Mux2.IN59
ROM_DATA[74] => Mux1.IN59
ROM_DATA[75] => Mux0.IN59
ROM_DATA[76] => Mux3.IN55
ROM_DATA[77] => Mux2.IN55
ROM_DATA[78] => Mux1.IN55
ROM_DATA[79] => Mux0.IN55
ROM_DATA[80] => Mux3.IN51
ROM_DATA[81] => Mux2.IN51
ROM_DATA[82] => Mux1.IN51
ROM_DATA[83] => Mux0.IN51
ROM_DATA[84] => Mux3.IN47
ROM_DATA[85] => Mux2.IN47
ROM_DATA[86] => Mux1.IN47
ROM_DATA[87] => Mux0.IN47
TCK => WORD_SR[0].CLK
TCK => WORD_SR[1].CLK
TCK => WORD_SR[2].CLK
TCK => WORD_SR[3].CLK
TCK => word_counter[0].CLK
TCK => word_counter[1].CLK
TCK => word_counter[2].CLK
TCK => word_counter[3].CLK
TCK => word_counter[4].CLK
SHIFT => word_counter.OUTPUTSELECT
SHIFT => word_counter.OUTPUTSELECT
SHIFT => word_counter.OUTPUTSELECT
SHIFT => word_counter.OUTPUTSELECT
SHIFT => word_counter.OUTPUTSELECT
SHIFT => WORD_SR.OUTPUTSELECT
SHIFT => WORD_SR.OUTPUTSELECT
SHIFT => WORD_SR.OUTPUTSELECT
SHIFT => WORD_SR.OUTPUTSELECT
UPDATE => clear_signal.IN0
USR1 => clear_signal.IN1
ENA => word_counter.OUTPUTSELECT
ENA => word_counter.OUTPUTSELECT
ENA => word_counter.OUTPUTSELECT
ENA => word_counter.OUTPUTSELECT
ENA => word_counter.OUTPUTSELECT
ENA => WORD_SR.OUTPUTSELECT
ENA => WORD_SR.OUTPUTSELECT
ENA => WORD_SR.OUTPUTSELECT
ENA => WORD_SR.OUTPUTSELECT
TDI => WORD_SR.DATAA
TDO <= WORD_SR[0].DB_MAX_OUTPUT_PORT_TYPE


|music|FDIV:inst4
CLK => FULL.CLK
CLK => Q1[0].CLK
CLK => Q1[1].CLK
CLK => Q1[2].CLK
CLK => Q1[3].CLK
CLK => Q1[4].CLK
CLK => Q1[5].CLK
CLK => Q1[6].CLK
CLK => Q1[7].CLK
CLK => Q1[8].CLK
PM <= FULL.DB_MAX_OUTPUT_PORT_TYPE


|music|pll20:inst7
inclk0 => sub_wire1[0].IN1
c0 <= altpll:altpll_component.clk
c1 <= altpll:altpll_component.clk


|music|pll20:inst7|altpll:altpll_component
inclk[0] => pll20_altpll:auto_generated.inclk[0]
inclk[1] => pll20_altpll:auto_generated.inclk[1]
fbin => ~NO_FANOUT~
pllena => ~NO_FANOUT~
clkswitch => ~NO_FANOUT~
areset => ~NO_FANOUT~
pfdena => ~NO_FANOUT~
clkena[0] => ~NO_FANOUT~
clkena[1] => ~NO_FANOUT~
clkena[2] => ~NO_FANOUT~
clkena[3] => ~NO_FANOUT~
clkena[4] => ~NO_FANOUT~
clkena[5] => ~NO_FANOUT~
extclkena[0] => ~NO_FANOUT~
extclkena[1] => ~NO_FANOUT~
extclkena[2] => ~NO_FANOUT~
extclkena[3] => ~NO_FANOUT~
scanclk => ~NO_FANOUT~
scanclkena => ~NO_FANOUT~
scanaclr => ~NO_FANOUT~
scanread => ~NO_FANOUT~
scanwrite => ~NO_FANOUT~
scandata => ~NO_FANOUT~
phasecounterselect[0] => ~NO_FANOUT~
phasecounterselect[1] => ~NO_FANOUT~
phasecounterselect[2] => ~NO_FANOUT~
phasecounterselect[3] => ~NO_FANOUT~
phaseupdown => ~NO_FANOUT~
phasestep => ~NO_FANOUT~
configupdate => ~NO_FANOUT~
fbmimicbidir <> <GND>
clk[0] <= clk[0].DB_MAX_OUTPUT_PORT_TYPE
clk[1] <= clk[1].DB_MAX_OUTPUT_PORT_TYPE
clk[2] <= clk[2].DB_MAX_OUTPUT_PORT_TYPE
clk[3] <= clk[3].DB_MAX_OUTPUT_PORT_TYPE
clk[4] <= clk[4].DB_MAX_OUTPUT_PORT_TYPE
extclk[0] <= <GND>
extclk[1] <= <GND>
extclk[2] <= <GND>
extclk[3] <= <GND>
clkbad[0] <= <GND>
clkbad[1] <= <GND>
enable1 <= <GND>
enable0 <= <GND>
activeclock <= <GND>
clkloss <= <GND>
locked <= <GND>
scandataout <= <GND>
scandone <= <GND>
sclkout0 <= <GND>
sclkout1 <= <GND>
phasedone <= <GND>
vcooverrange <= <GND>
vcounderrange <= <GND>
fbout <= <GND>
fref <= <GND>
icdrclk <= <GND>


|music|pll20:inst7|altpll:altpll_component|pll20_altpll:auto_generated
clk[0] <= pll1.CLK
clk[1] <= pll1.CLK1
clk[2] <= pll1.CLK2
clk[3] <= pll1.CLK3
clk[4] <= pll1.CLK4
inclk[0] => pll1.CLK
inclk[1] => pll1.CLK1


|music|CNT138T:inst
CLK => CNT[0].CLK
CLK => CNT[1].CLK
CLK => CNT[2].CLK
CLK => CNT[3].CLK
CLK => CNT[4].CLK
CLK => CNT[5].CLK
CLK => CNT[6].CLK
CLK => CNT[7].CLK
CNT8[0] <= CNT[0].DB_MAX_OUTPUT_PORT_TYPE
CNT8[1] <= CNT[1].DB_MAX_OUTPUT_PORT_TYPE
CNT8[2] <= CNT[2].DB_MAX_OUTPUT_PORT_TYPE
CNT8[3] <= CNT[3].DB_MAX_OUTPUT_PORT_TYPE
CNT8[4] <= CNT[4].DB_MAX_OUTPUT_PORT_TYPE
CNT8[5] <= CNT[5].DB_MAX_OUTPUT_PORT_TYPE
CNT8[6] <= CNT[6].DB_MAX_OUTPUT_PORT_TYPE
CNT8[7] <= CNT[7].DB_MAX_OUTPUT_PORT_TYPE


|music|SPKER:inst3
CLK => SPKS~reg0.CLK
CLK => CNT11[0].CLK
CLK => CNT11[1].CLK
CLK => CNT11[2].CLK
CLK => CNT11[3].CLK
CLK => CNT11[4].CLK
CLK => CNT11[5].CLK
CLK => CNT11[6].CLK
CLK => CNT11[7].CLK
CLK => CNT11[8].CLK
CLK => CNT11[9].CLK
CLK => CNT11[10].CLK
TN[0] => CNT11.DATAB
TN[1] => CNT11.DATAB
TN[2] => CNT11.DATAB
TN[3] => CNT11.DATAB
TN[4] => CNT11.DATAB
TN[5] => CNT11.DATAB
TN[6] => CNT11.DATAB
TN[7] => CNT11.DATAB
TN[8] => CNT11.DATAB
TN[9] => CNT11.DATAB
TN[10] => CNT11.DATAB
SPKS <= SPKS~reg0.DB_MAX_OUTPUT_PORT_TYPE