{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1685019431806 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition " "Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1685019431815 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu May 25 20:57:11 2023 " "Processing started: Thu May 25 20:57:11 2023" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1685019431815 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1685019431815 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off music -c music " "Command: quartus_map --read_settings_files=on --write_settings_files=off music -c music" {  } {  } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1685019431816 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1685019432202 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "16 16 " "Parallel compilation is enabled and will use 16 of the 16 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1685019432202 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "music.bdf 1 1 " "Found 1 design units, including 1 entities, in source file music.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 music " "Found entity 1: music" {  } { { "music.bdf" "" { Schematic "E:/FPGA/Hardware-based Music Performing Circuit Project/music.bdf" { } } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1685019440661 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1685019440661 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "output_files/cnt138t.v 1 1 " "Found 1 design units, including 1 entities, in source file output_files/cnt138t.v" { { "Info" "ISGN_ENTITY_NAME" "1 CNT138T " "Found entity 1: CNT138T" {  } { { "output_files/CNT138T.v" "" { Text "E:/FPGA/Hardware-based Music Performing Circuit Project/output_files/CNT138T.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1685019440663 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1685019440663 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rom.v 1 1 " "Found 1 design units, including 1 entities, in source file rom.v" { { "Info" "ISGN_ENTITY_NAME" "1 rom " "Found entity 1: rom" {  } { { "rom.v" "" { Text "E:/FPGA/Hardware-based Music Performing Circuit Project/rom.v" 39 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1685019440666 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1685019440666 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "f_code.v 1 1 " "Found 1 design units, including 1 entities, in source file f_code.v" { { "Info" "ISGN_ENTITY_NAME" "1 F_CODE " "Found entity 1: F_CODE" {  } { { "F_CODE.v" "" { Text "E:/FPGA/Hardware-based Music Performing Circuit Project/F_CODE.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1685019440668 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1685019440668 ""}
{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "SPKER.v(4) " "Verilog HDL information at SPKER.v(4): always construct contains both blocking and non-blocking assignments" {  } { { "SPKER.v" "" { Text "E:/FPGA/Hardware-based Music Performing Circuit Project/SPKER.v" 4 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "Analysis & Synthesis" 0 -1 1685019440670 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "spker.v 1 1 " "Found 1 design units, including 1 entities, in source file spker.v" { { "Info" "ISGN_ENTITY_NAME" "1 SPKER " "Found entity 1: SPKER" {  } { { "SPKER.v" "" { Text "E:/FPGA/Hardware-based Music Performing Circuit Project/SPKER.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1685019440671 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1685019440671 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "fdiv.v 1 1 " "Found 1 design units, including 1 entities, in source file fdiv.v" { { "Info" "ISGN_ENTITY_NAME" "1 FDIV " "Found entity 1: FDIV" {  } { { "FDIV.v" "" { Text "E:/FPGA/Hardware-based Music Performing Circuit Project/FDIV.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1685019440673 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1685019440673 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "pll20.v 1 1 " "Found 1 design units, including 1 entities, in source file pll20.v" { { "Info" "ISGN_ENTITY_NAME" "1 pll20 " "Found entity 1: pll20" {  } { { "pll20.v" "" { Text "E:/FPGA/Hardware-based Music Performing Circuit Project/pll20.v" 39 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1685019440676 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1685019440676 ""}
{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "DOUT FDIV.v(7) " "Verilog HDL Implicit Net warning at FDIV.v(7): created implicit net for \"DOUT\"" {  } { { "FDIV.v" "" { Text "E:/FPGA/Hardware-based Music Performing Circuit Project/FDIV.v" 7 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1685019440676 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "music " "Elaborating entity \"music\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1685019440717 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "F_CODE F_CODE:inst2 " "Elaborating entity \"F_CODE\" for hierarchy \"F_CODE:inst2\"" {  } { { "music.bdf" "inst2" { Schematic "E:/FPGA/Hardware-based Music Performing Circuit Project/music.bdf" { { 440 528 712 552 "inst2" "" } } } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1685019440735 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rom rom:inst1 " "Elaborating entity \"rom\" for hierarchy \"rom:inst1\"" {  } { { "music.bdf" "inst1" { Schematic "E:/FPGA/Hardware-based Music Performing Circuit Project/music.bdf" { { 424 264 480 552 "inst1" "" } } } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1685019440747 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram rom:inst1\|altsyncram:altsyncram_component " "Elaborating entity \"altsyncram\" for hierarchy \"rom:inst1\|altsyncram:altsyncram_component\"" {  } { { "rom.v" "altsyncram_component" { Text "E:/FPGA/Hardware-based Music Performing Circuit Project/rom.v" 81 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1685019440804 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "rom:inst1\|altsyncram:altsyncram_component " "Elaborated megafunction instantiation \"rom:inst1\|altsyncram:altsyncram_component\"" {  } { { "rom.v" "" { Text "E:/FPGA/Hardware-based Music Performing Circuit Project/rom.v" 81 0 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1685019440817 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "rom:inst1\|altsyncram:altsyncram_component " "Instantiated megafunction \"rom:inst1\|altsyncram:altsyncram_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_aclr_a NONE " "Parameter \"address_aclr_a\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1685019440817 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_input_a BYPASS " "Parameter \"clock_enable_input_a\" = \"BYPASS\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1685019440817 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_output_a BYPASS " "Parameter \"clock_enable_output_a\" = \"BYPASS\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1685019440817 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file ../music.mif " "Parameter \"init_file\" = \"../music.mif\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1685019440817 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone 10 LP " "Parameter \"intended_device_family\" = \"Cyclone 10 LP\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1685019440817 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=rom " "Parameter \"lpm_hint\" = \"ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=rom\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1685019440817 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altsyncram " "Parameter \"lpm_type\" = \"altsyncram\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1685019440817 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 256 " "Parameter \"numwords_a\" = \"256\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1685019440817 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode ROM " "Parameter \"operation_mode\" = \"ROM\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1685019440817 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_a NONE " "Parameter \"outdata_aclr_a\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1685019440817 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_a UNREGISTERED " "Parameter \"outdata_reg_a\" = \"UNREGISTERED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1685019440817 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 8 " "Parameter \"widthad_a\" = \"8\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1685019440817 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 4 " "Parameter \"width_a\" = \"4\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1685019440817 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 1 " "Parameter \"width_byteena_a\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1685019440817 ""}  } { { "rom.v" "" { Text "E:/FPGA/Hardware-based Music Performing Circuit Project/rom.v" 81 0 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1685019440817 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_b8b1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_b8b1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_b8b1 " "Found entity 1: altsyncram_b8b1" {  } { { "db/altsyncram_b8b1.tdf" "" { Text "E:/FPGA/Hardware-based Music Performing Circuit Project/db/altsyncram_b8b1.tdf" 27 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1685019440864 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1685019440864 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_b8b1 rom:inst1\|altsyncram:altsyncram_component\|altsyncram_b8b1:auto_generated " "Elaborating entity \"altsyncram_b8b1\" for hierarchy \"rom:inst1\|altsyncram:altsyncram_component\|altsyncram_b8b1:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "d:/intelfpga_lite/18.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1685019440864 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_5oc2.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_5oc2.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_5oc2 " "Found entity 1: altsyncram_5oc2" {  } { { "db/altsyncram_5oc2.tdf" "" { Text "E:/FPGA/Hardware-based Music Performing Circuit Project/db/altsyncram_5oc2.tdf" 27 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1685019440915 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1685019440915 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_5oc2 rom:inst1\|altsyncram:altsyncram_component\|altsyncram_b8b1:auto_generated\|altsyncram_5oc2:altsyncram1 " "Elaborating entity \"altsyncram_5oc2\" for hierarchy \"rom:inst1\|altsyncram:altsyncram_component\|altsyncram_b8b1:auto_generated\|altsyncram_5oc2:altsyncram1\"" {  } { { "db/altsyncram_b8b1.tdf" "altsyncram1" { Text "E:/FPGA/Hardware-based Music Performing Circuit Project/db/altsyncram_b8b1.tdf" 34 2 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1685019440916 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sld_mod_ram_rom rom:inst1\|altsyncram:altsyncram_component\|altsyncram_b8b1:auto_generated\|sld_mod_ram_rom:mgl_prim2 " "Elaborating entity \"sld_mod_ram_rom\" for hierarchy \"rom:inst1\|altsyncram:altsyncram_component\|altsyncram_b8b1:auto_generated\|sld_mod_ram_rom:mgl_prim2\"" {  } { { "db/altsyncram_b8b1.tdf" "mgl_prim2" { Text "E:/FPGA/Hardware-based Music Performing Circuit Project/db/altsyncram_b8b1.tdf" 35 2 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1685019441412 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "rom:inst1\|altsyncram:altsyncram_component\|altsyncram_b8b1:auto_generated\|sld_mod_ram_rom:mgl_prim2 " "Elaborated megafunction instantiation \"rom:inst1\|altsyncram:altsyncram_component\|altsyncram_b8b1:auto_generated\|sld_mod_ram_rom:mgl_prim2\"" {  } { { "db/altsyncram_b8b1.tdf" "" { Text "E:/FPGA/Hardware-based Music Performing Circuit Project/db/altsyncram_b8b1.tdf" 35 2 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1685019441435 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "rom:inst1\|altsyncram:altsyncram_component\|altsyncram_b8b1:auto_generated\|sld_mod_ram_rom:mgl_prim2 " "Instantiated megafunction \"rom:inst1\|altsyncram:altsyncram_component\|altsyncram_b8b1:auto_generated\|sld_mod_ram_rom:mgl_prim2\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "CVALUE 0000 " "Parameter \"CVALUE\" = \"0000\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1685019441435 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "IS_DATA_IN_RAM 1 " "Parameter \"IS_DATA_IN_RAM\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1685019441435 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "IS_READABLE 1 " "Parameter \"IS_READABLE\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1685019441435 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "NODE_NAME 1919905024 " "Parameter \"NODE_NAME\" = \"1919905024\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1685019441435 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "NUMWORDS 256 " "Parameter \"NUMWORDS\" = \"256\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1685019441435 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "SHIFT_COUNT_BITS 3 " "Parameter \"SHIFT_COUNT_BITS\" = \"3\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1685019441435 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTH_WORD 4 " "Parameter \"WIDTH_WORD\" = \"4\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1685019441435 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTHAD 8 " "Parameter \"WIDTHAD\" = \"8\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1685019441435 ""}  } { { "db/altsyncram_b8b1.tdf" "" { Text "E:/FPGA/Hardware-based Music Performing Circuit Project/db/altsyncram_b8b1.tdf" 35 2 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1685019441435 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sld_jtag_endpoint_adapter rom:inst1\|altsyncram:altsyncram_component\|altsyncram_b8b1:auto_generated\|sld_mod_ram_rom:mgl_prim2\|sld_jtag_endpoint_adapter:jtag_signal_adapter " "Elaborating entity \"sld_jtag_endpoint_adapter\" for hierarchy \"rom:inst1\|altsyncram:altsyncram_component\|altsyncram_b8b1:auto_generated\|sld_mod_ram_rom:mgl_prim2\|sld_jtag_endpoint_adapter:jtag_signal_adapter\"" {  } { { "sld_mod_ram_rom.vhd" "jtag_signal_adapter" { Text "d:/intelfpga_lite/18.1/quartus/libraries/megafunctions/sld_mod_ram_rom.vhd" 302 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1685019441565 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sld_jtag_endpoint_adapter_impl rom:inst1\|altsyncram:altsyncram_component\|altsyncram_b8b1:auto_generated\|sld_mod_ram_rom:mgl_prim2\|sld_jtag_endpoint_adapter:jtag_signal_adapter\|sld_jtag_endpoint_adapter_impl:sld_jtag_endpoint_adapter_impl_inst " "Elaborating entity \"sld_jtag_endpoint_adapter_impl\" for hierarchy \"rom:inst1\|altsyncram:altsyncram_component\|altsyncram_b8b1:auto_generated\|sld_mod_ram_rom:mgl_prim2\|sld_jtag_endpoint_adapter:jtag_signal_adapter\|sld_jtag_endpoint_adapter_impl:sld_jtag_endpoint_adapter_impl_inst\"" {  } { { "sld_jtag_endpoint_adapter.vhd" "sld_jtag_endpoint_adapter_impl_inst" { Text "d:/intelfpga_lite/18.1/quartus/libraries/megafunctions/sld_jtag_endpoint_adapter.vhd" 232 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1685019441698 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sld_rom_sr rom:inst1\|altsyncram:altsyncram_component\|altsyncram_b8b1:auto_generated\|sld_mod_ram_rom:mgl_prim2\|sld_rom_sr:\\ram_rom_logic_gen:name_gen:info_rom_sr " "Elaborating entity \"sld_rom_sr\" for hierarchy \"rom:inst1\|altsyncram:altsyncram_component\|altsyncram_b8b1:auto_generated\|sld_mod_ram_rom:mgl_prim2\|sld_rom_sr:\\ram_rom_logic_gen:name_gen:info_rom_sr\"" {  } { { "sld_mod_ram_rom.vhd" "\\ram_rom_logic_gen:name_gen:info_rom_sr" { Text "d:/intelfpga_lite/18.1/quartus/libraries/megafunctions/sld_mod_ram_rom.vhd" 828 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1685019441822 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "FDIV FDIV:inst4 " "Elaborating entity \"FDIV\" for hierarchy \"FDIV:inst4\"" {  } { { "music.bdf" "inst4" { Schematic "E:/FPGA/Hardware-based Music Performing Circuit Project/music.bdf" { { 64 648 784 144 "inst4" "" } } } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1685019441865 ""}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "DOUT FDIV.v(7) " "Verilog HDL or VHDL warning at FDIV.v(7): object \"DOUT\" assigned a value but never read" {  } { { "FDIV.v" "" { Text "E:/FPGA/Hardware-based Music Performing Circuit Project/FDIV.v" 7 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1685019441865 "|music|FDIV:inst4"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 9 FDIV.v(5) " "Verilog HDL assignment warning at FDIV.v(5): truncated value with size 32 to match size of target (9)" {  } { { "FDIV.v" "" { Text "E:/FPGA/Hardware-based Music Performing Circuit Project/FDIV.v" 5 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1685019441866 "|music|FDIV:inst4"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "9 1 FDIV.v(7) " "Verilog HDL assignment warning at FDIV.v(7): truncated value with size 9 to match size of target (1)" {  } { { "FDIV.v" "" { Text "E:/FPGA/Hardware-based Music Performing Circuit Project/FDIV.v" 7 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1685019441866 "|music|FDIV:inst4"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pll20 pll20:inst7 " "Elaborating entity \"pll20\" for hierarchy \"pll20:inst7\"" {  } { { "music.bdf" "inst7" { Schematic "E:/FPGA/Hardware-based Music Performing Circuit Project/music.bdf" { { 64 280 568 256 "inst7" "" } } } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1685019441877 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altpll pll20:inst7\|altpll:altpll_component " "Elaborating entity \"altpll\" for hierarchy \"pll20:inst7\|altpll:altpll_component\"" {  } { { "pll20.v" "altpll_component" { Text "E:/FPGA/Hardware-based Music Performing Circuit Project/pll20.v" 94 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1685019441921 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "pll20:inst7\|altpll:altpll_component " "Elaborated megafunction instantiation \"pll20:inst7\|altpll:altpll_component\"" {  } { { "pll20.v" "" { Text "E:/FPGA/Hardware-based Music Performing Circuit Project/pll20.v" 94 0 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1685019441934 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "pll20:inst7\|altpll:altpll_component " "Instantiated megafunction \"pll20:inst7\|altpll:altpll_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "bandwidth_type AUTO " "Parameter \"bandwidth_type\" = \"AUTO\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1685019441934 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_divide_by 70 " "Parameter \"clk0_divide_by\" = \"70\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1685019441934 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_duty_cycle 50 " "Parameter \"clk0_duty_cycle\" = \"50\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1685019441934 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_multiply_by 1 " "Parameter \"clk0_multiply_by\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1685019441934 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_phase_shift 0 " "Parameter \"clk0_phase_shift\" = \"0\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1685019441934 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_divide_by 10000 " "Parameter \"clk1_divide_by\" = \"10000\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1685019441934 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_duty_cycle 50 " "Parameter \"clk1_duty_cycle\" = \"50\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1685019441934 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_multiply_by 1 " "Parameter \"clk1_multiply_by\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1685019441934 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_phase_shift 0 " "Parameter \"clk1_phase_shift\" = \"0\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1685019441934 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "compensate_clock CLK0 " "Parameter \"compensate_clock\" = \"CLK0\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1685019441934 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "inclk0_input_frequency 20000 " "Parameter \"inclk0_input_frequency\" = \"20000\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1685019441934 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone 10 LP " "Parameter \"intended_device_family\" = \"Cyclone 10 LP\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1685019441934 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint CBX_MODULE_PREFIX=pll20 " "Parameter \"lpm_hint\" = \"CBX_MODULE_PREFIX=pll20\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1685019441934 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altpll " "Parameter \"lpm_type\" = \"altpll\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1685019441934 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode NORMAL " "Parameter \"operation_mode\" = \"NORMAL\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1685019441934 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_type AUTO " "Parameter \"pll_type\" = \"AUTO\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1685019441934 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_activeclock PORT_UNUSED " "Parameter \"port_activeclock\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1685019441934 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_areset PORT_UNUSED " "Parameter \"port_areset\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1685019441934 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkbad0 PORT_UNUSED " "Parameter \"port_clkbad0\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1685019441934 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkbad1 PORT_UNUSED " "Parameter \"port_clkbad1\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1685019441934 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkloss PORT_UNUSED " "Parameter \"port_clkloss\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1685019441934 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkswitch PORT_UNUSED " "Parameter \"port_clkswitch\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1685019441934 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_configupdate PORT_UNUSED " "Parameter \"port_configupdate\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1685019441934 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_fbin PORT_UNUSED " "Parameter \"port_fbin\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1685019441934 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_inclk0 PORT_USED " "Parameter \"port_inclk0\" = \"PORT_USED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1685019441934 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_inclk1 PORT_UNUSED " "Parameter \"port_inclk1\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1685019441934 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_locked PORT_UNUSED " "Parameter \"port_locked\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1685019441934 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_pfdena PORT_UNUSED " "Parameter \"port_pfdena\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1685019441934 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasecounterselect PORT_UNUSED " "Parameter \"port_phasecounterselect\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1685019441934 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasedone PORT_UNUSED " "Parameter \"port_phasedone\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1685019441934 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasestep PORT_UNUSED " "Parameter \"port_phasestep\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1685019441934 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phaseupdown PORT_UNUSED " "Parameter \"port_phaseupdown\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1685019441934 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_pllena PORT_UNUSED " "Parameter \"port_pllena\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1685019441934 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanaclr PORT_UNUSED " "Parameter \"port_scanaclr\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1685019441934 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanclk PORT_UNUSED " "Parameter \"port_scanclk\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1685019441934 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanclkena PORT_UNUSED " "Parameter \"port_scanclkena\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1685019441934 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandata PORT_UNUSED " "Parameter \"port_scandata\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1685019441934 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandataout PORT_UNUSED " "Parameter \"port_scandataout\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1685019441934 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandone PORT_UNUSED " "Parameter \"port_scandone\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1685019441934 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanread PORT_UNUSED " "Parameter \"port_scanread\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1685019441934 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanwrite PORT_UNUSED " "Parameter \"port_scanwrite\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1685019441934 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk0 PORT_USED " "Parameter \"port_clk0\" = \"PORT_USED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1685019441934 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk1 PORT_USED " "Parameter \"port_clk1\" = \"PORT_USED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1685019441934 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk2 PORT_UNUSED " "Parameter \"port_clk2\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1685019441934 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk3 PORT_UNUSED " "Parameter \"port_clk3\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1685019441934 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk4 PORT_UNUSED " "Parameter \"port_clk4\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1685019441934 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk5 PORT_UNUSED " "Parameter \"port_clk5\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1685019441934 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena0 PORT_UNUSED " "Parameter \"port_clkena0\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1685019441934 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena1 PORT_UNUSED " "Parameter \"port_clkena1\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1685019441934 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena2 PORT_UNUSED " "Parameter \"port_clkena2\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1685019441934 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena3 PORT_UNUSED " "Parameter \"port_clkena3\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1685019441934 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena4 PORT_UNUSED " "Parameter \"port_clkena4\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1685019441934 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena5 PORT_UNUSED " "Parameter \"port_clkena5\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1685019441934 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk0 PORT_UNUSED " "Parameter \"port_extclk0\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1685019441934 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk1 PORT_UNUSED " "Parameter \"port_extclk1\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1685019441934 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk2 PORT_UNUSED " "Parameter \"port_extclk2\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1685019441934 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk3 PORT_UNUSED " "Parameter \"port_extclk3\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1685019441934 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_clock 5 " "Parameter \"width_clock\" = \"5\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1685019441934 ""}  } { { "pll20.v" "" { Text "E:/FPGA/Hardware-based Music Performing Circuit Project/pll20.v" 94 0 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1685019441934 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/pll20_altpll.v 1 1 " "Found 1 design units, including 1 entities, in source file db/pll20_altpll.v" { { "Info" "ISGN_ENTITY_NAME" "1 pll20_altpll " "Found entity 1: pll20_altpll" {  } { { "db/pll20_altpll.v" "" { Text "E:/FPGA/Hardware-based Music Performing Circuit Project/db/pll20_altpll.v" 29 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1685019441981 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1685019441981 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pll20_altpll pll20:inst7\|altpll:altpll_component\|pll20_altpll:auto_generated " "Elaborating entity \"pll20_altpll\" for hierarchy \"pll20:inst7\|altpll:altpll_component\|pll20_altpll:auto_generated\"" {  } { { "altpll.tdf" "auto_generated" { Text "d:/intelfpga_lite/18.1/quartus/libraries/megafunctions/altpll.tdf" 897 3 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1685019441982 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "CNT138T CNT138T:inst " "Elaborating entity \"CNT138T\" for hierarchy \"CNT138T:inst\"" {  } { { "music.bdf" "inst" { Schematic "E:/FPGA/Hardware-based Music Performing Circuit Project/music.bdf" { { 336 48 216 416 "inst" "" } } } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1685019441990 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 CNT138T.v(4) " "Verilog HDL assignment warning at CNT138T.v(4): truncated value with size 32 to match size of target (8)" {  } { { "output_files/CNT138T.v" "" { Text "E:/FPGA/Hardware-based Music Performing Circuit Project/output_files/CNT138T.v" 4 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1685019441991 "|music|CNT138T:inst"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "SPKER SPKER:inst3 " "Elaborating entity \"SPKER\" for hierarchy \"SPKER:inst3\"" {  } { { "music.bdf" "inst3" { Schematic "E:/FPGA/Hardware-based Music Performing Circuit Project/music.bdf" { { 352 776 936 432 "inst3" "" } } } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1685019441996 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 11 SPKER.v(6) " "Verilog HDL assignment warning at SPKER.v(6): truncated value with size 32 to match size of target (11)" {  } { { "SPKER.v" "" { Text "E:/FPGA/Hardware-based Music Performing Circuit Project/SPKER.v" 6 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1685019441996 "|music|SPKER:inst3"}
{ "Info" "ISCI_START_SUPER_FABRIC_GEN" "alt_sld_fab " "Starting IP generation for the debug fabric: alt_sld_fab." {  } {  } 0 11170 "Starting IP generation for the debug fabric: %1!s!." 0 0 "Analysis & Synthesis" 0 -1 1685019442135 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "2023.05.25.20:57:25 Progress: Loading sld63346dfb/alt_sld_fab_wrapper_hw.tcl " "2023.05.25.20:57:25 Progress: Loading sld63346dfb/alt_sld_fab_wrapper_hw.tcl" {  } {  } 0 11172 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1685019445672 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Alt_sld_fab.alt_sld_fab: SLD fabric agents which did not specify prefer_host were connected to JTAG " "Alt_sld_fab.alt_sld_fab: SLD fabric agents which did not specify prefer_host were connected to JTAG" {  } {  } 0 11172 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1685019448843 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Alt_sld_fab: Generating alt_sld_fab \"alt_sld_fab\" for QUARTUS_SYNTH " "Alt_sld_fab: Generating alt_sld_fab \"alt_sld_fab\" for QUARTUS_SYNTH" {  } {  } 0 11172 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1685019448950 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Alt_sld_fab: \"alt_sld_fab\" instantiated alt_sld_fab \"alt_sld_fab\" " "Alt_sld_fab: \"alt_sld_fab\" instantiated alt_sld_fab \"alt_sld_fab\"" {  } {  } 0 11172 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1685019454060 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Presplit: \"alt_sld_fab\" instantiated altera_super_splitter \"presplit\" " "Presplit: \"alt_sld_fab\" instantiated altera_super_splitter \"presplit\"" {  } {  } 0 11172 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1685019454159 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Splitter: \"alt_sld_fab\" instantiated altera_sld_splitter \"splitter\" " "Splitter: \"alt_sld_fab\" instantiated altera_sld_splitter \"splitter\"" {  } {  } 0 11172 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1685019454255 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Sldfabric: \"alt_sld_fab\" instantiated altera_sld_jtag_hub \"sldfabric\" " "Sldfabric: \"alt_sld_fab\" instantiated altera_sld_jtag_hub \"sldfabric\"" {  } {  } 0 11172 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1685019454370 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Ident: \"alt_sld_fab\" instantiated altera_connection_identification_hub \"ident\" " "Ident: \"alt_sld_fab\" instantiated altera_connection_identification_hub \"ident\"" {  } {  } 0 11172 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1685019454375 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Alt_sld_fab: Done \"alt_sld_fab\" with 6 modules, 6 files " "Alt_sld_fab: Done \"alt_sld_fab\" with 6 modules, 6 files" {  } {  } 0 11172 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1685019454375 ""}
{ "Info" "ISCI_END_SUPER_FABRIC_GEN" "alt_sld_fab " "Finished IP generation for the debug fabric: alt_sld_fab." {  } {  } 0 11171 "Finished IP generation for the debug fabric: %1!s!." 0 0 "Analysis & Synthesis" 0 -1 1685019455051 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/sld63346dfb/alt_sld_fab.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/sld63346dfb/alt_sld_fab.v" { { "Info" "ISGN_ENTITY_NAME" "1 alt_sld_fab " "Found entity 1: alt_sld_fab" {  } { { "db/ip/sld63346dfb/alt_sld_fab.v" "" { Text "E:/FPGA/Hardware-based Music Performing Circuit Project/db/ip/sld63346dfb/alt_sld_fab.v" 9 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1685019455261 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1685019455261 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/sld63346dfb/submodules/alt_sld_fab_alt_sld_fab.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/sld63346dfb/submodules/alt_sld_fab_alt_sld_fab.v" { { "Info" "ISGN_ENTITY_NAME" "1 alt_sld_fab_alt_sld_fab " "Found entity 1: alt_sld_fab_alt_sld_fab" {  } { { "db/ip/sld63346dfb/submodules/alt_sld_fab_alt_sld_fab.v" "" { Text "E:/FPGA/Hardware-based Music Performing Circuit Project/db/ip/sld63346dfb/submodules/alt_sld_fab_alt_sld_fab.v" 9 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1685019455332 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1685019455332 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/sld63346dfb/submodules/alt_sld_fab_alt_sld_fab_ident.sv 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/sld63346dfb/submodules/alt_sld_fab_alt_sld_fab_ident.sv" { { "Info" "ISGN_ENTITY_NAME" "1 alt_sld_fab_alt_sld_fab_ident " "Found entity 1: alt_sld_fab_alt_sld_fab_ident" {  } { { "db/ip/sld63346dfb/submodules/alt_sld_fab_alt_sld_fab_ident.sv" "" { Text "E:/FPGA/Hardware-based Music Performing Circuit Project/db/ip/sld63346dfb/submodules/alt_sld_fab_alt_sld_fab_ident.sv" 33 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1685019455335 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1685019455335 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/sld63346dfb/submodules/alt_sld_fab_alt_sld_fab_presplit.sv 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/sld63346dfb/submodules/alt_sld_fab_alt_sld_fab_presplit.sv" { { "Info" "ISGN_ENTITY_NAME" "1 alt_sld_fab_alt_sld_fab_presplit " "Found entity 1: alt_sld_fab_alt_sld_fab_presplit" {  } { { "db/ip/sld63346dfb/submodules/alt_sld_fab_alt_sld_fab_presplit.sv" "" { Text "E:/FPGA/Hardware-based Music Performing Circuit Project/db/ip/sld63346dfb/submodules/alt_sld_fab_alt_sld_fab_presplit.sv" 3 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1685019455394 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1685019455394 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/sld63346dfb/submodules/alt_sld_fab_alt_sld_fab_sldfabric.vhd 2 1 " "Found 2 design units, including 1 entities, in source file db/ip/sld63346dfb/submodules/alt_sld_fab_alt_sld_fab_sldfabric.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 alt_sld_fab_alt_sld_fab_sldfabric-rtl " "Found design unit 1: alt_sld_fab_alt_sld_fab_sldfabric-rtl" {  } { { "db/ip/sld63346dfb/submodules/alt_sld_fab_alt_sld_fab_sldfabric.vhd" "" { Text "E:/FPGA/Hardware-based Music Performing Circuit Project/db/ip/sld63346dfb/submodules/alt_sld_fab_alt_sld_fab_sldfabric.vhd" 102 -1 0 } }  } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1685019455476 ""} { "Info" "ISGN_ENTITY_NAME" "1 alt_sld_fab_alt_sld_fab_sldfabric " "Found entity 1: alt_sld_fab_alt_sld_fab_sldfabric" {  } { { "db/ip/sld63346dfb/submodules/alt_sld_fab_alt_sld_fab_sldfabric.vhd" "" { Text "E:/FPGA/Hardware-based Music Performing Circuit Project/db/ip/sld63346dfb/submodules/alt_sld_fab_alt_sld_fab_sldfabric.vhd" 11 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1685019455476 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1685019455476 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/sld63346dfb/submodules/alt_sld_fab_alt_sld_fab_splitter.sv 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/sld63346dfb/submodules/alt_sld_fab_alt_sld_fab_splitter.sv" { { "Info" "ISGN_ENTITY_NAME" "1 alt_sld_fab_alt_sld_fab_splitter " "Found entity 1: alt_sld_fab_alt_sld_fab_splitter" {  } { { "db/ip/sld63346dfb/submodules/alt_sld_fab_alt_sld_fab_splitter.sv" "" { Text "E:/FPGA/Hardware-based Music Performing Circuit Project/db/ip/sld63346dfb/submodules/alt_sld_fab_alt_sld_fab_splitter.sv" 3 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1685019455543 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1685019455543 ""}
{ "Info" "IMLS_MLS_PRESET_POWER_UP" "" "Registers with preset signals will power-up high" {  } { { "FDIV.v" "" { Text "E:/FPGA/Hardware-based Music Performing Circuit Project/FDIV.v" 5 -1 0 } }  } 0 13000 "Registers with preset signals will power-up high" 0 0 "Analysis & Synthesis" 0 -1 1685019456713 ""}
{ "Info" "IMLS_MLS_DEV_CLRN_SETS_REGISTERS" "" "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" {  } {  } 0 13003 "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" 0 0 "Analysis & Synthesis" 0 -1 1685019456713 ""}
{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "LED\[3\] GND " "Pin \"LED\[3\]\" is stuck at GND" {  } { { "music.bdf" "" { Schematic "E:/FPGA/Hardware-based Music Performing Circuit Project/music.bdf" { { 560 840 1016 576 "LED\[3..0\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1685019456737 "|music|LED[3]"}  } {  } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Analysis & Synthesis" 0 -1 1685019456737 ""}
{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING_ON_PARTITION" "Top " "Timing-Driven Synthesis is running on partition \"Top\"" {  } {  } 0 286031 "Timing-Driven Synthesis is running on partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1685019456797 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "E:/FPGA/Hardware-based Music Performing Circuit Project/output_files/music.map.smsg " "Generated suppressed messages file E:/FPGA/Hardware-based Music Performing Circuit Project/output_files/music.map.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1685019457319 ""}
{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "1 0 1 0 0 " "Adding 1 node(s), including 0 DDIO, 1 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1685019457960 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1685019457960 ""}
{ "Error" "ECUT_CUT_ZIPPLEBACK_RAM_INIT_ILLEGAL_CONFIG_MODE" "" "Current Internal Configuration mode does not support memory initialization or ROM. Select Internal Configuration mode with ERAM." {  } { { "db/altsyncram_5oc2.tdf" "" { Text "E:/FPGA/Hardware-based Music Performing Circuit Project/db/altsyncram_5oc2.tdf" 34 2 0 } } { "db/altsyncram_b8b1.tdf" "" { Text "E:/FPGA/Hardware-based Music Performing Circuit Project/db/altsyncram_b8b1.tdf" 34 0 0 } } { "altsyncram.tdf" "" { Text "d:/intelfpga_lite/18.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 0 0 } } { "rom.v" "" { Text "E:/FPGA/Hardware-based Music Performing Circuit Project/rom.v" 81 0 0 } } { "music.bdf" "" { Schematic "E:/FPGA/Hardware-based Music Performing Circuit Project/music.bdf" { { 424 264 480 552 "inst1" "" } } } }  } 0 16031 "Current Internal Configuration mode does not support memory initialization or ROM. Select Internal Configuration mode with ERAM." 0 0 "Analysis & Synthesis" 0 -1 1685019457986 ""}
{ "Error" "ECUT_CUT_ZIPPLEBACK_RAM_INIT_ILLEGAL_CONFIG_MODE" "" "Current Internal Configuration mode does not support memory initialization or ROM. Select Internal Configuration mode with ERAM." {  } { { "db/altsyncram_5oc2.tdf" "" { Text "E:/FPGA/Hardware-based Music Performing Circuit Project/db/altsyncram_5oc2.tdf" 34 2 0 } } { "db/altsyncram_b8b1.tdf" "" { Text "E:/FPGA/Hardware-based Music Performing Circuit Project/db/altsyncram_b8b1.tdf" 34 0 0 } } { "altsyncram.tdf" "" { Text "d:/intelfpga_lite/18.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 0 0 } } { "rom.v" "" { Text "E:/FPGA/Hardware-based Music Performing Circuit Project/rom.v" 81 0 0 } } { "music.bdf" "" { Schematic "E:/FPGA/Hardware-based Music Performing Circuit Project/music.bdf" { { 424 264 480 552 "inst1" "" } } } }  } 0 16031 "Current Internal Configuration mode does not support memory initialization or ROM. Select Internal Configuration mode with ERAM." 0 0 "Analysis & Synthesis" 0 -1 1685019457986 ""}
{ "Error" "ECUT_CUT_ZIPPLEBACK_RAM_INIT_ILLEGAL_CONFIG_MODE" "" "Current Internal Configuration mode does not support memory initialization or ROM. Select Internal Configuration mode with ERAM." {  } { { "db/altsyncram_5oc2.tdf" "" { Text "E:/FPGA/Hardware-based Music Performing Circuit Project/db/altsyncram_5oc2.tdf" 34 2 0 } } { "db/altsyncram_b8b1.tdf" "" { Text "E:/FPGA/Hardware-based Music Performing Circuit Project/db/altsyncram_b8b1.tdf" 34 0 0 } } { "altsyncram.tdf" "" { Text "d:/intelfpga_lite/18.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 0 0 } } { "rom.v" "" { Text "E:/FPGA/Hardware-based Music Performing Circuit Project/rom.v" 81 0 0 } } { "music.bdf" "" { Schematic "E:/FPGA/Hardware-based Music Performing Circuit Project/music.bdf" { { 424 264 480 552 "inst1" "" } } } }  } 0 16031 "Current Internal Configuration mode does not support memory initialization or ROM. Select Internal Configuration mode with ERAM." 0 0 "Analysis & Synthesis" 0 -1 1685019457986 ""}
{ "Error" "ECUT_CUT_ZIPPLEBACK_RAM_INIT_ILLEGAL_CONFIG_MODE" "" "Current Internal Configuration mode does not support memory initialization or ROM. Select Internal Configuration mode with ERAM." {  } { { "db/altsyncram_5oc2.tdf" "" { Text "E:/FPGA/Hardware-based Music Performing Circuit Project/db/altsyncram_5oc2.tdf" 34 2 0 } } { "db/altsyncram_b8b1.tdf" "" { Text "E:/FPGA/Hardware-based Music Performing Circuit Project/db/altsyncram_b8b1.tdf" 34 0 0 } } { "altsyncram.tdf" "" { Text "d:/intelfpga_lite/18.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 0 0 } } { "rom.v" "" { Text "E:/FPGA/Hardware-based Music Performing Circuit Project/rom.v" 81 0 0 } } { "music.bdf" "" { Schematic "E:/FPGA/Hardware-based Music Performing Circuit Project/music.bdf" { { 424 264 480 552 "inst1" "" } } } }  } 0 16031 "Current Internal Configuration mode does not support memory initialization or ROM. Select Internal Configuration mode with ERAM." 0 0 "Analysis & Synthesis" 0 -1 1685019457986 ""}
{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 4 s 9 s Quartus Prime " "Quartus Prime Analysis & Synthesis was unsuccessful. 4 errors, 9 warnings" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "4876 " "Peak virtual memory: 4876 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1685019458005 ""} { "Error" "EQEXE_END_BANNER_TIME" "Thu May 25 20:57:38 2023 " "Processing ended: Thu May 25 20:57:38 2023" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1685019458005 ""} { "Error" "EQEXE_ELAPSED_TIME" "00:00:27 " "Elapsed time: 00:00:27" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1685019458005 ""} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:45 " "Total CPU time (on all processors): 00:00:45" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1685019458005 ""}  } {  } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1685019458005 ""}