# -------------------------------------------------------------------------- # # # Copyright (C) 2018 Intel Corporation. All rights reserved. # Your use of Intel Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any output files from any of the foregoing # (including device programming or simulation files), and any # associated documentation or information are expressly subject # to the terms and conditions of the Intel Program License # Subscription Agreement, the Intel Quartus Prime License Agreement, # the Intel FPGA IP License Agreement, or other applicable license # agreement, including, without limitation, that your use is for # the sole purpose of programming logic devices manufactured by # Intel and sold by Intel or its authorized distributors. Please # refer to the applicable agreement for further details. # # -------------------------------------------------------------------------- # # # Quartus Prime # Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition # Date created = 20:15:24 November 27, 2019 # # -------------------------------------------------------------------------- # # # Notes: # # 1) The default values for assignments are stored in the file: # music_assignment_defaults.qdf # If this file doesn't exist, see file: # assignment_defaults.qdf # # 2) Altera recommends that you do not modify this file. This # file is updated automatically by the Quartus Prime software # and any changes you make may be lost or overwritten. # # -------------------------------------------------------------------------- # set_global_assignment -name FAMILY "MAX 10" set_global_assignment -name DEVICE 10M08SCU169I7G set_global_assignment -name TOP_LEVEL_ENTITY music set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.1.0 set_global_assignment -name PROJECT_CREATION_TIME_DATE "20:15:24 NOVEMBER 27, 2019" set_global_assignment -name LAST_QUARTUS_VERSION "18.1.0 Lite Edition" set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40" set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100 set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 2 set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)" set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation set_global_assignment -name MIF_FILE music.mif set_global_assignment -name BDF_FILE music.bdf set_global_assignment -name VERILOG_FILE output_files/CNT138T.v set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST ON -section_id eda_simulation set_global_assignment -name QIP_FILE rom.qip set_global_assignment -name VERILOG_FILE F_CODE.v set_global_assignment -name VERILOG_FILE SPKER.v set_global_assignment -name VERILOG_FILE FDIV.v set_global_assignment -name QIP_FILE pll20.qip set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top set_global_assignment -name ENABLE_OCT_DONE OFF set_global_assignment -name EXTERNAL_FLASH_FALLBACK_ADDRESS 00000000 set_global_assignment -name USE_CONFIGURATION_DEVICE OFF set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "SINGLE IMAGE" set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top