Analysis & Synthesis report for music Thu May 25 20:57:37 2023 Quartus Prime Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition --------------------- ; Table of Contents ; --------------------- 1. Legal Notice 2. Analysis & Synthesis Summary 3. Analysis & Synthesis Settings 4. Parallel Compilation 5. Analysis & Synthesis IP Cores Summary 6. Registers Removed During Synthesis 7. Multiplexer Restructuring Statistics (Restructuring Performed) 8. Source assignments for rom:inst1|altsyncram:altsyncram_component|altsyncram_b8b1:auto_generated|altsyncram_5oc2:altsyncram1 9. Parameter Settings for User Entity Instance: rom:inst1|altsyncram:altsyncram_component 10. Parameter Settings for User Entity Instance: pll20:inst7|altpll:altpll_component 11. altsyncram Parameter Settings by Entity Instance 12. altpll Parameter Settings by Entity Instance 13. In-System Memory Content Editor Settings 14. Post-Synthesis Netlist Statistics for Top Partition 15. Elapsed Time Per Partition 16. Analysis & Synthesis Messages 17. Analysis & Synthesis Suppressed Messages ---------------- ; Legal Notice ; ---------------- Copyright (C) 2018 Intel Corporation. All rights reserved. Your use of Intel Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Intel Program License Subscription Agreement, the Intel Quartus Prime License Agreement, the Intel FPGA IP License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Intel and sold by Intel or its authorized distributors. Please refer to the applicable agreement for further details. +----------------------------------------------------------------------------------+ ; Analysis & Synthesis Summary ; +------------------------------------+---------------------------------------------+ ; Analysis & Synthesis Status ; Successful - Thu May 25 20:57:37 2023 ; ; Quartus Prime Version ; 18.1.0 Build 625 09/12/2018 SJ Lite Edition ; ; Revision Name ; music ; ; Top-level Entity Name ; music ; ; Family ; MAX 10 ; ; Total logic elements ; N/A until Partition Merge ; ; Total combinational functions ; N/A until Partition Merge ; ; Dedicated logic registers ; N/A until Partition Merge ; ; Total registers ; N/A until Partition Merge ; ; Total pins ; N/A until Partition Merge ; ; Total virtual pins ; N/A until Partition Merge ; ; Total memory bits ; N/A until Partition Merge ; ; Embedded Multiplier 9-bit elements ; N/A until Partition Merge ; ; Total PLLs ; N/A until Partition Merge ; ; UFM blocks ; N/A until Partition Merge ; ; ADC blocks ; N/A until Partition Merge ; +------------------------------------+---------------------------------------------+ +------------------------------------------------------------------------------------------------------------+ ; Analysis & Synthesis Settings ; +------------------------------------------------------------------+--------------------+--------------------+ ; Option ; Setting ; Default Value ; +------------------------------------------------------------------+--------------------+--------------------+ ; Device ; 10M08SCU169I7G ; ; ; Top-level entity name ; music ; music ; ; Family name ; MAX 10 ; Cyclone V ; ; Use smart compilation ; Off ; Off ; ; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ; ; Enable compact report table ; Off ; Off ; ; Restructure Multiplexers ; Auto ; Auto ; ; Create Debugging Nodes for IP Cores ; Off ; Off ; ; Preserve fewer node names ; On ; On ; ; Intel FPGA IP Evaluation Mode ; Enable ; Enable ; ; Verilog Version ; Verilog_2001 ; Verilog_2001 ; ; VHDL Version ; VHDL_1993 ; VHDL_1993 ; ; State Machine Processing ; Auto ; Auto ; ; Safe State Machine ; Off ; Off ; ; Extract Verilog State Machines ; On ; On ; ; Extract VHDL State Machines ; On ; On ; ; Ignore Verilog initial constructs ; Off ; Off ; ; Iteration limit for constant Verilog loops ; 5000 ; 5000 ; ; Iteration limit for non-constant Verilog loops ; 250 ; 250 ; ; Add Pass-Through Logic to Inferred RAMs ; On ; On ; ; Infer RAMs from Raw Logic ; On ; On ; ; Parallel Synthesis ; On ; On ; ; DSP Block Balancing ; Auto ; Auto ; ; NOT Gate Push-Back ; On ; On ; ; Power-Up Don't Care ; On ; On ; ; Remove Redundant Logic Cells ; Off ; Off ; ; Remove Duplicate Registers ; On ; On ; ; Ignore CARRY Buffers ; Off ; Off ; ; Ignore CASCADE Buffers ; Off ; Off ; ; Ignore GLOBAL Buffers ; Off ; Off ; ; Ignore ROW GLOBAL Buffers ; Off ; Off ; ; Ignore LCELL Buffers ; Off ; Off ; ; Ignore SOFT Buffers ; On ; On ; ; Limit AHDL Integers to 32 Bits ; Off ; Off ; ; Optimization Technique ; Balanced ; Balanced ; ; Carry Chain Length ; 70 ; 70 ; ; Auto Carry Chains ; On ; On ; ; Auto Open-Drain Pins ; On ; On ; ; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ; ; Auto ROM Replacement ; On ; On ; ; Auto RAM Replacement ; On ; On ; ; Auto DSP Block Replacement ; On ; On ; ; Auto Shift Register Replacement ; Auto ; Auto ; ; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ; ; Auto Clock Enable Replacement ; On ; On ; ; Strict RAM Replacement ; Off ; Off ; ; Allow Synchronous Control Signals ; On ; On ; ; Force Use of Synchronous Clear Signals ; Off ; Off ; ; Auto RAM Block Balancing ; On ; On ; ; Auto RAM to Logic Cell Conversion ; Off ; Off ; ; Auto Resource Sharing ; Off ; Off ; ; Allow Any RAM Size For Recognition ; Off ; Off ; ; Allow Any ROM Size For Recognition ; Off ; Off ; ; Allow Any Shift Register Size For Recognition ; Off ; Off ; ; Use LogicLock Constraints during Resource Balancing ; On ; On ; ; Ignore translate_off and synthesis_off directives ; Off ; Off ; ; Timing-Driven Synthesis ; On ; On ; ; Report Parameter Settings ; On ; On ; ; Report Source Assignments ; On ; On ; ; Report Connectivity Checks ; On ; On ; ; Ignore Maximum Fan-Out Assignments ; Off ; Off ; ; Synchronization Register Chain Length ; 2 ; 2 ; ; Power Optimization During Synthesis ; Normal compilation ; Normal compilation ; ; HDL message level ; Level2 ; Level2 ; ; Suppress Register Optimization Related Messages ; Off ; Off ; ; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ; ; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ; ; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ; ; Clock MUX Protection ; On ; On ; ; Auto Gated Clock Conversion ; Off ; Off ; ; Block Design Naming ; Auto ; Auto ; ; SDC constraint protection ; Off ; Off ; ; Synthesis Effort ; Auto ; Auto ; ; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ; ; Pre-Mapping Resynthesis Optimization ; Off ; Off ; ; Analysis & Synthesis Message Level ; Medium ; Medium ; ; Disable Register Merging Across Hierarchies ; Auto ; Auto ; ; Resource Aware Inference For Block RAM ; On ; On ; +------------------------------------------------------------------+--------------------+--------------------+ +------------------------------------------+ ; Parallel Compilation ; +----------------------------+-------------+ ; Processors ; Number ; +----------------------------+-------------+ ; Number detected on machine ; 16 ; ; Maximum allowed ; 16 ; ; ; ; ; Average used ; 1.00 ; ; Maximum used ; 16 ; ; ; ; ; Usage by Processor ; % Time Used ; ; Processor 1 ; 100.0% ; ; Processor 2 ; 0.0% ; ; Processors 3-16 ; 0.0% ; +----------------------------+-------------+ +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Analysis & Synthesis IP Cores Summary ; +--------+--------------+---------+--------------+--------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+ ; Vendor ; IP Core Name ; Version ; Release Date ; License Type ; Entity Instance ; IP Include File ; +--------+--------------+---------+--------------+--------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+ ; Altera ; Signal Tap ; N/A ; N/A ; Licensed ; |music|sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric ; ; ; Altera ; Signal Tap ; N/A ; N/A ; Licensed ; |music|sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab ; ; ; Altera ; Signal Tap ; N/A ; N/A ; Licensed ; |music|sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|alt_sld_fab_alt_sld_fab_presplit:presplit ; ; ; Altera ; Signal Tap ; N/A ; N/A ; Licensed ; |music|sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|alt_sld_fab_alt_sld_fab_sldfabric:sldfabric ; ; ; Altera ; Signal Tap ; N/A ; N/A ; Licensed ; |music|sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|alt_sld_fab_alt_sld_fab_splitter:splitter ; ; ; Altera ; ROM: 1-PORT ; 18.1 ; N/A ; N/A ; |music|rom:inst1 ; rom.v ; ; Altera ; ALTPLL ; 18.1 ; N/A ; N/A ; |music|pll20:inst7 ; pll20.v ; +--------+--------------+---------+--------------+--------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+ +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Registers Removed During Synthesis ; +-----------------------------------------------------------------------------------------------------------------------------------+----------------------------------------+ ; Register name ; Reason for Removal ; +-----------------------------------------------------------------------------------------------------------------------------------+----------------------------------------+ ; rom:inst1|altsyncram:altsyncram_component|altsyncram_b8b1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[2] ; Stuck at GND due to stuck port data_in ; ; Total Number of Removed Registers = 1 ; ; +-----------------------------------------------------------------------------------------------------------------------------------+----------------------------------------+ +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Multiplexer Restructuring Statistics (Restructuring Performed) ; +--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ; +--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; 3:1 ; 3 bits ; 6 LEs ; 3 LEs ; 3 LEs ; Yes ; |music|rom:inst1|altsyncram:altsyncram_component|altsyncram_b8b1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[0] ; ; 3:1 ; 4 bits ; 8 LEs ; 4 LEs ; 4 LEs ; Yes ; |music|rom:inst1|altsyncram:altsyncram_component|altsyncram_b8b1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[0] ; ; 3:1 ; 8 bits ; 16 LEs ; 8 LEs ; 8 LEs ; Yes ; |music|rom:inst1|altsyncram:altsyncram_component|altsyncram_b8b1:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[0] ; ; 4:1 ; 5 bits ; 10 LEs ; 5 LEs ; 5 LEs ; Yes ; |music|rom:inst1|altsyncram:altsyncram_component|altsyncram_b8b1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:name_gen:info_rom_sr|word_counter[0] ; ; 26:1 ; 4 bits ; 68 LEs ; 48 LEs ; 20 LEs ; Yes ; |music|rom:inst1|altsyncram:altsyncram_component|altsyncram_b8b1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:name_gen:info_rom_sr|WORD_SR[1] ; +--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +-----------------------------------------------------------------------------------------------------------------------------+ ; Source assignments for rom:inst1|altsyncram:altsyncram_component|altsyncram_b8b1:auto_generated|altsyncram_5oc2:altsyncram1 ; +---------------------------------+--------------------+------+---------------------------------------------------------------+ ; Assignment ; Value ; From ; To ; +---------------------------------+--------------------+------+---------------------------------------------------------------+ ; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ; +---------------------------------+--------------------+------+---------------------------------------------------------------+ +----------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: rom:inst1|altsyncram:altsyncram_component ; +------------------------------------+----------------------+----------------------------+ ; Parameter Name ; Value ; Type ; +------------------------------------+----------------------+----------------------------+ ; BYTE_SIZE_BLOCK ; 8 ; Untyped ; ; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; ; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; ; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; ; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ; WIDTH_BYTEENA ; 1 ; Untyped ; ; OPERATION_MODE ; ROM ; Untyped ; ; WIDTH_A ; 4 ; Signed Integer ; ; WIDTHAD_A ; 8 ; Signed Integer ; ; NUMWORDS_A ; 256 ; Signed Integer ; ; OUTDATA_REG_A ; UNREGISTERED ; Untyped ; ; ADDRESS_ACLR_A ; NONE ; Untyped ; ; OUTDATA_ACLR_A ; NONE ; Untyped ; ; WRCONTROL_ACLR_A ; NONE ; Untyped ; ; INDATA_ACLR_A ; NONE ; Untyped ; ; BYTEENA_ACLR_A ; NONE ; Untyped ; ; WIDTH_B ; 1 ; Untyped ; ; WIDTHAD_B ; 1 ; Untyped ; ; NUMWORDS_B ; 1 ; Untyped ; ; INDATA_REG_B ; CLOCK1 ; Untyped ; ; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ; ; RDCONTROL_REG_B ; CLOCK1 ; Untyped ; ; ADDRESS_REG_B ; CLOCK1 ; Untyped ; ; OUTDATA_REG_B ; UNREGISTERED ; Untyped ; ; BYTEENA_REG_B ; CLOCK1 ; Untyped ; ; INDATA_ACLR_B ; NONE ; Untyped ; ; WRCONTROL_ACLR_B ; NONE ; Untyped ; ; ADDRESS_ACLR_B ; NONE ; Untyped ; ; OUTDATA_ACLR_B ; NONE ; Untyped ; ; RDCONTROL_ACLR_B ; NONE ; Untyped ; ; BYTEENA_ACLR_B ; NONE ; Untyped ; ; WIDTH_BYTEENA_A ; 1 ; Signed Integer ; ; WIDTH_BYTEENA_B ; 1 ; Untyped ; ; RAM_BLOCK_TYPE ; AUTO ; Untyped ; ; BYTE_SIZE ; 8 ; Untyped ; ; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; Untyped ; ; READ_DURING_WRITE_MODE_PORT_A ; NEW_DATA_NO_NBE_READ ; Untyped ; ; READ_DURING_WRITE_MODE_PORT_B ; NEW_DATA_NO_NBE_READ ; Untyped ; ; INIT_FILE ; ../music.mif ; Untyped ; ; INIT_FILE_LAYOUT ; PORT_A ; Untyped ; ; MAXIMUM_DEPTH ; 0 ; Untyped ; ; CLOCK_ENABLE_INPUT_A ; BYPASS ; Untyped ; ; CLOCK_ENABLE_INPUT_B ; NORMAL ; Untyped ; ; CLOCK_ENABLE_OUTPUT_A ; BYPASS ; Untyped ; ; CLOCK_ENABLE_OUTPUT_B ; NORMAL ; Untyped ; ; CLOCK_ENABLE_CORE_A ; USE_INPUT_CLKEN ; Untyped ; ; CLOCK_ENABLE_CORE_B ; USE_INPUT_CLKEN ; Untyped ; ; ENABLE_ECC ; FALSE ; Untyped ; ; ECC_PIPELINE_STAGE_ENABLED ; FALSE ; Untyped ; ; WIDTH_ECCSTATUS ; 3 ; Untyped ; ; DEVICE_FAMILY ; MAX 10 ; Untyped ; ; CBXI_PARAMETER ; altsyncram_b8b1 ; Untyped ; +------------------------------------+----------------------+----------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +----------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: pll20:inst7|altpll:altpll_component ; +-------------------------------+-------------------------+------------------------+ ; Parameter Name ; Value ; Type ; +-------------------------------+-------------------------+------------------------+ ; OPERATION_MODE ; NORMAL ; Untyped ; ; PLL_TYPE ; AUTO ; Untyped ; ; LPM_HINT ; CBX_MODULE_PREFIX=pll20 ; Untyped ; ; QUALIFY_CONF_DONE ; OFF ; Untyped ; ; COMPENSATE_CLOCK ; CLK0 ; Untyped ; ; SCAN_CHAIN ; LONG ; Untyped ; ; PRIMARY_CLOCK ; INCLK0 ; Untyped ; ; INCLK0_INPUT_FREQUENCY ; 20000 ; Signed Integer ; ; INCLK1_INPUT_FREQUENCY ; 0 ; Untyped ; ; GATE_LOCK_SIGNAL ; NO ; Untyped ; ; GATE_LOCK_COUNTER ; 0 ; Untyped ; ; LOCK_HIGH ; 1 ; Untyped ; ; LOCK_LOW ; 1 ; Untyped ; ; VALID_LOCK_MULTIPLIER ; 1 ; Untyped ; ; INVALID_LOCK_MULTIPLIER ; 5 ; Untyped ; ; SWITCH_OVER_ON_LOSSCLK ; OFF ; Untyped ; ; SWITCH_OVER_ON_GATED_LOCK ; OFF ; Untyped ; ; ENABLE_SWITCH_OVER_COUNTER ; OFF ; Untyped ; ; SKIP_VCO ; OFF ; Untyped ; ; SWITCH_OVER_COUNTER ; 0 ; Untyped ; ; SWITCH_OVER_TYPE ; AUTO ; Untyped ; ; FEEDBACK_SOURCE ; EXTCLK0 ; Untyped ; ; BANDWIDTH ; 0 ; Untyped ; ; BANDWIDTH_TYPE ; AUTO ; Untyped ; ; SPREAD_FREQUENCY ; 0 ; Untyped ; ; DOWN_SPREAD ; 0 ; Untyped ; ; SELF_RESET_ON_GATED_LOSS_LOCK ; OFF ; Untyped ; ; SELF_RESET_ON_LOSS_LOCK ; OFF ; Untyped ; ; CLK9_MULTIPLY_BY ; 0 ; Untyped ; ; CLK8_MULTIPLY_BY ; 0 ; Untyped ; ; CLK7_MULTIPLY_BY ; 0 ; Untyped ; ; CLK6_MULTIPLY_BY ; 0 ; Untyped ; ; CLK5_MULTIPLY_BY ; 1 ; Untyped ; ; CLK4_MULTIPLY_BY ; 1 ; Untyped ; ; CLK3_MULTIPLY_BY ; 1 ; Untyped ; ; CLK2_MULTIPLY_BY ; 1 ; Untyped ; ; CLK1_MULTIPLY_BY ; 1 ; Signed Integer ; ; CLK0_MULTIPLY_BY ; 1 ; Signed Integer ; ; CLK9_DIVIDE_BY ; 0 ; Untyped ; ; CLK8_DIVIDE_BY ; 0 ; Untyped ; ; CLK7_DIVIDE_BY ; 0 ; Untyped ; ; CLK6_DIVIDE_BY ; 0 ; Untyped ; ; CLK5_DIVIDE_BY ; 1 ; Untyped ; ; CLK4_DIVIDE_BY ; 1 ; Untyped ; ; CLK3_DIVIDE_BY ; 1 ; Untyped ; ; CLK2_DIVIDE_BY ; 1 ; Untyped ; ; CLK1_DIVIDE_BY ; 10000 ; Signed Integer ; ; CLK0_DIVIDE_BY ; 70 ; Signed Integer ; ; CLK9_PHASE_SHIFT ; 0 ; Untyped ; ; CLK8_PHASE_SHIFT ; 0 ; Untyped ; ; CLK7_PHASE_SHIFT ; 0 ; Untyped ; ; CLK6_PHASE_SHIFT ; 0 ; Untyped ; ; CLK5_PHASE_SHIFT ; 0 ; Untyped ; ; CLK4_PHASE_SHIFT ; 0 ; Untyped ; ; CLK3_PHASE_SHIFT ; 0 ; Untyped ; ; CLK2_PHASE_SHIFT ; 0 ; Untyped ; ; CLK1_PHASE_SHIFT ; 0 ; Untyped ; ; CLK0_PHASE_SHIFT ; 0 ; Untyped ; ; CLK5_TIME_DELAY ; 0 ; Untyped ; ; CLK4_TIME_DELAY ; 0 ; Untyped ; ; CLK3_TIME_DELAY ; 0 ; Untyped ; ; CLK2_TIME_DELAY ; 0 ; Untyped ; ; CLK1_TIME_DELAY ; 0 ; Untyped ; ; CLK0_TIME_DELAY ; 0 ; Untyped ; ; CLK9_DUTY_CYCLE ; 50 ; Untyped ; ; CLK8_DUTY_CYCLE ; 50 ; Untyped ; ; CLK7_DUTY_CYCLE ; 50 ; Untyped ; ; CLK6_DUTY_CYCLE ; 50 ; Untyped ; ; CLK5_DUTY_CYCLE ; 50 ; Untyped ; ; CLK4_DUTY_CYCLE ; 50 ; Untyped ; ; CLK3_DUTY_CYCLE ; 50 ; Untyped ; ; CLK2_DUTY_CYCLE ; 50 ; Untyped ; ; CLK1_DUTY_CYCLE ; 50 ; Signed Integer ; ; CLK0_DUTY_CYCLE ; 50 ; Signed Integer ; ; CLK9_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; ; CLK8_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; ; CLK7_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; ; CLK6_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; ; CLK5_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; ; CLK4_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; ; CLK3_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; ; CLK2_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; ; CLK1_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; ; CLK0_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; ; CLK9_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; ; CLK8_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; ; CLK7_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; ; CLK6_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; ; CLK5_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; ; CLK4_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; ; CLK3_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; ; CLK2_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; ; CLK1_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; ; CLK0_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; ; LOCK_WINDOW_UI ; 0.05 ; Untyped ; ; LOCK_WINDOW_UI_BITS ; UNUSED ; Untyped ; ; VCO_RANGE_DETECTOR_LOW_BITS ; UNUSED ; Untyped ; ; VCO_RANGE_DETECTOR_HIGH_BITS ; UNUSED ; Untyped ; ; DPA_MULTIPLY_BY ; 0 ; Untyped ; ; DPA_DIVIDE_BY ; 1 ; Untyped ; ; DPA_DIVIDER ; 0 ; Untyped ; ; EXTCLK3_MULTIPLY_BY ; 1 ; Untyped ; ; EXTCLK2_MULTIPLY_BY ; 1 ; Untyped ; ; EXTCLK1_MULTIPLY_BY ; 1 ; Untyped ; ; EXTCLK0_MULTIPLY_BY ; 1 ; Untyped ; ; EXTCLK3_DIVIDE_BY ; 1 ; Untyped ; ; EXTCLK2_DIVIDE_BY ; 1 ; Untyped ; ; EXTCLK1_DIVIDE_BY ; 1 ; Untyped ; ; EXTCLK0_DIVIDE_BY ; 1 ; Untyped ; ; EXTCLK3_PHASE_SHIFT ; 0 ; Untyped ; ; EXTCLK2_PHASE_SHIFT ; 0 ; Untyped ; ; EXTCLK1_PHASE_SHIFT ; 0 ; Untyped ; ; EXTCLK0_PHASE_SHIFT ; 0 ; Untyped ; ; EXTCLK3_TIME_DELAY ; 0 ; Untyped ; ; EXTCLK2_TIME_DELAY ; 0 ; Untyped ; ; EXTCLK1_TIME_DELAY ; 0 ; Untyped ; ; EXTCLK0_TIME_DELAY ; 0 ; Untyped ; ; EXTCLK3_DUTY_CYCLE ; 50 ; Untyped ; ; EXTCLK2_DUTY_CYCLE ; 50 ; Untyped ; ; EXTCLK1_DUTY_CYCLE ; 50 ; Untyped ; ; EXTCLK0_DUTY_CYCLE ; 50 ; Untyped ; ; VCO_MULTIPLY_BY ; 0 ; Untyped ; ; VCO_DIVIDE_BY ; 0 ; Untyped ; ; SCLKOUT0_PHASE_SHIFT ; 0 ; Untyped ; ; SCLKOUT1_PHASE_SHIFT ; 0 ; Untyped ; ; VCO_MIN ; 0 ; Untyped ; ; VCO_MAX ; 0 ; Untyped ; ; VCO_CENTER ; 0 ; Untyped ; ; PFD_MIN ; 0 ; Untyped ; ; PFD_MAX ; 0 ; Untyped ; ; M_INITIAL ; 0 ; Untyped ; ; M ; 0 ; Untyped ; ; N ; 1 ; Untyped ; ; M2 ; 1 ; Untyped ; ; N2 ; 1 ; Untyped ; ; SS ; 1 ; Untyped ; ; C0_HIGH ; 0 ; Untyped ; ; C1_HIGH ; 0 ; Untyped ; ; C2_HIGH ; 0 ; Untyped ; ; C3_HIGH ; 0 ; Untyped ; ; C4_HIGH ; 0 ; Untyped ; ; C5_HIGH ; 0 ; Untyped ; ; C6_HIGH ; 0 ; Untyped ; ; C7_HIGH ; 0 ; Untyped ; ; C8_HIGH ; 0 ; Untyped ; ; C9_HIGH ; 0 ; Untyped ; ; C0_LOW ; 0 ; Untyped ; ; C1_LOW ; 0 ; Untyped ; ; C2_LOW ; 0 ; Untyped ; ; C3_LOW ; 0 ; Untyped ; ; C4_LOW ; 0 ; Untyped ; ; C5_LOW ; 0 ; Untyped ; ; C6_LOW ; 0 ; Untyped ; ; C7_LOW ; 0 ; Untyped ; ; C8_LOW ; 0 ; Untyped ; ; C9_LOW ; 0 ; Untyped ; ; C0_INITIAL ; 0 ; Untyped ; ; C1_INITIAL ; 0 ; Untyped ; ; C2_INITIAL ; 0 ; Untyped ; ; C3_INITIAL ; 0 ; Untyped ; ; C4_INITIAL ; 0 ; Untyped ; ; C5_INITIAL ; 0 ; Untyped ; ; C6_INITIAL ; 0 ; Untyped ; ; C7_INITIAL ; 0 ; Untyped ; ; C8_INITIAL ; 0 ; Untyped ; ; C9_INITIAL ; 0 ; Untyped ; ; C0_MODE ; BYPASS ; Untyped ; ; C1_MODE ; BYPASS ; Untyped ; ; C2_MODE ; BYPASS ; Untyped ; ; C3_MODE ; BYPASS ; Untyped ; ; C4_MODE ; BYPASS ; Untyped ; ; C5_MODE ; BYPASS ; Untyped ; ; C6_MODE ; BYPASS ; Untyped ; ; C7_MODE ; BYPASS ; Untyped ; ; C8_MODE ; BYPASS ; Untyped ; ; C9_MODE ; BYPASS ; Untyped ; ; C0_PH ; 0 ; Untyped ; ; C1_PH ; 0 ; Untyped ; ; C2_PH ; 0 ; Untyped ; ; C3_PH ; 0 ; Untyped ; ; C4_PH ; 0 ; Untyped ; ; C5_PH ; 0 ; Untyped ; ; C6_PH ; 0 ; Untyped ; ; C7_PH ; 0 ; Untyped ; ; C8_PH ; 0 ; Untyped ; ; C9_PH ; 0 ; Untyped ; ; L0_HIGH ; 1 ; Untyped ; ; L1_HIGH ; 1 ; Untyped ; ; G0_HIGH ; 1 ; Untyped ; ; G1_HIGH ; 1 ; Untyped ; ; G2_HIGH ; 1 ; Untyped ; ; G3_HIGH ; 1 ; Untyped ; ; E0_HIGH ; 1 ; Untyped ; ; E1_HIGH ; 1 ; Untyped ; ; E2_HIGH ; 1 ; Untyped ; ; E3_HIGH ; 1 ; Untyped ; ; L0_LOW ; 1 ; Untyped ; ; L1_LOW ; 1 ; Untyped ; ; G0_LOW ; 1 ; Untyped ; ; G1_LOW ; 1 ; Untyped ; ; G2_LOW ; 1 ; Untyped ; ; G3_LOW ; 1 ; Untyped ; ; E0_LOW ; 1 ; Untyped ; ; E1_LOW ; 1 ; Untyped ; ; E2_LOW ; 1 ; Untyped ; ; E3_LOW ; 1 ; Untyped ; ; L0_INITIAL ; 1 ; Untyped ; ; L1_INITIAL ; 1 ; Untyped ; ; G0_INITIAL ; 1 ; Untyped ; ; G1_INITIAL ; 1 ; Untyped ; ; G2_INITIAL ; 1 ; Untyped ; ; G3_INITIAL ; 1 ; Untyped ; ; E0_INITIAL ; 1 ; Untyped ; ; E1_INITIAL ; 1 ; Untyped ; ; E2_INITIAL ; 1 ; Untyped ; ; E3_INITIAL ; 1 ; Untyped ; ; L0_MODE ; BYPASS ; Untyped ; ; L1_MODE ; BYPASS ; Untyped ; ; G0_MODE ; BYPASS ; Untyped ; ; G1_MODE ; BYPASS ; Untyped ; ; G2_MODE ; BYPASS ; Untyped ; ; G3_MODE ; BYPASS ; Untyped ; ; E0_MODE ; BYPASS ; Untyped ; ; E1_MODE ; BYPASS ; Untyped ; ; E2_MODE ; BYPASS ; Untyped ; ; E3_MODE ; BYPASS ; Untyped ; ; L0_PH ; 0 ; Untyped ; ; L1_PH ; 0 ; Untyped ; ; G0_PH ; 0 ; Untyped ; ; G1_PH ; 0 ; Untyped ; ; G2_PH ; 0 ; Untyped ; ; G3_PH ; 0 ; Untyped ; ; E0_PH ; 0 ; Untyped ; ; E1_PH ; 0 ; Untyped ; ; E2_PH ; 0 ; Untyped ; ; E3_PH ; 0 ; Untyped ; ; M_PH ; 0 ; Untyped ; ; C1_USE_CASC_IN ; OFF ; Untyped ; ; C2_USE_CASC_IN ; OFF ; Untyped ; ; C3_USE_CASC_IN ; OFF ; Untyped ; ; C4_USE_CASC_IN ; OFF ; Untyped ; ; C5_USE_CASC_IN ; OFF ; Untyped ; ; C6_USE_CASC_IN ; OFF ; Untyped ; ; C7_USE_CASC_IN ; OFF ; Untyped ; ; C8_USE_CASC_IN ; OFF ; Untyped ; ; C9_USE_CASC_IN ; OFF ; Untyped ; ; CLK0_COUNTER ; G0 ; Untyped ; ; CLK1_COUNTER ; G0 ; Untyped ; ; CLK2_COUNTER ; G0 ; Untyped ; ; CLK3_COUNTER ; G0 ; Untyped ; ; CLK4_COUNTER ; G0 ; Untyped ; ; CLK5_COUNTER ; G0 ; Untyped ; ; CLK6_COUNTER ; E0 ; Untyped ; ; CLK7_COUNTER ; E1 ; Untyped ; ; CLK8_COUNTER ; E2 ; Untyped ; ; CLK9_COUNTER ; E3 ; Untyped ; ; L0_TIME_DELAY ; 0 ; Untyped ; ; L1_TIME_DELAY ; 0 ; Untyped ; ; G0_TIME_DELAY ; 0 ; Untyped ; ; G1_TIME_DELAY ; 0 ; Untyped ; ; G2_TIME_DELAY ; 0 ; Untyped ; ; G3_TIME_DELAY ; 0 ; Untyped ; ; E0_TIME_DELAY ; 0 ; Untyped ; ; E1_TIME_DELAY ; 0 ; Untyped ; ; E2_TIME_DELAY ; 0 ; Untyped ; ; E3_TIME_DELAY ; 0 ; Untyped ; ; M_TIME_DELAY ; 0 ; Untyped ; ; N_TIME_DELAY ; 0 ; Untyped ; ; EXTCLK3_COUNTER ; E3 ; Untyped ; ; EXTCLK2_COUNTER ; E2 ; Untyped ; ; EXTCLK1_COUNTER ; E1 ; Untyped ; ; EXTCLK0_COUNTER ; E0 ; Untyped ; ; ENABLE0_COUNTER ; L0 ; Untyped ; ; ENABLE1_COUNTER ; L0 ; Untyped ; ; CHARGE_PUMP_CURRENT ; 2 ; Untyped ; ; LOOP_FILTER_R ; 1.000000 ; Untyped ; ; LOOP_FILTER_C ; 5 ; Untyped ; ; CHARGE_PUMP_CURRENT_BITS ; 9999 ; Untyped ; ; LOOP_FILTER_R_BITS ; 9999 ; Untyped ; ; LOOP_FILTER_C_BITS ; 9999 ; Untyped ; ; VCO_POST_SCALE ; 0 ; Untyped ; ; CLK2_OUTPUT_FREQUENCY ; 0 ; Untyped ; ; CLK1_OUTPUT_FREQUENCY ; 0 ; Untyped ; ; CLK0_OUTPUT_FREQUENCY ; 0 ; Untyped ; ; INTENDED_DEVICE_FAMILY ; Cyclone 10 LP ; Untyped ; ; PORT_CLKENA0 ; PORT_UNUSED ; Untyped ; ; PORT_CLKENA1 ; PORT_UNUSED ; Untyped ; ; PORT_CLKENA2 ; PORT_UNUSED ; Untyped ; ; PORT_CLKENA3 ; PORT_UNUSED ; Untyped ; ; PORT_CLKENA4 ; PORT_UNUSED ; Untyped ; ; PORT_CLKENA5 ; PORT_UNUSED ; Untyped ; ; PORT_EXTCLKENA0 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_EXTCLKENA1 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_EXTCLKENA2 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_EXTCLKENA3 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_EXTCLK0 ; PORT_UNUSED ; Untyped ; ; PORT_EXTCLK1 ; PORT_UNUSED ; Untyped ; ; PORT_EXTCLK2 ; PORT_UNUSED ; Untyped ; ; PORT_EXTCLK3 ; PORT_UNUSED ; Untyped ; ; PORT_CLKBAD0 ; PORT_UNUSED ; Untyped ; ; PORT_CLKBAD1 ; PORT_UNUSED ; Untyped ; ; PORT_CLK0 ; PORT_USED ; Untyped ; ; PORT_CLK1 ; PORT_USED ; Untyped ; ; PORT_CLK2 ; PORT_UNUSED ; Untyped ; ; PORT_CLK3 ; PORT_UNUSED ; Untyped ; ; PORT_CLK4 ; PORT_UNUSED ; Untyped ; ; PORT_CLK5 ; PORT_UNUSED ; Untyped ; ; PORT_CLK6 ; PORT_UNUSED ; Untyped ; ; PORT_CLK7 ; PORT_UNUSED ; Untyped ; ; PORT_CLK8 ; PORT_UNUSED ; Untyped ; ; PORT_CLK9 ; PORT_UNUSED ; Untyped ; ; PORT_SCANDATA ; PORT_UNUSED ; Untyped ; ; PORT_SCANDATAOUT ; PORT_UNUSED ; Untyped ; ; PORT_SCANDONE ; PORT_UNUSED ; Untyped ; ; PORT_SCLKOUT1 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_SCLKOUT0 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_ACTIVECLOCK ; PORT_UNUSED ; Untyped ; ; PORT_CLKLOSS ; PORT_UNUSED ; Untyped ; ; PORT_INCLK1 ; PORT_UNUSED ; Untyped ; ; PORT_INCLK0 ; PORT_USED ; Untyped ; ; PORT_FBIN ; PORT_UNUSED ; Untyped ; ; PORT_PLLENA ; PORT_UNUSED ; Untyped ; ; PORT_CLKSWITCH ; PORT_UNUSED ; Untyped ; ; PORT_ARESET ; PORT_UNUSED ; Untyped ; ; PORT_PFDENA ; PORT_UNUSED ; Untyped ; ; PORT_SCANCLK ; PORT_UNUSED ; Untyped ; ; PORT_SCANACLR ; PORT_UNUSED ; Untyped ; ; PORT_SCANREAD ; PORT_UNUSED ; Untyped ; ; PORT_SCANWRITE ; PORT_UNUSED ; Untyped ; ; PORT_ENABLE0 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_ENABLE1 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_LOCKED ; PORT_UNUSED ; Untyped ; ; PORT_CONFIGUPDATE ; PORT_UNUSED ; Untyped ; ; PORT_FBOUT ; PORT_CONNECTIVITY ; Untyped ; ; PORT_PHASEDONE ; PORT_UNUSED ; Untyped ; ; PORT_PHASESTEP ; PORT_UNUSED ; Untyped ; ; PORT_PHASEUPDOWN ; PORT_UNUSED ; Untyped ; ; PORT_SCANCLKENA ; PORT_UNUSED ; Untyped ; ; PORT_PHASECOUNTERSELECT ; PORT_UNUSED ; Untyped ; ; PORT_VCOOVERRANGE ; PORT_CONNECTIVITY ; Untyped ; ; PORT_VCOUNDERRANGE ; PORT_CONNECTIVITY ; Untyped ; ; M_TEST_SOURCE ; 5 ; Untyped ; ; C0_TEST_SOURCE ; 5 ; Untyped ; ; C1_TEST_SOURCE ; 5 ; Untyped ; ; C2_TEST_SOURCE ; 5 ; Untyped ; ; C3_TEST_SOURCE ; 5 ; Untyped ; ; C4_TEST_SOURCE ; 5 ; Untyped ; ; C5_TEST_SOURCE ; 5 ; Untyped ; ; C6_TEST_SOURCE ; 5 ; Untyped ; ; C7_TEST_SOURCE ; 5 ; Untyped ; ; C8_TEST_SOURCE ; 5 ; Untyped ; ; C9_TEST_SOURCE ; 5 ; Untyped ; ; CBXI_PARAMETER ; pll20_altpll ; Untyped ; ; VCO_FREQUENCY_CONTROL ; AUTO ; Untyped ; ; VCO_PHASE_SHIFT_STEP ; 0 ; Untyped ; ; WIDTH_CLOCK ; 5 ; Signed Integer ; ; WIDTH_PHASECOUNTERSELECT ; 4 ; Untyped ; ; USING_FBMIMICBIDIR_PORT ; OFF ; Untyped ; ; DEVICE_FAMILY ; MAX 10 ; Untyped ; ; SCAN_CHAIN_MIF_FILE ; UNUSED ; Untyped ; ; SIM_GATE_LOCK_DEVICE_BEHAVIOR ; OFF ; Untyped ; ; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; ; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; ; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; ; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; +-------------------------------+-------------------------+------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +---------------------------------------------------------------------------------------+ ; altsyncram Parameter Settings by Entity Instance ; +-------------------------------------------+-------------------------------------------+ ; Name ; Value ; +-------------------------------------------+-------------------------------------------+ ; Number of entity instances ; 1 ; ; Entity Instance ; rom:inst1|altsyncram:altsyncram_component ; ; -- OPERATION_MODE ; ROM ; ; -- WIDTH_A ; 4 ; ; -- NUMWORDS_A ; 256 ; ; -- OUTDATA_REG_A ; UNREGISTERED ; ; -- WIDTH_B ; 1 ; ; -- NUMWORDS_B ; 1 ; ; -- ADDRESS_REG_B ; CLOCK1 ; ; -- OUTDATA_REG_B ; UNREGISTERED ; ; -- RAM_BLOCK_TYPE ; AUTO ; ; -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; +-------------------------------------------+-------------------------------------------+ +---------------------------------------------------------------------+ ; altpll Parameter Settings by Entity Instance ; +-------------------------------+-------------------------------------+ ; Name ; Value ; +-------------------------------+-------------------------------------+ ; Number of entity instances ; 1 ; ; Entity Instance ; pll20:inst7|altpll:altpll_component ; ; -- OPERATION_MODE ; NORMAL ; ; -- PLL_TYPE ; AUTO ; ; -- PRIMARY_CLOCK ; INCLK0 ; ; -- INCLK0_INPUT_FREQUENCY ; 20000 ; ; -- INCLK1_INPUT_FREQUENCY ; 0 ; ; -- VCO_MULTIPLY_BY ; 0 ; ; -- VCO_DIVIDE_BY ; 0 ; +-------------------------------+-------------------------------------+ +--------------------------------------------------------------------------------------------------------------------------------------+ ; In-System Memory Content Editor Settings ; +----------------+-------------+-------+-------+------------+--------------------------------------------------------------------------+ ; Instance Index ; Instance ID ; Width ; Depth ; Mode ; Hierarchy Location ; +----------------+-------------+-------+-------+------------+--------------------------------------------------------------------------+ ; 0 ; rom ; 4 ; 256 ; Read/Write ; rom:inst1|altsyncram:altsyncram_component|altsyncram_b8b1:auto_generated ; +----------------+-------------+-------+-------+------------+--------------------------------------------------------------------------+ +-----------------------------------------------------+ ; Post-Synthesis Netlist Statistics for Top Partition ; +-----------------------+-----------------------------+ ; Type ; Count ; +-----------------------+-----------------------------+ ; boundary_port ; 34 ; ; cycloneiii_ff ; 63 ; ; CLR ; 22 ; ; ENA ; 8 ; ; ENA CLR ; 7 ; ; ENA CLR SLD ; 8 ; ; ENA SCLR ; 5 ; ; SLD ; 11 ; ; plain ; 2 ; ; cycloneiii_lcell_comb ; 110 ; ; arith ; 34 ; ; 2 data inputs ; 32 ; ; 3 data inputs ; 2 ; ; normal ; 76 ; ; 0 data inputs ; 1 ; ; 1 data inputs ; 8 ; ; 2 data inputs ; 5 ; ; 3 data inputs ; 14 ; ; 4 data inputs ; 48 ; ; cycloneiii_pll ; 1 ; ; cycloneiii_ram_block ; 4 ; ; ; ; ; Max LUT depth ; 4.00 ; ; Average LUT depth ; 1.70 ; +-----------------------+-----------------------------+ +-------------------------------+ ; Elapsed Time Per Partition ; +----------------+--------------+ ; Partition Name ; Elapsed Time ; +----------------+--------------+ ; Top ; 00:00:00 ; +----------------+--------------+ +-------------------------------+ ; Analysis & Synthesis Messages ; +-------------------------------+ Info: ******************************************************************* Info: Running Quartus Prime Analysis & Synthesis Info: Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition Info: Processing started: Thu May 25 20:57:11 2023 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off music -c music Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Info (20030): Parallel compilation is enabled and will use 16 of the 16 processors detected Info (12021): Found 1 design units, including 1 entities, in source file music.bdf Info (12023): Found entity 1: music Info (12021): Found 1 design units, including 1 entities, in source file output_files/cnt138t.v Info (12023): Found entity 1: CNT138T File: E:/FPGA/Hardware-based Music Performing Circuit Project/output_files/CNT138T.v Line: 1 Info (12021): Found 1 design units, including 1 entities, in source file rom.v Info (12023): Found entity 1: rom File: E:/FPGA/Hardware-based Music Performing Circuit Project/rom.v Line: 39 Info (12021): Found 1 design units, including 1 entities, in source file f_code.v Info (12023): Found entity 1: F_CODE File: E:/FPGA/Hardware-based Music Performing Circuit Project/F_CODE.v Line: 1 Info (12021): Found 1 design units, including 1 entities, in source file spker.v Info (12023): Found entity 1: SPKER File: E:/FPGA/Hardware-based Music Performing Circuit Project/SPKER.v Line: 1 Info (12021): Found 1 design units, including 1 entities, in source file fdiv.v Info (12023): Found entity 1: FDIV File: E:/FPGA/Hardware-based Music Performing Circuit Project/FDIV.v Line: 1 Info (12021): Found 1 design units, including 1 entities, in source file pll20.v Info (12023): Found entity 1: pll20 File: E:/FPGA/Hardware-based Music Performing Circuit Project/pll20.v Line: 39 Warning (10236): Verilog HDL Implicit Net warning at FDIV.v(7): created implicit net for "DOUT" File: E:/FPGA/Hardware-based Music Performing Circuit Project/FDIV.v Line: 7 Info (12127): Elaborating entity "music" for the top level hierarchy Info (12128): Elaborating entity "F_CODE" for hierarchy "F_CODE:inst2" Info (12128): Elaborating entity "rom" for hierarchy "rom:inst1" Info (12128): Elaborating entity "altsyncram" for hierarchy "rom:inst1|altsyncram:altsyncram_component" File: E:/FPGA/Hardware-based Music Performing Circuit Project/rom.v Line: 81 Info (12130): Elaborated megafunction instantiation "rom:inst1|altsyncram:altsyncram_component" File: E:/FPGA/Hardware-based Music Performing Circuit Project/rom.v Line: 81 Info (12133): Instantiated megafunction "rom:inst1|altsyncram:altsyncram_component" with the following parameter: File: E:/FPGA/Hardware-based Music Performing Circuit Project/rom.v Line: 81 Info (12134): Parameter "address_aclr_a" = "NONE" Info (12134): Parameter "clock_enable_input_a" = "BYPASS" Info (12134): Parameter "clock_enable_output_a" = "BYPASS" Info (12134): Parameter "init_file" = "../music.mif" Info (12134): Parameter "intended_device_family" = "Cyclone 10 LP" Info (12134): Parameter "lpm_hint" = "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=rom" Info (12134): Parameter "lpm_type" = "altsyncram" Info (12134): Parameter "numwords_a" = "256" Info (12134): Parameter "operation_mode" = "ROM" Info (12134): Parameter "outdata_aclr_a" = "NONE" Info (12134): Parameter "outdata_reg_a" = "UNREGISTERED" Info (12134): Parameter "widthad_a" = "8" Info (12134): Parameter "width_a" = "4" Info (12134): Parameter "width_byteena_a" = "1" Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_b8b1.tdf Info (12023): Found entity 1: altsyncram_b8b1 File: E:/FPGA/Hardware-based Music Performing Circuit Project/db/altsyncram_b8b1.tdf Line: 27 Info (12128): Elaborating entity "altsyncram_b8b1" for hierarchy "rom:inst1|altsyncram:altsyncram_component|altsyncram_b8b1:auto_generated" File: d:/intelfpga_lite/18.1/quartus/libraries/megafunctions/altsyncram.tdf Line: 791 Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_5oc2.tdf Info (12023): Found entity 1: altsyncram_5oc2 File: E:/FPGA/Hardware-based Music Performing Circuit Project/db/altsyncram_5oc2.tdf Line: 27 Info (12128): Elaborating entity "altsyncram_5oc2" for hierarchy "rom:inst1|altsyncram:altsyncram_component|altsyncram_b8b1:auto_generated|altsyncram_5oc2:altsyncram1" File: E:/FPGA/Hardware-based Music Performing Circuit Project/db/altsyncram_b8b1.tdf Line: 34 Info (12128): Elaborating entity "sld_mod_ram_rom" for hierarchy "rom:inst1|altsyncram:altsyncram_component|altsyncram_b8b1:auto_generated|sld_mod_ram_rom:mgl_prim2" File: E:/FPGA/Hardware-based Music Performing Circuit Project/db/altsyncram_b8b1.tdf Line: 35 Info (12130): Elaborated megafunction instantiation "rom:inst1|altsyncram:altsyncram_component|altsyncram_b8b1:auto_generated|sld_mod_ram_rom:mgl_prim2" File: E:/FPGA/Hardware-based Music Performing Circuit Project/db/altsyncram_b8b1.tdf Line: 35 Info (12133): Instantiated megafunction "rom:inst1|altsyncram:altsyncram_component|altsyncram_b8b1:auto_generated|sld_mod_ram_rom:mgl_prim2" with the following parameter: File: E:/FPGA/Hardware-based Music Performing Circuit Project/db/altsyncram_b8b1.tdf Line: 35 Info (12134): Parameter "CVALUE" = "0000" Info (12134): Parameter "IS_DATA_IN_RAM" = "1" Info (12134): Parameter "IS_READABLE" = "1" Info (12134): Parameter "NODE_NAME" = "1919905024" Info (12134): Parameter "NUMWORDS" = "256" Info (12134): Parameter "SHIFT_COUNT_BITS" = "3" Info (12134): Parameter "WIDTH_WORD" = "4" Info (12134): Parameter "WIDTHAD" = "8" Info (12128): Elaborating entity "sld_jtag_endpoint_adapter" for hierarchy "rom:inst1|altsyncram:altsyncram_component|altsyncram_b8b1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_jtag_endpoint_adapter:jtag_signal_adapter" File: d:/intelfpga_lite/18.1/quartus/libraries/megafunctions/sld_mod_ram_rom.vhd Line: 302 Info (12128): Elaborating entity "sld_jtag_endpoint_adapter_impl" for hierarchy "rom:inst1|altsyncram:altsyncram_component|altsyncram_b8b1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_jtag_endpoint_adapter:jtag_signal_adapter|sld_jtag_endpoint_adapter_impl:sld_jtag_endpoint_adapter_impl_inst" File: d:/intelfpga_lite/18.1/quartus/libraries/megafunctions/sld_jtag_endpoint_adapter.vhd Line: 232 Info (12128): Elaborating entity "sld_rom_sr" for hierarchy "rom:inst1|altsyncram:altsyncram_component|altsyncram_b8b1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:name_gen:info_rom_sr" File: d:/intelfpga_lite/18.1/quartus/libraries/megafunctions/sld_mod_ram_rom.vhd Line: 828 Info (12128): Elaborating entity "FDIV" for hierarchy "FDIV:inst4" Warning (10036): Verilog HDL or VHDL warning at FDIV.v(7): object "DOUT" assigned a value but never read File: E:/FPGA/Hardware-based Music Performing Circuit Project/FDIV.v Line: 7 Warning (10230): Verilog HDL assignment warning at FDIV.v(5): truncated value with size 32 to match size of target (9) File: E:/FPGA/Hardware-based Music Performing Circuit Project/FDIV.v Line: 5 Warning (10230): Verilog HDL assignment warning at FDIV.v(7): truncated value with size 9 to match size of target (1) File: E:/FPGA/Hardware-based Music Performing Circuit Project/FDIV.v Line: 7 Info (12128): Elaborating entity "pll20" for hierarchy "pll20:inst7" Info (12128): Elaborating entity "altpll" for hierarchy "pll20:inst7|altpll:altpll_component" File: E:/FPGA/Hardware-based Music Performing Circuit Project/pll20.v Line: 94 Info (12130): Elaborated megafunction instantiation "pll20:inst7|altpll:altpll_component" File: E:/FPGA/Hardware-based Music Performing Circuit Project/pll20.v Line: 94 Info (12133): Instantiated megafunction "pll20:inst7|altpll:altpll_component" with the following parameter: File: E:/FPGA/Hardware-based Music Performing Circuit Project/pll20.v Line: 94 Info (12134): Parameter "bandwidth_type" = "AUTO" Info (12134): Parameter "clk0_divide_by" = "70" Info (12134): Parameter "clk0_duty_cycle" = "50" Info (12134): Parameter "clk0_multiply_by" = "1" Info (12134): Parameter "clk0_phase_shift" = "0" Info (12134): Parameter "clk1_divide_by" = "10000" Info (12134): Parameter "clk1_duty_cycle" = "50" Info (12134): Parameter "clk1_multiply_by" = "1" Info (12134): Parameter "clk1_phase_shift" = "0" Info (12134): Parameter "compensate_clock" = "CLK0" Info (12134): Parameter "inclk0_input_frequency" = "20000" Info (12134): Parameter "intended_device_family" = "Cyclone 10 LP" Info (12134): Parameter "lpm_hint" = "CBX_MODULE_PREFIX=pll20" Info (12134): Parameter "lpm_type" = "altpll" Info (12134): Parameter "operation_mode" = "NORMAL" Info (12134): Parameter "pll_type" = "AUTO" Info (12134): Parameter "port_activeclock" = "PORT_UNUSED" Info (12134): Parameter "port_areset" = "PORT_UNUSED" Info (12134): Parameter "port_clkbad0" = "PORT_UNUSED" Info (12134): Parameter "port_clkbad1" = "PORT_UNUSED" Info (12134): Parameter "port_clkloss" = "PORT_UNUSED" Info (12134): Parameter "port_clkswitch" = "PORT_UNUSED" Info (12134): Parameter "port_configupdate" = "PORT_UNUSED" Info (12134): Parameter "port_fbin" = "PORT_UNUSED" Info (12134): Parameter "port_inclk0" = "PORT_USED" Info (12134): Parameter "port_inclk1" = "PORT_UNUSED" Info (12134): Parameter "port_locked" = "PORT_UNUSED" Info (12134): Parameter "port_pfdena" = "PORT_UNUSED" Info (12134): Parameter "port_phasecounterselect" = "PORT_UNUSED" Info (12134): Parameter "port_phasedone" = "PORT_UNUSED" Info (12134): Parameter "port_phasestep" = "PORT_UNUSED" Info (12134): Parameter "port_phaseupdown" = "PORT_UNUSED" Info (12134): Parameter "port_pllena" = "PORT_UNUSED" Info (12134): Parameter "port_scanaclr" = "PORT_UNUSED" Info (12134): Parameter "port_scanclk" = "PORT_UNUSED" Info (12134): Parameter "port_scanclkena" = "PORT_UNUSED" Info (12134): Parameter "port_scandata" = "PORT_UNUSED" Info (12134): Parameter "port_scandataout" = "PORT_UNUSED" Info (12134): Parameter "port_scandone" = "PORT_UNUSED" Info (12134): Parameter "port_scanread" = "PORT_UNUSED" Info (12134): Parameter "port_scanwrite" = "PORT_UNUSED" Info (12134): Parameter "port_clk0" = "PORT_USED" Info (12134): Parameter "port_clk1" = "PORT_USED" Info (12134): Parameter "port_clk2" = "PORT_UNUSED" Info (12134): Parameter "port_clk3" = "PORT_UNUSED" Info (12134): Parameter "port_clk4" = "PORT_UNUSED" Info (12134): Parameter "port_clk5" = "PORT_UNUSED" Info (12134): Parameter "port_clkena0" = "PORT_UNUSED" Info (12134): Parameter "port_clkena1" = "PORT_UNUSED" Info (12134): Parameter "port_clkena2" = "PORT_UNUSED" Info (12134): Parameter "port_clkena3" = "PORT_UNUSED" Info (12134): Parameter "port_clkena4" = "PORT_UNUSED" Info (12134): Parameter "port_clkena5" = "PORT_UNUSED" Info (12134): Parameter "port_extclk0" = "PORT_UNUSED" Info (12134): Parameter "port_extclk1" = "PORT_UNUSED" Info (12134): Parameter "port_extclk2" = "PORT_UNUSED" Info (12134): Parameter "port_extclk3" = "PORT_UNUSED" Info (12134): Parameter "width_clock" = "5" Info (12021): Found 1 design units, including 1 entities, in source file db/pll20_altpll.v Info (12023): Found entity 1: pll20_altpll File: E:/FPGA/Hardware-based Music Performing Circuit Project/db/pll20_altpll.v Line: 29 Info (12128): Elaborating entity "pll20_altpll" for hierarchy "pll20:inst7|altpll:altpll_component|pll20_altpll:auto_generated" File: d:/intelfpga_lite/18.1/quartus/libraries/megafunctions/altpll.tdf Line: 897 Info (12128): Elaborating entity "CNT138T" for hierarchy "CNT138T:inst" Warning (10230): Verilog HDL assignment warning at CNT138T.v(4): truncated value with size 32 to match size of target (8) File: E:/FPGA/Hardware-based Music Performing Circuit Project/output_files/CNT138T.v Line: 4 Info (12128): Elaborating entity "SPKER" for hierarchy "SPKER:inst3" Warning (10230): Verilog HDL assignment warning at SPKER.v(6): truncated value with size 32 to match size of target (11) File: E:/FPGA/Hardware-based Music Performing Circuit Project/SPKER.v Line: 6 Info (11170): Starting IP generation for the debug fabric: alt_sld_fab. Info (11172): 2023.05.25.20:57:25 Progress: Loading sld63346dfb/alt_sld_fab_wrapper_hw.tcl Info (11172): Alt_sld_fab.alt_sld_fab: SLD fabric agents which did not specify prefer_host were connected to JTAG Info (11172): Alt_sld_fab: Generating alt_sld_fab "alt_sld_fab" for QUARTUS_SYNTH Info (11172): Alt_sld_fab: "alt_sld_fab" instantiated alt_sld_fab "alt_sld_fab" Info (11172): Presplit: "alt_sld_fab" instantiated altera_super_splitter "presplit" Info (11172): Splitter: "alt_sld_fab" instantiated altera_sld_splitter "splitter" Info (11172): Sldfabric: "alt_sld_fab" instantiated altera_sld_jtag_hub "sldfabric" Info (11172): Ident: "alt_sld_fab" instantiated altera_connection_identification_hub "ident" Info (11172): Alt_sld_fab: Done "alt_sld_fab" with 6 modules, 6 files Info (11171): Finished IP generation for the debug fabric: alt_sld_fab. Info (12021): Found 1 design units, including 1 entities, in source file db/ip/sld63346dfb/alt_sld_fab.v Info (12023): Found entity 1: alt_sld_fab File: E:/FPGA/Hardware-based Music Performing Circuit Project/db/ip/sld63346dfb/alt_sld_fab.v Line: 9 Info (12021): Found 1 design units, including 1 entities, in source file db/ip/sld63346dfb/submodules/alt_sld_fab_alt_sld_fab.v Info (12023): Found entity 1: alt_sld_fab_alt_sld_fab File: E:/FPGA/Hardware-based Music Performing Circuit Project/db/ip/sld63346dfb/submodules/alt_sld_fab_alt_sld_fab.v Line: 9 Info (12021): Found 1 design units, including 1 entities, in source file db/ip/sld63346dfb/submodules/alt_sld_fab_alt_sld_fab_ident.sv Info (12023): Found entity 1: alt_sld_fab_alt_sld_fab_ident File: E:/FPGA/Hardware-based Music Performing Circuit Project/db/ip/sld63346dfb/submodules/alt_sld_fab_alt_sld_fab_ident.sv Line: 33 Info (12021): Found 1 design units, including 1 entities, in source file db/ip/sld63346dfb/submodules/alt_sld_fab_alt_sld_fab_presplit.sv Info (12023): Found entity 1: alt_sld_fab_alt_sld_fab_presplit File: E:/FPGA/Hardware-based Music Performing Circuit Project/db/ip/sld63346dfb/submodules/alt_sld_fab_alt_sld_fab_presplit.sv Line: 3 Info (12021): Found 2 design units, including 1 entities, in source file db/ip/sld63346dfb/submodules/alt_sld_fab_alt_sld_fab_sldfabric.vhd Info (12022): Found design unit 1: alt_sld_fab_alt_sld_fab_sldfabric-rtl File: E:/FPGA/Hardware-based Music Performing Circuit Project/db/ip/sld63346dfb/submodules/alt_sld_fab_alt_sld_fab_sldfabric.vhd Line: 102 Info (12023): Found entity 1: alt_sld_fab_alt_sld_fab_sldfabric File: E:/FPGA/Hardware-based Music Performing Circuit Project/db/ip/sld63346dfb/submodules/alt_sld_fab_alt_sld_fab_sldfabric.vhd Line: 11 Info (12021): Found 1 design units, including 1 entities, in source file db/ip/sld63346dfb/submodules/alt_sld_fab_alt_sld_fab_splitter.sv Info (12023): Found entity 1: alt_sld_fab_alt_sld_fab_splitter File: E:/FPGA/Hardware-based Music Performing Circuit Project/db/ip/sld63346dfb/submodules/alt_sld_fab_alt_sld_fab_splitter.sv Line: 3 Info (13000): Registers with preset signals will power-up high File: E:/FPGA/Hardware-based Music Performing Circuit Project/FDIV.v Line: 5 Info (13003): DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back Warning (13024): Output pins are stuck at VCC or GND Warning (13410): Pin "LED[3]" is stuck at GND Info (286031): Timing-Driven Synthesis is running on partition "Top" Info (144001): Generated suppressed messages file E:/FPGA/Hardware-based Music Performing Circuit Project/output_files/music.map.smsg Info (16010): Generating hard_block partition "hard_block:auto_generated_inst" Info (16011): Adding 1 node(s), including 0 DDIO, 1 PLL, 0 transceiver and 0 LCELL Error (16031): Current Internal Configuration mode does not support memory initialization or ROM. Select Internal Configuration mode with ERAM. File: E:/FPGA/Hardware-based Music Performing Circuit Project/db/altsyncram_5oc2.tdf Line: 34 Error (16031): Current Internal Configuration mode does not support memory initialization or ROM. Select Internal Configuration mode with ERAM. File: E:/FPGA/Hardware-based Music Performing Circuit Project/db/altsyncram_5oc2.tdf Line: 34 Error (16031): Current Internal Configuration mode does not support memory initialization or ROM. Select Internal Configuration mode with ERAM. File: E:/FPGA/Hardware-based Music Performing Circuit Project/db/altsyncram_5oc2.tdf Line: 34 Error (16031): Current Internal Configuration mode does not support memory initialization or ROM. Select Internal Configuration mode with ERAM. File: E:/FPGA/Hardware-based Music Performing Circuit Project/db/altsyncram_5oc2.tdf Line: 34 Error: Quartus Prime Analysis & Synthesis was unsuccessful. 4 errors, 9 warnings Error: Peak virtual memory: 4876 megabytes Error: Processing ended: Thu May 25 20:57:38 2023 Error: Elapsed time: 00:00:27 Error: Total CPU time (on all processors): 00:00:45 +------------------------------------------+ ; Analysis & Synthesis Suppressed Messages ; +------------------------------------------+ The suppressed messages can be found in E:/FPGA/Hardware-based Music Performing Circuit Project/output_files/music.map.smsg.