{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1546840322013 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition " "Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1546840322024 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Jan 07 13:52:01 2019 " "Processing started: Mon Jan 07 13:52:01 2019" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1546840322024 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1546840322024 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off traffic -c traffic " "Command: quartus_map --read_settings_files=on --write_settings_files=off traffic -c traffic" {  } {  } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1546840322024 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1546840322934 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1546840322934 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "clk1h CLK1H traffic.v(47) " "Verilog HDL Declaration information at traffic.v(47): object \"clk1h\" differs only in case from object \"CLK1H\" in the same scope" {  } { { "traffic.v" "" { Text "E:/fpgaproject/stepmax10/workshop/lab10/traffic.v" 47 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1546840335129 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "traffic.v 1 1 " "Found 1 design units, including 1 entities, in source file traffic.v" { { "Info" "ISGN_ENTITY_NAME" "1 traffic " "Found entity 1: traffic" {  } { { "traffic.v" "" { Text "E:/fpgaproject/stepmax10/workshop/lab10/traffic.v" 19 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1546840335131 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1546840335131 ""}
{ "Warning" "WSGN_MEGAFN_REPLACE" "divide divide.v " "Entity \"divide\" obtained from \"divide.v\" instead of from Quartus Prime megafunction library" {  } { { "divide.v" "" { Text "E:/fpgaproject/stepmax10/workshop/lab10/divide.v" 18 -1 0 } }  } 0 12090 "Entity \"%1!s!\" obtained from \"%2!s!\" instead of from Quartus Prime megafunction library" 0 0 "Analysis & Synthesis" 0 -1 1546840335136 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "divide.v 1 1 " "Found 1 design units, including 1 entities, in source file divide.v" { { "Info" "ISGN_ENTITY_NAME" "1 divide " "Found entity 1: divide" {  } { { "divide.v" "" { Text "E:/fpgaproject/stepmax10/workshop/lab10/divide.v" 18 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1546840335137 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1546840335137 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "traffic " "Elaborating entity \"traffic\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1546840335176 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 traffic.v(117) " "Verilog HDL assignment warning at traffic.v(117): truncated value with size 32 to match size of target (4)" {  } { { "traffic.v" "" { Text "E:/fpgaproject/stepmax10/workshop/lab10/traffic.v" 117 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1546840335177 "|traffic"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 traffic.v(125) " "Verilog HDL assignment warning at traffic.v(125): truncated value with size 32 to match size of target (4)" {  } { { "traffic.v" "" { Text "E:/fpgaproject/stepmax10/workshop/lab10/traffic.v" 125 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1546840335177 "|traffic"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 traffic.v(133) " "Verilog HDL assignment warning at traffic.v(133): truncated value with size 32 to match size of target (4)" {  } { { "traffic.v" "" { Text "E:/fpgaproject/stepmax10/workshop/lab10/traffic.v" 133 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1546840335177 "|traffic"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 traffic.v(141) " "Verilog HDL assignment warning at traffic.v(141): truncated value with size 32 to match size of target (4)" {  } { { "traffic.v" "" { Text "E:/fpgaproject/stepmax10/workshop/lab10/traffic.v" 141 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1546840335178 "|traffic"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "divide divide:CLK1H " "Elaborating entity \"divide\" for hierarchy \"divide:CLK1H\"" {  } { { "traffic.v" "CLK1H" { Text "E:/fpgaproject/stepmax10/workshop/lab10/traffic.v" 53 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1546840335179 ""}
{ "Info" "IMLS_MLS_PRESET_POWER_UP" "" "Registers with preset signals will power-up high" {  } { { "traffic.v" "" { Text "E:/fpgaproject/stepmax10/workshop/lab10/traffic.v" 111 -1 0 } }  } 0 13000 "Registers with preset signals will power-up high" 0 0 "Analysis & Synthesis" 0 -1 1546840335607 ""}
{ "Info" "IMLS_MLS_DEV_CLRN_SETS_REGISTERS" "" "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" {  } {  } 0 13003 "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" 0 0 "Analysis & Synthesis" 0 -1 1546840335607 ""}
{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" {  } {  } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1546840335701 ""}
{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "2 " "2 registers lost all their fanouts during netlist optimizations." {  } {  } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Analysis & Synthesis" 0 -1 1546840336059 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "E:/fpgaproject/stepmax10/workshop/lab10/output_files/traffic.map.smsg " "Generated suppressed messages file E:/fpgaproject/stepmax10/workshop/lab10/output_files/traffic.map.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1546840336083 ""}
{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1546840336190 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1546840336190 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "90 " "Implemented 90 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "2 " "Implemented 2 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1546840336243 ""} { "Info" "ICUT_CUT_TM_OPINS" "6 " "Implemented 6 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1546840336243 ""} { "Info" "ICUT_CUT_TM_LCELLS" "82 " "Implemented 82 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1546840336243 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1546840336243 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 6 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4761 " "Peak virtual memory: 4761 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1546840336267 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Jan 07 13:52:16 2019 " "Processing ended: Mon Jan 07 13:52:16 2019" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1546840336267 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:15 " "Elapsed time: 00:00:15" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1546840336267 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:30 " "Total CPU time (on all processors): 00:00:30" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1546840336267 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1546840336267 ""}