# -------------------------------------------------------------------------- #
#
# Copyright (C) 2017  Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Intel Program License 
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors.  Please
# refer to the applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition
# Date created = 10:28:03  January 07, 2019
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
#		segment_assignment_defaults.qdf
#    If this file doesn't exist, see file:
#		assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
#    file is updated automatically by the Quartus Prime software
#    and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #


set_global_assignment -name FAMILY "MAX 10"
set_global_assignment -name DEVICE 10M08SCM153C8G
set_global_assignment -name TOP_LEVEL_ENTITY segment
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 17.1.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:28:03  JANUARY 07, 2019"
set_global_assignment -name LAST_QUARTUS_VERSION "17.1.0 Lite Edition"
set_global_assignment -name VERILOG_FILE segment.v
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name DEVICE_FILTER_PACKAGE MBGA
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_location_assignment PIN_H13 -to seg_data_1[3]
set_location_assignment PIN_H12 -to seg_data_1[2]
set_location_assignment PIN_H11 -to seg_data_1[1]
set_location_assignment PIN_J12 -to seg_data_1[0]
set_location_assignment PIN_J14 -to seg_data_2[3]
set_location_assignment PIN_J11 -to seg_data_2[2]
set_location_assignment PIN_K14 -to seg_data_2[1]
set_location_assignment PIN_J9 -to seg_data_2[0]
set_location_assignment PIN_E1 -to seg_led_1[0]
set_location_assignment PIN_D2 -to seg_led_1[1]
set_location_assignment PIN_K2 -to seg_led_1[2]
set_location_assignment PIN_J2 -to seg_led_1[3]
set_location_assignment PIN_G2 -to seg_led_1[4]
set_location_assignment PIN_F5 -to seg_led_1[5]
set_location_assignment PIN_G5 -to seg_led_1[6]
set_location_assignment PIN_L1 -to seg_led_1[7]
set_location_assignment PIN_E2 -to seg_led_1[8]
set_location_assignment PIN_B1 -to seg_led_2[8]
set_location_assignment PIN_R2 -to seg_led_2[7]
set_location_assignment PIN_C2 -to seg_led_2[6]
set_location_assignment PIN_C1 -to seg_led_2[5]
set_location_assignment PIN_N1 -to seg_led_2[4]
set_location_assignment PIN_P1 -to seg_led_2[3]
set_location_assignment PIN_P2 -to seg_led_2[2]
set_location_assignment PIN_A2 -to seg_led_2[1]
set_location_assignment PIN_A3 -to seg_led_2[0]
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top