Info: Start Nativelink Simulation process
Info: NativeLink has detected Verilog design -- Verilog simulation models will be used

========= EDA Simulation Settings =====================

Sim Mode              :  RTL
Family                :  max10
Quartus root          :  e:/intelfpga_lite/17.1/quartus/bin64/
Quartus sim root      :  e:/intelfpga_lite/17.1/quartus/eda/sim_lib
Simulation Tool       :  modelsim-altera
Simulation Language   :  verilog
Simulation Mode       :  GUI
Sim Output File       :  
Sim SDF file          :  
Sim dir               :  simulation\modelsim

=======================================================

Info: Starting NativeLink simulation with ModelSim-Altera software
Sourced NativeLink script e:/intelfpga_lite/17.1/quartus/common/tcl/internal/nativelink/modelsim.tcl
Warning: File divide_run_msim_rtl_verilog.do already exists - backing up current file as divide_run_msim_rtl_verilog.do.bak
Info: Spawning ModelSim-Altera Simulation software 
Info: NativeLink simulation flow was successful