{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1546829871584 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition " "Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1546829871595 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Jan 07 10:57:51 2019 " "Processing started: Mon Jan 07 10:57:51 2019" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1546829871595 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1546829871595 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off flashled -c flashled " "Command: quartus_map --read_settings_files=on --write_settings_files=off flashled -c flashled" {  } {  } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1546829871595 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1546829872441 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1546829872442 ""}
{ "Warning" "WSGN_MEGAFN_REPLACE" "divide divide.v " "Entity \"divide\" obtained from \"divide.v\" instead of from Quartus Prime megafunction library" {  } { { "divide.v" "" { Text "E:/fpgaproject/stepmax10/workshop/lab6/divide.v" 18 -1 0 } }  } 0 12090 "Entity \"%1!s!\" obtained from \"%2!s!\" instead of from Quartus Prime megafunction library" 0 0 "Analysis & Synthesis" 0 -1 1546829884708 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "divide.v 1 1 " "Found 1 design units, including 1 entities, in source file divide.v" { { "Info" "ISGN_ENTITY_NAME" "1 divide " "Found entity 1: divide" {  } { { "divide.v" "" { Text "E:/fpgaproject/stepmax10/workshop/lab6/divide.v" 18 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1546829884708 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1546829884708 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "decode38.v 1 1 " "Found 1 design units, including 1 entities, in source file decode38.v" { { "Info" "ISGN_ENTITY_NAME" "1 decode38 " "Found entity 1: decode38" {  } { { "decode38.v" "" { Text "E:/fpgaproject/stepmax10/workshop/lab6/decode38.v" 18 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1546829884713 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1546829884713 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "flashled.v 1 1 " "Found 1 design units, including 1 entities, in source file flashled.v" { { "Info" "ISGN_ENTITY_NAME" "1 flashled " "Found entity 1: flashled" {  } { { "flashled.v" "" { Text "E:/fpgaproject/stepmax10/workshop/lab6/flashled.v" 18 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1546829884718 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1546829884718 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "flashled " "Elaborating entity \"flashled\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1546829884757 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 flashled.v(46) " "Verilog HDL assignment warning at flashled.v(46): truncated value with size 32 to match size of target (3)" {  } { { "flashled.v" "" { Text "E:/fpgaproject/stepmax10/workshop/lab6/flashled.v" 46 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1546829884758 "|flashled"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "decode38 decode38:u1 " "Elaborating entity \"decode38\" for hierarchy \"decode38:u1\"" {  } { { "flashled.v" "u1" { Text "E:/fpgaproject/stepmax10/workshop/lab6/flashled.v" 32 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1546829884760 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "divide divide:u2 " "Elaborating entity \"divide\" for hierarchy \"divide:u2\"" {  } { { "flashled.v" "u2" { Text "E:/fpgaproject/stepmax10/workshop/lab6/flashled.v" 39 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1546829884762 ""}
{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" {  } {  } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1546829885252 ""}
{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1546829885720 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1546829885720 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "80 " "Implemented 80 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "2 " "Implemented 2 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1546829885779 ""} { "Info" "ICUT_CUT_TM_OPINS" "8 " "Implemented 8 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1546829885779 ""} { "Info" "ICUT_CUT_TM_LCELLS" "70 " "Implemented 70 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1546829885779 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1546829885779 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 3 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4760 " "Peak virtual memory: 4760 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1546829885798 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Jan 07 10:58:05 2019 " "Processing ended: Mon Jan 07 10:58:05 2019" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1546829885798 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:14 " "Elapsed time: 00:00:14" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1546829885798 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:30 " "Total CPU time (on all processors): 00:00:30" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1546829885798 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1546829885798 ""}