{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1546839351788 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition " "Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1546839351800 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Jan 07 13:35:51 2019 " "Processing started: Mon Jan 07 13:35:51 2019" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1546839351800 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1546839351800 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off counter -c counter " "Command: quartus_map --read_settings_files=on --write_settings_files=off counter -c counter" {  } {  } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1546839351800 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1546839352653 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1546839352653 ""}
{ "Warning" "WSGN_MEGAFN_REPLACE" "divide divide.v " "Entity \"divide\" obtained from \"divide.v\" instead of from Quartus Prime megafunction library" {  } { { "divide.v" "" { Text "E:/fpgaproject/stepmax10/workshop/lab8/divide.v" 18 -1 0 } }  } 0 12090 "Entity \"%1!s!\" obtained from \"%2!s!\" instead of from Quartus Prime megafunction library" 0 0 "Analysis & Synthesis" 0 -1 1546839364361 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "divide.v 1 1 " "Found 1 design units, including 1 entities, in source file divide.v" { { "Info" "ISGN_ENTITY_NAME" "1 divide " "Found entity 1: divide" {  } { { "divide.v" "" { Text "E:/fpgaproject/stepmax10/workshop/lab8/divide.v" 18 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1546839364362 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1546839364362 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "debounce.v 1 1 " "Found 1 design units, including 1 entities, in source file debounce.v" { { "Info" "ISGN_ENTITY_NAME" "1 debounce " "Found entity 1: debounce" {  } { { "debounce.v" "" { Text "E:/fpgaproject/stepmax10/workshop/lab8/debounce.v" 18 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1546839364367 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1546839364367 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "counter.v 1 1 " "Found 1 design units, including 1 entities, in source file counter.v" { { "Info" "ISGN_ENTITY_NAME" "1 counter " "Found entity 1: counter" {  } { { "counter.v" "" { Text "E:/fpgaproject/stepmax10/workshop/lab8/counter.v" 18 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1546839364372 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1546839364372 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "counter " "Elaborating entity \"counter\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1546839364418 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 counter.v(108) " "Verilog HDL assignment warning at counter.v(108): truncated value with size 32 to match size of target (4)" {  } { { "counter.v" "" { Text "E:/fpgaproject/stepmax10/workshop/lab8/counter.v" 108 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1546839364421 "|counter"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 counter.v(110) " "Verilog HDL assignment warning at counter.v(110): truncated value with size 32 to match size of target (4)" {  } { { "counter.v" "" { Text "E:/fpgaproject/stepmax10/workshop/lab8/counter.v" 110 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1546839364421 "|counter"}
{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "seg.data_a 0 counter.v(38) " "Net \"seg.data_a\" at counter.v(38) has no driver or initial value, using a default initial value '0'" {  } { { "counter.v" "" { Text "E:/fpgaproject/stepmax10/workshop/lab8/counter.v" 38 0 0 } }  } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Analysis & Synthesis" 0 -1 1546839364422 "|counter"}
{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "seg.waddr_a 0 counter.v(38) " "Net \"seg.waddr_a\" at counter.v(38) has no driver or initial value, using a default initial value '0'" {  } { { "counter.v" "" { Text "E:/fpgaproject/stepmax10/workshop/lab8/counter.v" 38 0 0 } }  } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Analysis & Synthesis" 0 -1 1546839364422 "|counter"}
{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "seg.we_a 0 counter.v(38) " "Net \"seg.we_a\" at counter.v(38) has no driver or initial value, using a default initial value '0'" {  } { { "counter.v" "" { Text "E:/fpgaproject/stepmax10/workshop/lab8/counter.v" 38 0 0 } }  } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Analysis & Synthesis" 0 -1 1546839364422 "|counter"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "debounce debounce:U2 " "Elaborating entity \"debounce\" for hierarchy \"debounce:U2\"" {  } { { "counter.v" "U2" { Text "E:/fpgaproject/stepmax10/workshop/lab8/counter.v" 71 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1546839364436 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "divide divide:U1 " "Elaborating entity \"divide\" for hierarchy \"divide:U1\"" {  } { { "counter.v" "U1" { Text "E:/fpgaproject/stepmax10/workshop/lab8/counter.v" 77 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1546839364450 ""}
{ "Critical Warning" "WCDB_CDB_LESS_INI_CONTENT" "16 10 E:/fpgaproject/stepmax10/workshop/lab8/db/counter.ram0_counter_4830daf4.hdl.mif " "Memory depth (16) in the design file differs from memory depth (10) in the Memory Initialization File \"E:/fpgaproject/stepmax10/workshop/lab8/db/counter.ram0_counter_4830daf4.hdl.mif\" -- setting initial value for remaining addresses to 0" {  } {  } 1 127005 "Memory depth (%1!d!) in the design file differs from memory depth (%2!d!) in the Memory Initialization File \"%3!s!\" -- setting initial value for remaining addresses to 0" 0 0 "Analysis & Synthesis" 0 -1 1546839364670 ""}
{ "Info" "IINFER_UNINFERRED_RAM_SUMMARY" "1 " "Found 1 instances of uninferred RAM logic" { { "Info" "IINFER_MIF_NOT_SUPPORTED_FOR_HARDCOPY" "seg " "RAM logic \"seg\" is uninferred because MIF is not supported for the selected family" {  } { { "counter.v" "seg" { Text "E:/fpgaproject/stepmax10/workshop/lab8/counter.v" 38 -1 0 } }  } 0 276013 "RAM logic \"%1!s!\" is uninferred because MIF is not supported for the selected family" 0 0 "Design Software" 0 -1 1546839364689 ""}  } {  } 0 276014 "Found %1!d! instances of uninferred RAM logic" 0 0 "Analysis & Synthesis" 0 -1 1546839364689 ""}
{ "Info" "IMLS_MLS_PRESET_POWER_UP" "" "Registers with preset signals will power-up high" {  } { { "counter.v" "" { Text "E:/fpgaproject/stepmax10/workshop/lab8/counter.v" 98 -1 0 } } { "debounce.v" "" { Text "E:/fpgaproject/stepmax10/workshop/lab8/debounce.v" 78 -1 0 } } { "debounce.v" "" { Text "E:/fpgaproject/stepmax10/workshop/lab8/debounce.v" 70 -1 0 } } { "debounce.v" "" { Text "E:/fpgaproject/stepmax10/workshop/lab8/debounce.v" 40 -1 0 } }  } 0 13000 "Registers with preset signals will power-up high" 0 0 "Analysis & Synthesis" 0 -1 1546839364916 ""}
{ "Info" "IMLS_MLS_DEV_CLRN_SETS_REGISTERS" "" "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" {  } {  } 0 13003 "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" 0 0 "Analysis & Synthesis" 0 -1 1546839364916 ""}
{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "seg_led_1\[7\] GND " "Pin \"seg_led_1\[7\]\" is stuck at GND" {  } { { "counter.v" "" { Text "E:/fpgaproject/stepmax10/workshop/lab8/counter.v" 31 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1546839364945 "|counter|seg_led_1[7]"} { "Warning" "WMLS_MLS_STUCK_PIN" "seg_led_1\[8\] GND " "Pin \"seg_led_1\[8\]\" is stuck at GND" {  } { { "counter.v" "" { Text "E:/fpgaproject/stepmax10/workshop/lab8/counter.v" 31 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1546839364945 "|counter|seg_led_1[8]"} { "Warning" "WMLS_MLS_STUCK_PIN" "seg_led_2\[7\] GND " "Pin \"seg_led_2\[7\]\" is stuck at GND" {  } { { "counter.v" "" { Text "E:/fpgaproject/stepmax10/workshop/lab8/counter.v" 31 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1546839364945 "|counter|seg_led_2[7]"} { "Warning" "WMLS_MLS_STUCK_PIN" "seg_led_2\[8\] GND " "Pin \"seg_led_2\[8\]\" is stuck at GND" {  } { { "counter.v" "" { Text "E:/fpgaproject/stepmax10/workshop/lab8/counter.v" 31 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1546839364945 "|counter|seg_led_2[8]"}  } {  } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Analysis & Synthesis" 0 -1 1546839364945 ""}
{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" {  } {  } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1546839365005 ""}
{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1546839365521 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1546839365521 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "148 " "Implemented 148 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "3 " "Implemented 3 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1546839365588 ""} { "Info" "ICUT_CUT_TM_OPINS" "26 " "Implemented 26 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1546839365588 ""} { "Info" "ICUT_CUT_TM_LCELLS" "119 " "Implemented 119 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1546839365588 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1546839365588 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 13 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 13 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4762 " "Peak virtual memory: 4762 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1546839365610 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Jan 07 13:36:05 2019 " "Processing ended: Mon Jan 07 13:36:05 2019" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1546839365610 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:14 " "Elapsed time: 00:00:14" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1546839365610 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:29 " "Total CPU time (on all processors): 00:00:29" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1546839365610 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1546839365610 ""}