{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 132 02/25/2009 SJ Full Version " "Info: Version 9.0 Build 132 02/25/2009 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Fri May 18 08:18:57 2018 " "Info: Processing started: Fri May 18 08:18:57 2018" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off lock -c lock " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off lock -c lock" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Info" "IQCU_PARALLEL_AUTODETECT_ONE_PROCESSOR" "" "Info: Only one processor detected - disabling parallel compilation" {  } {  } 0 0 "Only one processor detected - disabling parallel compilation" 0 0 "" 0 -1}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0 "" 0 -1}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0 -1}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "lock.vhd" "" { Text "C:/Users/Trinkle/Desktop/lock/lock.vhd" 10 -1 0 } } { "c:/altera/90/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0 -1}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0 -1}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register cnt\[6\] register state\[1\] 79.48 MHz 12.582 ns Internal " "Info: Clock \"clk\" has Internal fmax of 79.48 MHz between source register \"cnt\[6\]\" and destination register \"state\[1\]\" (period= 12.582 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "11.873 ns + Longest register register " "Info: + Longest register to register delay is 11.873 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cnt\[6\] 1 REG LC_X5_Y2_N0 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X5_Y2_N0; Fanout = 5; REG Node = 'cnt\[6\]'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { cnt[6] } "NODE_NAME" } } { "lock.vhd" "" { Text "C:/Users/Trinkle/Desktop/lock/lock.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.300 ns) + CELL(0.914 ns) 3.214 ns LessThan0~1 2 COMB LC_X7_Y1_N4 1 " "Info: 2: + IC(2.300 ns) + CELL(0.914 ns) = 3.214 ns; Loc. = LC_X7_Y1_N4; Fanout = 1; COMB Node = 'LessThan0~1'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "3.214 ns" { cnt[6] LessThan0~1 } "NODE_NAME" } } { "lock.vhd" "" { Text "C:/Users/Trinkle/Desktop/lock/lock.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.458 ns) + CELL(0.511 ns) 6.183 ns LessThan0~4 3 COMB LC_X2_Y2_N1 1 " "Info: 3: + IC(2.458 ns) + CELL(0.511 ns) = 6.183 ns; Loc. = LC_X2_Y2_N1; Fanout = 1; COMB Node = 'LessThan0~4'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "2.969 ns" { LessThan0~1 LessThan0~4 } "NODE_NAME" } } { "lock.vhd" "" { Text "C:/Users/Trinkle/Desktop/lock/lock.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.305 ns) + CELL(0.200 ns) 6.688 ns LessThan0~9 4 COMB LC_X2_Y2_N2 3 " "Info: 4: + IC(0.305 ns) + CELL(0.200 ns) = 6.688 ns; Loc. = LC_X2_Y2_N2; Fanout = 3; COMB Node = 'LessThan0~9'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "0.505 ns" { LessThan0~4 LessThan0~9 } "NODE_NAME" } } { "lock.vhd" "" { Text "C:/Users/Trinkle/Desktop/lock/lock.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.725 ns) + CELL(0.200 ns) 7.613 ns alarm~14 5 COMB LC_X2_Y2_N5 3 " "Info: 5: + IC(0.725 ns) + CELL(0.200 ns) = 7.613 ns; Loc. = LC_X2_Y2_N5; Fanout = 3; COMB Node = 'alarm~14'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "0.925 ns" { LessThan0~9 alarm~14 } "NODE_NAME" } } { "lock.vhd" "" { Text "C:/Users/Trinkle/Desktop/lock/lock.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.118 ns) + CELL(0.200 ns) 9.931 ns state~222 6 COMB LC_X2_Y3_N4 3 " "Info: 6: + IC(2.118 ns) + CELL(0.200 ns) = 9.931 ns; Loc. = LC_X2_Y3_N4; Fanout = 3; COMB Node = 'state~222'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "2.318 ns" { alarm~14 state~222 } "NODE_NAME" } } { "lock.vhd" "" { Text "C:/Users/Trinkle/Desktop/lock/lock.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.699 ns) + CELL(1.243 ns) 11.873 ns state\[1\] 7 REG LC_X2_Y3_N0 12 " "Info: 7: + IC(0.699 ns) + CELL(1.243 ns) = 11.873 ns; Loc. = LC_X2_Y3_N0; Fanout = 12; REG Node = 'state\[1\]'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "1.942 ns" { state~222 state[1] } "NODE_NAME" } } { "lock.vhd" "" { Text "C:/Users/Trinkle/Desktop/lock/lock.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.268 ns ( 27.52 % ) " "Info: Total cell delay = 3.268 ns ( 27.52 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "8.605 ns ( 72.48 % ) " "Info: Total interconnect delay = 8.605 ns ( 72.48 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "11.873 ns" { cnt[6] LessThan0~1 LessThan0~4 LessThan0~9 alarm~14 state~222 state[1] } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "11.873 ns" { cnt[6] {} LessThan0~1 {} LessThan0~4 {} LessThan0~9 {} alarm~14 {} state~222 {} state[1] {} } { 0.000ns 2.300ns 2.458ns 0.305ns 0.725ns 2.118ns 0.699ns } { 0.000ns 0.914ns 0.511ns 0.200ns 0.200ns 0.200ns 1.243ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.348 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 3.348 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_12 58 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 58; CLK Node = 'clk'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "lock.vhd" "" { Text "C:/Users/Trinkle/Desktop/lock/lock.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(0.918 ns) 3.348 ns state\[1\] 2 REG LC_X2_Y3_N0 12 " "Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X2_Y3_N0; Fanout = 12; REG Node = 'state\[1\]'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "2.185 ns" { clk state[1] } "NODE_NAME" } } { "lock.vhd" "" { Text "C:/Users/Trinkle/Desktop/lock/lock.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 62.16 % ) " "Info: Total cell delay = 2.081 ns ( 62.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.267 ns ( 37.84 % ) " "Info: Total interconnect delay = 1.267 ns ( 37.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { clk state[1] } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { clk {} clk~combout {} state[1] {} } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.348 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 3.348 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_12 58 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 58; CLK Node = 'clk'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "lock.vhd" "" { Text "C:/Users/Trinkle/Desktop/lock/lock.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(0.918 ns) 3.348 ns cnt\[6\] 2 REG LC_X5_Y2_N0 5 " "Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X5_Y2_N0; Fanout = 5; REG Node = 'cnt\[6\]'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "2.185 ns" { clk cnt[6] } "NODE_NAME" } } { "lock.vhd" "" { Text "C:/Users/Trinkle/Desktop/lock/lock.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 62.16 % ) " "Info: Total cell delay = 2.081 ns ( 62.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.267 ns ( 37.84 % ) " "Info: Total interconnect delay = 1.267 ns ( 37.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { clk cnt[6] } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { clk {} clk~combout {} cnt[6] {} } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1}  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { clk state[1] } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { clk {} clk~combout {} state[1] {} } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { clk cnt[6] } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { clk {} clk~combout {} cnt[6] {} } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "lock.vhd" "" { Text "C:/Users/Trinkle/Desktop/lock/lock.vhd" 24 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "lock.vhd" "" { Text "C:/Users/Trinkle/Desktop/lock/lock.vhd" 24 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 -1}  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "11.873 ns" { cnt[6] LessThan0~1 LessThan0~4 LessThan0~9 alarm~14 state~222 state[1] } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "11.873 ns" { cnt[6] {} LessThan0~1 {} LessThan0~4 {} LessThan0~9 {} alarm~14 {} state~222 {} state[1] {} } { 0.000ns 2.300ns 2.458ns 0.305ns 0.725ns 2.118ns 0.699ns } { 0.000ns 0.914ns 0.511ns 0.200ns 0.200ns 0.200ns 1.243ns } "" } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { clk state[1] } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { clk {} clk~combout {} state[1] {} } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { clk cnt[6] } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { clk {} clk~combout {} cnt[6] {} } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0 -1}
{ "Info" "ITDB_TSU_RESULT" "alarm~reg0 code\[1\] clk 10.665 ns register " "Info: tsu for register \"alarm~reg0\" (data pin = \"code\[1\]\", clock pin = \"clk\") is 10.665 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "13.680 ns + Longest pin register " "Info: + Longest pin to register delay is 13.680 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns code\[1\] 1 PIN PIN_17 9 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_17; Fanout = 9; PIN Node = 'code\[1\]'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { code[1] } "NODE_NAME" } } { "lock.vhd" "" { Text "C:/Users/Trinkle/Desktop/lock/lock.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.992 ns) + CELL(0.740 ns) 4.864 ns Equal8~0 2 COMB LC_X2_Y1_N5 1 " "Info: 2: + IC(2.992 ns) + CELL(0.740 ns) = 4.864 ns; Loc. = LC_X2_Y1_N5; Fanout = 1; COMB Node = 'Equal8~0'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "3.732 ns" { code[1] Equal8~0 } "NODE_NAME" } } { "lock.vhd" "" { Text "C:/Users/Trinkle/Desktop/lock/lock.vhd" 82 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.767 ns) + CELL(0.511 ns) 6.142 ns Equal8~2 3 COMB LC_X2_Y1_N8 3 " "Info: 3: + IC(0.767 ns) + CELL(0.511 ns) = 6.142 ns; Loc. = LC_X2_Y1_N8; Fanout = 3; COMB Node = 'Equal8~2'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "1.278 ns" { Equal8~0 Equal8~2 } "NODE_NAME" } } { "lock.vhd" "" { Text "C:/Users/Trinkle/Desktop/lock/lock.vhd" 82 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.529 ns) + CELL(0.740 ns) 9.411 ns alarm~10 4 COMB LC_X5_Y4_N7 1 " "Info: 4: + IC(2.529 ns) + CELL(0.740 ns) = 9.411 ns; Loc. = LC_X5_Y4_N7; Fanout = 1; COMB Node = 'alarm~10'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "3.269 ns" { Equal8~2 alarm~10 } "NODE_NAME" } } { "lock.vhd" "" { Text "C:/Users/Trinkle/Desktop/lock/lock.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.732 ns) + CELL(0.740 ns) 10.883 ns alarm~12 5 COMB LC_X5_Y4_N2 2 " "Info: 5: + IC(0.732 ns) + CELL(0.740 ns) = 10.883 ns; Loc. = LC_X5_Y4_N2; Fanout = 2; COMB Node = 'alarm~12'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "1.472 ns" { alarm~10 alarm~12 } "NODE_NAME" } } { "lock.vhd" "" { Text "C:/Users/Trinkle/Desktop/lock/lock.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.736 ns) + CELL(1.061 ns) 13.680 ns alarm~reg0 6 REG LC_X3_Y4_N5 47 " "Info: 6: + IC(1.736 ns) + CELL(1.061 ns) = 13.680 ns; Loc. = LC_X3_Y4_N5; Fanout = 47; REG Node = 'alarm~reg0'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "2.797 ns" { alarm~12 alarm~reg0 } "NODE_NAME" } } { "lock.vhd" "" { Text "C:/Users/Trinkle/Desktop/lock/lock.vhd" 24 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.924 ns ( 35.99 % ) " "Info: Total cell delay = 4.924 ns ( 35.99 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "8.756 ns ( 64.01 % ) " "Info: Total interconnect delay = 8.756 ns ( 64.01 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "13.680 ns" { code[1] Equal8~0 Equal8~2 alarm~10 alarm~12 alarm~reg0 } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "13.680 ns" { code[1] {} code[1]~combout {} Equal8~0 {} Equal8~2 {} alarm~10 {} alarm~12 {} alarm~reg0 {} } { 0.000ns 0.000ns 2.992ns 0.767ns 2.529ns 0.732ns 1.736ns } { 0.000ns 1.132ns 0.740ns 0.511ns 0.740ns 0.740ns 1.061ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "lock.vhd" "" { Text "C:/Users/Trinkle/Desktop/lock/lock.vhd" 24 0 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.348 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 3.348 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_12 58 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 58; CLK Node = 'clk'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "lock.vhd" "" { Text "C:/Users/Trinkle/Desktop/lock/lock.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(0.918 ns) 3.348 ns alarm~reg0 2 REG LC_X3_Y4_N5 47 " "Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X3_Y4_N5; Fanout = 47; REG Node = 'alarm~reg0'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "2.185 ns" { clk alarm~reg0 } "NODE_NAME" } } { "lock.vhd" "" { Text "C:/Users/Trinkle/Desktop/lock/lock.vhd" 24 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 62.16 % ) " "Info: Total cell delay = 2.081 ns ( 62.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.267 ns ( 37.84 % ) " "Info: Total interconnect delay = 1.267 ns ( 37.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { clk alarm~reg0 } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { clk {} clk~combout {} alarm~reg0 {} } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1}  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "13.680 ns" { code[1] Equal8~0 Equal8~2 alarm~10 alarm~12 alarm~reg0 } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "13.680 ns" { code[1] {} code[1]~combout {} Equal8~0 {} Equal8~2 {} alarm~10 {} alarm~12 {} alarm~reg0 {} } { 0.000ns 0.000ns 2.992ns 0.767ns 2.529ns 0.732ns 1.736ns } { 0.000ns 1.132ns 0.740ns 0.511ns 0.740ns 0.740ns 1.061ns } "" } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { clk alarm~reg0 } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { clk {} clk~combout {} alarm~reg0 {} } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 -1}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk err err~reg0 8.719 ns register " "Info: tco from clock \"clk\" to destination pin \"err\" through register \"err~reg0\" is 8.719 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.348 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 3.348 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_12 58 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 58; CLK Node = 'clk'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "lock.vhd" "" { Text "C:/Users/Trinkle/Desktop/lock/lock.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(0.918 ns) 3.348 ns err~reg0 2 REG LC_X5_Y4_N9 4 " "Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X5_Y4_N9; Fanout = 4; REG Node = 'err~reg0'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "2.185 ns" { clk err~reg0 } "NODE_NAME" } } { "lock.vhd" "" { Text "C:/Users/Trinkle/Desktop/lock/lock.vhd" 24 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 62.16 % ) " "Info: Total cell delay = 2.081 ns ( 62.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.267 ns ( 37.84 % ) " "Info: Total interconnect delay = 1.267 ns ( 37.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { clk err~reg0 } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { clk {} clk~combout {} err~reg0 {} } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "lock.vhd" "" { Text "C:/Users/Trinkle/Desktop/lock/lock.vhd" 24 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.995 ns + Longest register pin " "Info: + Longest register to pin delay is 4.995 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns err~reg0 1 REG LC_X5_Y4_N9 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X5_Y4_N9; Fanout = 4; REG Node = 'err~reg0'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { err~reg0 } "NODE_NAME" } } { "lock.vhd" "" { Text "C:/Users/Trinkle/Desktop/lock/lock.vhd" 24 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.673 ns) + CELL(2.322 ns) 4.995 ns err 2 PIN PIN_6 0 " "Info: 2: + IC(2.673 ns) + CELL(2.322 ns) = 4.995 ns; Loc. = PIN_6; Fanout = 0; PIN Node = 'err'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "4.995 ns" { err~reg0 err } "NODE_NAME" } } { "lock.vhd" "" { Text "C:/Users/Trinkle/Desktop/lock/lock.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.322 ns ( 46.49 % ) " "Info: Total cell delay = 2.322 ns ( 46.49 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "2.673 ns ( 53.51 % ) " "Info: Total interconnect delay = 2.673 ns ( 53.51 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "4.995 ns" { err~reg0 err } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "4.995 ns" { err~reg0 {} err {} } { 0.000ns 2.673ns } { 0.000ns 2.322ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1}  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { clk err~reg0 } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { clk {} clk~combout {} err~reg0 {} } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "4.995 ns" { err~reg0 err } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "4.995 ns" { err~reg0 {} err {} } { 0.000ns 2.673ns } { 0.000ns 2.322ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0 -1}
{ "Info" "ITDB_TH_RESULT" "pwd\[2\]\[3\] code\[3\] clk -1.330 ns register " "Info: th for register \"pwd\[2\]\[3\]\" (data pin = \"code\[3\]\", clock pin = \"clk\") is -1.330 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.348 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 3.348 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_12 58 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 58; CLK Node = 'clk'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "lock.vhd" "" { Text "C:/Users/Trinkle/Desktop/lock/lock.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(0.918 ns) 3.348 ns pwd\[2\]\[3\] 2 REG LC_X2_Y1_N2 1 " "Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X2_Y1_N2; Fanout = 1; REG Node = 'pwd\[2\]\[3\]'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "2.185 ns" { clk pwd[2][3] } "NODE_NAME" } } { "lock.vhd" "" { Text "C:/Users/Trinkle/Desktop/lock/lock.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 62.16 % ) " "Info: Total cell delay = 2.081 ns ( 62.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.267 ns ( 37.84 % ) " "Info: Total interconnect delay = 1.267 ns ( 37.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { clk pwd[2][3] } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { clk {} clk~combout {} pwd[2][3] {} } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TH_DELAY" "0.221 ns + " "Info: + Micro hold delay of destination is 0.221 ns" {  } { { "lock.vhd" "" { Text "C:/Users/Trinkle/Desktop/lock/lock.vhd" 24 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.899 ns - Shortest pin register " "Info: - Shortest pin to register delay is 4.899 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns code\[3\] 1 PIN PIN_19 9 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_19; Fanout = 9; PIN Node = 'code\[3\]'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { code[3] } "NODE_NAME" } } { "lock.vhd" "" { Text "C:/Users/Trinkle/Desktop/lock/lock.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.584 ns) + CELL(1.183 ns) 4.899 ns pwd\[2\]\[3\] 2 REG LC_X2_Y1_N2 1 " "Info: 2: + IC(2.584 ns) + CELL(1.183 ns) = 4.899 ns; Loc. = LC_X2_Y1_N2; Fanout = 1; REG Node = 'pwd\[2\]\[3\]'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "3.767 ns" { code[3] pwd[2][3] } "NODE_NAME" } } { "lock.vhd" "" { Text "C:/Users/Trinkle/Desktop/lock/lock.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.315 ns ( 47.25 % ) " "Info: Total cell delay = 2.315 ns ( 47.25 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "2.584 ns ( 52.75 % ) " "Info: Total interconnect delay = 2.584 ns ( 52.75 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "4.899 ns" { code[3] pwd[2][3] } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "4.899 ns" { code[3] {} code[3]~combout {} pwd[2][3] {} } { 0.000ns 0.000ns 2.584ns } { 0.000ns 1.132ns 1.183ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1}  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { clk pwd[2][3] } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { clk {} clk~combout {} pwd[2][3] {} } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "4.899 ns" { code[3] pwd[2][3] } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "4.899 ns" { code[3] {} code[3]~combout {} pwd[2][3] {} } { 0.000ns 0.000ns 2.584ns } { 0.000ns 1.132ns 1.183ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "231 " "Info: Peak virtual memory: 231 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Fri May 18 08:18:58 2018 " "Info: Processing ended: Fri May 18 08:18:58 2018" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}