{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 132 02/25/2009 SJ Full Version " "Info: Version 9.0 Build 132 02/25/2009 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Sat Apr 28 13:02:28 2018 " "Info: Processing started: Sat Apr 28 13:02:28 2018" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off fp4 -c fp4 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off fp4 -c fp4" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "successive.vhd 1 0 " "Info: Found 1 design units, including 0 entities, in source file successive.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 fp4-successive " "Info: Found design unit 1: fp4-successive" {  } { { "successive.vhd" "" { Text "C:/altera/13.0/fp4/successive.vhd" 1 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "advance.vhd 0 0 " "Info: Found 0 design units, including 0 entities, in source file advance.vhd" {  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system.vhd 0 0 " "Info: Found 0 design units, including 0 entities, in source file system.vhd" {  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "fp1.vhd 3 2 " "Info: Found 3 design units, including 2 entities, in source file fp1.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 fp1-plus " "Info: Found design unit 1: fp1-plus" {  } { { "fp1.vhd" "" { Text "C:/altera/13.0/fp4/fp1.vhd" 14 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "1 fp1 " "Info: Found entity 1: fp1" {  } { { "fp1.vhd" "" { Text "C:/altera/13.0/fp4/fp1.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "2 fp4 " "Info: Found entity 2: fp4" {  } { { "fp1.vhd" "" { Text "C:/altera/13.0/fp4/fp1.vhd" 33 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_TOP" "fp4 " "Info: Elaborating entity \"fp4\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "p successive.vhd(9) " "Warning (10036): Verilog HDL or VHDL warning at successive.vhd(9): object \"p\" assigned a value but never read" {  } { { "successive.vhd" "" { Text "C:/altera/13.0/fp4/successive.vhd" 9 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "g successive.vhd(9) " "Warning (10036): Verilog HDL or VHDL warning at successive.vhd(9): object \"g\" assigned a value but never read" {  } { { "successive.vhd" "" { Text "C:/altera/13.0/fp4/successive.vhd" 9 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "fp1 fp1:fa0 " "Info: Elaborating entity \"fp1\" for hierarchy \"fp1:fa0\"" {  } { { "successive.vhd" "fa0" { Text "C:/altera/13.0/fp4/successive.vhd" 11 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ICUT_CUT_TM_SUMMARY" "22 " "Info: Implemented 22 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "9 " "Info: Implemented 9 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_OPINS" "5 " "Info: Implemented 5 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_LCELLS" "8 " "Info: Implemented 8 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 -1}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 2 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "282 " "Info: Peak virtual memory: 282 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Sat Apr 28 13:02:31 2018 " "Info: Processing ended: Sat Apr 28 13:02:31 2018" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}