# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, Altera MegaCore Function License 
# Agreement, or other applicable license agreement, including, 
# without limitation, that your use is for the sole purpose of 
# programming logic devices manufactured by Altera and sold by 
# Altera or its authorized distributors.  Please refer to the 
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.0.0 Build 156 04/24/2013 SJ Web Edition
# Date created = 21:54:02  April 26, 2018
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
#		fp4_assignment_defaults.qdf
#    If this file doesn't exist, see file:
#		assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
#    file is updated automatically by the Quartus II software
#    and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #


set_global_assignment -name FAMILY "MAX II"
set_global_assignment -name DEVICE EPM240T100C5
set_global_assignment -name TOP_LEVEL_ENTITY fp4
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:54:02  APRIL 26, 2018"
set_global_assignment -name LAST_QUARTUS_VERSION 9.0
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name MISC_FILE "C:/altera/13.0/fp4/fp4.dpf"
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name POWER_EXT_SUPPLY_VOLTAGE_TO_REGULATOR 3.3V
set_global_assignment -name USE_CONFIGURATION_DEVICE ON
set_global_assignment -name INCREMENTAL_COMPILATION OFF
set_location_assignment PIN_4 -to a[3]
set_location_assignment PIN_3 -to a[2]
set_location_assignment PIN_2 -to a[1]
set_location_assignment PIN_1 -to a[0]
set_location_assignment PIN_8 -to b[3]
set_location_assignment PIN_7 -to b[2]
set_location_assignment PIN_6 -to b[1]
set_location_assignment PIN_5 -to b[0]
set_location_assignment PIN_17 -to s[3]
set_location_assignment PIN_16 -to s[2]
set_location_assignment PIN_15 -to s[1]
set_location_assignment PIN_14 -to s[0]
set_location_assignment PIN_18 -to cin
set_location_assignment PIN_21 -to cout
set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
set_global_assignment -name VHDL_FILE successive.vhd
set_global_assignment -name VECTOR_WAVEFORM_FILE fp4.vwf
set_global_assignment -name VHDL_FILE advance.vhd
set_global_assignment -name VHDL_FILE system.vhd
set_global_assignment -name VHDL_FILE fp1.vhd