Analysis & Synthesis report for count Fri May 11 14:16:08 2018 Quartus II Version 9.0 Build 132 02/25/2009 SJ Full Version --------------------- ; Table of Contents ; --------------------- 1. Legal Notice 2. Analysis & Synthesis Summary 3. Analysis & Synthesis Settings 4. Analysis & Synthesis Source Files Read 5. Analysis & Synthesis Resource Usage Summary 6. Analysis & Synthesis Resource Utilization by Entity 7. General Register Statistics 8. Analysis & Synthesis Messages ---------------- ; Legal Notice ; ---------------- Copyright (C) 1991-2009 Altera Corporation Your use of Altera Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Altera Program License Subscription Agreement, Altera MegaCore Function License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Altera and sold by Altera or its authorized distributors. Please refer to the applicable agreement for further details. +------------------------------------------------------------------------+ ; Analysis & Synthesis Summary ; +-----------------------------+------------------------------------------+ ; Analysis & Synthesis Status ; Successful - Fri May 11 14:16:08 2018 ; ; Quartus II Version ; 9.0 Build 132 02/25/2009 SJ Full Version ; ; Revision Name ; count ; ; Top-level Entity Name ; count ; ; Family ; MAX II ; ; Total logic elements ; 74 ; ; Total pins ; 26 ; ; Total virtual pins ; 0 ; ; UFM blocks ; 0 / 1 ( 0 % ) ; +-----------------------------+------------------------------------------+ +----------------------------------------------------------------------------------------------------------+ ; Analysis & Synthesis Settings ; +----------------------------------------------------------------+--------------------+--------------------+ ; Option ; Setting ; Default Value ; +----------------------------------------------------------------+--------------------+--------------------+ ; Device ; EPM240T100C5 ; ; ; Top-level entity name ; count ; count ; ; Family name ; MAX II ; Stratix II ; ; Use Generated Physical Constraints File ; Off ; ; ; Use smart compilation ; Off ; Off ; ; Restructure Multiplexers ; Auto ; Auto ; ; Create Debugging Nodes for IP Cores ; Off ; Off ; ; Preserve fewer node names ; On ; On ; ; Disable OpenCore Plus hardware evaluation ; Off ; Off ; ; Verilog Version ; Verilog_2001 ; Verilog_2001 ; ; VHDL Version ; VHDL93 ; VHDL93 ; ; State Machine Processing ; Auto ; Auto ; ; Safe State Machine ; Off ; Off ; ; Extract Verilog State Machines ; On ; On ; ; Extract VHDL State Machines ; On ; On ; ; Ignore Verilog initial constructs ; Off ; Off ; ; Iteration limit for constant Verilog loops ; 5000 ; 5000 ; ; Iteration limit for non-constant Verilog loops ; 250 ; 250 ; ; Add Pass-Through Logic to Inferred RAMs ; On ; On ; ; Parallel Synthesis ; Off ; Off ; ; NOT Gate Push-Back ; On ; On ; ; Power-Up Don't Care ; On ; On ; ; Remove Redundant Logic Cells ; Off ; Off ; ; Remove Duplicate Registers ; On ; On ; ; Ignore CARRY Buffers ; Off ; Off ; ; Ignore CASCADE Buffers ; Off ; Off ; ; Ignore GLOBAL Buffers ; Off ; Off ; ; Ignore ROW GLOBAL Buffers ; Off ; Off ; ; Ignore LCELL Buffers ; Off ; Off ; ; Ignore SOFT Buffers ; On ; On ; ; Limit AHDL Integers to 32 Bits ; Off ; Off ; ; Optimization Technique ; Balanced ; Balanced ; ; Carry Chain Length ; 70 ; 70 ; ; Auto Carry Chains ; On ; On ; ; Auto Open-Drain Pins ; On ; On ; ; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ; ; Auto Shift Register Replacement ; Auto ; Auto ; ; Auto Clock Enable Replacement ; On ; On ; ; Allow Synchronous Control Signals ; On ; On ; ; Force Use of Synchronous Clear Signals ; Off ; Off ; ; Auto Resource Sharing ; Off ; Off ; ; Use LogicLock Constraints during Resource Balancing ; On ; On ; ; Ignore translate_off and synthesis_off directives ; Off ; Off ; ; Show Parameter Settings Tables in Synthesis Report ; On ; On ; ; Ignore Maximum Fan-Out Assignments ; Off ; Off ; ; Synchronization Register Chain Length ; 2 ; 2 ; ; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ; ; HDL message level ; Level2 ; Level2 ; ; Suppress Register Optimization Related Messages ; Off ; Off ; ; Number of Removed Registers Reported in Synthesis Report ; 100 ; 100 ; ; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ; ; Clock MUX Protection ; On ; On ; ; Block Design Naming ; Auto ; Auto ; ; Synthesis Effort ; Auto ; Auto ; ; Allows Asynchronous Clear Usage For Shift Register Replacement ; On ; On ; ; Analysis & Synthesis Message Level ; Medium ; Medium ; +----------------------------------------------------------------+--------------------+--------------------+ +-----------------------------------------------------------------------------------------------------------------+ ; Analysis & Synthesis Source Files Read ; +----------------------------------+-----------------+-----------------+------------------------------------------+ ; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; +----------------------------------+-----------------+-----------------+------------------------------------------+ ; count.vhd ; yes ; User VHDL File ; C:/Users/Trinkle/Desktop/count/count.vhd ; +----------------------------------+-----------------+-----------------+------------------------------------------+ +-----------------------------------------------------+ ; Analysis & Synthesis Resource Usage Summary ; +---------------------------------------------+-------+ ; Resource ; Usage ; +---------------------------------------------+-------+ ; Total logic elements ; 74 ; ; -- Combinational with no register ; 34 ; ; -- Register only ; 0 ; ; -- Combinational with a register ; 40 ; ; ; ; ; Logic element usage by number of LUT inputs ; ; ; -- 4 input functions ; 33 ; ; -- 3 input functions ; 5 ; ; -- 2 input functions ; 33 ; ; -- 1 input functions ; 3 ; ; -- 0 input functions ; 0 ; ; ; ; ; Logic elements by mode ; ; ; -- normal mode ; 43 ; ; -- arithmetic mode ; 31 ; ; -- qfbk mode ; 0 ; ; -- register cascade mode ; 0 ; ; -- synchronous clear/load mode ; 32 ; ; -- asynchronous clear/load mode ; 40 ; ; ; ; ; Total registers ; 40 ; ; Total logic cells in carry chains ; 32 ; ; I/O pins ; 26 ; ; Maximum fan-out node ; clk ; ; Maximum fan-out ; 40 ; ; Total fan-out ; 388 ; ; Average fan-out ; 3.88 ; +---------------------------------------------+-------+ +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Analysis & Synthesis Resource Utilization by Entity ; +----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+ ; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ; +----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+ ; |count ; 74 (0) ; 40 ; 0 ; 26 ; 0 ; 34 (0) ; 0 (0) ; 40 (0) ; 32 (0) ; 0 (0) ; |count ; work ; ; |digit_7:tmp1| ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; 7 (7) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |count|digit_7:tmp1 ; work ; ; |digit_7:tmp2| ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; 7 (7) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |count|digit_7:tmp2 ; work ; ; |ff:tmp0| ; 60 (60) ; 40 ; 0 ; 0 ; 0 ; 20 (20) ; 0 (0) ; 40 (40) ; 32 (32) ; 0 (0) ; |count|ff:tmp0 ; work ; +----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+ Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. +------------------------------------------------------+ ; General Register Statistics ; +----------------------------------------------+-------+ ; Statistic ; Value ; +----------------------------------------------+-------+ ; Total registers ; 40 ; ; Number of registers using Synchronous Clear ; 32 ; ; Number of registers using Synchronous Load ; 0 ; ; Number of registers using Asynchronous Clear ; 40 ; ; Number of registers using Asynchronous Load ; 0 ; ; Number of registers using Clock Enable ; 38 ; ; Number of registers using Preset ; 0 ; +----------------------------------------------+-------+ +-------------------------------+ ; Analysis & Synthesis Messages ; +-------------------------------+ Info: ******************************************************************* Info: Running Quartus II Analysis & Synthesis Info: Version 9.0 Build 132 02/25/2009 SJ Full Version Info: Processing started: Fri May 11 14:16:06 2018 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off count -c count Info: Found 6 design units, including 3 entities, in source file count.vhd Info: Found design unit 1: ff-arc Info: Found design unit 2: digit_7-arc Info: Found design unit 3: count-arc Info: Found entity 1: ff Info: Found entity 2: digit_7 Info: Found entity 3: count Info: Elaborating entity "count" for the top level hierarchy Info: Elaborating entity "ff" for hierarchy "ff:tmp0" Warning (10492): VHDL Process Statement warning at count.vhd(22): signal "pause" is read inside the Process Statement but isn't in the Process Statement's sensitivity list Info: Elaborating entity "digit_7" for hierarchy "digit_7:tmp1" Info: Implemented 100 device resources after synthesis - the final resource count might be different Info: Implemented 4 input pins Info: Implemented 22 output pins Info: Implemented 74 logic cells Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning Info: Peak virtual memory: 293 megabytes Info: Processing ended: Fri May 11 14:16:08 2018 Info: Elapsed time: 00:00:02 Info: Total CPU time (on all processors): 00:00:01