{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 132 02/25/2009 SJ Full Version " "Info: Version 9.0 Build 132 02/25/2009 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Fri May 11 14:16:19 2018 " "Info: Processing started: Fri May 11 14:16:19 2018" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off count -c count " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off count -c count" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Info" "IQCU_PARALLEL_AUTODETECT_ONE_PROCESSOR" "" "Info: Only one processor detected - disabling parallel compilation" {  } {  } 0 0 "Only one processor detected - disabling parallel compilation" 0 0 "" 0 -1}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0 "" 0 -1}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0 -1}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "count.vhd" "" { Text "C:/Users/Trinkle/Desktop/count/count.vhd" 90 -1 0 } } { "c:/altera/90/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0 -1}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0 -1}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register ff:tmp0\|cnt\[16\] register ff:tmp0\|n0\[0\] 80.24 MHz 12.463 ns Internal " "Info: Clock \"clk\" has Internal fmax of 80.24 MHz between source register \"ff:tmp0\|cnt\[16\]\" and destination register \"ff:tmp0\|n0\[0\]\" (period= 12.463 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "11.754 ns + Longest register register " "Info: + Longest register to register delay is 11.754 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ff:tmp0\|cnt\[16\] 1 REG LC_X5_Y1_N0 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X5_Y1_N0; Fanout = 5; REG Node = 'ff:tmp0\|cnt\[16\]'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { ff:tmp0|cnt[16] } "NODE_NAME" } } { "count.vhd" "" { Text "C:/Users/Trinkle/Desktop/count/count.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(3.150 ns) + CELL(0.914 ns) 4.064 ns ff:tmp0\|Equal0~9 2 COMB LC_X4_Y2_N9 1 " "Info: 2: + IC(3.150 ns) + CELL(0.914 ns) = 4.064 ns; Loc. = LC_X4_Y2_N9; Fanout = 1; COMB Node = 'ff:tmp0\|Equal0~9'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "4.064 ns" { ff:tmp0|cnt[16] ff:tmp0|Equal0~9 } "NODE_NAME" } } { "count.vhd" "" { Text "C:/Users/Trinkle/Desktop/count/count.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.713 ns) + CELL(0.511 ns) 6.288 ns ff:tmp0\|Equal0~10 3 COMB LC_X3_Y1_N0 1 " "Info: 3: + IC(1.713 ns) + CELL(0.511 ns) = 6.288 ns; Loc. = LC_X3_Y1_N0; Fanout = 1; COMB Node = 'ff:tmp0\|Equal0~10'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "2.224 ns" { ff:tmp0|Equal0~9 ff:tmp0|Equal0~10 } "NODE_NAME" } } { "count.vhd" "" { Text "C:/Users/Trinkle/Desktop/count/count.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.885 ns) + CELL(0.511 ns) 8.684 ns ff:tmp0\|n0\[0\]~8 4 COMB LC_X3_Y2_N7 6 " "Info: 4: + IC(1.885 ns) + CELL(0.511 ns) = 8.684 ns; Loc. = LC_X3_Y2_N7; Fanout = 6; COMB Node = 'ff:tmp0\|n0\[0\]~8'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "2.396 ns" { ff:tmp0|Equal0~10 ff:tmp0|n0[0]~8 } "NODE_NAME" } } { "count.vhd" "" { Text "C:/Users/Trinkle/Desktop/count/count.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.827 ns) + CELL(1.243 ns) 11.754 ns ff:tmp0\|n0\[0\] 5 REG LC_X2_Y3_N7 13 " "Info: 5: + IC(1.827 ns) + CELL(1.243 ns) = 11.754 ns; Loc. = LC_X2_Y3_N7; Fanout = 13; REG Node = 'ff:tmp0\|n0\[0\]'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "3.070 ns" { ff:tmp0|n0[0]~8 ff:tmp0|n0[0] } "NODE_NAME" } } { "count.vhd" "" { Text "C:/Users/Trinkle/Desktop/count/count.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.179 ns ( 27.05 % ) " "Info: Total cell delay = 3.179 ns ( 27.05 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "8.575 ns ( 72.95 % ) " "Info: Total interconnect delay = 8.575 ns ( 72.95 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "11.754 ns" { ff:tmp0|cnt[16] ff:tmp0|Equal0~9 ff:tmp0|Equal0~10 ff:tmp0|n0[0]~8 ff:tmp0|n0[0] } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "11.754 ns" { ff:tmp0|cnt[16] {} ff:tmp0|Equal0~9 {} ff:tmp0|Equal0~10 {} ff:tmp0|n0[0]~8 {} ff:tmp0|n0[0] {} } { 0.000ns 3.150ns 1.713ns 1.885ns 1.827ns } { 0.000ns 0.914ns 0.511ns 0.511ns 1.243ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.348 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 3.348 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_12 40 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 40; CLK Node = 'clk'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "count.vhd" "" { Text "C:/Users/Trinkle/Desktop/count/count.vhd" 90 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(0.918 ns) 3.348 ns ff:tmp0\|n0\[0\] 2 REG LC_X2_Y3_N7 13 " "Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X2_Y3_N7; Fanout = 13; REG Node = 'ff:tmp0\|n0\[0\]'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "2.185 ns" { clk ff:tmp0|n0[0] } "NODE_NAME" } } { "count.vhd" "" { Text "C:/Users/Trinkle/Desktop/count/count.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 62.16 % ) " "Info: Total cell delay = 2.081 ns ( 62.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.267 ns ( 37.84 % ) " "Info: Total interconnect delay = 1.267 ns ( 37.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { clk ff:tmp0|n0[0] } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { clk {} clk~combout {} ff:tmp0|n0[0] {} } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.348 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 3.348 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_12 40 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 40; CLK Node = 'clk'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "count.vhd" "" { Text "C:/Users/Trinkle/Desktop/count/count.vhd" 90 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(0.918 ns) 3.348 ns ff:tmp0\|cnt\[16\] 2 REG LC_X5_Y1_N0 5 " "Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X5_Y1_N0; Fanout = 5; REG Node = 'ff:tmp0\|cnt\[16\]'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "2.185 ns" { clk ff:tmp0|cnt[16] } "NODE_NAME" } } { "count.vhd" "" { Text "C:/Users/Trinkle/Desktop/count/count.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 62.16 % ) " "Info: Total cell delay = 2.081 ns ( 62.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.267 ns ( 37.84 % ) " "Info: Total interconnect delay = 1.267 ns ( 37.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { clk ff:tmp0|cnt[16] } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { clk {} clk~combout {} ff:tmp0|cnt[16] {} } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1}  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { clk ff:tmp0|n0[0] } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { clk {} clk~combout {} ff:tmp0|n0[0] {} } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { clk ff:tmp0|cnt[16] } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { clk {} clk~combout {} ff:tmp0|cnt[16] {} } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "count.vhd" "" { Text "C:/Users/Trinkle/Desktop/count/count.vhd" 18 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "count.vhd" "" { Text "C:/Users/Trinkle/Desktop/count/count.vhd" 18 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 -1}  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "11.754 ns" { ff:tmp0|cnt[16] ff:tmp0|Equal0~9 ff:tmp0|Equal0~10 ff:tmp0|n0[0]~8 ff:tmp0|n0[0] } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "11.754 ns" { ff:tmp0|cnt[16] {} ff:tmp0|Equal0~9 {} ff:tmp0|Equal0~10 {} ff:tmp0|n0[0]~8 {} ff:tmp0|n0[0] {} } { 0.000ns 3.150ns 1.713ns 1.885ns 1.827ns } { 0.000ns 0.914ns 0.511ns 0.511ns 1.243ns } "" } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { clk ff:tmp0|n0[0] } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { clk {} clk~combout {} ff:tmp0|n0[0] {} } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { clk ff:tmp0|cnt[16] } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { clk {} clk~combout {} ff:tmp0|cnt[16] {} } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0 -1}
{ "Info" "ITDB_TSU_RESULT" "ff:tmp0\|n0\[0\] pause clk 4.590 ns register " "Info: tsu for register \"ff:tmp0\|n0\[0\]\" (data pin = \"pause\", clock pin = \"clk\") is 4.590 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.605 ns + Longest pin register " "Info: + Longest pin to register delay is 7.605 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns pause 1 PIN PIN_8 2 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_8; Fanout = 2; PIN Node = 'pause'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { pause } "NODE_NAME" } } { "count.vhd" "" { Text "C:/Users/Trinkle/Desktop/count/count.vhd" 90 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.489 ns) + CELL(0.914 ns) 4.535 ns ff:tmp0\|n0\[0\]~8 2 COMB LC_X3_Y2_N7 6 " "Info: 2: + IC(2.489 ns) + CELL(0.914 ns) = 4.535 ns; Loc. = LC_X3_Y2_N7; Fanout = 6; COMB Node = 'ff:tmp0\|n0\[0\]~8'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "3.403 ns" { pause ff:tmp0|n0[0]~8 } "NODE_NAME" } } { "count.vhd" "" { Text "C:/Users/Trinkle/Desktop/count/count.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.827 ns) + CELL(1.243 ns) 7.605 ns ff:tmp0\|n0\[0\] 3 REG LC_X2_Y3_N7 13 " "Info: 3: + IC(1.827 ns) + CELL(1.243 ns) = 7.605 ns; Loc. = LC_X2_Y3_N7; Fanout = 13; REG Node = 'ff:tmp0\|n0\[0\]'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "3.070 ns" { ff:tmp0|n0[0]~8 ff:tmp0|n0[0] } "NODE_NAME" } } { "count.vhd" "" { Text "C:/Users/Trinkle/Desktop/count/count.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.289 ns ( 43.25 % ) " "Info: Total cell delay = 3.289 ns ( 43.25 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "4.316 ns ( 56.75 % ) " "Info: Total interconnect delay = 4.316 ns ( 56.75 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "7.605 ns" { pause ff:tmp0|n0[0]~8 ff:tmp0|n0[0] } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "7.605 ns" { pause {} pause~combout {} ff:tmp0|n0[0]~8 {} ff:tmp0|n0[0] {} } { 0.000ns 0.000ns 2.489ns 1.827ns } { 0.000ns 1.132ns 0.914ns 1.243ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "count.vhd" "" { Text "C:/Users/Trinkle/Desktop/count/count.vhd" 18 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.348 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 3.348 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_12 40 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 40; CLK Node = 'clk'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "count.vhd" "" { Text "C:/Users/Trinkle/Desktop/count/count.vhd" 90 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(0.918 ns) 3.348 ns ff:tmp0\|n0\[0\] 2 REG LC_X2_Y3_N7 13 " "Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X2_Y3_N7; Fanout = 13; REG Node = 'ff:tmp0\|n0\[0\]'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "2.185 ns" { clk ff:tmp0|n0[0] } "NODE_NAME" } } { "count.vhd" "" { Text "C:/Users/Trinkle/Desktop/count/count.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 62.16 % ) " "Info: Total cell delay = 2.081 ns ( 62.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.267 ns ( 37.84 % ) " "Info: Total interconnect delay = 1.267 ns ( 37.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { clk ff:tmp0|n0[0] } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { clk {} clk~combout {} ff:tmp0|n0[0] {} } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1}  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "7.605 ns" { pause ff:tmp0|n0[0]~8 ff:tmp0|n0[0] } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "7.605 ns" { pause {} pause~combout {} ff:tmp0|n0[0]~8 {} ff:tmp0|n0[0] {} } { 0.000ns 0.000ns 2.489ns 1.827ns } { 0.000ns 1.132ns 0.914ns 1.243ns } "" } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { clk ff:tmp0|n0[0] } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { clk {} clk~combout {} ff:tmp0|n0[0] {} } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 -1}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk ll\[6\] ff:tmp0\|n0\[1\] 11.536 ns register " "Info: tco from clock \"clk\" to destination pin \"ll\[6\]\" through register \"ff:tmp0\|n0\[1\]\" is 11.536 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.348 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 3.348 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_12 40 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 40; CLK Node = 'clk'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "count.vhd" "" { Text "C:/Users/Trinkle/Desktop/count/count.vhd" 90 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(0.918 ns) 3.348 ns ff:tmp0\|n0\[1\] 2 REG LC_X2_Y3_N2 12 " "Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X2_Y3_N2; Fanout = 12; REG Node = 'ff:tmp0\|n0\[1\]'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "2.185 ns" { clk ff:tmp0|n0[1] } "NODE_NAME" } } { "count.vhd" "" { Text "C:/Users/Trinkle/Desktop/count/count.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 62.16 % ) " "Info: Total cell delay = 2.081 ns ( 62.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.267 ns ( 37.84 % ) " "Info: Total interconnect delay = 1.267 ns ( 37.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { clk ff:tmp0|n0[1] } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { clk {} clk~combout {} ff:tmp0|n0[1] {} } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "count.vhd" "" { Text "C:/Users/Trinkle/Desktop/count/count.vhd" 18 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.812 ns + Longest register pin " "Info: + Longest register to pin delay is 7.812 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ff:tmp0\|n0\[1\] 1 REG LC_X2_Y3_N2 12 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X2_Y3_N2; Fanout = 12; REG Node = 'ff:tmp0\|n0\[1\]'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { ff:tmp0|n0[1] } "NODE_NAME" } } { "count.vhd" "" { Text "C:/Users/Trinkle/Desktop/count/count.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.046 ns) + CELL(0.914 ns) 2.960 ns digit_7:tmp1\|Mux0~0 2 COMB LC_X3_Y2_N3 1 " "Info: 2: + IC(2.046 ns) + CELL(0.914 ns) = 2.960 ns; Loc. = LC_X3_Y2_N3; Fanout = 1; COMB Node = 'digit_7:tmp1\|Mux0~0'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "2.960 ns" { ff:tmp0|n0[1] digit_7:tmp1|Mux0~0 } "NODE_NAME" } } { "count.vhd" "" { Text "C:/Users/Trinkle/Desktop/count/count.vhd" 61 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.530 ns) + CELL(2.322 ns) 7.812 ns ll\[6\] 3 PIN PIN_7 0 " "Info: 3: + IC(2.530 ns) + CELL(2.322 ns) = 7.812 ns; Loc. = PIN_7; Fanout = 0; PIN Node = 'll\[6\]'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "4.852 ns" { digit_7:tmp1|Mux0~0 ll[6] } "NODE_NAME" } } { "count.vhd" "" { Text "C:/Users/Trinkle/Desktop/count/count.vhd" 92 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.236 ns ( 41.42 % ) " "Info: Total cell delay = 3.236 ns ( 41.42 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "4.576 ns ( 58.58 % ) " "Info: Total interconnect delay = 4.576 ns ( 58.58 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "7.812 ns" { ff:tmp0|n0[1] digit_7:tmp1|Mux0~0 ll[6] } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "7.812 ns" { ff:tmp0|n0[1] {} digit_7:tmp1|Mux0~0 {} ll[6] {} } { 0.000ns 2.046ns 2.530ns } { 0.000ns 0.914ns 2.322ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1}  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { clk ff:tmp0|n0[1] } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { clk {} clk~combout {} ff:tmp0|n0[1] {} } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "7.812 ns" { ff:tmp0|n0[1] digit_7:tmp1|Mux0~0 ll[6] } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "7.812 ns" { ff:tmp0|n0[1] {} digit_7:tmp1|Mux0~0 {} ll[6] {} } { 0.000ns 2.046ns 2.530ns } { 0.000ns 0.914ns 2.322ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0 -1}
{ "Info" "ITDB_TH_RESULT" "ff:tmp0\|cnt\[5\] pause clk -2.189 ns register " "Info: th for register \"ff:tmp0\|cnt\[5\]\" (data pin = \"pause\", clock pin = \"clk\") is -2.189 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.348 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 3.348 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_12 40 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 40; CLK Node = 'clk'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "count.vhd" "" { Text "C:/Users/Trinkle/Desktop/count/count.vhd" 90 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(0.918 ns) 3.348 ns ff:tmp0\|cnt\[5\] 2 REG LC_X3_Y1_N9 3 " "Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X3_Y1_N9; Fanout = 3; REG Node = 'ff:tmp0\|cnt\[5\]'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "2.185 ns" { clk ff:tmp0|cnt[5] } "NODE_NAME" } } { "count.vhd" "" { Text "C:/Users/Trinkle/Desktop/count/count.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 62.16 % ) " "Info: Total cell delay = 2.081 ns ( 62.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.267 ns ( 37.84 % ) " "Info: Total interconnect delay = 1.267 ns ( 37.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { clk ff:tmp0|cnt[5] } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { clk {} clk~combout {} ff:tmp0|cnt[5] {} } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TH_DELAY" "0.221 ns + " "Info: + Micro hold delay of destination is 0.221 ns" {  } { { "count.vhd" "" { Text "C:/Users/Trinkle/Desktop/count/count.vhd" 18 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.758 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.758 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns pause 1 PIN PIN_8 2 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_8; Fanout = 2; PIN Node = 'pause'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { pause } "NODE_NAME" } } { "count.vhd" "" { Text "C:/Users/Trinkle/Desktop/count/count.vhd" 90 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.494 ns) + CELL(0.200 ns) 3.826 ns ff:tmp0\|cnt\[0\]~128 2 COMB LC_X3_Y1_N3 32 " "Info: 2: + IC(2.494 ns) + CELL(0.200 ns) = 3.826 ns; Loc. = LC_X3_Y1_N3; Fanout = 32; COMB Node = 'ff:tmp0\|cnt\[0\]~128'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "2.694 ns" { pause ff:tmp0|cnt[0]~128 } "NODE_NAME" } } { "count.vhd" "" { Text "C:/Users/Trinkle/Desktop/count/count.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.689 ns) + CELL(1.243 ns) 5.758 ns ff:tmp0\|cnt\[5\] 3 REG LC_X3_Y1_N9 3 " "Info: 3: + IC(0.689 ns) + CELL(1.243 ns) = 5.758 ns; Loc. = LC_X3_Y1_N9; Fanout = 3; REG Node = 'ff:tmp0\|cnt\[5\]'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "1.932 ns" { ff:tmp0|cnt[0]~128 ff:tmp0|cnt[5] } "NODE_NAME" } } { "count.vhd" "" { Text "C:/Users/Trinkle/Desktop/count/count.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.575 ns ( 44.72 % ) " "Info: Total cell delay = 2.575 ns ( 44.72 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "3.183 ns ( 55.28 % ) " "Info: Total interconnect delay = 3.183 ns ( 55.28 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "5.758 ns" { pause ff:tmp0|cnt[0]~128 ff:tmp0|cnt[5] } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "5.758 ns" { pause {} pause~combout {} ff:tmp0|cnt[0]~128 {} ff:tmp0|cnt[5] {} } { 0.000ns 0.000ns 2.494ns 0.689ns } { 0.000ns 1.132ns 0.200ns 1.243ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1}  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { clk ff:tmp0|cnt[5] } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { clk {} clk~combout {} ff:tmp0|cnt[5] {} } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "5.758 ns" { pause ff:tmp0|cnt[0]~128 ff:tmp0|cnt[5] } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "5.758 ns" { pause {} pause~combout {} ff:tmp0|cnt[0]~128 {} ff:tmp0|cnt[5] {} } { 0.000ns 0.000ns 2.494ns 0.689ns } { 0.000ns 1.132ns 0.200ns 1.243ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "231 " "Info: Peak virtual memory: 231 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Fri May 11 14:16:19 2018 " "Info: Processing ended: Fri May 11 14:16:19 2018" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}