{
    "version": "0.9",
    "description": "Framework for Verilog RTL synthesis",
    "homepage": "https://yosyshq.net/yosys/",
    "license": "ISC",
    "notes": "Separate binaries are no longer released for Yosys, but updated versions are included in OSS CAD Suite (versions/oss-cad-suite-nightly)",
    "url": "https://github.com/ScoopInstaller/Binary/raw/master/yosys/yosys-win32-mxebin-0.9.zip",
    "hash": "d638d860dff1f351c15ff0caeaa668742649677b874b1a9bdb0b6ce0e54840f5",
    "extract_dir": "yosys-win32-mxebin-0.9",
    "bin": [
        "yosys.exe",
        "yosys-abc.exe"
    ]
}