Silicon Lab Inc. SILAB RS1xxxx ARMCM4 1.2 ARM 32-bit Cortex-M4 Microcontroller based device, CPU clock up to 80MHz, etc. ARM Limited (ARM) is supplying this software for use with Cortex-M\n processor based microcontroller, but can be equally used for other\n suitable processor architectures. This file can be freely distributed.\n Modifications to this file shall be clearly marked.\n \n THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\n OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\n MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\n ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\n CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. CM4 r1p0 little true true 6 false 8 32 32 read-write 0x00000000 0xFFFFFFFF I2C0 1.0 Inter Integrated Circuit(I2C) is programmable control bus that provides support for the communications link between integrated circuits in a system I2C 0x44010000 32 read-write 0 0x100 registers I2C0 42 IC_CON This register can be written only when the i2c is disabled, which corresponds to IC_ENABLE[0] being set to 0. Writes at other times have no effect. 0x00 32 read-write 0x007F 0xFFFF MASTER_MODE This bit controls whether the I2C master is enabled. [0:0] read-write Disable master disabled 0 Enable master enabled 1 SPEED These bits control at which speed the I2C operates. Hardware protects against illegal values being programmed by software. [2:1] read-write Standard_Mode standard mode (0 to 100 kbit/s) 1 Fast_Mode fast mode (less than or equal 400 kbit/s) 2 High_Speed_Mode high speed mode (less than or equal 3.4 Mbit/s) 3 IC_10BITADDR_SLAVE When acting as a slave, this bit controls whether the I2C responds to 7- or 10-bit addresses. [3:3] read-write Disable 7-bit addressing. The DW_apb_i2c ignores transactions that involve 10-bit addressing; for 7-bit addressing, only the lower 7 bits of the IC_SAR register are compared 0 Enable 10-bit addressing. The DW_apb_i2c responds to only 10-bit addressing transfers that match the full 10 bits of the IC_SAR register. 1 IC_10BITADDR_MASTER_RD_ONLY the function of this bit is handled by bit 12 of IC_TAR register, and becomes a read-only copy called IC_10BITADDR_MASTER_rd_only [4:4] read-only Disable 7-bit addressing 0 Enable 10-bit addressing 1 IC_RESTART_EN Determines whether RESTART conditions may be sent when acting as a master [5:5] read-write Disable Disabled 0 Enable Enabled 1 IC_SLAVE_DISABLE This bit controls whether I2C has its slave disabled [6:6] read-write Disable slave is enabled 0 Enable slave is disabled 1 STOP_DET_IFADDRESSED The STOP DETECTION interrupt is generated only when the transmitted address matches the slave address of SAR [7:7] read-write Disable Issues the STOP DETECTION irrespective of whether it is addressed or not. 0 Enable issues the STOP DETECTION interrupt only when it is addressed. 1 TX_EMPTY_CTRL This bit controls the generation of the TX EMPTY interrupt, as described in the IC RAW INTR STAT register. [8:8] read-write RESERVED1 reserved1 [9:9] read-only STOP_DET_IF_MASTER_ACTIVE In Master mode. [10:10] read-write Disable Issues the STOP_DET irrespective of whether the master is active. 0 Enable Issues the STOP_DET interrupt only when the master is active 1 BUS_CLEAR_FEATURE_CTRL In Master mode. [11:11] read-write Disable Bus Clear Feature is disabled 0 Enable Bus Clear Feature is enabled 1 RESERVED2 reserved2 [31:12] read-write IC_TAR I2C Target Address Register 0x04 32 read-write 0x10A0 0xFFFF IC_TAR This is the target address for any master transaction [9:0] read-write GC_OR_START If bit 11 (SPECIAL) is set to 1, then this bit indicates whether a General Call or START byte command is to be performed by the DW_apb_i2c [10:10] read-write Disable General Call Address 0 Enable START BYTE 1 SPECIAL This bit indicates whether software performs a General Call or START BYTE command [11:11] read-write Disable ignore bit 10 GC_OR_START and use IC_TAR normally 0 Enable perform special I2C command as specified in GC_OR_START bit 1 IC_10BITADDR_MASTER This bit controls whether the i2c starts its transfers in 7-or 10-bit addressing mode when acting as a master [12:12] read-write Disable 7-bit addressing 0 Enable 10-bit addressing 1 DEVICE_ID If bit 11 (SPECIAL) is set to 1, then this bit indicates whether a Device-ID of a particular slave mentioned in IC_TAR[6:0] is to be performed by the I2C Master [13:13] read-write Disable Device-ID is not performed and checks ic_tar[10] to perform either general call or START byte command. 0 Enable : Device-ID transfer is performed and bytes based on the number of read commands in the Tx-FIFO are received from the targeted slave and put in the Rx-FIFO. 1 RESERVED1 reserved1 [31:14] read-only IC_SAR I2C Slave Address Register 0x08 32 read-write 0x55 0xFFFF IC_SAR The IC_SAR holds the slave address when the I2C is operating as a slave. For 7-bit addressing, only IC_SAR[6:0] is used. [9:0] read-write RESERVED1 reserved1 [31:10] read-only IC_HS_MADDR I2C High Speed Master Mode Code Address Register 0x0C 32 read-write 0x0001 0xF IC_HS_MAR This bit field holds the value of the I2C HS mode master code [2:0] read-write RESERVED1 reserved1 [31:3] read-only IC_DATA_CMD I2C Rx/Tx Data Buffer and Command Register 0x10 32 read-write 0x0000 0xFFFF DAT This register contains the data to be transmitted or received on the I2C bus [7:0] read-write CMD This bit controls whether a read or a write is performed [8:8] write-only Disable write 0 Enable Read 1 STOP This bit controls whether a STOP is issued after the byte is sent or received [9:9] write-only Disable STOP is not issued after this byte, regardless of whether or not the Tx FIFO is empty 0 Enable STOP is issued after this byte, regardless of whether or not the Tx FIFO is empty 1 RESTART This bit controls whether a RESTART is issued before the byte is sent or received [10:10] write-only Disable If IC_RESTART_EN is 1, a RESTART is issued only if the transfer direction is changing from the previous command 0 Enable If IC_RESTART_EN is 1, a RESTART is issued before the data is sent/received 1 FIRST_DATA_BYTE Indicates the first data byte received after the address phase for receive transfer in Master receiver or Slave receiver mode [11:11] read-only Disable If IC_RESTART_EN is 1, a RESTART is issued only if the transfer direction is changing from the previous command 0 Enable If IC_RESTART_EN is 1, a RESTART is issued before the data is sent/received 1 RESERVED1 reserved1 [31:12] read-only IC_SS_SCL_HCNT Standard Speed I2C Clock SCL High Count Register 0x14 32 read-write 0x01F4 0xFFFF IC_SS_SCL_HCNT This register must be set before any I2C bus transaction can take place to ensure proper I/O timing [15:0] read-write RESERVED1 reserved1 [31:16] read-only IC_SS_SCL_LCNT Standard Speed I2C Clock SCL Low Count Register 0x18 32 read-write 0x024C 0xFFFF IC_SS_SCL_LCNT This register must be set before any I2C bus transaction can take place to ensure proper I/O timing [15:0] read-write RESERVED1 reserved1 [31:16] read-only IC_FS_SCL_HCNT Fast Speed I2C Clock SCL High Count Register 0x1C 32 read-write 0x004b 0xFFFF IC_FS_SCL_HCNT This register must be set before any I2C bus transaction can take place to ensure proper I/O timing [15:0] read-write RESERVED1 reserved1 [31:16] read-only IC_FS_SCL_LCNT Fast Speed I2C Clock SCL Low Count Register 0x20 32 read-write 0x00a3 0xFFFF IC_FS_SCL_LCNT This register must be set before any I2C bus transaction can take place to ensure proper I/O timing [15:0] read-write RESERVED1 reserved1 [31:16] read-only IC_HS_SCL_HCNT High Speed I2C Clock SCL High Count Register 0x24 32 read-write 0x000f 0xFFFF IC_HS_SCL_HCNT This register must be set before any I2C bus transaction can take place to ensure proper I/O timing [15:0] read-write RESERVED1 reserved1 [31:16] read-only IC_HS_SCL_LCNT High Speed I2C Clock SCL Low Count Register 0x28 32 read-write 0x0028 0xFFFF IC_HS_SCL_LCNT This register must be set before any I2C bus transaction can take place to ensure proper I/O timing [15:0] read-write RESERVED1 reserved1 [31:16] read-only IC_INTR_STAT I2C Interrupt Status Register 0x2C 32 read-only 0x0000 0xFFFF R_RX_UNDER Set if the processor attempts to read the receive buffer when it is empty by reading from the IC_DATA_CMD register [0:0] read-only R_RX_OVER Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and an additional byte is received from an external I2C device [1:1] read-only R_RX_FULL Set when the receive buffer reaches or goes above the RX_TL threshold in the IC_RX_TL register. [2:2] read-only R_TX_OVER Set during transmit if the transmit buffer is filled to IC_TX_BUFFER_DEPTH and the processor attempts to issue another I2C command by writing to the IC_DATA_CMD register. [3:3] read-only R_TX_EMPTY This bit is set to 1 when the transmit buffer is at or below the threshold value set in the IC_TX_TL register. [4:4] read-only R_RD_REQ This bit is set to 1 when DW_apb_i2c is acting as a slave and another I2C master is attempting to read data from DW_apb_i2c. [5:5] read-only R_TX_ABRT This bit indicates if DW_apb_i2c, as an I2C transmitter, is unable to complete the intended actions on the contents of the transmit FIFO [6:6] read-only R_RX_DONE When the DW_apb_i2c is acting as a slave-transmitter, this bit is set to 1 if the master does not acknowledge a transmitted byte [7:7] read-only R_ACTIVITY This bit captures DW_apb_i2c activity and stays set until it is cleared [8:8] read-only R_STOP_DET Indicates whether a STOP condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode. [9:9] read-only R_START_DET Indicates whether a START or RESTART condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode. [10:10] read-only R_GEN_CALL Set only when a General Call address is received and it is acknowledged [11:11] read-only R_RESTART_DET Indicates whether a RESTART condition has occurred on the I2C interface when DW_apb_i2c is operating in slave mode and the slave is the addressed slave [12:12] read-only R_MST_ON_HOLD Indicates whether a master is holding the bus and the Tx FIFO is empty. [13:13] read-only M_SCL_STUCK_AT_LOW Indicates whether the SCL Line is stuck at low for the IC_SCL_STUCK_LOW_TIMOUT number of ic_clk periods [14:14] read-only RESERVED1 reserved1 [31:15] read-only IC_INTR_MASK I2C Interrupt Mask Register 0x30 32 read-write 0x08FF 0xFFFF M_RX_UNDER This bit mask their corresponding interrupt status bits in the IC_INTR_STAT register. [0:0] read-write M_RX_OVER This bit mask their corresponding interrupt status bits in the IC_INTR_STAT register. [1:1] read-write M_RX_FULL This bit mask their corresponding interrupt status bits in the IC_INTR_STAT register. [2:2] read-write M_TX_OVER This bit mask their corresponding interrupt status bits in the IC_INTR_STAT register [3:3] read-write M_TX_EMPTY This bit mask their corresponding interrupt status bits in the IC_INTR_STAT register. [4:4] read-write M_RD_REQ This bit mask their corresponding interrupt status bits in the IC_INTR_STAT register. [5:5] read-write M_TX_ABRT This bit mask their corresponding interrupt status bits in the IC_INTR_STAT register. [6:6] read-write M_RX_DONE This bit mask their corresponding interrupt status bits in the IC_INTR_STAT register. [7:7] read-write M_ACTIVITY This bit mask their corresponding interrupt status bits in the IC_INTR_STAT register. [8:8] read-write M_STOP_DET This bit mask their corresponding interrupt status bits in the IC_INTR_STAT register. [9:9] read-write M_START_DET This bit mask their corresponding interrupt status bits in the IC_INTR_STAT register. [10:10] read-write M_GEN_CALL This bit mask their corresponding interrupt status bits in the IC_INTR_STAT register. [11:11] read-write M_RESTART_DET Indicates whether a RESTART condition has occurred on the I2C interface when DW_apb_i2c is operating in slave mode and the slave is the addressed slave [12:12] read-write M_MST_ON_HOLD Indicates whether a master is holding the bus and the Tx FIFO is empty. [13:13] read-write M_SCL_STUCK_AT_LOW Indicates whether the SCL Line is stuck at low for the IC_SCL_STUCK_LOW_TIMOUT number of ic_clk periods [14:14] read-write RESERVED1 reserved1 [31:15] read-only IC_RAW_INTR_STAT I2C Raw Interrupt Status Register 0x34 32 read-only 0x0000 0xFFFF RX_UNDER Set if the processor attempts to read the receive buffer when it is empty by reading from the IC_DATA_CMD register [0:0] read-only RX_OVER Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and an additional byte is received from an external I2C device [1:1] read-only RX_FULL Set when the receive buffer reaches or goes above the RX_TL threshold in the IC_RX_TL register. [2:2] read-only TX_OVER Set during transmit if the transmit buffer is filled to IC_TX_BUFFER_DEPTH and the processor attempts to issue another I2C command by writing to the IC_DATA_CMD register. [3:3] read-only TX_EMPTY This bit is set to 1 when the transmit buffer is at or below the threshold value set in the IC_TX_TL register. [4:4] read-only RD_REQ This bit is set to 1 when DW_apb_i2c is acting as a slave and another I2C master is attempting to read data from DW_apb_i2c. [5:5] read-only TX_ABRT This bit indicates if DW_apb_i2c, as an I2C transmitter, is unable to complete the intended actions on the contents of the transmit FIFO [6:6] read-only RX_DONE When the DW_apb_i2c is acting as a slave-transmitter, this bit is set to 1 if the master does not acknowledge a transmitted byte [7:7] read-only ACTIVITY This bit captures DW_apb_i2c activity and stays set until it is cleared [8:8] read-only STOP_DET Indicates whether a STOP condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode. [9:9] read-only START_DET Indicates whether a START or RESTART condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode. [10:10] read-only GEN_CALL Set only when a General Call address is received and it is acknowledged [11:11] read-only RESTART_DET Indicates whether a RESTART condition has occurred on the I2C interface when DW_apb_i2c is operating in slave mode and the slave is the addressed slave [12:12] read-only MST_ON_HOLD Indicates whether a master is holding the bus and the Tx FIFO is empty. [13:13] read-only SCL_STUCK_AT_LOW Indicates whether the SCL Line is stuck at low for the IC_SCL_STUCK_LOW_TIMOUT number of ic_clk periods [14:14] read-only RESERVED1 reserved1 [31:15] read-only IC_RX_TL I2C Receive FIFO Threshold Register 0x38 32 read-write 0x0008 0xFF RX_TL Receive FIFO Threshold Level [7:0] read-write RESERVED1 reserved1 [31:8] read-only IC_TX_TL I2C Transmit FIFO Threshold Register 0x3C 32 read-write 0x0008 0xFF TX_TL Transmit FIFO Threshold Level [7:0] read-write RESERVED1 reserved1 [31:8] read-only IC_CLR_INTR Clear Combined and Individual Interrupt Register 0x40 32 read-only 0x0000 0x01 CLR_INTR Read this register to clear the combined interrupt, all individual interrupts, and the IC_TXABRT_SOURCE register [0:0] read-only RESERVED1 reserved1 [31:1] read-only IC_CLR_RX_UNDER Clear RX_UNDER Interrupt Register 0x44 32 read-only 0x00000000 0x01 CLR_RX_UNDER Read this register to clear the RX_UNDER interrupt (bit 0) of the IC_RAW_INTR_STAT register. [0:0] read-only RESERVED1 reserved1 [31:1] read-only IC_CLR_RX_OVER Clear RX_OVER Interrupt Register 0x48 32 read-only 0x0000 0x01 CLR_RX_OVER Read this register to clear the RX_OVER interrupt (bit 1) of the IC_RAW_INTR_STAT register [0:0] read-only RESERVED1 reserved1 [31:1] read-only IC_CLR_TX_OVER Clear TX_OVER Interrupt Register 0x4C 32 read-only 0x00000000 0x01 CLR_TX_OVER Read this register to clear the TX_OVER interrupt (bit 3) of the IC_RAW_INTR_STAT register. [0:0] read-only RESERVED1 reserved1 [31:1] read-only IC_CLR_RD_REQ Clear RD_REQ Interrupt Register 0x50 32 read-only 0x0000 0x01 CLR_RD_REQ Read this register to clear the RD_REQ interrupt (bit 5) of the IC_RAW_INTR_STAT register. [0:0] read-only RESERVED1 reserved1 [31:1] read-only IC_CLR_TX_ABRT Clear TX_ABRT Interrupt Register 0x54 32 read-only 0x0000 0x01 CLR_TX_ABRT Read this register to clear the TX_ABRT interrupt (bit 6) of the C_RAW_INTR_STAT register, and the IC_TX_ABRT_SOURCE register [0:0] read-only RESERVED1 reserved1 [31:1] read-only IC_CLR_RX_DONE Clear RX_DONE Interrupt Register 0x58 32 read-only 0x0000 0x01 CLR_RX_DONE Read this register to clear the RX_DONE interrupt (bit 7) of the IC_RAW_INTR_STAT register [0:0] read-only RESERVED1 reserved1 [31:1] read-only IC_CLR_ACTIVITY Clear ACTIVITY Interrupt Register 0x5C 32 read-only 0x0000 0x01 CLR_ACTIVITY Reading this register clears the ACTIVITY interrupt if the I2C is not active any more [0:0] read-only RESERVED1 reserved1 [31:1] read-only IC_CLR_STOP_DET Clear STOP_DET Interrupt Register 0x60 32 read-only 0x0000 0x01 CLR_STOP_DET Read this register to clear the STOP_DET interrupt (bit 9) of the IC_RAW_INTR_STAT register. [0:0] read-only RESERVED1 reserved1 [31:1] read-only IC_CLR_START_DET Clear START_DET Interrupt Register 0x64 32 read-only 0x0000 0x01 CLR_START_DET Read this register to clear the START_DET interrupt (bit 10) of the IC_RAW_INTR_STAT register [0:0] read-only RESERVED1 reserved1 [31:1] read-only IC_CLR_GEN_CALL Clear GEN_CALL Interrupt Register 0x68 32 read-only 0x0000 0x01 CLR_GEN_CALL Read this register to clear the GEN_CALL interrupt (bit 11) of IC_RAW_INTR_STAT register [0:0] read-only RESERVED1 reserved1 [31:1] read-only IC_ENABLE Clear GEN_CALL Interrupt Register 0x6C 32 read-write 0x0000 0x01 EN Controls whether the DW_apb_i2c is enabled [0:0] read-write Disable Disables DW_apb_i2c (TX and RX FIFOs are held in an erased state) 0 Enable Enables DW_apb_i2c 1 ABORT When set, the controller initiates the transfer abort [1:1] read-write Disable ABORT not initiated or ABORT done 0 Enable ABORT operation in progress 1 TX_CMD_BLOCK none [2:2] read-write Disable The transmission of data starts on I2C bus automatically, as soon as the first data is available in the Tx FIFO 0 Enable Blocks the transmission of data on I2C bus even if Tx FIFO has data to transmit 1 SDA_STUCK_RECOVERY_ENABLE SDA STUCK RECOVERY ENABLE [3:3] read-write RESERVED1 reserved1 [31:4] read-only IC_STATUS I2C Status Register 0x70 32 read-only 0x00000006 0x0F ACTIVITY I2C Activity Status [0:0] read-only TFNF Transmit FIFO Not Full [1:1] read-only Disable Transmit FIFO is full 0 Enable Transmit FIFO is not full 1 TFE Transmit FIFO Completely Empty [2:2] read-only Disable Transmit FIFO is not empty 0 Enable Transmit FIFO is empty 1 RFNE Receive FIFO Not Empty [3:3] read-only Disable Receive FIFO is not empty 0 Enable Receive FIFO is not empty 1 RFF Receive FIFO Completely Full [4:4] read-only Disable Receive FIFO is not full 0 Enable Receive FIFO is full 1 MST_ACTIVITY Master FSM Activity Status [5:5] read-only Disable Master FSM is in IDLE state so the Master part of DW_apb_i2c is not Active 0 Enable Master FSM is not in IDLE state so the Master part of DW_apb_i2c is Active 1 SLV_ACTIVITY Slave FSM Activity Status [6:6] read-only Disable Slave FSM is in IDLE state so the Slave part of DW_apb_i2c is not Active 0 Enable Slave FSM is not in IDLE state so the Slave part of DW_apb_i2c is Active 1 MST_HOLD_TX_FIFO_EMPTY The I2C master stalls the write transfer when Tx FIFO is empty, and the the last byte does not have the Stop bit set. [7:7] read-only MST_HOLD_RX_FIFO_FULL This bit indicates the BUS Hold in Master mode due to Rx FIFO is Full and additional byte has been received. [8:8] read-only SLV_HOLD_TX_FIFO_EMPTY This bit indicates the BUS Hold in Slave mode for the Read request when the Tx FIFO is empty. [9:9] read-only SLV_HOLD_RX_FIFO_FULL This bit indicates the BUS Hold in Slave mode due to the Rx FIFO being Full and an additional byte being received. [10:10] read-only SDA_STUCK_NOT_RECOVERED This bit indicates that an SDA stuck at low is not recovered after the recovery mechanism. [11:11] read-only RESERVED1 reserved1 [31:12] read-only IC_TXFLR I2C Transmit FIFO Level Register 0x74 32 read-only 0x0000 0xF TXFLR Contains the number of valid data entries in the transmit FIFO. [3:0] read-only RESERVED1 reserved1 [31:4] read-only IC_RXFLR I2C Receive FIFO Level Register 0x78 32 read-only 0x0000 0xF RXFLR Receive FIFO Level. Contains the number of valid data entries in the receive FIFO [3:0] read-only RESERVED1 reserved1 [31:4] read-only IC_SDA_HOLD I2C SDA Hold Time Length Register 0x7C 32 read-write 0x0001 0xF IC_SDA_TX_HOLD Sets the required SDA hold time in units of ic_clk period,when I2C acts as a transmitter. [15:0] read-write IC_SDA_RX_HOLD Sets the required SDA hold time in units of ic_clk period,when I2C acts as a receiver. [23:16] read-write RESERVED1 reserved1 [31:24] read-only IC_TX_ABRT_SOURCE I2C Transmit Abort Source Register 0x80 32 read-only 0x00000000 0xFFFF ABRT_7B_ADDR_NOACK 1: Master is in 7-bit addressing mode and the address sent was not acknowledged by any slave [0:0] read-only ABRT_10ADDR1_NOACK 1: Master is in 10-bit address mode and the first 10-bit address byte was not acknowledged by any slave [1:1] read-only ABRT_10ADDR2_NOACK 1: Master is in 10-bit address mode and the second address byte of the 10-bit address was not acknowledged by any slave [2:2] read-only ABRT_TXDATA_NOACK 1: This is a master-mode only bit. Master has received an acknowledgement for the address, but when it sent data byte(s) following the address, it did not receive an acknowledge from the remote slave(s) [3:3] read-only ABRT_GCALL_NOACK 1: DW_apb_i2c in master mode sent a General Call and no slave on the bus acknowledged the General Call [4:4] read-only ABRT_GCALL_READ 1: DW_apb_i2c in master mode sent a General Call but the user programmed the byte following the General Call to be a read from the bus (IC_DATA_CMD[9] is set to 1) [5:5] read-only ABRT_HS_ACKDET 1: Master is in High Speed mode and the High Speed Master code was acknowledged [6:6] read-only ABRT_SBYTE_ACKDET 1: Master has sent a START Byte and the START Byte was acknowledged (wrong behavior) [7:7] read-only ABRT_HS_NORSTRT 1: The restart is disabled (IC_RESTART_EN bit (IC_CON[5]) = 0) and the user is trying to use the master to transfer data in High Speed mode [8:8] read-only ABRT_SBYTE_NORSTRT 1: The restart is disabled (IC_RESTART_EN bit (IC_CON[5]) = 0) and the user is trying to send a START Byte [9:9] read-only ABRT_10B_RD_NORSTRT 1: The restart is disabled (IC_RESTART_EN bit (IC_CON[5]) = 0) and the master sends a read command in 10-bit addressing mode [10:10] read-only ABRT_MASTER_DIS 1: User tries to initiate a Master operation with the Master mode disabled [11:11] read-only ARB_LOST 1: Master has lost arbitration, or if IC_TX_ABRT_SOURCE[14] is also set, then the slave transmitter has lost arbitration [12:12] read-only ABRT_SLVFLUSH_TXFIFO 1: Slave has received a read command and some data exists in the TX FIFO so the slave issues a TX_ABRT interrupt to flush old data in TX FIFO [13:13] read-only ABRT_SLV_ARBLOST 1: Slave lost the bus while transmitting data to a remote master. IC_TX_ABRT_SOURCE[12] is set at the same time [14:14] read-only ABRT_SLVRD_INTX 1: When the processor side responds to a slave mode request for data to be transmitted to a remote master and user writes a 1 in CMD (bit 8) of IC_DATA_CMD register [15:15] read-only ABRT_USER_ABRT This is a master-mode-only bit. Master has detected the transfer abort (IC_ENABLE[1]). [16:16] read-only ABRT_SDA_STUCK_AT_LOW Master detects the SDA is Stuck at low for the IC_SDA_STUCK_AT_LOW_TIMEOUT value of ic_clks [17:17] read-only ABRT_DEVICE_NOACK Master initiates the DEVICE_ID transfer and the device ID sent is not acknowledged by any slave [18:18] read-only ABRT_DEVICE_SLVADDR_NOACK Master is initiating the DEVICE_ID transfer and the slave address sent was not acknowledged by any slave [19:19] read-only ABRT_DEVICE_WRITE Master is initiating the DEVICE_ID transfer and the Tx- FIFO consists of write commands. [20:20] read-only RESERVED1 reserved1 [22:21] read-only TX_FLUSH_CNT This field indicates the number of Tx FIFO data commands that are flushed due to TX_ABRT interrupt [31:23] read-only IC_SLV_DATA_NACK_ONLY Generate Slave Data NACK Register 0x84 32 read-write 0x00000000 0xFFFF NACK Generate NACK. This NACK generation only occurs when DW_apb_i2c is a slave receiver. [0:0] read-write RESERVED1 reserved1 [31:1] read-only IC_DMA_CR DMA Control Register 0x88 32 read-write 0x00000000 0xF RDMAE Receive DMA Enable [0:0] read-write Disable Receive DMA disabled 0 Enable Receive DMA enabled 1 TDMAE Transmit DMA Enable.This bit enables/disables the transmit FIFO DMA channel [1:1] read-write Disable Transmit DMA disabled 0 Enable Transmit DMA enabled 1 RESERVED1 reserved1 [31:2] read-only IC_DMA_TDLR DMA Transmit Data Level Register 0x8C 32 read-write 0x00000000 0xF DMATDL This bit field controls the level at which a DMA request is made by the transmit logic [3:0] read-write RESERVED1 reserved1 [31:4] read-only IC_DMA_RDLR I2C Receive Data Level Register 0x90 32 read-write 0x00000000 0x7 DMARDL This bit field controls the level at which a DMA request is made by the receive logic [3:0] read-write RESERVED1 reserved1 [31:4] read-only IC_SDA_SETUP I2C SDA Setup Register 0x94 32 read-write 0x00000000 0xFFFF SDA_SETUP This register controls the amount of time delay (in terms of number of ic_clk clock periods) [7:0] read-write RESERVED1 reserved1 [31:8] read-only IC_ACK_GENERAL_CALL I2C ACK General Call Register 0x98 32 read-write 0x00000001 0xF ACK_GEN_CALL ACK General Call [0:0] read-write Disable DW_apb_i2c does not generate General Call interrupts 0 Enable DW_apb_i2c responds with a ACK (by asserting ic_data_oe) when it receives a General Call. 1 RESERVED1 reserved1 [31:1] read-only IC_ENABLE_STATUS I2C Enable Status Register 0x9C 32 read-only 0x00000000 0xF IC_EN This bit always reflects the value driven on the output port ic_en. [0:0] read-only Disable DW_apb_i2c is deemed completely inactive 0 Enable DW_apb_i2c is deemed to be in an enabled state 1 SLV_DISABLED_WHILE_BUSY This bit indicates if a potential or active Slave operation has been aborted due to the setting of the IC_ENABLE register from 1 to 0 [1:1] read-only Disable DW_apb_i2c is deemed to have been disabled when there is master activity, or when the I2C bus is idle. 0 Enable DW_apb_i2c is deemed to have forced a NACK during any part of an I2C transfer 1 SLV_RX_DATA_LOST Slave Received Data Lost [2:2] read-only Disable DW_apb_i2c is deemed to have been actively engaged in an aborted I2C transfer (with matching address) and the data phase of the I2C transfer has been entered, even though a data byte has been responded with a NACK 0 Enable DW_apb_i2c is deemed to have been disabled without being actively involved in the data phase of a Slave-Receiver transfer 1 RESERVED1 reserved1 [31:3] read-only IC_FS_SPKLEN I2C SS and FS Spike Suppression Limit Register IC_UFM_SPKLEN 0xA0 32 read-write 0x00000006 0x000000FF IC_FS_SPKLEN This register sets the duration, measured in ic_clk cycles, of the longest spike in the SCL or SDA lines that are filtered out by the spike suppression logic [7:0] read-write RESERVED1 reserved1 [31:8] read-only IC_HS_SPKLEN I2C HS Spike Suppression Limit Register 0xA4 32 read-write 0x00000002 0x000000FF IC_HS_SPKLEN This register sets the duration, measured in ic_clk cycles, of the longest spike in the SCL or SDA lines that are filtered out by the spike suppression logic [7:0] read-write RESERVED1 reserved1 [31:8] read-only IC_CLR_RESTART_DET Clear RESTART_DET Interrupt Register 0xA8 32 read-only 0x0000 CLR_RESTART_DET Read this register to clear the RESTART_DET interrupt (bit 12) of the IC_RAW_INTR_STAT registe [0:0] read-only RESERVED1 reserved1 [31:1] read-only IC_COMP_PARAM_1 I2C HS Spike Suppression Limit Register 0xF4 32 read-only 0x000808EC CLR_RESTART_DET Read this register to clear the RESTART_DET interrupt (bit 12) of the IC_RAW_INTR_STAT register [1:0] read-only MAX_SPEED_MODE Maximum Speed Mode [3:2] read-only HC_COUNT_VALUES Hard Code the count values [4:4] read-only INTR_IO Single Interrupt Output port [5:5] read-only HAS_DMA DMA Handshake Interface signal [6:6] read-only ADD_ENCODED_PARAMS Add Encoded Parameters [7:7] read-only RX_BUFFER_DEPTH Depth of receive buffer;the buffer is 8 bits wide;2 to 256 [15:8] read-only TX_BUFFER_DEPTH Depth of Transmit buffer;the buffer is 8 bits wide;2 to 256 [23:16] read-only RESERVED1 reserved1 [31:24] read-only IC_COMP_VERSION I2C Component Version Register 0xF8 32 read-only 0x00000000 IC_COMP_VERSION Signifies the component version [31:0] read-only IC_COMP_TYPE I2C Component Type Register 0xFC 32 read-only 0x00000000 IC_COMP_TYPE Design ware Component Type number = 0x44_57_01_40 [31:0] read-only IC_SCL_STUCK_AT_LOW_TIMEOUT I2C SCL Stuck at Low Timeout 0xAC 32 read-write 0xFFFFFFFF IC_SCL_STUCK_LOW_TIMEOUT Generates the interrupt to indicate SCL stuck at low if it detects the SCL stuck at low for the IC_SCL_STUCK_LOW_TIMEOUT in units of ic_clk period [31:0] read-write IC_SDA_STUCK_AT_LOW_TIMEOUT I2C SDA Stuck at Low Timeout 0xB0 32 read-write 0xFFFFFFFF IC_SDA_STUCK_LOW_TIMEOUT Initiates the recovery of SDA line , if it detects the SDA stuck at low for the IC_SDA_STUCK_LOW_TIMEOUT in units of ic_clk period. [31:0] read-write IC_CLR_SCL_STUCK_DET Clear SCL Stuck at Low Detect Interrupt Register 0xB4 32 read-only 0x0 CLR_SCL_STUCK Read this register to clear the SCL_STUCK_DET interrupt [0:0] read-only RESERVED1 reserved1 [31:1] read-only IC_DEVICE_ID I2C Device ID 0xB8 32 read-only 0x00000001 DEVICE_ID Contains the Device-ID of the component assigned through the configuration parameter [0:0] read-only RESERVED1 reserved1 [31:1] read-only IC_SMBUS_CLOCK_LOW_SEXT SMBUS Slave Clock Extend Timeout Register 0xBC 32 read-write 0xFFFFFFFF 0xFFFFFFFF SMBUS_CLK_LOW_SEXT_TIMEOUT The values in this register are in units of ic_clk period. [31:0] read-write IC_SMBUS_CLOCK_LOW_MEXT SMBUS Master extend clock Timeout Register 0xC0 32 read-write 0xFFFFFFFF 0xFFFFFFFF SMBUS_CLK_LOW_MEXT_TIMEOUT The values in this register are in units of ic_clk period.. [31:0] read-write IC_SMBUS_THIGH_MAX_IDLE_COUNT SMBus Thigh MAX Bus-Idle count Register 0xC4 32 read-write 0XFFFF 0xFFFF SMBUS_THIGH_MAX_BUS_IDLE_CNT The values in this register are in units of ic_clk period. [15:0] read-write RESERVED1 Reserved1 [31:16] read-write IC_SMBUS_INTR_STAT SMBUS Interrupt Status Register 0xC8 32 read-write 0x00 0x00 RESERVED1 Reserved1 [31:0] read-write IC_SMBUS_INTR_MASK Interrupt Mask Register 0xCC 32 read-write 0x00 0x00 RESERVED1 Reserved1 [31:0] read-write IC_SMBUS_INTR_RAW_STATUS SMBUS Raw Interrupt Status Register 0xD0 32 read-write 0x00 0x00 RESERVED1 Reserved1. [31:0] read-write IC_CLR_SMBUS_INTR Clear SMBUS Interrupt Register 0xD4 32 read-write 0x00 0x00 RESERVED1 RESERVED1 [31:0] read-write IC_OPTIONAL_SAR Optional Slave Address Register 0xD8 32 read-write 0x00 0x00 RESERVED1 Reserved1. [31:0] read-write IC_SMBUS_UDID_LSB SMBUS ARP UDID LSB Register 0xDC 32 read-write 0xFFFFFFFF 0xFFFFFFFF IC_SMBUS_ARP_UDID_LSB This field is used to store the LSB 32 bit value of slave unique device identifier used in Address Resolution Protocol. [31:0] read-write I2C1 1.0 Inter Integrated Circuit(I2C) is programmable control bus that provides support for the communications link between integrated circuits in a system I2C 0x47040000 32 read-write 0 0x100 registers I2C1 61 IC_CON This register can be written only when the i2c is disabled, which corresponds to IC_ENABLE[0] being set to 0. Writes at other times have no effect. 0x00 32 read-write 0x007F 0xFFFF MASTER_MODE This bit controls whether the I2C master is enabled. [0:0] read-write Disable master disabled 0 Enable master enabled 1 SPEED These bits control at which speed the I2C operates. Hardware protects against illegal values being programmed by software. [2:1] read-write Standard_Mode standard mode (0 to 100 kbit/s) 1 Fast_Mode fast mode (less than or equal 400 kbit/s) 2 High_Speed_Mode high speed mode (less than or equal 3.4 Mbit/s) 3 IC_10BITADDR_SLAVE When acting as a slave, this bit controls whether the I2C responds to 7- or 10-bit addresses. [3:3] read-write Disable 7-bit addressing. The DW_apb_i2c ignores transactions that involve 10-bit addressing; for 7-bit addressing, only the lower 7 bits of the IC_SAR register are compared 0 Enable 10-bit addressing. The DW_apb_i2c responds to only 10-bit addressing transfers that match the full 10 bits of the IC_SAR register. 1 IC_10BITADDR_MASTER_RD_ONLY the function of this bit is handled by bit 12 of IC_TAR register, and becomes a read-only copy called IC_10BITADDR_MASTER_rd_only [4:4] read-only Disable 7-bit addressing 0 Enable 10-bit addressing 1 IC_RESTART_EN Determines whether RESTART conditions may be sent when acting as a master [5:5] read-write Disable Disabled 0 Enable Enabled 1 IC_SLAVE_DISABLE This bit controls whether I2C has its slave disabled [6:6] read-write Disable slave is enabled 0 Enable slave is disabled 1 STOP_DET_IFADDRESSED The STOP DETECTION interrupt is generated only when the transmitted address matches the slave address of SAR [7:7] read-write Disable Issues the STOP DETECTION irrespective of whether it is addressed or not. 0 Enable issues the STOP DETECTION interrupt only when it is addressed. 1 TX_EMPTY_CTRL This bit controls the generation of the TX EMPTY interrupt, as described in the IC RAW INTR STAT register. [8:8] read-write RESERVED1 reserved1 [9:9] read-only STOP_DET_IF_MASTER_ACTIVE In Master mode. [10:10] read-write Disable Issues the STOP_DET irrespective of whether the master is active. 0 Enable Issues the STOP_DET interrupt only when the master is active 1 BUS_CLEAR_FEATURE_CTRL In Master mode. [11:11] read-write Disable Bus Clear Feature is disabled 0 Enable Bus Clear Feature is enabled 1 RESERVED2 reserved2 [31:12] read-write IC_TAR I2C Target Address Register 0x04 32 read-write 0x10A0 0xFFFF IC_TAR This is the target address for any master transaction [9:0] read-write GC_OR_START If bit 11 (SPECIAL) is set to 1, then this bit indicates whether a General Call or START byte command is to be performed by the DW_apb_i2c [10:10] read-write Disable General Call Address 0 Enable START BYTE 1 SPECIAL This bit indicates whether software performs a General Call or START BYTE command [11:11] read-write Disable ignore bit 10 GC_OR_START and use IC_TAR normally 0 Enable perform special I2C command as specified in GC_OR_START bit 1 IC_10BITADDR_MASTER This bit controls whether the i2c starts its transfers in 7-or 10-bit addressing mode when acting as a master [12:12] read-write Disable 7-bit addressing 0 Enable 10-bit addressing 1 DEVICE_ID If bit 11 (SPECIAL) is set to 1, then this bit indicates whether a Device-ID of a particular slave mentioned in IC_TAR[6:0] is to be performed by the I2C Master [13:13] read-write Disable Device-ID is not performed and checks ic_tar[10] to perform either general call or START byte command. 0 Enable : Device-ID transfer is performed and bytes based on the number of read commands in the Tx-FIFO are received from the targeted slave and put in the Rx-FIFO. 1 RESERVED1 reserved1 [31:14] read-only IC_SAR I2C Slave Address Register 0x08 32 read-write 0x55 0xFFFF IC_SAR The IC_SAR holds the slave address when the I2C is operating as a slave. For 7-bit addressing, only IC_SAR[6:0] is used. [9:0] read-write RESERVED1 reserved1 [31:10] read-only IC_HS_MADDR I2C High Speed Master Mode Code Address Register 0x0C 32 read-write 0x0001 0xF IC_HS_MAR This bit field holds the value of the I2C HS mode master code [2:0] read-write RESERVED1 reserved1 [31:3] read-only IC_DATA_CMD I2C Rx/Tx Data Buffer and Command Register 0x10 32 read-write 0x0000 0xFFFF DAT This register contains the data to be transmitted or received on the I2C bus [7:0] read-write CMD This bit controls whether a read or a write is performed [8:8] write-only Disable write 0 Enable Read 1 STOP This bit controls whether a STOP is issued after the byte is sent or received [9:9] write-only Disable STOP is not issued after this byte, regardless of whether or not the Tx FIFO is empty 0 Enable STOP is issued after this byte, regardless of whether or not the Tx FIFO is empty 1 RESTART This bit controls whether a RESTART is issued before the byte is sent or received [10:10] write-only Disable If IC_RESTART_EN is 1, a RESTART is issued only if the transfer direction is changing from the previous command 0 Enable If IC_RESTART_EN is 1, a RESTART is issued before the data is sent/received 1 FIRST_DATA_BYTE Indicates the first data byte received after the address phase for receive transfer in Master receiver or Slave receiver mode [11:11] read-only Disable If IC_RESTART_EN is 1, a RESTART is issued only if the transfer direction is changing from the previous command 0 Enable If IC_RESTART_EN is 1, a RESTART is issued before the data is sent/received 1 RESERVED1 reserved1 [31:12] read-only IC_SS_SCL_HCNT Standard Speed I2C Clock SCL High Count Register 0x14 32 read-write 0x01F4 0xFFFF IC_SS_SCL_HCNT This register must be set before any I2C bus transaction can take place to ensure proper I/O timing [15:0] read-write RESERVED1 reserved1 [31:16] read-only IC_SS_SCL_LCNT Standard Speed I2C Clock SCL Low Count Register 0x18 32 read-write 0x024C 0xFFFF IC_SS_SCL_LCNT This register must be set before any I2C bus transaction can take place to ensure proper I/O timing [15:0] read-write RESERVED1 reserved1 [31:16] read-only IC_FS_SCL_HCNT Fast Speed I2C Clock SCL High Count Register 0x1C 32 read-write 0x004b 0xFFFF IC_FS_SCL_HCNT This register must be set before any I2C bus transaction can take place to ensure proper I/O timing [15:0] read-write RESERVED1 reserved1 [31:16] read-only IC_FS_SCL_LCNT Fast Speed I2C Clock SCL Low Count Register 0x20 32 read-write 0x00a3 0xFFFF IC_FS_SCL_LCNT This register must be set before any I2C bus transaction can take place to ensure proper I/O timing [15:0] read-write RESERVED1 reserved1 [31:16] read-only IC_HS_SCL_HCNT High Speed I2C Clock SCL High Count Register 0x24 32 read-write 0x000f 0xFFFF IC_HS_SCL_HCNT This register must be set before any I2C bus transaction can take place to ensure proper I/O timing [15:0] read-write RESERVED1 reserved1 [31:16] read-only IC_HS_SCL_LCNT High Speed I2C Clock SCL Low Count Register 0x28 32 read-write 0x0028 0xFFFF IC_HS_SCL_LCNT This register must be set before any I2C bus transaction can take place to ensure proper I/O timing [15:0] read-write RESERVED1 reserved1 [31:16] read-only IC_INTR_STAT I2C Interrupt Status Register 0x2C 32 read-only 0x0000 0xFFFF R_RX_UNDER Set if the processor attempts to read the receive buffer when it is empty by reading from the IC_DATA_CMD register [0:0] read-only R_RX_OVER Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and an additional byte is received from an external I2C device [1:1] read-only R_RX_FULL Set when the receive buffer reaches or goes above the RX_TL threshold in the IC_RX_TL register. [2:2] read-only R_TX_OVER Set during transmit if the transmit buffer is filled to IC_TX_BUFFER_DEPTH and the processor attempts to issue another I2C command by writing to the IC_DATA_CMD register. [3:3] read-only R_TX_EMPTY This bit is set to 1 when the transmit buffer is at or below the threshold value set in the IC_TX_TL register. [4:4] read-only R_RD_REQ This bit is set to 1 when DW_apb_i2c is acting as a slave and another I2C master is attempting to read data from DW_apb_i2c. [5:5] read-only R_TX_ABRT This bit indicates if DW_apb_i2c, as an I2C transmitter, is unable to complete the intended actions on the contents of the transmit FIFO [6:6] read-only R_RX_DONE When the DW_apb_i2c is acting as a slave-transmitter, this bit is set to 1 if the master does not acknowledge a transmitted byte [7:7] read-only R_ACTIVITY This bit captures DW_apb_i2c activity and stays set until it is cleared [8:8] read-only R_STOP_DET Indicates whether a STOP condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode. [9:9] read-only R_START_DET Indicates whether a START or RESTART condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode. [10:10] read-only R_GEN_CALL Set only when a General Call address is received and it is acknowledged [11:11] read-only R_RESTART_DET Indicates whether a RESTART condition has occurred on the I2C interface when DW_apb_i2c is operating in slave mode and the slave is the addressed slave [12:12] read-only R_MST_ON_HOLD Indicates whether a master is holding the bus and the Tx FIFO is empty. [13:13] read-only M_SCL_STUCK_AT_LOW Indicates whether the SCL Line is stuck at low for the IC_SCL_STUCK_LOW_TIMOUT number of ic_clk periods [14:14] read-only RESERVED1 reserved1 [31:15] read-only IC_INTR_MASK I2C Interrupt Mask Register 0x30 32 read-write 0x08FF 0xFFFF M_RX_UNDER This bit mask their corresponding interrupt status bits in the IC_INTR_STAT register. [0:0] read-write M_RX_OVER This bit mask their corresponding interrupt status bits in the IC_INTR_STAT register. [1:1] read-write M_RX_FULL This bit mask their corresponding interrupt status bits in the IC_INTR_STAT register. [2:2] read-write M_TX_OVER This bit mask their corresponding interrupt status bits in the IC_INTR_STAT register [3:3] read-write M_TX_EMPTY This bit mask their corresponding interrupt status bits in the IC_INTR_STAT register. [4:4] read-write M_RD_REQ This bit mask their corresponding interrupt status bits in the IC_INTR_STAT register. [5:5] read-write M_TX_ABRT This bit mask their corresponding interrupt status bits in the IC_INTR_STAT register. [6:6] read-write M_RX_DONE This bit mask their corresponding interrupt status bits in the IC_INTR_STAT register. [7:7] read-write M_ACTIVITY This bit mask their corresponding interrupt status bits in the IC_INTR_STAT register. [8:8] read-write M_STOP_DET This bit mask their corresponding interrupt status bits in the IC_INTR_STAT register. [9:9] read-write M_START_DET This bit mask their corresponding interrupt status bits in the IC_INTR_STAT register. [10:10] read-write M_GEN_CALL This bit mask their corresponding interrupt status bits in the IC_INTR_STAT register. [11:11] read-write M_RESTART_DET Indicates whether a RESTART condition has occurred on the I2C interface when DW_apb_i2c is operating in slave mode and the slave is the addressed slave [12:12] read-write M_MST_ON_HOLD Indicates whether a master is holding the bus and the Tx FIFO is empty. [13:13] read-write M_SCL_STUCK_AT_LOW Indicates whether the SCL Line is stuck at low for the IC_SCL_STUCK_LOW_TIMOUT number of ic_clk periods [14:14] read-write RESERVED1 reserved1 [31:15] read-only IC_RAW_INTR_STAT I2C Raw Interrupt Status Register 0x34 32 read-only 0x0000 0xFFFF RX_UNDER Set if the processor attempts to read the receive buffer when it is empty by reading from the IC_DATA_CMD register [0:0] read-only RX_OVER Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and an additional byte is received from an external I2C device [1:1] read-only RX_FULL Set when the receive buffer reaches or goes above the RX_TL threshold in the IC_RX_TL register. [2:2] read-only TX_OVER Set during transmit if the transmit buffer is filled to IC_TX_BUFFER_DEPTH and the processor attempts to issue another I2C command by writing to the IC_DATA_CMD register. [3:3] read-only TX_EMPTY This bit is set to 1 when the transmit buffer is at or below the threshold value set in the IC_TX_TL register. [4:4] read-only RD_REQ This bit is set to 1 when DW_apb_i2c is acting as a slave and another I2C master is attempting to read data from DW_apb_i2c. [5:5] read-only TX_ABRT This bit indicates if DW_apb_i2c, as an I2C transmitter, is unable to complete the intended actions on the contents of the transmit FIFO [6:6] read-only RX_DONE When the DW_apb_i2c is acting as a slave-transmitter, this bit is set to 1 if the master does not acknowledge a transmitted byte [7:7] read-only ACTIVITY This bit captures DW_apb_i2c activity and stays set until it is cleared [8:8] read-only STOP_DET Indicates whether a STOP condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode. [9:9] read-only START_DET Indicates whether a START or RESTART condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode. [10:10] read-only GEN_CALL Set only when a General Call address is received and it is acknowledged [11:11] read-only RESTART_DET Indicates whether a RESTART condition has occurred on the I2C interface when DW_apb_i2c is operating in slave mode and the slave is the addressed slave [12:12] read-only MST_ON_HOLD Indicates whether a master is holding the bus and the Tx FIFO is empty. [13:13] read-only SCL_STUCK_AT_LOW Indicates whether the SCL Line is stuck at low for the IC_SCL_STUCK_LOW_TIMOUT number of ic_clk periods [14:14] read-only RESERVED1 reserved1 [31:15] read-only IC_RX_TL I2C Receive FIFO Threshold Register 0x38 32 read-write 0x0008 0xFF RX_TL Receive FIFO Threshold Level [7:0] read-write RESERVED1 reserved1 [31:8] read-only IC_TX_TL I2C Transmit FIFO Threshold Register 0x3C 32 read-write 0x0008 0xFF TX_TL Transmit FIFO Threshold Level [7:0] read-write RESERVED1 reserved1 [31:8] read-only IC_CLR_INTR Clear Combined and Individual Interrupt Register 0x40 32 read-only 0x0000 0x01 CLR_INTR Read this register to clear the combined interrupt, all individual interrupts, and the IC_TXABRT_SOURCE register [0:0] read-only RESERVED1 reserved1 [31:1] read-only IC_CLR_RX_UNDER Clear RX_UNDER Interrupt Register 0x44 32 read-only 0x00000000 0x01 CLR_RX_UNDER Read this register to clear the RX_UNDER interrupt (bit 0) of the IC_RAW_INTR_STAT register. [0:0] read-only RESERVED1 reserved1 [31:1] read-only IC_CLR_RX_OVER Clear RX_OVER Interrupt Register 0x48 32 read-only 0x0000 0x01 CLR_RX_OVER Read this register to clear the RX_OVER interrupt (bit 1) of the IC_RAW_INTR_STAT register [0:0] read-only RESERVED1 reserved1 [31:1] read-only IC_CLR_TX_OVER Clear TX_OVER Interrupt Register 0x4C 32 read-only 0x00000000 0x01 CLR_TX_OVER Read this register to clear the TX_OVER interrupt (bit 3) of the IC_RAW_INTR_STAT register. [0:0] read-only RESERVED1 reserved1 [31:1] read-only IC_CLR_RD_REQ Clear RD_REQ Interrupt Register 0x50 32 read-only 0x0000 0x01 CLR_RD_REQ Read this register to clear the RD_REQ interrupt (bit 5) of the IC_RAW_INTR_STAT register. [0:0] read-only RESERVED1 reserved1 [31:1] read-only IC_CLR_TX_ABRT Clear TX_ABRT Interrupt Register 0x54 32 read-only 0x0000 0x01 CLR_TX_ABRT Read this register to clear the TX_ABRT interrupt (bit 6) of the C_RAW_INTR_STAT register, and the IC_TX_ABRT_SOURCE register [0:0] read-only RESERVED1 reserved1 [31:1] read-only IC_CLR_RX_DONE Clear RX_DONE Interrupt Register 0x58 32 read-only 0x0000 0x01 CLR_RX_DONE Read this register to clear the RX_DONE interrupt (bit 7) of the IC_RAW_INTR_STAT register [0:0] read-only RESERVED1 reserved1 [31:1] read-only IC_CLR_ACTIVITY Clear ACTIVITY Interrupt Register 0x5C 32 read-only 0x0000 0x01 CLR_ACTIVITY Reading this register clears the ACTIVITY interrupt if the I2C is not active any more [0:0] read-only RESERVED1 reserved1 [31:1] read-only IC_CLR_STOP_DET Clear STOP_DET Interrupt Register 0x60 32 read-only 0x0000 0x01 CLR_STOP_DET Read this register to clear the STOP_DET interrupt (bit 9) of the IC_RAW_INTR_STAT register. [0:0] read-only RESERVED1 reserved1 [31:1] read-only IC_CLR_START_DET Clear START_DET Interrupt Register 0x64 32 read-only 0x0000 0x01 CLR_START_DET Read this register to clear the START_DET interrupt (bit 10) of the IC_RAW_INTR_STAT register [0:0] read-only RESERVED1 reserved1 [31:1] read-only IC_CLR_GEN_CALL Clear GEN_CALL Interrupt Register 0x68 32 read-only 0x0000 0x01 CLR_GEN_CALL Read this register to clear the GEN_CALL interrupt (bit 11) of IC_RAW_INTR_STAT register [0:0] read-only RESERVED1 reserved1 [31:1] read-only IC_ENABLE Clear GEN_CALL Interrupt Register 0x6C 32 read-write 0x0000 0x01 EN Controls whether the DW_apb_i2c is enabled [0:0] read-write Disable Disables DW_apb_i2c (TX and RX FIFOs are held in an erased state) 0 Enable Enables DW_apb_i2c 1 ABORT When set, the controller initiates the transfer abort [1:1] read-write Disable ABORT not initiated or ABORT done 0 Enable ABORT operation in progress 1 TX_CMD_BLOCK none [2:2] read-write Disable The transmission of data starts on I2C bus automatically, as soon as the first data is available in the Tx FIFO 0 Enable Blocks the transmission of data on I2C bus even if Tx FIFO has data to transmit 1 SDA_STUCK_RECOVERY_ENABLE SDA STUCK RECOVERY ENABLE [3:3] read-write RESERVED1 reserved1 [31:4] read-only IC_STATUS I2C Status Register 0x70 32 read-only 0x00000006 0x0F ACTIVITY I2C Activity Status [0:0] read-only TFNF Transmit FIFO Not Full [1:1] read-only Disable Transmit FIFO is full 0 Enable Transmit FIFO is not full 1 TFE Transmit FIFO Completely Empty [2:2] read-only Disable Transmit FIFO is not empty 0 Enable Transmit FIFO is empty 1 RFNE Receive FIFO Not Empty [3:3] read-only Disable Receive FIFO is not empty 0 Enable Receive FIFO is not empty 1 RFF Receive FIFO Completely Full [4:4] read-only Disable Receive FIFO is not full 0 Enable Receive FIFO is full 1 MST_ACTIVITY Master FSM Activity Status [5:5] read-only Disable Master FSM is in IDLE state so the Master part of DW_apb_i2c is not Active 0 Enable Master FSM is not in IDLE state so the Master part of DW_apb_i2c is Active 1 SLV_ACTIVITY Slave FSM Activity Status [6:6] read-only Disable Slave FSM is in IDLE state so the Slave part of DW_apb_i2c is not Active 0 Enable Slave FSM is not in IDLE state so the Slave part of DW_apb_i2c is Active 1 MST_HOLD_TX_FIFO_EMPTY The I2C master stalls the write transfer when Tx FIFO is empty, and the the last byte does not have the Stop bit set. [7:7] read-only MST_HOLD_RX_FIFO_FULL This bit indicates the BUS Hold in Master mode due to Rx FIFO is Full and additional byte has been received. [8:8] read-only SLV_HOLD_TX_FIFO_EMPTY This bit indicates the BUS Hold in Slave mode for the Read request when the Tx FIFO is empty. [9:9] read-only SLV_HOLD_RX_FIFO_FULL This bit indicates the BUS Hold in Slave mode due to the Rx FIFO being Full and an additional byte being received. [10:10] read-only SDA_STUCK_NOT_RECOVERED This bit indicates that an SDA stuck at low is not recovered after the recovery mechanism. [11:11] read-only RESERVED1 reserved1 [31:12] read-only IC_TXFLR I2C Transmit FIFO Level Register 0x74 32 read-only 0x0000 0xF TXFLR Contains the number of valid data entries in the transmit FIFO. [3:0] read-only RESERVED1 reserved1 [31:4] read-only IC_RXFLR I2C Receive FIFO Level Register 0x78 32 read-only 0x0000 0xF RXFLR Receive FIFO Level. Contains the number of valid data entries in the receive FIFO [3:0] read-only RESERVED1 reserved1 [31:4] read-only IC_SDA_HOLD I2C SDA Hold Time Length Register 0x7C 32 read-write 0x0001 0xF IC_SDA_TX_HOLD Sets the required SDA hold time in units of ic_clk period,when I2C acts as a transmitter. [15:0] read-write IC_SDA_RX_HOLD Sets the required SDA hold time in units of ic_clk period,when I2C acts as a receiver. [23:16] read-write RESERVED1 reserved1 [31:24] read-only IC_TX_ABRT_SOURCE I2C Transmit Abort Source Register 0x80 32 read-only 0x00000000 0xFFFF ABRT_7B_ADDR_NOACK 1: Master is in 7-bit addressing mode and the address sent was not acknowledged by any slave [0:0] read-only ABRT_10ADDR1_NOACK 1: Master is in 10-bit address mode and the first 10-bit address byte was not acknowledged by any slave [1:1] read-only ABRT_10ADDR2_NOACK 1: Master is in 10-bit address mode and the second address byte of the 10-bit address was not acknowledged by any slave [2:2] read-only ABRT_TXDATA_NOACK 1: This is a master-mode only bit. Master has received an acknowledgement for the address, but when it sent data byte(s) following the address, it did not receive an acknowledge from the remote slave(s) [3:3] read-only ABRT_GCALL_NOACK 1: DW_apb_i2c in master mode sent a General Call and no slave on the bus acknowledged the General Call [4:4] read-only ABRT_GCALL_READ 1: DW_apb_i2c in master mode sent a General Call but the user programmed the byte following the General Call to be a read from the bus (IC_DATA_CMD[9] is set to 1) [5:5] read-only ABRT_HS_ACKDET 1: Master is in High Speed mode and the High Speed Master code was acknowledged [6:6] read-only ABRT_SBYTE_ACKDET 1: Master has sent a START Byte and the START Byte was acknowledged (wrong behavior) [7:7] read-only ABRT_HS_NORSTRT 1: The restart is disabled (IC_RESTART_EN bit (IC_CON[5]) = 0) and the user is trying to use the master to transfer data in High Speed mode [8:8] read-only ABRT_SBYTE_NORSTRT 1: The restart is disabled (IC_RESTART_EN bit (IC_CON[5]) = 0) and the user is trying to send a START Byte [9:9] read-only ABRT_10B_RD_NORSTRT 1: The restart is disabled (IC_RESTART_EN bit (IC_CON[5]) = 0) and the master sends a read command in 10-bit addressing mode [10:10] read-only ABRT_MASTER_DIS 1: User tries to initiate a Master operation with the Master mode disabled [11:11] read-only ARB_LOST 1: Master has lost arbitration, or if IC_TX_ABRT_SOURCE[14] is also set, then the slave transmitter has lost arbitration [12:12] read-only ABRT_SLVFLUSH_TXFIFO 1: Slave has received a read command and some data exists in the TX FIFO so the slave issues a TX_ABRT interrupt to flush old data in TX FIFO [13:13] read-only ABRT_SLV_ARBLOST 1: Slave lost the bus while transmitting data to a remote master. IC_TX_ABRT_SOURCE[12] is set at the same time [14:14] read-only ABRT_SLVRD_INTX 1: When the processor side responds to a slave mode request for data to be transmitted to a remote master and user writes a 1 in CMD (bit 8) of IC_DATA_CMD register [15:15] read-only ABRT_USER_ABRT This is a master-mode-only bit. Master has detected the transfer abort (IC_ENABLE[1]). [16:16] read-only ABRT_SDA_STUCK_AT_LOW Master detects the SDA is Stuck at low for the IC_SDA_STUCK_AT_LOW_TIMEOUT value of ic_clks [17:17] read-only ABRT_DEVICE_NOACK Master initiates the DEVICE_ID transfer and the device ID sent is not acknowledged by any slave [18:18] read-only ABRT_DEVICE_SLVADDR_NOACK Master is initiating the DEVICE_ID transfer and the slave address sent was not acknowledged by any slave [19:19] read-only ABRT_DEVICE_WRITE Master is initiating the DEVICE_ID transfer and the Tx- FIFO consists of write commands. [20:20] read-only RESERVED1 reserved1 [22:21] read-only TX_FLUSH_CNT This field indicates the number of Tx FIFO data commands that are flushed due to TX_ABRT interrupt [31:23] read-only IC_SLV_DATA_NACK_ONLY Generate Slave Data NACK Register 0x84 32 read-write 0x00000000 0xFFFF NACK Generate NACK. This NACK generation only occurs when DW_apb_i2c is a slave receiver. [0:0] read-write RESERVED1 reserved1 [31:1] read-only IC_DMA_CR DMA Control Register 0x88 32 read-write 0x00000000 0xF RDMAE Receive DMA Enable [0:0] read-write Disable Receive DMA disabled 0 Enable Receive DMA enabled 1 TDMAE Transmit DMA Enable.This bit enables/disables the transmit FIFO DMA channel [1:1] read-write Disable Transmit DMA disabled 0 Enable Transmit DMA enabled 1 RESERVED1 reserved1 [31:2] read-only IC_DMA_TDLR DMA Transmit Data Level Register 0x8C 32 read-write 0x00000000 0xF DMATDL This bit field controls the level at which a DMA request is made by the transmit logic [3:0] read-write RESERVED1 reserved1 [31:4] read-only IC_DMA_RDLR I2C Receive Data Level Register 0x90 32 read-write 0x00000000 0x7 DMARDL This bit field controls the level at which a DMA request is made by the receive logic [3:0] read-write RESERVED1 reserved1 [31:4] read-only IC_SDA_SETUP I2C SDA Setup Register 0x94 32 read-write 0x00000000 0xFFFF SDA_SETUP This register controls the amount of time delay (in terms of number of ic_clk clock periods) [7:0] read-write RESERVED1 reserved1 [31:8] read-only IC_ACK_GENERAL_CALL I2C ACK General Call Register 0x98 32 read-write 0x00000001 0xF ACK_GEN_CALL ACK General Call [0:0] read-write Disable DW_apb_i2c does not generate General Call interrupts 0 Enable DW_apb_i2c responds with a ACK (by asserting ic_data_oe) when it receives a General Call. 1 RESERVED1 reserved1 [31:1] read-only IC_ENABLE_STATUS I2C Enable Status Register 0x9C 32 read-only 0x00000000 0xF IC_EN This bit always reflects the value driven on the output port ic_en. [0:0] read-only Disable DW_apb_i2c is deemed completely inactive 0 Enable DW_apb_i2c is deemed to be in an enabled state 1 SLV_DISABLED_WHILE_BUSY This bit indicates if a potential or active Slave operation has been aborted due to the setting of the IC_ENABLE register from 1 to 0 [1:1] read-only Disable DW_apb_i2c is deemed to have been disabled when there is master activity, or when the I2C bus is idle. 0 Enable DW_apb_i2c is deemed to have forced a NACK during any part of an I2C transfer 1 SLV_RX_DATA_LOST Slave Received Data Lost [2:2] read-only Disable DW_apb_i2c is deemed to have been actively engaged in an aborted I2C transfer (with matching address) and the data phase of the I2C transfer has been entered, even though a data byte has been responded with a NACK 0 Enable DW_apb_i2c is deemed to have been disabled without being actively involved in the data phase of a Slave-Receiver transfer 1 RESERVED1 reserved1 [31:3] read-only IC_FS_SPKLEN I2C SS and FS Spike Suppression Limit Register IC_UFM_SPKLEN 0xA0 32 read-write 0x00000006 0x000000FF IC_FS_SPKLEN This register sets the duration, measured in ic_clk cycles, of the longest spike in the SCL or SDA lines that are filtered out by the spike suppression logic [7:0] read-write RESERVED1 reserved1 [31:8] read-only IC_HS_SPKLEN I2C HS Spike Suppression Limit Register 0xA4 32 read-write 0x00000002 0x000000FF IC_HS_SPKLEN This register sets the duration, measured in ic_clk cycles, of the longest spike in the SCL or SDA lines that are filtered out by the spike suppression logic [7:0] read-write RESERVED1 reserved1 [31:8] read-only IC_CLR_RESTART_DET Clear RESTART_DET Interrupt Register 0xA8 32 read-only 0x0000 CLR_RESTART_DET Read this register to clear the RESTART_DET interrupt (bit 12) of the IC_RAW_INTR_STAT registe [0:0] read-only RESERVED1 reserved1 [31:1] read-only IC_COMP_PARAM_1 I2C HS Spike Suppression Limit Register 0xF4 32 read-only 0x000808EC CLR_RESTART_DET Read this register to clear the RESTART_DET interrupt (bit 12) of the IC_RAW_INTR_STAT register [1:0] read-only MAX_SPEED_MODE Maximum Speed Mode [3:2] read-only HC_COUNT_VALUES Hard Code the count values [4:4] read-only INTR_IO Single Interrupt Output port [5:5] read-only HAS_DMA DMA Handshake Interface signal [6:6] read-only ADD_ENCODED_PARAMS Add Encoded Parameters [7:7] read-only RX_BUFFER_DEPTH Depth of receive buffer;the buffer is 8 bits wide;2 to 256 [15:8] read-only TX_BUFFER_DEPTH Depth of Transmit buffer;the buffer is 8 bits wide;2 to 256 [23:16] read-only RESERVED1 reserved1 [31:24] read-only IC_COMP_VERSION I2C Component Version Register 0xF8 32 read-only 0x00000000 IC_COMP_VERSION Signifies the component version [31:0] read-only IC_COMP_TYPE I2C Component Type Register 0xFC 32 read-only 0x00000000 IC_COMP_TYPE Design ware Component Type number = 0x44_57_01_40 [31:0] read-only IC_SCL_STUCK_AT_LOW_TIMEOUT I2C SCL Stuck at Low Timeout 0xAC 32 read-write 0xFFFFFFFF IC_SCL_STUCK_LOW_TIMEOUT Generates the interrupt to indicate SCL stuck at low if it detects the SCL stuck at low for the IC_SCL_STUCK_LOW_TIMEOUT in units of ic_clk period [31:0] read-write IC_SDA_STUCK_AT_LOW_TIMEOUT I2C SDA Stuck at Low Timeout 0xB0 32 read-write 0xFFFFFFFF IC_SDA_STUCK_LOW_TIMEOUT Initiates the recovery of SDA line , if it detects the SDA stuck at low for the IC_SDA_STUCK_LOW_TIMEOUT in units of ic_clk period. [31:0] read-write IC_CLR_SCL_STUCK_DET Clear SCL Stuck at Low Detect Interrupt Register 0xB4 32 read-only 0x0 CLR_SCL_STUCK Read this register to clear the SCL_STUCK_DET interrupt [0:0] read-only RESERVED1 reserved1 [31:1] read-only IC_DEVICE_ID I2C Device ID 0xB8 32 read-only 0x00000001 DEVICE_ID Contains the Device-ID of the component assigned through the configuration parameter [0:0] read-only RESERVED1 reserved1 [31:1] read-only IC_SMBUS_CLOCK_LOW_SEXT SMBUS Slave Clock Extend Timeout Register 0xBC 32 read-write 0xFFFFFFFF 0xFFFFFFFF SMBUS_CLK_LOW_SEXT_TIMEOUT The values in this register are in units of ic_clk period. [31:0] read-write IC_SMBUS_CLOCK_LOW_MEXT SMBUS Master extend clock Timeout Register 0xC0 32 read-write 0xFFFFFFFF 0xFFFFFFFF SMBUS_CLK_LOW_MEXT_TIMEOUT The values in this register are in units of ic_clk period.. [31:0] read-write IC_SMBUS_THIGH_MAX_IDLE_COUNT SMBus Thigh MAX Bus-Idle count Register 0xC4 32 read-write 0XFFFF 0xFFFF SMBUS_THIGH_MAX_BUS_IDLE_CNT The values in this register are in units of ic_clk period. [15:0] read-write RESERVED1 Reserved1 [31:16] read-write IC_SMBUS_INTR_STAT SMBUS Interrupt Status Register 0xC8 32 read-write 0x00 0x00 RESERVED1 Reserved1 [31:0] read-write IC_SMBUS_INTR_MASK Interrupt Mask Register 0xCC 32 read-write 0x00 0x00 RESERVED1 Reserved1 [31:0] read-write IC_SMBUS_INTR_RAW_STATUS SMBUS Raw Interrupt Status Register 0xD0 32 read-write 0x00 0x00 RESERVED1 Reserved1. [31:0] read-write IC_CLR_SMBUS_INTR Clear SMBUS Interrupt Register 0xD4 32 read-write 0x00 0x00 RESERVED1 RESERVED1 [31:0] read-write IC_OPTIONAL_SAR Optional Slave Address Register 0xD8 32 read-write 0x00 0x00 RESERVED1 Reserved1. [31:0] read-write IC_SMBUS_UDID_LSB SMBUS ARP UDID LSB Register 0xDC 32 read-write 0xFFFFFFFF 0xFFFFFFFF IC_SMBUS_ARP_UDID_LSB This field is used to store the LSB 32 bit value of slave unique device identifier used in Address Resolution Protocol. [31:0] read-write ULP_I2C 1.0 Inter Integrated Circuit(I2C) is programmable control bus that provides support for the communications link between integrated circuits in a system I2C 0x24040000 32 read-write 0 0x100 registers I2C2 13 IC_CON This register can be written only when the i2c is disabled, which corresponds to IC_ENABLE[0] being set to 0. Writes at other times have no effect. 0x00 32 read-write 0x007F 0xFFFF MASTER_MODE This bit controls whether the I2C master is enabled. [0:0] read-write Disable master disabled 0 Enable master enabled 1 SPEED These bits control at which speed the I2C operates. Hardware protects against illegal values being programmed by software. [2:1] read-write Standard_Mode standard mode (0 to 100 kbit/s) 1 Fast_Mode fast mode (less than or equal 400 kbit/s) 2 High_Speed_Mode high speed mode (less than or equal 3.4 Mbit/s) 3 IC_10BITADDR_SLAVE When acting as a slave, this bit controls whether the I2C responds to 7- or 10-bit addresses. [3:3] read-write Disable 7-bit addressing. The DW_apb_i2c ignores transactions that involve 10-bit addressing; for 7-bit addressing, only the lower 7 bits of the IC_SAR register are compared 0 Enable 10-bit addressing. The DW_apb_i2c responds to only 10-bit addressing transfers that match the full 10 bits of the IC_SAR register. 1 IC_10BITADDR_MASTER_RD_ONLY the function of this bit is handled by bit 12 of IC_TAR register, and becomes a read-only copy called IC_10BITADDR_MASTER_rd_only [4:4] read-only Disable 7-bit addressing 0 Enable 10-bit addressing 1 IC_RESTART_EN Determines whether RESTART conditions may be sent when acting as a master [5:5] read-write Disable Disabled 0 Enable Enabled 1 IC_SLAVE_DISABLE This bit controls whether I2C has its slave disabled [6:6] read-write Disable slave is enabled 0 Enable slave is disabled 1 STOP_DET_IFADDRESSED The STOP DETECTION interrupt is generated only when the transmitted address matches the slave address of SAR [7:7] read-write Disable Issues the STOP DETECTION irrespective of whether it is addressed or not. 0 Enable issues the STOP DETECTION interrupt only when it is addressed. 1 TX_EMPTY_CTRL This bit controls the generation of the TX EMPTY interrupt, as described in the IC RAW INTR STAT register. [8:8] read-write RESERVED1 reserved1 [9:9] read-only STOP_DET_IF_MASTER_ACTIVE In Master mode. [10:10] read-write Disable Issues the STOP_DET irrespective of whether the master is active. 0 Enable Issues the STOP_DET interrupt only when the master is active 1 BUS_CLEAR_FEATURE_CTRL In Master mode. [11:11] read-write Disable Bus Clear Feature is disabled 0 Enable Bus Clear Feature is enabled 1 RESERVED2 reserved2 [31:12] read-write IC_TAR I2C Target Address Register 0x04 32 read-write 0x10A0 0xFFFF IC_TAR This is the target address for any master transaction [9:0] read-write GC_OR_START If bit 11 (SPECIAL) is set to 1, then this bit indicates whether a General Call or START byte command is to be performed by the DW_apb_i2c [10:10] read-write Disable General Call Address 0 Enable START BYTE 1 SPECIAL This bit indicates whether software performs a General Call or START BYTE command [11:11] read-write Disable ignore bit 10 GC_OR_START and use IC_TAR normally 0 Enable perform special I2C command as specified in GC_OR_START bit 1 IC_10BITADDR_MASTER This bit controls whether the i2c starts its transfers in 7-or 10-bit addressing mode when acting as a master [12:12] read-write Disable 7-bit addressing 0 Enable 10-bit addressing 1 DEVICE_ID If bit 11 (SPECIAL) is set to 1, then this bit indicates whether a Device-ID of a particular slave mentioned in IC_TAR[6:0] is to be performed by the I2C Master [13:13] read-write Disable Device-ID is not performed and checks ic_tar[10] to perform either general call or START byte command. 0 Enable : Device-ID transfer is performed and bytes based on the number of read commands in the Tx-FIFO are received from the targeted slave and put in the Rx-FIFO. 1 RESERVED1 reserved1 [31:14] read-only IC_SAR I2C Slave Address Register 0x08 32 read-write 0x55 0xFFFF IC_SAR The IC_SAR holds the slave address when the I2C is operating as a slave. For 7-bit addressing, only IC_SAR[6:0] is used. [9:0] read-write RESERVED1 reserved1 [31:10] read-only IC_HS_MADDR I2C High Speed Master Mode Code Address Register 0x0C 32 read-write 0x0001 0xF IC_HS_MAR This bit field holds the value of the I2C HS mode master code [2:0] read-write RESERVED1 reserved1 [31:3] read-only IC_DATA_CMD I2C Rx/Tx Data Buffer and Command Register 0x10 32 read-write 0x0000 0xFFFF DAT This register contains the data to be transmitted or received on the I2C bus [7:0] read-write CMD This bit controls whether a read or a write is performed [8:8] write-only Disable write 0 Enable Read 1 STOP This bit controls whether a STOP is issued after the byte is sent or received [9:9] write-only Disable STOP is not issued after this byte, regardless of whether or not the Tx FIFO is empty 0 Enable STOP is issued after this byte, regardless of whether or not the Tx FIFO is empty 1 RESTART This bit controls whether a RESTART is issued before the byte is sent or received [10:10] write-only Disable If IC_RESTART_EN is 1, a RESTART is issued only if the transfer direction is changing from the previous command 0 Enable If IC_RESTART_EN is 1, a RESTART is issued before the data is sent/received 1 FIRST_DATA_BYTE Indicates the first data byte received after the address phase for receive transfer in Master receiver or Slave receiver mode [11:11] read-only Disable If IC_RESTART_EN is 1, a RESTART is issued only if the transfer direction is changing from the previous command 0 Enable If IC_RESTART_EN is 1, a RESTART is issued before the data is sent/received 1 RESERVED1 reserved1 [31:12] read-only IC_SS_SCL_HCNT Standard Speed I2C Clock SCL High Count Register 0x14 32 read-write 0x01F4 0xFFFF IC_SS_SCL_HCNT This register must be set before any I2C bus transaction can take place to ensure proper I/O timing [15:0] read-write RESERVED1 reserved1 [31:16] read-only IC_SS_SCL_LCNT Standard Speed I2C Clock SCL Low Count Register 0x18 32 read-write 0x024C 0xFFFF IC_SS_SCL_LCNT This register must be set before any I2C bus transaction can take place to ensure proper I/O timing [15:0] read-write RESERVED1 reserved1 [31:16] read-only IC_FS_SCL_HCNT Fast Speed I2C Clock SCL High Count Register 0x1C 32 read-write 0x004b 0xFFFF IC_FS_SCL_HCNT This register must be set before any I2C bus transaction can take place to ensure proper I/O timing [15:0] read-write RESERVED1 reserved1 [31:16] read-only IC_FS_SCL_LCNT Fast Speed I2C Clock SCL Low Count Register 0x20 32 read-write 0x00a3 0xFFFF IC_FS_SCL_LCNT This register must be set before any I2C bus transaction can take place to ensure proper I/O timing [15:0] read-write RESERVED1 reserved1 [31:16] read-only IC_HS_SCL_HCNT High Speed I2C Clock SCL High Count Register 0x24 32 read-write 0x000f 0xFFFF IC_HS_SCL_HCNT This register must be set before any I2C bus transaction can take place to ensure proper I/O timing [15:0] read-write RESERVED1 reserved1 [31:16] read-only IC_HS_SCL_LCNT High Speed I2C Clock SCL Low Count Register 0x28 32 read-write 0x0028 0xFFFF IC_HS_SCL_LCNT This register must be set before any I2C bus transaction can take place to ensure proper I/O timing [15:0] read-write RESERVED1 reserved1 [31:16] read-only IC_INTR_STAT I2C Interrupt Status Register 0x2C 32 read-only 0x0000 0xFFFF R_RX_UNDER Set if the processor attempts to read the receive buffer when it is empty by reading from the IC_DATA_CMD register [0:0] read-only R_RX_OVER Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and an additional byte is received from an external I2C device [1:1] read-only R_RX_FULL Set when the receive buffer reaches or goes above the RX_TL threshold in the IC_RX_TL register. [2:2] read-only R_TX_OVER Set during transmit if the transmit buffer is filled to IC_TX_BUFFER_DEPTH and the processor attempts to issue another I2C command by writing to the IC_DATA_CMD register. [3:3] read-only R_TX_EMPTY This bit is set to 1 when the transmit buffer is at or below the threshold value set in the IC_TX_TL register. [4:4] read-only R_RD_REQ This bit is set to 1 when DW_apb_i2c is acting as a slave and another I2C master is attempting to read data from DW_apb_i2c. [5:5] read-only R_TX_ABRT This bit indicates if DW_apb_i2c, as an I2C transmitter, is unable to complete the intended actions on the contents of the transmit FIFO [6:6] read-only R_RX_DONE When the DW_apb_i2c is acting as a slave-transmitter, this bit is set to 1 if the master does not acknowledge a transmitted byte [7:7] read-only R_ACTIVITY This bit captures DW_apb_i2c activity and stays set until it is cleared [8:8] read-only R_STOP_DET Indicates whether a STOP condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode. [9:9] read-only R_START_DET Indicates whether a START or RESTART condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode. [10:10] read-only R_GEN_CALL Set only when a General Call address is received and it is acknowledged [11:11] read-only R_RESTART_DET Indicates whether a RESTART condition has occurred on the I2C interface when DW_apb_i2c is operating in slave mode and the slave is the addressed slave [12:12] read-only R_MST_ON_HOLD Indicates whether a master is holding the bus and the Tx FIFO is empty. [13:13] read-only M_SCL_STUCK_AT_LOW Indicates whether the SCL Line is stuck at low for the IC_SCL_STUCK_LOW_TIMOUT number of ic_clk periods [14:14] read-only RESERVED1 reserved1 [31:15] read-only IC_INTR_MASK I2C Interrupt Mask Register 0x30 32 read-write 0x08FF 0xFFFF M_RX_UNDER This bit mask their corresponding interrupt status bits in the IC_INTR_STAT register. [0:0] read-write M_RX_OVER This bit mask their corresponding interrupt status bits in the IC_INTR_STAT register. [1:1] read-write M_RX_FULL This bit mask their corresponding interrupt status bits in the IC_INTR_STAT register. [2:2] read-write M_TX_OVER This bit mask their corresponding interrupt status bits in the IC_INTR_STAT register [3:3] read-write M_TX_EMPTY This bit mask their corresponding interrupt status bits in the IC_INTR_STAT register. [4:4] read-write M_RD_REQ This bit mask their corresponding interrupt status bits in the IC_INTR_STAT register. [5:5] read-write M_TX_ABRT This bit mask their corresponding interrupt status bits in the IC_INTR_STAT register. [6:6] read-write M_RX_DONE This bit mask their corresponding interrupt status bits in the IC_INTR_STAT register. [7:7] read-write M_ACTIVITY This bit mask their corresponding interrupt status bits in the IC_INTR_STAT register. [8:8] read-write M_STOP_DET This bit mask their corresponding interrupt status bits in the IC_INTR_STAT register. [9:9] read-write M_START_DET This bit mask their corresponding interrupt status bits in the IC_INTR_STAT register. [10:10] read-write M_GEN_CALL This bit mask their corresponding interrupt status bits in the IC_INTR_STAT register. [11:11] read-write M_RESTART_DET Indicates whether a RESTART condition has occurred on the I2C interface when DW_apb_i2c is operating in slave mode and the slave is the addressed slave [12:12] read-write M_MST_ON_HOLD Indicates whether a master is holding the bus and the Tx FIFO is empty. [13:13] read-write M_SCL_STUCK_AT_LOW Indicates whether the SCL Line is stuck at low for the IC_SCL_STUCK_LOW_TIMOUT number of ic_clk periods [14:14] read-write RESERVED1 reserved1 [31:15] read-only IC_RAW_INTR_STAT I2C Raw Interrupt Status Register 0x34 32 read-only 0x0000 0xFFFF RX_UNDER Set if the processor attempts to read the receive buffer when it is empty by reading from the IC_DATA_CMD register [0:0] read-only RX_OVER Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and an additional byte is received from an external I2C device [1:1] read-only RX_FULL Set when the receive buffer reaches or goes above the RX_TL threshold in the IC_RX_TL register. [2:2] read-only TX_OVER Set during transmit if the transmit buffer is filled to IC_TX_BUFFER_DEPTH and the processor attempts to issue another I2C command by writing to the IC_DATA_CMD register. [3:3] read-only TX_EMPTY This bit is set to 1 when the transmit buffer is at or below the threshold value set in the IC_TX_TL register. [4:4] read-only RD_REQ This bit is set to 1 when DW_apb_i2c is acting as a slave and another I2C master is attempting to read data from DW_apb_i2c. [5:5] read-only TX_ABRT This bit indicates if DW_apb_i2c, as an I2C transmitter, is unable to complete the intended actions on the contents of the transmit FIFO [6:6] read-only RX_DONE When the DW_apb_i2c is acting as a slave-transmitter, this bit is set to 1 if the master does not acknowledge a transmitted byte [7:7] read-only ACTIVITY This bit captures DW_apb_i2c activity and stays set until it is cleared [8:8] read-only STOP_DET Indicates whether a STOP condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode. [9:9] read-only START_DET Indicates whether a START or RESTART condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode. [10:10] read-only GEN_CALL Set only when a General Call address is received and it is acknowledged [11:11] read-only RESTART_DET Indicates whether a RESTART condition has occurred on the I2C interface when DW_apb_i2c is operating in slave mode and the slave is the addressed slave [12:12] read-only MST_ON_HOLD Indicates whether a master is holding the bus and the Tx FIFO is empty. [13:13] read-only SCL_STUCK_AT_LOW Indicates whether the SCL Line is stuck at low for the IC_SCL_STUCK_LOW_TIMOUT number of ic_clk periods [14:14] read-only RESERVED1 reserved1 [31:15] read-only IC_RX_TL I2C Receive FIFO Threshold Register 0x38 32 read-write 0x0008 0xFF RX_TL Receive FIFO Threshold Level [7:0] read-write RESERVED1 reserved1 [31:8] read-only IC_TX_TL I2C Transmit FIFO Threshold Register 0x3C 32 read-write 0x0008 0xFF TX_TL Transmit FIFO Threshold Level [7:0] read-write RESERVED1 reserved1 [31:8] read-only IC_CLR_INTR Clear Combined and Individual Interrupt Register 0x40 32 read-only 0x0000 0x01 CLR_INTR Read this register to clear the combined interrupt, all individual interrupts, and the IC_TXABRT_SOURCE register [0:0] read-only RESERVED1 reserved1 [31:1] read-only IC_CLR_RX_UNDER Clear RX_UNDER Interrupt Register 0x44 32 read-only 0x00000000 0x01 CLR_RX_UNDER Read this register to clear the RX_UNDER interrupt (bit 0) of the IC_RAW_INTR_STAT register. [0:0] read-only RESERVED1 reserved1 [31:1] read-only IC_CLR_RX_OVER Clear RX_OVER Interrupt Register 0x48 32 read-only 0x0000 0x01 CLR_RX_OVER Read this register to clear the RX_OVER interrupt (bit 1) of the IC_RAW_INTR_STAT register [0:0] read-only RESERVED1 reserved1 [31:1] read-only IC_CLR_TX_OVER Clear TX_OVER Interrupt Register 0x4C 32 read-only 0x00000000 0x01 CLR_TX_OVER Read this register to clear the TX_OVER interrupt (bit 3) of the IC_RAW_INTR_STAT register. [0:0] read-only RESERVED1 reserved1 [31:1] read-only IC_CLR_RD_REQ Clear RD_REQ Interrupt Register 0x50 32 read-only 0x0000 0x01 CLR_RD_REQ Read this register to clear the RD_REQ interrupt (bit 5) of the IC_RAW_INTR_STAT register. [0:0] read-only RESERVED1 reserved1 [31:1] read-only IC_CLR_TX_ABRT Clear TX_ABRT Interrupt Register 0x54 32 read-only 0x0000 0x01 CLR_TX_ABRT Read this register to clear the TX_ABRT interrupt (bit 6) of the C_RAW_INTR_STAT register, and the IC_TX_ABRT_SOURCE register [0:0] read-only RESERVED1 reserved1 [31:1] read-only IC_CLR_RX_DONE Clear RX_DONE Interrupt Register 0x58 32 read-only 0x0000 0x01 CLR_RX_DONE Read this register to clear the RX_DONE interrupt (bit 7) of the IC_RAW_INTR_STAT register [0:0] read-only RESERVED1 reserved1 [31:1] read-only IC_CLR_ACTIVITY Clear ACTIVITY Interrupt Register 0x5C 32 read-only 0x0000 0x01 CLR_ACTIVITY Reading this register clears the ACTIVITY interrupt if the I2C is not active any more [0:0] read-only RESERVED1 reserved1 [31:1] read-only IC_CLR_STOP_DET Clear STOP_DET Interrupt Register 0x60 32 read-only 0x0000 0x01 CLR_STOP_DET Read this register to clear the STOP_DET interrupt (bit 9) of the IC_RAW_INTR_STAT register. [0:0] read-only RESERVED1 reserved1 [31:1] read-only IC_CLR_START_DET Clear START_DET Interrupt Register 0x64 32 read-only 0x0000 0x01 CLR_START_DET Read this register to clear the START_DET interrupt (bit 10) of the IC_RAW_INTR_STAT register [0:0] read-only RESERVED1 reserved1 [31:1] read-only IC_CLR_GEN_CALL Clear GEN_CALL Interrupt Register 0x68 32 read-only 0x0000 0x01 CLR_GEN_CALL Read this register to clear the GEN_CALL interrupt (bit 11) of IC_RAW_INTR_STAT register [0:0] read-only RESERVED1 reserved1 [31:1] read-only IC_ENABLE Clear GEN_CALL Interrupt Register 0x6C 32 read-write 0x0000 0x01 EN Controls whether the DW_apb_i2c is enabled [0:0] read-write Disable Disables DW_apb_i2c (TX and RX FIFOs are held in an erased state) 0 Enable Enables DW_apb_i2c 1 ABORT When set, the controller initiates the transfer abort [1:1] read-write Disable ABORT not initiated or ABORT done 0 Enable ABORT operation in progress 1 TX_CMD_BLOCK none [2:2] read-write Disable The transmission of data starts on I2C bus automatically, as soon as the first data is available in the Tx FIFO 0 Enable Blocks the transmission of data on I2C bus even if Tx FIFO has data to transmit 1 SDA_STUCK_RECOVERY_ENABLE SDA STUCK RECOVERY ENABLE [3:3] read-write RESERVED1 reserved1 [31:4] read-only IC_STATUS I2C Status Register 0x70 32 read-only 0x00000006 0x0F ACTIVITY I2C Activity Status [0:0] read-only TFNF Transmit FIFO Not Full [1:1] read-only Disable Transmit FIFO is full 0 Enable Transmit FIFO is not full 1 TFE Transmit FIFO Completely Empty [2:2] read-only Disable Transmit FIFO is not empty 0 Enable Transmit FIFO is empty 1 RFNE Receive FIFO Not Empty [3:3] read-only Disable Receive FIFO is not empty 0 Enable Receive FIFO is not empty 1 RFF Receive FIFO Completely Full [4:4] read-only Disable Receive FIFO is not full 0 Enable Receive FIFO is full 1 MST_ACTIVITY Master FSM Activity Status [5:5] read-only Disable Master FSM is in IDLE state so the Master part of DW_apb_i2c is not Active 0 Enable Master FSM is not in IDLE state so the Master part of DW_apb_i2c is Active 1 SLV_ACTIVITY Slave FSM Activity Status [6:6] read-only Disable Slave FSM is in IDLE state so the Slave part of DW_apb_i2c is not Active 0 Enable Slave FSM is not in IDLE state so the Slave part of DW_apb_i2c is Active 1 MST_HOLD_TX_FIFO_EMPTY The I2C master stalls the write transfer when Tx FIFO is empty, and the the last byte does not have the Stop bit set. [7:7] read-only MST_HOLD_RX_FIFO_FULL This bit indicates the BUS Hold in Master mode due to Rx FIFO is Full and additional byte has been received. [8:8] read-only SLV_HOLD_TX_FIFO_EMPTY This bit indicates the BUS Hold in Slave mode for the Read request when the Tx FIFO is empty. [9:9] read-only SLV_HOLD_RX_FIFO_FULL This bit indicates the BUS Hold in Slave mode due to the Rx FIFO being Full and an additional byte being received. [10:10] read-only SDA_STUCK_NOT_RECOVERED This bit indicates that an SDA stuck at low is not recovered after the recovery mechanism. [11:11] read-only RESERVED1 reserved1 [31:12] read-only IC_TXFLR I2C Transmit FIFO Level Register 0x74 32 read-only 0x0000 0xF TXFLR Contains the number of valid data entries in the transmit FIFO. [3:0] read-only RESERVED1 reserved1 [31:4] read-only IC_RXFLR I2C Receive FIFO Level Register 0x78 32 read-only 0x0000 0xF RXFLR Receive FIFO Level. Contains the number of valid data entries in the receive FIFO [3:0] read-only RESERVED1 reserved1 [31:4] read-only IC_SDA_HOLD I2C SDA Hold Time Length Register 0x7C 32 read-write 0x0001 0xF IC_SDA_TX_HOLD Sets the required SDA hold time in units of ic_clk period,when I2C acts as a transmitter. [15:0] read-write IC_SDA_RX_HOLD Sets the required SDA hold time in units of ic_clk period,when I2C acts as a receiver. [23:16] read-write RESERVED1 reserved1 [31:24] read-only IC_TX_ABRT_SOURCE I2C Transmit Abort Source Register 0x80 32 read-only 0x00000000 0xFFFF ABRT_7B_ADDR_NOACK 1: Master is in 7-bit addressing mode and the address sent was not acknowledged by any slave [0:0] read-only ABRT_10ADDR1_NOACK 1: Master is in 10-bit address mode and the first 10-bit address byte was not acknowledged by any slave [1:1] read-only ABRT_10ADDR2_NOACK 1: Master is in 10-bit address mode and the second address byte of the 10-bit address was not acknowledged by any slave [2:2] read-only ABRT_TXDATA_NOACK 1: This is a master-mode only bit. Master has received an acknowledgement for the address, but when it sent data byte(s) following the address, it did not receive an acknowledge from the remote slave(s) [3:3] read-only ABRT_GCALL_NOACK 1: DW_apb_i2c in master mode sent a General Call and no slave on the bus acknowledged the General Call [4:4] read-only ABRT_GCALL_READ 1: DW_apb_i2c in master mode sent a General Call but the user programmed the byte following the General Call to be a read from the bus (IC_DATA_CMD[9] is set to 1) [5:5] read-only ABRT_HS_ACKDET 1: Master is in High Speed mode and the High Speed Master code was acknowledged [6:6] read-only ABRT_SBYTE_ACKDET 1: Master has sent a START Byte and the START Byte was acknowledged (wrong behavior) [7:7] read-only ABRT_HS_NORSTRT 1: The restart is disabled (IC_RESTART_EN bit (IC_CON[5]) = 0) and the user is trying to use the master to transfer data in High Speed mode [8:8] read-only ABRT_SBYTE_NORSTRT 1: The restart is disabled (IC_RESTART_EN bit (IC_CON[5]) = 0) and the user is trying to send a START Byte [9:9] read-only ABRT_10B_RD_NORSTRT 1: The restart is disabled (IC_RESTART_EN bit (IC_CON[5]) = 0) and the master sends a read command in 10-bit addressing mode [10:10] read-only ABRT_MASTER_DIS 1: User tries to initiate a Master operation with the Master mode disabled [11:11] read-only ARB_LOST 1: Master has lost arbitration, or if IC_TX_ABRT_SOURCE[14] is also set, then the slave transmitter has lost arbitration [12:12] read-only ABRT_SLVFLUSH_TXFIFO 1: Slave has received a read command and some data exists in the TX FIFO so the slave issues a TX_ABRT interrupt to flush old data in TX FIFO [13:13] read-only ABRT_SLV_ARBLOST 1: Slave lost the bus while transmitting data to a remote master. IC_TX_ABRT_SOURCE[12] is set at the same time [14:14] read-only ABRT_SLVRD_INTX 1: When the processor side responds to a slave mode request for data to be transmitted to a remote master and user writes a 1 in CMD (bit 8) of IC_DATA_CMD register [15:15] read-only ABRT_USER_ABRT This is a master-mode-only bit. Master has detected the transfer abort (IC_ENABLE[1]). [16:16] read-only ABRT_SDA_STUCK_AT_LOW Master detects the SDA is Stuck at low for the IC_SDA_STUCK_AT_LOW_TIMEOUT value of ic_clks [17:17] read-only ABRT_DEVICE_NOACK Master initiates the DEVICE_ID transfer and the device ID sent is not acknowledged by any slave [18:18] read-only ABRT_DEVICE_SLVADDR_NOACK Master is initiating the DEVICE_ID transfer and the slave address sent was not acknowledged by any slave [19:19] read-only ABRT_DEVICE_WRITE Master is initiating the DEVICE_ID transfer and the Tx- FIFO consists of write commands. [20:20] read-only RESERVED1 reserved1 [22:21] read-only TX_FLUSH_CNT This field indicates the number of Tx FIFO data commands that are flushed due to TX_ABRT interrupt [31:23] read-only IC_SLV_DATA_NACK_ONLY Generate Slave Data NACK Register 0x84 32 read-write 0x00000000 0xFFFF NACK Generate NACK. This NACK generation only occurs when DW_apb_i2c is a slave receiver. [0:0] read-write RESERVED1 reserved1 [31:1] read-only IC_DMA_CR DMA Control Register 0x88 32 read-write 0x00000000 0xF RDMAE Receive DMA Enable [0:0] read-write Disable Receive DMA disabled 0 Enable Receive DMA enabled 1 TDMAE Transmit DMA Enable.This bit enables/disables the transmit FIFO DMA channel [1:1] read-write Disable Transmit DMA disabled 0 Enable Transmit DMA enabled 1 RESERVED1 reserved1 [31:2] read-only IC_DMA_TDLR DMA Transmit Data Level Register 0x8C 32 read-write 0x00000000 0xF DMATDL This bit field controls the level at which a DMA request is made by the transmit logic [3:0] read-write RESERVED1 reserved1 [31:4] read-only IC_DMA_RDLR I2C Receive Data Level Register 0x90 32 read-write 0x00000000 0x7 DMARDL This bit field controls the level at which a DMA request is made by the receive logic [3:0] read-write RESERVED1 reserved1 [31:4] read-only IC_SDA_SETUP I2C SDA Setup Register 0x94 32 read-write 0x00000000 0xFFFF SDA_SETUP This register controls the amount of time delay (in terms of number of ic_clk clock periods) [7:0] read-write RESERVED1 reserved1 [31:8] read-only IC_ACK_GENERAL_CALL I2C ACK General Call Register 0x98 32 read-write 0x00000001 0xF ACK_GEN_CALL ACK General Call [0:0] read-write Disable DW_apb_i2c does not generate General Call interrupts 0 Enable DW_apb_i2c responds with a ACK (by asserting ic_data_oe) when it receives a General Call. 1 RESERVED1 reserved1 [31:1] read-only IC_ENABLE_STATUS I2C Enable Status Register 0x9C 32 read-only 0x00000000 0xF IC_EN This bit always reflects the value driven on the output port ic_en. [0:0] read-only Disable DW_apb_i2c is deemed completely inactive 0 Enable DW_apb_i2c is deemed to be in an enabled state 1 SLV_DISABLED_WHILE_BUSY This bit indicates if a potential or active Slave operation has been aborted due to the setting of the IC_ENABLE register from 1 to 0 [1:1] read-only Disable DW_apb_i2c is deemed to have been disabled when there is master activity, or when the I2C bus is idle. 0 Enable DW_apb_i2c is deemed to have forced a NACK during any part of an I2C transfer 1 SLV_RX_DATA_LOST Slave Received Data Lost [2:2] read-only Disable DW_apb_i2c is deemed to have been actively engaged in an aborted I2C transfer (with matching address) and the data phase of the I2C transfer has been entered, even though a data byte has been responded with a NACK 0 Enable DW_apb_i2c is deemed to have been disabled without being actively involved in the data phase of a Slave-Receiver transfer 1 RESERVED1 reserved1 [31:3] read-only IC_FS_SPKLEN I2C SS and FS Spike Suppression Limit Register IC_UFM_SPKLEN 0xA0 32 read-write 0x00000006 0x000000FF IC_FS_SPKLEN This register sets the duration, measured in ic_clk cycles, of the longest spike in the SCL or SDA lines that are filtered out by the spike suppression logic [7:0] read-write RESERVED1 reserved1 [31:8] read-only IC_HS_SPKLEN I2C HS Spike Suppression Limit Register 0xA4 32 read-write 0x00000002 0x000000FF IC_HS_SPKLEN This register sets the duration, measured in ic_clk cycles, of the longest spike in the SCL or SDA lines that are filtered out by the spike suppression logic [7:0] read-write RESERVED1 reserved1 [31:8] read-only IC_CLR_RESTART_DET Clear RESTART_DET Interrupt Register 0xA8 32 read-only 0x0000 CLR_RESTART_DET Read this register to clear the RESTART_DET interrupt (bit 12) of the IC_RAW_INTR_STAT registe [0:0] read-only RESERVED1 reserved1 [31:1] read-only IC_COMP_PARAM_1 I2C HS Spike Suppression Limit Register 0xF4 32 read-only 0x000808EC CLR_RESTART_DET Read this register to clear the RESTART_DET interrupt (bit 12) of the IC_RAW_INTR_STAT register [1:0] read-only MAX_SPEED_MODE Maximum Speed Mode [3:2] read-only HC_COUNT_VALUES Hard Code the count values [4:4] read-only INTR_IO Single Interrupt Output port [5:5] read-only HAS_DMA DMA Handshake Interface signal [6:6] read-only ADD_ENCODED_PARAMS Add Encoded Parameters [7:7] read-only RX_BUFFER_DEPTH Depth of receive buffer;the buffer is 8 bits wide;2 to 256 [15:8] read-only TX_BUFFER_DEPTH Depth of Transmit buffer;the buffer is 8 bits wide;2 to 256 [23:16] read-only RESERVED1 reserved1 [31:24] read-only IC_COMP_VERSION I2C Component Version Register 0xF8 32 read-only 0x00000000 IC_COMP_VERSION Signifies the component version [31:0] read-only IC_COMP_TYPE I2C Component Type Register 0xFC 32 read-only 0x00000000 IC_COMP_TYPE Design ware Component Type number = 0x44_57_01_40 [31:0] read-only IC_SCL_STUCK_AT_LOW_TIMEOUT I2C SCL Stuck at Low Timeout 0xAC 32 read-write 0xFFFFFFFF IC_SCL_STUCK_LOW_TIMEOUT Generates the interrupt to indicate SCL stuck at low if it detects the SCL stuck at low for the IC_SCL_STUCK_LOW_TIMEOUT in units of ic_clk period [31:0] read-write IC_SDA_STUCK_AT_LOW_TIMEOUT I2C SDA Stuck at Low Timeout 0xB0 32 read-write 0xFFFFFFFF IC_SDA_STUCK_LOW_TIMEOUT Initiates the recovery of SDA line , if it detects the SDA stuck at low for the IC_SDA_STUCK_LOW_TIMEOUT in units of ic_clk period. [31:0] read-write IC_CLR_SCL_STUCK_DET Clear SCL Stuck at Low Detect Interrupt Register 0xB4 32 read-only 0x0 CLR_SCL_STUCK Read this register to clear the SCL_STUCK_DET interrupt [0:0] read-only RESERVED1 reserved1 [31:1] read-only IC_DEVICE_ID I2C Device ID 0xB8 32 read-only 0x00000001 DEVICE_ID Contains the Device-ID of the component assigned through the configuration parameter [0:0] read-only RESERVED1 reserved1 [31:1] read-only IC_SMBUS_CLOCK_LOW_SEXT SMBUS Slave Clock Extend Timeout Register 0xBC 32 read-write 0xFFFFFFFF 0xFFFFFFFF SMBUS_CLK_LOW_SEXT_TIMEOUT The values in this register are in units of ic_clk period. [31:0] read-write IC_SMBUS_CLOCK_LOW_MEXT SMBUS Master extend clock Timeout Register 0xC0 32 read-write 0xFFFFFFFF 0xFFFFFFFF SMBUS_CLK_LOW_MEXT_TIMEOUT The values in this register are in units of ic_clk period.. [31:0] read-write IC_SMBUS_THIGH_MAX_IDLE_COUNT SMBus Thigh MAX Bus-Idle count Register 0xC4 32 read-write 0XFFFF 0xFFFF SMBUS_THIGH_MAX_BUS_IDLE_CNT The values in this register are in units of ic_clk period. [15:0] read-write RESERVED1 Reserved1 [31:16] read-write IC_SMBUS_INTR_STAT SMBUS Interrupt Status Register 0xC8 32 read-write 0x00 0x00 RESERVED1 Reserved1 [31:0] read-write IC_SMBUS_INTR_MASK Interrupt Mask Register 0xCC 32 read-write 0x00 0x00 RESERVED1 Reserved1 [31:0] read-write IC_SMBUS_INTR_RAW_STATUS SMBUS Raw Interrupt Status Register 0xD0 32 read-write 0x00 0x00 RESERVED1 Reserved1. [31:0] read-write IC_CLR_SMBUS_INTR Clear SMBUS Interrupt Register 0xD4 32 read-write 0x00 0x00 RESERVED1 RESERVED1 [31:0] read-write IC_OPTIONAL_SAR Optional Slave Address Register 0xD8 32 read-write 0x00 0x00 RESERVED1 Reserved1. [31:0] read-write IC_SMBUS_UDID_LSB SMBUS ARP UDID LSB Register 0xDC 32 read-write 0xFFFFFFFF 0xFFFFFFFF IC_SMBUS_ARP_UDID_LSB This field is used to store the LSB 32 bit value of slave unique device identifier used in Address Resolution Protocol. [31:0] read-write MCPWM 1.0 The Motor Control PWM (MCPWM) controller is used to generate a periodic pulse waveform, which is useful in motor control and power control applications MCPWM 0x47070000 32 read-write 0x00 0x14C registers MCPWM 48 PWM_INTR_STS PWM Interrupt Status Register 0x00 32 read-only 0x00000000 RISE_PWM_TIME_PERIOD_MATCH_INTR_CH0 This time base interrupt for 0th channel without considering postscaler [0:0] read-only PWM_TIME_PRD_MATCH_INTR_CH0 This time base interrupt for 0th channel, which considers postscaler value [1:1] read-only FLT_A_INTR When the fault A pin is driven low, this interrupt is raised. [2:2] read-only FLT_B_INTR When the fault B pin is driven low, this interrupt is raised. [3:3] read-only RISE_PWM_TIME_PERIOD_MATCH_INTR_CH1 This time base interrupt for 1st channel without considering postscaler value [4:4] read-only PWM_TIME_PRD_MATCH_INTR_CH1 This time base interrupt for 1st channel, which considers postscaler value. [5:5] read-only RISE_PWM_TIME_PERIOD_MATCH_INTR_CH2 This time base interrupt for 2nd channel without considering postscaler value. [6:6] read-only PWM_TIME_PRD_MATCH_INTR_CH2 This time base interrupt for 2nd channel, which considers postscaler value [7:7] read-only RISE_PWM_TIME_PERIOD_MATCH_INTR_CH3 This time base interrupt for 3rd channel without considering postscaler value. [8:8] read-only PWM_TIME_PRD_MATCH_INTR_CH3 This time base interrupt for 3rd channel, which considers postscaler value. [9:9] read-only RESERVED1 reserved1 [31:10] read-only PWM_INTR_UNMASK PWM Interrupt Unmask Register 0x04 32 read-write 0x00000000 0xFFFF PWM_INTR_UNMASK Interrupt Unmask [15:0] read-write RESERVED1 reserved1 [31:16] read-write PWM_INTR_MASK PWM Interrupt mask Register 0x08 32 read-write 0x00000000 0xFFFF PWM_INTR_MASK Interrupt Mask [15:0] read-write RESERVED1 reserved1 [31:16] read-write PWM_INTR_ACK PWM Interrupt Acknowledgement Register 0x0C 32 read-write 0x00000000 0xFFFF RISE_PWM_TIME_PERIOD_MATCH_CH0_ACK pwm time period match interrupt for 0th channel will be cleared. [0:0] write-only Disable No effect. 0 Enable PWM time period match interrupt for 0th channel will be cleared. 1 PWM_TIME_PRD_MATCH_INTR_CH0_ACK pwm time period match interrupt for 0th channel will be cleared [1:1] write-only Disable No effect 0 Enable pwm time period match interrupt for 0th channel will be cleared 1 FLT_A_INTR_ACK pwm fault A interrupt will be cleared. [2:2] write-only Disable No effect 0 Enable pwm faultA interrupt will be cleared 1 FLT_B_INTR_ACK pwm fault B interrupt will be cleared. [3:3] write-only Disable No effect 0 Enable pwm faultB interrupt will be cleared. 1 RISE_PWM_TIME_PERIOD_MATCH_CH1_ACK pwm time period match interrupt for 1st channel will be cleared [4:4] write-only Disable No effect 0 Enable pwm time period match interrupt for 1st channel will be cleared 1 PWM_TIME_PRD_MATCH_INTR_CH1_ACK pwm time period match interrupt for 1st channel will be cleared. [5:5] write-only Disable No effect 0 Enable pwm time period match interrupt for 1st channel will be cleared. 1 RISE_PWM_TIME_PERIOD_MATCH_CH2_ACK pwm time period match interrupt for 2nd channel will be cleared. [6:6] write-only Disable No effect 0 Enable pwm time period match interrupt for 2nd channel will be cleared 1 PWM_TIME_PRD_MATCH_INTR_CH2_ACK pwm time period match interrupt for 2nd channel will be cleared. [7:7] write-only Disable No effect 0 Enable pwm time period match interrupt for 2nd channel will be cleared. 1 RISE_PWM_TIME_PERIOD_MATCH_CH3_ACK pwm time period match interrupt for 3rd channel will be cleared. [8:8] write-only Disable No effect 0 Enable pwm time period match interrupt for 3rd channel will be cleared 1 PWM_TIME_PRD_MATCH_INTR_CH3_ACK pwm time period match interrupt for 3rd channel will be cleared. [9:9] write-only Disable No effect 0 Enable pwm time period match interrupt for 3rd channel will be cleared 1 RESERVED1 reserved1 [31:10] read-write PWM_TIME_PRD_WR_REG_CH0 Base timer period register of channel 0 0x28 32 read-write 0x00000000 0xFFFF PWM_TIME_PRD_REG_WR_VALUE_CH0 Value to update the base timer period register of channel 0 [15:0] read-write RESERVED1 reserved1 [31:16] read-write PWM_TIME_PRD_CNTR_WR_REG_CH0 Base time counter initial value register for channel 0 0x2C 32 read-write 0x00000000 0xFFFF PWM_TIME_PRD_CNTR_WR_REG_CH0 To update the base time counter initial value for channel 0 [15:0] read-write RESERVED1 reserved1 [31:16] read-write PWM_TIME_PRD_PARAM_REG_CH0 Base time period config parameter's register for channel0 0x30 32 read-write 0x00000000 0xFFFF TMR_OPEARATING_MODE_CH0 Base timer operating mode for channel0 [2:0] read-write FREE_RUNNING_MODE free running mode 0 SINGLE_EVENT_MODE single event mode 1 DOWN_COUNT_MODE down count mode 2 NONE1 none1 3 UP_DOWN_MODE up/down mode 4 UP_DOWN_DOUBLER_MODE up/down mode with interrupts for double PWM updates 5 NONE2 none2 6 NONE3 none3 7 RESERVED1 reserved1 [3:3] read-write PWM_TIME_PRD_PRE_SCALAR_VALUE_CH0 Base timer input clock pre scale select value for channel0. [6:4] read-write 1X_CLOCK_PERIOD 1x input clock period 0 2X_CLOCK_PERIOD 2x input clock period 1 4X_CLOCK_PERIOD 4x input clock period 2 16X_CLOCK_PERIOD 16x input clock period 3 32X_CLOCK_PERIOD 32x input clock period 4 NONE1 none1 5 64X_CLOCK_PERIOD 64x input clock period 6 NONE2 none2 7 RESERVED2 reserved2 [7:7] read-write PWM_TIME_PRD_POST_SCALAR_VALUE_CH0 Time base output post scale bits for channel0 [11:8] read-write [1:1]_POST_SCALE 0000 1 to 1 post scale 0 [1:2]_POST_SCALE 0001 1 to 2 1 [1:3]_POST_SCALE 0010 1 to 3 2 [1:4]_POST_SCALE 0011 1 to 4 3 [1:5]_POST_SCALE 0100 1 to 5 4 [1:6]_POST_SCALE 0101 1 to 6 5 [1:7]_POST_SCALE 0110 1 to 7 6 [1:8]_POST_SCALE 0111 1 to 8 7 [1:9]_POST_SCALE 1000 1 to 9 8 [1:10]_POST_SCALE 1001 1 to 10 9 [1:11]_POST_SCALE 1010 1 to 11 10 [1:12]_POST_SCALE 1011 [1:12] 11 [1:13]_POST_SCALE 1100 [1:13] 12 [1:14]_POST_SCALE 1101 1 to 14 13 [1:15]_POST_SCALE 1110 1 to 15 14 [1:16]_POST_SCALE 1111 1 to 16 15 RESERVED3 reserved3 [31:12] read-write PWM_TIME_PRD_CTRL_REG_CH0 Base time counter initial value register for channel 0 0x34 32 read-write 0x00000000 0x7 PWM_TIME_PRD_CNTR_RST_FRM_REG Time period counter soft reset [0:0] read-write PWM_TIME_BASE_EN_FRM_REG_CH0 Base timer enable for channnel0 [1:1] read-write Disable timer is disabled 0 Enable timer is enabled 1 PWM_SFT_RST MC PWM soft reset [2:2] read-write RESERVED1 reserved1 [31:3] read-only PWM_TIME_PRD_STS_REG_CH0 Base time period status register for channel0 0x38 32 read-only 0x00000000 0x1 PWM_TIME_PRD_DIR_STS_CH0 Time period counter direction status for channel0 [0:0] read-only Downward Time period counter direction is downward 0 Upward Time period counter direction is upward 1 RESERVED1 reserved1 [31:1] read-only PWM_TIME_PRD_CNTR_VALUE_CH0 Base Time period counter current value register for channel0 0x3C 32 read-only 0x00000000 0xFFFF PWM_TIME_PRD_CNTR_VALUE_CH0 Time period counter current value for channel0 [15:0] read-only RESERVED1 reserved1 [31:16] read-only PWM_DUTYCYCLE_CTRL_SET_REG Duty cycle Control Set Register 0x50 32 read-write 0x0000000F 0xFFFF IMDT_DUTYCYCLE_UPDATE_EN Enable to update the duty cycle immediately [3:0] read-write DUTYCYCLE_UPDATE_DISABLE Duty cycle register updation disable. There is a separate bit for each channel [7:4] read-write RESERVED1 reserved1 [31:8] read-only PWM_DUTYCYCLE_CTRL_RESET_REG Duty cycle Control Reset Register 0x54 32 read-write 0x0000000F 0xFFFF IMDT_DUTYCYCLE_UPDATE_EN Enable to update the duty cycle immediately [3:0] read-write DUTYCYCLE_UPDATE_DISABLE Duty cycle register updation disable. There is a separate bit for each channel. [7:4] read-write RESERVED1 reserved1 [31:8] read-only 4 0x4 PWM_DUTYCYCLE_REG_WR_VALUEn Duty cycle Value Register for Channel 0 to channel 3 0x58 PWM_DUTYCYCLE_REG_WR_VALUE__n_ Duty cycle Value Register for Channel 0x00 32 read-write 0x00000000 0xFFFF PWM_DUTYCYCLE_REG_WR_VALUE_CH_n_ Duty cycle value for channel0 to channel3 [15:0] read-write RESERVED1 reserved1 [31:16] read-only PWM_DEADTIME_CTRL_SET_REG Dead time Control Set Register 0x78 32 read-write 0x00000000 0xFFF DEADTIME_SELECT_ACTIVE Dead time select bits for PWM going active [3:0] read-write Disable means use counter A 0 Enable means use counter B 1 DEADTIME_SELECT_INACTIVE Dead time select bits for PWM going inactive [7:4] read-write Disable means use counter A 0 Enable means use counter B 1 DEADTIME_DISABLE_FRM_REG Dead time counter soft reset for each channel. [11:8] read-write RESERVED1 reserved1 [31:12] read-only PWM_DEADTIME_CTRL_RESET_REG Dead time Control Reset Register 0x7C 32 read-write 0x00000000 0xFFF DEADTIME_SELECT_ACTIVE Dead time select bits for PWM going active [3:0] read-write Disable means use counter A 0 Enable means use counter B 1 DEADTIME_SELECT_INACTIVE Dead time select bits for PWM going inactive [7:4] read-write Disable means use counter A 0 Enable means use counter B 1 DEADTIME_DISABLE_FRM_REG Dead time counter soft reset for each channel. [11:8] read-write RESERVED1 reserved1 [31:12] read-only PWM_DEADTIME_PRESCALE_SELECT_A Dead time Prescale Select Register for A 0x80 32 read-write 0x00000000 0xF DEADTIME_PRESCALE_SELECT_A Dead time prescale selection bits for unit A. [7:0] read-write RESERVED1 reserved1 [31:8] read-only PWM_DEADTIME_PRESCALE_SELECT_B Dead time Prescale Select Register for B 0x84 32 read-write 0x00000000 0xF DEADTIME_PRESCALE_SELECT_B Dead time prescale selection bits for unit B [7:0] read-write RESERVED1 reserved1 [31:8] read-only 4 0x08 PWM_DEADTIMEn PWM_DEADTIME_A (0-3) and PWM_DEADTIME_B (0-3) 0x88 PWM_DEADTIME_A__n_ PWM deadtime for A and channel varies from 0 to 3 0x00 32 read-write 0x00000000 0x3F DEADTIME_A_CH_n_ Dead time A value to load into dead time counter A of channel0 to channel3 [5:0] read-write RESERVED1 reserved1 [31:6] read-write PWM_DEADTIME_B__n_ PWM deadtime for B and channel varies from 0 to 3 0x04 32 read-write 0x00000000 0x3F DEADTIME_B_CH_n_ Dead time B value to load into deadtime counter B of channel0 to channel3 [5:0] read-write RESERVED1 reserved1 [31:6] read-write PWM_OP_OVERRIDE_CTRL_SET_REG output override control set register 0xC8 32 read-write 0x00000000 0x1 OP_OVERRIDE_SYNC Output override is synced with pwm time period depending on operating mode [0:0] read-write RESERVED1 reserved1 [31:1] read-only PWM_OP_OVERRIDE_CTRL_RESET_REG output override control reset register 0xCC 32 read-write 0x00000000 0xFFFF OP_OVERRIDE_SYNC Output override is synced with pwm time period depending on operating mode [0:0] read-write RESERVED1 reserved1 [31:1] read-write PWM_OP_OVERRIDE_ENABLE_SET_REG output override enable set register 0xD0 32 read-write 0x00000000 0xFF PWM_OP_OVERRIDE_ENABLE_REG Pwm output over ride enable [7:0] read-write RESERVED1 reserved1 [31:8] read-write PWM_OP_OVERRIDE_ENABLE_RESET_REG output override enable reset register 0xD4 32 read-write 0x00000000 0xFF PWM_OP_OVERRIDE_ENABLE_REG Pwm output over ride enable [7:0] read-write RESERVED1 reserved1 [31:8] read-write PWM_OP_OVERRIDE_VALUE_SET_REG output override value set register 0xD8 32 read-write 0x00000000 0xFF OP_OVERRIDE_VALUE Pwm output over ride value. [7:0] read-write RESERVED1 reserved1 [31:8] read-write PWM_OP_OVERRIDE_VALUE_RESET_REG output override enable reset register 0xDC 32 read-write 0x00000000 0xFF OP_OVERRIDE_VALUE Pwm output over ride value. [7:0] read-write RESERVED1 reserved1 [31:8] read-write PWM_FLT_OVERRIDE_CTRL_SET_REG fault override control set register 0xE0 32 read-write 0x00000000 0xFFFF FLT_A_MODE Fault A mode [0:0] read-write Disable latched mode 0 Enable cycle by cycle by mode 1 FLT_B_MODE Fault B mode [1:1] read-write Disable latched mode 0 Enable cycle by cycle by mode 1 OP_POLARITY_H Ouput polarity for high (H3, H2, H1, H0) side signals [2:2] read-write Disable means active low mode 0 Enable means active high mode 1 OP_POLARITY_L Ouput polarity for low (L3, L2, L1, L0) side signals. [3:3] read-write Disable means active low mode 0 Enable means active high mode 1 FLT_A_ENABLE Fault A enable. Separate enable bit is present for channel [7:4] read-write FLT_B_ENABLE Fault B enable. Separate enable bit is present for channel [11:8] read-write COMPLEMENTARY_MODE PWM I/O pair mode [15:12] read-write Disable PWM I/O pin pair is in the independent output mode 0 Enable PWM I/O pin pair is in the complementary output mode 1 RESERVED1 reserved1 [31:16] read-write PWM_FLT_OVERRIDE_CTRL_RESET_REG fault override control reset register 0xE4 32 read-write 0x00000000 0xFF FLT_A_MODE Fault B mode [0:0] read-write Disable latched mode 0 Enable cycle by cycle by mode 1 FLT_B_MODE Fault B mode [1:1] read-write Disable latched mode 0 Enable cycle by cycle by mode 1 OP_POLARITY_H Ouput polarity for high (H3, H2, H1, H0) side signals [2:2] read-write Disable means active low mode 0 Enable means active high mode 1 OP_POLARITY_L Ouput polarity for low (L3, L2, L1, L0) side signals. [3:3] read-write Disable means active low mode 0 Enable means active high mode 1 FLT_A_ENABLE Fault A enable. Separate enable bit is present for channel [7:4] read-write FLT_B_ENABLE Fault B enable. Separate enable bit is present for channel [11:8] read-write COMPLEMENTARY_MODE PWM I/O pair mode [15:12] read-write Disable PWM I/O pin pair is in the independent output mode 0 Enable PWM I/O pin pair is in the complementary output mode 1 RESERVED1 reserved1 [31:16] read-write PWM_FLT_A_OVERRIDE_VALUE_REG Fault input A PWM override value 0xE8 32 read-write 0x00000000 0xFF PWM_FLT_A_OVERRIDE_VALUE_reg 0 bit for L0,1-L1,2-L2,3-L3,4-L4,5-L5,6-L6,7-L7 [7:0] read-write Inactive 0 means PWM output pin is driven inactive on an external fault input A event 0 Active 1 means PWM output pin is driven active on an external fault input A event. 1 RESERVED1 reserved1 [31:8] read-write PWM_FLT_B_OVERRIDE_VALUE_REG Fault input B PWM override value 0xEC 32 read-write 0x00000000 0xFF PWM_FLT_B_OVERRIDE_VALUE_reg 0 bit for L0, 1-L1,2-L2,3-L3,4-L4,5-L5,6-L6,7-L7 [7:0] read-write Inactive 0 means PWM output pin is driven inactive on an external fault input A event 0 Active 1 means PWM output pin is driven active on an external fault input A event. 1 RESERVED1 reserved1 [31:8] read-write PWM_SVT_CTRL_SET_REG NONE 0xF0 32 read-write 0x00000000 0x3 SVT_ENABLE_FRM Special event trigger enable. This is used to enable generation special event trigger [0:0] read-write SVT_DIRECTION_FRM Special event trigger for time base direction [1:1] read-write COUNT_UP A special event trigger will occur when PWM time base is counting up 0 COUNT_DOWN A special event trigger will occur when PWM time base is counting down 1 RESERVED1 reserved1 [31:2] read-write PWM_SVT_CTRL_RESET_REG Special event control reset register 0xF4 32 read-write 0x00000000 0x3 SVT_ENABLE_FRM Special event trigger enable. This is used to enable generation special event trigger [0:0] read-write SVT_DIRECTION_FRM Special event trigger for time base direction [1:1] read-write COUNT_UP A special event trigger will occur when PWM time base is counting up 0 COUNT_DOWN A special event trigger will occur when PWM time base is counting down 1 RESERVED1 reserved1 [31:2] read-write PWM_SVT_PARAM_REG Special event parameter register 0xF8 32 read-write 0x00000000 0xF SVT_POSTSCALER_SELECT PWM special event trigger output postscale select bits [3:0] read-write RESERVED1 reserved1 [31:4] read-write PWM_SVT_COMPARE_VALUE_REG Special event compare value register 0xFC 32 read-write 0x00000000 0xFFFF PWM_SVT_COMPARE_VALUE Special event compare value. This is used to compare with pwm time period counter to generate special event trigger [15:0] read-write RESERVED1 reserved1 [31:16] read-write PWM_TIME_PRD_WR_REG_CH1 Base timer period register of channel1 0x100 32 read-write 0x00000000 0xFFFF PWM_TIME_PRD_REG_WR_VALUE_CH1 Value to update the base timer period register of channel 1 [15:0] read-write RESERVED1 reserved1 [31:16] read-write PWM_TIME_PRD_CNTR_WR_REG_CH1 Base time counter initial value register for channel1 0x104 32 read-write 0x00000000 0xFFFF PWM_TIME_PRD_CNTR_WR_REG_CH1 To update the base time counter initial value for channel 1 [15:0] read-write RESERVED1 reserved1 [31:16] read-write PWM_TIME_PRD_PARAM_REG_CH1 NONE 0x108 32 read-write 0x00000000 0xFF TMR_OPEARATING_MODE_CH1 Base timer operating mode for channel1 [2:0] read-write FREE_RUNNING_MODE free running mode 0 SINGLE_EVENT_MODE single event mode 1 DOWN_COUNT_MODE down count mode 2 NONE1 none1 3 UP_DOWN_MODE up/down mode 4 UP_DOWN_DOUBLER_MODE up/dowm mode with interrupts for double PWM updates 5 NONE2 none2 6 NONE3 none3 7 RESERVED1 reserved1 [3:3] read-write PWM_TIME_PRD_PRE_SCALAR_VALUE_CH1 Base timer input clock prescale select value for channel1. [6:4] read-write 1x_clock_period 1x input clock period 0 2x_clock_period 2x input clock period 1 4x_clock_period 4x input clock period 2 16x_clock_period 16x input clock period 3 32x_clock_period 32x input clock period 4 NONE1 none2 5 64x_clock_period 64x input clock period 6 NONE2 none1 7 RESERVED2 reserved2 [7:7] read-write PWM_TIME_PRD_POST_SCALAR_VALUE_CH1 Time base output post scale bits for channel1 [11:8] read-write [1:1]_post_scale 0000 [1:1] post scale 0 [1:2]_post_scale 0001 [1:2] 1 [1:3]_post_scale 0010 [1:3] 2 [1:4]_post_scale 0011 [1:4] 3 [1:5]_post_scale 0100 [1:5] 4 [1:6]_post_scale 0101 [1:6] 5 [1:7]_post_scale 0110 [1:7] 6 [1:8]_post_scale 0111 [1:8] 7 [1:9]_post_scale 1000 [1:9] 8 [1:10]_post_scale 1001 [1:10] 9 [1:11]_post_scale 1010 [1:11] 10 [1:12]_post_scale 1011 [1:12] 11 [1:13]_post_scale 1100 [1:13] 12 [1:14]_post_scale 1101 [1:14] 13 [1:15]_post_scale 1110 [1:15] 14 [1:16]_post_scale 1111 [1:16] 15 RESERVED3 reserved3 [31:12] read-write PWM_TIME_PRD_CTRL_REG_CH1 Base time period control register for channel1 0x10C 32 read-write 0x00000000 0x7 PWM_TIME_PRD_CNTR_RST_FRM_REG Time period counter soft reset [0:0] read-write PWM_TIME_BASE_EN_FRM_REG_CH1 Base timer enable for channnel1 [1:1] read-write Disable timer is disabled 0 Enable timer is enabled 1 PWM_SFT_RST MC PWM soft reset [2:2] read-write RESERVED1 reserved1 [31:3] read-write PWM_TIME_PRD_STS_REG_CH1 Base time period status register for channel1 0x110 32 read-only 0x00000000 0x1 PWM_TIME_PRD_DIR_STS_CH1 Time period counter direction status for channel1. [0:0] read-only Downward downward 0 Upward upward 1 RESERVED1 reserved1 [31:1] read-only PWM_TIME_PRD_CNTR_VALUE_CH1 Time period counter current value for channel1 0x114 32 read-only 0x00000000 0x0000FFFF PWM_TIME_PRD_CNTR_VALUE_CH1 Time period counter current value for channel1 [15:0] read-only RESERVED1 reserved1 [31:16] read-only PWM_TIME_PRD_WR_REG_CH2 Base timer period register of channel2 0x118 32 read-write 0x00000000 0xFFFF PWM_TIME_PRD_REG_WR_VALUE_CH2 Value to update the base timer period register of channel 2 [15:0] read-write RESERVED1 reserved1 [31:16] read-write PWM_TIME_PRD_CNTR_WR_REG_CH2 Base time counter initial value register for channal2 0x11C 32 read-write 0x00000000 0xFFFF PWM_TIME_PRD_CNTR_WR_REG_CH2 To update the base time counter initial value for channel 2 [15:0] read-write RESERVED1 reserved1 [31:16] read-write PWM_TIME_PRD_PARAM_REG_CH2 Base time period config parameter's register for channel2 0x120 32 read-write 0x00000000 0xFFFF TMR_OPEARATING_MODE_CH2 Base timer operating mode for channel2 [2:0] read-write FREE_RUNNING_MODE free running mode 0 SINGLE_EVENT_MODE single event mode 1 DOWN_COUNT_MODE down count mode 2 NONE1 none1 3 UP_DOWN_MODE up/down mode 4 UP_DOWN_DOUBLER_MODE up/down mode with interrupts for double PWM updates 5 NONE2 none2 6 NONE3 none3 7 RESERVED1 reserved1 [3:3] read-write PWM_TIME_PRD_PRE_SCALAR_VALUE_CH2 Base timer input clock pre scale select value for channel2. [6:4] read-write 1X_CLOCK_PERIOD 1x input clock period 0 2X_CLOCK_PERIOD 2x input clock period 1 4X_CLOCK_PERIOD 4x input clock period 2 16X_CLOCK_PERIOD 16x input clock period 3 32X_CLOCK_PERIOD 32x input clock period 4 NONE1 none1 5 64X_CLOCK_PERIOD 64x input clock period 6 NONE2 none2 7 RESERVED2 reserved2 [7:7] read-write PWM_TIME_PRD_POST_SCALAR_VALUE_CH2 Time base output post scale bits for channel2 [11:8] read-write [1:1]_POST_SCALE 0000 [1:1] post scale 0 [1:2]_POST_SCALE 0001 [1:2] 1 [1:3]_POST_SCALE 0010 [1:3] 2 [1:4]_POST_SCALE 0011 [1:4] 3 [1:5]_POST_SCALE 0100 [1:5] 4 [1:6]_POST_SCALE 0101 [1:6] 5 [1:7]_POST_SCALE 0110 [1:7] 6 [1:8]_POST_SCALE 0111 [1:8] 7 [1:9]_POST_SCALE 1000 [1:9] 8 [1:10]_POST_SCALE 1001 [1:10] 9 [1:11]_POST_SCALE 1010 [1:11] 10 [1:12]_POST_SCALE 1011 [1:12] 11 [1:13]_POST_SCALE 1100 [1:13] 12 [1:14]_POST_SCALE 1101 [1:14] 13 [1:15]_POST_SCALE 1110 [1:15] 14 [1:16]_POST_SCALE 1111 [1:16] 15 RESERVED3 reserved3 [31:12] read-write PWM_TIME_PRD_CTRL_REG_CH2 Base time period control register for channel2 0x124 32 read-write 0x00000000 0x7 PWM_TIME_PRD_CNTR_RST_FRM_REG Time period counter soft reset [0:0] read-write PWM_TIME_BASE_EN_FRM_REG_CH2 Base timer enable for channnel2 [1:1] read-write Disable timer is disabled 0 Enable timer is enabled 1 PWM_SFT_RST MC PWM soft reset [2:2] read-write RESERVED1 reserved1 [31:3] read-write PWM_TIME_PRD_STS_REG_CH2 Base time period status register for channel2 0x128 32 read-only 0x00000000 0x1 PWM_TIME_PRD_DIR_STS_CH2 Time period counter direction status for channel2. [0:0] read-only Downward downward 0 Upward upward 1 RESERVED1 reserved1 [31:1] read-only PWM_TIME_PRD_CNTR_VALUE_CH2 Time period counter current value register for channel2 0x12C 32 read-only 0x00000000 0x1 PWM_TIME_PRD_CNTR_VALUE_CH2 Time period counter current value for channel2 [15:0] read-only RESERVED Reserved [31:16] read-only PWM_TIME_PRD_WR_REG_CH3 Base timer period register of channel3 0x130 32 read-write 0x00000000 0xFFFF PWM_TIME_PRD_REG_WR_VALUE_CH3 To update the base time counter initial value for channel 3 [15:0] read-write RESERVED1 reserved1 [31:16] read-write PWM_TIME_PRD_CNTR_WR_REG_CH3 Base time counter initial value register for channel3 0x134 32 read-write 0x00000000 0xFFFF PWM_TIME_PRD_CNTR_WR_REG_CH3 Value to update the base timer period register of channel 3 [15:0] read-write RESERVED1 reserved1 [31:16] read-write PWM_TIME_PRD_PARAM_REG_CH3 Base time period config parameter's register for channel3 0x138 32 read-write 0x00000000 0xFFFF TMR_OPEARATING_MODE_CH3 Base timer operating mode for channel3 [2:0] read-write FREE_RUNNING_MODE free running mode 0 SINGLE_EVENT_MODE single event mode 1 DOWN_COUNT_MODE down count mode 2 NONE1 none 3 UP_DOWN_MODE up/down mode 4 DOUBLE_PWM_UPDATES up/down mode with interrupts for double PWM updates 5 NONE2 none2 6 NONE3 none3 7 RESERVED1 reserved1 [3:3] read-write PWM_TIME_PRD_PRE_SCALAR_VALUE_CH3 Base timer input clock pre scale select value for channel2. [6:4] read-write 1X_CLOCK_PERIOD 1x input clock period 0 2X_CLOCK_PERIOD 2x input clock period 1 4X_CLOCK_PERIOD 4x input clock period 2 16X_CLOCK_PERIOD 16x input clock period 3 32X_CLOCK_PERIOD 32x input clock period 4 NONE1 none 5 64X_CLOCK_PERIOD 64x input clock period 6 NONE2 none2 7 RESERVED2 reserved2 [7:7] read-write PWM_TIME_PRD_POST_SCALAR_VALUE_CH3 Time base output post scale bits for channel3 [11:8] read-write [1:1]_POST_SCALE 0000 [1:1] post scale 0 [1:2]_POST_SCALE 0001 [1:2] 1 [1:3]_POST_SCALE 0010 [1:3] 2 [1:4]_POST_SCALE 0011 [1:4] 3 [1:5]_POST_SCALE 0100 [1:5] 4 [1:6]_POST_SCALE 0101 [1:6] 5 [1:7]_POST_SCALE 0110 [1:7] 6 [1:8]_POST_SCALE 0111 [1:8] 7 [1:9]_POST_SCALE 1000 [1:9] 8 [1:10]_POST_SCALE 1001 [1:10] 9 [1:11]_POST_SCALE 1010 [1:11] 10 [1:12]_POST_SCALE 1011 [1:12] 11 [1:13]_POST_SCALE 1100 [1:13] 12 [1:14]_POST_SCALE 1101 [1:14] 13 [1:15]_POST_SCALE 1110 [1:15] 14 [1:16]_POST_SCALE 1111 [1:16] 15 RESERVED3 reserved3 [31:12] read-write PWM_TIME_PRD_CTRL_REG_CH3 Base time period control register for channel3 0x13C 32 read-write 0x00000000 0x7 PWM_TIME_PRD_CNTR_RST_FRM_REG Time period counter soft reset [0:0] read-write PWM_TIME_BASE_EN_FRM_REG_CH3 Base timer enable for channnel3 [1:1] read-write Disable timer is disabled 0 Enable timer is enabled 1 PWM_SFT_RST MC PWM soft reset [2:2] read-write RESERVED1 reserved1 [31:3] read-write PWM_TIME_PRD_STS_REG_CH3 Base time period status register for channel3 0x140 32 read-only 0x00000000 0x1 PWM_TIME_PRD_DIR_STS_CH3 Time period counter direction status for channel3. [0:0] read-only downward downward 0 upward upward 1 RESERVED1 reserved1 [15:1] read-only RESERVED2 reserved2 [31:16] read-only PWM_TIME_PRD_CNTR_VALUE_CH3 Time period counter current value register for channel3 0x144 32 read-only 0x00000000 0x1 PWM_TIME_PRD_CNTR_VALUE_CH3 Time period counter current value for channe3 [15:0] read-only RESERVED1 reserved1 [31:16] read-only PWM_TIME_PRD_COMMON_REG Time period common register 0x148 32 read-write 0x00000001 0x00000001 PWM_TIME_PRD_USE_0TH_TIMER_ONLY Instead of use four base timers for four channels, use only one base timer for all channels. [0:0] read-write ONE_TIMER_ONE_CHANNEL one base timer for each channel 0 ONE_TIMER_ALL_CHANNEL only one base timer for all channels 1 PWM_TIME_PRD_COMMON_TIMER_VALUE Base timers select to generate special event trigger [2:1] read-write USE_EXT_TIMER_TRIG_FRM_REG Enable to use external trigger for base time counter increment or decrement. [3:3] read-write RESERVED1 reserved1 [31:4] read-write UDMA0 1.0 DMA Performs data transfers along with Addresses and control information UDMA 0x44030000 32 read-write 0 0x830 registers UDMA0 33 DMA_STATUS UDMA Status Register 0x00 32 read-only 0x00000000 MASTER_ENABLE Enable status of controller [0:0] read-only Disable controller is disable 0 Enable controller is enable 1 RESERVED1 Reserved1 [3:1] read-only STATE Current state of the control state machine [7:4] read-only 0 15 RESERVED2 Reserved2 [15:8] read-only CHNLS_MINUS1 Number of available DMA channels minus one [20:16] read-only 0 31 RESERVED3 Reserved3 [27:21] read-only TEST_STATUS To reduce the gate count you can configure the controller [31:28] read-only 0x0 Controller does not includes integration test logic 0 0x1 Controller does not includes integration test logic 1 DMA_CFG DMA Configuration 0x04 32 write-only MASTER_ENABLE Enable for the controller [0:0] write-only Disable controller is disable 0 Enable controller is enable 1 RESERVED1 Reserved1 [4:1] write-only CHNL_PROT_CTRL Sets the AHB-Lite protection by controlling the HPROT[3:1]] signal levels as follows Bit[7]-Controls HPROT[3] to indicate if cacheable access is occurring Bit[6]-Controls HPROT[2] to indicate if cacheable access is occurring Bit[5]-Controls HPROT[1] to indicate if cacheable access is occurring [7:5] write-only RESERVED2 Reserved2 [31:8] write-only CTRL_BASE_PTR Channel Control Data Base Pointer 0x08 32 read-write 0x00000000 0xFFFFFC00 RESERVED1 Reserved1 [9:0] write-only CTRL_BASE_PTR Pointer to the base address of the primary data structure [31:10] read-write ALT_CTRL_BASE_PTR Channel Alternate Control Data Base Pointer 0x0C 32 read-only 0x00000000 ALT_CTRL_BASE_PTR Base address of the alternative data structure [31:0] read-only DMA_WAITONREQUEST_STATUS Channel Wait on request status register 0x10 32 read-only 0x00000000 DMA_WAITONREQ_STATUS Per Channel wait on request status [31:0] read-only CHNL_SW_REQUEST Channel Software Request 0x14 32 write-only CHNL_SW_REQUEST Set the appropriate bit to generate a software DMA request on the corresponding DMA channel [31:0] write-only CHNL_USEBURST_SET UDMA Channel use burst set 0x18 32 read-write 0x00000000 0xFFFFFFFF CHNL_USEBURST_SET The use burst status, or disables dma_sreq[C] from generating DMA requests. [31:0] read-write CHNL_USEBURST_CLR UDMA Channel use burst clear 0x1C 32 write-only CHNL_USEBURST_CLR Set the appropriate bit to enable dma_sreq[] to generate requests [31:0] write-only CHNL_REQ_MASK_SET UDMA Channel request mask set Register 0x20 32 read-write 0x00000000 0xFFFFFFFF CHNL_REQ_MASK_SET Returns the request mask status of dma_req[] and dma_sreq[], or disables the corresponding channel from generating DMA requests [31:0] read-write CHNL_REQ_MASK_CLR UDMA Channel request mask clear 0x24 32 write-only CHNL_REQ_MASK_CLR Set the appropriate bit to enable DMA requests for the channel corresponding to dma_req[] and dma_sreq[] [31:0] write-only CHNL_ENABLE_SET UDMA Channel enable register 0x28 32 read-write 0x00000000 0xFFFFFFFF CHNL_ENABLE_SET This Bits are Used to Load the 16bits of Source address [31:0] read-write CHNL_ENABLE_CLR UDMA Channel enable clear register 0x2C 32 write-only CHNL_ENABLE_CLR Set the appropriate bit to disable the corresponding DMA channel [31:0] write-only CHNL_PRI_ALT_SET UDMA Channel primary or alternate set 0x30 32 read-write 0x00000000 0xFFFFFFFF CHNL_PRI_ALT_SET Returns the channel control data structure status or selects the alternate data structure for the corresponding DMA channel [31:0] read-write CHNL_PRI_ALT_CLR UDMA Channel primary alternate clear 0x34 32 write-only CHNL_PRI_ALT_CLR Set the appropriate bit to select the primary data structure for the corresponding DMA channel [31:0] write-only CHNL_PRIORITY_SET UDMA Channel Priority Set 0x38 32 read-write 0x0000000 0xFFFFFFFF CHNL_PRIORITY_SET Set the appropriate bit to select the primary data structure for the corresponding DMA channel [31:0] read-write CHNL_PRIORITY_CLR UDMA Channel Priority Clear 0x3C 32 write-only CHNL_PRIORITY_CLR Set the appropriate bit to select the default priority level for the specified DMA channel [31:0] write-only ERR_CLR UDMA Bus Error Clear Register 0x4C 32 read-write 0x00000000 0x1 ERR_CLR Returns the status of dma_err [0:0] read-write disabled Read as:0 = dma_err is LOW Write as:0 = No effect, status of dma_err is unchanged 0 enabled Read as:1 = dma_err is HIGH Write as:1 = Sets dma_err LOW 1 RESERVED1 Reserved1 [31:1] read-write UDMA_SKIP_DESC_FETCH_REG UDMA skip descriptor fetch Register 0x50 32 read-write 0x00000000 0x1 SKIP_DESC_FETCH improving the performance of transfer and saves bus cycles. This features has to be enabled always. [31:0] read-write UDMA_DONE_STATUS_REG UDMA Done status Register 0x800 32 read-write 0x000000000 0xFFFFFFFF DONE_STATUS_CHANNEL_0 UDMA done Status of the channel 0 [0:0] read-write disabled Write as:0 will have no effect 0 enabled Read as:1 indicates the transfer is completed for channel 0th Write as:1 will clear the bit 1 DONE_STATUS_CHANNEL_1 UDMA done Status of the channel 1 [1:1] read-write disabled Write as:0 will have no effect 0 enabled Read as:1 indicates the transfer is completed for channel 1st Write as:1 will clear the bit 1 DONE_STATUS_CHANNEL_2 UDMA done Status of the channel 2 [2:2] read-write disabled Write as:0 will have no effect 0 enabled Read as:1 indicates the transfer is completed for channel 2nd Write as:1 will clear the bit 1 DONE_STATUS_CHANNEL_3 UDMA done Status of the channel 3 [3:3] read-write disabled Write as:0 will have no effect 0 enabled Read as:1 indicates the transfer is completed for channel 3rd Write as:1 will clear the bit 1 DONE_STATUS_CHANNEL_4 UDMA done Status of the channel 4 [4:4] read-write disabled Write as:0 will have no effect 0 enabled Read as:1 indicates the transfer is completed for channel 4th Write as:1 will clear the bit 1 DONE_STATUS_CHANNEL_5 UDMA done Status of the channel 5 [5:5] read-write disabled Write as:0 will have no effect 0 enabled Read as:1 indicates the transfer is completed for channel 5th Write as:1 will clear the bit 1 DONE_STATUS_CHANNEL_6 UDMA done Status of the channel 6 [6:6] read-write disabled Write as:0 will have no effect 0 enabled Read as:1 indicates the transfer is completed for channel 6th Write as:1 will clear the bit 1 DONE_STATUS_CHANNEL_7 UDMA done Status of the channel 7 [7:7] read-write disabled Write as:0 will have no effect 0 enabled Read as:1 indicates the transfer is completed for channel 7th Write as:1 will clear the bit 1 DONE_STATUS_CHANNEL_8 UDMA done Status of the channel 8 [8:8] read-write disabled Write as:0 will have no effect 0 enabled Read as:1 indicates the transfer is completed for channel 8th Write as:1 will clear the bit 1 DONE_STATUS_CHANNEL_9 UDMA done Status of the channel 9 [9:9] read-write disabled Write as:0 will have no effect 0 enabled Read as:1 indicates the transfer is completed for channel 9th Write as:1 will clear the bit 1 DONE_STATUS_CHANNEL_10 UDMA done Status of the channel 10 [10:10] read-write disabled Write as:0 will have no effect 0 enabled Read as:1 indicates the transfer is completed for channel 10th Write as:1 will clear the bit 1 DONE_STATUS_CHANNEL_11 UDMA done Status of the channel 3 [11:11] read-write disabled Write as:0 will have no effect 0 enabled Read as:1 indicates the transfer is completed for channel 11th Write as:1 will clear the bit 1 DONE_STATUS_CHANNEL_12 UDMA done Status of the channel 12 [12:12] read-write disabled Write as:0 will have no effect 0 enabled Read as:1 indicates the transfer is completed for channel 12th Write as:1 will clear the bit 1 DONE_STATUS_CHANNEL_13 UDMA done Status of the channel 13 [13:13] read-write disabled Write as:0 will have no effect 0 enabled Read as:1 indicates the transfer is completed for channel 13th Write as:1 will clear the bit 1 DONE_STATUS_CHANNEL_14 UDMA done Status of the channel 14 [14:14] read-write disabled Write as:0 will have no effect 0 enabled Read as:1 indicates the transfer is completed for channel 14th Write as:1 will clear the bit 1 DONE_STATUS_CHANNEL_15 UDMA done Status of the channel 15 [15:15] read-write disabled Write as:0 will have no effect 0 enabled Read as:1 indicates the transfer is completed for channel 15th Write as:1 will clear the bit 1 DONE_STATUS_CHANNEL_16 UDMA done Status of the channel 16 [16:16] read-write disabled Write as:0 will have no effect 0 enabled Read as:1 indicates the transfer is completed for channel 16th Write as:1 will clear the bit 1 DONE_STATUS_CHANNEL_17 UDMA done Status of the channel 17 [17:17] read-write disabled Write as:0 will have no effect 0 enabled Read as:1 indicates the transfer is completed for channel 17th Write as:1 will clear the bit 1 DONE_STATUS_CHANNEL_18 UDMA done Status of the channel 18 [18:18] read-write disabled Write as:0 will have no effect 0 enabled Read as:1 indicates the transfer is completed for channel 18th Write as:1 will clear the bit 1 DONE_STATUS_CHANNEL_19 UDMA done Status of the channel 19 [19:19] read-write disabled Write as:0 will have no effect 0 enabled Read as:1 indicates the transfer is completed for channel 19th Write as:1 will clear the bit 1 DONE_STATUS_CHANNEL_20 UDMA done Status of the channel 3 [20:20] read-write disabled Write as:0 will have no effect 0 enabled Read as:1 indicates the transfer is completed for channel 20th Write as:1 will clear the bit 1 DONE_STATUS_CHANNEL_21 UDMA done Status of the channel 21 [21:21] read-write disabled Write as:0 will have no effect 0 enabled Read as:1 indicates the transfer is completed for channel 21th Write as:1 will clear the bit 1 DONE_STATUS_CHANNEL_22 UDMA done Status of the channel 22 [22:22] read-write disabled Write as:0 will have no effect 0 enabled Read as:1 indicates the transfer is completed for channel 22th Write as:1 will clear the bit 1 DONE_STATUS_CHANNEL_23 UDMA done Status of the channel 23 [23:23] read-write disabled Write as:0 will have no effect 0 enabled Read as:1 indicates the transfer is completed for channel 23rd Write as:1 will clear the bit 1 DONE_STATUS_CHANNEL_24 UDMA done Status of the channel 24 [24:24] read-write disabled Write as:0 will have no effect 0 enabled Read as:1 indicates the transfer is completed for channel 24th Write as:1 will clear the bit 1 DONE_STATUS_CHANNEL_25 UDMA done Status of the channel 25 [25:25] read-write disabled Write as:0 will have no effect 0 enabled Read as:1 indicates the transfer is completed for channel 25th Write as:1 will clear the bit 1 DONE_STATUS_CHANNEL_26 UDMA done Status of the channel 26 [26:26] read-write disabled Write as:0 will have no effect 0 enabled Read as:1 indicates the transfer is completed for channel 26th Write as:1 will clear the bit 1 DONE_STATUS_CHANNEL_27 UDMA done Status of the channel 27 [27:27] read-write disabled Write as:0 will have no effect 0 enabled Read as:1 indicates the transfer is completed for channel 27th Write as:1 will clear the bit 1 DONE_STATUS_CHANNEL_28 UDMA done Status of the channel 28 [28:28] read-write disabled Write as:0 will have no effect 0 enabled Read as:1 indicates the transfer is completed for channel 28th Write as:1 will clear the bit 1 DONE_STATUS_CHANNEL_29 UDMA done Status of the channel 29 [29:29] read-write disabled Write as:0 will have no effect 0 enabled Read as:1 indicates the transfer is completed for channel 29th Write as:1 will clear the bit 1 DONE_STATUS_CHANNEL_30 UDMA done Status of the channel 30 [30:30] read-write disabled Write as:0 will have no effect 0 enabled Read as:1 indicates the transfer is completed for channel 30th Write as:1 will clear the bit 1 DONE_STATUS_CHANNEL_31 UDMA done Status of the channel 31 [31:31] read-write disabled Write as:0 will have no effect 0 enabled Read as:1 indicates the transfer is completed for channel 31st Write as:1 will clear the bit 1 CHANNEL_STATUS_REG Channel status Register 0x804 32 read-only 0x00000000 0xFFFFFFFF BUSY_OR_IDEAL_STATUS_CHANNEL_0 Reading 1 indicates that the channel 0 is busy [0:0] read-only BUSY_OR_IDEAL_STATUS_CHANNEL_1 Reading 1 indicates that the channel 1 is busy [1:1] read-only BUSY_OR_IDEAL_STATUS_CHANNEL_2 Reading 1 indicates that the channel 2 is busy [2:2] read-only BUSY_OR_IDEAL_STATUS_CHANNEL_3 Reading 1 indicates that the channel 3 is busy [3:3] read-only BUSY_OR_IDEAL_STATUS_CHANNEL_4 Reading 1 indicates that the channel 4 is busy [4:4] read-only BUSY_OR_IDEAL_STATUS_CHANNEL_5 Reading 1 indicates that the channel 5 is busy [5:5] read-only BUSY_OR_IDEAL_STATUS_CHANNEL_6 Reading 1 indicates that the channel 6 is busy [6:6] read-only BUSY_OR_IDEAL_STATUS_CHANNEL_7 Reading 1 indicates that the channel 7 is busy [7:7] read-only BUSY_OR_IDEAL_STATUS_CHANNEL_8 Reading 1 indicates that the channel 8 is busy [8:8] read-only BUSY_OR_IDEAL_STATUS_CHANNEL_9 Reading 1 indicates that the channel 9 is busy [9:9] read-only BUSY_OR_IDEAL_STATUS_CHANNEL_10 Reading 1 indicates that the channel 10 is busy [10:10] read-only BUSY_OR_IDEAL_STATUS_CHANNEL_11 Reading 1 indicates that the channel 11 is busy [11:11] read-only BUSY_OR_IDEAL_STATUS_CHANNEL_12 Reading 1 indicates that the channel 12 is busy [12:12] read-only BUSY_OR_IDEAL_STATUS_CHANNEL_13 Reading 1 indicates that the channel 13 is busy [13:13] read-only BUSY_OR_IDEAL_STATUS_CHANNEL_14 Reading 1 indicates that the channel 14 is busy [14:14] read-only BUSY_OR_IDEAL_STATUS_CHANNEL_15 Reading 1 indicates that the channel 15 is busy [15:15] read-only BUSY_OR_IDEAL_STATUS_CHANNEL_16 Reading 1 indicates that the channel 16 is busy [16:16] read-only BUSY_OR_IDEAL_STATUS_CHANNEL_17 Reading 1 indicates that the channel 17 is busy [17:17] read-only BUSY_OR_IDEAL_STATUS_CHANNEL_18 Reading 1 indicates that the channel 18 is busy [18:18] read-only BUSY_OR_IDEAL_STATUS_CHANNEL_19 Reading 1 indicates that the channel 19 is busy [19:19] read-only BUSY_OR_IDEAL_STATUS_CHANNEL_20 Reading 1 indicates that the channel 20 is busy [20:20] read-only BUSY_OR_IDEAL_STATUS_CHANNEL_21 Reading 1 indicates that the channel 21 is busy [21:21] read-only BUSY_OR_IDEAL_STATUS_CHANNEL_22 Reading 1 indicates that the channel 22 is busy [22:22] read-only BUSY_OR_IDEAL_STATUS_CHANNEL_23 Reading 1 indicates that the channel 23 is busy [23:23] read-only BUSY_OR_IDEAL_STATUS_CHANNEL_24 Reading 1 indicates that the channel 24 is busy [24:24] read-only BUSY_OR_IDEAL_STATUS_CHANNEL_25 Reading 1 indicates that the channel 25 is busy [25:25] read-only BUSY_OR_IDEAL_STATUS_CHANNEL_26 Reading 1 indicates that the channel 26 is busy [26:26] read-only BUSY_OR_IDEAL_STATUS_CHANNEL_27 Reading 1 indicates that the channel 27 is busy [27:27] read-only BUSY_OR_IDEAL_STATUS_CHANNEL_28 Reading 1 indicates that the channel 28 is busy [28:28] read-only BUSY_OR_IDEAL_STATUS_CHANNEL_29 Reading 1 indicates that the channel 29 is busy [29:29] read-only BUSY_OR_IDEAL_STATUS_CHANNEL_30 Reading 1 indicates that the channel 30 is busy [30:30] read-only BUSY_OR_IDEAL_STATUS_CHANNEL_31 Reading 1 indicates that the channel 31 is busy [31:31] read-only UDMA_CONFIG_CTRL_REG DMA Controller Transfer Length Register 0x828 32 read-write 0x000000000 0x1 SINGLE_REQUEST_ENABLE Enabled signal for single request [0:0] read-write disabled Single request will be disabled 0 enabled Single request will be enabled 1 RESERVED1 Reserved for future use. [31:1] read-write 8 0x4 UDMA_PERIPHERAL_SEL_CHn_REG Peripheral select channel register channels 0 - 7 0x808 Peripheral_Select_CH__n_ peripheral select for channel _n_ 0x00 32 read-write 0x00000000 0x0000000F peripheral_select_channel_n_ peripheral select channel _n_ [4:0] read-write RESERVED1 reserved1 [31:5] read-write UDMA1 1.0 DMA Performs data transfers along with Addresses and control information UDMA 0x24078000 32 read-write 0 0x830 registers UDMA1 10 DMA_STATUS UDMA Status Register 0x00 32 read-only 0x00000000 MASTER_ENABLE Enable status of controller [0:0] read-only Disable controller is disable 0 Enable controller is enable 1 RESERVED1 Reserved1 [3:1] read-only STATE Current state of the control state machine [7:4] read-only 0 15 RESERVED2 Reserved2 [15:8] read-only CHNLS_MINUS1 Number of available DMA channels minus one [20:16] read-only 0 31 RESERVED3 Reserved3 [27:21] read-only TEST_STATUS To reduce the gate count you can configure the controller [31:28] read-only 0x0 Controller does not includes integration test logic 0 0x1 Controller does not includes integration test logic 1 DMA_CFG DMA Configuration 0x04 32 write-only MASTER_ENABLE Enable for the controller [0:0] write-only Disable controller is disable 0 Enable controller is enable 1 RESERVED1 Reserved1 [4:1] write-only CHNL_PROT_CTRL Sets the AHB-Lite protection by controlling the HPROT[3:1]] signal levels as follows Bit[7]-Controls HPROT[3] to indicate if cacheable access is occurring Bit[6]-Controls HPROT[2] to indicate if cacheable access is occurring Bit[5]-Controls HPROT[1] to indicate if cacheable access is occurring [7:5] write-only RESERVED2 Reserved2 [31:8] write-only CTRL_BASE_PTR Channel Control Data Base Pointer 0x08 32 read-write 0x00000000 0xFFFFFC00 RESERVED1 Reserved1 [9:0] write-only CTRL_BASE_PTR Pointer to the base address of the primary data structure [31:10] read-write ALT_CTRL_BASE_PTR Channel Alternate Control Data Base Pointer 0x0C 32 read-only 0x00000000 ALT_CTRL_BASE_PTR Base address of the alternative data structure [31:0] read-only DMA_WAITONREQUEST_STATUS Channel Wait on request status register 0x10 32 read-only 0x00000000 DMA_WAITONREQ_STATUS Per Channel wait on request status [31:0] read-only CHNL_SW_REQUEST Channel Software Request 0x14 32 write-only CHNL_SW_REQUEST Set the appropriate bit to generate a software DMA request on the corresponding DMA channel [31:0] write-only CHNL_USEBURST_SET UDMA Channel use burst set 0x18 32 read-write 0x00000000 0xFFFFFFFF CHNL_USEBURST_SET The use burst status, or disables dma_sreq[C] from generating DMA requests. [31:0] read-write CHNL_USEBURST_CLR UDMA Channel use burst clear 0x1C 32 write-only CHNL_USEBURST_CLR Set the appropriate bit to enable dma_sreq[] to generate requests [31:0] write-only CHNL_REQ_MASK_SET UDMA Channel request mask set Register 0x20 32 read-write 0x00000000 0xFFFFFFFF CHNL_REQ_MASK_SET Returns the request mask status of dma_req[] and dma_sreq[], or disables the corresponding channel from generating DMA requests [31:0] read-write CHNL_REQ_MASK_CLR UDMA Channel request mask clear 0x24 32 write-only CHNL_REQ_MASK_CLR Set the appropriate bit to enable DMA requests for the channel corresponding to dma_req[] and dma_sreq[] [31:0] write-only CHNL_ENABLE_SET UDMA Channel enable register 0x28 32 read-write 0x00000000 0xFFFFFFFF CHNL_ENABLE_SET This Bits are Used to Load the 16bits of Source address [31:0] read-write CHNL_ENABLE_CLR UDMA Channel enable clear register 0x2C 32 write-only CHNL_ENABLE_CLR Set the appropriate bit to disable the corresponding DMA channel [31:0] write-only CHNL_PRI_ALT_SET UDMA Channel primary or alternate set 0x30 32 read-write 0x00000000 0xFFFFFFFF CHNL_PRI_ALT_SET Returns the channel control data structure status or selects the alternate data structure for the corresponding DMA channel [31:0] read-write CHNL_PRI_ALT_CLR UDMA Channel primary alternate clear 0x34 32 write-only CHNL_PRI_ALT_CLR Set the appropriate bit to select the primary data structure for the corresponding DMA channel [31:0] write-only CHNL_PRIORITY_SET UDMA Channel Priority Set 0x38 32 read-write 0x0000000 0xFFFFFFFF CHNL_PRIORITY_SET Set the appropriate bit to select the primary data structure for the corresponding DMA channel [31:0] read-write CHNL_PRIORITY_CLR UDMA Channel Priority Clear 0x3C 32 write-only CHNL_PRIORITY_CLR Set the appropriate bit to select the default priority level for the specified DMA channel [31:0] write-only ERR_CLR UDMA Bus Error Clear Register 0x4C 32 read-write 0x00000000 0x1 ERR_CLR Returns the status of dma_err [0:0] read-write disabled Read as:0 = dma_err is LOW Write as:0 = No effect, status of dma_err is unchanged 0 enabled Read as:1 = dma_err is HIGH Write as:1 = Sets dma_err LOW 1 RESERVED1 Reserved1 [31:1] read-write UDMA_SKIP_DESC_FETCH_REG UDMA skip descriptor fetch Register 0x50 32 read-write 0x00000000 0x1 SKIP_DESC_FETCH improving the performance of transfer and saves bus cycles. This features has to be enabled always. [31:0] read-write UDMA_DONE_STATUS_REG UDMA Done status Register 0x800 32 read-write 0x000000000 0xFFFFFFFF DONE_STATUS_CHANNEL_0 UDMA done Status of the channel 0 [0:0] read-write disabled Write as:0 will have no effect 0 enabled Read as:1 indicates the transfer is completed for channel 0th Write as:1 will clear the bit 1 DONE_STATUS_CHANNEL_1 UDMA done Status of the channel 1 [1:1] read-write disabled Write as:0 will have no effect 0 enabled Read as:1 indicates the transfer is completed for channel 1st Write as:1 will clear the bit 1 DONE_STATUS_CHANNEL_2 UDMA done Status of the channel 2 [2:2] read-write disabled Write as:0 will have no effect 0 enabled Read as:1 indicates the transfer is completed for channel 2nd Write as:1 will clear the bit 1 DONE_STATUS_CHANNEL_3 UDMA done Status of the channel 3 [3:3] read-write disabled Write as:0 will have no effect 0 enabled Read as:1 indicates the transfer is completed for channel 3rd Write as:1 will clear the bit 1 DONE_STATUS_CHANNEL_4 UDMA done Status of the channel 4 [4:4] read-write disabled Write as:0 will have no effect 0 enabled Read as:1 indicates the transfer is completed for channel 4th Write as:1 will clear the bit 1 DONE_STATUS_CHANNEL_5 UDMA done Status of the channel 5 [5:5] read-write disabled Write as:0 will have no effect 0 enabled Read as:1 indicates the transfer is completed for channel 5th Write as:1 will clear the bit 1 DONE_STATUS_CHANNEL_6 UDMA done Status of the channel 6 [6:6] read-write disabled Write as:0 will have no effect 0 enabled Read as:1 indicates the transfer is completed for channel 6th Write as:1 will clear the bit 1 DONE_STATUS_CHANNEL_7 UDMA done Status of the channel 7 [7:7] read-write disabled Write as:0 will have no effect 0 enabled Read as:1 indicates the transfer is completed for channel 7th Write as:1 will clear the bit 1 DONE_STATUS_CHANNEL_8 UDMA done Status of the channel 8 [8:8] read-write disabled Write as:0 will have no effect 0 enabled Read as:1 indicates the transfer is completed for channel 8th Write as:1 will clear the bit 1 DONE_STATUS_CHANNEL_9 UDMA done Status of the channel 9 [9:9] read-write disabled Write as:0 will have no effect 0 enabled Read as:1 indicates the transfer is completed for channel 9th Write as:1 will clear the bit 1 DONE_STATUS_CHANNEL_10 UDMA done Status of the channel 10 [10:10] read-write disabled Write as:0 will have no effect 0 enabled Read as:1 indicates the transfer is completed for channel 10th Write as:1 will clear the bit 1 DONE_STATUS_CHANNEL_11 UDMA done Status of the channel 3 [11:11] read-write disabled Write as:0 will have no effect 0 enabled Read as:1 indicates the transfer is completed for channel 11th Write as:1 will clear the bit 1 DONE_STATUS_CHANNEL_12 UDMA done Status of the channel 12 [12:12] read-write disabled Write as:0 will have no effect 0 enabled Read as:1 indicates the transfer is completed for channel 12th Write as:1 will clear the bit 1 DONE_STATUS_CHANNEL_13 UDMA done Status of the channel 13 [13:13] read-write disabled Write as:0 will have no effect 0 enabled Read as:1 indicates the transfer is completed for channel 13th Write as:1 will clear the bit 1 DONE_STATUS_CHANNEL_14 UDMA done Status of the channel 14 [14:14] read-write disabled Write as:0 will have no effect 0 enabled Read as:1 indicates the transfer is completed for channel 14th Write as:1 will clear the bit 1 DONE_STATUS_CHANNEL_15 UDMA done Status of the channel 15 [15:15] read-write disabled Write as:0 will have no effect 0 enabled Read as:1 indicates the transfer is completed for channel 15th Write as:1 will clear the bit 1 DONE_STATUS_CHANNEL_16 UDMA done Status of the channel 16 [16:16] read-write disabled Write as:0 will have no effect 0 enabled Read as:1 indicates the transfer is completed for channel 16th Write as:1 will clear the bit 1 DONE_STATUS_CHANNEL_17 UDMA done Status of the channel 17 [17:17] read-write disabled Write as:0 will have no effect 0 enabled Read as:1 indicates the transfer is completed for channel 17th Write as:1 will clear the bit 1 DONE_STATUS_CHANNEL_18 UDMA done Status of the channel 18 [18:18] read-write disabled Write as:0 will have no effect 0 enabled Read as:1 indicates the transfer is completed for channel 18th Write as:1 will clear the bit 1 DONE_STATUS_CHANNEL_19 UDMA done Status of the channel 19 [19:19] read-write disabled Write as:0 will have no effect 0 enabled Read as:1 indicates the transfer is completed for channel 19th Write as:1 will clear the bit 1 DONE_STATUS_CHANNEL_20 UDMA done Status of the channel 3 [20:20] read-write disabled Write as:0 will have no effect 0 enabled Read as:1 indicates the transfer is completed for channel 20th Write as:1 will clear the bit 1 DONE_STATUS_CHANNEL_21 UDMA done Status of the channel 21 [21:21] read-write disabled Write as:0 will have no effect 0 enabled Read as:1 indicates the transfer is completed for channel 21th Write as:1 will clear the bit 1 DONE_STATUS_CHANNEL_22 UDMA done Status of the channel 22 [22:22] read-write disabled Write as:0 will have no effect 0 enabled Read as:1 indicates the transfer is completed for channel 22th Write as:1 will clear the bit 1 DONE_STATUS_CHANNEL_23 UDMA done Status of the channel 23 [23:23] read-write disabled Write as:0 will have no effect 0 enabled Read as:1 indicates the transfer is completed for channel 23rd Write as:1 will clear the bit 1 DONE_STATUS_CHANNEL_24 UDMA done Status of the channel 24 [24:24] read-write disabled Write as:0 will have no effect 0 enabled Read as:1 indicates the transfer is completed for channel 24th Write as:1 will clear the bit 1 DONE_STATUS_CHANNEL_25 UDMA done Status of the channel 25 [25:25] read-write disabled Write as:0 will have no effect 0 enabled Read as:1 indicates the transfer is completed for channel 25th Write as:1 will clear the bit 1 DONE_STATUS_CHANNEL_26 UDMA done Status of the channel 26 [26:26] read-write disabled Write as:0 will have no effect 0 enabled Read as:1 indicates the transfer is completed for channel 26th Write as:1 will clear the bit 1 DONE_STATUS_CHANNEL_27 UDMA done Status of the channel 27 [27:27] read-write disabled Write as:0 will have no effect 0 enabled Read as:1 indicates the transfer is completed for channel 27th Write as:1 will clear the bit 1 DONE_STATUS_CHANNEL_28 UDMA done Status of the channel 28 [28:28] read-write disabled Write as:0 will have no effect 0 enabled Read as:1 indicates the transfer is completed for channel 28th Write as:1 will clear the bit 1 DONE_STATUS_CHANNEL_29 UDMA done Status of the channel 29 [29:29] read-write disabled Write as:0 will have no effect 0 enabled Read as:1 indicates the transfer is completed for channel 29th Write as:1 will clear the bit 1 DONE_STATUS_CHANNEL_30 UDMA done Status of the channel 30 [30:30] read-write disabled Write as:0 will have no effect 0 enabled Read as:1 indicates the transfer is completed for channel 30th Write as:1 will clear the bit 1 DONE_STATUS_CHANNEL_31 UDMA done Status of the channel 31 [31:31] read-write disabled Write as:0 will have no effect 0 enabled Read as:1 indicates the transfer is completed for channel 31st Write as:1 will clear the bit 1 CHANNEL_STATUS_REG Channel status Register 0x804 32 read-only 0x00000000 0xFFFFFFFF BUSY_OR_IDEAL_STATUS_CHANNEL_0 Reading 1 indicates that the channel 0 is busy [0:0] read-only BUSY_OR_IDEAL_STATUS_CHANNEL_1 Reading 1 indicates that the channel 1 is busy [1:1] read-only BUSY_OR_IDEAL_STATUS_CHANNEL_2 Reading 1 indicates that the channel 2 is busy [2:2] read-only BUSY_OR_IDEAL_STATUS_CHANNEL_3 Reading 1 indicates that the channel 3 is busy [3:3] read-only BUSY_OR_IDEAL_STATUS_CHANNEL_4 Reading 1 indicates that the channel 4 is busy [4:4] read-only BUSY_OR_IDEAL_STATUS_CHANNEL_5 Reading 1 indicates that the channel 5 is busy [5:5] read-only BUSY_OR_IDEAL_STATUS_CHANNEL_6 Reading 1 indicates that the channel 6 is busy [6:6] read-only BUSY_OR_IDEAL_STATUS_CHANNEL_7 Reading 1 indicates that the channel 7 is busy [7:7] read-only BUSY_OR_IDEAL_STATUS_CHANNEL_8 Reading 1 indicates that the channel 8 is busy [8:8] read-only BUSY_OR_IDEAL_STATUS_CHANNEL_9 Reading 1 indicates that the channel 9 is busy [9:9] read-only BUSY_OR_IDEAL_STATUS_CHANNEL_10 Reading 1 indicates that the channel 10 is busy [10:10] read-only BUSY_OR_IDEAL_STATUS_CHANNEL_11 Reading 1 indicates that the channel 11 is busy [11:11] read-only BUSY_OR_IDEAL_STATUS_CHANNEL_12 Reading 1 indicates that the channel 12 is busy [12:12] read-only BUSY_OR_IDEAL_STATUS_CHANNEL_13 Reading 1 indicates that the channel 13 is busy [13:13] read-only BUSY_OR_IDEAL_STATUS_CHANNEL_14 Reading 1 indicates that the channel 14 is busy [14:14] read-only BUSY_OR_IDEAL_STATUS_CHANNEL_15 Reading 1 indicates that the channel 15 is busy [15:15] read-only BUSY_OR_IDEAL_STATUS_CHANNEL_16 Reading 1 indicates that the channel 16 is busy [16:16] read-only BUSY_OR_IDEAL_STATUS_CHANNEL_17 Reading 1 indicates that the channel 17 is busy [17:17] read-only BUSY_OR_IDEAL_STATUS_CHANNEL_18 Reading 1 indicates that the channel 18 is busy [18:18] read-only BUSY_OR_IDEAL_STATUS_CHANNEL_19 Reading 1 indicates that the channel 19 is busy [19:19] read-only BUSY_OR_IDEAL_STATUS_CHANNEL_20 Reading 1 indicates that the channel 20 is busy [20:20] read-only BUSY_OR_IDEAL_STATUS_CHANNEL_21 Reading 1 indicates that the channel 21 is busy [21:21] read-only BUSY_OR_IDEAL_STATUS_CHANNEL_22 Reading 1 indicates that the channel 22 is busy [22:22] read-only BUSY_OR_IDEAL_STATUS_CHANNEL_23 Reading 1 indicates that the channel 23 is busy [23:23] read-only BUSY_OR_IDEAL_STATUS_CHANNEL_24 Reading 1 indicates that the channel 24 is busy [24:24] read-only BUSY_OR_IDEAL_STATUS_CHANNEL_25 Reading 1 indicates that the channel 25 is busy [25:25] read-only BUSY_OR_IDEAL_STATUS_CHANNEL_26 Reading 1 indicates that the channel 26 is busy [26:26] read-only BUSY_OR_IDEAL_STATUS_CHANNEL_27 Reading 1 indicates that the channel 27 is busy [27:27] read-only BUSY_OR_IDEAL_STATUS_CHANNEL_28 Reading 1 indicates that the channel 28 is busy [28:28] read-only BUSY_OR_IDEAL_STATUS_CHANNEL_29 Reading 1 indicates that the channel 29 is busy [29:29] read-only BUSY_OR_IDEAL_STATUS_CHANNEL_30 Reading 1 indicates that the channel 30 is busy [30:30] read-only BUSY_OR_IDEAL_STATUS_CHANNEL_31 Reading 1 indicates that the channel 31 is busy [31:31] read-only UDMA_CONFIG_CTRL_REG DMA Controller Transfer Length Register 0x828 32 read-write 0x000000000 0x1 SINGLE_REQUEST_ENABLE Enabled signal for single request [0:0] read-write disabled Single request will be disabled 0 enabled Single request will be enabled 1 RESERVED1 Reserved for future use. [31:1] read-write UDMA_INTR_MASK_REG Mask the uDMA interrupt register 0x82C 32 read-write UDMA_INTR_MASK Mask the uDMA interrupt register [11:0] read-write RESERVED1 RESERVED1 [31:12] read-only GPDMA 1.0 GPDMA is an AMBA complaint peripheral unit supports 8-channels GPDMA 0x21080000 32 read-write 0x00 0x734 registers GPDMA 31 INTERRUPT_REG Interrupt Register 0x1084 32 read-write 0x00000000 0xFFFFFFFF GPDMAC_INT_STAT Interrupt Status [7:0] read-write RESERVED1 reserved1 [31:8] read-only INTERRUPT_MASK_REG Interrupt Mask Register 0x1088 32 read-write 0xFFFF 0xFF RESERVED1 reserved1 [7:0] read-write LINK_LIST_FETCH_MASK Linked list fetch done interrupt bit mask control. By default, descriptor fetch done interrupt is masked. [15:8] read-write TFR_DONE_MASK Transfer done interrupt bit mask control. [23:16] read-write RESERVED2 reserved2 [31:24] read-write INTERRUPT_STAT_REG Interrupt status register 0x108C 32 read-write 0x00000000 0xFFFFFFFF HRESP_ERR0 DMA error bit [0:0] read-write LINK_LIST_FETCH_DONE0 This bit indicates the status of linked list descriptor fetch done for channel 0 [1:1] read-write TFR_DONE0 This bit indicates the status of DMA transfer done interrupt for channel 0 [2:2] read-write GPDMAC_ERR0 transfer size or burst size or h size mismatch error [3:3] read-write HRESP_ERR1 HRESP error bit [4:4] read-write LINK_LIST_FETCH_DONE1 This bit indicates the status of linked list descriptor fetch done for channel 1 [5:5] read-write TFR_DONE1 This bit indicates the status of DMA transfer done interrupt for channel 1. [6:6] read-write GPDMAC_ERR1 transfer size or burst size or h size mismatch error [7:7] read-write HRESP_ERR2 HRESP error bit [8:8] read-write LINK_LIST_FETCH_DONE2 This bit indicates the status of linked list descriptor fetch done for channel 2. [9:9] read-write TFR_DONE2 This bit indicates the status of DMA transfer done interrupt for channel 2. [10:10] read-write GPDMAC_ERR2 transfer size or burst size or h size mismatch error [11:11] read-write HRESP_ERR3 HRESP error bit [12:12] read-write LINK_LIST_FETCH_DONE3 This bit indicates the status of linked list descriptor fetch done for channel 3. [13:13] read-write TFR_DONE3 This bit indicates the status of DMA transfer done interrupt for channel 3. [14:14] read-write GPDMAC_ERR3 transfer size or burst size or h size mismatch error [15:15] read-write HRESP_ERR4 HRESP error bit [16:16] read-write LINK_LIST_FETCH_DONE4 This bit indicates the status of linked list descriptor fetch done for channel 4. [17:17] read-write TFR_DONE4 This bit indicates the status of DMA transfer done interrupt for channel 4. [18:18] read-write GPDMAC_ERR4 transfer size or burst size or h size mismatch error [19:19] read-write HRESP_ERR5 HRESP error bit [20:20] read-write LINK_LIST_FETCH_DONE5 This bit indicates the status of linked list descriptor fetch done for channel 5. [21:21] read-write TFR_DONE5 This bit indicates the status of DMA transfer done interrupt for channel 5. [22:22] read-write GPDMAC_ERR5 transfer size or burst size or h size mismatch error [23:23] read-write HRESP_ERR6 HRESP error bit [24:24] read-only LINK_LIST_FETCH_DONE6 This bit indicates the status of linked list descriptor fetch done for channel 6. [25:25] read-write TFR_DONE6 This bit indicates the status of DMA transfer done interrupt for channel 6. [26:26] read-write GPDMAC_ERR6 transfer size or burst size or h size mismatch error [27:27] read-write HRESP_ERR7 HRESP error bit [28:28] read-write LINK_LIST_FETCH_DONE7 This bit indicates the status of linked list descriptor fetch done for channel 7. [29:29] read-write TFR_DONE7 This bit indicates the status of DMA transfer done interrupt for channel 7. [30:30] read-write GPDMAC_ERR7 transfer size or burst size or h size mismatch error [31:31] read-write DMA_CHNL_ENABLE_REG This register used for enable DMA channel 0X1090 32 read-write 0x00000000 0xFFFFFFFF CH_ENB CWhen a bit is set to one, it indicates, corresponding channel is enabled for dma operation [7:0] read-write RESERVED1 Reserved1 [31:8] read-only DMA_CHNL_SQUASH_REG This register used for enable DMA channel squash 0x1094 32 read-write 0x00000000 0xFFFFFFFF CH_DIS CPU Will be masked to write zeros, CPU is allowed write 1 only [7:0] read-write RESERVED1 Reserved1 [31:8] read-only DMA_CHNL_LOCK_REG This register used for enable DMA channel squash 0x1098 32 read-write 0x00000000 0xFFFFFFFF CHNL_LOCK When set entire DMA block transfer is done, before other DMA request is serviced [7:0] read-write RESERVED1 Reserved1 [31:8] read-only 8 0x100 CHANNEL_CONFIGn channel configuration registers (0-7) 0x1004 LINK_LIST_PTR_REGS_CHNL__n_ Link List Register for channel _n_ 0x00 32 read-write 0x00 0xFF LINK_LIST_PTR_REG_CHNL This is the address of the memory location from which we get our next descriptor [31:0] read-write SRC_ADDR_REG_CHNL__n_ Source Address Register for channel _n_ 0x04 32 read-write 0x00000000 0xFFFFFFFF SRC_ADDR This is the address of the memory location from which we get our next descriptor [31:0] read-write DEST_ADDR_REG_CHNL__n_ Source Address Register for channel _n_ 0x08 32 read-write 0x00000000 0xFFFFFFFF DEST_ADDR This is the destination address to whih the data is sent [31:0] read-write CHANNEL_CTRL_REG_CHNL__n_ Channel Control Register for channel _n_ 0x0C 32 read-write 0x00000000 0xFFFFFFFF DMA_BLK_SIZE This is data to be transmitted. Loaded at the beginning of the DMA transfer and decremented at every dma transaction. [11:0] read-write TRNS_TYPE DMA transfer type [13:12] read-write 00 Memory to Memory 0 01 memory to peripheral 1 10 peripheral to memory 2 11 peripheral to peripheral 3 DMA_FLOW_CTRL DMA flow control [15:14] read-write 00 RPDMAC :can be set for any type of transfers 0 01 source peripheral : typically set for peripheral to memory 1 10 peripheral to memory destination peripheral : typically set for memory to peripheral 2 11 src_and_dest peripheral : Typically set for peripheral to peripheral 3 MSTR_IF_FETCH_SEL This selects the MASTER IF from which data to be fetched [16:16] read-write Disable 0:MSTR-0 for fetch (from src) 0 Enable 1:MSTR-1 for fetch (from src) 1 MSTR_IF_SEND_SEL This selects the MASTER IF from which data to be sent [17:17] read-write Disable 0:MSTR-0 for send (to destination) 0 Enable 1:MSTR-1 for send (to destination) 1 DEST_DATA_WIDTH Data transfer to destination. [19:18] read-write 8_Bits_Data_On_Bus 08 bits of data on the bus 00 16_Bits_Data_On_Bus 16 bits of data on the bus 01 32_Bits_Data_On_Bus 32 bits of data on the bus 2 Reserved Reserved 3 SRC_DATA_WIDTH Data transfer from source. [21:20] read-write 00 08 bits of data on the bus 0 01 16 bits of data on the bus 1 10 32 bits of data on the bus 2 11 reserved2 3 SRC_ALIGN Reserved.Value set to 0 We do not do any singles. We just do burst, save first 3 bytes in to residue buffer in one cycle, In the next cycle send 4 bytes to fifo, save 3 bytes in to residue. This continues on. [22:22] read-write LINK_LIST_ON This mode is set, when we do link listed operation [23:23] read-write LINK_LIST_MSTR_SEL This mode is set, when we do link listed operation [24:24] read-write Disable 0:M0 will be used to fetch desc 0 Enable 1:M1 will be used to fetch desc 1 SRC_ADDR_CONTIGUOUS Indicates Address is contiguous from previous [25:25] read-write Disable None 0 Enable 1:Indicates Address is contiguous from previous 1 DEST_ADDR_CONTIGUOUS Indicates Address is contiguous from previous [26:26] read-write Disable None 0 Enable 1:Indicates Address is contiguous from previous 1 RETRY_ON_ERROR When this bit is set, if we recieve HRESPERR, We will retry the DMA for that channel. [27:27] read-write LINK_INTERRUPT This bit is set in link list descriptor.Hard ware will send an interrupt when the DMA transfer is done for the corresponding link list address [28:28] read-write SRC_FIFO_MODE If set to 1; source address will not be incremented(means fifo mode for source) [29:29] read-write DEST_FIFO_MODE If set to 1; destination address will not be incremented(means fifo mode for destination) [30:30] read-write RESERVED1 Reserved1 [31:31] read-only MISC_CHANNEL_CTRL_REG_CHNL__n_ Misc Channel Control Register for channel _n_ 0x10 32 read-write 0x00000000 0xFFFFFFFF AHB_BURST_SIZE Burst size [2:0] read-write 0 7 DEST_DATA_BURST Burst writes in beats to destination.(000000-64 beats .....111111-63 beats) [8:3] read-write oneToSet 0 63 SRC_DATA_BURST Burst writes in beats from source(000000-64 beats .....111111-63 beats) [14:9] read-write oneToSet 0 63 DEST_CHNL_ID This is the destination channel Id to which the data is sent. Must be set up prior to DMA_CHANNEL_ENABLE [20:15] read-write SRC_CHNL_ID This is the source channel Id, from which the data is fetched. must be set up prior to DMA_CHANNEL_ENABLE [26:21] read-write DMA_PROT Protection level to go with the data. It will be concatenated with 1 b1 as there will be no opcode fetching and directly assign to hprot in AHB interface [29:27] read-write MEM_FILL_ENABLE Enable for memory filling with either 1s or 0s. [30:30] read-write Disable Disabled 0 Enable Enabled the memory filling 1 MEM_ONE_FILL Select for memory filling with either 1s or 0s. [31:31] read-write Disable Memory fill with 0s. 0 Enable Memory fill with 1s. 1 FIFO_CONFIG_REG_CHNL__n_ FIFO Configuration Register for channel _n_ 0x14 32 read-write 0x0000 0xFFFF FIFO_STRT_ADDR Starting row address of channel [5:0] read-write FIFO_SIZE Channel size [11:6] read-write RESERVED1 Reserved1 [31:12] read-only PRIORITY_LEVEL_REG_CHNL__n_ Priority Register for channel _n_ 0x18 32 read-write 0x0 0xF PRIORITY_CH Set a value between 2 b00 to 2 b11. The channel having highest number is the highest priority channel. [1:0] read-write 00 priority level 0 0 01 priority level 1 1 10 priority level 2 2 11 priority level 3 3 RESERVED1 Reserved1 [31:2] read-only HWRNG 1.0 Random numbers generated are 16-bit random numbers and are generated using either the True random number generator or the Pseudo random number generator. HWRNG 0x45090000 32 read-write 0x00 0x8 registers HWRNG_CTRL_REG Random Number Generator Control Register 0x00 32 read-write 0x00000000 0xFFFFFFFF HWRNG_RNG_ST This bit is used to start the true number generation. [0:0] read-write Enable Enables true random number generation 1 Disable Disables true random number generation 0 HWRNG_PRBS_ST This bit is used to start the pseudo random number generation [1:1] read-write Enable Enables pseudo random number generation 1 Disable Disables pseudo random number generation 0 SOFT_RESET This bit is used to start the pseudo random number generation [2:2] read-write Enable Reset the scrambled data 1 Disable Not resetted 0 RESERVED1 RESERVED1 [31:3] read-only HWRNG_RAND_NUM_REG Hardware Random Number Register 0x04 32 read-only 0x00000000 0xFFFFFFFF HWRNG_RAND_NUM Generated random number can be read from this register. [31:0] read-only ULP_TIMERS 1.0 TIMER can be used to generate various timing events for the software ULP_TIMERS 0x24042000 32 read-write 0 0xA0 registers TIMER0 2 TIMER1 3 TIMER2 4 TIMER3 5 4 0x8 MATCH_CTRLn MATCH Control registers (0-3) 0x0000 MCUULP_TMR_n__MATCH Timer Match Register 0x00 32 read-write 0xFFFF 0xFFFF TMR_MATCH This bits are used to program the lower significant 16-bits of timer time out value in millisecond or number of system clocks [31:0] read-write MCUULP_TMR_n__CNTRL Timer Control Register 0x04 32 read-write 0x0000 0xFF TMR_START This Bit are Used to start the timer timer gets reset upon setting this bit [0:0] write-only None Timer start 1 TMR_INTR_CLR This Bit are Used to clear the timer [1:1] write-only Clear_Interrupt Clear interrupt 1 TMR_INTR_ENABLE This Bit are Used to enable the time out interrupt [2:2] read-write Enable Interrupt enable 1 Disable Interrupt disable 0 TMR_TYPE This Bit are Used to select the type of timer [4:3] read-write 256_MICRO_SECOND 256 Micro second mode 2 ONE_MICRO_SECOND 1 Micro second mode 1 COUNT_DOWN_TIMER Count down timer 0 TMR_MODE This Bit are Used to select the mode working of timer [5:5] read-write Enable Periodic timer 1 Disable One shot timer 0 TMR_STOP This Bit are Used to stop the timer [6:6] write-only None Stops the timer 1 COUNTER_UP For reading/tracking counter in up counting this bit has to be set [7:7] read-write RESERVED1 reserved1 [31:8] read-write MCUULP_TMR_INTR_STAT Timer Status Register 0x80 32 read-write 0x0000 0xFFFF TMR0_INTR_STATUS This bit indicates status of the interrupt generated by timer 0 [0:0] read-write Interrupt_Present Interrupt present 1 Interrupt_Absent No Interrupt present 0 TMR1_INTR_STATUS This bit indicates status of the interrupt generated by timer 1 [1:1] read-write Interrupt_Present Interrupt present 1 Interrupt_Absent No Interrupt present 0 TMR2_INTR_STATUS This bit indicates status of the interrupt generated by timer 2 [2:2] read-write Interrupt_Present Interrupt present 1 Interrupt_Absent No Interrupt present 0 TMR3_INTR_STATUS This bit indicates status of the interrupt generated by timer 3 [3:3] read-write Interrupt_Present Interrupt present 1 Interrupt_Absent No Interrupt present 0 RESERVED1 reserved1 [31:4] read-only MCUULP_TMR_US_PERIOD_INT Timer micro second period Integral Part Register 0x84 32 read-write 0xFFFF 0xFFFF TMR_US_PERIOD_INT This bits are used to program the integer part of number of clock cycles per microseconds of the system clock used [15:0] read-write RESERVED1 reserved1 [31:16] read-only MCUULP_TMR_US_PERIOD_FRAC Timer microsecond period Fractional Part Register 0x88 32 read-write 0xFF 0xFF TMR_US_PERIOD_FRAC This bits are used to program the fractional part of number of clock cycles per microseconds of the system clock used [7:0] read-write RESERVED1 reserved1 [31:8] read-only MCUULP_TMR_MS_PERIOD_INT Timer 256 microsecond period Integral Part Register 0x8C 32 read-write 0xFFFF 0xFFFF TMR_MS_PERIOD_INT This bits are used to program the integer part of number of clock cycles per 256 microseconds of the system clock used [15:0] read-write RESERVED1 reserved1 [31:16] read-only MCUULP_TMR_MS_PERIOD_FRAC Timer 256 microsecond period Fractional Part Register 0x90 32 read-write 0xFF 0xFF TMR_MS_PERIOD_FRAC This bits are used to program the fractional part of number of clock cycles per 256 microseconds of the system clock used [7:0] read-write RESERVED1 reserved1 [31:8] read-only MCUULP_TMR_ACTIVE_STATUS Timer Active Status Register 0x9C 32 read-only 0x00000000 0x00000000 TIMER_ACTIVE Timer active status for each timer. LSB bit specifies the status for 0th timer and so on. [3:0] read-only Timer_Active Interrupt present 1 Timer_Inative No Interrupt present 0 RESERVED1 reserved1 [31:4] read-only QEI 1.0 The Quadrature Encoder Interface (QEI) module provides the interface to incremental encoders for obtaining mechanical position data QEI 0x47060000 32 read-write 0x00 0x50 registers QEI 49 QEI_STATUS_REG Quadrature Encoder status register 0x00 32 read-only 0x00000000 0xFFFF QEI_INDEX This is a direct value from the position signal generator [0:0] read-only QEI_POSITION_B This is a direct value from the position signal generator.Value refers to the signal Position_B from the generator. [1:1] read-only QEI_POSITION_A This is a direct value from the position signal generator.Value refers to the signal Position_A from the generator. [2:2] read-only POSITION_CNTR_ERR Count Error Status Flag bit [3:3] read-only POSITION_CNTR_DIRECTION Position Counter Direction Status bit [4:4] read-only Disable Position counter direction is negative (-) 0 Enable Position counter direction is positive (+) 1 RESERVED1 Reserved1 [31:5] read-only QEI_CTRL_REG_SET Quadrature Encoder control set register 0x04 32 read-write 0x00000000 0xFFFF QEI_SFT_RST Quadrature encoder soft reset. It is self reset signal. [0:0] read-only QEI_SWAP_PHASE_AB Phase A and Phase B Input Swap Select bit [1:1] read-write Disable Phase A and Phase B inputs are not swapped 0 Enable Phase A and Phase B inputs are swapped 1 POS_CNT_RST_WITH_INDEX_EN Phase A and Phase B Input Swap Select bit [2:2] read-write Disable position counter is getting reset after reaching max count, which is mentioned in position_max_cnt 0 Enable position counter is getting reset for every index pulse 1 RESERVED1 Reserved1 [3:3] read-write POS_CNT_DIRECTION_CTRL NONE [4:4] read-write Disable position B pin defines the direction of position counter 0 Enable pos_cnt_dir_frm_reg defines the position counter direction 1 POS_CNT_DIR_FRM_REG Position Counter Direction indication from user [5:5] read-write Disable Position counter direction is negative (-) 0 Enable Position counter direction is positive (+) 1 RESERVED2 Reserved2 [6:6] read-write RESERVED3 Reserved3 [7:7] read-write INDEX_CNT_RST_EN Index count reset enable [8:8] read-write Disable NONE 0 Enable index counter is going to reset after reaching max count, which is mentioned in qei_index_max_cnt register. 1 DIGITAL_FILTER_BYPASS NONE [9:9] read-write Disable digital filter is in-path for all input signals 0 Enable digital filter is bypassed for all input signals (position A, position B and Index) 1 TIMER_MODE NONE [10:10] read-write Disable Quadrature encoder mode 0 Enable timer mode. In this mode, decoded timer pulse and direction are taken from position A and position B pins respectively. 1 START_VELOCITY_CNTR Starting the velocity counter. It is self reset bit. [11:11] read-write QEI_STOP_IN_IDLE NONE [12:12] read-write Disable QEI position status counter is working as 32 bit counter. 0 Enable QEI position status counter is working as 16 bit counter 1 QEI_POS_CNT_16_BIT_MODE Qei position counter 16 bit mode enable [13:13] read-write Disable No effect 0 Enable QEI position status counter will be working as a 16 bit counter 1 POS_CNT_RST 1=position counter is going to reset [14:14] read-write INDEX_CNT_RST 1= index counter is going to reset. [15:15] read-write RESERVED4 Reserved4 [31:16] read-write QEI_CTRL_REG_RESET Quadrature Encoder control reset register 0x08 32 read-write 0x00000000 0xFFFF QEI_SFT_RST Quadrature encoder soft reset. It is self reset signal [0:0] read-only QEI_SWAP_PHASE_AB Phase A and Phase B Input Swap Select bit [1:1] read-write Disable Phase A and Phase B inputs are not swapped 0 Enable Phase A and Phase B inputs are swapped 1 POS_CNT_RST_WITH_INDEX_EN Phase A and Phase B Input Swap Select bit [2:2] read-write Disable position counter is getting reset after reaching max count, which is mentioned in position_max_cnt 0 Enable position counter is getting reset for every index pulse 1 RESERVED1 Reserved1 [3:3] read-write POS_CNT_DIRECTION_CTRL NONE [4:4] read-write Disable position B pin defines the direction of position counter 0 Enable pos_cnt_dir_frm_reg defines the position counter direction 1 POS_CNT_DIR_FRM_REG Position Counter Direction indication from user [5:5] read-write Disable Position counter direction is negative (-) 0 Enable Position counter direction is positive (+) 1 RESERVED2 Reserved2 [6:6] read-write RESERVED3 Reserved3 [7:7] read-write INDEX_CNT_RST_EN NONE [8:8] read-write Disable NONE 0 Enable index counter is going to reset after reaching max count, which is mentioned in qei_index_max_cnt register. 1 DIGITAL_FILTER_BYPASS NONE [9:9] read-write Disable digital filter is in-path for all input signals 0 Enable digital filter is bypassed for all input signals (position A, position B and Index) 1 TIMER_MODE NONE [10:10] read-write Disable Quadrature encoder mode 0 Enable timer mode. In this mode, decoded timer pulse and direction are taken from position A and position B pins respectively 1 START_VELOCITY_CNTR Starting the velocity counter. It is self reset bit. [11:11] read-write QEI_STOP_IN_IDLE NONE [12:12] read-write Disable QEI position status counter is working as 32 bit counter. 0 Enable QEI position status counter is working as 16 bit counter 1 QEI_POS_CNT_16_BIT_MODE Qei position counter 16 bit mode enable [13:13] read-write Disable No effect 0 Enable QEI position status counter will be working as a 16 bit counter 1 POS_CNT_RST 1=position counter is going to reset [14:14] read-write INDEX_CNT_RST 1= index counter is going to reset. [15:15] read-write RESERVED4 Reserved4 [31:16] read-write QEI_CNTLR_INIT_REG Quadrature Encoder initialization register 0x0C 32 read-write 0x00000000 0xFFFF QEI_ENCODING_MODE NONE [1:0] read-write 00 1x mode 0 01 2x mode 1 10 4x mode 2 11 NONE 3 RESERVED1 Reserved1 [3:2] read-write INDEX_MATCH_VALUE These bits allow user to specify the state of position A and B during index pulse generation. [5:4] read-write DF_CLK_DIVIDE_SLT Digital Filter Clock Divide Select bits [9:6] read-write 0000 0000 = [1:1] Clock divide for Index, position A and B 0 0001 0001 = [1:2] Clock divide for Index, position A and B 1 0010 0010 = [1:4] Clock divide for Index, position A and B 2 0011 0011 = [1:8] Clock divide for Index, position A and B 3 0100 0100 = [1:16] Clock divide for Index, position A and B 4 0101 0101 = [1:32] Clock divide for Index, position A and B 5 0110 0110 = [1:6]4 Clock divide for Index, position A and B 6 0111 0111 = [1:12]8 Clock divide for Index, position A and B 7 1000 1000 = [1:25]6 Clock divide for Index, position A and B 8 1001 1001 = [1:5]12 Clock divide for Index, position A and B 9 1010 1010 = [1:10]24 Clock divide for Index, position A and B 10 UNIDIRECTIONAL_VELOCITY Uni directional velocity enable. [10:10] read-write Disable NONE 0 Enable 1 means direction change in position counter resets velocity counter 1 UNIDIRECTIONAL_INDEX Uni directional index enable. [11:11] read-write Disable NONE 0 Enable 1 means direction change in position counter resets index counter 1 INDEX_CNT_INIT Index counter initial value in unidirectional index enable mode. [12:12] read-write RESERVED2 Reserved2 [31:13] read-write QEI_INDEX_CNT_REG Quadrature Encoder index counter register 0x10 32 read-write 0x00000000 0xFFFF QEI_INDEX_CNT Index counter value.User can initialize/change the index counter using this register [15:0] read-write QEI_INDEX_CNT_WR_VALUE User can initialize/change the index counter using this register. [31:16] read-write QEI_INDEX_MAX_CNT_REG Quadrature Encoder maximum index counter value register 0x14 32 read-write 0xFFFF 0xFFFF QEI_INDEX_MAX_CNT This is a maximum count value that is allowed to increment in the index counter. If index counter reaches this value, will get reset to zero [15:0] read-write RESERVED1 Reserved1 [31:16] read-write QEI_POSITION_CNT_REG Quadrature Encoder maximum position counter value register 0x18 32 read-write 0x0000FFFF 0xFFFFFFFF QEI_POSITION_CNT_WR_VALUE_L This is a maximum count value that is allowed to increment in the position counter. [15:0] read-write QEI_POSITION_CNT_WR_VALUE_H This is a maximum count value that is allowed to increment in the position counter. [31:16] read-write QEI_POSITION_MAX_CNT_LSW_REG Quadrature Encoder maximum position counter value register 0x20 32 read-write 0x0000FFFF 0xFFFFFFFF QEI_POSITION_MAX_CNT_L This is a maximum count value that is allowed to increment in the position counter. [15:0] read-write QEI_POSITION_MAX_CNT_H This is a maximum count value that is allowed to increment in the position counter. [31:16] read-write QEI_INTR_STS_REG Quadrature Encoder interrupt status register 0x28 32 read-only 0x0000FFFF 0x1F QEI_POSITION_CNT_RESET_INTR_LEV This is raised when the position counter reaches it's extremes [0:0] read-only QEI_INDEX_CNT_MATCH_INTR_LEV This is raised when index counter reaches max value loaded in to index_max_cnt register. [1:1] read-only POSITION_CNTR_ERR_INTR_LEV Whenever number of possible positions are mismatched with actual positions are received between two index pulses this will raised [2:2] read-only VELOCITY_LESS_THAN_INTR_LEV When velocity count is less than the value given in velocity_value_to_compare register, interrupt is raised [3:3] read-only QEI_POSITION_CNT_MATCH_INTR_LEV This is raised when the position counter reaches position match value, which is programmable. [4:4] read-only QEI_VELOCITY_COMPUTATION_OVER_INTR_LEV When velocity count is computed for given delta time, than interrupt is raised. [5:5] read-only RESERVED1 Reserved1 [31:6] read-only QEI_INTR_ACK_REG Quadrature Encoder interrupt acknowledge register 0x2C 32 read-write 0x00000000 0x1F QEI_POSITION_CNT_RESET_INTR_LEV Qei_position_cnt_reset_intr_ack [0:0] read-write Disable No effect. 0 Enable Qei position cnt reset intr will be cleared. 1 QEI_INDEX_CNT_MATCH_INTR_LEV NONE [1:1] read-write Disable No effect. 0 Enable Qei index cnt match intr will be cleared. 1 POSITION_CNTR_ERR_INTR_LEV Position_cntr_err_intr_ack [2:2] read-write Disable No effect. 0 Enable Position cntr err intr will be cleared. 1 VELOCITY_LESS_THAN_INTR_LEV Velocity_less_than_intr_ack [3:3] read-write Disable No effect. 0 Enable Velocity less than intr will be cleared 1 QEI_POSITION_CNT_MATCH_INTR_LEV Qei_position_cnt_match_intr_ack [4:4] read-write Disable No effect. 0 Enable Qei position cnt match intr will be cleared. 1 VELOCITY_COMPUTATION_OVER_INTR_LEV Velocity_computation_over_intr_ack [5:5] read-write Disable No effect. 0 Enable Velocity computation is over intr will be cleared. 1 RESERVED1 Reserved1 [31:6] read-write QEI_INTR_MASK_REG Quadrature Encoder interrupt mask register 0x30 32 read-write 0x00000000 0x1F QEI_POSITION_CNT_RESET_INTR_MASK Qei_position_cnt_reset_intr_mask [0:0] read-write Disable If read : Qei position cnt reset intr is not given on qei_intr pin. If write: No effect 0 Enable If read : Qei position cnt reset intr is given on qei_intr pin If write: Qei position cnt reset intr will not be given on qei_intr pin 1 QEI_INDEX_CNT_MATCH_INTR_MASK Qei_index_cnt_match_intr_mask [1:1] read-write Disable If read : Qei index cnt match intr is not given on qei_intr pin If write: No effect 0 Enable If read : Qei index cnt match intr is given on qei_intr pin. If write: Qei index cnt match intr will not be given on qei_intr pin. 1 POSITION_CNTR_ERR_INTR_MASK Position_cntr_err_intr_mask [2:2] read-write Disable If read : Position cntr err intr is not given on qei_intr pin. If write: No effect 0 Enable If read : Position cntr err intr is given on qei_intr pin. If write: Position cntr err intr will not be given on qei_intr pin 1 VELOCITY_LESS_THAN_INTR_MASK Velocity_less_than_intr_mask [3:3] read-write Disable If read : Velocity less than intr is not given on qei_intr pin. If write: No effect 0 Enable If read :Velocity less than intr is given on qei_intr pin. If write: Velocity less than intr will not be given on qei_intr pin. 1 QEI_POSITION_CNT_MATCH_INTR_MASK Qei_position_cnt_match_intr_mask [4:4] read-write Disable If read :Qei position cnt match intr is given on qei_intr pin If write: No effect 0 Enable If read :Qei position cnt match intr is given on qei_intr pin. If write:Qei position cnt match intr will not be given on qei_intr pin 1 VELOCITY_COMPUTATION_OVER_INTR_MASK Velocity_computation_over_intr_mask [5:5] read-write Disable If read :Qei position cnt match intr is given on qei_intr pin If write: No effect 0 Enable If read :Qei position cnt match intr is given on qei_intr pin. If write:Qei position cnt match intr will not be given on qei_intr pin 1 RESERVED1 Reserved1 [31:6] read-write QEI_INTR_UNMASK_REg Quadrature Encoder interrupt unmask register 0x34 32 read-write 0x00000000 0x1F QEI_POSITION_CNT_RESET_INTR_UNMASK Qei_position_cnt_reset_intr_unmask [0:0] read-write Disable If read : Qei position cnt reset intr is not given on qei_intr pin. If write: No effect 0 Enable If read : Qei position cnt reset intr is given on qei_intr pin If write: Qei position cnt reset intr will not be given on qei_intr pin 1 QEI_INDEX_CNT_MATCH_INTR_UNMASK Qei_index_cnt_match_intr_unmask [1:1] read-write Disable If read : Qei index cnt match intr is not given on qei_intr pin If write: No effect 0 Enable If read : Qei index cnt match intr is given on qei_intr pin. If write: Qei index cnt match intr will not be given on qei_intr pin. 1 POSITION_CNTR_ERR_INTR_UNMASK Position_cntr_err_intr_unmask [2:2] read-write Disable If read : Position cntr err intr is not given on qei_intr pin. If write: No effect 0 Enable If read : Position cntr err intr is given on qei_intr pin. If write: Position cntr err intr will not be given on qei_intr pin 1 VELOCITY_LESS_THAN_INTR_UNMASK Velocity_less_than_intr_unmask [3:3] read-write Disable If read : Velocity less than intr is not given on qei_intr pin. If write: No effect 0 Enable If read :Velocity less than intr is given on qei_intr pin. If write: Velocity less than intr will not be given on qei_intr pin. 1 QEI_POSITION_CNT_MATCH_INTR_UNMASK Qei_position_cnt_match_intr_unmask [4:4] read-write Disable If read :Qei position cnt match intr is given on qei_intr pin If write: No effect 0 Enable If read :Qei position cnt match intr is given on qei_intr pin. If write:Qei position cnt match intr will not be given on qei_intr pin 1 RESERVED1 Reserved1 [31:5] read-write QEI_CLK_FREQ_REG Quadrature Encoder clock frequency register 0x38 32 read-write 0x00000027 0xFF QEI_CLK_FREQ Indication of clock frequency on which QEI controller is running. [8:0] read-write RESERVED1 Reserved1 [31:9] read-write QEI_DELTA_TIME_REG Quadrature Delta time register 0x3C 32 read-write 0x000003E7 0xFFFFF DELTA_TIME_FOR_VELOCITY Delta time LSW to compute velocity [19:0] read-write RESERVED1 Reserved1 [31:20] read-write QEI_VELOCITY_REG Quadrature velocity register 0x44 32 read-write 0x00000000 0xFFFFFFFF VELOCITY_VALUE_TO_COMPARE_L For read operation :It is the velocity count to compare using TA firmware For write operation :It is the velocity value to compare with velocity count [15:0] read-write VELOCITY_VALUE_TO_COMPARE_H For read operation :It is the velocity count to compare using TA firmware For write operation :It is the velocity value to compare with velocity count [31:16] read-write QEI_POSITION_MATCH_REG Quadrature position match register 0x4C 32 read-write 0x00000000 0xFFFFFFFF POSTION_MATCH_VALUE_L Position match value to compare the position counter. [15:0] read-write POSTION_MATCH_VALUE_H Position match value to compare the position counter. [31:16] read-write USART0 1.0 Universal Asynchronous Receiver/Transmitter is for serial communication with peripherals, modems and datasets UART_USRT 0x44000100 32 read-write 0 0x100 registers USART0 38 USART_DLL Divisor Latch Low 0x00 32 read-write 0x00000000 0xFF DLL Lower 8-bits of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. [7:0] read-write RESERVED1 reserved1 [31:8] read-only USART_THR Transmit Holding Register DLL 0x00 32 write-only 0x00000000 0xFF THR Data to be transmitted on serial output port [7:0] write-only RESERVED1 reserved1 [31:8] read-only USART_RBR Receive Buffer Register DLL 0x00 32 read-only 0x00000000 0xFF RBR Receive Buffer Field [7:0] read-only RESERVED1 reserved1 [31:8] read-only USART_IER Interrupt Enable Register 0x04 32 read-write 0x00000000 0x8F ERBFI Enable Received Data Available Interrupt [0:0] read-write Disable Received Data Available Interrupt is disabled 0 Enable Received Data Available Interrupt is enabled 1 ETBEI Enable Transmit Holding Register Empty Interrupt [1:1] read-write Disable Transmit Holding Register Empty Interrupt is disabled 0 Enable Transmit Holding Register Empty Interrupt is enabled 1 ELSI Enable Receiver Line Status Interrupt [2:2] read-write Disable Receiver Line Status Interrupt is disabled 0 Enable Receiver Line Status Interrupt is enabled 1 EDSSI Enable Modem Status Interrupt [3:3] read-write Disable Modem Status Interrupt is disabled 0 Enable Modem Status Interrupt is enabled 1 RESERVED1 reserved1 [6:4] read-only PTIME Programmable THRE Interrupt Mode Enable [7:7] read-write Disable generation of THRE Interrupt is disabled 0 Enable generation of THRE Interrupt is enabled 1 RESERVED2 reserved2 [31:8] read-only USART_DLH Divisor Latch High IER 0x04 32 read-write 0x00000000 0xFF DLH Upper 8-bits of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART [7:0] read-write RESERVED1 reserved1 [31:8] read-only USART_FCR FIFO Control Register 0x08 32 write-only 0x00000000 0xFF FIFOE This enables/disables the transmit (XMIT) and receive (RCVR) FIFOs [0:0] write-only RFIFOR RCVR FIFO Reset [1:1] write-only XFIFOR XMIT FIFO Reset [2:2] write-only DMAM DMA signalling mode [3:3] write-only Mode0 DMA Signalling mode0 0 Mode1 DMA Signalling mode1 1 TET TX Empty Trigger [5:4] write-only FIFO_EMPTY FIFO Empty 0 FIFO_2_CHARACTER 2 characters in the FIFO 1 FIFO_1_BY_4_CHARACTER FIFO 1/4 full 2 FIFO_1_BY_2_CHARACTER FIFO 1/2 full 3 RT This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt is generated [7:6] write-only FIFO_1_CHARACTER 1 character in the FIFO 0 FIFO_1_BY_4_CHARACTER FIFO 1/4 full 1 FIFO_1_BY_2_CHARACTER FIFO 1/2 full 2 FIFO_LESS_THAN_2_CHARACTER FIFO 2 less than full 3 RESERVED1 reserved1 [31:8] write-only USART_IIR Interrupt Identity Register 0x08 32 read-only 0x00000001 IID Interrupt ID [3:0] read-only 0000 modem status pending pending interrupt 0 0001 This field indicates no interrupt pending status 1 0010 Transmit Holding Register Empty pending interrupt 2 0100 Received Data Available pending interrupt 4 0110 Receive line status pending interrupt 6 0111 Busy detect pending interrupt 7 1100 Character Timeout pending interrupt 12 RESERVED1 reserved1 [5:4] read-only FIFOSE This is used to indicate whether the FIFOs are enabled or disabled. [7:6] read-only Disable FIFO is disabled 0 Enable FIFO is enabled 1 RESERVED2 reserved2 [31:8] read-only USART_LCR Line Control Register 0x0C 32 read-write 0x00000000 0xFF DLS Data Length Select,This is used to select the number of data bits per character that the peripheral transmits and receives [1:0] read-write 5_BITS_PER_CHARACTER 5 bits per character 0 6_BITS_PER_CHARACTER 6 bits per character 1 7_BITS_PER_CHARACTER 7 bits per character 2 8_BITS_PER_CHARACTER 8 bits per character 3 STOP This is used to select the number of stop bits per character that the peripheral transmits and receives [2:2] read-write 1_STOP_BIT_PER_CHARACTER 1 stop bit per character 0 1_5_OR_2_STOPS_BIT_PER_CHARACTER 1.5 or 2 stop bits per character 1 PEN This bit is used to enable and disable parity generation and detection in transmitted and received serial character [3:3] read-write Disable Parity disabled 0 Enable Parity Enabled 1 EPS This is used to select between even and odd parity [4:4] read-write Set_to_0 An odd number of logic 1s is transmitted or checked 0 Set_to_1 An even number of logic 1s is transmitted or checked 1 STICK_PARITY This bit is used to force parity value [5:5] read-write LOGIC0 When PEN, EPS, and Stick Parity are set to 1, the parity bit is transmitted and checked as logic 0 0 LOGIC1 If PEN and Stick Parity are set to 1 and EPS is a logic 0,then parity bit is transmitted and checked as a logic 1 1 BC This is used to cause a break condition to be transmitted to the receiving device [6:6] read-write SERIAL_OUTPUT_SPACING_STATE If set to 1, the serial output is forced to the spacing (logic 0) state 1 DLAB This bit is used to enable reading and writing of the Divisor Latch register to set the baud rate of the UART [7:7] read-write write UNSET This bit must be cleared after initial baud rate set up 0 RESERVED1 reserved1 [31:8] read-only USART_MCR Modem Control Register 0x10 32 read-write 0x00000000 0x7F DTR This is used to directly control the Data Terminal Ready (dtr_n) output [0:0] read-write DTR_LOGIC1 dtr_n de-asserted (logic 1) 0 DTR_LOGIC0 dtr_n asserted (logic 0) 1 RTS This is used to directly control the Request to Send (rts_n) output [1:1] read-write OUT1 This is used to directly control the user-designated Output1 (out1_n) output [2:2] read-write OUT1_LOGIC1 out1_n de-asserted (logic 1) 0 OUT1_LOGIC0 out1_n asserted (logic 0) 1 OUT2 This is used to directly control the user-designated Output2 (out2_n) output [3:3] read-write OUT2_LOGIC1 out2_n de-asserted (logic 1) 0 OUT2_LOGIC0 out2_n asserted (logic 0) 1 LB This is used to put the UART into a diagnostic mode for test purposes [4:4] read-write AFCE This is used to directly control the user-designated Output2 (out2_n) output [5:5] read-write Disabled Auto Flow Control Mode disabled 0 Enabled Auto Flow Control Mode enabled 1 SIRE This is used to enable/disable the IrDA SIR Mode features [6:6] read-write Disabled IrDA SIR Mode disabled 0 Enabled IrDA SIR Mode enabled 1 RESERVED1 reserved1 [31:7] read-only USART_LSR Line Status Register 0x14 32 read-only 0x00000060 DR This is used to indicate that the receiver contains at least one character in the RBR or the receiver FIFO [0:0] read-only read Disabled No data Ready 0 Enabled Data Ready 1 OE This is used to indicate the occurrence of an overrun error [1:1] read-only read Disabled no overrun error 0 Enabled overrun error 1 PE This is used to indicate the occurrence of a parity error in the receiver if the Parity Enable (PEN) bit (LCR[3]) is set [2:2] read-only read Disabled no parity error 0 Enabled parity error 1 FE This is used to indicate the occurrence of a framing error in the receiver [3:3] read-only read Disabled no framing error 0 Enabled framing error 1 BI This is used to indicate the detection of a break sequence on the serial input data [4:4] read-only THRE Transmit Holding Register Empty bit [5:5] read-only TEMT Transmitter Empty bit [6:6] read-only RFE This is used to indicate if there is at least one parity error,framing error, or break indication in the FIFO [7:7] read-only read Disabled no error in RX FIFO 0 Enabled error in RX FIFO 1 RESERVED1 reserved1 [31:8] read-only USART_MSR Modem Status Register 0x18 32 read-only 0x00000000 0xFF DCTS This is used to indicate that the modem control line cts_n has changed since the last time the MSR was read [0:0] read-only change_on_cts_n read No_Change no change on cts_n since last read of MSR 0 Change change on cts_n since last read of MSR 1 DDSR This is used to indicate that the modem control line dsr_n has changed since the last time the MSR was read [1:1] read-only Change_on_dsr_n read No_Change no change on dsr_n since last read of MSR 0 Change change on dsr_n since last read of MSR 1 TERI This is used to indicate that a change on the input ri_n(from an active-low to an inactive-high state)has occurred since the last time the MSR was read [2:2] read-only Change_on_ri_n read No_Change no change on ri_n since last read of MSR 0 Change change on ri_n since last read of MSR 1 DDCD This is used to indicate that the modem control line dcd_n has changed since the last time the MSR was read [3:3] read-only Change_on_dcd_n read No_Change no change on dcd_n since last read of MSR 0 Change change on dcd_n since last read of MSR 1 CTS This is used to indicate the current state of the modem control line cts_n [4:4] read-only cts_n_Input read Deasserted cts_n input is de-asserted (logic 1) 0 Asserted cts_n input is asserted (logic 0) 1 DSR This is used to indicate the current state of the modem control line dsr_n [5:5] read-only dsr_n_Input read Deasserted dsr_n input is de-asserted (logic 1) 0 Asserted dsr_n input is asserted (logic 0) 1 RI This is used to indicate the current state of the modem control line ri_n [6:6] read-only ri_n_input read Deasserted ri_n input is de-asserted (logic 1) 0 Asserted ri_n input is asserted (logic 0) 1 DCD This is used to indicate the current state of the modem control line dcd_n [7:7] read-only dcd_n_input read Deasserted dcd_n input is de-asserted (logic 1) 0 Asserted dcd_n input is asserted (logic 0) 1 RESERVED1 reserved1 [31:8] read-only USART_SCR Scratch pad Register 0x1C 32 read-write 0x00000000 0xFF SCRATCH_PAD This register is for programmers to use as a temporary storage space. It has no defined purpose [7:0] read-write RESERVED1 reserved1 [31:8] read-only USART_HDEN Hardware Enable register 0x40 32 read-write 0x00000000 0xFF FULL_DUPLEX_MODE none [0:0] read-write Full_Duplex_Mode ENABLE Full duplex mode enable 1 DISABLE Full duplex mode disable 0 TX_MODE_RX_MODE This signal is valid when full_duplex_mode is disabled [1:1] read-write tx_mode tx_mode 0 rx_mode rx_mode 1 RESERVED1 reserved1 [31:2] read-only USART_SMCR Control register 0x58 32 read-write 0x00000000 0xFF SYNC_MODE Sync Mode [0:0] read-write SYNC_MODE Sync mode 1 NON_SYNC_MODE Non-Sync mode 0 MST_MODE Master Mode [1:1] read-write MST_MODE MST mode 1 NON_MST_MODE Non-MST mode 0 RESERVED1 reserved1 [3:2] read-only CONTI_CLK_MODE none [4:4] read-write CONTINUOUS_CLK_MODE Continuous clock mode 1 NON_CONTINUOUS_CLK_MODE Non-continuous clock mode 0 START_STOP_EN start stop enable [5:5] read-write ENABLE_START_STOP Enable start stop 1 DISABLE_START_STOP Disable start stop 0 RESERVED2 reserved2 [31:6] read-only USART_FAR FIFO Access Register 0x70 32 read-write 0x00000000 0xFF FIFO_Access Enable fifo access mode [0:0] read-write RESERVED1 reserved1 [31:1] read-only USART_TFR Transmit FIFO Read Register 0x74 32 read-only 0x00000000 TX_FIFO_RD Transmit FIFO Read [7:0] read-only RESERVED1 reserved1 [31:8] read-only USART_RFW Receive FIFO Write Register 0x78 32 read-write 0x00000000 RFWD Receive FIFO Write Data [7:0] write-only RFPE Receive FIFO Parity Error [8:8] write-only RFFE Receive FIFO Framing Error [9:9] write-only RESERVED1 reserved1 [31:10] read-only USART_USR UART Status Register 0x7C 32 read-only 0x00000006 BUSY Indicates that a serial transfer is in progress [0:0] read-only read Disabled UART is idle or inactive 0 Enabled UART is busy (actively transferring data) 1 TFNF To Indicate that the transmit FIFO is not full [1:1] read-only read Disabled Transmit FIFO is full 0 Enabled Transmit FIFO is not full 1 TFE To Indicate that the transmit FIFO is completely empty [2:2] read-only read Disabled Transmit FIFO is not empty 0 Enabled Transmit FIFO is empty 1 RFNE To Indicate that the receive FIFO contains one or more entries [3:3] read-only read Disabled Receive FIFO is empty 0 Enabled Receive FIFO is not empty 1 RFF To Indicate that the receive FIFO is completely full [4:4] read-only read Disabled Receive FIFO not full 0 Enabled Receive FIFO Full 1 RESERVED1 reserved1 [31:5] read-only USART_TFL Transmit FIFO Level 0x80 32 read-only 0x00000000 Transmit_FIFO_Level This is indicates the number of data entries in the transmit FIFO. [29:0] read-only RESERVED1 reserved1 [31:30] read-only USART_RFL Receive FIFO Level 0x84 32 read-only 0x00000000 Recieve_FIFO_Level This is indicates the number of data entries in the receive FIFO. [29:0] read-only RESERVED1 reserved1 [31:30] read-only USART_SRR Software Reset Register 0x88 32 write-only 0x00000000 UR UART Reset [0:0] write-only RFR RCVR FIFO Reset [1:1] write-only XFR XMIT FIFO Reset [2:2] write-only RESERVED1 reserved1 [31:3] read-only USART_SRTS Shadow Request to Send 0x8C 32 read-write 0x00000000 0xF SRTS Shadow Request to Send. [0:0] read-write RESERVED1 reserved1 [31:1] read-only USART_SBCR Shadow Break Control Register 0x90 32 read-write 0x00000000 0xF SBCR Shadow Break Control Bit [0:0] read-write RESERVED1 reserved1 [31:1] read-only USART_SDMAM Shadow DMA Mode 0x94 32 read-write 0x00000000 0xF SDMAM Shadow DMA Mode [0:0] read-write MODE0 mode 0 0 MODE1 mode 1 1 RESERVED1 reserved1 [31:1] read-only USART_SFE Shadow FIFO Enable 0x98 32 read-write 0x00000000 0xF SFE Shadow FIFO Enable [0:0] read-write RESERVED1 reserved1 [31:1] read-only USART_SRT Shadow RCVR Trigger 0x9C 32 read-write 0x00000000 0xF SRT Shadow RCVR Trigger [1:0] read-write RESERVED1 reserved1 [31:2] read-only USART_STET Shadow TX Empty Trigger 0xA0 32 read-write 0x00000000 0xF STET Shadow TX Empty Trigger [1:0] read-write RESERVED1 reserved1 [31:2] read-only USART_HTX Halt Transmit 0xA4 32 read-write 0x00000000 0x01 HALT_TX This register is use to halt transmissions for testing [0:0] read-write HALT_TX Disabled Halt TX disabled 0 Enabled Halt TX enabled 1 RESERVED1 reserved1 [31:1] read-only USART_DMASA DMA Software Acknowledge 0xA8 32 read-write 0x00000000 0x01 DMA_SOFTWARE_ACK This register is use to perform a DMA software acknowledge if a transfer needs to be terminated due to an error condition [0:0] write-only RESERVED1 reserved1 [31:1] read-only USART_CPR Component Parameter Register 0xF4 32 read-only 0x000125F2 APB_DATA_WIDTH APB data width register. [1:0] read-only APB_DATA_WIDTH read 8_BIT APB Data Width 8 BIT 0 16_BIT APB Data Width 16 BIT 1 32_BIT APB Data Width 32 BIT 2 RESERVED Reserved 2 RESERVED1 reserved1 [3:2] read-only AFCE_MODE none [4:4] read-only AFCE_MODE read TRUE True 1 FALSE False 0 THRE_MODE none [5:5] read-only THRE_MODE read TRUE True 1 FALSE False 0 SIR_MODE none [6:6] read-only SIR_MODE read TRUE True 1 FALSE False 0 SIR_LP_MODE none [7:7] read-only SIR_LP_MODE read TRUE True 1 FALSE False 0 ADDITIONAL_FEAT none [8:8] read-only ADDITIONAL_FEAT read TRUE True 1 FALSE False 0 FIFO_ACCESS none [9:9] read-only FIFO_ACCESS read TRUE True 1 FALSE False 0 FIFO_STAT none [10:10] read-only FIFO_STAT read TRUE True 1 FALSE False 0 SHADOW none [11:11] read-only SHADOW read TRUE True 1 FALSE False 0 UART_ADD_ENCODED_PARAMS none [12:12] read-only UART_ADD_ENCODED_PARAMS read TRUE True 1 FALSE False 0 DMA_EXTRA none [13:13] read-only DMA_EXTRA read TRUE True 1 FALSE False 0 RESERVED2 reserved2 [15:14] read-only FIFO_MODE none [23:16] read-only FIFO_MODE read TRUE True 1 FALSE False 0 RESERVED3 reserved3 [31:24] read-only UCV UART Component Version 0xF8 32 read-only 0x3430302A UART_COMP_VER ASCII value for each number in the version, followed by * [31:0] read-only USART_CTR Component Type Register 0xFC 32 read-only 0x44570110 UART_COMP_VER This register contains the peripherals identification code. [31:0] read-only UART0 1.0 Universal Asynchronous Receiver/Transmitter is for serial communication with peripherals, modems and datasets UART_USRT 0x44000000 32 read-write 0 0x100 registers UART0 38 DLL Divisor Latch Low 0x00 32 read-write 0x00000000 0xFF DLL Lower 8-bits of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. [7:0] read-write RESERVED1 reserved1 [31:8] read-only THR Transmit Holding Register DLL 0x00 32 write-only 0x00000000 0xFF THR_LSB_8_Bits Data to be transmitted on serial output port [7:0] write-only THR_MSB_9th_Bit Data to be transmitted on the serial output port(sout) in UART mode for the MSB 9th bit. [8:8] write-only RESERVED1 reserved1 [31:9] write-only RBR Receive Buffer Register DLL 0x00 32 read-only 0x00000000 0xFF RBR_LSB_8_Bits Receive Buffer Field [7:0] read-only RBR_MSB_9th_Bit Data byte received on the serial input port (sin) in UART mode for the MSB 9th bit. [8:8] read-only RESERVED1 reserved1 [31:9] read-only IER Interrupt Enable Register 0x04 32 read-write 0x00000000 0x8F ERBFI Enable Received Data Available Interrupt [0:0] read-write Disable Received Data Available Interrupt is disabled 0 Enable Received Data Available Interrupt is enabled 1 ETBEI Enable Transmit Holding Register Empty Interrupt [1:1] read-write Disable Transmit Holding Register Empty Interrupt is disabled 0 Enable Transmit Holding Register Empty Interrupt is enabled 1 ELSI Enable Receiver Line Status Interrupt [2:2] read-write Disable Receiver Line Status Interrupt is disabled 0 Enable Receiver Line Status Interrupt is enabled 1 EDSSI Enable Modem Status Interrupt [3:3] read-write Disable Modem Status Interrupt is disabled 0 Enable Modem Status Interrupt is enabled 1 RESERVED1 reserved1 [6:4] read-only PTIME Programmable THRE Interrupt Mode Enable [7:7] read-write Disable generation of THRE Interrupt is disabled 0 Enable generation of THRE Interrupt is enabled 1 RESERVED2 reserved2 [31:8] read-only DLH Divisor Latch High DLL 0x00 32 read-write 0x00000000 0xFF DLH Upper 8-bits of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART [7:0] read-write RESERVED1 reserved1 [31:8] read-only FCR FIFO Control Register 0x08 32 write-only 0x00000000 0xFF FIFOE This enables/disables the transmit (XMIT) and receive (RCVR) FIFOs [0:0] write-only RFIFOR RCVR FIFO Reset [1:1] write-only XFIFOR XMIT FIFO Reset [2:2] write-only DMAM DMA signalling mode [3:3] write-only Mode0 DMA Signalling mode0 0 Mode1 DMA Signalling mode1 1 TET TX Empty Trigger [5:4] write-only FIFO_EMPTY FIFO Empty 0 FIFO_2_CHARACTER 2 characters in the FIFO 1 FIFO_1_BY_4_CHARACTER FIFO 1/4 full 2 FIFO_1_BY_2_CHARACTER FIFO 1/2 full 3 write RT This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt is generated [7:6] write-only write FIFO_1_CHARACTER 1 character in the FIFO 0 FIFO_1_BY_4_CHARACTER FIFO 1/4 full 1 FIFO_1_BY_2_CHARACTER FIFO 1/2 full 2 FIFO_LESS_THAN_2_CHARACTER FIFO 2 less than full 3 RESERVED1 reserved1 [31:8] read-only IIR Interrupt Identity Register 0x08 32 read-only 0x00000001 IID Interrupt ID [3:0] read-only read Modem_Status modem status pending pending interrupt 0 No_Interrupt_Pending This field indicates no interrupt pending status 1 THR_Empty Transmit Holding Register Empty pending interrupt 2 Receive_Data_Available Received Data Available pending interrupt 4 Receiver_Line_Status Receive line status pending interrupt 6 Busy_Detect Busy detect pending interrupt 7 Character_Timeout Character Timeout pending interrupt 12 RESERVED1 reserved1 [5:4] read-only FIFOSE This is used to indicate whether the FIFOs are enabled or disabled. [7:6] read-only read Disable FIFO is disabled 0 Enable FIFO is enabled 3 RESERVED2 reserved2 [31:8] read-only LCR Line Control Register 0x0C 32 read-write 0x00000000 0xFF DLS Data Length Select,This is used to select the number of data bits per character that the peripheral transmits and receives [1:0] read-write 5_BITS_PER_CHARACTER 5 bits per character 0 6_BITS_PER_CHARACTER 6 bits per character 1 7_BITS_PER_CHARACTER 7 bits per character 2 8_BITS_PER_CHARACTER 8 bits per character 3 STOP This is used to select the number of stop bits per character that the peripheral transmits and receives [2:2] read-write 1_STOP_BIT_PER_CHARACTER 1 stop bit per character 0 1_5_OR_2_STOPS_BIT_PER_CHARACTER 1.5 or 2 stop bits per character 1 PEN This bit is used to enable and disable parity generation and detection in transmitted and received serial character [3:3] read-write Parity_Disable Parity disabled 0 Parity_Enable Parity Enabled 1 EPS This is used to select between even and odd parity [4:4] read-write Set_to_0 An odd number of logic 1s is transmitted or checked 0 Set_to_1 An even number of logic 1s is transmitted or checked 1 STICK_PARITY This bit is used to force parity value [5:5] read-write LOGIC0 When PEN, EPS, and Stick Parity are set to 1, the parity bit is transmitted and checked as logic 0 0 LOGIC1 If PEN and Stick Parity are set to 1 and EPS is a logic 0,then parity bit is transmitted and checked as a logic 1 1 BC This is used to cause a break condition to be transmitted to the receiving device [6:6] read-write SERIAL_OUTPUT_SPACING_STATE If set to 1, the serial output is forced to the spacing (logic 0) state 1 DLAB enable reading and writing of the Divisor Latch register, This bit must be cleared after initial baud rate set up [7:7] read-write RESERVED1 reserved1 [31:8] read-only MCR Modem Control Register 0x10 32 read-write 0x00000000 0x7F DTR This is used to directly control the Data Terminal Ready (dtr_n) output [0:0] read-write DTR_LOGIC1 dtr_n de-asserted (logic 1) 0 DTR_LOGIC0 dtr_n asserted (logic 0) 1 RTS This is used to directly control the Request to Send (rts_n) output [1:1] read-write OUT1 This is used to directly control the user-designated Output1 (out1_n) output [2:2] read-write OUT1_LOGIC1 out1_n de-asserted (logic 1) 0 OUT1_LOGIC0 out1_n asserted (logic 0) 1 OUT2 This is used to directly control the user-designated Output2 (out2_n) output [3:3] read-write OUT2_LOGIC1 out2_n de-asserted (logic 1) 0 OUT2_LOGIC0 out2_n asserted (logic 0) 1 LB This is used to put the UART into a diagnostic mode for test purposes [4:4] read-write AFCE This is used to directly control the user-designated Output2 (out2_n) output [5:5] read-write Auto_Flow_Control Disabled Auto Flow Control Mode disabled 0 Enabled Auto Flow Control Mode enabled 1 SIRE This is used to enable/disable the IrDA SIR Mode features [6:6] read-write IrDA_SIR_Mode Disabled IrDA SIR Mode disabled 0 Enabled IrDA SIR Mode enabled 1 RESERVED1 reserved1 [31:7] read-only LSR Line Status Register 0x14 32 read-only 0x00000060 DR This is used to indicate that the receiver contains at least one character in the RBR or the receiver FIFO [0:0] read-only read No_Data_Ready No data Ready 0 Data_Ready Data Ready 1 OE This is used to indicate the occurrence of an overrun error [1:1] read-only read No_OverRun_Error no overrun error 0 OverRun_Error overrun error 1 PE This is used to indicate the occurrence of a parity error in the receiver if the Parity Enable (PEN) bit (LCR[3]) is set [2:2] read-only read No_Parity_Error no parity error 0 Parity_Error parity error 1 FE This is used to indicate the occurrence of a framing error in the receiver [3:3] read-only read No_Framing_Error no framing error 0 Framing_Error framing error 1 BI his is used to indicate the detection of a break sequence on the serial input data [4:4] read-only THRE Transmit Holding Register Empty bit [5:5] read-only TEMT Transmitter Empty bit [6:6] read-only RFE This is used to indicate if there is at least one parity error,framing error, or break indication in the FIFO [7:7] read-only read No_Error_in_RX_FIFO no error in RX FIFO 0 Error_in_RX_FIFO error in RX FIFO 1 ADDR_RCVD Address Received bit,If 9-bit data mode (LCR_EXT[0]=1) is enabled, this bit is used to indicate that the 9th bit of the receive data is set to 1. [8:8] read-only read Character_is_Address Indicates that the character is an address. 1 Character_is_Data Indicates that the character is data. 0 RESERVED1 reserved1 [31:9] read-only MSR Modem Status Register 0x18 32 read-only 0x00000000 0xFF DCTS This is used to indicate that the modem control line cts_n has changed since the last time the MSR was read [0:0] read-only change_on_cts_n read No_Change no change on cts_n since last read of MSR 0 Change change on cts_n since last read of MSR 1 DDSR This is used to indicate that the modem control line dsr_n has changed since the last time the MSR was read [1:1] read-only Change_on_dsr_n read No_Change no change on dsr_n since last read of MSR 0 Change change on dsr_n since last read of MSR 1 TERI This is used to indicate that a change on the input ri_n(from an active-low to an inactive-high state)has occurred since the last time the MSR was read [2:2] read-only Change_on_ri_n read No_Change no change on ri_n since last read of MSR 0 Change change on ri_n since last read of MSR 1 DDCD This is used to indicate that the modem control line dcd_n has changed since the last time the MSR was read [3:3] read-only Change_on_dcd_n read No_Change no change on dcd_n since last read of MSR 0 Change change on dcd_n since last read of MSR 1 CTS This is used to indicate the current state of the modem control line cts_n [4:4] read-only cts_n_Input read Deasserted cts_n input is de-asserted (logic 1) 0 Asserted cts_n input is asserted (logic 0) 1 DSR This is used to indicate the current state of the modem control line dsr_n [5:5] read-only dsr_n_Input read Deasserted dsr_n input is de-asserted (logic 1) 0 Asserted dsr_n input is asserted (logic 0) 1 RI This is used to indicate the current state of the modem control line ri_n [6:6] read-only ri_n_input read Deasserted ri_n input is de-asserted (logic 1) 0 Asserted ri_n input is asserted (logic 0) 1 DCD This is used to indicate the current state of the modem control line dcd_n [7:7] read-only dcd_n_input read Deasserted dcd_n input is de-asserted (logic 1) 0 Asserted dcd_n input is asserted (logic 0) 1 RESERVED1 reserved1 [31:8] read-only SCR Scratch pad Register 0x1C 32 read-write 0x00000000 0xFF SCRATCH_PAD This register is for programmers to use as a temporary storage space. It has no defined purpose [7:0] read-write RESERVED1 reserved1 [31:8] read-only LPDLL Low Power Divisor Latch Low Register 0x20 32 read-write 0x00000000 0xFF LPDLL This register makes up the lower 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K [7:0] read-write RESERVED1 reserved1 [31:8] read-write LPDLH Low Power Divisor Latch High Register 0x24 32 read-write 0x00000000 0xFF LPDLH This register makes up the upper 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115200 [7:0] read-write RESERVED1 reserved1 [31:8] read-write SRBR Shadow Receive Buffer Register STHR 0x30 32 read-only 0x00000000 0xFF SRBR_LSB_8_Bits This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode [7:0] read-only SRBR_MSB_9th_Bit This is a shadow register for the RBR[8] bit.It is applicable only when UART_9BIT_DATA_EN=1. [8:8] read-only RESERVED1 reserved1 [31:9] read-only STHR Transmit Holding Register SRBR 0x30 32 write-only 0x00000000 0xFF STHR_LSB_8_Bits Data to be transmitted on serial output port [7:0] write-only STHR_MSB_9th_Bit This is a shadow register for the THR[8] bit.It is applicable only when UART_9BIT_DATA_EN=1 [8:8] write-only RESERVED1 reserved1 [31:9] write-only FAR This register is use to enable a FIFO access mode for testing, 0x70 32 read-write 0x00000000 0xFF FIFO_Access This register is use to enable a FIFO access mode for testing, [0:0] read-write RESERVED1 reserved1 [31:1] read-only TFR Reading this register gives the data at the top of the transmit FIFO.Each consecutive read pops the transmit FIFO and gives next data in FIFO 0x74 32 read-only 0x00000000 TX_FIFO_RD Transmit FIFO Read [7:0] read-only RESERVED1 reserved1 [31:8] read-only RFW none 0x78 32 read-write 0x00000000 RFWD Receive FIFO Write Data [7:0] write-only RFPE Receive FIFO Parity Error [8:8] write-only RFFE Receive FIFO Framing Error [9:9] write-only RESERVED1 reserved1 [31:10] read-only USR UART Status Register 0x7C 32 read-only 0x00000000 BUSY Indicates that a serial transfer is in progress [0:0] read-only read UART_IDLE UART is idle or inactive 0 UART_BUSY UART is busy (actively transferring data) 1 TFNF To Indicate that the transmit FIFO is not full [1:1] read-only read Transmit_FIFO_Full Transmit FIFO is full 0 Transmit_FIFO_Not_Full Transmit FIFO is not full 1 TFE To Indicate that the transmit FIFO is completely empty [2:2] read-only read Transmit_FIFO_Empty Transmit FIFO is not empty 0 Transmit_FIFO_Empty Transmit FIFO is empty 1 RFNE To Indicate that the receive FIFO contains one or more entries [3:3] read-only read Receive_FIFO_Empty Receive FIFO is empty 0 Receive FIFO_Not_Empty Receive FIFO is not empty 1 RFE To Indicate that the receive FIFO is completely full [4:4] read-only read Receive_FIFO_Not_Full Receive FIFO not full 0 Receive_FIFO_Full Receive FIFO Full 1 RESERVED1 reserved1 [31:5] read-only TFL Transmit FIFO Level 0x80 32 read-only 0x00000000 Transmit_FIFO_Level Transmit FIFO Level. This is indicates the number of data entries in the transmit FIFO. [29:0] read-only RESERVED1 reserved1 [31:30] read-only RFL Receive FIFO Level 0x84 32 read-only 0x00000000 Receive_FIFO_Level Receive FIFO Level. This is indicates the number of data entries in the receive FIFO. [29:0] read-only RESERVED1 reserved1 [31:30] read-only SRR Software Reset Register 0x88 32 read-write 0x00000000 UR UART Reset [0:0] write-only RFR RCVR FIFO Reset [1:1] write-only XFR XMIT FIFO Reset [2:2] write-only RESERVED1 reserved1 [31:3] read-only SRTS Shadow Request to Send 0x8C 32 read-write 0x00000000 0xF SRTS Shadow Request to Send. [0:0] read-write RESERVED1 reserved1 [31:1] read-only SBCR Shadow Break Control Register 0x90 32 read-write 0x00000000 0xF SBCR Shadow Break Control Bit [0:0] read-write RESERVED1 reserved1 [31:1] read-only SDMAM Shadow DMA Mode 0x94 32 read-write 0x00000000 0xF SDMAM Shadow DMA Mode [0:0] read-write MODE0 mode 0 0 MODE1 mode 1 1 RESERVED1 reserved1 [31:1] read-only SFE Shadow FIFO Enable 0x98 32 read-write 0x00000000 0xF Shadow_FIFO_En Shadow FIFO Enable [0:0] read-write RESERVED1 reserved1 [31:1] read-only SRT Shadow RCVR Trigger 0x9C 32 read-write 0x00000000 0xF SRCVRT Shadow RCVR Trigger [0:0] read-write 1_Character_in_FIFO 1 Character in FIFO 0 FIFO_1_4th_Full FIFO 1/4th Full 1 FIFO_Half_Full FIFO 1/2 Full 2 FIFO_2_Less_than_Full FIFO 2 Less than Full 3 RESERVED1 reserved1 [31:1] read-only STET Shadow TX Empty Trigger 0xA0 32 read-write 0x00000000 0xF STXET Shadow TX Empty Trigger [1:0] read-write FIFO_Empty FIFO Empty 0 2_Characters_in_FIFO 2 Characters in FIFO 1 FIFO_1_4th_Full FIFO 1/4th Full 2 FIFO_Half_Full FIFO 1/2 Full 3 RESERVED1 reserved1 [31:2] read-only HTX Halt Transmit 0xA4 32 read-write 0x00000000 0x01 HALT_TX This register is use to halt transmissions for testing [0:0] read-write Halt_TX Disabled Halt TX disabled 0 Enabled Halt TX enabled 1 RESERVED1 reserved1 [31:1] read-only DMASA DMA Software Acknowledge 0xA8 32 read-write 0x00000000 0x01 DMA_SOFTWARE_ACK This register is use to perform a DMA software acknowledge if a transfer needs to be terminated due to an error condition [0:0] write-only RESERVED1 reserved1 [31:1] read-only TCR Transceiver Control Register. 0xAC 32 read-write 0x00000006 RS485_EN RS485 Transfer Enable. [0:0] read-write RE_POL Receiver Enable Polarity. [1:1] read-write RE_Signal Active_Low RE signal is active low 0 Active_High RE signal is active high 1 DE_POL Driver Enable Polarity. [2:2] read-write DE_Signal Active_Low DE signal is active low 0 Active_High DE signal is active high 1 XFER_MODE Transfer Mode. [4:3] read-write RESERVED1 reserved1 [31:5] read-only DE_EN Driver Output Enable Register. 0xB0 32 read-write 0x00000000 DE_EN DE Enable control. [0:0] read-write DE_Signal Deassert De-assert 'de' signal 0 Assert Assert 'de' signal 1 RESERVED1 reserved1 [31:1] read-only RE_EN Receiver Output Enable Register. 0xB4 32 read-write 0x00000000 RE_EN RE Enable control. [0:0] read-write RE_Signal Deassert De-assert 're' signal 0 Assert Assert 're' signal 1 RESERVED1 reserved1 [31:1] read-only DET Driver Output Enable Timing Register. 0xB8 32 read-write 0x00000000 DE_ASSERT_TIME Driver enable assertion time. [7:0] read-write RESERVED0 reserved. [15:8] read-only DE_DE_ASSERT_TIME Driver enable de-assertion time. [23:16] read-write RESERVED1 reserved1 [31:24] read-only TAT TurnAround Timing Register 0xBC 32 read-write 0x00000000 DE_RE Driver Enable to Receiver Enable TurnAround time. [15:0] read-write RE_DE Receiver Enable to Driver Enable TurnAround time. [31:16] read-write DLF Divisor Latch Fraction Register. 0xC0 32 read-write 0x00000000 DLF_Val Fractional part of divisor. [5:0] read-write RESERVED1 reserved1 [31:6] read-only RAR Receive Address Register. 0xC4 32 read-write 0x00000000 RAR This is an address matching register during receive mode. [7:0] read-write RESERVED1 reserved1 [31:8] read-only TAR Transmit Address Register. 0xC8 32 read-write 0x00000000 TAR This is an address matching register during transmit mode. [7:0] read-write RESERVED1 reserved1 [31:8] read-only LCR_EXT Line Extended Control Register 0xCC 32 read-write 0x00000000 DLS_E Extension for DLS. [0:0] read-write ADDR_MATCH Address Match Mode. [1:1] read-write SEND_ADDR Send address control bit. [2:2] read-write TRANSMIT_MODE Transmit mode control bit. [3:3] read-write RESERVED1 reserved1 [31:4] read-only CPR Component Parameter Register 0xF4 32 read-only 0X000125F2 APB_DATA_WIDTH APB data width register. [1:0] read-only APB_DATA_WIDTH read 8_BIT APB Data Width 8 BIT 0 16_BIT APB Data Width 16 BIT 1 32_BIT APB Data Width 32 BIT 2 RESERVED Reserved 2 RESERVED1 reserved1 [3:2] read-only AFCE_MODE none [4:4] read-only AFCE_MODE read TRUE True 1 FALSE False 0 THRE_MODE none [5:5] read-only THRE_MODE read TRUE True 1 FALSE False 0 SIR_MODE none [6:6] read-only SIR_MODE read TRUE True 1 FALSE False 0 SIR_LP_MODE none [7:7] read-only SIR_LP_MODE read TRUE True 1 FALSE False 0 ADDITIONAL_FEAT none [8:8] read-only ADDITIONAL_FEAT read TRUE True 1 FALSE False 0 FIFO_ACCESS none [9:9] read-only FIFO_ACCESS read TRUE True 1 FALSE False 0 FIFO_STAT none [10:10] read-only FIFO_STAT read TRUE True 1 FALSE False 0 SHADOW none [11:11] read-only SHADOW read TRUE True 1 FALSE False 0 UART_ADD_ENCODED_PARAMS none [12:12] read-only UART_ADD_ENCODED_PARAMS read TRUE True 1 FALSE False 0 DMA_EXTRA none [13:13] read-only DMA_EXTRA read TRUE True 1 FALSE False 0 RESERVED2 reserved2 [15:14] read-only FIFO_MODE none [23:16] read-only RESERVED3 reserved3 [31:24] read-only UCV UART Component Version 0xF8 32 read-only 0x3430302A UART_COMP_VER This register contains UART Component Version. [31:0] read-only CTR Component Type Register,This register contains the peripherals identification code 0xFC 32 read-only 0x44570110 UART_COMP_VER This register contains the peripherals identification code. [31:0] read-only UART1 1.0 Universal Asynchronous Receiver/Transmitter is for serial communication with peripherals, modems and datasets UART_USRT 0x45020000 32 read-write 0 0x100 registers UART1 39 DLL Divisor Latch Low 0x00 32 read-write 0x00000000 0xFF DLL Lower 8-bits of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. [7:0] read-write RESERVED1 reserved1 [31:8] read-only THR Transmit Holding Register DLL 0x00 32 write-only 0x00000000 0xFF THR_LSB_8_Bits Data to be transmitted on serial output port [7:0] write-only THR_MSB_9th_Bit Data to be transmitted on the serial output port(sout) in UART mode for the MSB 9th bit. [8:8] write-only RESERVED1 reserved1 [31:9] write-only RBR Receive Buffer Register DLL 0x00 32 read-only 0x00000000 0xFF RBR_LSB_8_Bits Receive Buffer Field [7:0] read-only RBR_MSB_9th_Bit Data byte received on the serial input port (sin) in UART mode for the MSB 9th bit. [8:8] read-only RESERVED1 reserved1 [31:9] read-only IER Interrupt Enable Register 0x04 32 read-write 0x00000000 0x8F ERBFI Enable Received Data Available Interrupt [0:0] read-write Disable Received Data Available Interrupt is disabled 0 Enable Received Data Available Interrupt is enabled 1 ETBEI Enable Transmit Holding Register Empty Interrupt [1:1] read-write Disable Transmit Holding Register Empty Interrupt is disabled 0 Enable Transmit Holding Register Empty Interrupt is enabled 1 ELSI Enable Receiver Line Status Interrupt [2:2] read-write Disable Receiver Line Status Interrupt is disabled 0 Enable Receiver Line Status Interrupt is enabled 1 EDSSI Enable Modem Status Interrupt [3:3] read-write Disable Modem Status Interrupt is disabled 0 Enable Modem Status Interrupt is enabled 1 RESERVED1 reserved1 [6:4] read-only PTIME Programmable THRE Interrupt Mode Enable [7:7] read-write Disable generation of THRE Interrupt is disabled 0 Enable generation of THRE Interrupt is enabled 1 RESERVED2 reserved2 [31:8] read-only DLH Divisor Latch High DLL 0x00 32 read-write 0x00000000 0xFF DLH Upper 8-bits of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART [7:0] read-write RESERVED1 reserved1 [31:8] read-only FCR FIFO Control Register 0x08 32 write-only 0x00000000 0xFF FIFOE This enables/disables the transmit (XMIT) and receive (RCVR) FIFOs [0:0] write-only RFIFOR RCVR FIFO Reset [1:1] write-only XFIFOR XMIT FIFO Reset [2:2] write-only DMAM DMA signalling mode [3:3] write-only Mode0 DMA Signalling mode0 0 Mode1 DMA Signalling mode1 1 TET TX Empty Trigger [5:4] write-only FIFO_EMPTY FIFO Empty 0 FIFO_2_CHARACTER 2 characters in the FIFO 1 FIFO_1_BY_4_CHARACTER FIFO 1/4 full 2 FIFO_1_BY_2_CHARACTER FIFO 1/2 full 3 write RT This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt is generated [7:6] write-only write FIFO_1_CHARACTER 1 character in the FIFO 0 FIFO_1_BY_4_CHARACTER FIFO 1/4 full 1 FIFO_1_BY_2_CHARACTER FIFO 1/2 full 2 FIFO_LESS_THAN_2_CHARACTER FIFO 2 less than full 3 RESERVED1 reserved1 [31:8] read-only IIR Interrupt Identity Register 0x08 32 read-only 0x00000001 IID Interrupt ID [3:0] read-only read Modem_Status modem status pending pending interrupt 0 No_Interrupt_Pending This field indicates no interrupt pending status 1 THR_Empty Transmit Holding Register Empty pending interrupt 2 Receive_Data_Available Received Data Available pending interrupt 4 Receiver_Line_Status Receive line status pending interrupt 6 Busy_Detect Busy detect pending interrupt 7 Character_Timeout Character Timeout pending interrupt 12 RESERVED1 reserved1 [5:4] read-only FIFOSE This is used to indicate whether the FIFOs are enabled or disabled. [7:6] read-only read Disable FIFO is disabled 0 Enable FIFO is enabled 3 RESERVED2 reserved2 [31:8] read-only LCR Line Control Register 0x0C 32 read-write 0x00000000 0xFF DLS Data Length Select,This is used to select the number of data bits per character that the peripheral transmits and receives [1:0] read-write 5_BITS_PER_CHARACTER 5 bits per character 0 6_BITS_PER_CHARACTER 6 bits per character 1 7_BITS_PER_CHARACTER 7 bits per character 2 8_BITS_PER_CHARACTER 8 bits per character 3 STOP This is used to select the number of stop bits per character that the peripheral transmits and receives [2:2] read-write 1_STOP_BIT_PER_CHARACTER 1 stop bit per character 0 1_5_OR_2_STOPS_BIT_PER_CHARACTER 1.5 or 2 stop bits per character 1 PEN This bit is used to enable and disable parity generation and detection in transmitted and received serial character [3:3] read-write Parity_Disable Parity disabled 0 Parity_Enable Parity Enabled 1 EPS This is used to select between even and odd parity [4:4] read-write Set_to_0 An odd number of logic 1s is transmitted or checked 0 Set_to_1 An even number of logic 1s is transmitted or checked 1 STICK_PARITY This bit is used to force parity value [5:5] read-write LOGIC0 When PEN, EPS, and Stick Parity are set to 1, the parity bit is transmitted and checked as logic 0 0 LOGIC1 If PEN and Stick Parity are set to 1 and EPS is a logic 0,then parity bit is transmitted and checked as a logic 1 1 BC This is used to cause a break condition to be transmitted to the receiving device [6:6] read-write SERIAL_OUTPUT_SPACING_STATE If set to 1, the serial output is forced to the spacing (logic 0) state 1 DLAB enable reading and writing of the Divisor Latch register, This bit must be cleared after initial baud rate set up [7:7] read-write RESERVED1 reserved1 [31:8] read-only MCR Modem Control Register 0x10 32 read-write 0x00000000 0x7F DTR This is used to directly control the Data Terminal Ready (dtr_n) output [0:0] read-write DTR_LOGIC1 dtr_n de-asserted (logic 1) 0 DTR_LOGIC0 dtr_n asserted (logic 0) 1 RTS This is used to directly control the Request to Send (rts_n) output [1:1] read-write OUT1 This is used to directly control the user-designated Output1 (out1_n) output [2:2] read-write OUT1_LOGIC1 out1_n de-asserted (logic 1) 0 OUT1_LOGIC0 out1_n asserted (logic 0) 1 OUT2 This is used to directly control the user-designated Output2 (out2_n) output [3:3] read-write OUT2_LOGIC1 out2_n de-asserted (logic 1) 0 OUT2_LOGIC0 out2_n asserted (logic 0) 1 LB This is used to put the UART into a diagnostic mode for test purposes [4:4] read-write AFCE This is used to directly control the user-designated Output2 (out2_n) output [5:5] read-write Auto_Flow_Control Disabled Auto Flow Control Mode disabled 0 Enabled Auto Flow Control Mode enabled 1 SIRE This is used to enable/disable the IrDA SIR Mode features [6:6] read-write IrDA_SIR_Mode Disabled IrDA SIR Mode disabled 0 Enabled IrDA SIR Mode enabled 1 RESERVED1 reserved1 [31:7] read-only LSR Line Status Register 0x14 32 read-only 0x00000060 DR This is used to indicate that the receiver contains at least one character in the RBR or the receiver FIFO [0:0] read-only read No_Data_Ready No data Ready 0 Data_Ready Data Ready 1 OE This is used to indicate the occurrence of an overrun error [1:1] read-only read No_OverRun_Error no overrun error 0 OverRun_Error overrun error 1 PE This is used to indicate the occurrence of a parity error in the receiver if the Parity Enable (PEN) bit (LCR[3]) is set [2:2] read-only read No_Parity_Error no parity error 0 Parity_Error parity error 1 FE This is used to indicate the occurrence of a framing error in the receiver [3:3] read-only read No_Framing_Error no framing error 0 Framing_Error framing error 1 BI his is used to indicate the detection of a break sequence on the serial input data [4:4] read-only THRE Transmit Holding Register Empty bit [5:5] read-only TEMT Transmitter Empty bit [6:6] read-only RFE This is used to indicate if there is at least one parity error,framing error, or break indication in the FIFO [7:7] read-only read No_Error_in_RX_FIFO no error in RX FIFO 0 Error_in_RX_FIFO error in RX FIFO 1 ADDR_RCVD Address Received bit,If 9-bit data mode (LCR_EXT[0]=1) is enabled, this bit is used to indicate that the 9th bit of the receive data is set to 1. [8:8] read-only read Character_is_Address Indicates that the character is an address. 1 Character_is_Data Indicates that the character is data. 0 RESERVED1 reserved1 [31:9] read-only MSR Modem Status Register 0x18 32 read-only 0x00000000 0xFF DCTS This is used to indicate that the modem control line cts_n has changed since the last time the MSR was read [0:0] read-only change_on_cts_n read No_Change no change on cts_n since last read of MSR 0 Change change on cts_n since last read of MSR 1 DDSR This is used to indicate that the modem control line dsr_n has changed since the last time the MSR was read [1:1] read-only Change_on_dsr_n read No_Change no change on dsr_n since last read of MSR 0 Change change on dsr_n since last read of MSR 1 TERI This is used to indicate that a change on the input ri_n(from an active-low to an inactive-high state)has occurred since the last time the MSR was read [2:2] read-only Change_on_ri_n read No_Change no change on ri_n since last read of MSR 0 Change change on ri_n since last read of MSR 1 DDCD This is used to indicate that the modem control line dcd_n has changed since the last time the MSR was read [3:3] read-only Change_on_dcd_n read No_Change no change on dcd_n since last read of MSR 0 Change change on dcd_n since last read of MSR 1 CTS This is used to indicate the current state of the modem control line cts_n [4:4] read-only cts_n_Input read Deasserted cts_n input is de-asserted (logic 1) 0 Asserted cts_n input is asserted (logic 0) 1 DSR This is used to indicate the current state of the modem control line dsr_n [5:5] read-only dsr_n_Input read Deasserted dsr_n input is de-asserted (logic 1) 0 Asserted dsr_n input is asserted (logic 0) 1 RI This is used to indicate the current state of the modem control line ri_n [6:6] read-only ri_n_input read Deasserted ri_n input is de-asserted (logic 1) 0 Asserted ri_n input is asserted (logic 0) 1 DCD This is used to indicate the current state of the modem control line dcd_n [7:7] read-only dcd_n_input read Deasserted dcd_n input is de-asserted (logic 1) 0 Asserted dcd_n input is asserted (logic 0) 1 RESERVED1 reserved1 [31:8] read-only SCR Scratch pad Register 0x1C 32 read-write 0x00000000 0xFF SCRATCH_PAD This register is for programmers to use as a temporary storage space. It has no defined purpose [7:0] read-write RESERVED1 reserved1 [31:8] read-only LPDLL Low Power Divisor Latch Low Register 0x20 32 read-write 0x00000000 0xFF LPDLL This register makes up the lower 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K [7:0] read-write RESERVED1 reserved1 [31:8] read-write LPDLH Low Power Divisor Latch High Register 0x24 32 read-write 0x00000000 0xFF LPDLH This register makes up the upper 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115200 [7:0] read-write RESERVED1 reserved1 [31:8] read-write SRBR Shadow Receive Buffer Register STHR 0x30 32 read-only 0x00000000 0xFF SRBR_LSB_8_Bits This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode [7:0] read-only SRBR_MSB_9th_Bit This is a shadow register for the RBR[8] bit.It is applicable only when UART_9BIT_DATA_EN=1. [8:8] read-only RESERVED1 reserved1 [31:9] read-only STHR Transmit Holding Register SRBR 0x30 32 write-only 0x00000000 0xFF STHR_LSB_8_Bits Data to be transmitted on serial output port [7:0] write-only STHR_MSB_9th_Bit This is a shadow register for the THR[8] bit.It is applicable only when UART_9BIT_DATA_EN=1 [8:8] write-only RESERVED1 reserved1 [31:9] write-only FAR This register is use to enable a FIFO access mode for testing, 0x70 32 read-write 0x00000000 0xFF FIFO_Access This register is use to enable a FIFO access mode for testing, [0:0] read-write RESERVED1 reserved1 [31:1] read-only TFR Reading this register gives the data at the top of the transmit FIFO.Each consecutive read pops the transmit FIFO and gives next data in FIFO 0x74 32 read-only 0x00000000 TX_FIFO_RD Transmit FIFO Read [7:0] read-only RESERVED1 reserved1 [31:8] read-only RFW none 0x78 32 read-write 0x00000000 RFWD Receive FIFO Write Data [7:0] write-only RFPE Receive FIFO Parity Error [8:8] write-only RFFE Receive FIFO Framing Error [9:9] write-only RESERVED1 reserved1 [31:10] read-only USR UART Status Register 0x7C 32 read-only 0x00000000 BUSY Indicates that a serial transfer is in progress [0:0] read-only read UART_IDLE UART is idle or inactive 0 UART_BUSY UART is busy (actively transferring data) 1 TFNF To Indicate that the transmit FIFO is not full [1:1] read-only read Transmit_FIFO_Full Transmit FIFO is full 0 Transmit_FIFO_Not_Full Transmit FIFO is not full 1 TFE To Indicate that the transmit FIFO is completely empty [2:2] read-only read Transmit_FIFO_Empty Transmit FIFO is not empty 0 Transmit_FIFO_Empty Transmit FIFO is empty 1 RFNE To Indicate that the receive FIFO contains one or more entries [3:3] read-only read Receive_FIFO_Empty Receive FIFO is empty 0 Receive FIFO_Not_Empty Receive FIFO is not empty 1 RFE To Indicate that the receive FIFO is completely full [4:4] read-only read Receive_FIFO_Not_Full Receive FIFO not full 0 Receive_FIFO_Full Receive FIFO Full 1 RESERVED1 reserved1 [31:5] read-only TFL Transmit FIFO Level 0x80 32 read-only 0x00000000 Transmit_FIFO_Level Transmit FIFO Level. This is indicates the number of data entries in the transmit FIFO. [29:0] read-only RESERVED1 reserved1 [31:30] read-only RFL Receive FIFO Level 0x84 32 read-only 0x00000000 Receive_FIFO_Level Receive FIFO Level. This is indicates the number of data entries in the receive FIFO. [29:0] read-only RESERVED1 reserved1 [31:30] read-only SRR Software Reset Register 0x88 32 read-write 0x00000000 UR UART Reset [0:0] write-only RFR RCVR FIFO Reset [1:1] write-only XFR XMIT FIFO Reset [2:2] write-only RESERVED1 reserved1 [31:3] read-only SRTS Shadow Request to Send 0x8C 32 read-write 0x00000000 0xF SRTS Shadow Request to Send. [0:0] read-write RESERVED1 reserved1 [31:1] read-only SBCR Shadow Break Control Register 0x90 32 read-write 0x00000000 0xF SBCR Shadow Break Control Bit [0:0] read-write RESERVED1 reserved1 [31:1] read-only SDMAM Shadow DMA Mode 0x94 32 read-write 0x00000000 0xF SDMAM Shadow DMA Mode [0:0] read-write MODE0 mode 0 0 MODE1 mode 1 1 RESERVED1 reserved1 [31:1] read-only SFE Shadow FIFO Enable 0x98 32 read-write 0x00000000 0xF Shadow_FIFO_En Shadow FIFO Enable [0:0] read-write RESERVED1 reserved1 [31:1] read-only SRT Shadow RCVR Trigger 0x9C 32 read-write 0x00000000 0xF SRCVRT Shadow RCVR Trigger [0:0] read-write 1_Character_in_FIFO 1 Character in FIFO 0 FIFO_1_4th_Full FIFO 1/4th Full 1 FIFO_Half_Full FIFO 1/2 Full 2 FIFO_2_Less_than_Full FIFO 2 Less than Full 3 RESERVED1 reserved1 [31:1] read-only STET Shadow TX Empty Trigger 0xA0 32 read-write 0x00000000 0xF STXET Shadow TX Empty Trigger [1:0] read-write FIFO_Empty FIFO Empty 0 2_Characters_in_FIFO 2 Characters in FIFO 1 FIFO_1_4th_Full FIFO 1/4th Full 2 FIFO_Half_Full FIFO 1/2 Full 3 RESERVED1 reserved1 [31:2] read-only HTX Halt Transmit 0xA4 32 read-write 0x00000000 0x01 HALT_TX This register is use to halt transmissions for testing [0:0] read-write Halt_TX Disabled Halt TX disabled 0 Enabled Halt TX enabled 1 RESERVED1 reserved1 [31:1] read-only DMASA DMA Software Acknowledge 0xA8 32 read-write 0x00000000 0x01 DMA_SOFTWARE_ACK This register is use to perform a DMA software acknowledge if a transfer needs to be terminated due to an error condition [0:0] write-only RESERVED1 reserved1 [31:1] read-only TCR Transceiver Control Register. 0xAC 32 read-write 0x00000006 RS485_EN RS485 Transfer Enable. [0:0] read-write RE_POL Receiver Enable Polarity. [1:1] read-write RE_Signal Active_Low RE signal is active low 0 Active_High RE signal is active high 1 DE_POL Driver Enable Polarity. [2:2] read-write DE_Signal Active_Low DE signal is active low 0 Active_High DE signal is active high 1 XFER_MODE Transfer Mode. [4:3] read-write RESERVED1 reserved1 [31:5] read-only DE_EN Driver Output Enable Register. 0xB0 32 read-write 0x00000000 DE_EN DE Enable control. [0:0] read-write DE_Signal Deassert De-assert 'de' signal 0 Assert Assert 'de' signal 1 RESERVED1 reserved1 [31:1] read-only RE_EN Receiver Output Enable Register. 0xB4 32 read-write 0x00000000 RE_EN RE Enable control. [0:0] read-write RE_Signal Deassert De-assert 're' signal 0 Assert Assert 're' signal 1 RESERVED1 reserved1 [31:1] read-only DET Driver Output Enable Timing Register. 0xB8 32 read-write 0x00000000 DE_ASSERT_TIME Driver enable assertion time. [7:0] read-write RESERVED0 reserved. [15:8] read-only DE_DE_ASSERT_TIME Driver enable de-assertion time. [23:16] read-write RESERVED1 reserved1 [31:24] read-only TAT TurnAround Timing Register 0xBC 32 read-write 0x00000000 DE_RE Driver Enable to Receiver Enable TurnAround time. [15:0] read-write RE_DE Receiver Enable to Driver Enable TurnAround time. [31:16] read-write DLF Divisor Latch Fraction Register. 0xC0 32 read-write 0x00000000 DLF_Val Fractional part of divisor. [5:0] read-write RESERVED1 reserved1 [31:6] read-only RAR Receive Address Register. 0xC4 32 read-write 0x00000000 RAR This is an address matching register during receive mode. [7:0] read-write RESERVED1 reserved1 [31:8] read-only TAR Transmit Address Register. 0xC8 32 read-write 0x00000000 TAR This is an address matching register during transmit mode. [7:0] read-write RESERVED1 reserved1 [31:8] read-only LCR_EXT Line Extended Control Register 0xCC 32 read-write 0x00000000 DLS_E Extension for DLS. [0:0] read-write ADDR_MATCH Address Match Mode. [1:1] read-write SEND_ADDR Send address control bit. [2:2] read-write TRANSMIT_MODE Transmit mode control bit. [3:3] read-write RESERVED1 reserved1 [31:4] read-only CPR Component Parameter Register 0xF4 32 read-only 0X000125F2 APB_DATA_WIDTH APB data width register. [1:0] read-only APB_DATA_WIDTH read 8_BIT APB Data Width 8 BIT 0 16_BIT APB Data Width 16 BIT 1 32_BIT APB Data Width 32 BIT 2 RESERVED Reserved 2 RESERVED1 reserved1 [3:2] read-only AFCE_MODE none [4:4] read-only AFCE_MODE read TRUE True 1 FALSE False 0 THRE_MODE none [5:5] read-only THRE_MODE read TRUE True 1 FALSE False 0 SIR_MODE none [6:6] read-only SIR_MODE read TRUE True 1 FALSE False 0 SIR_LP_MODE none [7:7] read-only SIR_LP_MODE read TRUE True 1 FALSE False 0 ADDITIONAL_FEAT none [8:8] read-only ADDITIONAL_FEAT read TRUE True 1 FALSE False 0 FIFO_ACCESS none [9:9] read-only FIFO_ACCESS read TRUE True 1 FALSE False 0 FIFO_STAT none [10:10] read-only FIFO_STAT read TRUE True 1 FALSE False 0 SHADOW none [11:11] read-only SHADOW read TRUE True 1 FALSE False 0 UART_ADD_ENCODED_PARAMS none [12:12] read-only UART_ADD_ENCODED_PARAMS read TRUE True 1 FALSE False 0 DMA_EXTRA none [13:13] read-only DMA_EXTRA read TRUE True 1 FALSE False 0 RESERVED2 reserved2 [15:14] read-only FIFO_MODE none [23:16] read-only RESERVED3 reserved3 [31:24] read-only UCV UART Component Version 0xF8 32 read-only 0x3430302A UART_COMP_VER This register contains UART Component Version. [31:0] read-only CTR Component Type Register,This register contains the peripherals identification code 0xFC 32 read-only 0x44570110 UART_COMP_VER This register contains the peripherals identification code. [31:0] read-only ULP_UART 1.0 Universal Asynchronous Receiver/Transmitter is for serial communication with peripherals, modems and datasets UART_USRT 0x24041800 32 read-write 0 0x100 registers ULP_UART 12 DLL Divisor Latch Low 0x00 32 read-write 0x00000000 0xFF DLL Lower 8-bits of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. [7:0] read-write RESERVED1 reserved1 [31:8] read-only THR Transmit Holding Register DLL 0x00 32 write-only 0x00000000 0xFF THR_LSB_8_Bits Data to be transmitted on serial output port [7:0] write-only THR_MSB_9th_Bit Data to be transmitted on the serial output port(sout) in UART mode for the MSB 9th bit. [8:8] write-only RESERVED1 reserved1 [31:9] write-only RBR Receive Buffer Register DLL 0x00 32 read-only 0x00000000 0xFF RBR_LSB_8_Bits Receive Buffer Field [7:0] read-only RBR_MSB_9th_Bit Data byte received on the serial input port (sin) in UART mode for the MSB 9th bit. [8:8] read-only RESERVED1 reserved1 [31:9] read-only IER Interrupt Enable Register 0x04 32 read-write 0x00000000 0x8F ERBFI Enable Received Data Available Interrupt [0:0] read-write Disable Received Data Available Interrupt is disabled 0 Enable Received Data Available Interrupt is enabled 1 ETBEI Enable Transmit Holding Register Empty Interrupt [1:1] read-write Disable Transmit Holding Register Empty Interrupt is disabled 0 Enable Transmit Holding Register Empty Interrupt is enabled 1 ELSI Enable Receiver Line Status Interrupt [2:2] read-write Disable Receiver Line Status Interrupt is disabled 0 Enable Receiver Line Status Interrupt is enabled 1 EDSSI Enable Modem Status Interrupt [3:3] read-write Disable Modem Status Interrupt is disabled 0 Enable Modem Status Interrupt is enabled 1 RESERVED1 reserved1 [6:4] read-only PTIME Programmable THRE Interrupt Mode Enable [7:7] read-write Disable generation of THRE Interrupt is disabled 0 Enable generation of THRE Interrupt is enabled 1 RESERVED2 reserved2 [31:8] read-only DLH Divisor Latch High DLL 0x00 32 read-write 0x00000000 0xFF DLH Upper 8-bits of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART [7:0] read-write RESERVED1 reserved1 [31:8] read-only FCR FIFO Control Register 0x08 32 write-only 0x00000000 0xFF FIFOE This enables/disables the transmit (XMIT) and receive (RCVR) FIFOs [0:0] write-only RFIFOR RCVR FIFO Reset [1:1] write-only XFIFOR XMIT FIFO Reset [2:2] write-only DMAM DMA signalling mode [3:3] write-only Mode0 DMA Signalling mode0 0 Mode1 DMA Signalling mode1 1 TET TX Empty Trigger [5:4] write-only FIFO_EMPTY FIFO Empty 0 FIFO_2_CHARACTER 2 characters in the FIFO 1 FIFO_1_BY_4_CHARACTER FIFO 1/4 full 2 FIFO_1_BY_2_CHARACTER FIFO 1/2 full 3 write RT This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt is generated [7:6] write-only write FIFO_1_CHARACTER 1 character in the FIFO 0 FIFO_1_BY_4_CHARACTER FIFO 1/4 full 1 FIFO_1_BY_2_CHARACTER FIFO 1/2 full 2 FIFO_LESS_THAN_2_CHARACTER FIFO 2 less than full 3 RESERVED1 reserved1 [31:8] read-only IIR Interrupt Identity Register 0x08 32 read-only 0x00000001 IID Interrupt ID [3:0] read-only read Modem_Status modem status pending pending interrupt 0 No_Interrupt_Pending This field indicates no interrupt pending status 1 THR_Empty Transmit Holding Register Empty pending interrupt 2 Receive_Data_Available Received Data Available pending interrupt 4 Receiver_Line_Status Receive line status pending interrupt 6 Busy_Detect Busy detect pending interrupt 7 Character_Timeout Character Timeout pending interrupt 12 RESERVED1 reserved1 [5:4] read-only FIFOSE This is used to indicate whether the FIFOs are enabled or disabled. [7:6] read-only read Disable FIFO is disabled 0 Enable FIFO is enabled 3 RESERVED2 reserved2 [31:8] read-only LCR Line Control Register 0x0C 32 read-write 0x00000000 0xFF DLS Data Length Select,This is used to select the number of data bits per character that the peripheral transmits and receives [1:0] read-write 5_BITS_PER_CHARACTER 5 bits per character 0 6_BITS_PER_CHARACTER 6 bits per character 1 7_BITS_PER_CHARACTER 7 bits per character 2 8_BITS_PER_CHARACTER 8 bits per character 3 STOP This is used to select the number of stop bits per character that the peripheral transmits and receives [2:2] read-write 1_STOP_BIT_PER_CHARACTER 1 stop bit per character 0 1_5_OR_2_STOPS_BIT_PER_CHARACTER 1.5 or 2 stop bits per character 1 PEN This bit is used to enable and disable parity generation and detection in transmitted and received serial character [3:3] read-write Parity_Disable Parity disabled 0 Parity_Enable Parity Enabled 1 EPS This is used to select between even and odd parity [4:4] read-write Set_to_0 An odd number of logic 1s is transmitted or checked 0 Set_to_1 An even number of logic 1s is transmitted or checked 1 STICK_PARITY This bit is used to force parity value [5:5] read-write LOGIC0 When PEN, EPS, and Stick Parity are set to 1, the parity bit is transmitted and checked as logic 0 0 LOGIC1 If PEN and Stick Parity are set to 1 and EPS is a logic 0,then parity bit is transmitted and checked as a logic 1 1 BC This is used to cause a break condition to be transmitted to the receiving device [6:6] read-write SERIAL_OUTPUT_SPACING_STATE If set to 1, the serial output is forced to the spacing (logic 0) state 1 DLAB enable reading and writing of the Divisor Latch register, This bit must be cleared after initial baud rate set up [7:7] read-write RESERVED1 reserved1 [31:8] read-only MCR Modem Control Register 0x10 32 read-write 0x00000000 0x7F DTR This is used to directly control the Data Terminal Ready (dtr_n) output [0:0] read-write DTR_LOGIC1 dtr_n de-asserted (logic 1) 0 DTR_LOGIC0 dtr_n asserted (logic 0) 1 RTS This is used to directly control the Request to Send (rts_n) output [1:1] read-write OUT1 This is used to directly control the user-designated Output1 (out1_n) output [2:2] read-write OUT1_LOGIC1 out1_n de-asserted (logic 1) 0 OUT1_LOGIC0 out1_n asserted (logic 0) 1 OUT2 This is used to directly control the user-designated Output2 (out2_n) output [3:3] read-write OUT2_LOGIC1 out2_n de-asserted (logic 1) 0 OUT2_LOGIC0 out2_n asserted (logic 0) 1 LB This is used to put the UART into a diagnostic mode for test purposes [4:4] read-write AFCE This is used to directly control the user-designated Output2 (out2_n) output [5:5] read-write Auto_Flow_Control Disabled Auto Flow Control Mode disabled 0 Enabled Auto Flow Control Mode enabled 1 SIRE This is used to enable/disable the IrDA SIR Mode features [6:6] read-write IrDA_SIR_Mode Disabled IrDA SIR Mode disabled 0 Enabled IrDA SIR Mode enabled 1 RESERVED1 reserved1 [31:7] read-only LSR Line Status Register 0x14 32 read-only 0x00000060 DR This is used to indicate that the receiver contains at least one character in the RBR or the receiver FIFO [0:0] read-only read No_Data_Ready No data Ready 0 Data_Ready Data Ready 1 OE This is used to indicate the occurrence of an overrun error [1:1] read-only read No_OverRun_Error no overrun error 0 OverRun_Error overrun error 1 PE This is used to indicate the occurrence of a parity error in the receiver if the Parity Enable (PEN) bit (LCR[3]) is set [2:2] read-only read No_Parity_Error no parity error 0 Parity_Error parity error 1 FE This is used to indicate the occurrence of a framing error in the receiver [3:3] read-only read No_Framing_Error no framing error 0 Framing_Error framing error 1 BI his is used to indicate the detection of a break sequence on the serial input data [4:4] read-only THRE Transmit Holding Register Empty bit [5:5] read-only TEMT Transmitter Empty bit [6:6] read-only RFE This is used to indicate if there is at least one parity error,framing error, or break indication in the FIFO [7:7] read-only read No_Error_in_RX_FIFO no error in RX FIFO 0 Error_in_RX_FIFO error in RX FIFO 1 ADDR_RCVD Address Received bit,If 9-bit data mode (LCR_EXT[0]=1) is enabled, this bit is used to indicate that the 9th bit of the receive data is set to 1. [8:8] read-only read Character_is_Address Indicates that the character is an address. 1 Character_is_Data Indicates that the character is data. 0 RESERVED1 reserved1 [31:9] read-only MSR Modem Status Register 0x18 32 read-only 0x00000000 0xFF DCTS This is used to indicate that the modem control line cts_n has changed since the last time the MSR was read [0:0] read-only change_on_cts_n read No_Change no change on cts_n since last read of MSR 0 Change change on cts_n since last read of MSR 1 DDSR This is used to indicate that the modem control line dsr_n has changed since the last time the MSR was read [1:1] read-only Change_on_dsr_n read No_Change no change on dsr_n since last read of MSR 0 Change change on dsr_n since last read of MSR 1 TERI This is used to indicate that a change on the input ri_n(from an active-low to an inactive-high state)has occurred since the last time the MSR was read [2:2] read-only Change_on_ri_n read No_Change no change on ri_n since last read of MSR 0 Change change on ri_n since last read of MSR 1 DDCD This is used to indicate that the modem control line dcd_n has changed since the last time the MSR was read [3:3] read-only Change_on_dcd_n read No_Change no change on dcd_n since last read of MSR 0 Change change on dcd_n since last read of MSR 1 CTS This is used to indicate the current state of the modem control line cts_n [4:4] read-only cts_n_Input read Deasserted cts_n input is de-asserted (logic 1) 0 Asserted cts_n input is asserted (logic 0) 1 DSR This is used to indicate the current state of the modem control line dsr_n [5:5] read-only dsr_n_Input read Deasserted dsr_n input is de-asserted (logic 1) 0 Asserted dsr_n input is asserted (logic 0) 1 RI This is used to indicate the current state of the modem control line ri_n [6:6] read-only ri_n_input read Deasserted ri_n input is de-asserted (logic 1) 0 Asserted ri_n input is asserted (logic 0) 1 DCD This is used to indicate the current state of the modem control line dcd_n [7:7] read-only dcd_n_input read Deasserted dcd_n input is de-asserted (logic 1) 0 Asserted dcd_n input is asserted (logic 0) 1 RESERVED1 reserved1 [31:8] read-only SCR Scratch pad Register 0x1C 32 read-write 0x00000000 0xFF SCRATCH_PAD This register is for programmers to use as a temporary storage space. It has no defined purpose [7:0] read-write RESERVED1 reserved1 [31:8] read-only LPDLL Low Power Divisor Latch Low Register 0x20 32 read-write 0x00000000 0xFF LPDLL This register makes up the lower 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K [7:0] read-write RESERVED1 reserved1 [31:8] read-write LPDLH Low Power Divisor Latch High Register 0x24 32 read-write 0x00000000 0xFF LPDLH This register makes up the upper 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115200 [7:0] read-write RESERVED1 reserved1 [31:8] read-write SRBR Shadow Receive Buffer Register STHR 0x30 32 read-only 0x00000000 0xFF SRBR_LSB_8_Bits This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode [7:0] read-only SRBR_MSB_9th_Bit This is a shadow register for the RBR[8] bit.It is applicable only when UART_9BIT_DATA_EN=1. [8:8] read-only RESERVED1 reserved1 [31:9] read-only STHR Transmit Holding Register SRBR 0x30 32 write-only 0x00000000 0xFF STHR_LSB_8_Bits Data to be transmitted on serial output port [7:0] write-only STHR_MSB_9th_Bit This is a shadow register for the THR[8] bit.It is applicable only when UART_9BIT_DATA_EN=1 [8:8] write-only RESERVED1 reserved1 [31:9] write-only FAR This register is use to enable a FIFO access mode for testing, 0x70 32 read-write 0x00000000 0xFF FIFO_Access This register is use to enable a FIFO access mode for testing, [0:0] read-write RESERVED1 reserved1 [31:1] read-only TFR Reading this register gives the data at the top of the transmit FIFO.Each consecutive read pops the transmit FIFO and gives next data in FIFO 0x74 32 read-only 0x00000000 TX_FIFO_RD Transmit FIFO Read [7:0] read-only RESERVED1 reserved1 [31:8] read-only RFW none 0x78 32 read-write 0x00000000 RFWD Receive FIFO Write Data [7:0] write-only RFPE Receive FIFO Parity Error [8:8] write-only RFFE Receive FIFO Framing Error [9:9] write-only RESERVED1 reserved1 [31:10] read-only USR UART Status Register 0x7C 32 read-only 0x00000000 BUSY Indicates that a serial transfer is in progress [0:0] read-only read UART_IDLE UART is idle or inactive 0 UART_BUSY UART is busy (actively transferring data) 1 TFNF To Indicate that the transmit FIFO is not full [1:1] read-only read Transmit_FIFO_Full Transmit FIFO is full 0 Transmit_FIFO_Not_Full Transmit FIFO is not full 1 TFE To Indicate that the transmit FIFO is completely empty [2:2] read-only read Transmit_FIFO_Empty Transmit FIFO is not empty 0 Transmit_FIFO_Empty Transmit FIFO is empty 1 RFNE To Indicate that the receive FIFO contains one or more entries [3:3] read-only read Receive_FIFO_Empty Receive FIFO is empty 0 Receive FIFO_Not_Empty Receive FIFO is not empty 1 RFE To Indicate that the receive FIFO is completely full [4:4] read-only read Receive_FIFO_Not_Full Receive FIFO not full 0 Receive_FIFO_Full Receive FIFO Full 1 RESERVED1 reserved1 [31:5] read-only TFL Transmit FIFO Level 0x80 32 read-only 0x00000000 Transmit_FIFO_Level Transmit FIFO Level. This is indicates the number of data entries in the transmit FIFO. [29:0] read-only RESERVED1 reserved1 [31:30] read-only RFL Receive FIFO Level 0x84 32 read-only 0x00000000 Receive_FIFO_Level Receive FIFO Level. This is indicates the number of data entries in the receive FIFO. [29:0] read-only RESERVED1 reserved1 [31:30] read-only SRR Software Reset Register 0x88 32 read-write 0x00000000 UR UART Reset [0:0] write-only RFR RCVR FIFO Reset [1:1] write-only XFR XMIT FIFO Reset [2:2] write-only RESERVED1 reserved1 [31:3] read-only SRTS Shadow Request to Send 0x8C 32 read-write 0x00000000 0xF SRTS Shadow Request to Send. [0:0] read-write RESERVED1 reserved1 [31:1] read-only SBCR Shadow Break Control Register 0x90 32 read-write 0x00000000 0xF SBCR Shadow Break Control Bit [0:0] read-write RESERVED1 reserved1 [31:1] read-only SDMAM Shadow DMA Mode 0x94 32 read-write 0x00000000 0xF SDMAM Shadow DMA Mode [0:0] read-write MODE0 mode 0 0 MODE1 mode 1 1 RESERVED1 reserved1 [31:1] read-only SFE Shadow FIFO Enable 0x98 32 read-write 0x00000000 0xF Shadow_FIFO_En Shadow FIFO Enable [0:0] read-write RESERVED1 reserved1 [31:1] read-only SRT Shadow RCVR Trigger 0x9C 32 read-write 0x00000000 0xF SRCVRT Shadow RCVR Trigger [0:0] read-write 1_Character_in_FIFO 1 Character in FIFO 0 FIFO_1_4th_Full FIFO 1/4th Full 1 FIFO_Half_Full FIFO 1/2 Full 2 FIFO_2_Less_than_Full FIFO 2 Less than Full 3 RESERVED1 reserved1 [31:1] read-only STET Shadow TX Empty Trigger 0xA0 32 read-write 0x00000000 0xF STXET Shadow TX Empty Trigger [1:0] read-write FIFO_Empty FIFO Empty 0 2_Characters_in_FIFO 2 Characters in FIFO 1 FIFO_1_4th_Full FIFO 1/4th Full 2 FIFO_Half_Full FIFO 1/2 Full 3 RESERVED1 reserved1 [31:2] read-only HTX Halt Transmit 0xA4 32 read-write 0x00000000 0x01 HALT_TX This register is use to halt transmissions for testing [0:0] read-write Halt_TX Disabled Halt TX disabled 0 Enabled Halt TX enabled 1 RESERVED1 reserved1 [31:1] read-only DMASA DMA Software Acknowledge 0xA8 32 read-write 0x00000000 0x01 DMA_SOFTWARE_ACK This register is use to perform a DMA software acknowledge if a transfer needs to be terminated due to an error condition [0:0] write-only RESERVED1 reserved1 [31:1] read-only TCR Transceiver Control Register. 0xAC 32 read-write 0x00000006 RS485_EN RS485 Transfer Enable. [0:0] read-write RE_POL Receiver Enable Polarity. [1:1] read-write RE_Signal Active_Low RE signal is active low 0 Active_High RE signal is active high 1 DE_POL Driver Enable Polarity. [2:2] read-write DE_Signal Active_Low DE signal is active low 0 Active_High DE signal is active high 1 XFER_MODE Transfer Mode. [4:3] read-write RESERVED1 reserved1 [31:5] read-only DE_EN Driver Output Enable Register. 0xB0 32 read-write 0x00000000 DE_EN DE Enable control. [0:0] read-write DE_Signal Deassert De-assert 'de' signal 0 Assert Assert 'de' signal 1 RESERVED1 reserved1 [31:1] read-only RE_EN Receiver Output Enable Register. 0xB4 32 read-write 0x00000000 RE_EN RE Enable control. [0:0] read-write RE_Signal Deassert De-assert 're' signal 0 Assert Assert 're' signal 1 RESERVED1 reserved1 [31:1] read-only DET Driver Output Enable Timing Register. 0xB8 32 read-write 0x00000000 DE_ASSERT_TIME Driver enable assertion time. [7:0] read-write RESERVED0 reserved. [15:8] read-only DE_DE_ASSERT_TIME Driver enable de-assertion time. [23:16] read-write RESERVED1 reserved1 [31:24] read-only TAT TurnAround Timing Register 0xBC 32 read-write 0x00000000 DE_RE Driver Enable to Receiver Enable TurnAround time. [15:0] read-write RE_DE Receiver Enable to Driver Enable TurnAround time. [31:16] read-write DLF Divisor Latch Fraction Register. 0xC0 32 read-write 0x00000000 DLF_Val Fractional part of divisor. [5:0] read-write RESERVED1 reserved1 [31:6] read-only RAR Receive Address Register. 0xC4 32 read-write 0x00000000 RAR This is an address matching register during receive mode. [7:0] read-write RESERVED1 reserved1 [31:8] read-only TAR Transmit Address Register. 0xC8 32 read-write 0x00000000 TAR This is an address matching register during transmit mode. [7:0] read-write RESERVED1 reserved1 [31:8] read-only LCR_EXT Line Extended Control Register 0xCC 32 read-write 0x00000000 DLS_E Extension for DLS. [0:0] read-write ADDR_MATCH Address Match Mode. [1:1] read-write SEND_ADDR Send address control bit. [2:2] read-write TRANSMIT_MODE Transmit mode control bit. [3:3] read-write RESERVED1 reserved1 [31:4] read-only CPR Component Parameter Register 0xF4 32 read-only 0X000125F2 APB_DATA_WIDTH APB data width register. [1:0] read-only APB_DATA_WIDTH read 8_BIT APB Data Width 8 BIT 0 16_BIT APB Data Width 16 BIT 1 32_BIT APB Data Width 32 BIT 2 RESERVED Reserved 2 RESERVED1 reserved1 [3:2] read-only AFCE_MODE none [4:4] read-only AFCE_MODE read TRUE True 1 FALSE False 0 THRE_MODE none [5:5] read-only THRE_MODE read TRUE True 1 FALSE False 0 SIR_MODE none [6:6] read-only SIR_MODE read TRUE True 1 FALSE False 0 SIR_LP_MODE none [7:7] read-only SIR_LP_MODE read TRUE True 1 FALSE False 0 ADDITIONAL_FEAT none [8:8] read-only ADDITIONAL_FEAT read TRUE True 1 FALSE False 0 FIFO_ACCESS none [9:9] read-only FIFO_ACCESS read TRUE True 1 FALSE False 0 FIFO_STAT none [10:10] read-only FIFO_STAT read TRUE True 1 FALSE False 0 SHADOW none [11:11] read-only SHADOW read TRUE True 1 FALSE False 0 UART_ADD_ENCODED_PARAMS none [12:12] read-only UART_ADD_ENCODED_PARAMS read TRUE True 1 FALSE False 0 DMA_EXTRA none [13:13] read-only DMA_EXTRA read TRUE True 1 FALSE False 0 RESERVED2 reserved2 [15:14] read-only FIFO_MODE none [23:16] read-only RESERVED3 reserved3 [31:24] read-only UCV UART Component Version 0xF8 32 read-only 0x3430302A UART_COMP_VER This register contains UART Component Version. [31:0] read-only CTR Component Type Register,This register contains the peripherals identification code 0xFC 32 read-only 0x44570110 UART_COMP_VER This register contains the peripherals identification code. [31:0] read-only GSPI_Master 1.0 GSPI, or Generic SPI, is a module which has been derived from QSPI. GSPI can act only as a master GSPI 0x45030000 32 read-write 0 0xc0 registers GSPI0 46 GSPI_CLK_CONFIG GSPI Clock Configuration Register 0x00 32 read-write 0x00000004 0xFFFFFFFF GSPI_CLK_SYNC If the clock frequency to FLASH (spi_clk) and SOC clk is same. [0:0] read-write Disable Divided SOC clock is connected SCLK. Division value is programmable 0 Enable SCLK clock and SOC clock are same 1 GSPI_CLK_EN GSPI clock enable [1:1] read-write Disable Dynamic clock gating is enabled in side GSPI controller 0 Enable Full time clock is enabled for GSPI controller. 1 RESERVED1 reserved for future use [31:2] read-write GSPI_BUS_MODE GSPI Bus Mode Register 0x04 32 read-write 0x00000000 0x7FF GSPI_DATA_SAMPLE_EDGE Samples MISO data on clock edges. This should be ZERO for mode3 clock [0:0] read-write Disable Pos edge of loop back spi_pad_clk 0 Enable Neg edge of loop back spi_pad_clk 1 GSPI_CLK_MODE_CSN0 NONE [1:1] read-write Disable Mode 0, GSPI_CLK is low when GSPI_CS is high for chip select0 (csn0) 0 Enable Mode 3, GSPI_CLK is high when GSPI_CS is high for chip select0 (csn0) 1 GSPI_CLK_MODE_CSN1 NONE [2:2] read-write Disable Mode 0, GSPI_CLK is low when GSPI_CS is high for chip select1 (csn1) 0 Enable Mode 3, GSPI_CLK is high when GSPI_CS is high for chip select1 (csn1) 1 GSPI_CLK_MODE_CSN2 NONE [3:3] read-write Disable Mode 0, GSPI_CLK is low when GSPI_CS is high for chip select2 (csn2) 0 Enable Mode 3, GSPI_CLK is high when GSPI_CS is high for chip select2 (csn2) 1 GSPI_CLK_MODE_CSN3 NONE [4:4] read-write Disable Mode 0, GSPI_CLK is low when GSPI_CS is high for chip select3 (csn3) 0 Enable Mode 3, GSPI_CLK is high when GSPI_CS is high for chip select3 (csn3) 1 GSPI_GPIO_MODE_ENABLES These bits are used to map GSPI on GPIO pins [10:5] read-write SPI_HIGH_PERFORMANCE_EN High performance features are enabled when this bit is set to one [11:11] read-write RESERVED1 reserved for future use [31:12] read-write GSPI_CONFIG1 GSPI Configuration 1 Register 0x10 32 read-write 0x00000001 0xFFFF GSPI_MANUAL_CSN SPI CS in manual mode [0:0] read-write GSPI_MANUAL_WR Write enable for manual mode when CS is low. [1:1] read-write GSPI_MANUAL_RD Read enable for manual mode when CS is low [2:2] read-write GSPI_MANUAL_RD_CNT Indicates total number of bytes to be read [12:3] read-write GSPI_MANUAL_CSN_SELECT Indicates which CSn is valid. Can be programmable in manual mode [14:13] read-write SPI_FULL_DUPLEX_EN Full duplex mode enable [15:15] read-write Disable Full duplex mode disabled. 0 Enable Full duplex mode enabled 1 RESERVED1 reserved for future use [31:16] read-write GSPI_CONFIG2 GSPI Manual Configuration 2 Register 0x14 32 read-write 0x000001F0 0xFFF GSPI_WR_DATA_SWAP_MNL_CSN0 Swap the write data inside the GSPI controller it-self. [0:0] read-write Disable Manual write data swap is disabled for csn0. 0 Enable Manual write data swap is enabled for csn0. 1 GSPI_WR_DATA_SWAP_MNL_CSN1 Swap the write data inside the GSPI controller it-self. [1:1] read-write Disable Manual write data swap is disabled for csn1 0 Enable Manual write data swap is enabled for csn1 1 GSPI_WR_DATA_SWAP_MNL_CSN2 Swap the write data inside the GSPI controller it-self. [2:2] read-write Disable Manual write data swap is disabled for csn2 0 Enable Manual write data swap is enabled for csn2 1 GSPI_WR_DATA_SWAP_MNL_CSN3 Swap the write data inside the GSPI controller it-self. [3:3] read-write Disable Manual write data swap is disabled for csn3 0 Enable Manual write data swap is enabled for csn3 1 GSPI_RD_DATA_SWAP_MNL_CSN0 Swap the read data inside the GSPI controller it-self. [4:4] read-write Disable Manual read data swap is disabled for csn0 0 Enable Manual read data swap is enabled for csn0 1 GSPI_RD_DATA_SWAP_MNL_CSN1 Swap the read data inside the GSPI controller it-self. [5:5] read-write Disable Manual read data swap is disabled for csn1 0 Enable Manual read data swap is enabled for csn1 1 GSPI_RD_DATA_SWAP_MNL_CSN2 Swap the read data inside the GSPI controller it-self. [6:6] read-write Disable Manual read data swap is disabled for csn2 0 Enable Manual read data swap is enabled for csn2 1 GSPI_RD_DATA_SWAP_MNL_CSN3 Swap the read data inside the GSPI controller it-self. [7:7] read-write Disable Manual read data swap is disabled for csn3 0 Enable Manual read data swap is enabled for csn3 1 GSPI_MANUAL_SIZE_FRM_REG Manual reads and manual writes [8:8] read-write Disable 1 Byte 8 bit mode 0 Enable 2 Bytes 16 bit mode 1 RESERVED1 reserved for future use [9:9] read-write TAKE_GSPI_MANUAL_WR_SIZE_FRM_REG NONE [10:10] read-write Disable No action 0 Enable Take write size from Manual config register1[20:19] 1 RESERVED2 reserved for future use [31:11] read-write GSPI_WRITE_DATA2 GSPI Write Data 2 Register 0x18 32 read-write 0x00000000 0x8F GSPI_MANUAL_WRITE_DATA2 Number of bits to be written in write mode [3:0] read-write RESERVED1 reserved for future use [6:4] read-write USE_PREV_LENGTH Use previous length [7:7] read-write Disable No action 0 Enable Uses previously programmed length in [3:0] of this register for next writes 1 RESERVED2 reserved for future use [31:8] read-write GSPI_FIFO_THRLD GSPI FIFO Threshold Register 0x1C 32 read-write 0x000000C7 0x3FF FIFO_AEMPTY_THRLD FIFO almost empty threshold [3:0] read-write FIFO_AFULL_THRLD FIFO almost full threshold [7:4] read-write WFIFO_RESET Write FIFO reset [8:8] read-write RFIFO_RESET read FIFO reset [9:9] read-write RESERVED1 reserved for future use [31:10] read-write GSPI_STATUS GSPI Status Register 0x20 32 read-only 0x00000588 0x7FF GSPI_BUSY State of Manual mode [0:0] read-only Disable GSPI controller is IDLE in Manual mode. 0 Enable A read, write or dummy cycle operation is in process in manual mode 1 FIFO_FULL_WFIFO_S Full status indication for Wfifo in manual mode [1:1] read-only FIFO_AFULL_WFIFO_S Almost full status indication for Wfifo in manual mode [2:2] read-only FIFO_EMPTY_WFIFO Empty status indication for Wfifo in manual mode [3:3] read-only RESERVED1 reserved for future use [4:4] read-only FIFO_FULL_RFIFO Full status indication for Rfifo in manual mode [5:5] read-only RESERVED2 reserved for future use [6:6] read-only FIFO_EMPTY_RFIFO_S Empty status indication for Rfifo in manual mode [7:7] read-only FIFO_AEMPTY_RFIFO_S Aempty status indication for Rfifo in manual mode [8:8] read-only GSPI_MANUAL_RD_CNT This is a result of 10 bits ORing counter [9:9] read-only Disable No read transactions are in pending 0 Enable Read transactions are in pending ( to be done) 1 GSPI_MANUAL_CSN Provide the status of chip select signal [10:10] read-only Disable Active 0 Enable Inactive 1 RESERVED3 reserved for future use [31:11] read-only GSPI_INTR_MASK GSPI Interrupt Mask Register 0x24 32 read-write 0x00000000 0x7F GSPI_INTR_MASK GSPI Interrupt mask bit [0:0] read-write Disable Do not touch 0 Enable mask the GSPI intr 1 FIFO_AEMPTY_RFIFO_MASK NONE [1:1] read-write Disable Do not touch 0 Enable Read fifo almost empty intr mask. 1 FIFO_AFULL_RFIFO_MASK NONE [2:2] read-write Disable Do not touch 0 Enable read fifo almost full intr mask 1 FIFO_AEMPTY_WFIFO_MASK NONE [3:3] read-write Disable Do not touch 0 Enable write fifo almost empty intr mask 1 FIFO_AFULL_WFIFO_MASK NONE [4:4] read-write Disable Do not touch 0 Enable Write fifo almost full intr mask. 1 FIFO_FULL_WFIFO_MASK NONE [5:5] read-write Disable Do not touch 0 Enable write fifo full intr mask. 1 FIFO_EMPTY_RFIFO_MASK NONE [6:6] read-write Disable Do not touch 0 Enable Read fifo is empty intr mask 1 RESERVED1 reserved for future use [31:7] read-write GSPI_INTR_UNMASK GSPI Interrupt Unmask Register 0x28 32 read-write 0x00000000 0x7F GSPI_INTR_UNMASK GSPI Interrupt unmask bit [0:0] read-write Disable Do not touch 0 Enable unmask the GSPI intr 1 FIFO_AEMPTY_RFIFO_UNMASK NONE [1:1] read-write Disable Do not touch 0 Enable Read fifo almost empty intr unmask. 1 FIFO_AFULL_RFIFO_UNMASK NONE [2:2] read-write Disable Do not touch 0 Enable read fifo almost full intr unmask. 1 FIFO_AEMPTY_WFIFO_UNMASK NONE [3:3] read-write Disable Do not touch 0 Enable write fifo almost empty intr unmask 1 FIFO_AFULL_WFIFO_UNMASK NONE [4:4] read-write Disable Do not touch 0 Enable Write fifo almost full intr unmask. 1 FIFO_FULL_WFIFO_UNMASK NONE [5:5] read-write Disable Do not touch 0 Enable write fifo full intr unmask. 1 FIFO_EMPTY_RFIFO_UNMASK NONE [6:6] read-write Disable Do not touch 0 Enable Read fifo is empty intr unmask 1 RESERVED1 reserved for future use [31:7] read-write GSPI_INTR_STS GSPI Interrupt Status Register 0x2C 32 read-only 0x00000042 0x7F GSPI_INTR_LVL GSPI Interrupt status bit [0:0] read-only Disable no interrupt 0 Enable GSPI raised a interrupt 1 FIFO_AEMPTY_RFIFO_LVL NONE [1:1] read-only Disable Read fifo does not reach almost empty threshold. 0 Enable Read fifo reached almost empty threshold 1 RESERVED1 reserved for future use [3:2] read-only FIFO_AFULL_WFIFO_LVL NONE [4:4] read-only Disable Write fifo not reached almost full threshold 0 Enable Write fifo almost full threshold 1 FIFO_FULL_WFIFO_LVL NONE [5:5] read-only Disable write fifo not full 0 Enable write fifo full 1 FIFO_EMPTY_RFIFO_LVL NONE [6:6] read-only Disable Read fifo is not empty 0 Enable Read fifo is empty 1 RESERVED2 reserved for future use [31:7] read-only GSPI_INTR_ACK GSPI Interrupt Acknowledge Register 0x30 32 write-only 0x00000000 0x7F GSPI_INTR_ACK GSPI Interrupt status bit [0:0] write-only Disable Do not touch 0 Enable GSPI intr ack. 1 FIFO_AEMPTY_RFIFO_ACK NONE [1:1] write-only Disable Do not touch 0 Enable Read fifo almost empty intr ack 1 RESERVED1 reserved1 [3:2] write-only FIFO_AFULL_WFIFO_ACK NONE [4:4] write-only Disable Do not touch 0 Enable Write fifo almost full intr ack 1 FIFO_FULL_WFIFO_ACK NONE [5:5] write-only Disable Do not touch 0 Enable write fifo full intr ack 1 FIFO_EMPTY_RFIFO_ACK NONE [6:6] write-only Disable Do not touch 0 Enable Read fifo is empty intr ack 1 RESERVED2 reserved2 [31:7] write-only GSPI_STS_MC GSPI State Machine Monitor Register 0x34 32 read-only 0x00000000 0xF BUS_CTRL_PSTATE Provides SPI bus controller present state [2:0] read-only SPI_RD_CNT number of pending bytes to be read by device [15:3] read-only RESERVED1 reserved1 [31:16] read-only GSPI_CLK_DIV GSPI Clock Division Factor Register 0x38 32 read-write 0x00000000 0xFF GSPI_CLK_DIV_FACTOR Provides GSPI clock division factor to the clock divider, which takes SOC clock as input clock and generates required clock according to division factor [7:0] read-write RESERVED1 reserved1 [31:8] read-only GSPI_CONFIG3 GSPI Configuration 3 Register 0x3C 32 read-write 0x00000000 SPI_MANUAL_RD_LNTH_TO_BC Bits are used to indicate the total number of bytes to read from flash during read operation [14:0] read-write RESERVED1 reserved1 [31:15] read-write 16 0x4 GSPI_WRITE_FIFOn GSPI FIFO 0 to 16 GSPI_READ_FIFOn 0x80 GSPI_WRITE_FIFO_n_ GSPI Fifo _n_ 0x00 32 write-only 0x00000000 0xFFFFFFFF WRITE_FIFO FIFO data is write to this address space [31:0] write-only 16 0x4 GSPI_READ_FIFOn GSPI FIFO 0 to 16 GSPI_WRITE_FIFOn 0x80 GSPI_READ_FIFO_n_ GSPI READ FIFO 0x00 32 read-only 0x00000000 0xFFFFFFFF READ_FIFO FIFO data is read from this address space [31:0] read-only SSI_Master 1.0 Synchronous Serial Interface(SSI) SSI 0x44020000 32 read-write 0 0xF8 registers SSI0 47 CTRLR0 Control Register 0 0x00 32 read-write 0x00070007 0xFFFFFFFF DFS Select the data frame length (4-bit to 16-bit serial data transfers) [3:0] read-write 0 16 FRF Frame Format, Selects which serial protocol transfers the data [5:4] read-write Motorola_SPI Motorola SPI 0 Texas_Instruments_SSP Texas Instruments SSP 1 National_Semi_Conductors_Micro_Wire National Semiconductors Micro wire 2 Reserved none 3 SCPH Serial Clock Phase. Valid when the frame format (FRF) is set to Motorola SPI [6:6] read-write disable Serial clock toggles in middle of first data bit 0 enable Serial clock toggles at start of first data bit 1 SCPOL Serial Clock Polarity. Valid when the frame format (FRF) is set to Motorola SPI [7:7] read-write Serial_Clock_Inactive_State Inactive_State_Low Inactive state of serial clock is low 0 Inactive_State_High Inactive state of serial clock is high 1 TMOD Selects the mode of transfer for serial communication [9:8] read-write Transmit_and_Receive Transmit and Receive 0 Transmit Transmit Only 1 Receive Receive Only 2 RESERVED0 Reserved [10:10] read-write SRL Shift Register Loop Used for testing purposes only [11:11] read-write Normal_Mode_Operation Normal Mode Operation 0 Test_Mode_Operation Test Mode Operation 1 CFS Control Frame Size Selects the length of the control word for the Micro wire frame format [15:12] read-write 1_Bit_Word_Control Range -> 1 bit 0 16_Bit_Word_Control Range -> 16 bit 15 DFS_32 Selects the data frame length [20:16] read-write Data_Frame_Length 4_Bit Range -> 3 bit 3 16_Bit Range -> 16 bit 15 SPI_FRF Selects data frame format for transmitting or receiving data [22:21] read-write SPI_Frame_Format Standard_SPI Standard SPI Format 0 Dual_SPI Dual SPI Format 1 Quad_SPI Quad SPI Format 2 Reserved Reserved 3 RESERVED1 Reserved for future use [31:23] read-write CTRLR1 Control Register 1 0x04 32 read-write 0x00000000 0xFFFF NDF Number of Data Frames.When TMOD = 10 or TMOD = 11, this register field sets the number of data frames to be continuously received by the ssi_master [15:0] read-write RESERVED0 Reserved for future use. [31:16] read-write SSIENR SSI Enable Register 0x08 32 read-write 0x00000000 0x1 SSI_EN Enables and disables all ssi operations [0:0] read-write RESERVED1 Reserved for future use [31:1] read-write MWCR Micro wire Control Register 0x0C 32 read-write 0x00000000 0xF MWMOD The Micro wire transfer is sequential or non-sequential [0:0] read-write Non_Sequential_Transfer non-sequential transfer 0 Sequential_Transfer sequential transfer 1 MDD The direction of the data word when the Micro wire serial protocol is used [1:1] read-write disable the data word is received by the SSI MacroCell from the external serial device 0 enable the data word is transmitted from the SSI MacroCell to the external serial device 1 MHS Microwire Handshaking. Used to enable and disable the busy/ready handshaking interface for the Microwire protocol [2:2] read-write Hand_Shaking_Interface disable handshaking interface is disabled 0 enable handshaking interface is enabled 1 RESERVED1 Reserved for future use [31:3] read-write SER SLAVE ENABLE REGISTER 0x10 32 read-write 0x00000000 0x0F SER Each bit in this register corresponds to a slave select line (ss_x_n) from the SSI master. [3:0] read-write RESERVED1 Reserved for future use [31:4] read-write BAUDR Baud Rate Select Register 0x14 32 read-write 0x00000000 0xFFFF SCKDV SSI Clock Divider.The LSB for this field is always set to 0 and is unaffected by a write operation, which ensures an even value is held in this register [15:0] read-write RESERVED1 Reserved for future use [31:16] read-write TXFTLR Transmit FIFO Threshold Level Register 0x18 32 read-write 0x00000000 0xF TFT Controls the level of entries (or below) at which the transmit FIFO controller triggers an interrupt [3:0] read-write RESERVED1 Reserved for future use [31:4] read-write RXFTLR Receive FIFO Threshold Level 0x1C 32 read-write 0x00000000 0xF RFT Controls the level of entries (or above) at which the receive FIFO controller triggers an interrupt [3:0] read-write RESERVED1 Reserved for future use [31:4] read-write TXFLR Transmit FIFO Level Register 0x20 32 read-only 0x00000000 TXTFL Contains the number of valid data entries in the transmit FIFO [4:0] read-only RESERVED1 Reserved for future use [31:5] read-only RXFLR Receive FIFO Level Register 0x24 32 read-only 0x00000000 RXTFL Contains the number of valid data entries in the receive FIFO [4:0] read-only RESERVED1 Reserved for future use [31:5] read-only SR Status Register 0x28 32 read-only 0x00000006 BUSY indicates that a serial transfer is in progress [0:0] read-only SSI_Busy_Flag Idle SSI is idle or disabled 0 Transferring_Data SSI is actively transferring data 1 TFNF Set when the transmit FIFO contains one or more empty locations and is cleared when the FIFO is full [1:1] read-only Transmit_FIFO_Full Transmit FIFO is full 0 Transmit_FIFO_Not_Full Transmit FIFO is not full 1 TFE When the transmit FIFO is completely empty this bit is set [2:2] read-only Transmit_FIFO_Not_Empty Transmit FIFO is not empty 0 Transmit_FIFO_Empty Transmit FIFO is empty 1 RFNE Set when the receive FIFO contains one or more entries and is cleared when the receive FIFO is empty [3:3] read-only Receive_FIFO_Empty Receive FIFO is empty 0 Receive_FIFO_Not_Empty Receive FIFO is not empty 1 RFF When the receive FIFO is completely full this bit is set [4:4] read-only Receive_FIFO_Not_Full Receive FIFO is not full 0 Receive_FIFO_Full Receive FIFO is full 1 RESERVED0 Reserved [5:5] read-only DCOL This bit is set if the ss_in_n input is asserted by another master, while the ssi master is in the middle of the transfer [6:6] read-only Data_Collision_Error No_Error No error 0 Transmit_Data_Collection_Error Transmit data collision error 1 RESERVED1 Reserved for future use [31:7] read-only IMR Interrupt Mask Register 0x2C 32 read-write 0x0000003F 0x3F TXEIM Transmit FIFO Empty Interrupt Mask [0:0] read-write ssi_txe_intr Masked ssi_txe_intr interrupt is masked 0 Not_Masked ssi_txe_intr interrupt is not masked 1 TXOIM Transmit FIFO Overflow Interrupt Mask [1:1] read-write ssi_txo_intr Masked ssi_txo_intr interrupt is masked 0 Non_Masked ssi_txo_intr interrupt is not masked 1 RXUIM Receive FIFO Underflow Interrupt Mask [2:2] read-write ssi_rxu_intr Masked ssi_rxu_intr interrupt is masked 0 Not_Masked ssi_rxu_intr interrupt is not masked 1 RXOIM Receive FIFO Overflow Interrupt Mask [3:3] read-write ssi_rxo_intr Masked ssi_rxo_intr interrupt is masked 0 Not_Masked ssi_rxo_intr interrupt is not masked 1 RXFIM Receive FIFO Full Interrupt Mask [4:4] read-write ssi_rxf_intr Masked ssi_rxf_intr interrupt is masked 0 Not_Masked ssi_rxf_intr interrupt is not masked 1 MSTIM Multi-Master Contention Interrupt Mask [5:5] read-write ssi_mst_intr Masked ssi_mst_intr interrupt is masked 0 Not_Masked ssi_mst_intr interrupt is not masked 1 RESERVED1 Reserved for future use [31:6] read-only ISR Interrupt Status Register 0x30 32 read-only 0x00000000 TXEIS Transmit FIFO Empty Interrupt Status [0:0] read-only ssi_txe_intr_After_Masking Not_Active ssi_txe_intr interrupt is not active after masking 0 Active ssi_txe_intr interrupt is active after masking 1 TXOIS Transmit FIFO Overflow Interrupt Status [1:1] read-only ssi_txo_intr_After_Masking Not_Active ssi_txo_intr interrupt is not active after masking 0 Active ssi_txo_intr interrupt is active after masking 1 RXUIS Receive FIFO Underflow Interrupt Status [2:2] read-only ssi_rxu_intr_After_Masking Not_Active ssi_rxu_intr interrupt is not active after masking 0 Active ssi_rxu_intr interrupt is active after masking 1 RXOIS Receive FIFO Overflow Interrupt Status [3:3] read-only ssi_rxo_intr_After_Masking Not_Active ssi_rxo_intr interrupt is not active after masking 0 Active ssi_rxo_intr interrupt is active after masking 1 RXFIS Receive FIFO Full Interrupt Status [4:4] read-only ssi_rxf_intr_After_Masking Not_Active ssi_rxf_intr interrupt is not active after masking 0 Full ssi_rxf_intr interrupt is full after masking 1 MSTIS Multi-Master Contention Interrupt Status [5:5] read-only ssi_mst_intr_After_Masking Not_Active ssi_mst_intr interrupt not active after masking 0 Active ssi_mst_intr interrupt is active after masking 1 RESERVED1 Reserved for future use [31:6] read-only RISR Raw Interrupt Status Register 0x34 32 read-only 0x00000000 TXEIR Transmit FIFO Empty Raw Interrupt Status [0:0] read-only ssi_txe_intr_Prior_Masking Not_Active ssi_txe_intr interrupt is not active prior to masking 0 Active ssi_txe_intr interrupt is active prior masking 1 TXOIR Transmit FIFO Overflow Raw Interrupt Status [1:1] read-only ssi_txo_intr_Prior_Masking Not_Active ssi_txo_intr interrupt is not active prior to masking 0 Active 1 => ssi_txo_intr interrupt is active prior masking 1 RXUIR Receive FIFO Underflow Raw Interrupt Status [2:2] read-only ssi_rxu_intr_Prior_Masking Not_Active ssi_rxu_intr interrupt is not active prior to masking 0 Active ssi_rxu_intr interrupt is active prior to masking 1 RXOIR Receive FIFO Overflow Raw Interrupt Status [3:3] read-only ssi_rxo_intr_Prior_Masking Not_Active ssi_rxo_intr interrupt is not active prior to masking 0 Active ssi_rxo_intr interrupt is active prior masking 1 RXFIR Receive FIFO Full Raw Interrupt Status [4:4] read-only ssi_rxf_intr_Prior_Masking Not_Active ssi_rxf_intr interrupt is not active prior to masking 0 Active ssi_rxf_intr interrupt is active prior to masking 1 MSTIR Multi-Master Contention Raw Interrupt Status [5:5] read-only ssi_mst_intr_Prior_Masking Not_Active ssi_mst_intr interrupt is not active prior to masking 0 Active ssi_mst_intr interrupt is active prior masking 1 RESERVED1 Reserved for future use [31:6] read-only TXOICR Transmit FIFO Overflow Interrupt Clear Register 0x38 32 read-only 0x00000000 TXOICR Clear Transmit FIFO Overflow Interrupt This register reflects the status of the interrupt [0:0] read-only RESERVED1 Reserved for future use [31:1] read-only RXOICR Receive FIFO Overflow Interrupt Clear Register 0x3C 32 read-only 0x00000000 RXOICR This register reflects the status of the interrupt A read from this register clears the ssi_rxo_intr interrupt [0:0] read-only RESERVED1 Reserved for future use [31:1] read-only RXUICR Receive FIFO Underflow Interrupt Clear Register 0x40 32 read-only 0x00000000 0x1 RXUICR This register reflects the status of the interrupt A read from this register clears the ssi_rxu_intr interrupt [0:0] read-only RESERVED1 Reserved for future use [31:1] read-only MSTICR Multi-Master Interrupt Clear Register 0x44 32 read-only 0x00000000 MSTICR This register reflects the status of the interrupt A read from this register clears the ssi_mst_intr interrupt [0:0] read-only RESERVED1 Reserved for future use [31:1] read-only ICR Interrupt Clear Register 0x48 32 read-only 0x00000000 ICR This register is set if any of the interrupts below are active A read clears the ssi_txo_intr, ssi_rxu_intr, ssi_rxo_intr, and the ssi_mst_intr interrupts [0:0] read-only RESERVED1 Reserved for future use [31:1] read-only DMACR DMA Control Register 0x4C 32 read-write 0x00000000 0x3 RDMAE This bit enables/disables the receive FIFO DMA channel [0:0] read-write Receive_DMA disabled Receive DMA disabled 0 enabled Receive DMA enabled 1 TDMAE This bit enables/disables the transmit FIFO DMA channel [1:1] read-write Transmit_DMA disabled Transmit DMA disabled 0 enabled Transmit DMA enabled 1 RESERVED1 Reserved for future use [31:2] read-only DMATDLR DMA Transmit Data Level 0x50 32 read-write 0x00000000 0xF DMATDL This bit field controls the level at which a DMA request is made by the transmit logic [3:0] read-write RESERVED1 Reserved for future use [31:4] read-only DMARDLR DMA Receive Data Level Register 0x54 32 read-write 0x00000000 0xF DMARDL This bit field controls the level at which a DMA request is made by the receive logic [3:0] read-write RESERVED1 Reserved for future use [31:4] read-write IDR Identification Register 0x58 32 read-only 0xFFFFFFFF 0xFFFFFFFF IDCODE This register contains the peripherals identification code [31:0] read-only SSI_COMP_VERSION coreKit version ID register 0x5C 32 read-only 0x3430302A 0xFFFFFFFF SSI_COMP_VERSION Contains the hex representation of the Synopsys component version [31:0] read-only DR Data Register 0x60 32 read-write 0x00000000 0xFFFF DR When writing to this register must right-justify the data [31:0] read-write RX_SAMPLE_DLY Rx Sample Delay Register 0xF0 32 read-write 0x00000000 0xFF RSD Receive Data (rxd) Sample Delay. This register is used to delay the sample of the rxd input signal. [7:0] read-write RESERVED1 Reserved for future use [31:8] read-write SPI_CTRLR0 SPI control Register 0xF4 32 read-write 0x00000200 0x7FFF TRANS_TYPE Address and instruction transfer format [1:0] read-write ADDR_L This bit defines length of address to be transmitted, The transfer begins only after these many bits are programmed into the FIFO [5:2] read-write RESERVED1 Reserved for future use [7:6] read-only INST_L DUAL/QUAD length in bits [9:8] read-write RESERVED2 Reserved for future use [10:10] read-only WAIT_CYCLES This bit defines the wait cycles in dual/quad mode between control frames transmit and data reception, Specified as number of SPI clock cycles [14:11] read-write RESERVED3 Reserved for future use [31:15] read-only SSI_Slave 1.0 Synchronous Serial Interface(SSI) SSI 0x45010000 32 read-write 0 0xF8 registers SSISlave 44 CTRLR0 Control Register 0 0x00 32 read-write 0x00000007 0xFFFF DFS Select the data frame length (4-bit to 16-bit serial data transfers) [3:0] read-write 0 16 FRF Frame Format, Selects which serial protocol transfers the data [5:4] read-write Motorola_SPI Motorola SPI 0 Texas_Instruments_SSP Texas Instruments SSP 1 National_Semi_Conductors_Micro_Wire National Semiconductors Micro wire 2 Reserved none 3 SCPH Serial Clock Phase. Valid when the frame format (FRF) is set to Motorola SPI [6:6] read-write disable Serial clock toggles in middle of first data bit 0 enable Serial clock toggles at start of first data bit 1 SCPOL Serial Clock Polarity. Valid when the frame format (FRF) is set to Motorola SPI [7:7] read-write Serial_Clock_Inactive_State Inactive_State_Low Inactive state of serial clock is low 0 Inactive_State_High Inactive state of serial clock is high 1 TMOD Selects the mode of transfer for serial communication [9:8] read-write Transmit_and_Receive Transmit and Receive 0 Transmit Transmit Only 1 Receive Receive Only 2 SLV_OE DW_apb_ssi is configured as a serial-slave device [10:10] read-write None Slave txd is enabled 0 none Slave txd is disabled 1 SRL Shift Register Loop Used for testing purposes only [11:11] read-write Normal_Mode_Operation Normal Mode Operation 0 Test_Mode_Operation Test Mode Operation 1 CFS Control Frame Size Selects the length of the control word for the Micro wire frame format [15:12] read-write 1_Bit_Word_Control Range -> 1 bit 0 16_Bit_Word_Control Range -> 16 bit 15 RESERVED1 Reserved for future use [31:16] read-write SSIENR SSI Enable Register 0x08 32 read-write 0x00000000 0x1 SSI_EN Enables and disables all ssi operations [0:0] read-write RESERVED1 Reserved for future use [31:1] read-write MWCR Micro wire Control Register 0x0C 32 read-write 0x00000000 0xF MWMOD The Micro wire transfer is sequential or non-sequential [0:0] read-write Non_Sequential_Transfer non-sequential transfer 0 Sequential_Transfer sequential transfer 1 MDD The direction of the data word when the Micro wire serial protocol is used [1:1] read-write disable the data word is received by the SSI MacroCell from the external serial device 0 enable the data word is transmitted from the SSI MacroCell to the external serial device 1 RESERVED1 Reserved for future use [31:2] read-write TXFTLR Transmit FIFO Threshold Level Register 0x18 32 read-write 0x00000000 0xF TFT Controls the level of entries (or below) at which the transmit FIFO controller triggers an interrupt [3:0] read-write RESERVED1 Reserved for future use [31:4] read-write RXFTLR Receive FIFO Threshold Level 0x1C 32 read-write 0x00000000 0xF RFT Controls the level of entries (or above) at which the receive FIFO controller triggers an interrupt [3:0] read-write RESERVED1 Reserved for future use [31:4] read-write TXFLR Transmit FIFO Level Register 0x20 32 read-only 0x00000000 TXTFL Contains the number of valid data entries in the transmit FIFO [4:0] read-only RESERVED1 Reserved for future use [31:5] read-only RXFLR Receive FIFO Level Register 0x24 32 read-only 0x00000000 RXTFL Contains the number of valid data entries in the receive FIFO [4:0] read-only RESERVED1 Reserved for future use [31:5] read-only SR Status Register 0x28 32 read-only 0x00000006 BUSY indicates that a serial transfer is in progress [0:0] read-only SSI_Busy_Flag read Idle SSI is idle or disabled 0 Transferring_Data SSI is actively transferring data 1 TFNF Set when the transmit FIFO contains one or more empty locations and is cleared when the FIFO is full [1:1] read-only read Transmit_FIFO_Full Transmit FIFO is full 0 Transmit_FIFO_Not_Full Transmit FIFO is not full 1 TFE When the transmit FIFO is completely empty this bit is set [2:2] read-only read Transmit_FIFO_Not_Empty Transmit FIFO is not empty 0 Transmit_FIFO_Empty Transmit FIFO is empty 1 RFNE Set when the receive FIFO contains one or more entries and is cleared when the receive FIFO is empty [3:3] read-only read Receive_FIFO_Empty Receive FIFO is empty 0 Receive_FIFO_Not_Empty Receive FIFO is not empty 1 RFF When the receive FIFO is completely full this bit is set [4:4] read-only read Receive_FIFO_Not_Full Receive FIFO is not full 0 Receive_FIFO_Full Receive FIFO is full 1 TXE Transmission Error [5:5] read-only read No_Error No error 0 Transmission_Error Transmission Error 1 RESERVED1 Reserved for future use [31:6] read-only IMR Interrupt Mask Register 0x2C 32 read-write 0x0000001F 0x1F TXEIM Transmit FIFO Empty Interrupt Mask [0:0] read-write ssi_txe_intr Masked ssi_txe_intr interrupt is masked 0 Not_Masked ssi_txe_intr interrupt is not masked 1 TXOIM Transmit FIFO Overflow Interrupt Mask [1:1] read-write ssi_txo_intr Masked ssi_txo_intr interrupt is masked 0 Non_Masked ssi_txo_intr interrupt is not masked 1 RXUIM Receive FIFO Underflow Interrupt Mask [2:2] read-write ssi_rxu_intr Masked ssi_rxu_intr interrupt is masked 0 Not_Masked ssi_rxu_intr interrupt is not masked 1 RXOIM Receive FIFO Overflow Interrupt Mask [3:3] read-write ssi_rxo_intr Masked ssi_rxo_intr interrupt is masked 0 Not_Masked ssi_rxo_intr interrupt is not masked 1 RXFIM Receive FIFO Full Interrupt Mask [4:4] read-write ssi_rxf_intr Masked ssi_rxf_intr interrupt is masked 0 Not_Masked ssi_rxf_intr interrupt is not masked 1 RESERVED1 Reserved for future use [31:5] read-only ISR Interrupt Status Register 0x30 32 read-only 0x00000000 TXEIS Transmit FIFO Empty Interrupt Status [0:0] read-only ssi_txe_intr_After_Masking read Not_Active ssi_txe_intr interrupt is not active after masking 0 Active ssi_txe_intr interrupt is active after masking 1 TXOIS Transmit FIFO Overflow Interrupt Status [1:1] read-only ssi_txo_intr_After_Masking read Not_Active ssi_txo_intr interrupt is not active after masking 0 Active ssi_txo_intr interrupt is active after masking 1 RXUIS Receive FIFO Underflow Interrupt Status [2:2] read-only ssi_rxu_intr_After_Masking read Not_Active ssi_rxu_intr interrupt is not active after masking 0 Active ssi_rxu_intr interrupt is active after masking 1 RXOIS Receive FIFO Overflow Interrupt Status [3:3] read-only ssi_rxo_intr_After_Masking read Not_Active ssi_rxo_intr interrupt is not active after masking 0 Active ssi_rxo_intr interrupt is active after masking 1 RXFIS Receive FIFO Full Interrupt Status [4:4] read-only ssi_rxf_intr_After_Masking read Not_Active ssi_rxf_intr interrupt is not active after masking 0 Full ssi_rxf_intr interrupt is full after masking 1 RESERVED1 Reserved for future use [31:5] read-only RISR Raw Interrupt Status Register 0x34 32 read-only 0x00000000 TXEIR Transmit FIFO Empty Raw Interrupt Status [0:0] read-only ssi_txe_intr_Prior_Masking read Not_Active ssi_txe_intr interrupt is not active prior to masking 0 Active ssi_txe_intr interrupt is active prior masking 1 TXOIR Transmit FIFO Overflow Raw Interrupt Status [1:1] read-only ssi_txo_intr_Prior_Masking read Not_Active ssi_txo_intr interrupt is not active prior to masking 0 Active 1 => ssi_txo_intr interrupt is active prior masking 1 RXUIR Receive FIFO Underflow Raw Interrupt Status [2:2] read-only ssi_rxu_intr_Prior_Masking read Not_Active ssi_rxu_intr interrupt is not active prior to masking 0 Active ssi_rxu_intr interrupt is active prior to masking 1 RXOIR Receive FIFO Overflow Raw Interrupt Status [3:3] read-only ssi_rxo_intr_Prior_Masking read Not_Active ssi_rxo_intr interrupt is not active prior to masking 0 Active ssi_rxo_intr interrupt is active prior masking 1 RXFIR Receive FIFO Full Raw Interrupt Status [4:4] read-only ssi_rxf_intr_Prior_Masking read Not_Active ssi_rxf_intr interrupt is not active prior to masking 0 Active ssi_rxf_intr interrupt is active prior to masking 1 RESERVED1 Reserved for future use [31:5] read-only TXOICR Transmit FIFO Overflow Interrupt Clear Register 0x38 32 read-only 0x00000000 TXOICR Clear Transmit FIFO Overflow Interrupt This register reflects the status of the interrupt [0:0] read-only RESERVED1 Reserved for future use [31:1] read-only RXOICR Receive FIFO Overflow Interrupt Clear Register 0x3C 32 read-only 0x00000000 RXOICR This register reflects the status of the interrupt A read from this register clears the ssi_rxo_intr interrupt [0:0] read-only RESERVED1 Reserved for future use [31:1] read-only RXUICR Receive FIFO Underflow Interrupt Clear Register 0x40 32 read-only 0x00000000 0x1 RXUICR This register reflects the status of the interrupt A read from this register clears the ssi_rxu_intr interrupt [0:0] read-only RESERVED1 Reserved for future use [31:1] read-only MSTICR Multi-Master Interrupt Clear Register 0x44 32 read-only 0x00000000 MSTICR This register reflects the status of the interrupt A read from this register clears the ssi_mst_intr interrupt [0:0] read-only RESERVED1 Reserved for future use [31:1] read-only ICR Interrupt Clear Register 0x48 32 read-only 0x00000000 ICR This register is set if any of the interrupts below are active A read clears the ssi_txo_intr, ssi_rxu_intr, ssi_rxo_intr, and the ssi_mst_intr interrupts [0:0] read-only RESERVED1 Reserved for future use [31:1] read-only DMACR DMA Control Register 0x4C 32 read-write 0x00000000 0x3 RDMAE This bit enables/disables the receive FIFO DMA channel [0:0] read-write Receive_DMA disabled Receive DMA disabled 0 enabled Receive DMA enabled 1 TDMAE This bit enables/disables the transmit FIFO DMA channel [1:1] read-write Transmit_DMA disabled Transmit DMA disabled 0 enabled Transmit DMA enabled 1 RESERVED1 Reserved for future use [31:2] read-only DMATDLR DMA Transmit Data Level 0x50 32 read-write 0x00000000 0xF DMATDL This bit field controls the level at which a DMA request is made by the transmit logic [3:0] read-write RESERVED1 Reserved for future use [31:4] read-only DMARDLR DMA Receive Data Level Register 0x54 32 read-write 0x00000000 0xF DMARDL This bit field controls the level at which a DMA request is made by the receive logic [3:0] read-write RESERVED1 Reserved for future use [31:4] read-write IDR Identification Register 0x58 32 read-only 0xFFFFFFFF 0xFFFFFFFF IDCODE This register contains the peripherals identification code [31:0] read-only SSI_COMP_VERSION coreKit version ID register 0x5C 32 read-only 0x3430302A 0xFFFFFFFF SSI_COMP_VERSION Contains the hex representation of the Synopsys component version [31:0] read-only DR Data Register 0x60 32 read-write 0x00000000 0xFFFF DR When writing to this register must right-justify the data [31:0] read-write ULP_SSI 1.0 Synchronous Serial Interface(SSI) SSI 0x24040800 32 read-write 0 0xF8 registers SSI2 16 CTRLR0 Control Register 0 0x00 32 read-write 0x00000007 0xFFFF DFS Select the data frame length (4-bit to 16-bit serial data transfers) [3:0] read-write 0 16 FRF Frame Format, Selects which serial protocol transfers the data [5:4] read-write 00 Motorola SPI 0 01 Texas Instruments SSP 1 10 National Semiconductors Micro wire 2 11 none 3 SCPH Serial Clock Phase. Valid when the frame format (FRF) is set to Motorola SPI [6:6] read-write disable Serial clock toggles in middle of first data bit 0 enable Serial clock toggles at start of first data bit 1 SCPOL Serial Clock Polarity. Valid when the frame format (FRF) is set to Motorola SPI [7:7] read-write disable Inactive state of serial clock is low 0 enable Inactive state of serial clock is high 1 TMOD Selects the mode of transfer for serial communication [9:8] read-write 00 Transmit and Receive 0 01 Transmit Only 1 10 Receive Only 2 SLV_OE DW_apb_ssi is configured as a serial-slave device [10:10] read-write None Slave txd is enabled 0 none Slave txd is disabled 1 SRL Shift Register Loop Used for testing purposes only [11:11] read-write None Normal Mode Operation 0 none Test Mode Operation 1 CFS Control Frame Size Selects the length of the control word for the Micro wire frame format [15:12] read-write None Range -> 1 bit 0 none Range -> 16 bit 15 DFS_32 Selects the data frame length [20:16] read-write None Range -> 3 bit 3 none Range -> 16 bit 15 SPI_FRF Selects data frame format for transmitting or receiving data [22:21] read-write 00 Standard SPI Format 0 01 Dual SPI Format 1 10 Quad SPI Format 2 11 Reser 3 RESERVED1 Reserved for future use [31:23] read-write CTRLR1 Control Register 1 0x04 32 read-write 0x00000000 0xFFFF NDF Number of Data Frames.When TMOD = 10 or TMOD = 11, this register field sets the number of data frames to be continuously received by the ssi_master [15:0] read-write RESERVED1 Reserved for future use. [31:16] read-write SSIENR SSI Enable Register 0x08 32 read-write 0x00000000 0x1 SSI_EN Enables and disables all ssi operations [0:0] read-write RESERVED1 Reserved for future use [31:1] read-write MWCR Micro wire Control Register 0x0C 32 read-write 0x00000000 0xF MWMOD The Micro wire transfer is sequential or non-sequential [0:0] read-write disable non-sequential transfer 0 enable sequential transfer 1 MDD The direction of the data word when the Micro wire serial protocol is used [1:1] read-write disable the data word is received by the SSI MacroCell from the external serial device 0 enable the data word is transmitted from the SSI MacroCell to the external serial device 1 MHS Microwire Handshaking. Used to enable and disable the busy/ready handshaking interface for the Microwire protocol [2:2] read-write disable handshaking interface is disabled 0 enable handshaking interface is enabled 1 RESERVED1 Reserved for future use [31:3] read-write SER SLAVE ENABLE REGISTER 0x10 32 read-write 0x00000000 0x0F SER Each bit in this register corresponds to a slave select line (ss_x_n) from the SSI master. [3:0] read-write disable Not selected 0 enable selected 1 RESERVED1 Reserved for future use [31:4] read-write BAUDR Baud Rate Select Register 0x14 32 read-write 0x00000000 0xFFFF SCKDV SSI Clock Divider.The LSB for this field is always set to 0 and is unaffected by a write operation, which ensures an even value is held in this register [15:0] read-write RESERVED1 Reserved for future use [31:16] read-write TXFTLR Transmit FIFO Threshold Level Register 0x18 32 read-write 0x00000000 0xF TFT Controls the level of entries (or below) at which the transmit FIFO controller triggers an interrupt [3:0] read-write RESERVED1 Reserved for future use [31:4] read-write RXFTLR Receive FIFO Threshold Level 0x1C 32 read-write 0x00000000 0xF RFT Controls the level of entries (or above) at which the receive FIFO controller triggers an interrupt [3:0] read-write RESERVED1 Reserved for future use [31:4] read-write TXFLR Transmit FIFO Level Register 0x20 32 read-only 0x00000000 TXTFL Contains the number of valid data entries in the transmit FIFO [4:0] read-only RESERVED1 Reserved for future use [31:5] read-only RXFLR Receive FIFO Level Register 0x24 32 read-only 0x00000000 RXTFL Contains the number of valid data entries in the receive FIFO [4:0] read-only RESERVED1 Reserved for future use [31:5] read-only SR Status Register 0x28 32 read-only 0x00000006 BUSY indicates that a serial transfer is in progress [0:0] read-only disable SSI is idle or disabled 0 enable SSI is actively transferring data 1 TFNF Set when the transmit FIFO contains one or more empty locations and is cleared when the FIFO is full [1:1] read-only disable Transmit FIFO is full 0 enable Transmit FIFO is not full 1 TFE When the transmit FIFO is completely empty this bit is set [2:2] read-only disable Transmit FIFO is not empty 0 enable Transmit FIFO is empty 1 RFNE Set when the receive FIFO contains one or more entries and is cleared when the receive FIFO is empty [3:3] read-only disable Receive FIFO is empty 0 enable Receive FIFO is not empty 1 RFF When the receive FIFO is completely full this bit is set [4:4] read-only disable Receive FIFO is not full 0 enable Receive FIFO is full 1 TXE This bit is cleared when read [5:5] read-only disable No error 0 enable Transmission error 1 DCOL This bit is set if the ss_in_n input is asserted by another master, while the ssi master is in the middle of the transfer [6:6] read-only disable No error 0 enable Transmit data collision error 1 RESERVED1 Reserved for future use [31:7] read-only IMR Interrupt Mask Register 0x2C 32 read-write 0x0000003F 0x3F TXEIM Transmit FIFO Empty Interrupt Mask [0:0] read-write disable ssi_txe_intr interrupt is masked 0 enable ssi_txe_intr interrupt is not masked 1 TXOIM Transmit FIFO Overflow Interrupt Mask [1:1] read-write disable ssi_txo_intr interrupt is masked 0 enable ssi_txo_intr interrupt is not masked 1 RXUIM Receive FIFO Underflow Interrupt Mask [2:2] read-write disable ssi_rxu_intr interrupt is masked 0 enable ssi_rxu_intr interrupt is not masked 1 RXOIM Receive FIFO Overflow Interrupt Mask [3:3] read-write disable ssi_rxo_intr interrupt is masked 0 enable ssi_rxo_intr interrupt is not masked 1 RXFIM Receive FIFO Full Interrupt Mask [4:4] read-write disable ssi_rxf_intr interrupt is masked 0 enable ssi_rxf_intr interrupt is not masked 1 MSTIM Multi-Master Contention Interrupt Mask [5:5] read-write disable ssi_mst_intr interrupt is masked 0 enable ssi_mst_intr interrupt is not masked 1 RESERVED1 Reserved for future use [31:6] read-only ISR Interrupt Status Register 0x30 32 read-only 0x00000000 TXEIS Transmit FIFO Empty Interrupt Status [0:0] read-only disable ssi_txe_intr interrupt is not active after masking 0 enable ssi_txe_intr interrupt is active after masking 1 TXOIS Transmit FIFO Overflow Interrupt Status [1:1] read-only disable ssi_txo_intr interrupt is not active after masking 0 enable ssi_txo_intr interrupt is active after masking 1 RXUIS Receive FIFO Underflow Interrupt Status [2:2] read-only disable ssi_rxu_intr interrupt is not active after masking 0 enable ssi_rxu_intr interrupt is active after masking 1 RXOIS Receive FIFO Overflow Interrupt Status [3:3] read-only disable ssi_rxo_intr interrupt is not active after masking 0 enable ssi_rxo_intr interrupt is active after masking 1 RXFIS Receive FIFO Full Interrupt Status [4:4] read-only disable ssi_rxf_intr interrupt is not active after masking 0 enable ssi_rxf_intr interrupt is full after masking 1 MSTIS Multi-Master Contention Interrupt Status [5:5] read-only disable ssi_mst_intr interrupt not active after masking 0 enable ssi_mst_intr interrupt is active after masking 1 RESERVED1 Reserved for future use [31:6] read-only RISR Raw Interrupt Status Register 0x34 32 read-only 0x00000000 TXEIR Transmit FIFO Empty Raw Interrupt Status [0:0] read-only disable ssi_txe_intr interrupt is not active prior to masking 0 enable ssi_txe_intr interrupt is active prior masking 1 TXOIR Transmit FIFO Overflow Raw Interrupt Status [1:1] read-only disable ssi_txo_intr interrupt is not active prior to masking 0 enable 1 = ssi_txo_intr interrupt is active prior masking 1 RXUIR Receive FIFO Underflow Raw Interrupt Status [2:2] read-only disable ssi_rxu_intr interrupt is not active prior to masking 0 enable ssi_rxu_intr interrupt is active prior to masking 1 RXOIR Receive FIFO Overflow Raw Interrupt Status [3:3] read-only disable ssi_rxo_intr interrupt is not active prior to masking 0 enable ssi_rxo_intr interrupt is active prior masking 1 RXFIR Receive FIFO Full Raw Interrupt Status [4:4] read-only disable ssi_rxf_intr interrupt is not active prior to masking 0 enable ssi_rxf_intr interrupt is active prior to masking 1 MSTIR Multi-Master Contention Raw Interrupt Status [5:5] read-only disable ssi_mst_intr interrupt is not active prior to masking 0 enable ssi_mst_intr interrupt is active prior masking 1 RESERVED1 Reserved for future use [31:6] read-only TXOICR Transmit FIFO Overflow Interrupt Clear Register 0x38 32 read-only 0x00000000 TXOICR Clear Transmit FIFO Overflow Interrupt This register reflects the status of the interrupt [0:0] read-only RESERVED1 Reserved for future use [31:1] read-only RXOICR Receive FIFO Overflow Interrupt Clear Register 0x3C 32 read-only 0x00000000 RXOICR This register reflects the status of the interrupt A read from this register clears the ssi_rxo_intr interrupt [0:0] read-only RESERVED1 Reserved for future use [31:1] read-only RXUICR Receive FIFO Underflow Interrupt Clear Register 0x40 32 read-only 0x00000000 0x1 RXUICR This register reflects the status of the interrupt A read from this register clears the ssi_rxu_intr interrupt [0:0] read-only RESERVED1 Reserved for future use [31:1] read-only MSTICR Multi-Master Interrupt Clear Register 0x44 32 read-only 0x00000000 MSTICR This register reflects the status of the interrupt A read from this register clears the ssi_mst_intr interrupt [0:0] read-only RESERVED1 Reserved for future use [31:1] read-only ICR Interrupt Clear Register 0x48 32 read-only 0x00000000 ICR This register is set if any of the interrupts below are active A read clears the ssi_txo_intr, ssi_rxu_intr, ssi_rxo_intr, and the ssi_mst_intr interrupts [0:0] read-only RESERVED1 Reserved for future use [31:1] read-only DMACR DMA Control Register 0x4C 32 read-write 0x00000000 0x3 RDMAE This bit enables/disables the receive FIFO DMA channel [0:0] read-write disabled Receive DMA disabled 0 enabled Receive DMA enabled 1 TDMAE This bit enables/disables the transmit FIFO DMA channel [1:1] read-write disabled Transmit DMA disabled 0 enabled Transmit DMA enabled 1 RESERVED1 Reserved for future use [31:2] read-only DMATDLR DMA Transmit Data Level 0x50 32 read-write 0x00000000 0xF DMATDL This bit field controls the level at which a DMA request is made by the transmit logic [3:0] read-write RESERVED1 Reserved for future use [31:4] read-only DMARDLR DMA Receive Data Level Register 0x54 32 read-write 0x00000000 0xF DMARDL This bit field controls the level at which a DMA request is made by the receive logic [3:0] read-write RESERVED1 Reserved for future use [31:4] read-write IDR Identification Register 0x58 32 read-only 0xFFFFFFFF 0xFFFFFFFF IDCODE This register contains the peripherals identification code [31:0] read-only SSI_COMP_VERSION coreKit version ID register 0x5C 32 read-only 0x3430302a 0xFFFFFFFF SSI_COMP_VERSION Contains the hex representation of the Synopsys component version [31:0] read-only DR Data Register 0x60 32 read-write 0x00000000 0xFFFF DR When writing to this register must right-justify the data [31:0] read-write RX_SAMPLE_DLY Rx Sample Delay Register 0xF0 32 read-write 0x00000000 0xFF RSD Receive Data (rxd) Sample Delay. This register is used to delay the sample of the rxd input signal. [7:0] read-write RESERVED1 Reserved for future use [31:8] read-write SPI_CTRLR0 SPI control Register 0xF4 32 read-write 0x00000200 0x7FFF TRANS_TYPE Address and instruction transfer format [1:0] read-write ADDR_L This bit defines length of address to be transmitted, The transfer begins only after these many bits are programmed into the FIFO [5:2] read-write RESERVED1 Reserved for future use [7:6] read-only INST_L DUAL/QUAD length in bits [9:8] read-write RESERVED2 Reserved for future use [10:10] read-only WAIT_CYCLES This bit defines the wait cycles in dual/quad mode between control frames transmit and data reception, Specified as number of SPI clock cycles [14:11] read-write RESERVED3 Reserved for future use [31:15] read-only SIO 1.0 SERIAL GENERAL PERPOSE INPUT/OUTPUT SGPIO 0x47000000 32 read-write 0 0x2CC registers SIO 37 SIO_ENABLE_REG ENABLE REGISTER 0x00 32 read-write 0x00000000 0xFFFF SIO_OPERATION_ENABLE Contains the Enables for all SIO [15:0] read-write RESERVED3 Reserved for future use [31:16] read-only SIO_PAUSE_REG PAUSE REGISTER 0x04 32 read-write 0x00000000 0xFFFF SIO_POSITION_COUNTER_DISABLE Contains sio position counter disable for all SIOs [15:0] read-write RESERVED3 Reserved for future use [31:16] read-only 16 0x4 SIO_OUT_MUX_REGn SIO Output mux register 0x230 SIO_OUT_MUX_REG__n_ Output muxing Register 0x00 32 read-write 0x00000000 0x3F DOUT_OEN_SEL OEN select for GPIO pin 0 [2:0] read-write DOUT_SEL Output mux select for GPIO pin 0 [5:3] read-write RESERVED1 Reserved for future use [31:6] read-only 16 0x4 SIO_INPUT_MUX_REGn SIO Input mux register 0x270 SIO_INPUT_MUX_REG__n_ Input muxing Register 0x00 32 read-write 0x00000000 0x3FF CLK_SEL Input clock select for SIO 0 [2:0] read-write QUALIFIER_SELECT qualifier select [4:3] read-write QUALIFIER_MODE qualifier mode [6:5] read-write DIN_SEL Data in mux select [9:7] read-write RESERVED1 Reserved for future use [31:10] read-only 16 0x4 SIO_SHIFT_COUNTERn Shift counter register 0x28 SIO_SHIFT_COUNTER__n_ Shift counter register 0x00 32 read-only 0x00000000 0x3FFF SHIFT_COUNTER shift counter current value [13:0] read-only RESERVED1 Reserved for future use [31:14] read-only 16 0x4 SIO_BUFFER_REGn SIO Buffer registers 0x68 SIO_BUFFER_REG__n_ Buffer Register 0x00 32 read-write 0x00000000 0xFFFFFFFF DATA Data to load into the shift register [31:0] read-write 16 0x4 SIO_SHIFT_COUNT_PRELOAD_REGn SIO Shift count preload register 0xA8 SIO_SHIFT_COUNT_PRELOAD_REG__n_ Shift counter preload Register 0x00 32 read-write 0x00000000 0xBFFF RELOAD_VALUE division factor required to generate shift clock [13:0] read-write RESERVED1 Reserved for future use [14:14] read-only REVERSE_LOAD When set, the data on APB is loaded to buffer is reverse order [15:15] read-write RESERVED2 Reserved for future use [31:16] read-only 16 0x4 SIO_DATA_POS_COUNT_REGn SIO DATA position count registers 0xE8 SIO_DATA_POS_COUNT_REG__n_ Data Position Counter Register 0x00 32 read-write 0x00000000 0xFFFF RELOAD_VALUE No. of shifts to happen before reloading the shift register with data/ pausing the operation [7:0] read-write POSITION_COUNTER The position counter can be loaded via AHB [15:8] read-write RESERVED3 Reserved for future use [31:16] read-only 16 0x4 SIO_CONFIG_REGn SIO Configuration Registers 0 to 15 0x128 SIO_CONFIG_REG__n_ Configuration Register 0x00 32 read-write 0x00000000 0x1FFFF FULL_ENABLE When set, fifo full indication would be asserted when internal buffer is full [0:0] read-write EMPTY_ENABLE When set, fifo full indication would be asserted when internal buffer is empty [1:1] read-write EDGE_SEL edge selection [2:2] read-write Disable pos edge 0 Enable neg edge 1 CLK_SEL clock selection [3:3] read-write Disable internal counter clock is used for shift operations and sent out 0 Enable external clock is used for shift operations and is sent out 1 IGNORE_FIRST_SHIFT_CONDITION data shift condition [4:4] read-write Disable at a shift/capture happens at the first clock edge 0 FLOW_CONTROL_ENABLED flow control [5:5] read-write Disable flow control disable 0 Enable flow control enable 1 PATTERN_MATCH_ENABLE pattern match [6:6] read-write Disable pattern match disable 0 Enable pattern match enable 1 QUALIFIER_MODE qualifier mode [7:7] read-write none Use direct qualifier input 0 None Use inverted qualifier 1 QUALIFY_CLOCK qualify clock [8:8] read-write none output clock is not qualified 0 None output clock is qualified with qualifier 1 INVERT_CLOCK invert clock [9:9] read-write None direct version of shift clock is provided out 0 none inverted version of the clock is provided out 1 PARALLEL_MODE No. of bits to shift/capture at valid clk edge [11:10] read-write 00 1 bit 0 01 2 bits 1 10 4 bits 2 11 8 bits 3 PIN_DETECTION_MODE Pin mode to be considered for gpio interrupt [13:12] read-write 00 rise edge 0 01 fall edge 1 10 level zero 2 11 level one 3 SET_CLK_OUT When high sets the sio clock_out port. This is used only when sio is not enabled [14:14] read-write RESET_CLK_OUT When high resets the sio clock_out port. This is used only when sio is not enabled [15:15] read-write LOAD_DATA_POS_CNTR_VIA_APB When set, data position counter can be loaded via APB [16:16] read-write RESERVED1 Reserved for future use [31:17] read-only SIO_PATTERN_MATCH_MASK_REG_SLICE_0 Pattern Match Mask Register 0 0x168 32 read-write 0x00000000 0xFFFFFFFF MATCH_MASK_LOWER16_BITS Enable for lower 16 bits [31:0] read-write SIO_PATTERN_MATCH_MASK_REG_SLICE_1 Pattern Match Mask Register Slice 1 0x16C 32 read-write 0x00000000 0xFFFFFFFF MATCH_MASK_LOWER16_BITS Enable for lower 16 bits [31:0] read-write SIO_PATTERN_MATCH_MASK_REG_SLICE_2 Pattern Match Mask Register Slice 2 0x170 32 read-write 0x00000000 0xFFFFFFFF MATCH_MASK_LOWER16_BITS Enable for lower 16 bits [31:0] read-write SIO_PATTERN_MATCH_MASK_REG_SLICE_8 Pattern Match Mask Register Slice 8 0x188 32 read-write 0x00000000 0xFFFFFFFF MATCH_MASK_LOWER16_BITS Enable for lower 16 bits [31:0] read-write SIO_PATTERN_MATCH_MASK_REG_SLICE_9 Pattern Match Mask Register Slice 9 0x18C 32 read-write 0x00000000 0xFFFFFFFF MATCH_MASK_LOWER16_BITS Enable for lower 16 bits [31:0] read-write SIO_PATTERN_MATCH_MASK_REG_SLICE_10 Pattern Match Mask Register Slice 10 0x190 32 read-write 0x00000000 0xFFFFFFFF MATCH_MASK_LOWER16_BITS Enable for lower 16 bits [31:0] read-write SIO_PATTERN_MATCH_REG_SLICE_0 Pattern Match Mask Register Slice 0 0x1A8 32 read-write 0x00000000 0xFFFFFFFF PATTERN_MATCH_LOWER16_BITS Lower 16-bits of pattern to be detected [31:0] read-write SIO_PATTERN_MATCH_REG_SLICE_1 Pattern Match Mask Register Slice 1 0x1AC 32 read-write 0x00000000 0xFFFFFFFF PATTERN_MATCH_LOWER16_BITS Lower 16-bits of pattern to be detected [31:0] read-write SIO_PATTERN_MATCH_REG_SLICE_2 Pattern Match Mask Register Slice 2 0x1B0 32 read-write 0x00000000 0xFFFFFFFF PATTERN_MATCH_LOWER16_BITS Lower 16-bits of pattern to be detected [31:0] read-write SIO_PATTERN_MATCH_REG_SLICE_8 Pattern Match Mask Register Slice 8 0x1C8 32 read-write 0x00000000 0xFFFFFFFF PATTERN_MATCH_LOWER16_BITS Lower 16 bits of pattern to be detected [31:0] read-write SIO_PATTERN_MATCH_REG_SLICE_9 Pattern Match Mask Register Slice 9 0x1CC 32 read-write 0x00000000 0xFFFFFFFF PATTERN_MATCH_LOWER16_BITS Lower 16 bits of pattern to be detected [31:0] read-write SIO_PATTERN_MATCH_REG_SLICE_10 Pattern Match Mask Register Slice 10 0x1D0 32 read-write 0x00000000 0xFFFFFFFF PATTERN_MATCH_LOWER16_BITS Lower 16 bits of pattern to be detected [31:0] read-write SIO_PATTERN_MATCH_INTR_EN_SET_REG Pattern Match Interrupt Enable Set Register 0x218 32 read-write 0x00000000 0xFFFF INTR_ENABLE_SET Common pattern or buffer under run interrupt enable set register for all SIOs. Each bit corresponds to one SIO [15:0] read-write RESERVED1 Reserved for future use [31:16] read-only SIO_PATTERN_MATCH_INTR_EN_CLEAR_REG Pattern Match Interrupt Enable Clear Register 0x21C 32 write-only 0x00000000 0xFFFF INRT_ENABLE_CLEAR Common pattern or buffer under run interrupt enable clear register for all SIOs [15:0] write-only RESERVED1 Reserved for future use [31:16] write-only SIO_PATTERN_MATCH_INTR_MASK_SET_REG Pattern Match Interrupt Mask Set Register 0x220 32 read-write 0xFFFF 0xFFFF INTR_MASK_SET Common pattern or buffer under run interrupt mask set register for all SIOs [15:0] read-write RESERVED1 Reserved for future use [31:16] read-only SIO_PATTERN_MATCH_INTR_MASK_CLEAR_REG Pattern Match Interrupt Mask Clear Register 0x224 32 write-only 0xFFFF 0xFFFF INTR_MASK_CLEAR Common pattern or buffer under run interrupt mask clear register for all SIOs [15:0] write-only RESERVED1 Reserved for future use [31:16] write-only SIO_PATTERN_MATCH_INTR_STATUS_REG Pattern Match Interrupt Status Register 0x228 32 read-write 0x00000000 0xFFFF INTR_STATUS Common pattern interrupt status register for all SIOs [15:0] read-write RESERVED3 Reserved for future use [31:16] read-only SIO_BUFFER_INTR_STATUS_REG Buffer Interrupt Status Register 0x22C 32 read-write 0x00000000 0xFFFF INTR_STATUS Common pattern interrupt status register for all SIOs [15:0] read-write RESERVED1 Reserved for future use [31:16] read-only SIO_SHIFT_INTR_EN_SET_REG Shift Interrupt Enable Set Register 0x1F0 32 read-write 0x00000000 0xFFFF INTR_ENABLE_SET Common shift interrupt enable set register for all SIOs [15:0] read-write RESERVED3 Reserved for future use [31:16] read-only SIO_SHIFT_INTR_EN_CLEAR_REG Shift Interrupt Enable Clear Register 0x1F4 32 write-only 0x00000000 0xFFFF INRT_ENABLE_CLEAR Common shift interrupt enable Clear register for all SIOs [15:0] write-only RESERVED3 Reserved for future use [31:16] write-only SIO_SHIFT_INTR_MASK_SET_REG Shift Interrupt Mask Set Register 0x1F8 32 read-write 0xFFFF 0xFFFF INTR_MASK_SET Common shift interrupt enable Set register for all SIOs [15:0] read-write RESERVED1 Reserved for future use [31:16] read-only SIO_SHIFT_INTR_MASK_CLEAR_REG Shift Interrupt Mask Clear Register 0x1FC 32 write-only 0xFFFF 0xFFFF INTR_MASK_CLEAR Common shift interrupt mask clear register for all SIOs [15:0] write-only RESERVED1 Reserved for future use [31:16] write-only SIO_SHIFT_INTR_STATUS_REG Shift Interrupt Status Register 0x200 32 read-write 0x00000000 0xFFFF INTR_ENABLE_SET Common shift interrupt mask clear register for all SIOs [15:0] read-write RESERVED1 Reserved for future use [31:16] read-only SIO_SWAP_INTR_EN_SET_REG Swap Interrupt Enable Set Register 0x204 32 read-write 0x00000000 0xFFFF INTR_ENABLE_SET Swap interrupt enable set register for all SIOs [15:0] read-write RESERVED1 Reserved for future use [31:16] read-only SIO_SWAP_INTR_EN_CLEAR_REG Swap Interrupt Enable Clear Register 0x208 32 write-only 0x00000000 0xFFFF INTR_ENABLE_CLEAR Swap interrupt enable Clear register for all SIOs [15:0] write-only RESERVED1 Reserved for future use [31:16] write-only SIO_SWAP_INTR_MASK_SET_REG Swap Interrupt Mask Set Register 0x20C 32 read-write 0xFFFF 0xFFFF INTR_MASK_SET Common swap interrupt mask set register for all SIOs [15:0] read-write RESERVED1 Reserved for future use [31:16] read-only SIO_SWAP_INTR_MASK_CLEAR_REG Swap Interrupt Mask Clear Register 0x210 32 write-only 0xFFFF 0xFFFF INTR_MASK_CLEAR Common swap interrupt mask Clear register for all SIOs [15:0] write-only RESERVED1 Reserved for future use [31:16] write-only SIO_SWAP_INTR_STATUS_REG Swap Interrupt Statusr Register 0x214 32 read-write 0x00000000 0xFFFF INTR_ENABLE_SET Common swap interrupt status register for all SIOs [15:0] read-write RESERVED1 Reserved for future use [31:16] read-only SIO_GPIO_INTR_EN_SET_REG GPIO Interrupt Enable Set Register 0x14 32 read-write 0x00000000 0xFFFF INTR_ENABLE_SET gpio interrupt enable set register for all SIOs [15:0] write-only RESERVED1 Reserved for future use [31:16] read-only SIO_GPIO_INTR_EN_CLEAR_REG GPIO Interrupt Enable Clear Register 0x18 32 write-only 0x00000000 0xFFFF INTR_ENABLE_CLEAR gpio interrupt enable Clear register for all SIOs [15:0] write-only RESERVED1 Reserved for future use [31:16] write-only SIO_GPIO_INTR_MASK_SET_REG GPIO Interrupt Enable Clear Register 0x1C 32 read-write 0xFFFF 0xFFFF INTR_MASK_SET Common gpio interrupt mask set register for all SIOs [15:0] read-write RESERVED1 Reserved for future use [31:16] read-only SIO_GPIO_INTR_MASK_CLEAR_REG GPIO Interrupt Enable Clear Register 0x20 32 write-only 0xFFFF 0xFFFF INTR_MASK_CLEAR gpio interrupt mask clear register for all SIOs [15:0] write-only RESERVED1 Reserved for future use [31:16] write-only SIO_GPIO_INTR_STATUS_REG GPIO Interrupt Status Register 0x24 32 read-write 0xFFFF 0xFFFF INTR_MASK_SET Common gpio interrupt status register for all SIOs [15:0] write-only RESERVED1 Reserved for future use [31:16] read-only SIO_GPIO_IN_REG GPIO Input Register 0x8 32 read-only 0x00000000 0xFFFFFFFF IN_VALUE GPIO input pin status [31:0] read-only SIO_GPIO_OUT_REG GPIO Output Register 0xC 32 read-write 0x00000000 0xFFFFFFFF OUT_VALUE Value to be loaded on GPIO out pins [31:0] read-write SIO_GPIO_OEN_REG GPIO Output enable Register 0x10 32 read-write 0xFFFF 0xFFFFFFFF OEN_VALUE OEN for the GPIO pins [31:0] read-write SIO_FIFO_WR_RD_REG FIFO READ/WRITE Register 0x2B0 32 read-write 0x00000000 0xFFFFFFFF FIFO_DATA_REGISTER Writes and read into this register will be written into SIO buffer register [31:0] read-write SIO_FIFO_WR_OFFSET_START_REG Points to start slice number forming the FIFO 0x2B4 32 read-write 0x0000 0xFFFFFFFF SIO_START_SLICE_NUMBER Points to start slice number forming the FIFO,On write, FIFO_WR_OFFSET_CNT_REG will also be reset to the value pointed written into this register [31:0] read-write SIO_FIFO_WR_OFFSET_END_REG SIO last slice no indication Register 0x2B8 32 read-write 0x00000000 0xFFFFFFFF SIO_END_SLICE_NUMBER points to last slice no forming fifo [31:0] read-write SIO_FIFO_WR_OFFSET_CNT_REG Points to current slice number forming the FIFO 0x2BC 32 read-write 0x00000 0xFFFFFFFF SIO_CURRENT_SLICE_NUMBER Next FIFO operation will happen to buffer in the slice pointed by this register [31:0] read-write SIO_FIFO_RD_OFFSET_START_REG Points to start slice number forming the FIFO 0x2C0 32 read-write 0x00000 0xFFFFFFFF SIO_START_SLICE_NUMBER Points to start slice number forming the FIFO [31:0] read-write SIO_FIFO_RD_OFFSET_END_REG Points to last slice number forming the FIFO 0x2C4 32 read-write 0x00000 0xFFFFFFFF SIO_END_SLICE_NUMBER Points to last slice number forming the FIFO [31:0] read-write SIO_FIFO_RD_OFFSET_CNT_REG Points to start current number forming the FIFO 0x2C8 32 read-write 0x00000 0xFFFFFFFF SIO_CURRENT_SLICE_NUMBER Next FIFO operation will happen to buffer in the slice pointed by this register This register has to be set to zero before starting fresh DMA operation [31:0] read-write QSPI 1.0 The queued serial peripheral interface module provides a serial peripheral interface with queued transfer capability QSPI 0x12000000 32 read-write 0 0x164 registers QSPI 60 QSPI_CLK_CONFIG QSPI Clock Configuration Register 0x00 32 read-write 0x11F 0xFFF QSPI_AUTO_CSN_HIGH_CNT Minimum SOC clock cycles, during which QSPI auto csn should be high between consecutive CSN assertions [4:0] read-write RESERVED0 Reserved [5:5] read-write RESERVED1 reserved1 [7:6] read-write QSPI_CLK_EN_SCLK QSPI clock enable [8:8] read-write Dynamic_Clock_Gating_Enabled Dynamic clock gating is enabled in side QSPI controller 0 Full_Time_Clock_Enabled Full time clock is enabled for QSPI controller. 1 RESERVED2 reserved2 [11:9] read-write SPI_CLK_DELAY_VAL Delay value programmed to RX QSPI DLL on read side. This delay is used to delay the pad clock/DQS according to the requirement [17:12] read-write OCTA_MODE_ENABLE_WITH_DQS Enables SPI octa mode along with DQS in DDR mode [18:18] read-write QSPI_DLL_ENABLE Enable for RX QSPI DLL in read mode.This is used in M4SS QSPI DDR pads to delay the pad clock DQS input [19:19] read-write DLL Disabled DLL is disabled/bypassed. 0 Enabled DLL is enabled 1 DDR_CLK_POLARITY_FROM_REG Used this bit to sample the data at posedge negedge after interface FFs with internal qspi clock 0-Sample at negedge 1-Sample at posedge [20:20] read-write Sample_Edge Negative_Edge Sample at Negative edge 0 Positive_Edge Sample at positive edge 1 QSPI_DLL_ENABLE_TX Enable for TX QSPI DLL in write path. This is used in M4SS QSPI DDR pads to delay the qspi clock output. 0–DLL is disabled bypassed 1–DLL is enabled [21:21] read-write DLL Disabled DLL is disabled/bypassed. 0 Enabled DLL is enabled 1 SPI_CLK_DELAY_VAL_TX Delay value programmed to TX QSPI DLL in write path. This delay is used to delay the qspi clock output according to the requirement [27:22] read-write QSPI_RX_DQS_DLL_CALIB Delay value programmed to TX QSPI DLL in write path. This delay is used to delay the qspi clock output according to the requirement [28:28] read-write RESERVED3 reserved3 [31:29] read-write QSPI_BUS_MODE QSPI Bus Mode Register 0x04 32 read-write 0x00000000 0xFFFFFFFF QSPI_9116_FEATURE_EN 9115 specific features are enabled with this enable [0:0] read-write QSPI_MAN_MODE_CONF_CSN0 Configures the QSPI flash for Single/Dual/Quad mode operation in manual mode [2:1] read-write 00 Single Mode 0 01 Dual Mode 1 10 Quad Mode 2 11 none 3 AUTO_MODE_RESET QSPI Auto controller reset. This is not a Self clearing bit [3:3] read-write Disable Auto mode is active 0 Enable Auto mode is inactive 1 QSPI_PREFETCH_EN Pre-fetch of data from the model which is connected to QSPI, automatically with out reading on AHB and is supplied to AHB, when address is matched with AHB read transaction address [4:4] read-write Disable Pre-fetch mode is disabled. 0 Enable Pre-fetch mode is enabled 1 QSPI_WRAP_EN Model wrap is considered with this bit and uses wrap instruction to read from FLASH [5:5] read-write Disable Wrap mode is disabled (AHB WRAP can be used). 0 Enable Wrap mode is enabled 1 QSPI_AUTO_MODE_FRM_REG QSPI Mode of Operation [6:6] read-write Disable Manual Mode is selected 0 Enable Auto Mode is selected. 1 PROGRAMMABLE_AUTO_CSN_BASE_ADDR_EN Programmable auto csn mode enable [7:7] read-write QSPI_D2_OEN_CSN0 Direction Control for SPI_IO2 in case of dual/single mode for chip select0 csn0. It is used both in Auto and Manual Mode [8:8] read-write QSPI_D3_OEN_CSN0 Direction Control for SPI_IO3 in case of dual/single mode for chip select0 csn0. It is used both in Auto and Manual Mode. [9:9] read-write QSPI_D2_DATA_CSN0 Value of SPI_IO2 in case of dual/single mode for chip select0 csn0. It is used both in Auto and Manual Mode. [10:10] read-write QSPI_D3_DATA_CSN0 Value of SPI_IO3 in case of dual/single mode for chip select0 csn0. It is used both in Auto and Manual Mode [11:11] read-write QSPI_D2_OEN_CSN1 Direction Control for SPI_IO2 in case of dual/single mode for chip select1 csn1 [12:12] read-write QSPI_D3_OEN_CSN1 Direction Control for SPI_IO3 in case of dual/single mode for chip select1 csn1 [13:13] read-write QSPI_D2_DATA_CSN1 Direction Control for SPI_IO3 in case of dual/single mode for chip select1 csn1 [14:14] read-write QSPI_D3_DATA_CSN1 Value of SPI_IO3 in case of dual/single mode for chip select1 csn1 [15:15] read-write QSPI_DATA_SAMPLE_EDGE Samples MISO data on clock edges [16:16] read-write Disable Pos edge of loop back spi_pad_clk 0 Enable Neg edge of loop back spi_pad_clk 1 QSPI_CLK_MODE_CSN0 QSPI Clock Mode [17:17] read-write MOde0 Mode 0, QSPI_CLK is low when QSPI_CS is high for chip select0 csn0 0 Mode3 Mode 3, QSPI_CLK is high when QSPI_CS is high for chip select0 csn0 1 QSPI_CLK_MODE_CSN1 QSPI Clock Mode [18:18] read-write MOde0 Mode 0, QSPI_CLK is low when QSPI_CS is high for chip select1 csn1 0 Mode3 Mode 3, QSPI_CLK is high when QSPI_CS is high for chip select1 csn1 1 QSPI_CLK_MODE_CSN2 QSPI Clock Mode [19:19] read-write MOde0 Mode 0 QSPI_CLK is low when QSPI_CS is high for chip select2 csn2 0 Mode3 Mode 3 QSPI_CLK is high when QSPI_CS is high for chip select2 csn2 1 QSPI_CLK_MODE_CSN3 QSPI Clock Mode [20:20] read-write MOde0 Mode 0, QSPI_CLK is low when QSPI_CS is high for chip select3 csn3 0 Mode3 Mode 3, QSPI_CLK is high when QSPI_CS is high for chip select3 csn3 1 FLASH_AW_FIFO_LS_EN Qspi flash auto write fifo light sleep enable [21:21] read-write FLASH_SEC_AES_LS_EN Qspi flash auto write fifo light sleep enable [22:22] read-write RESERVED1 reserved1 [23:23] read-write QSPI_D2_OEN_CSN2 Direction Control for SPI_IO2 in case of dual/single mode for chip select2 csn2 [24:24] read-write QSPI_D3_OEN_CSN2 Direction Control for SPI_IO3 in case of dual/single mode for chip select2 csn2 [25:25] read-write QSPI_D2_DATA_CSN2 Value of SPI_IO2 in case of dual/single mode for chip select2 csn2 [26:26] read-write QSPI_D3_DATA_CSN2 Value of SPI_IO3 in case of dual/single mode for chip select2 csn2 [27:27] read-write QSPI_D2_OEN_CSN3 Direction Control for SPI_IO2 in case of dual/single mode for chip select3 csn3 [28:28] read-write QSPI_D3_OEN_CSN3 Direction Control for SPI_IO3 in case of dual/single mode for chip select3 csn3 [29:29] read-write QSPI_D2_DATA_CSN3 Value of SPI_IO2 in case of dual/single mode for chip select3 csn3 [30:30] read-write QSPI_D3_DATA_CSN3 Value of SPI_IO3 in case of dual/single mode for chip select3 csn3 [31:31] read-write QSPI_AUTO_CONFIG_1 QSPI Auto Controller Configuration 1 Register 0x08 32 read-write 0x00000000 0xFF8FFFFF QSPI_EXT_BYTE_MODE_CSN0 Mode of operation of QSPI in the extra byte phase [1:0] read-write 00 SPI 0 01 Dual SPI 1 10 Quad SPI 2 11 none 3 QSPI_DUMMY_MODE_CSN0 Mode of operation of QSPI in instruction phase [3:2] read-write 00 SPI 0 01 Dual SPI 1 10 Quad SPI 2 11 none 3 QSPI_ADDR_MODE_CSN0 Mode of operation of QSPI in instruction phase [5:4] read-write 00 SPI 0 01 Dual SPI 1 10 Quad SPI 2 11 none 3 QSPI_CMD_MODE_CSN0 Mode of operation of QSPI in instruction phase [7:6] read-write 00 SPI 0 01 Dual SPI 1 10 Quad SPI 2 11 none 3 QSPI_DATA_MODE_CSN0 Mode of operation of QSPI in DATA phase [9:8] read-write 00 SPI 0 01 Dual SPI 1 10 Quad SPI 2 11 none 3 QSPI_EXTRA_BYTE_CSN0 Value of the extra byte to be transmitted, if the extra byte mode is enabled [17:10] read-write QSPI_EXTRA_BYTE_EN_CSN0 Value of the extra byte to be transmitted, if the extra byte mode is enabled [19:18] read-write 00 Do not transmit extra byte. 0 01 Transmit Extra byte after address phase 1 10 Transmit only first nibble of the byte and maintain Hi-Z on the IO bus for next nibble 2 11 none 3 QSPI_WRAP_SIZE Qspi auto wrap size [21:20] read-write RESERVED1 reserved1 [22:22] read-write QSPI_PG_JUMP_CSN0 NONE [23:23] read-write QSPI_DUMMY_BYTES_INCR_CSN0 Specifies the number of dummy bytes 0 to 7 for the selected SPI mode [27:24] read-write QSPI_DUMMY_BYTES_WRAP_CSN0 Specifies the number of dummy bytes 0 to 7 for the selected SPI mode in case of wrap instruction [31:28] read-write QSPI_AUTO_CONFIG_2 QSPI Auto Controller Configuration 2 Register 0x0C 32 read-write 0x00000301 0xFFFFFFFF QSPI_RD_DATA_SWAP_AUTO_CSN0 NONE [0:0] read-write Disable Do not swap the read data in auto mode 0 Enable Swap the auto read data in auto mode 1 QSPI_ADR_SIZE_16BIT_AUTO_MODE_CSN0 NONE [1:1] read-write Disable 24 bit address is sent to model 0 Enable 16 Bit address is sent to model 1 QSPI_CONTI_RD_EN_CSN0 NONE [2:2] read-write Continuous_Read Disabled Continuous read disabled. 0 Enabled Continuous read enabled. 1 DUMMY_BYTES_WR_RD_CSN0 Dummy bytes to the model to be read or to be write [3:3] read-write Disable Dummy bytes will be read 0 Enable Dummy bytes to be write. 1 QSPI_DUMMY_BYTES_JMP_CSN0 Dummy cycles to be selected in case of JUMP [7:4] read-write QSPI_RD_INST_CSN0_LSB Read instruction LS Byte to be used for the selected SPI modes and when wrap is not supported [15:8] read-write QSPI_RD_WRAP_INST_CSN0 Read instruction to be used, when wrap mode is supported by QSPI flash [23:16] read-write QSPI_PG_JMP_INST_CSN0 Read instruction to be used, when Page jump is to be used [31:24] read-write QSPI_MANUAL_CONFIG1 QSPI Manual Configuration 1 Register 0x10 32 read-write 0x000C0001 0xFFFFFFFF QSPI_MANUAL_CSN SPI CS in manual mode [0:0] read-write QSPI_MANUAL_WR Write enable for manual mode when CS is low [1:1] read-write QSPI_MANUAL_RD Read enable for manual mode when CS is low [2:2] read-write QSPI_MANUAL_RD_CNT_0_to_9_Bits Indicates total number of bytes to be read along with [31:27] bits of this register. Maximum length supported is 32k bytes [12:3] read-write QSPI_MANUAL_CSN_SELECT Indicates which CSn is valid [14:13] read-write RESERVED1 reserved1 [18:15] read-write QSPI_MANUAL_SIZE_FRM_REG Manual reads and manual writes follow this size [20:19] read-write TAKE_QSPI_MANUAL_WR_SIZE_FRM_REG NONE [21:21] read-write Disable No action. Takes write size from fifo 0 Enable Take write size from Manual config register1 1 QSPI_FULL_DUPLEX_EN Full duplex mode enable. [22:22] read-write Disable Full duplex mode disabled. 0 Enable Full duplex mode enabled 1 RESERVED2 reserved2 [24:23] read-write HW_CTRLD_QSPI_MODE_CTRL Hardware controlled qspi mode in between AUTO and manual [25:25] read-write Hardware_Control Disabled Hardware control is disabled 0 Enabled Hardware control is enabled. 1 QSPI_MANUAL_GSPI_MODE Internally the priority is given to manual mode [26:26] read-write SPI_Mode SPI mode 0 Host_SPI_Mode Host SPI mode. 1 QSPI_MANUAL_RD_CNT_10_to_14_Bits Indicates total number of bytes or bits [31:27] read-write QSPI_MANUAL_CONFIG2 QSPI Manual Configuration 2 Register 0x14 32 read-write 0x000000F0 0xFFF QSPI_WR_DATA_SWAP_MNL_CSN0 Swap the write data inside the QSPI controller it-self [0:0] read-write Disable Manual write data swap is disabled for csn0. 0 Enable Manual write data swap is enabled for csn0. 1 QSPI_WR_DATA_SWAP_MNL_CSN1 Swap the write data inside the QSPI controller it-self. [1:1] read-write Disable Manual write data swap is disabled for csn1. 0 Enable Manual write data swap is enabled for csn1. 1 QSPI_WR_DATA_SWAP_MNL_CSN2 Swap the write data inside the QSPI controller itself. [2:2] read-write Disable Manual write data swap is disabled for csn2. 0 Enable Manual write data swap is enabled for csn2. 1 QSPI_WR_DATA_SWAP_MNL_CSN3 Swap the write data inside the QSPI controller itself. [3:3] read-write Disable Manual write data swap is disabled for csn3. 0 Enable Manual write data swap is enabled for csn3. 1 QSPI_RD_DATA_SWAP_MNL_CSN0 Swap the read data inside the QSPIcontroller it self. [4:4] read-write Disable Manual read data swap is disabled for csn0. 0 Enable Manual read data swap is enabled for csn0. 1 QSPI_RD_DATA_SWAP_MNL_CSN1 Swap the read data inside the QSPIcontroller itself. [5:5] read-write Disable Manual read data swap is disabled for csn1 0 Enable Manual read data swap is enabled for csn1 1 QSPI_RD_DATA_SWAP_MNL_CSN2 Swap the read data inside the QSPIcontroller it-self [6:6] read-write Disable Manual read data swap is disabled for csn2 0 Enable Manual read data swap is enabled for csn2 1 QSPI_RD_DATA_SWAP_MNL_CSN3 Swap the read data inside the QSPIcontroller itself [7:7] read-write Disable Manual read data swap is disabled for csn3 0 Enable Manual read data swap is enabled for csn3 1 QSPI_MAN_MODE_CONF_CSN1 Configures the QSPI flash for Single/Dual/Quad mode operation in manual mode for chip select1 csn1 [9:8] read-write 00 Single 0 01 Dual 1 10 Quad 2 11 none 3 QSPI_MAN_MODE_CONF_CSN2 Configures the QSPI flash for Single or Dual or Quad mode operation in manual mode for chip select2 csn2 [11:10] read-write 00 Single 0 01 Dual 1 10 Quad 2 11 none 3 QSPI_MAN_MODE_CONF_CSN3 Configures the QSPI flash for Single or Dual or Quad mode operation in manual mode for chip select3 csn3 [13:12] read-write 00 Single 0 01 Dual 1 10 Quad 2 11 none 3 LOOP_BACK_EN Internal loop back test mode. [14:14] read-write QSPI_MANUAL_DDR_PHASE DDR operations can be performed even in manual mode [15:15] read-write QSPI_DDR_CLK_EN DDR operations can be performed even in manual mode [16:16] read-write Disable Use SDR mode clk 0 Enable Use DDR mode clk 1 RESERVED1 reserved1 [17:17] read-write QSPI_RD_DATA_SWAP_WORD_LVL_MNL_CSN0 Set this bit for read data byte swapping within the word. It is valid only for octa ddr mode. It is valid for csn0. [18:18] read-write QSPI_RD_DATA_SWAP_WORD_LVL_MNL_CSN1 Set this bit for read data byte swapping within the word. It is valid only for octa ddr mode. It is valid for csn1. [19:19] read-write QSPI_RD_DATA_SWAP_WORD_LVL_MNL_CSN2 Set this bit for read data byte swapping within the word. It is valid only for octa ddr mode. It is valid for csn2. [20:20] read-write QSPI_WR_DATA_SWAP_WORD_LVL_MNL_CSN0 Set this bit for write data byte swapping within the word. It is valid only for octa ddr mode. It is valid for csn0. [21:21] read-write QSPI_WR_DATA_SWAP_WORD_LVL_MNL_CSN1 Set this bit for write data byte swapping within the word. It is valid only for octa ddr mode. It is valid for csn1. [22:22] read-write QSPI_WR_DATA_SWAP_WORD_LVL_MNL_CSN2 Set this bit for write data byte swapping within the word. It is valid only for octa ddr mode. It is valid for csn2. [23:23] read-write QSPI_WR_DATA_SWAP_WORD_LVL_MNL_CSN3 Set this bit for write data byte swapping within the word. It is valid only for octa ddr mode. It is valid for csn3. [24:24] read-write QSPI_MANUAL_DUMMY_BYTE_OR_BIT_MODE Indicates qspi_manual_rd_cnt values are dummy bytes or bits in manual mode. [25:25] read-write RESERVED2 reserved2 [31:26] read-write QSPI_MANUAL_WRITE_DATA2 QSPI Manual Write Data 2 Register 0x80 32 read-write 0x00000000 0xFF QSPI_MANUAL_WRITE_DATA2 Number of bits to be written in write mode [4:0] read-write RESERVED1 reserved1 [6:5] read-write USE_PREV_LENGTH Use previous length. [7:7] read-write Disable No action 0 Enable Uses previously programmed length in [4:0] of this register for next writes 1 QSPI_CLK_ENABLE_HCLK reserved2 [8:8] read-write RESERVED2 reserved2 [31:9] read-write QSPI_FIFO_THRLD QSPI FIFO Threshold Register 0x1C 32 read-write 0x00000C7 0x1FF FIFO_AEMPTY_THRLD FIFO almost empty threshold [3:0] read-write FIFO_AFULL_THRLD FIFO almost full threshold [7:4] read-write WFIFO_RESET Write fifo reset [8:8] read-write RFIFO_RESET Read fifo reset [9:9] read-write RESERVED1 reserved1 [31:10] read-write QSPI_MANUAL_STATUS QSPI Manual Status Register 0x20 32 read-only 0x00000591 0x7FFF QSPI_BUSY State of Manual mode. [0:0] read-only Disable QSPI controller is IDLE in Manual mode. 0 Enable A read, write or dummy cycle operation is in process in manual mode. 1 FIFO_FULL_WFIFO_S Status indication for Wfifo in manual mode [1:1] read-only FIFO_AFULL_WFIFO_S Status indication for Wfifo in manual mode [2:2] read-only FIFO_EMPTY_WFIFO Status indication for Wfifo in manual mode [3:3] read-only FIFO_AEMPTY_WFIFO Status indication for Wfifo in manual mode [4:4] read-only FIFO_FULL_RFIFO Status indication for Rfifo in manual mode [5:5] read-only FIFO_AFULL_RFIFO Status indication for Rfifo in manual mode [6:6] read-only FIFO_EMPTY_RFIFO_S Status indication for Rfifo in manual mode [7:7] read-only FIFO_AEMPTY_RFIFO_S Status indication for Rfifo in manual mode [8:8] read-only GSPI_MANUAL_RD_CNT This is a result of 10 bits ORing counter [9:9] read-only Disable No read transactions are in pending 0 Enable Read transactions are in pending ( to be done) 1 AUTO_MODE_FSM_IDLE_SCLK Auto mode idle signal to track auto controller is busy or idle. [10:10] read-only Disable Auto mode is busy 0 Enable Auto mode is idle 1 QSPI_AUTO_MODE QSPI controller status. [11:11] read-only Disable QSPI controller is in manual mode. 0 Enable QSPI controller is in auto mode. 1 QSPI_AUTO_MODE_FRM_REG_SCLK QSPI auto mode status. Valid only when HW_CTRLD_QSPI_MODE_CTRL is zero. [12:12] read-only Disable QSPI controller is hot coded to manual mode operations. 0 Enable QSPI controller is hot coded to AUTO mode operations 1 HW_CTRLD_MODE_SCLK QSPI mode status in HW_CTRLD_MODE [13:13] read-only Disable QSPI controller is in MANUAL mode. 0 Enable QSPI controller is working in AUTO MODE. 1 HW_CTRLD_MODE_CTRL_SCLK HW_CTRLD_MODE status [14:14] read-only Disable HW_CTRL_MODE is disabled. 0 Enable HW_CTRL_MODE is enabled 1 AW_CTRL_BUSY Auto write busy indication. [15:15] read-only RESERVED1 reserved1 [31:16] read-only QSPI_INTR_MASK QSPI Interrupt Mask Register 0x24 32 read-write 0x00000000 0x6F QSPI_INTR_MASK Interrupt Status bit [0:0] read-write Disable Do not touch 0 Enable mask the qspi intr 1 FIFO_AEMPTY_RFIFO_MASK NONE [1:1] read-write Disable Do not touch 0 Enable Read fifo almost empty intr mask. 1 FIFO_AFULL_RFIFO_MASK NONE [2:2] read-write Disable Do not touch 0 Enable read fifo almost full intr mask 1 FIFO_AEMPTY_WFIFO_MASK NONE [3:3] read-write Disable Do not touch 0 Enable write fifo almost empty intr mask. 1 FIFO_AFULL_WFIFO_MASK NONE [4:4] read-write Disable Do not touch 0 Enable Write fifo almost full intr mask 1 FIFO_FULL_WFIFO_MASK NONE [5:5] read-write Disable Do not touch 0 Enable write fifo full intr mask 1 FIFO_EMPTY_RFIFO_MASK NONE [6:6] read-write Disable Do not touch 0 Enable Read fifo is empty intr mask 1 AHB_AUTO_WRITE_INTR_MASK Rising interrupt for any auto write operation on AHB bus. This bit is a mask for this interrupt [7:7] read-write QSPI_AUTO_BASE_ADDR_ERR_INTR_MASK Rising interrupt when no csn is selected using programmable auto base address. This bit is a mask for this interrupt. [8:8] read-write M4QSPI_MANUAL_BLOCKED_INTR_MASK Rising interrupt when M4 QSPI tries to do manual mode transactions in Common flash mode (3). This bit is a mask for this interrupt. [9:9] read-write M4_AUTO_READ_OUT_range_intr_mask Rising interrupt when M4 QSPI tries to read TA locations in Common flash mode (3). This bit is a mask for this interrupt. [10:10] read-write RESERVED1 reserved1 [31:11] read-write QSPI_INTR_UNMASK QSPI Interrupt Unmask Register 0x28 32 read-write 0x00000000 0x7F QSPI_INTR_UNMASK Interrupt Status bit [0:0] read-write Disable Do not touch 0 Enable unmask the qspi intr 1 FIFO_AEMPTY_RFIFO_UN NONE [1:1] read-write Disable Do not touch 0 Enable Read fifo almost empty intr unmask 1 FIFO_AFULL_RFIFO_UNMASK NONE [2:2] read-write Disable Do not touch 0 Enable read fifo almost full intr unmask. 1 FIFO_AEMPTY_WFIFO_UNMASK NONE [3:3] read-write Disable Do not touch 0 Enable write fifo almost empty intr unmask 1 FIFO_AFULL_WFIFO_UNMASK NONE [4:4] read-write Disable Do not touch 0 Enable Write fifo almost full intr unmask. 1 FIFO_FULL_WFIFO_UNMASK NONE [5:5] read-write Disable Do not touch 0 Enable write fifo full intr unmask 1 FIFO_EMPTY_RFIFO_UNMASK NONE [6:6] read-write Disable Do not touch 0 Enable Read fifo is empty intr unmask 1 AHB_AUTO_WRITE_INTR_UNMASK Rising interrupt for any auto write operation on AHB bus. This bit is a unmask for this interrupt. [7:7] read-write QSPI_AUTO_BASE_ADDR_ERR_INTR_UNMASK Rising interrupt when M4 QSPI tries to do manual mode transactions in Common flash mode (3). This bit is a unmask for this interrupt. [8:8] read-write M4QSPI_MANUAL_BLOCKED_INTR_UNMASK Rising interrupt when M4 QSPI tries to do manual mode transactions in Common flash mode (3). This bit is a unmask for this interrupt. [9:9] read-write M4_AUTO_READ_OUT_RANGE_INTR_UNMASK Rising interrupt when M4 QSPI tries to read TA locations in Common flash mode (3). This bit is a unmask for this interrupt. [10:10] read-write RESERVED1 reserved1 [31:11] read-write QSPI_INTR_STS QSPI Interrupt Status Register 0x2C 32 read-only 0x0000004A 0x7F QSPI_INTR_LVL Interrupt Status bit [0:0] read-only Disable no interrupt 0 Enable qspi raised a interrupt 1 FIFO_AEMPTY_RFIFO_LVL NONE [1:1] read-only Disable Read fifo does not reached almost empty threshold 0 Enable Read fifo reached almost empty threshold 1 FIFO_AFULL_RFIFO_LVL NONE [2:2] read-only Disable read FIFO do not reached almost full threshold 0 Enable read FIFO reached almost full threshold 1 FIFO_AEMPTY_WFIFO_LVL NONE [3:3] read-only Disable write FIFO not reached almost full threshold. 0 Enable write FIFO reached almost empty threshold. 1 FIFO_AFULL_WFIFO_LVL NONE [4:4] read-only Disable write FIFO not reached almost full threshold 0 Enable Write FIFO reached almost full threshold 1 FIFO_FULL_WFIFO_LVL NONE [5:5] read-only Disable Write fifo not got full 0 Enable write fifo got full. 1 FIFO_EMPTY_RFIFO_LVL NONE [6:6] read-only Disable Read FIFO is not empty 0 Enable Read FIFO is empty 1 AHB_AUTO_WRITE_INTR_LEV rising interrupt for any auto write operation on AHB bus. [7:7] read-only QSPI_AUTO_BASE_ADDR_ERR_INTR_LVL Rising interrupt when no csn is selected using programmable auto base address. [8:8] read-only M4QSPI_MANUAL_BLOCKED_LVL Rising interrupt when M4 QSPI tries to do manual mode transactions in Common flash mode (3). [9:9] read-only M4_AUTO_READ_OUT_RANGE_LVL Rising interrupt when M4 QSPI tries to read TA locations in Common flash mode (3). [10:10] read-only RESERVED1 reserved1 [31:11] read-only QSPI_INTR_ACK QSPI Interrupt Acknowledge Register 0x30 32 read-write 0x00000000 0x7F QSPI_INTR_ACK Interrupt Status bit [0:0] write-only Disable Do not touch 0 Enable unmask the qspi intr. 1 FIFO_AEMPTY_RFIFO_ACK NONE [1:1] write-only Disable Do not touch 0 Enable Read fifo almost empty intr unmask 1 FIFO_AFULL_RFIFO_ACK NONE [2:2] write-only Disable Do not touch 0 Enable read fifo almost full intr unmask. 1 FIFO_AEMPTY_WFIFO_ACK NONE [3:3] write-only Disable Do not touch 0 Enable write fifo almost empty intr unmask. 1 FIFO_AFULL_WFIFO_ACK NONE [4:4] write-only Disable Do not touch 0 Enable Write fifo almost full intr unmask. 1 FIFO_FULL_WFIFO_ACK NONE [5:5] write-only Disable Do not touch 0 Enable write fifo full intr unmask 1 FIFO_EMPTY_RFIFO_ACK NONE [6:6] write-only Disable Do not touch 0 Enable Read fifo is empty intr unmask 1 AHB_AUTO_WRITE_INTR_ACK Rising interrupt for any auto write operation on AHB bus. This bit is an ack for this interrupt. [7:7] write-only QSPI_AUTO_BASE_ADDR_ERR_INTR_ACK Rising interrupt when no csn is selected using programmable auto base address. This bit is an ack for this interrupt. [8:8] write-only M4QSPI_MANUAL_BLOCKED_INTR_ACK Rising interrupt when M4 QSPI tries to do manual mode transactions in Common flash mode (3). This bit is an ack for this interrupt. [9:9] read-write M4_AUTO_READ_OUT_RANGE_INTR_ACK Rising interrupt when M4 QSPI tries to read TA locations in Common flash mode (3). This bit is an ack for this interrupt. [10:10] read-write RESERVED1 reserved1 [31:11] write-only QSPI_STS_MC QSPI State Machine Monitor Register 0x34 32 read-only 0x00000000 0x6FF BUS_CTRL_PSTATE Bus controller present state [3:0] read-only AUTO_CTRL_PSTATE Auto controller present state [6:4] read-only QSPI_MASTER_PSTATE Qspi master present state [9:7] read-only QSPI_MANUAL_RD_CNT Qspi manual read counter value [24:10] read-only RESERVED1 reserved1 [31:25] read-only QSPI_AUTO_CONFIG_1_CSN1 QSPI Auto Controller Configuration 1 CSN1 Register 0x38 32 read-write 0x00000000 0x87FFFF QSPI_EXT_BYTE_MODE_CSN1 Mode of operation of QSPI in instruction phase. [1:0] read-write 00 SPI 0 01 Dual SPI 1 10 Quad SPI 2 11 none 3 QSPI_DUMMY_MODE_CSN1 Mode of operation of QSPI in instruction phase [3:2] read-write 00 SPI 0 01 Dual SPI 1 10 Quad SPI 2 11 none 3 QSPI_ADDR_MODE_CSN1 Mode of operation of QSPI in instruction phase. [5:4] read-write 00 SPI 0 01 Dual SPI 1 10 Quad SPI 2 11 none 3 QSPI_CMD_MODE_CSN1 Mode of operation of QSPI in instruction phase. [7:6] read-write 00 SPI 0 01 Dual SPI 1 10 Quad SPI 2 11 none 3 QSPI_DATA_MODE_CSN1 Mode of operation of QSPI in DATA phase. [9:8] read-write 00 SPI 0 01 Dual SPI 1 10 Quad SPI 2 11 none 3 QSPI_EXTRA_BYTE_CSN1 Value of the extra byte to be transmitted, if the extra byte mode is enabled. [17:10] read-only QSPI_EXTRA_BYTE_EN_CSN1 Mode of operation of QSPI in DATA phase. [19:18] read-write 00 Do not transmit extra byte. 0 01 Transmit Extra byte after address phase 1 10 Transmit only first nibble of the byte and maintain Hi-Z on the IO bus for next nibble. 2 11 none 3 QSPI_WRAP_SIZE Qspi auto wrap size [21:20] read-write RESERVED1 reserved1 [22:22] read-write QSPI_PG_JUMP_CSN1 NONE [23:23] write-only Disable Do not use Index jump instruction. 0 Enable Use Index jump instruction specified by QSPI_PG_JUMP_INST 1 QSPI_DUMMY_BYTES_INCR_CSN1 Specifies the number of dummy bytes 0 to 7 for the selected SPI mode. [27:24] read-only QSPI_DUMMY_BYTES_WRAP_CSN1 Specifies the number of dummy bytes 0 to 7 for the selected SPI mode in case of wrap instruction. [31:28] read-only QSPI_AUTO_CONFIG_2_CSN1 QSPI Auto Controller Configuration 2 CSN1 Register 0x3C 32 read-write 0x00000001 0xFFFFFFFF QSPI_RD_SWAP_AUTO_CSN1 Swap the read data from the flash in byte order for chip select1 csn1 in auto mode. [0:0] read-write Swap_Disable Swap is disabled. 0 Swap_Enable Swap is enabled 1 QSPI_ADR_SIZE_16BIT_AUTO_MODE_CSN1 NONE [1:1] read-write QSPI_CONTI_RD_EN_CSN1 Continuous read enable bit. [2:2] read-write DUMMY_BYTES_WR_RD Dummy bytes to the model to be read or to be write. [3:3] read-write QSPI_DUMMY_BYTES_JMP_CSN1 Dummy cycles to be selected in case of JUMP [7:4] read-write QSPI_RD_INST_CSN1 Read instruction to be used for the selected SPI modes and when wrap is not needed or supported [15:8] read-write QSPI_RD_WRAP_INST_CSN1 Read instruction to be used for the selected SPI modes and when wrap is not needed or supported [23:16] read-write QSPI_PG_JMP_INST_CSN1 Read instruction to be used, when Page jump is to be used. [31:24] read-write QSPI_AUTO_CONFIG_3 QSPI Auto Controller Configuration 3 CSN0 Register 0x90 32 read-write 0x00000001 0xFFFFFFFF QSPI_DUMMY_BYTE_OR_BIT_CSN0 Indicates all above mention values are dummy bytes or bits in auto mode. [0:0] read-write QSPI_DUMMY_BYTES_INCR_CSN0 Specifies the number of dummy bytes for the selected SPI mode. It contains MS nibble for byte. [4:1] read-write QSPI_DUMMY_BYTES_WRAP_CSN0 Specifies the number of dummy bytes for the selected SPI mode in case of wrap instruction. It contains MS nibble for byte. [8:5] read-write RESERVED1 reserved1 [11:9] read-write QSPI_DDR_CMD_MODE_CSN0 DDR Command mode [12:12] read-write Disable Command byte is driven in SDR fashion 0 Enable Command byte is driven in DDR fashion. 1 QSPI_DDR_ADDR_MODE_CSN0 DDR Address mode [13:13] read-write Disable Address bytes are driven in SDR fashion 0 Enable Address bytes are driven in DDR fashion 1 QSPI_DDR_DUMMY_MODE_CSN0 DDR Address mode [14:14] read-write Disable Dummy bytes are driven in SDR fashion 0 Enable Dummy bytes are driven in DDR fashion. 1 QSPI_DDR_EXTRA_MODE_CSN0 DDR Address mode [15:15] read-write Disable Extra byte is driven in SDR fashion 0 Enable Extra byte is driven in DDR fashion 1 QSPI_DDR_DATA_MODE_CSN0 DDR Address mode [16:16] read-write Disable Data are sampled in SDR fashion 0 Enable Data are sampled in DDR fashion 1 QSPI_AUTO_DDR_CMD_MODE_CSN0 DDR data mode. [17:17] read-write QSPI_CMD_SIZE_16BIT_CSN0 Enable for 16 read cmd size for csn0. [18:18] read-write QSPI_ADR_SIZE_32BIT_AUTO_MODE 32 bit addressing support enable. [19:19] read-write QSPI_RD_DATA_SWAP_WORD_LVL_AUTO_CSN0 Rd data swap at word level in auto mode for csn0. It is valid for octa mode. [20:20] read-write RESERVED3 reserved3 [23:21] read-write QSPI_RD_INST_CSN0_MSB Read instruction MS byte to be used the selected SPI modes and when wrap is not needed or supported. [31:24] read-write QSPI_AUTO_CONFIG_3_CSN1 QSPI Auto Controller Configuration 3 CSN1 Register 0x94 32 read-write 0x00000001 0xFFFFFFFF QSPI_DUMMY_BYTE_OR_BIT_CSN1 Indicates all above mention values are dummy bytes or bits in auto mode. [0:0] read-write QSPI_DUMMY_BYTES_INCR_CSN1 Specifies the number of dummy bytes for the selected SPI mode. It contains MS nibble for byte. [4:1] read-write QSPI_DUMMY_BYTES_WRAP_CSN1 Specifies the number of dummy bytes for the selected SPI mode in case of wrap instruction. It contains MS nibble for byte. [8:5] read-write RESERVED1 reserved1 [11:9] read-write QSPI_DDR_CMD_MODE_CSN1 DDR Command mode [12:12] read-write 0 Command byte is driven in SDR fashion 0 1 Command byte is driven in DDR fashion. 1 QSPI_DDR_ADDR_MODE_CSN1 DDR Address mode [13:13] read-write 0 Address bytes are driven in SDR fashion 0 1 Address bytes are driven in DDR fashion 1 QSPI_DDR_DUMMY_MODE_CSN1 DDR Address mode [14:14] read-write 0 Dummy bytes are driven in SDR fashion 0 1 Dummy bytes are driven in DDR fashion. 1 QSPI_DDR_EXTRA_MODE_CSN1 DDR Address mode [15:15] read-write 0 Extra byte is driven in SDR fashion 0 1 Extra byte is driven in DDR fashion 1 QSPI_DDR_DATA_MODE_CSN1 DDR Address mode [16:16] read-write 0 Data are sampled in SDR fashion 0 1 Data are sampled in DDR fashion 1 QSPI_AUTO_DDR_CMD_MODE_CSN1 DDR data mode. [17:17] read-write QSPI_CMD_SIZE_16BIT_CSN1 Enable for 16 read cmd size for csn1. [18:18] read-write RESERVED3 RESERVED3 [19:19] read-write QSPI_RD_DATA_SWAP_WORD_LVL_AUTO_CSN1 Rd data swap at word level in auto mode for csn1. It is valid for octa mode. [20:20] read-write RESERVED4 reserved4 [23:21] read-write QSPI_RD_INST_CSN1_MSB Read instruction MS byte to be used the selected SPI modes and when wrap is not needed or supported. [31:24] read-write QSPI_AUTO_BASE_ADDR_CSN0 none 0xA0 32 read-write 0x00000000 0xFFFFFFFF QSPI_AUTO_BASE_ADDR_CSN0 Holds the 32 bit base address for select chip select0 in programmable auto csn mode. It is valid only programmable auto csn mode is enabled. [31:0] read-write QSPI_AUTO_BASE_ADDR_CSN1 none 0xA4 32 read-write 0x00000000 0xFFFFFFFF QSPI_AUTO_BASE_ADDR_CSN1 Holds the 32 bit base address for select chip select1 in programmable auto csn mode. It is valid only programmable auto csn mode is enabled. [31:0] read-write OCTASPI_BUS_CONTROLLER none 0xB0 32 read-write 0x00000000 0xFFFFFFFF QSPI_D7TOD4_DATA_CSN0 Value of SPI_IO7,6,5 and 4 in case of quad/dual/single mode for chip select1 (cs_n0). It is used both in Auto and Manual Mode. [3:0] read-write QSPI_D7TOD4_OEN_CSN0 Direction Control for SPI_IO 7,6,5 and 4 in case of quad/dual/single mode for chip select0 (cs_n0). It is used both in Auto and Manual Mode. [7:4] read-write QSPI_D7TOD4_DATA_CSN1 Value of SPI_IO7,6,5 and 4 in case of quad/dual/single mode for chip select1 (cs_n1). It is used both in Auto and Manual Mode. [11:8] read-write QSPI_D7TOD4_OEN_CSN1 Direction Control for SPI_IO 7,6,5 and 4 in case of quad/dual/single mode for chip select1 (cs_n1). It is used both in Auto and Manual Mode. [15:12] read-write QSPI_D7TOD4_DATA_CSN2 Value of SPI_IO7,6,5 and 4 in case of quad/dual/single mode for chip select2 (cs_n2). It is used both in Auto and Manual Mode. [19:16] read-write QSPI_D7TOD4_OEN_CSN2 Direction Control for SPI_IO 7,6,5 and 4 in case of quad/dual/single mode for chip select2 (cs_n2). It is used both in Auto and Manual Mode. [23:20] read-write QSPI_D7TOD4_DATA_CSN3 Value of SPI_IO7,6,5 and 4 in case of quad/dual/single mode for chip select3 (cs_n3). It is used both in Auto and Manual Mode. [27:24] read-write QSPI_D7TOD4_OEN_CSN3 Direction Control for SPI_IO 7,6,5 and 4 in case of quad/dual/single mode for chip select3 (cs_n3). It is used both in Auto and Manual Mode. [31:28] read-write QSPI_AUTO_BASE_ADDR_UNMASK_CSN0 none 0xB4 32 read-write 0xFFFFFFFF QSPI_AUTO_BASE_ADDR_UNMASK_CSN0 Holds the 32 bit base address unmask value for select chip select0 in programmable auto csn mode. It is valid only programmable auto csn mode is enabled. [31:0] read-write QSPI_AUTO_BASE_ADDR_UNMASK_CSN1 none 0xB8 32 read-write 0xFFFFFFFF QSPI_AUTO_BASE_ADDR_UNMASK_CSN1 Holds the 32 bit base address unmask value for select chip select1 in programmable auto csn mode. It is valid only programmable auto csn mode is enabled. [31:0] read-write OCTASPI_BUS_CONTROLLER_2 none 0xC4 32 read-write 0x00000000 0xFFFFFFFF SET_IP_MODE This bit enables the qspi interface pins into HiZ mode [0:0] read-write AES_NONCE_INIT This bit enables the AES initialization with nonce [1:1] read-write AES_SEC_ENABLE This bit enables the AES security enable or not [2:2] read-write DUAL_MODE_EN Dual flash mode enable control. [3:3] read-write CSN0_2_CSN Map csn0 to the programmed csn. It is valid for both manual and auto modes [5:4] read-write 00 Not valid 0 01 Map csn0 to csn1. Reads on csn0 will have data from csn1 also 1 10 Map csn0 to csn2. Reads on csn0 will have data from csn2 also 2 11 Map csn0 to csn3. Reads on csn0 will have data from csn3 also 3 CSN1_2_CSN Map csn1 to the programmed csn. It is valid for both manual and auto modes [7:6] read-write 00 Map csn1 to csn0. Reads on csn1 will have data from csn1 also 0 01 Not valid 1 10 Map csn1 to csn2. Reads on csn1 will have data from csn2 also 2 11 Map csn1 to csn3. Reads on csn1 will have data from csn3 also 3 CSN2_2_CSN Map csn2 to the programmed csn. It is valid for both manual and auto modes [9:8] read-write 00 Map csn2 to csn1. Reads on csn2 will have data from csn0 also 0 01 Map csn2 to csn1. Reads on csn2 will have data from csn1 also 1 10 Not valid 2 11 Map csn2 to csn3. Reads on csn2 will have data from csn3 also. 3 CSN3_2_CSN Map csn3 to the programmed csn. It is valid for both manual and auto modes [11:10] read-write 00 Map csn3 to csn0. Reads on csn3 will have data from csn0 also. 0 01 Map csn3 to csn1. Reads on csn3 will have data from csn0 also 1 10 Map csn3 to csn2. Reads on csn3 will have data from csn0 also. 2 11 Not valid 3 AES_SEC_ENABLE_SG1 This bit enables the AES security enable or not for segment 1 [12:12] read-write AES_SEC_ENABLE_SG2 This bit enables the AES security enable or not for segment 2 [13:13] read-write AES_SEC_ENABLE_SG3 This bit enables the AES security enable or not for segment 3 [14:14] read-write AES_SEC_ENABLE_SG4 This bit enables the AES security enable or not for segment 4 [15:15] read-write DUAL_MODE_SWAP_LINES This bit controls the 8 lines of qspi with 4 bit swap manner [16:16] read-write AUTO_MODE_IN_DEFAULT_EN Qspi works in auto mode if set this is bit by default. [17:17] read-write OTP_KEY_LOAD Enable to load key from OTP/KH [18:18] read-write DUAL_STAGE_EN_MANUAL Dual stage en for dual flash mode [19:19] read-write RESERVED2 reserved2 [31:20] read-write QSPI_AES_CONFIG QSPI AES CONFIG REG 0xC8 32 read-write 0x00000080 0xFFFFFFFF QSPI_AES_MODE AES mode of decryption CTR/XTS [8:0] read-write QSPI_AES_DECKEYCAL Enables pre-calculation of KEY before decryption operation [9:9] read-write FLIP_KEY_FRM_REG writing 1 to this Flips the 32-bit endian key taken from kh [10:10] read-write FLIP_KEY_FRM_KH writing 1 to this Flips the 32-bit endian key taken from kh [11:11] read-write QSPI_AES_SRST Synchronous soft reset for AES Module. Write only bit. Reading this bit gives alway 0 [12:12] write-only RESERVED1 reserved1 [31:13] read-write QSPI_AES_KEY_IV_VALID QSPI AES KEYS and IVS VALID 0xCC 32 read-write 0x00000000 0xFFFFFFFF QSPI_AES_KEY1_VALID Write enables for AES KEY 1. Denotes which bytes of key1 is valid [3:0] read-write RESERVED1 reserved1 [7:4] read-write QSPI_AES_KEY2_VALID Write enables for AES KEY 2. Denotes which bytes of key2 is valid [11:8] read-write RESERVED2 reserved2 [15:12] read-write QSPI_AES_IV1_VALID Write enables for AES IV 1. Denotes which bytes of IV1 is valid [19:16] read-write RESERVED3 reserved3 [31:20] read-write QSPI_CMNFLASH_STS QSPI Common Flash Status 0xD0 32 read-only 0x00000000 0xFFFFFFFF QSPI_MANUAL_BLOCKED 1 - Manual read/write transaction initiated is blocked.0- No manual transactions [0:0] read-only AUTO_READ_OUT_RANGE 1- Auto read transaction is out of M4 Address range 0- Auto read transaction is in Address range [1:1] read-only QSPI_AUTO_RD_BUSY 1 - Auto read transactions in progress.0 - No Auto read transactions [2:2] read-only RESERVED1 reserved1 [31:3] read-only QSPI_AES_KEY1_0_3 QSPI_AES_KEY1_0_3 0x134 32 read-write 0x00000000 0xFFFFFFFF QSPI_AES_KEY1_0_3 To hold first 3-0 bytes of aes key1 as 0 referred as lsb in the key [31:0] read-write QSPI_AES_KEY1_4_7 QSPI_AES_KEY1_4_7 0x138 32 read-write 0x00000000 0xFFFFFFFF QSPI_AES_KEY1_4_7 To hold first 7-4 bytes of aes key1 as 0 referred as lsb [31:0] read-write QSPI_AES_KEY1_8_B QSPI_AES_KEY1_8_B 0x13C 32 read-write 0x00000000 0xFFFFFFFF QSPI_AES_KEY1_8_B To hold first 11-8 bytes of aes key1 as 0 referred as lsb [31:0] read-write QSPI_AES_KEY1_C_F QSPI_AES_KEY1_C_F 0x140 32 read-write 0x00000000 0xFFFFFFFF QSPI_AES_KEY1_C_F To hold first 11-8 bytes of aes key1 as 0 referred as lsb [31:0] read-write QSPI_AES_KEY2_0_3 QSPI_AES_KEY2_0_3 0x154 32 read-write 0x00000000 0xFFFFFFFF QSPI_AES_KEY2_0_3 To hold first 3-0 bytes of aes key2 as 0 referred as lsb in the key [31:0] read-write QSPI_AES_KEY2_4_7 QSPI_AES_KEY2_4_7 0x158 32 read-write 0x00000000 0xFFFFFFFF QSPI_AES_KEY2_4_7 To hold first 7-4 bytes of aes key2 as 0 referred as lsb [31:0] read-write QSPI_AES_KEY2_8_B QSPI_AES_KEY2_8_B 0x15C 32 read-write 0x00000000 0xFFFFFFFF QSPI_AES_KEY2_8_B To hold first 11-8 bytes of aes key2 as 0 referred as lsb [31:0] read-write QSPI_AES_KEY2_C_F QSPI_AES_KEY2_C_F 0x160 32 read-write 0x00000000 0xFFFFFFFF QSPI_AES_KEY2_C_F To hold first 15-12 bytes of aes key2 as 0 referred as lsb [31:0] read-write QSPI_AES_SEC_SEG_LS_ADDR_1 QSPI_AES_SEC_SEG_LS_ADDR_1 0xE4 32 read-write 0x00000000 0xFFFFFFFF QSPI_AES_SEC_SEG_LS_ADDR_1 This register specifies the lower boundary address of 1st segment [31:0] read-write QSPI_AES_SEC_SEG_MS_ADDR_1 QSPI_AES_SEC_SEG_MS_ADDR_1 0xE8 32 read-write 0x00000000 0xFFFFFFFF QSPI_AES_SEC_SEG_MS_ADDR_1 This register specifies the upper boundary address of 1st segment [31:0] read-write QSPI_AES_SEC_SEG_LS_ADDR_2 QSPI_AES_SEC_SEG_LS_ADDR_2 0xEC 32 read-write 0x00000000 0xFFFFFFFF QSPI_AES_SEC_SEG_LS_ADDR_2 This register specifies the lower boundary address of 2nd segment [31:0] read-write QSPI_AES_SEC_SEG_MS_ADDR_2 QSPI_AES_SEC_SEG_MS_ADDR_2 0xF0 32 read-write 0x00000000 0xFFFFFFFF QSPI_AES_SEC_SEG_MS_ADDR_2 This register specifies the upper boundary address of 2nd segment [31:0] read-write QSPI_AES_SEC_SEG_LS_ADDR_3 QSPI_AES_SEC_SEG_LS_ADDR_3 0xF4 32 read-write 0x00000000 0xFFFFFFFF QSPI_AES_SEC_SEG_LS_ADDR_3 This register specifies the lower boundary address of 3rd segment [31:0] read-write QSPI_AES_SEC_SEG_MS_ADDR_3 QSPI_AES_SEC_SEG_MS_ADDR_3 0xF8 32 read-write 0x00000000 0xFFFFFFFF QSPI_AES_SEC_SEG_MS_ADDR_3 This register specifies the upper boundary address of 3rd segment [31:0] read-write QSPI_AES_SEC_SEG_LS_ADDR_4 QSPI_AES_SEC_SEG_LS_ADDR_4 0xFC 32 read-write 0x00000000 0xFFFFFFFF QSPI_AES_SEC_SEG_LS_ADDR_4 This register specifies the lower boundary address of 4th segment [31:0] read-write QSPI_AES_SEC_SEG_MS_ADDR_4 QSPI_AES_SEC_SEG_MS_ADDR_4 0x100 32 read-write 0x00000000 0xFFFFFFFF QSPI_AES_SEC_SEG_MS_ADDR_4 This register specifies the upper boundary address of 4th segment [31:0] read-write 2 0x4 0-1 QSPI_SRAM_CTRL_CSNn_REG QSPI SRAM CTRL CSN (0-1) 0x104 QSPI_SRAM_CTRL_CSN_n__REG QSPI SRAM CTRL CSN 0x00 32 read-write 0x00000000 0xFFFFFFFF BIT_8_MODE Flash 8bit (1 byte) boundary mode [0:0] read-write 0 Flash is not with 8bit (1 byte) boundary 0 1 Flash is with 8bit (1 byte) boundary 1 BYTE_32_MODE Flash 32 byte boundary mode [1:1] read-write 0 Flash is not with 32 byte boundary 0 1 Flash is with 32 byte boundary. 1 ADDR_16BIT_MODE Send only lower 16bits of Address enable. [2:2] read-write 0 24 address bit flash is connected 0 1 16 address bit flash is connected 1 RESERVED1 reserved1 [7:3] read-write CMD_MODE writing cmd mode [9:8] read-write 00 Single SPI 0 01 Dual SPI 1 10 Quad SPI 2 11 OCTA SPI 3 ADDR_MODE writing address mode [11:10] read-write 00 Single SPI 0 01 Dual SPI 1 10 Quad SPI 2 11 OCTA SPI 3 DATA_MODE writing address mode [13:12] read-write 00 Single SPI 0 01 Dual SPI 1 10 Quad SPI 2 11 OCTA SPI 3 RESERVED2 reserved2 [15:14] read-write WR_CMD Command to be used for writing [23:16] read-write RESERVED3 reserved3 [31:24] read-write SEMI_AUTO_MODE_ADDR_REG Byte address to read the data from flash in semi auto mode. It is valid only semi auto mode enable bit is asserted 0x11C 32 read-write 0x00000000 0xFFFFFFFF SEMI_AUTO_MODE_CONFIG_REG none 0x120 32 read-write 0x00000000 0xFFFFFFFF QSPI_SEMI_AUTO_BSIZE This is burst size to read data from flash in semi auto mode [7:0] read-write QSPI_SEMI_AUTO_HSIZE Indicates number of bytes valid in each transaction [9:8] read-write 00 1 byte valid 0 01 2 bytes valid 1 10 4 bytes valid 2 11 none 3 RESERVED1 reserved1 [31:10] read-write SEMI_AUTO_MODE_CONFIG2_REG none 0x124 32 read-write 0x00000000 0xFFFFFFFF QSPI_SEMI_AUTO_RD_CNT Total number of bytes to be read flash continuously from the address given by SEMI_AUTO_MODE_ADDR_REG [11:0] read-write QSPI_SEMI_AUTO_MODE_EN Enable for semi auto mode read operation. Make sure manual mode read/write operation is completed before asserting this bit [12:12] read-write QSPI_SEMI_AUTO_RD_BUSY Indicates status of semi auto mode read status. If it is high, semi auto mode read operation is progressing [13:13] read-write RESERVED1 reserved1 [31:14] read-write QSPI_BUS_MODE2_REG none 0x128 32 read-write 0x00000000 0xFFFFFFFF PREFETCH_ENBLD_MSTR_ID Holds the programmable prefetch enabled AHB master ID. This is commonly used for enabling prefetch for icache master. [3:0] read-write PREFETCH_EN_FOR_ICACHE_MSTR Prefetch enable for icache AHB master. [4:4] read-write RESERVED1 Reserved for future use [7:5] read-write QSPI_PREFETCH_ENBLD_TRANS_BYTES Programmable prefetch enabled AHB master transfer bytes. Assume this is used for icache and dma ahb master access in auto mode. [15:8] read-write RESERVED2 Reserved for future use [31:16] read-write QSPI_AES_SEC_KEY_FRM_KH_REG none 0x12C 32 read-write 0x00000000 0xFFFFFFFF START_LOADING_SEC_KEY_FRM_KH Start Security key loading from KH. [0:0] write-only LOADING_SEC_KEY_FRM_KH Indicates security key loading status from KH. [1:1] read-only SEC_KEY_READING_INTERVAL Security key reading interval [5:2] read-write RESERVED1 Reserved for future use [31:6] read-write QSPI_AUTO_CONITNUE_FETCH_CTRL_REG none 0x130 32 read-write 0x00000000 0xFFFFFFFF CONTINUE_FETCH_WAIT_TIMEOUT_VALUE_FRM_REG Maximum Continue fetch wait time between two qspi auto reads. [11:0] read-write CONTINUE_FETCH_EN Continue fetch feature enable. [12:12] read-write RESERVED1 Reserved for future use [31:13] read-write CRC_Accelerator 1.0 CRC is used in all wireless communication as a first data integrity check CRC 0x45080000 32 read-write 0 0x3C registers CRC_DIN_STS Input data status register 0x34 32 read-only 0x00000003 FIFO_EMPTY FIFO empty indication status [0:0] read-only FIFO_AEMPTY FIFO almost empty indication status. [1:1] read-only FIFO_AFULL FIFO almost full indication status [2:2] read-only FIFO_FULL FIFO full indication status [3:3] read-only FIFO_OCC FIFO occupancy [9:4] read-only RESERVED1 Reserved for future use. [31:10] read-only CRC_GEN_CTRL_SET_REG General control set register 0x00 32 read-write 0x0000 0xFFFF SOFT_RST Soft reset. This clears the FIFO and settles all the state machines to their IDLE [0:0] read-write Enable Soft reset will be triggered. 1 Disable No effect 0 RESERVED1 Reserved for future use. [31:1] read-write CRC_GEN_CTRL_RESET General control reset register 0x04 32 read-write 0x0000 RESERVED1 Reserved for future use. [31:0] read-write CRC_GEN_STS General status register 0x08 32 read-only 0x0000 CALC_DONE When the computation of final CRC with the data out of fifo, this will get set to 1 otherwise 0 [0:0] read-only DIN_NUM_BYTES_DONE When number of bytes requested for computation of final CRC is read from fifo by internal FSM, this will get set to 1 otherwise 0. [1:1] read-only RESERVED1 Reserved for future use. [31:2] read-only CRC_POLYNOMIAL This register holds the polynomial with which the final CRC is computed. 0x0C 32 read-write 0x0000 0xFFFF POLYNOMIAL Polynomial register. This register holds the polynomial with which the final CRC is computed.When write Polynomial will be updated.When read read polynomial. [31:0] read-write CRC_POLYNOMIAL_CTRL_SET Polynomial control set register 0x10 32 read-write 0x0000 0xFFFF POLYNOMIAL_WIDTH_SET Polynomial width set. Number of bits/width of the polynomial has to be written here for the computation of final CRC. If a new width has to be configured, clear the existing length first by writing 0x1f in polynomial_ctrl_reset register. When read, actual polynomial width is read. [4:0] read-write RESERVED1 Reserved for future use. [31:5] read-write CRC_POLYNOMIAL_CTRL_RESET Polynomial control set register 0x14 32 read-write 0x0000 0xFFFF POLYNOMIAL_WIDTH_SET Polynomial width reset. If a new width has to be configured, clear the existing length first by writing 0x1f. When read, actual polynomial width is read. [4:0] read-write RESERVED1 Reserved for future use. [31:5] read-write CRC_LFSR_INIT_VAL LFSR initial value 0x18 32 read-write 0x0000 0xFFFF LFSR_INIT This holds LFSR initialization value. When ever LFSR needs to be initialized, this has to be updated with the init value and trigger init_lfsr in LFSR_INIT_CTRL_SET register. For example, in WiFi case, 0xffffffff is used as init value of LFSR. [31:0] read-write CRC_LFSR_INIT_CTRL_SET LFSR state initialization control set register 0x1C 32 read-write 0x0000 0xFFFF CLEAR_LFSR Clear LFSR state. When this is set, LFSR state is cleared to 0 [0:0] read-write Enable LFSR state will be cleared in next cycle 1 Disable No effect 0 INIT_LFSR Initialize LFSR state. When this is set LFSR state will be initialized with LFSR_INIT_VAL/bit swapped LFSR_INIT_VAL in the next cycle [1:1] read-write Enable Initialization will be done in next cycle 1 Disable No effect 0 USE_SWAPPED_INIT_VAL Use bit swapped init value. If this is set bit swapped version of LFSR init value will be loaded / initialized to LFSR state [2:2] read-write Enable write 1 use_swapped_init_val will be enabled read 1 use_swapped_init_val is enabled 1 Disable write 0 No effect read 0 use_swapped_init_val is disabled. 0 RESERVED1 Reserved for future use. [31:3] read-write CRC_LFSR_INIT_CTRL_RESET LFSR state initialization control reset register 0x20 32 read-write 0x0000 0xFFFF RESERVED1 Reserved for future use. [0:0] read-write RESERVED2 Reserved for future use. [1:1] read-write USE_SWAPPED_INIT_VAL Use bit swapped init value. If this is set bit swapped version of LFSR init value will be loaded / initialized to LFSR state [2:2] read-write Enable write 1 use_swapped_init_val will be enabled read 1 use_swapped_init_val is enabled 1 Disable write 0 No effect read 0 use_swapped_init_val is disabled. 0 RESERVED3 Reserved for future use. [31:3] read-write CRC_DIN_FIFO Data input FIFO register 0x24 32 write-only 0x0000 0xFFFF DIN_FIFO FIFO input port is mapped to this register. Data on which the final CRC has to be computed has to be loaded to this FIFO [31:0] write-only CRC_DIN_CTRL_SET Input data control set register 0x28 32 read-write 0x0000 0xFFFF DIN_WIDTH_REG Valid number of bits in the input data in din_width_from_reg set mode. Before writing a new value into this, din_ctrl_reset_reg has to be written with 0x1f to clear this field as these are set/clear bits. [4:0] read-write DIN_WIDTH_FROM_REG Valid number of bits in the input data. In default, number of valid bits in the input data is taken from ULI (uli_be). If this is set, whatever is the input size, only din_ctrl_reg[4:0] is taken as valid length/width for inout data. [5:5] read-write Enable write 1 Din valid width will be taken from reg. read 1 Din valid width is taken from reg. 1 Disable write 0 No effect read 0 Din valid width is not taken from reg 0 DIN_WIDTH_FROM_CNT Valid number of bits in the input data. In default, number of valid bits in the input data is taken from ULI (uli_be). If this is set, a mix of ULI length and number of bytes remaining will form the valid bits (which ever is less that will be considered as valid bits). [6:6] read-write Enable write 1 Din width will be taken from both apb and cnt value. read 1 Din width is from ULI and cnt value. 1 Disable write 0 No effect read 0 Din width does not consider cnt value.This overrides the din_width_from_reg 0 USE_SWAPPED_DIN Use bit swapped input data. If this is set, input data will be swapped and filled in to FIFO. Whatever read out from FIFO will be directly fed to LFSR engine. [7:7] read-write Enable write 1 Bit swapped data will be filled in to FIFO read 1 Bit swapped data is filled in to FIFO 1 Disable write 0 No effect read 0 Direct write data is filled in to FIFO. 0 RESET_FIFO_PTRS Reset fifo pointer. This clears the FIFO.When this is set, FIFO will be cleared. [8:8] read-write Enable write 1 FIFO will be cleared in the next cycle. 1 Disable write 0 No effect 0 RESERVED1 Reserved for future use. [23:9] read-write FIFO_AEMPTY_THRESHOLD FIFO almost empty threshold value. This has to be cleared by writing 0x0f000000 into din_ctrl_reset before updating any new value. [27:24] read-write FIFO_AFULL_THRESHOULD FIFO almost full threshold value. This has to be cleared by writing 0xf0000000 into din_ctrl_reset before updating any new value [31:28] read-write CRC_DIN_CTRL_RESET_REG Input data control set register 0x2C 32 read-write 0x0000 0xFFFF DIN_WIDTH_REG Valid number of bits in the input data in din_width_from_reg set mode. Before writing a new value into this, din_ctrl_reset_reg has to be written with 0x1f to clear this field as these are set/clear bits. [4:0] read-write DIN_WIDTH_FROM_REG Valid number of bits in the input data. In default, number of valid bits in the input data is taken from ULI (uli_be). If this is set, whatever is the input size, only din_ctrl_reg[4:0] is taken as valid length/width for inout data. [5:5] read-write Enable write 1 Din valid width will be taken from reg. read 1 Din valid width is taken from reg. 1 Disable write 0 No effect read 0 Din valid width is not taken from reg 0 DIN_WIDTH_FROM_CNT Valid number of bits in the input data. In default, number of valid bits in the input data is taken from ULI (uli_be). If this is set, a mix of ULI length and number of bytes remaining will form the valid bits (which ever is less that will be considered as valid bits). [6:6] read-write Enable write 1 Din width will be taken from both apb and cnt value. read 1 Din width is from ULI and cnt value. 1 Disable write 0 No effect read 0 Din width does not consider cnt value.This overrides the din_width_from_reg 0 USE_SWAPPED_DIN Use bit swapped input data. If this is set input data will be swapped and filled in to FIFO. Whatever read out from FIFO will be directly fed to LFSR engine. [7:7] read-write Enable write 1 Bit swapped data will be filled in to FIFO read 1 Bit swapped data is filled in to FIFO 1 Disable write 0 No effect read 0 Direct write data is filled in to FIFO. 0 RESERVED1 Reserved for future use. [8:8] read-write RESERVED2 Reserved for future use. [23:9] read-write FIFO_AEMPTY_THRESHOLD FIFO almost empty threshold value. This has to be cleared by writing 0x0f000000 into din_ctrl_reset before updating any new value. [27:24] read-write FIFO_AFULL_THRESHOULD FIFO almost full threshold value. This has to be cleared by writing 0xf0000000 into din_ctrl_reset before updating any new value [31:28] read-write CRC_DIN_NUM_BYTES Data input FIFO register 0x30 32 read-write 0x0000 0xFFFF DIN_NUM_BYTES in out data number of bytes [31:0] read-write CRC_LFSR_STATE LFSR state register 0x38 32 read-write 0x0003 LFSR_STATE If LFSR dynamic loading is required this can be used for writing the LFSR state directly. [31:0] read-write EFUSE_Controller 1.0 The EFUSE controller is used to provide an interface to one time program memory (EFUSE macro) to perform write and read operations EFUSE 0x4600C000 32 read-write 0 0x38 registers EFUSE_DA_ADDR_REG Direct Access Registers 0x00 32 read-write 0x00000000 0xFFFFFFFF ADDR_BITS These bits specifies the address to write or read from EFUSE macro model [15:0] read-write RESERVED1 reserved1 [31:16] read-write EFUSE_DA_CTRL_SET_REG Direct Access Set Registers 0x04 32 read-write 0x00000003 0xFFFFFFFF PGENB Set Program enable [0:0] read-write enable Sets EFUSE program enable (PGENB) pin when direct accessing is enabled 1 disable no effect 0 CSB Set Chip Enable [1:1] read-write enable Sets EFUSE Chip enable (CSB) pin when direct accessing is enabled 1 disable no effect 0 STROBE Set strobe enable [2:2] read-write enable Sets EFUSE STROBE enable (STROBE) pin when direct accessing is enabled 1 disable no effect 0 LOAD Set Load enable [3:3] read-write enable Sets EFUSE load enable (LOAD) pin when direct accessing is enabled 1 disable no effect 0 RESERVED1 reserved1 [15:4] read-write RESERVED2 reserved2 [31:16] read-write EFUSE_DA_CTRL_CLEAR_REG Direct Access Clear Registers 0x08 32 read-write 0x00000003 0xFFFFFFFF PGENB Clear Program enable [0:0] read-write enable Clear EFUSE program enable (PGENB) pin when direct accessing is enabled 1 disable no effect 0 CSB Clear Chip Enable [1:1] read-write enable Clear EFUSE Chip enable (CSB) pin when direct accessing is enabled 1 disable no effect 0 RESERVED1 reserved1 [2:2] read-only LOAD Clear Load enable [3:3] read-write enable Clear EFUSE load enable (LOAD) pin when direct accessing is enabled 1 disable no effect 0 RESERVED2 reserved2 [31:4] read-only EFUSE_CTRL_REG Control Register 0x0C 32 read-write 0x00000000 0xFFFFFFFF EFUSE_ENABLE This bit specifies whether the EFUSE module is enabled or not [0:0] read-write enable EFUSE module enabled 1 disable EFUSE module disabled 0 EFUSE_DIRECT_PATH_ENABLE This bit specifies whether the EFUSE direct path is enabled or not for direct accessing of the EFUSE pins [1:1] read-write enable EFUSE direct accessing enabled 1 disable EFUSE direct accessing disabled 0 ENABLE_EFUSE_WRITE Controls the switch on VDDIQ for eFuse read/write. [2:2] read-write enable VDDIQ is supplied 1 disable VDDIQ is gated 0 RESERVED1 reserved1 [15:3] read-only RESERVED2 reserved2 [31:16] read-only EFUSE_READ_ADDR_REG Read address Register 0x10 32 read-write 0x00008000 0xFFFFFFFF READ_ADDR_BITS These bits specifies the address from which read operation has to be performed [11:0] read-write RESERVED1 reserved1 [14:12] read-only DO_READ Enables read FSM after EFUSE is enabled [15:15] write-only RESERVED2 reserved2 [31:16] read-only EFUSE_READ_DATA_REG Read address Register 0x14 32 read-write 0x00000000 0xFFFFFFFF READ_DATA_BITS These bits specifies the data bits that are read from a given address specified in the EFUSE_READ_ADDRESS_REGISTER bits [8:0] [7:0] read-write RESERVED1 reserved1 [14:8] read-only READ_FSM_DONE Indicates read fsm is done. After this read data is available in EFUSE_READ_DATA_REGISTER bits [7:0] [15:15] read-only RESERVED2 reserved2 [31:16] read-only EFUSE_STATUS_REG Read address Register 0x18 32 read-only 0x00000000 0xFFFFFFFF EFUSE_ENABLED This bit specifies whether the EFUSE is enabled or not [0:0] read-only RESERVED1 reserved1 [1:1] read-only EFUSE_DOUT_SYNC This bit specifies the 8-bit data read out from the EFUSE macro. This is synchronized with pclk [9:2] read-only STROBE_CLEAR_BIT This bit indicates STROBE signal goes low after strobe count value reached '0' [10:10] read-only RESERVED2 reserved2 [15:11] read-only RESERVED3 reserved3 [31:16] read-only EFUSE_RD_TMNG_PARAM_REG none 0x1C 32 read-write 0x00000521 0xFFFFFFFF TSUR_CS CSB to STROBE setup time into read mode [3:0] read-write TSQ Q7-Q0 access time from STROBE rising edge [7:4] read-write THRA for 32x8 macro: A4 A0 to STROBE hold time into Read mode 5122x8 macro: A8 A0 to STROBE hold time into Read mode [11:8] read-write RESERVED1 reserved1 [31:12] read-only EFUSE_MEM_MAP_LENGTH_REG none 0x24 32 read-write 0x00000000 0xFFFFFFFF EFUSE_MEM_MAP_LEN 0: 8 bit read 1: 16 bit read [0:0] read-write RESERVED1 reserved1 [15:1] read-only RESERVED2 reserved2 [31:16] read-only EFUSE_READ_BLOCK_STARTING_LOCATION Starting address from which the read has to be blocked. Once the end address is written, it cannot be changed till power on reset is given 0x28 32 read-write 0x00000000 0xFFFFFFFF EFUSE_READ_BLOCK_STARTING_LOCATION Starting address from which the read has to be blocked. Once the end address is written, it cannot be changed till power on reset is given. [15:0] read-write RESERVED1 reserved1 [31:16] read-only EFUSE_READ_BLOCK_END_LOCATION Starting address from which the read has to be blocked. Once the end address is written, it cannot be changed till power on reset is given 0x2C 32 read-write 0x00000000 0xFFFFFFFF EFUSE_READ_BLOCK_END_LOCATION End address till which the read has to be blocked. Once the end address is written , it cannot be changed till power on reset is given. [15:0] read-write RESERVED1 reserved1 [31:16] read-only EFUSE_READ_BLOCK_ENABLE_REG The Transmit Poll Demand register enables the Transmit DMA to check whether or not the current descriptor is owned by DMA 0x30 32 read-write 0x00000000 0xFFFFFFFF EFUSE_READ_BLOCK_ENABLE Enable for blocking the read access from a programmable memory location [0:0] read-write RESERVED1 reserved1 [15:1] read-only RESERVED2 reserved2 [31:16] read-only EFUSE_DA_CLR_STROBE_REG none 0x34 32 read-write 0x00000000 0xFFFFFFFF EFUSE_STROBE_CLR_CNT Strobe signal Clear count in direct access mode. value depends on APB clock frequency of eFuse controller [8:0] read-write EFUSE_STROBE_ENABLE none [9:9] read-write RESERVED1 reserved1 [31:10] read-only I2S_PCM 1.0 I2S(Inter-IC Sound) is transferring two-channel digital audio data from one IC device to another I2S 0x47050000 32 read-write 0 0x200 registers I2S0 64 I2S_IER I2S Enable Register 0x00 32 read-write 0x00000000 0x1 IEN Inter Block Enable [0:0] read-write Disable Disable DWP_apb_i2s 0 Enable Enable DWP_apb_i2s 1 RESERVED1 Reserved for future use [31:1] read-write I2S_IRER I2S Receiver Block Enable Register 0x04 32 read-write 0x00000000 0x1 RXEN Receive Block Enable, Bit Overrides any Individual Receive Channel Enables [0:0] read-write Disable Disable Receiver 0 Enable Enable Receiver 1 RESERVED1 Reserved for future use [31:1] read-write I2S_ITER Transmitter Block Enable 0x08 32 read-write 0x00000000 0x1 TXEN Transmitter Block Enable, Bit Overrides any Individual Transmit Channel Enables [0:0] read-write Disable Transmit channel is disabled 0 Enable Transmit channel is enabled 1 RESERVED1 Reserved for future use [31:1] read-write I2S_CER Clock Enable Register 0x0C 32 read-write 0x00000000 0x1 CLKEN Clock generation enable/disable [0:0] read-write Disable none 0 Enable none 1 RESERVED1 Reserved for future use [31:1] read-write I2S_CCR Clock Configuration Register 0x10 32 read-write 0x00000000 0x1 SCLKG These bits are used to program the gating of sclk [2:0] read-write WSS These bits are used to program the number of sclk cycles [4:3] read-write RESERVED1 Reserved for future use [31:5] read-write I2S_RXFFR Receiver Block FIFO Reset Register 0x14 32 write-only 0x00000000 0x1 RXFFR Writing a 1 To This Register Flushes All The RX FIFO's Receiver Block Must be Disable Prior to Writing This Bit [0:0] write-only RESERVED1 Reserved for future use [31:1] write-only I2S_TXFFR Transmitter Block FIFO Reset Register 0x18 32 write-only 0x00000000 0x1 TXFFR Writing a 1 To This Register Flushes All The RX FIFO's Receiver Block Must be Disable Prior to Writing This Bit [0:0] write-only RESERVED1 Reserved for future use [31:1] write-only 4 0x4 CHANNEL_CONFIGn Channel config registers (0-3) 0x20 I2S_LRBR_n_ Left Receive Buffer Register 0x00 32 read-only 0x00000000 0xFFFF LRBR Data received serially from the received channel input [23:0] read-only RESERVED1 Reserved for future use [31:24] read-only I2S_LTHR_n_ Left Receive Buffer Register LRBR 0x00 32 write-only 0x00000000 0xFFFF LTHR The Left Stereo Data to be transmitted serially from the Transmitted channel output [23:0] write-only RESERVED1 Reserved for future use [31:24] write-only I2S_RRBR_n_ Right Receive Buffer Register 0x4 32 read-only 0x00000000 0xFFFF RRBR The Right Stereo Data received serially from the received channel input through this register [23:0] read-only RESERVED1 Reserved for future use [31:24] read-only I2S_RTHR_n_ Right Transmit Holding Register RRBR 0x4 32 write-only 0x00000000 0xFFFF RTHR The Right Stereo Data to be transmitted serially from the Transmit channel output written through this register [23:0] write-only RESERVED1 Reserved for future use [31:24] write-only I2S_RER_n_ Receive Enable Register 0x8 32 read-write 0x00000001 0x1 RXCHEN This Bit enables/disables a receive channel independently of all other channels [0:0] read-write Disable Receive Channel is Disable 0 Enable Receive Channel is Disable 1 RESERVED1 Reserved for future use [31:1] read-write I2S_TER_n_ Transmit Enable Register 0xC 32 read-write 0x00000001 0x1 TXCHEN This Bit enables/disables a transmit channel independently of all other channels [0:0] read-write Disable Transmit Channel is Disable 0 Enable Transmit Channel is Enable 1 RESERVED1 Reserved for future use [31:1] read-write I2S_RCR_n_ Receive Configuration Register 0x10 32 read-write 0x0000004 0x7 WLEN This Bits are used to program the desired data resolution of the receiver and enables LSB of the incoming left or right word [2:0] read-write 000 Ignore Word Length 0 001 12 Bit Resolution 1 010 16 Bit Resolution 2 011 20 Bit Resolution 3 100 24 Bit Resolution 4 101 32 Bit Resolution 5 RESERVED1 Reserved for future use [31:3] read-write I2S_TCR_n_ Transmit Configuration Register 0x14 32 read-write 0x00000004 0x7 WLEN This Bits are used to program the desired data resolution of the transmitter and ensure that MSB of the data is transmitted first. [2:0] read-write 000 Ignore Word Length 0 001 12 Bit Resolution 1 010 16 Bit Resolution 2 011 20 Bit Resolution 3 100 24 Bit Resolution 4 101 32 Bit Resolution 5 RESERVED1 Reserved for future use [31:3] read-write I2S_ISR_n_ Interrupt Status Register 0x18 32 read-only 0x00000010 0x33 RXDA Receive Data Available [0:0] read-only Reached trigger level reached 1 Not_reached trigger level not reached 0 RXFO Receive Data FIFO [1:1] read-only Valid RX FIFO Write valid 0 Overrun RX FIFO Write overrun 1 RESERVED1 Reserved for future use [3:2] read-only TXFE Transmit FIFO Empty [4:4] read-only Reached trigger level reached 1 Not_reached trigger level not reached 0 TXFO Transmit FIFO [5:5] read-only Valid TX FIFO Write valid 0 Overrun TX FIFO Write overrun 1 RESERVED2 Reserved for future use [31:6] read-only I2S_IMR_n_ Interrupt Mask Register 0x1C 32 read-write 0x00000033 0x33 RXDAM RX Data Available Mask Interrupt [0:0] read-write Mask Mask Interrupt 1 Unmask Unmask Interrupt 0 RXFOM RX FIFO Overrun Mask Interrupt [1:1] read-write Mask Mask Interrupt 1 Unmask Unmask Interrupt 0 RESERVED1 Reserved for future use [3:2] read-write TXFEM TX FIFO Empty Interrupt [4:4] read-write Mask Mask Interrupt 1 Unmask Unmask Interrupt 0 TXFOM TX FIFO Overrun Interrupt [5:5] read-write Mask Mask Interrupt 1 Unmask Unmask Interrupt 0 RESERVED2 Reserved for future use [31:6] read-write I2S_ROR_n_ Receive Overrun Register 0x20 32 read-only 0x00000000 0x1 RXCHO Read this bit to clear the RX FIFO data overrun interrupt [0:0] read-only Overrun RX FIFO Write Overrun 1 Valid RX FIFO Write Valid 0 RESERVED1 Reserved for future use [31:1] read-only I2S_TOR_n_ Transmit Overrun Register 0x24 32 read-only 0x00000000 0x1 TXCHO Read this bit to clear the TX FIFO data overrun interrupt [0:0] read-only Overrun TX FIFO Write Overrun 1 Valid TX FIFO Write Valid 0 RESERVED1 Reserved for future use [31:1] read-only I2S_RFCR_n_ Receive FIFO Configuration Register0 0x28 32 read-write 0x00000003 0xF RXCHDT This bits program the trigger level in the RX FIFO at which the data available interrupt is generated [3:0] read-write RESERVED1 Reserved for future use [31:4] read-write I2S_TXFCR_n_ Transmit FIFO Configuration Register 0x2C 32 read-write 0x00000003 0xF TXCHET This bits program the trigger level in the TX FIFO at which the Empty Threshold Reached interrupt is generated [3:0] read-write RESERVED1 Reserved for future use [31:4] read-only I2S_RFF_n_ Receive FIFO Flush 0x30 32 write-only 0x00000000 0x01 RXCHFR Writing a 1 to this register flushes an individual RX FIFO RX channel or block must be disable prior to writing to this bit [0:0] write-only RESERVED1 Reserved for future use [31:1] write-only I2S_TFF_n_ Transmit FIFO Flush 0x34 32 write-only 0x00000000 0x01 TXCHFR Writing a 1 to this register flushes an individual TX FIFO TX channel or block must be disable prior to writing to this bit [0:0] write-only RESERVED1 Reserved for future use [31:1] write-only RSVD0 none 0x38 32 read-only 0x00000000 0x01 RSVD1 none 0x3C 32 read-only 0x00000000 0x01 I2S_RXDMA Receiver Block DMA Register 0x1C0 32 read-only 0x00000000 0xFFFF RXDMA Used to cycle repeatedly through the enabled receive channels Reading stereo data pairs [31:0] read-only I2S_RRXDMA Reset Receiver Block DMA Register 0x1C4 32 write-only 0x00000000 0xFFFF RRXDMA Writing a 1 to this self-clearing register resets the RXDMA register [0:0] write-only RESERVED1 Reserved for future use [31:1] write-only I2S_TXDMA Transmitter Block DMA Register 0x1C8 32 write-only 0x00000000 0xFFFF TXDMA Used to cycle repeatedly through the enabled transmit channels allow to writing of stereo data pairs [31:0] write-only I2S_RTXDMA Reset Transmitter Block DMA Register 0x1CC 32 write-only 0x00000000 0xFFFF RTXDMA Writing a 1 to this self-clearing register resets the TXDMA register [0:0] write-only RESERVED1 Reserved1 [31:1] write-only I2S_COMP_PARAM_2 Component Parameter 2 Register 0x1F0 32 read-only 0x00000489 0x1FBF I2S_RX_WORDSIZE_0 On Read returns the value of word size of receiver channel 0 [2:0] read-only I2S_RX_WORDSIZE_1 On Read returns the value of word size of receiver channel 1 [5:3] read-only RESERVED1 Reserved1 [31:6] read-only I2S_COMP_PARAM_1 Component Parameter 1 Register 0x1F4 32 read-only 0x02490069 0xFFF07FF APB_DATA_WIDTH Width of APB data bus [1:0] read-only 0x0 8 Bits 0 0x1 16 Bits 1 0x2 32 Bits 2 0x3 Reserved1 3 I2S_FIFO_DEPTH_GLOBAL Determines FIFO depth for all channels [3:2] read-only 0x0 2 Words deep 0 0x1 4 Words deep 1 0x2 8 Words deep 2 0x3 16 words deep 3 I2S_MODE_EN Determines whether component act as Master or Slave [4:4] read-only Slave Mode 0 Master Mode 1 I2S_TRANSMITTER_BLOCK Shows the presence of the transmitter block [5:5] read-only Absent Block not present 0 Present Block is present 1 I2S_RECEIVER_BLOCK Shows the presence of the receiver block [6:6] read-only Absent Block not present 0 Present Block is present 1 I2S_RX_CHANNELS Returns the number of receiver channels [8:7] read-only 00 1 Channel 0 01 2 Channels 1 10 3 Channels 2 11 4 Channels 3 I2S_TX_CHANNELS Returns the number of transmitter channels [10:9] read-only 00 1 Channel 0 01 2 Channels 1 10 3 Channels 2 11 4 Channels 3 RESERVED1 Reserved1 [15:11] read-only I2S_TX_WORDSIZE_0 Returns the value of word size of transmitter channel 0 [18:16] read-only I2S_TX_WORDSIZE_1 Returns the value of word size of transmitter channel 1 [21:19] read-only RESERVED2 Reserved2 [31:22] read-only I2S_COMP_VERSION_REG Component Version ID 0x1F8 32 read-only 0x3130362a 0xFFFFFFFF I2S_COMP_VERSION Return the component version(1.02) [31:0] read-only I2S_COMP_TYPE_REG Component Type 0x1FC 32 read-only 0x445701a0 0xFFFFFFFF I2S_COMP_TYPE Return the component type [31:0] read-only ULP_I2S 1.0 I2S(Inter-IC Sound) is transferring two-channel digital audio data from one IC device to another I2S 0x24040400 32 read-write 0 0x200 registers I2S1 14 I2S_IER I2S Enable Register 0x00 32 read-write 0x00000000 0x1 IEN Inter Block Enable [0:0] read-write Disable Disable DWP_apb_i2s 0 Enable Enable DWP_apb_i2s 1 RESERVED1 Reserved for future use [31:1] read-write I2S_IRER I2S Receiver Block Enable Register 0x04 32 read-write 0x00000000 0x1 RXEN Receive Block Enable, Bit Overrides any Individual Receive Channel Enables [0:0] read-write Disable Disable Receiver 0 Enable Enable Receiver 1 RESERVED1 Reserved for future use [31:1] read-write I2S_ITER Transmitter Block Enable 0x08 32 read-write 0x00000000 0x1 TXEN Transmitter Block Enable, Bit Overrides any Individual Transmit Channel Enables [0:0] read-write Disable Transmit channel is disabled 0 Enable Transmit channel is enabled 1 RESERVED1 Reserved for future use [31:1] read-write I2S_CER Clock Enable Register 0x0C 32 read-write 0x00000000 0x1 CLKEN Clock generation enable/disable [0:0] read-write Disable none 0 Enable none 1 RESERVED1 Reserved for future use [31:1] read-write I2S_CCR Clock Configuration Register 0x10 32 read-write 0x00000000 0x1 SCLKG These bits are used to program the gating of sclk [2:0] read-write WSS These bits are used to program the number of sclk cycles [4:3] read-write RESERVED1 Reserved for future use [31:5] read-write I2S_RXFFR Receiver Block FIFO Reset Register 0x14 32 write-only 0x00000000 0x1 RXFFR Writing a 1 To This Register Flushes All The RX FIFO's Receiver Block Must be Disable Prior to Writing This Bit [0:0] write-only RESERVED1 Reserved for future use [31:1] write-only I2S_TXFFR Transmitter Block FIFO Reset Register 0x18 32 write-only 0x00000000 0x1 TXFFR Writing a 1 To This Register Flushes All The RX FIFO's Receiver Block Must be Disable Prior to Writing This Bit [0:0] write-only RESERVED1 Reserved for future use [31:1] write-only 4 0x4 CHANNEL_CONFIGn 0x20 I2S_LRBR_n_ Left Receive Buffer Register 0x00 32 read-only 0x00000000 0xFFFF LRBR Data received serially from the received channel input [23:0] read-only RESERVED1 Reserved for future use [31:24] read-only I2S_LTHR_n_ Left Receive Buffer Register LRBR 0x00 32 write-only 0x00000000 0xFFFF LTHR The Left Stereo Data to be transmitted serially from the Transmitted channel output [23:0] write-only RESERVED1 Reserved for future use [31:24] write-only I2S_RRBR_n_ Right Receive Buffer Register 0x4 32 read-only 0x00000000 0xFFFF RRBR The Right Stereo Data received serially from the received channel input through this register [23:0] read-only RESERVED1 Reserved for future use [31:24] read-only I2S_RTHR_n_ Right Transmit Holding Register RRBR 0x4 32 write-only 0x00000000 0xFFFF RTHR The Right Stereo Data to be transmitted serially from the Transmit channel output written through this register [23:0] write-only RESERVED1 Reserved for future use [31:24] write-only I2S_RER_n_ Receive Enable Register 0x8 32 read-write 0x00000001 0x1 RXCHEN This Bit enables/disables a receive channel independently of all other channels [0:0] read-write Disable Receive Channel is Disable 0 Enable Receive Channel is Disable 1 RESERVED1 Reserved for future use [31:1] read-write I2S_TER_n_ Transmit Enable Register 0xC 32 read-write 0x00000001 0x1 TXCHEN This Bit enables/disables a transmit channel independently of all other channels [0:0] read-write Disable Transmit Channel is Disable 0 Enable Transmit Channel is Enable 1 RESERVED1 Reserved for future use [31:1] read-write I2S_RCR_n_ Receive Configuration Register 0x10 32 read-write 0x0000002 0x7 WLEN This Bits are used to program the desired data resolution of the receiver and enables LSB of the incoming left or right word [2:0] read-write 000 Ignore Word Length 0 001 12 Bit Resolution 1 010 16 Bit Resolution 2 011 20 Bit Resolution 3 100 24 Bit Resolution 4 101 32 Bit Resolution 5 RESERVED1 Reserved for future use [31:3] read-write I2S_TCR_n_ Transmit Configuration Register 0x14 32 read-write 0x00000002 0x7 WLEN This Bits are used to program the desired data resolution of the transmitter and ensure that MSB of the data is transmitted first. [2:0] read-write 000 Ignore Word Length 0 001 12 Bit Resolution 1 010 16 Bit Resolution 2 011 20 Bit Resolution 3 100 24 Bit Resolution 4 101 32 Bit Resolution 5 RESERVED1 Reserved for future use [31:3] read-write I2S_ISR_n_ Interrupt Status Register 0x18 32 read-only 0x00000010 0x33 RXDA Receive Data Available [0:0] read-only Reached trigger level reached 1 Not_reached trigger level not reached 0 RXFO Receive Data FIFO [1:1] read-only Valid RX FIFO Write valid 0 Overrun RX FIFO Write overrun 1 RESERVED1 Reserved for future use [3:2] read-only TXFE Transmit FIFO Empty [4:4] read-only Reached trigger level reached 1 Not_reached trigger level not reached 0 TXFO Transmit FIFO [5:5] read-only Valid TX FIFO Write valid 0 Overrun TX FIFO Write overrun 1 RESERVED2 Reserved for future use [31:6] read-only I2S_IMR_n_ Interrupt Mask Register 0x1C 32 read-write 0x00000033 0x33 RXDAM RX Data Available Mask Interrupt [0:0] read-write Mask Mask Interrupt 1 Unmask Unmask Interrupt 0 RXFOM RX FIFO Overrun Mask Interrupt [1:1] read-write Mask Mask Interrupt 1 Unmask Unmask Interrupt 0 RESERVED1 Reserved for future use [3:2] read-write TXFEM TX FIFO Empty Interrupt [4:4] read-write Mask Mask Interrupt 1 Unmask Unmask Interrupt 0 TXFOM TX FIFO Overrun Interrupt [5:5] read-write Mask Mask Interrupt 1 Unmask Unmask Interrupt 0 RESERVED2 Reserved for future use [31:6] read-write I2S_ROR_n_ Receive Overrun Register 0x20 32 read-only 0x00000000 0x1 RXCHO Read this bit to clear the RX FIFO data overrun interrupt [0:0] read-only Overrun RX FIFO Write Overrun 1 Valid RX FIFO Write Valid 0 RESERVED1 Reserved for future use [31:1] read-only I2S_TOR_n_ Transmit Overrun Register 0x24 32 read-only 0x00000000 0x1 TXCHO Read this bit to clear the TX FIFO data overrun interrupt [0:0] read-only Overrun TX FIFO Write Overrun 1 Valid TX FIFO Write Valid 0 RESERVED1 Reserved for future use [31:1] read-only I2S_RFCR_n_ Receive FIFO Configuration Register0 0x28 32 read-write 0x00000003 0xF RXCHDT This bits program the trigger level in the RX FIFO at which the data available interrupt is generated [3:0] read-write RESERVED1 Reserved for future use [31:4] read-write I2S_TXFCR_n_ Transmit FIFO Configuration Register 0x2C 32 read-write 0x00000003 0xF TXCHET This bits program the trigger level in the TX FIFO at which the Empty Threshold Reached interrupt is generated [3:0] read-write RESERVED1 Reserved for future use [31:4] read-only I2S_RFF_n_ Receive FIFO Flush 0x30 32 write-only 0x00000000 0x01 RXCHFR Writing a 1 to this register flushes an individual RX FIFO RX channel or block must be disable prior to writing to this bit [0:0] write-only RESERVED1 Reserved for future use [31:1] write-only I2S_TFF_n_ Transmit FIFO Flush 0x34 32 write-only 0x00000000 0x01 TXCHFR Writing a 1 to this register flushes an individual TX FIFO TX channel or block must be disable prior to writing to this bit [0:0] write-only RESERVED1 Reserved for future use [31:1] write-only RSVD0 none 0x38 32 read-only 0x00000000 0x01 RSVD1 none 0x3C 32 read-only 0x00000000 0x01 I2S_RXDMA Receiver Block DMA Register 0x1C0 32 read-only 0x00000000 0xFFFF RXDMA Used to cycle repeatedly through the enabled receive channels Reading stereo data pairs [31:0] read-only I2S_RRXDMA Reset Receiver Block DMA Register 0x1C4 32 write-only 0x00000000 0xFFFF RRXDMA Writing a 1 to this self-clearing register resets the RXDMA register [0:0] write-only RESERVED1 Reserved for future use [31:1] write-only I2S_TXDMA Transmitter Block DMA Register 0x1C8 32 write-only 0x00000000 0xFFFF TXDMA Used to cycle repeatedly through the enabled transmit channels allow to writing of stereo data pairs [31:0] write-only I2S_RTXDMA Reset Transmitter Block DMA Register 0x1CC 32 write-only 0x00000000 0xFFFF RTXDMA Writing a 1 to this self-clearing register resets the TXDMA register [0:0] write-only RESERVED1 Reserved1 [31:1] write-only I2S_COMP_PARAM_2 Component Parameter 2 Register 0x1F0 32 read-only 0x00000489 0x1FBF I2S_RX_WORDSIZE_0 On Read returns the value of word size of receiver channel 0 [2:0] read-only I2S_RX_WORDSIZE_1 On Read returns the value of word size of receiver channel 1 [5:3] read-only RESERVED1 Reserved1 [6:6] read-only I2S_RX_WORDSIZE_2 On Read returns the value of word size of receiver channel 2 [9:7] read-only I2S_RX_WORDSIZE_3 On Read returns the value of word size of receiver channel 3 [12:10] read-only RESERVED2 Reserved2 [31:13] read-only I2S_COMP_PARAM_1 Component Parameter 1 Register 0x1F4 32 read-only 0x02490069 0xFFF07FF APB_DATA_WIDTH Width of APB data bus [1:0] read-only 0x0 8 Bits 0 0x1 16 Bits 1 0x2 32 Bits 2 0x3 Reserved1 3 I2S_FIFO_DEPTH_GLOBAL Determines FIFO depth for all channels [3:2] read-only 0x0 2 Words deep 0 0x1 4 Words deep 1 0x2 8 Words deep 2 0x3 16 words deep 3 I2S_FIFO_MODE_EN Determines whether component act as Master or Slave [4:4] read-only Slave Mode 0 Master Mode 1 I2S_TRANSMITTER_BLOCK Shows the presence of the transmitter block [5:5] read-only Absent Block not present 0 Present Block is present 1 I2S_RECEIVER_BLOCK Shows the presence of the receiver block [6:6] read-only Absent Block not present 0 Present Block is present 1 I2S_RX_CHANNELS Returns the number of receiver channels [8:7] read-only 00 1 Channel 0 01 2 Channels 1 10 3 Channels 2 11 4 Channels 3 I2S_TX_CHANNELS Returns the number of transmitter channels [10:9] read-only 00 1 Channel 0 01 2 Channels 1 10 3 Channels 2 11 4 Channels 3 RESERVED1 Reserved1 [15:11] read-only I2S_TX_WORDSIZE_0 Returns the value of word size of transmitter channel 0 [18:16] read-only I2S_TX_WORDSIZE_1 Returns the value of word size of transmitter channel 1 [21:19] read-only I2S_TX_WORDSIZE_2 Returns the value of word size of transmitter channel 2 [24:22] read-only I2S_TX_WORDSIZE_3 Returns the value of word size of transmitter channel 3 [27:25] read-only RESERVED2 Reserved2 [31:28] read-only I2S_COMP_VERSION_REG Component Version ID 0x1F8 32 read-only 0x3130362a 0xFFFFFFFF I2S_COMP_VERSION Return the component version(1.02) [31:0] read-only I2S_COMP_TYPE_REG Component Type 0x1FC 32 read-only 0x445701a0 0xFFFFFFFF I2S_COMP_TYPE Return the component type [31:0] read-only IID_AES 1.0 The AES module provides AES encoding and decoding functionality. It can be used in a microprocessor based environment IIDEngine 0x20480500 32 read-write 0 0x104 registers AES_KCR AES Key Control register 0x00 32 read-write 0x00000000 0xFFFFFFFF AES_KEY_CHNG_REQ Programming 1 clears the current key and starts a request a for a new key Auto-reverts to 0 as soon as the request is accepted [0:0] read-write AES_KEY_SIZE Size of the AES key 0: 128-bit 1: 256-bit [1:1] read-write AES_KEY_SRC Source of the AES key 0: Interface 1: Register [7:7] read-write AES_MODE_REG AES Mode register 0x04 32 read-write 0x00000000 0xFFFFFFFF AES_MODE The AES Mode register defines which mode of AES is used. [7:0] read-write AES_ACT_REG AES Action register 0x08 32 read-write 0x00000000 0xFFFFFFFF AES_ACTION The AES Mode register defines which mode of AES is used. [1:0] read-write 00 Idle 0 01 Encode 1 10 Decode 2 11 Clear 3 AES_SR_REG AES Status register 0x20 32 read-only 0x00000000 AES_BUSY Indicates that the AES core is processing data [0:0] read-only Enable Indicates that the AES core is processing data 1 Disable none 0 AES_CLEAR_DONE Indicates that the Clear action is finished [2:2] read-only Enable Indicates that the Clear action is finished 1 Disable none 0 AES_KEY_PRESENT Indicates that the Clear action is finished [3:3] read-only Enable Indicates that a complete key is present 1 Disable none 0 AES_KEY_REQ Indicates that a key must be provided [5:5] read-only Enable Indicates that a key must be provided 1 Disable none 0 AES_DATA_REQ Indicates that data must be provided [6:6] read-only Enable Indicates that data must be provided 1 Disable none 0 AES_DATA_AV Indicates that data is available [7:7] read-only Enable Indicates that data is available 1 Disable none 0 AES_KEY_REG The AES Key register is used to program a key into the AES module. 0x40 32 write-only 0x00000000 AES_KEY 4 writes of 32 bits make up the 128-bit key for AES, 8 writes make up the 256-bit key [31:0] write-only AES_DIN_REG AES Data In register 0x044 32 write-only 0x00000000 AES_DIN Data for encoding or decoding, 4 writes of 32 bits make up a 128-bit data word [31:0] write-only AES_DOUT_REG AES Data out register 0x048 32 read-only 0x00000000 AES_DOUT Result from encoding or decoding, 4 reads of 32 bits make up a 128-bit data word [31:0] read-only AES_IF_SR_C_REG AES Interface Status Clear register AES_IF_SR_REG 0xDC 32 write-only 0x00000000 IFB_ERROR Clears the if_error bit [0:0] write-only AES_IF_SR_REG AES Interface Status register 0xE0 32 read-only 0x00000000 IF_ERROR Indicates that an interface error has occurred [0:0] read-only AES_TEST_REG AES Test register 0xE4 32 read-write 0x00000000 AES_BIST_ENABLE Isolates the iid_aes module and runs a BIST [0:0] read-write AES_BIST_RUNNING BIST is in progress or finishing up [4:4] read-write AES_BIST_ACTIVE Indicates that the BIST is running [5:5] read-write AES_BIST_OK Indicates that the BIST has passed [6:6] read-write AES_BIST_ERROR Indicates that the BIST has failed [7:7] read-write AES_VER_REG AES Version register 0x100 32 read-only 0x00000000 AES_VERSION Version of iid_aes [31:0] read-only IID_QK 1.0 The purpose of Quiddikey is to provide secure key storage without storing the key. IIDEngine 0x20480600 32 read-write 0 0x104 registers QK_CR_REG Quiddikey Control register.The Quiddikey Control register defines which command must be executed next. 0x00 32 write-only 0x00000000 0xFFFFFFFF QK_ZEROIZE Begin Zeroize operation and go to Error state [0:0] write-only QK_ENROLL Begin Enroll operation [1:1] write-only QK_START Begin Start operation [2:2] write-only QK_SET_IK Begin Set Intrinsic Key operation [3:3] write-only QK_SET_UK Begin Set User Key operation [4:4] write-only QK_SET_XK Begin Set External Key operation [5:5] write-only QK_GET_KEY Begin Get Key operation [6:6] write-only QK_KIDX_REG The Quiddikey Key Index register defines the key index for the next set_key command 0x04 32 read-write 0x00000000 0xFFFFFFFF QK_KEY_INDEX Key index for Set Key operations [3:0] read-write QK_KSZ_REG Quiddikey Key Size register 0x08 32 read-write 0x00000000 0xFFFFFFFF QK_KEY_SIZE Key size for Set Key operations [5:0] read-write QK_KT_REG Quiddikey Key Size register 0x0C 32 read-write 0x00000000 0xFFFFFFFF QK_KEY_TARGET Target of reconstructed key [0:0] read-write QK_SR_REG Quiddikey Status register 0x20 32 read-only 0x00000001 0xFFFFFFFF QK_BUSY Indicates that operation is in progress [0:0] read-only QK_OK Last operation was successful [1:1] read-only QK_ERROR Quiddikey is in the Error state and no operations can be performed [2:2] read-only QK_XO_AV Next part of XKPD is available [3:3] read-only QK_KI_REQ Request for next part of key [4:4] read-only QK_KO_AV Next part of key is available [5:5] read-only QK_CI_REQ Request for next part of AC/KC [6:6] read-only QK_CO_AV Next part of AC/KC is available [7:7] read-only QK_AR_REG Quiddikey allow register 0x28 32 read-only 0x00000000 QK_ALLOW_ENROLL Enroll operation is allowed [0:0] read-only QK_ALLOW_START Start operation is allowed [1:1] read-only QK_ALLOW_SET_KEY Set Key operations are allowed [2:2] read-only QK_ALLOW_GET_KEY Get Key operation is allowed [3:3] read-only QK_ALLOW_BIST BIST is allowed to be started [7:7] read-only QK_KI_REG Quiddikey Key Input register 0x40 32 read-write 0x00000000 0xFFFFFFFF QK_KI Key input data [31:0] read-write QK_CI_REG Quiddikey Code Input register 0x44 32 read-write 0x00000000 0xFFFFFFFF QK_CI AC/KC input data [31:0] read-write QK_CO_REG Quiddikey Code Output register 0x48 32 read-only 0x00000000 0xFFFFFFFF QK_CO AC/KC output data [31:0] read-only QK_XO_REG Quiddikey XKPD Output register 0x4C 32 read-only 0x00000000 0xFFFFFFFF QK_XO XKPD output data [31:0] read-only QK_KO_IDX_REG Quiddikey Key Output Index register 0x60 32 read-only 0x00000000 0xFFFFFFFF qk_ko_index Key index for the key that is currently output via the Key Output register [3:0] read-only QK_KO_REG Quiddikey Code Output register 0x64 32 read-only 0x00000000 0xFFFFFFFF QK_KO Key output data [31:0] read-only QK_IF_SR_C_REG Quiddikey Interface Status register QK_IF_SR_REG 0xDC 32 read-only 0x00000000 0xFFFFFFFF IF_ERROR Clears the if_error bit [0:0] read-only QK_IF_SR_REG Quiddikey Interface Status register 0xE0 32 read-only 0x00000000 0xFFFFFFFF IF_ERROR Indicates that an interface error has occurred [0:0] read-only QK_TEST_REG QK Test register 0xE4 32 read-write 0x00000000 QK_BIST_ENABLE Isolates the iid_quiddikey module and runs a BIST [0:0] read-write QK_BIST_RUNNING BIST is in progress or finishing up [4:4] read-write QK_BIST_ACTIVE Indicates that the BIST is running [5:5] read-write QK_BIST_OK Indicates that the BIST has passed [6:6] read-write QK_BIST_ERROR Indicates that the BIST has failed [7:7] read-write QK_VER_REG QK Version register 0x100 32 read-only 0x00000000 QK_VERSION Version of iid_qk [31:0] read-only IID_RPINE 1.0 none IIDEngine 0x20480400 32 read-write 0 0x2C registers IID_BIST_CTRL_REG Quiddikey Control register.The Quiddikey Control register defines which command must be executed next. 0x00 32 read-write 0x00000000 0xFFFFFFFF QK_BIST_ENABLE none [0:0] read-write AES_BIST_ENABLE none [1:1] read-write KH_BIST_ENABLE none [2:2] read-write IID_BIST_STATUS_REG none 0x04 32 read-write 0x00000000 QK_BIST_ACTIVE none [0:0] read-write QK_BIST_ERROR Indicates that the BIST has failed [1:1] read-write QK_BIST_RUNNING Indicates that the BIST is running [3:3] read-write QK_BIST_OK Indicates that the BIST has passed [2:2] read-write AES_BIST_ACTIVE none [4:4] read-write AES_BIST_ERROR none [5:5] read-write AES_BIST_OK Indicates that the BIST has passed [6:6] read-write AES_BIST_RUNNING Indicates that the BIST is running [7:7] read-write KH_BIST_STATUS none [8:8] read-write IID_CTRL_REG none 0x08 32 read-write 0x00000000 AES_MAX_KEY_SIZE 1 256 bit key, 0 128 bit key [0:0] read-write SOURCE_KEY_KH When set KH will source the key to AES engine. When this is not QK key output is connected to AES key input [1:1] read-write LATCH_KEY_KH When set KH will latch the key given by QK. When this is not QK key output is connected to AES key input [2:2] read-write KH_RESET_N 0 KH will be in reset 1 Out of reset [3:3] read-write KH_KEY_SIZE 0 128 bit key 1 256 bit key This is used by KH [4:4] read-write KH_CLOCK_RATIO Indicates the division factor to be used for generating kh_clk. [7:5] read-write WKE_CTRL_REG none 0x0c 32 read-write 0x00000000 ENABLE_WKE When WKE will be enabled. This is a self clearing bit. Once enabled WKE can not be disabled till process is done [0:0] read-write WKE_KEY_SIZE 0 128 bit size 1 256 bit size [1:1] read-write WKE_FLUSH When set, WKE will flush out the data from AES. When WEK is active, firmware reads to AES engine are masked. This gets cleared once four dwords are read from AES [2:2] read-write WKE_COMPARE When set, WKE will compare the data from AES engine with the data provided by firmware [3:3] read-write WKE_SET_KEY This has to be set after key available from AES [4:4] read-write KEY_CODE_DONE This has to be set after reading key code [5:5] read-write IID_AES_CTRL_REG none 0x14 32 read-write 0x00000001 KEY_REQ_IN_DMA_PATH Include key req in dma path. With this KEY Also can be loaded using DMA. [0:0] read-write AES_MAX_KEY_SIZE_FRM_REG This is valid only when aes_max_key_size_frm_reg_en is set. [1:1] read-write AES_MAX_KEY_SIZE_FRM_REG_EN When set, WKE will flush out the data from AES. When WEK is active, firmware reads to AES engine are masked. This gets cleared once four dwords are read from AES [2:2] read-write Enable AES bit length prog enable. 1 Disable AES bit length prog disable. 0 OTP_KEY_LOADING When set, WKE will compare the data from AES engine with the data provided by firmware [3:3] read-write Enable Loads the OTP Key into the AES Engine, before setting this bit, key should be read from the OTP by reading the otp registers, more information please refer the otp section 1 Disable OTP Key will not be loaded 0 IID_AES_STS_REG none 0x18 32 read-only 0x00000000 DIN_FIFO_FULL Input data fifo full indication [0:0] read-only DOUT_FIFO_EMPTY Output data fifo empty indication [1:1] read-only WKE_STATUS_REG none 0x20 32 read-write 0x00000000 WKE_ACTIVE Will be high when WKE is active [0:0] read-write WKE_KEY_FEED_IN_PROGRESS Will be high when WKE is feeding key to AES engine [1:1] read-write WKE_FLUSH_IN_PROGRESS Will be high when WKE flushing out the data from AES [2:2] read-write WKE_COMPARE_IN_PROGRESS Will be high when WKE is comparing the data from AES [3:3] read-write WKE_SET_KEY_IN_PROGRESS Will be high when WKE is doing set key operation with QK [4:4] read-write WKE_KEY_READY Firmware has to load the authentication, which will be compared with AES output, when this bit is low [5:5] read-write WKE_CMP_DATA_READY Firmware has to load the authentication, which will be compared with AES output, when this bit is low [6:6] read-write WKE_COMPARE_FAIL This bit will be set when authentication data comparison fails [7:7] read-write WKE_DATA_REG none 0x28 32 read-write 0x00000000 CT0 1.0 Configurable timer is used in counting clocks, events and states with reference clock external clock and system clock CT 0x45060000 32 read-write 0 0xB0 registers CT 34 CT_GEN_CTRL_SET_REG General control set register 0x00 32 read-write 0x00000000 0xFFFFFFFF COUNTER_IN_32_BIT_MODE Counter_1 and Counter_0 will be merged and used as a single 32 bit counter [0:0] read-write Disable If Write: Counter will be 32 bit mode If Read: Counter is in two 16 bit mode 0 Enable If Write: Counter will be 32 bit mode If Read: Counter is in two 16 bit mode 1 SOFT_RESET_COUNTER_0_FRM_REG This is applied to 32 bits of counter only when the counter is in 32 bit counter mode otherwise this will be applied to only lower 16 bits of counter [1:1] read-write Disable If Write: No effect If Read: Always should return 0 0 Enable If Write: Counter_1 will be reset If Read: Always should return 0 1 PERIODIC_EN_COUNTER_0_FRM_REG This is applied to 32 bits of counter only when the counter is in 32 bit counter mode otherwise this will be applied to only lower 16 bits of counter [2:2] read-write Disable If Write: No effect If Read: Counter_1 is not in periodic mode 0 Enable If Write: Counter_1 will be in periodic mode If Read: Counter_1 is in periodic mode 1 COUNTER_0_TRIG_FRM_REG This enables the counter to run/active [3:3] read-write Disable If Write: No effect If Read:Read should always return 0 0 Enable If Write:Counter_1 will be active If Read:Read should always return 0 1 COUNTER_0_UP_DOWN This enables the counter to run in up/down/up-down/down-up directions [5:4] read-write 00 If Write:No effect If Read:Counter_0 is in down-up counting mode 0 01 If Write:Counter_0 will be up-counting If Read:Counter_0 is in up-counting mode 1 10 If Write:Counter down direction enable If Read:Counter_0 is in down counting mode 2 11 If Write:Both up and down directions enable. If Read:Counter_0 is in up-down counting mode 3 COUNTER_0_SYNC_TRIG This is applied to 32 bits of counter only when the counter is in 32 bit counter mode otherwise this will be applied to only lower 16 bits of counter. This enables the counter to run/active when sync is found. [6:6] read-write Disable If Write: No effect If Read:Read should always return 0 0 Enable If Write:Counter_0 will be active. If Read:Read should always return 0 1 BUF_REG_0_EN Buffer register gets enabled for MATCH REG. MATCH_BUF_REG is always available and whenever this bit is set only, gets copied to MATCH REG. [7:7] read-write Disable If Write: No effect If Read:Buffer is not enabled and not in path. 0 Enable If Write:Buffer will be enabled and in path If Read:Buffer is enabled and in path 1 RESERVED1 Reserved1 [16:8] read-write SOFT_RESET_COUNTER_1_FRM_REG This resets the counter on the write [17:17] read-write Disable If Write:No effect If Read:Always should return 0 0 Enable If Write:Counter_1 will be reset If Read:Always should return 0 1 PERIODIC_EN_COUNTER_1_FRM_REG This resets the counter on the write [18:18] read-write Disable If Write:No effect If Read:Counter_1 is not in periodic mode 0 Enable If Write:Counter_1 will be in periodic mode If Read:Counter_1 is in periodic mode 1 COUNTER_1_TRIG_FRM This enables the counter to run/active [19:19] read-write Disable If Write:No effect If Read:Always should return 0 0 Enable If Write:Counter_1 will be active If Read:Always should return 0 1 COUNTER_1_UP_DOWN This enables the counter to run in upward direction [21:20] read-write 00 If Write:No effect If Read:Counter_1 is in down-up counting mode 0 01 If Write:Counter_1 will be up-counting If Read:Counter_1 is in up-counting mode 1 10 If Write:Counter down direction enable If Read:Counter_1 is in down counting mode 2 11 If Write:Both up and down directions enable. If Read:Counter_1 is in up-down counting mode 3 COUNTER_1_SYNC_TRIG This is applied to 32 bits of counter only when the counter is in 32 bit counter mode otherwise this will be applied to only lower 16 bits of counter. This enables the counter to run/active when sync is found. [22:22] read-write Disable If Write: No effect If Read:Read should always return 0 0 Enable If Write:Counter_1 will be active. If Read:Read should always return 0 1 BUF_REG_1_EN Buffer register gets enabled for MATCH REG. MATCH_BUF_REG is always available and whenever this bit is set only, gets copied to MATCH REG. [23:23] read-write Disable If Write: No effect If Read:Buffer is not enabled and not in path. 0 Enable If Write:Buffer will be enabled and in path If Read:Buffer is enabled and in path 1 RESERVED2 Reserved2 [31:24] read-write CT_GEN_CTRL_RESET_REG General control reset register 0x04 32 read-write 0x00000000 0xFFFFFFFF COUNTER_IN_32_BIT_MODE Counter_1 and Counter_0 will be merged and used as a single 32 bit counter [0:0] read-write Disable If Write: Counter will be 32 bit mode If Read: Counter is in two 16 bit mode 0 Enable If Write: Counter will be 32 bit mode If Read: Counter is in two 16 bit mode 1 Soft_Reset_Counter_0_frm_reg This is a self clear bit in set register. [1:1] read-only PERIODIC_EN_COUNTER_0_FRM_REG This is applied to 32 bits of counter only when the counter is in 32 bit counter mode otherwise this will be applied to only lower 16 bits of counter [2:2] read-write Disable If Write: No effect If Read: Counter_1 is not in periodic mode 0 Enable If Write: Counter_1 will be in periodic mode If Read: Counter_1 is in periodic mode 1 Counter_0_Trig_frm_reg This is a self clear bit in set register. [3:3] read-only COUNTER_0_UP_DOWN This enables the counter to run in up/down/up-down/down-up directions [5:4] read-write 00 If Write:No effect If Read:Counter_0 is in down-up counting mode 0 01 If Write:Counter_0 will be up-counting If Read:Counter_0 is in up-counting mode 1 10 If Write:Counter down direction enable If Read:Counter_0 is in down counting mode 2 11 If Write:Both up and down directions enable. If Read:Counter_0 is in up-down counting mode 3 Counter_0_Sync_Trig This is a self clear bit in set register. [6:6] read-only BUF_REG_0_EN Buffer register gets enabled for MATCH REG. MATCH_BUF_REG is always available and whenever this bit is set only, gets copied to MATCH REG. [7:7] read-write Disable If Write: No effect If Read:Buffer is not enabled and not in path. 0 Enable If Write:Buffer will be enabled and in path If Read:Buffer is enabled and in path 1 RESERVED1 Reserved1 [16:8] read-only Soft_Reset_Counter_1_frm_reg This is a self clear bit in set register. [17:17] read-only PERIODIC_EN_COUNTER_1_FRM_REG This resets the counter on the write [18:18] read-write Disable If Write:No effect If Read:Counter_1 is not in periodic mode 0 Enable If Write:Counter_1 will be in periodic mode If Read:Counter_1 is in periodic mode 1 Counter_1_Trig_frm_reg Self clear bit [19:19] read-only COUNTER_1_UP_DOWN This enables the counter to run in upward direction [21:20] read-write 00 If Write:No effect If Read:Counter_1 is in down-up counting mode 0 01 If Write:Counter_1 will be up-counting If Read:Counter_1 is in up-counting mode 1 10 If Write:Counter down direction enable If Read:Counter_1 is in down counting mode 2 11 If Write:Both up and down directions enable. If Read:Counter_1 is in up-down counting mode 3 Counter_1_sync_trig self clear bit [22:22] read-only BUF_REG_1_EN Buffer register gets enabled for MATCH REG. MATCH_BUF_REG is always available and whenever this bit is set only, gets copied to MATCH REG. [23:23] read-write Disable If Write: No effect If Read:Buffer is not enabled and not in path. 0 Enable If Write:Buffer will be enabled and in path If Read:Buffer is enabled and in path 1 RESERVED2 Reserved2 [31:24] read-only CT_INTR_STS Interrupt status 0x08 32 read-only 0x00000000 INTR_0_L Indicates the FIFO full signal of channel-0 [0:0] read-only FIFO_0_FULL_L Indicates the FIFO full signal of channel-0 [1:1] read-only COUNTER_0_IS_ZERO_L Counter 0 hit zero in active mode. [2:2] read-only COUNTER_0_IS_PEAK_L Counter 0 hit peak (MATCH) in active mode. [3:3] read-only RESERVED1 Reserved1 [15:4] read-only INTR_1_L Indicates the FIFO full signal of channel-1 [16:16] read-only FIFO_1_FULL_L Indicates the FIFO full signal of channel-1 [17:17] read-only COUNTER_1_IS_ZERO_L Counter 1 hit zero in active mode. [18:18] read-only COUNTER_1_IS_PEAK_L Counter 1 hit peak (MATCH) in active mode. [19:19] read-only RESERVED2 Reserved2 [31:20] read-only CT_INTR_MASK Interrupts mask 0x0C 32 read-write 0x00000000 0x0 INTR_0_L Interrupt mask signal. [0:0] read-write Disable If Write: No effect If Read:Interrupt is masked. 0 Enable If Write: Interrupt will be masked. If Read: Interrupt is unmasked. 1 FIFO_0_FULL_L Interrupt mask signal. [1:1] read-write Disable If Write: No effect If Read:Interrupt is masked. 0 Enable If Write: Interrupt will be masked. If Read: Interrupt is unmasked. 1 COUNTER_0_IS_ZERO_L Interrupt mask signal. [2:2] read-write Disable If Write: No effect If Read:Interrupt is masked. 0 Enable If Write: Interrupt will be masked. If Read: Interrupt is unmasked. 1 COUNTER_0_IS_PEAK_L Interrupt mask signal. [3:3] read-write Disable If Write: No effect If Read:Interrupt is masked. 0 Enable If Write: Interrupt will be masked. If Read: Interrupt is unmasked. 1 RESERVED1 Reserved1 [15:4] read-write INTR_1_L Interrupt mask signal. [16:16] read-write Disable If Write: No effect If Read:Interrupt is masked. 0 Enable If Write: Interrupt will be masked. If Read: Interrupt is unmasked. 1 FIFO_1_FULL_L Interrupt mask signal. [17:17] read-write Disable If Write: No effect If Read:Interrupt is masked. 0 Enable If Write: Interrupt will be masked. If Read: Interrupt is unmasked. 1 COUNTER_1_IS_ZERO_L Interrupt mask signal. [18:18] read-write Disable If Write: No effect If Read:Interrupt is masked. 0 Enable If Write: Interrupt will be masked. If Read: Interrupt is unmasked. 1 COUNTER_1_IS_PEAK_L Interrupt mask signal. [19:19] read-write Disable If Write: No effect If Read:Interrupt is masked. 0 Enable If Write: Interrupt will be masked. If Read: Interrupt is unmasked. 1 RESERVED2 Reserved2 [31:20] read-write CT_INTER_UNMASK Interrupts unmask 0x10 32 read-write 0x00000000 0x0 INTR_0_L Interrupt unmask signal. [0:0] read-write Disable If Write: No effect If Read:Interrupt is masked. 0 Enable If Write: Interrupt will be unmasked. If Read: Interrupt is unmasked. 1 FIFO_0_FULL_L Interrupt unmask signal. [1:1] read-write Disable If Write: No effect If Read:Interrupt is masked. 0 Enable If Write: Interrupt will be unmasked. If Read: Interrupt is unmasked. 1 COUNTER_0_IS_ZERO_L Interrupt unmask signal. [2:2] read-write Disable If Write: No effect If Read:Interrupt is masked. 0 Enable If Write: Interrupt will be unmasked. If Read: Interrupt is unmasked. 1 COUNTER_0_IS_PEAK_L Interrupt unmask signal. [3:3] read-write Disable If Write: No effect If Read:Interrupt is masked. 0 Enable If Write: Interrupt will be unmasked. If Read: Interrupt is unmasked. 1 RESERVED1 Reserved1 [15:4] read-only INTR_1_L Interrupt unmask signal. [16:16] read-write Disable If Write: No effect If Read:Interrupt is masked. 0 Enable If Write: Interrupt will be unmasked. If Read: Interrupt is unmasked. 1 FIFO_1_FULL_L Interrupt unmask signal [17:17] read-write Disable If Write: No effect If Read:Interrupt is masked. 0 Enable If Write: Interrupt will be unmasked. If Read: Interrupt is unmasked. 1 COUNTER_1_IS_ZERO_L Interrupt unmask signal. [18:18] read-write Disable If Write: No effect If Read:Interrupt is masked. 0 Enable If Write: Interrupt will be unmasked. If Read: Interrupt is unmasked. 1 COUNTER_1_IS_PEAK_L Interrupt unmask signal. [19:19] read-write Disable If Write: No effect If Read:Interrupt is masked. 0 Enable If Write: Interrupt will be unmasked. If Read: Interrupt is unmasked. 1 RESERVED2 Reserved2 [31:20] read-only CT_INTR_ACK Interrupt clear/ack register 0x14 32 read-write 0x00000000 0x0 INTR_0_L Interrupt ack signal. [0:0] read-write Disable If Write: No effect. If Read: should be returned as this is self clear bit 0 Enable If Write: Interrupt will be de asserted. 1 FIFO_0_FULL_L Interrupt ack signal. [1:1] read-write Disable If Write: No effect. If Read: should be returned as this is self clear bit 0 Enable If Write: Interrupt will be de asserted. 1 COUNTER_0_IS_ZERO_L Interrupt ack signal. [2:2] read-write Disable If Write: No effect. If Read: should be returned as this is self clear bit 0 Enable If Write: Interrupt will be de asserted. 1 COUNTER_0_IS_PEAK_L Interrupt ack signal. [3:3] read-write Disable If Write: No effect. If Read: should be returned as this is self clear bit 0 Enable If Write: Interrupt will be de asserted. 1 RESERVED1 Reserved1 [15:4] read-only INTR_1_L Interrupt ack signal. [16:16] read-write Disable If Write: No effect. If Read: should be returned as this is self clear bit 0 Enable If Write: Interrupt will be de asserted. 1 FIFO_1_FULL_L Interrupt ack signal. [17:17] read-write Disable If Write: No effect. If Read: should be returned as this is self clear bit 0 Enable If Write: Interrupt will be de asserted. 1 COUNTER_1_IS_ZERO_L Interrupt ack signal. [18:18] read-write Disable If Write: No effect. If Read: should be returned as this is self clear bit 0 Enable If Write: Interrupt will be de asserted. 1 COUNTER_1_IS_PEAK_L Interrupt ack signal. [19:19] read-write Disable If Write: No effect. If Read: should be returned as this is self clear bit 0 Enable If Write: Interrupt will be de asserted. 1 RESERVED2 Reserved2 [31:20] read-write CT_MATCH_REG Match value register 0x18 32 read-write 0xFFFFFFFF 0xFFFFFFFF COUNTER_0_MATCH This will be used as lower match [15:0] read-write COUNTER_1_MATCH This will be used as upper match [31:16] read-write CT_MATCH_BUF_REG Match Buffer register 0x1C 32 read-write 0xFFFFFFFF 0xFFFFFFFF COUNTER_0_MATCH_BUF This gets copied to MATCH register if bug_reg_0_en is set. Copying is done when counter 0 is active and hits 0. [15:0] read-write COUNTER_1_MATCH_BUF This gets copied to MATCH register if bug_reg_1_en is set. Copying is done when counter 1 is active and hits 0. [31:16] read-write CT_CAPTURE_REG Capture Register 0x20 32 read-only 0x00000000 COUNTER_0_CAPTURE This is a latched value of counter lower part when the selected capture_event occurs [15:0] read-only COUNTER_1_CAPTURE This is a latched value of counter upper part when the selected capture_event occurs [31:16] read-only CT_COUNTER_REG Counter Register 0x24 32 read-write 0x00000000 COUNTER0 This holds the value of counter-0 [15:0] read-only COUNTER1 This holds the value of counter-1 [31:16] read-only CT_OCU_CTRL_REG OCU control register 0x28 32 read-write 0x00000000 0x7FFFFF OUTPUT_IS_OCU_0 Indicates whether the output is in OCU mode or not for channel-0 [0:0] read-write SYNC_WITH_0 Indicates whether the other channel is in sync with this channel [3:1] read-write OCU_0_DMA_MODE Indicates whether the OCU DMA mode is active or not for channel 0 [4:4] read-write OCU_0_MODE_8_16 Indicates whether entire 16 bits or only 8-bits of the channel 0 are used in OCU mode [5:5] read-write MAKE_OUTPUT_0_HIGH_SEL Check counter ocus for possibilities. When this is hit output will be made high. [8:6] read-write MAKE_OUTPUT_0_LOW_SEL Check counter ocus for possibilities. When this is hit output will be made low. [11:9] read-write RESERVED1 Reserved1 [15:12] read-write OUTPUT_1_IS_OCU Indicates whether the output is in OCU mode or not for channel 1 [16:16] read-write SYNC_WITH_1 Indicates whether the other channel is in sync with this channel [19:17] read-write OCU_1_DMA_MODE Indicates whether the OCU DMA mode is active or not for channel 1 [20:20] read-write OCU_1_MODE_8_16_MODE Indicates whether entire 16 bits or only 8-bits of the channel 1 are used in OCU mode [21:21] read-write MAKE_OUTPUT_1_HIGH_SEL Check counter ocus for possibilities. When this is hit output will be made high. [24:22] read-write MAKE_OUTPUT_1_LOW_SEL Check counter ocus for possibilities. When this is hit output will be made low. [27:25] read-write RESERVED2 Reserved2 [31:28] read-write CT_OCU_COMPARE_REG OCU Compare Register 0x2C 32 read-write 0x00000000 0xFFFF OCU_COMPARE_0_REG Holds the threshold value of present OCU period which denotes the number of clock cycles for which the OCU output should be considered (counter 0) [15:0] read-write OCU_COMPARE_1_REG Holds the threshold value of present OCU period which denotes the number of clock cycles for which the OCU output should be considered (counter 1) [31:16] read-write CT_OCU_COMPARE2_REG OCU Compare2 Register 0x30 32 read-write 0x00000000 0xFFFF OCU_COMPARE2_0_REG Holds the threshold value of present OCU period2 which denotes the number of clock cycles for which the OCU output should be considered (counter 0) [15:0] read-write OCU_COMPARE2_1_REG Holds the threshold value of present OCU period2 which denotes the number of clock cycles for which the OCU output should be considered (counter 1) [31:16] read-write CT_OCU_SYNC_REG OCU Synchronization Register 0x34 32 read-write 0x00000000 0xFFFFFFFF OCU_SYNC_REG_0 Starting point of channel 0 for synchronization purpose [15:0] read-write OCU_SYNC_REG_1 Starting point of channel 1 for synchronization purpose [31:16] read-write CT_OCU_COMPARE_NXT_REG PWM compare next register 0x38 32 read-write 0x00000000 0xFFFFFFFF OCU_COMPARE_NXT_COUNTER1 OCU output should be high for counter 1 [15:0] read-write OCU_COMPARE_NXT_COUNTER0 PWM output should be high for counter 0 [31:16] read-write CT_OCU_COMPARE2_NXT_REG PWM compare next register 0x40 32 read-write 0x00000000 0xFFFFFFFF OCU_COMPARE2_NXT_COUNTER0 OCU output should be high for counter 1 [15:0] read-write OCU_COMPARE2_NXT_COUNTER1 PWM output should be high for counter 0 [31:16] read-write CT_WFG_CTRL_REG WFG control register 0x3C 32 read-write 0x00000000 0x7FFFFF MAKE_OUTPUT_0_TGL_0_SEL Check the counter ocus possibilities for description for channel 0. [2:0] read-write MAKE_OUTPUT_0_TGL_1_SEL Check the counter ocus possibilities for description for channel 0. [5:3] read-write RESERVED1 Reserved1 [7:6] read-write WFG_TGL_CNT_0_PEAK WFG mode output toggle count clock for channel 0. [15:8] read-write MAKE_OUTPUT_1_TGL_0_SEL Check the counter ocus possibilities for description for channel 1. [18:16] read-write MAKE_OUTPUT_1_TGL_1_SEL Check the counter ocus possibilities for description for channel 1. [21:19] read-write RESERVED2 Reserved2 [23:22] read-write WFG_TGL_CNT_1_PEAK WFG mode output toggle count clock for channel 1 [31:24] read-write CT_START_COUNTER_EVENT_SEL Start counter event select register 0x50 32 read-write 0x00000000 0x3F003F START_COUNTER_0_EVENT_SEL For two 16 bit counters mode: Event select for starting the Counter 0 For 32 bit counter mode: Event select for starting counter [5:0] read-write RESERVED1 Reserved1 [15:6] read-write START_COUNTER_1_EVENT_SEL For two 16 bit counters mode: Event select for starting the Counter 1. For 32 bit counter mode: Invalid. Please refer to events table for description [21:16] read-write RESERVED2 Reserved2 [31:22] read-only CT_START_COUNTER_AND_EVENT Start counter AND event register 0x54 32 read-write 0x00000000 0XF000F START_COUNTER_0_AND_EVENT For two 16 bit counter mode: AND expression valids for AND event in start Counter 0 event For 32 bit counter mode AND expression valids for AND event in start counter event [3:0] read-write RESERVED1 Reserved1 [7:4] read-write START_COUNTER_0_AND_VLD none [11:8] read-write RESERVED2 Reserved2 [15:12] read-only START_COUNTER_1_AND_EVENT For two 16 bit counters mode: AND expression valids for AND event in start counter event For 32 bit counter mode : Invalid [19:16] read-write RESERVED3 Reserved3 [23:20] read-only START_COUNTER_1_AND_VLD none [27:24] read-write RESERVED4 Reserved4 [31:28] read-only CT_START_COUNTER_OR_EVENT Start counter OR event register 0x58 32 read-write 0x00000000 0XF000F START_COUNTER_0_OR_EVENT For two 16 bit counter mode: OR expression valids for OR event in start Counter 0 event For 32 bit counter mode OR expression valids for OR event in start counter event [3:0] read-write RESERVED1 Reserved1 [7:4] read-write START_COUNTER_0_OR_VLD none [11:8] read-write RESERVED2 Reserved2 [15:12] read-write START_COUNTER_1_OR_EVENT For two 16 bit counters mode: OR expression valids for OR event in start counter event For 32 bit counter mode : Invalid. [19:16] read-write RESERVED3 Reserved3 [23:20] read-only START_COUNTER_1_OR_VLD none [27:24] read-write RESERVED4 Reserved4 [31:28] read-only CT_CONTINUE_COUNTER_EVENT_SEL Continue counter event select register 0x5C 32 read-write 0x00000000 0X3F003F CONTINUE_COUNTER_0_EVENT_SEL For two 16 bit counters mode: Event select for continuing the Counter 0 For 32 bit counter mode: Event select for continuing counter [5:0] read-write RESERVED1 Reserved1 [15:6] read-write CONTINUE_COUNTER_1_EVENT_SEL For two 16 bit counters mode: Event select for continuing the Counter 1 For 32 bit counter mode: Invalid. [21:16] read-write RESERVED2 Reserved2 [31:22] read-only CT_CONTINUE_COUNTER_AND_EVENT Continue counter AND event register 0x60 32 read-write 0x00000000 0XF000F CONTINUE_COUNTER_0_AND_EVENT For two 16 bit counter mode: AND expression valids for AND event in continue Counter 0 event For 32 bit counter mode AND expression valids for AND event in continue counter event. [3:0] read-write RESERVED1 Reserved1 [7:4] read-write CONTINUE_COUNTER_0_AND_VLD none [11:8] read-write RESERVED2 Reserved2 [15:12] read-write CONTINUE_COUNTER_1_AND_EVENT For two 16 bit counters mode: AND expression valids for AND event in continue counter event For 32 bit counter mode : Invalid [19:16] read-write RESERVED3 Reserved3 [23:20] read-only CONTINUE_COUNTER_1_AND_VLD none [27:24] read-write RESERVED4 Reserved4 [31:28] read-only CT_CONTINUE_COUNTER_OR_EVENT Continue counter OR event register 0x64 32 read-write 0x00000000 0XF000F CONTINUE_COUNTER_0_OR_EVENT For two 16 bit counter mode: OR expression valids for OR event in continue Counter 0 event For 32 bit counter mode OR expression valids for OR event in continue counter event [3:0] read-write RESERVED1 Reserved1 [7:4] read-write CONTINUE_COUNTER_0_OR_VLD none [11:8] read-write RESERVED2 Reserved2 [15:12] read-write CONTINUE_COUNTER_1_OR_EVENT For two 16 bit counters mode: OR expression valids for OR event in continue counter event For 32 bit counter mode : Invalid [19:16] read-write RESERVED3 Reserved3 [23:20] read-only CONTINUE_COUNTER_1_OR_VLD none [27:24] read-write RESERVED4 Reserved4 [31:28] read-only CT_STOP_COUNTER_EVENT_SEL Stop counter event select register 0x68 32 read-write 0x00000000 0X3F003F STOP_COUNTER_0_EVENT_SEL For two 16 bit counters mode: Event select for Stopping the Counter 0 For 32 bit counter mode: Event select for Stopping counter [5:0] read-write RESERVED1 Reserved1 [15:6] read-write STOP_COUNTER_1_EVENT_SEL For two 16 bit counters mode: Event select for Stopping the Counter 1 For 32 bit counter mode: Invalid [21:16] read-write RESERVED2 Reserved2 [31:22] read-only CT_STOP_COUNTER_AND_EVENT Stop counter AND event register 0x6C 32 read-write 0x00000000 0XF000F STOP_COUNTER_0_AND_EVENT For two 16 bit counter mode: AND expression valids for AND event in stop Counter 0 event For 32 bit counter mode AND expression valids for AND event in stop counter event [3:0] read-write RESERVED1 Reserved1 [7:4] read-write STOP_COUNTER_0_AND_VLD Indicates which bits in [3:0] are valid for considering AND event [11:8] read-write RESERVED2 Reserved2 [15:12] read-write STOP_COUNTER_1_AND_EVENT For two 16 bit counters mode: AND expression valids for AND event in stop counter event For 32 bit counter mode : Invalid [19:16] read-write RESERVED3 Reserved3 [23:20] read-only STOP_COUNTER_1_AND_VLD none [27:24] read-write RESERVED4 Reserved4 [31:28] read-only CT_STOP_COUNTER_OR_EVENT Stop counter OR event register 0x70 32 read-write 0x00000000 0XF000F STOP_COUNTER_0_OR_EVENT For two 16 bit counter mode: OR expression valids for OR event in Stop Counter 0 event For 32 bit counter mode OR expression valids for OR event in Stop counter event [3:0] read-write RESERVED1 Reserved1 [7:4] read-write STOP_COUNTER_0_OR_VLD none [11:8] read-write RESERVED2 Reserved2 [15:12] read-write STOP_COUNTER_1_OR_EVENT For two 16 bit counters mode: OR expression valids for OR event in Stop counter event For 32 bit counter mode : Invalid [19:16] read-write RESERVED3 Reserved3 [23:20] read-only STOP_COUNTER_1_OR_VLD none [27:24] read-write RESERVED4 Reserved4 [31:28] read-only CT_HALT_COUNTER_EVENT_SEL Halt counter event select register 0x74 32 read-write 0x00000000 0X3F003F HALT_COUNTER_0_EVENT_SEL For two 16 bit counters mode: Event select for Halting the Counter 0 For 32 bit counter mode: Event select for Halting counter [5:0] read-write RESUME_FROM_HALT_COUNTER_0 For two 16 bit counters mode: Event select for Halting the Counter 0 For 32 bit counter mode: Event select for Halting counter [6:6] write-only RESERVED1 Reserved1 [15:7] read-only HALT_COUNTER_1_EVENT_SEL For two 16 bit counters mode: Event select for Halting the Counter 1 For 32 bit counter mode: Invalid [21:16] read-write RESUME_FROM_HALT_COUNTER_1 For two 16 bit counters mode: Event select for Halting the Counter 0 For 32 bit counter mode: Event select for Halting counter [22:22] write-only RESERVED2 Reserved2 [31:23] read-only CT_HALT_COUNTER_AND_EVENT Halt counter AND event register 0x78 32 read-write 0x00000000 0XF000F HALT_COUNTER_0_AND_EVENT For two 16 bit counter mode: AND expression valids for AND event in stop Counter 0 event For 32 bit counter mode AND expression valids for AND event in stop counter event [3:0] read-write RESERVED1 Reserved1 [7:4] read-write HALT_COUNTER_0_AND_VLD Indicates which bits in [3:0] are valid for considering AND event [11:8] read-write RESERVED2 Reserved2 [15:12] read-only HALT_COUNTER_1_AND_EVENT For two 16 bit counters mode: AND expression valids for AND event in stop counter event For 32 bit counter mode : Invalid [19:16] read-write RESERVED3 Reserved3 [23:20] read-only HALT_COUNTER_1_AND_VLD none [27:24] read-write RESERVED4 Reserved4 [31:28] read-only CT_HALT_COUNTER_OR_EVENT Halt counter OR event register 0x7C 32 read-write 0x00000000 0XF000F HALT_COUNTER_0_OR_EVENT For two 16 bit counter mode: OR expression valids for OR event in Halt Counter 0 event For 32 bit counter mode OR expression valids for OR event in Halt counter event [3:0] read-write RESERVED1 Reserved1 [7:4] read-write HALT_COUNTER_0_OR_VLD none [11:8] read-write RESERVED2 Reserved2 [15:12] read-only HALT_COUNTER_1_OR_EVENT For two 16 bit counters mode: OR expression valids for OR event in Halt counter event For 32 bit counter mode : Invalid [19:16] read-write RESERVED3 Reserved3 [23:20] read-only HALT_COUNTER_1_OR_VLD none [27:24] read-write RESERVED4 Reserved4 [31:28] read-only CT_INCREMENT_COUNTER_EVENT_SEL Increment counter event select register 0x80 32 read-write 0x00000000 0X3F003F INCREMENT_COUNTER_0_EVENT_SEL For two 16 bit counters mode: Event select for Incrementing the Counter 0 For 32 bit counter mode: Event select for Incrementing counter [5:0] read-write RESERVED1 Reserved1 [15:6] read-only INCREMENT_COUNTER_1_EVENT_SEL For two 16 bit counters mode: Event select for Incrementing the Counter 1 For 32 bit counter mode: Invalid [21:16] read-write RESERVED2 Reserved2 [31:22] read-only CT_INCREMENT_COUNTER_AND_EVENT Increment counter AND event register 0x84 32 read-write 0x00000000 0XF000F INCREMENT_COUNTER_0_AND_EVENT For two 16 bit counter mode: AND expression valids for AND event in stop Counter 0 event For 32 bit counter mode AND expression valids for AND event in stop counter event [3:0] read-write RESERVED1 Reserved1 [7:4] read-write INCREMENT_COUNTER_0_AND_VLD none [11:8] read-write RESERVED2 Reserved2 [15:12] read-only INCREMENT_COUNTER_1_AND_EVENT For two 16 bit counters mode: AND expression valids for AND event in stop counter event For 32 bit counter mode : Invalid [19:16] read-write RESERVED3 Reserved3 [23:20] read-only INCREMENT_COUNTER_1_AND_VLD none [27:24] read-write RESERVED4 Reserved4 [31:28] read-only CT_INCREMENT_COUNTER_OR_EVENT Increment counter OR event register 0x88 32 read-write 0x00000000 0XF000F INCREMENT_COUNTER_0_OR_EVENT For two 16 bit counter mode: OR expression valids for OR event in Increment Counter 0 event For 32 bit counter mode OR expression valids for OR event in Increment counter event [3:0] read-write RESERVED1 Reserved1 [7:4] read-write INCREMENT_COUNTER_0_OR_VLD none [11:8] read-write RESERVED2 Reserved2 [15:12] read-only INCREMENT_COUNTER_1_OR_EVENT For two 16 bit counters mode: OR expression valids for OR event in Increment counter event For 32 bit counter mode : Invalid [19:16] read-write RESERVED4 Reserved4 [23:20] read-only INCREMENT_COUNTER_1_OR_VLD none [27:24] read-write RESERVED5 Reserved5 [31:28] read-only CT_CAPTURE_COUNTER_EVENT_SEL Capture counter event select register 0x8C 32 read-write 0x00000000 0X3F003F CAPTURE_COUNTER_0_EVENT_SEL For two 16 bit counters mode: Event select for Capturing the Counter 0 For 32 bit counter mode: Event select for Capturing counter [5:0] read-write RESERVED1 Reserved1 [15:6] read-only CAPTURE_COUNTER_1_EVENT_SEL For two 16 bit counters mode: Event select for Capturing the Counter 1 For 32 bit counter mode : Invalid [21:16] read-write RESERVED2 Reserved2 [31:22] read-only CT_CAPTURE_COUNTER_AND_EVENT Capture counter AND event register 0x90 32 read-write 0x00000000 0XF000F CAPTURE_COUNTER_0_AND_EVENT For two 16 bit counter mode: AND expression valids for AND event in stop Counter 0 event For 32 bit counter mode AND expression valids for AND event in stop counter event [3:0] read-write RESERVED1 Reserved1 [7:4] read-write CAPTURE_COUNTER_0_AND_VLD none [11:8] read-write RESERVED2 Reserved2 [15:12] read-only CAPTURE_COUNTER_1_AND_EVENT For two 16 bit counters mode: AND expression valids for AND event in stop counter event For 32 bit counter mode : Invalid [19:16] read-write RESERVED3 Reserved3 [23:20] read-only CAPTURE_COUNTER_1_AND_VLD none [27:24] read-write RESERVED4 Reserved4 [31:28] read-only CT_CAPTURE_COUNTER_OR_EVENT Capture counter OR event register 0x94 32 read-write 0x00000000 0XF000F CAPTURE_COUNTER_0_OR_EVENT For two 16 bit counter mode: OR expression valids for OR event in Capture Counter 0 event For 32 bit counter mode OR expression valids for OR event in Capture counter event [3:0] read-write RESERVED1 Reserved1 [7:4] read-write CAPTURE_COUNTER_0_OR_VLD none [11:8] read-write RESERVED2 Reserved2 [15:12] read-only CAPTURE_COUNTER_1_OR_EVENT For two 16 bit counters mode: OR expression valids for OR event in Capture counter event For 32 bit counter mode : Invalid [19:16] read-write RESERVED3 Reserved3 [23:20] read-only CAPTURE_COUNTER_1_OR_VLD none [27:24] read-write RESERVED4 Reserved4 [31:28] read-only CT_OUTPUT_EVENT_SEL Output event select register 0x98 32 read-write 0x00000000 0X3F003F OUTPUT_EVENT_SEL_0 For two 16 bit counters mode: Event select for output event from Counter 0 For 32 bit counter mode: Event select for output event [5:0] read-write RESERVED1 Reserved1 [15:6] read-only OUTPUT_EVENT_SEL_1 For two 16 bit counters mode: Event select for output event from counter 1 For 32 bit counter mode : Invalid [21:16] read-write RESERVED2 Reserved2 [31:22] read-only CT_OUTPUT_AND_EVENT_REG Output AND event Register 0x9C 32 read-write 0x00000000 0xFFFFFFFF OUTPUT_0_AND_EVENT AND expression for AND event in output Counter_0 event. [3:0] read-write RESERVED1 Reserved1 [7:4] read-write OUTPUT_0_AND_VLD AND expression for AND event in output Counter_0 event. [11:8] read-write RESERVED2 Reserved2 [15:12] read-only OUTPUT_1_AND_EVENT AND expression for AND event in output Counter_1 event. [19:16] read-write RESERVED3 Reserved3 [23:20] read-only OUTPUT_1_AND_VLD AND expression for AND event in output Counter_1 event. [27:24] read-write RESERVED4 Reserved4 [31:28] read-only CT_OUTPUT_OR_EVENT Output OR event Register 0xA0 32 read-write 0x00000000 0xFFFFFFFF OUTPUT_0_OR_EVENT OR expression for OR event in output Counter_0 event [3:0] read-write RESERVED1 Reserved1 [7:4] read-write OUTPUT_0_OR_VLD Indicates which bits in [3:0] are valid for considering OR event [11:8] read-write RESERVED2 Reserved2 [15:12] read-only OUTPUT_1_OR_EVENT OR expression for OR event in output Counter_0 event [19:16] read-write RESERVED3 Reserved3 [23:20] read-only OUTPUT_1_OR_VLD Indicates which bits in [3:0] are valid for considering OR event [27:24] read-write RESERVED4 Reserved4 [31:28] read-only CT_INTR_EVENT_SEL Interrupt Event Select Register 0xA4 32 read-write 0x00000000 0X3F003F INTR_EVENT_SEL_0 For two 16 bit counters mode: Event select for interrupt event from Counter 0 For 32 bit counter mode: Event select for output event [5:0] read-write RESERVED1 Reserved1 [15:6] read-only INTR_EVENT_SEL_1 For two 16 bit counters mode: Event select for interrupt event from counter 1 For 32 bit counter mode : Invalid [21:16] read-write RESERVED2 Reserved2 [31:22] read-only CT_INTR_AND_EVENT Interrupt AND Event Register 0xA8 32 read-write 0x00000000 0X3F003F INTR_0_AND_EVENT None [3:0] read-write RESERVED1 Reserved1 [7:4] read-write INTR_0_AND_VLD None [11:8] read-write RESERVED2 Reserved2 [15:12] read-only INTR_1_AND_EVENT None [19:16] read-write RESERVED3 Reserved3 [23:20] read-only INTR_1_AND_VLD None [27:24] read-write RESERVED4 Reserved4 [31:28] read-only CT_INTR_OR_EVENT_REG Interrupt OR Event Register 0xAC 32 read-write 0x00000000 0X3F003F INTR_0_OR_EVENT None [3:0] read-write RESERVED1 Reserved1 [7:4] read-write INTR_0_OR_VLD None [11:8] read-write RESERVED2 Reserved2 [15:12] read-only INTR_1_OR_EVENT None [19:16] read-write RESERVED3 Reserved3 [23:20] read-only INTR_1_OR_VLD None [27:24] read-write RESERVED4 Reserved4 [31:28] read-only CT_RE_FE_RFE_LEV0_LEV1_EVENT_ENABLE_REG Rising Edge Falling Edge Rising and Falling Edge level0 level1 event enable register 0xB0 32 read-write 0x000FFFFF 0X000FFFFF Input_Event_RE_Enable Input event rising edge enables [3:0] read-write Input_Event_FE_Enable Input event falling edge enables: [7:4] read-write Input_Event_RFE_Enable Input event rising and falling edge enables [11:8] read-write Input_Event_lev0_Enable Input event level0 enables [15:12] read-write Input_Event_lev1_Enable Input event level1 enables [19:16] read-write RESERVED Reserved [31:20] read-only CT1 1.0 Configurable timer is used in counting clocks, events and states with reference clock external clock and system clock CT 0x45060100 32 read-write 0 0xB0 registers CT 34 CT_GEN_CTRL_SET_REG General control set register 0x00 32 read-write 0x00000000 0xFFFFFFFF COUNTER_IN_32_BIT_MODE Counter_1 and Counter_0 will be merged and used as a single 32 bit counter [0:0] read-write Disable If Write: Counter will be 32 bit mode If Read: Counter is in two 16 bit mode 0 Enable If Write: Counter will be 32 bit mode If Read: Counter is in two 16 bit mode 1 SOFT_RESET_COUNTER_0_FRM_REG This is applied to 32 bits of counter only when the counter is in 32 bit counter mode otherwise this will be applied to only lower 16 bits of counter [1:1] read-write Disable If Write: No effect If Read: Always should return 0 0 Enable If Write: Counter_1 will be reset If Read: Always should return 0 1 PERIODIC_EN_COUNTER_0_FRM_REG This is applied to 32 bits of counter only when the counter is in 32 bit counter mode otherwise this will be applied to only lower 16 bits of counter [2:2] read-write Disable If Write: No effect If Read: Counter_1 is not in periodic mode 0 Enable If Write: Counter_1 will be in periodic mode If Read: Counter_1 is in periodic mode 1 COUNTER_0_TRIG_FRM_REG This enables the counter to run/active [3:3] read-write Disable If Write: No effect If Read:Read should always return 0 0 Enable If Write:Counter_1 will be active If Read:Read should always return 0 1 COUNTER_0_UP_DOWN This enables the counter to run in up/down/up-down/down-up directions [5:4] read-write 00 If Write:No effect If Read:Counter_0 is in down-up counting mode 0 01 If Write:Counter_0 will be up-counting If Read:Counter_0 is in up-counting mode 1 10 If Write:Counter down direction enable If Read:Counter_0 is in down counting mode 2 11 If Write:Both up and down directions enable. If Read:Counter_0 is in up-down counting mode 3 COUNTER_0_SYNC_TRIG This is applied to 32 bits of counter only when the counter is in 32 bit counter mode otherwise this will be applied to only lower 16 bits of counter. This enables the counter to run/active when sync is found. [6:6] read-write Disable If Write: No effect If Read:Read should always return 0 0 Enable If Write:Counter_0 will be active. If Read:Read should always return 0 1 BUF_REG_0_EN Buffer register gets enabled for MATCH REG. MATCH_BUF_REG is always available and whenever this bit is set only, gets copied to MATCH REG. [7:7] read-write Disable If Write: No effect If Read:Buffer is not enabled and not in path. 0 Enable If Write:Buffer will be enabled and in path If Read:Buffer is enabled and in path 1 RESERVED1 Reserved1 [16:8] read-write SOFT_RESET_COUNTER_1_FRM_REG This resets the counter on the write [17:17] read-write Disable If Write:No effect If Read:Always should return 0 0 Enable If Write:Counter_1 will be reset If Read:Always should return 0 1 PERIODIC_EN_COUNTER_1_FRM_REG This resets the counter on the write [18:18] read-write Disable If Write:No effect If Read:Counter_1 is not in periodic mode 0 Enable If Write:Counter_1 will be in periodic mode If Read:Counter_1 is in periodic mode 1 COUNTER_1_TRIG_FRM This enables the counter to run/active [19:19] read-write Disable If Write:No effect If Read:Always should return 0 0 Enable If Write:Counter_1 will be active If Read:Always should return 0 1 COUNTER_1_UP_DOWN This enables the counter to run in upward direction [21:20] read-write 00 If Write:No effect If Read:Counter_1 is in down-up counting mode 0 01 If Write:Counter_1 will be up-counting If Read:Counter_1 is in up-counting mode 1 10 If Write:Counter down direction enable If Read:Counter_1 is in down counting mode 2 11 If Write:Both up and down directions enable. If Read:Counter_1 is in up-down counting mode 3 COUNTER_1_SYNC_TRIG This is applied to 32 bits of counter only when the counter is in 32 bit counter mode otherwise this will be applied to only lower 16 bits of counter. This enables the counter to run/active when sync is found. [22:22] read-write Disable If Write: No effect If Read:Read should always return 0 0 Enable If Write:Counter_1 will be active. If Read:Read should always return 0 1 BUF_REG_1_EN Buffer register gets enabled for MATCH REG. MATCH_BUF_REG is always available and whenever this bit is set only, gets copied to MATCH REG. [23:23] read-write Disable If Write: No effect If Read:Buffer is not enabled and not in path. 0 Enable If Write:Buffer will be enabled and in path If Read:Buffer is enabled and in path 1 RESERVED2 Reserved2 [31:24] read-write CT_GEN_CTRL_RESET_REG General control reset register 0x04 32 read-write 0x00000000 0xFFFFFFFF COUNTER_IN_32_BIT_MODE Counter_1 and Counter_0 will be merged and used as a single 32 bit counter [0:0] read-write Disable If Write: Counter will be 32 bit mode If Read: Counter is in two 16 bit mode 0 Enable If Write: Counter will be 32 bit mode If Read: Counter is in two 16 bit mode 1 Soft_Reset_Counter_0_frm_reg This is a self clear bit in set register. [1:1] read-only PERIODIC_EN_COUNTER_0_FRM_REG This is applied to 32 bits of counter only when the counter is in 32 bit counter mode otherwise this will be applied to only lower 16 bits of counter [2:2] read-write Disable If Write: No effect If Read: Counter_1 is not in periodic mode 0 Enable If Write: Counter_1 will be in periodic mode If Read: Counter_1 is in periodic mode 1 Counter_0_Trig_frm_reg This is a self clear bit in set register. [3:3] read-only COUNTER_0_UP_DOWN This enables the counter to run in up/down/up-down/down-up directions [5:4] read-write 00 If Write:No effect If Read:Counter_0 is in down-up counting mode 0 01 If Write:Counter_0 will be up-counting If Read:Counter_0 is in up-counting mode 1 10 If Write:Counter down direction enable If Read:Counter_0 is in down counting mode 2 11 If Write:Both up and down directions enable. If Read:Counter_0 is in up-down counting mode 3 Counter_0_Sync_Trig This is a self clear bit in set register. [6:6] read-only BUF_REG_0_EN Buffer register gets enabled for MATCH REG. MATCH_BUF_REG is always available and whenever this bit is set only, gets copied to MATCH REG. [7:7] read-write Disable If Write: No effect If Read:Buffer is not enabled and not in path. 0 Enable If Write:Buffer will be enabled and in path If Read:Buffer is enabled and in path 1 RESERVED1 Reserved1 [16:8] read-only Soft_Reset_Counter_1_frm_reg This is a self clear bit in set register. [17:17] read-only PERIODIC_EN_COUNTER_1_FRM_REG This resets the counter on the write [18:18] read-write Disable If Write:No effect If Read:Counter_1 is not in periodic mode 0 Enable If Write:Counter_1 will be in periodic mode If Read:Counter_1 is in periodic mode 1 Counter_1_Trig_frm_reg Self clear bit [19:19] read-only COUNTER_1_UP_DOWN This enables the counter to run in upward direction [21:20] read-write 00 If Write:No effect If Read:Counter_1 is in down-up counting mode 0 01 If Write:Counter_1 will be up-counting If Read:Counter_1 is in up-counting mode 1 10 If Write:Counter down direction enable If Read:Counter_1 is in down counting mode 2 11 If Write:Both up and down directions enable. If Read:Counter_1 is in up-down counting mode 3 Counter_1_sync_trig self clear bit [22:22] read-only BUF_REG_1_EN Buffer register gets enabled for MATCH REG. MATCH_BUF_REG is always available and whenever this bit is set only, gets copied to MATCH REG. [23:23] read-write Disable If Write: No effect If Read:Buffer is not enabled and not in path. 0 Enable If Write:Buffer will be enabled and in path If Read:Buffer is enabled and in path 1 RESERVED2 Reserved2 [31:24] read-only CT_INTR_STS Interrupt status 0x08 32 read-only 0x00000000 INTR_0_L Indicates the FIFO full signal of channel-0 [0:0] read-only FIFO_0_FULL_L Indicates the FIFO full signal of channel-0 [1:1] read-only COUNTER_0_IS_ZERO_L Counter 0 hit zero in active mode. [2:2] read-only COUNTER_0_IS_PEAK_L Counter 0 hit peak (MATCH) in active mode. [3:3] read-only RESERVED1 Reserved1 [15:4] read-only INTR_1_L Indicates the FIFO full signal of channel-1 [16:16] read-only FIFO_1_FULL_L Indicates the FIFO full signal of channel-1 [17:17] read-only COUNTER_1_IS_ZERO_L Counter 1 hit zero in active mode. [18:18] read-only COUNTER_1_IS_PEAK_L Counter 1 hit peak (MATCH) in active mode. [19:19] read-only RESERVED2 Reserved2 [31:20] read-only CT_INTR_MASK Interrupts mask 0x0C 32 read-write 0x00000000 0x0 INTR_0_L Interrupt mask signal. [0:0] read-write Disable If Write: No effect If Read:Interrupt is masked. 0 Enable If Write: Interrupt will be masked. If Read: Interrupt is unmasked. 1 FIFO_0_FULL_L Interrupt mask signal. [1:1] read-write Disable If Write: No effect If Read:Interrupt is masked. 0 Enable If Write: Interrupt will be masked. If Read: Interrupt is unmasked. 1 COUNTER_0_IS_ZERO_L Interrupt mask signal. [2:2] read-write Disable If Write: No effect If Read:Interrupt is masked. 0 Enable If Write: Interrupt will be masked. If Read: Interrupt is unmasked. 1 COUNTER_0_IS_PEAK_L Interrupt mask signal. [3:3] read-write Disable If Write: No effect If Read:Interrupt is masked. 0 Enable If Write: Interrupt will be masked. If Read: Interrupt is unmasked. 1 RESERVED1 Reserved1 [15:4] read-write INTR_1_L Interrupt mask signal. [16:16] read-write Disable If Write: No effect If Read:Interrupt is masked. 0 Enable If Write: Interrupt will be masked. If Read: Interrupt is unmasked. 1 FIFO_1_FULL_L Interrupt mask signal. [17:17] read-write Disable If Write: No effect If Read:Interrupt is masked. 0 Enable If Write: Interrupt will be masked. If Read: Interrupt is unmasked. 1 COUNTER_1_IS_ZERO_L Interrupt mask signal. [18:18] read-write Disable If Write: No effect If Read:Interrupt is masked. 0 Enable If Write: Interrupt will be masked. If Read: Interrupt is unmasked. 1 COUNTER_1_IS_PEAK_L Interrupt mask signal. [19:19] read-write Disable If Write: No effect If Read:Interrupt is masked. 0 Enable If Write: Interrupt will be masked. If Read: Interrupt is unmasked. 1 RESERVED2 Reserved2 [31:20] read-write CT_INTER_UNMASK Interrupts unmask 0x10 32 read-write 0x00000000 0x0 INTR_0_L Interrupt unmask signal. [0:0] read-write Disable If Write: No effect If Read:Interrupt is masked. 0 Enable If Write: Interrupt will be unmasked. If Read: Interrupt is unmasked. 1 FIFO_0_FULL_L Interrupt unmask signal. [1:1] read-write Disable If Write: No effect If Read:Interrupt is masked. 0 Enable If Write: Interrupt will be unmasked. If Read: Interrupt is unmasked. 1 COUNTER_0_IS_ZERO_L Interrupt unmask signal. [2:2] read-write Disable If Write: No effect If Read:Interrupt is masked. 0 Enable If Write: Interrupt will be unmasked. If Read: Interrupt is unmasked. 1 COUNTER_0_IS_PEAK_L Interrupt unmask signal. [3:3] read-write Disable If Write: No effect If Read:Interrupt is masked. 0 Enable If Write: Interrupt will be unmasked. If Read: Interrupt is unmasked. 1 RESERVED1 Reserved1 [15:4] read-only INTR_1_L Interrupt unmask signal. [16:16] read-write Disable If Write: No effect If Read:Interrupt is masked. 0 Enable If Write: Interrupt will be unmasked. If Read: Interrupt is unmasked. 1 FIFO_1_FULL_L Interrupt unmask signal [17:17] read-write Disable If Write: No effect If Read:Interrupt is masked. 0 Enable If Write: Interrupt will be unmasked. If Read: Interrupt is unmasked. 1 COUNTER_1_IS_ZERO_L Interrupt unmask signal. [18:18] read-write Disable If Write: No effect If Read:Interrupt is masked. 0 Enable If Write: Interrupt will be unmasked. If Read: Interrupt is unmasked. 1 COUNTER_1_IS_PEAK_L Interrupt unmask signal. [19:19] read-write Disable If Write: No effect If Read:Interrupt is masked. 0 Enable If Write: Interrupt will be unmasked. If Read: Interrupt is unmasked. 1 RESERVED2 Reserved2 [31:20] read-only CT_INTR_ACK Interrupt clear/ack register 0x14 32 read-write 0x00000000 0x0 INTR_0_L Interrupt ack signal. [0:0] read-write Disable If Write: No effect. If Read: should be returned as this is self clear bit 0 Enable If Write: Interrupt will be de asserted. 1 FIFO_0_FULL_L Interrupt ack signal. [1:1] read-write Disable If Write: No effect. If Read: should be returned as this is self clear bit 0 Enable If Write: Interrupt will be de asserted. 1 COUNTER_0_IS_ZERO_L Interrupt ack signal. [2:2] read-write Disable If Write: No effect. If Read: should be returned as this is self clear bit 0 Enable If Write: Interrupt will be de asserted. 1 COUNTER_0_IS_PEAK_L Interrupt ack signal. [3:3] read-write Disable If Write: No effect. If Read: should be returned as this is self clear bit 0 Enable If Write: Interrupt will be de asserted. 1 RESERVED1 Reserved1 [15:4] read-only INTR_1_L Interrupt ack signal. [16:16] read-write Disable If Write: No effect. If Read: should be returned as this is self clear bit 0 Enable If Write: Interrupt will be de asserted. 1 FIFO_1_FULL_L Interrupt ack signal. [17:17] read-write Disable If Write: No effect. If Read: should be returned as this is self clear bit 0 Enable If Write: Interrupt will be de asserted. 1 COUNTER_1_IS_ZERO_L Interrupt ack signal. [18:18] read-write Disable If Write: No effect. If Read: should be returned as this is self clear bit 0 Enable If Write: Interrupt will be de asserted. 1 COUNTER_1_IS_PEAK_L Interrupt ack signal. [19:19] read-write Disable If Write: No effect. If Read: should be returned as this is self clear bit 0 Enable If Write: Interrupt will be de asserted. 1 RESERVED2 Reserved2 [31:20] read-write CT_MATCH_REG Match value register 0x18 32 read-write 0xFFFFFFFF 0xFFFFFFFF COUNTER_0_MATCH This will be used as lower match [15:0] read-write COUNTER_1_MATCH This will be used as upper match [31:16] read-write CT_MATCH_BUF_REG Match Buffer register 0x1C 32 read-write 0xFFFFFFFF 0xFFFFFFFF COUNTER_0_MATCH_BUF This gets copied to MATCH register if bug_reg_0_en is set. Copying is done when counter 0 is active and hits 0. [15:0] read-write COUNTER_1_MATCH_BUF This gets copied to MATCH register if bug_reg_1_en is set. Copying is done when counter 1 is active and hits 0. [31:16] read-write CT_CAPTURE_REG Capture Register 0x20 32 read-only 0x00000000 COUNTER_0_CAPTURE This is a latched value of counter lower part when the selected capture_event occurs [15:0] read-only COUNTER_1_CAPTURE This is a latched value of counter upper part when the selected capture_event occurs [31:16] read-only CT_COUNTER_REG Counter Register 0x24 32 read-write 0x00000000 COUNTER0 This holds the value of counter-0 [15:0] read-only COUNTER1 This holds the value of counter-1 [31:16] read-only CT_OCU_CTRL_REG OCU control register 0x28 32 read-write 0x00000000 0x7FFFFF OUTPUT_IS_OCU_0 Indicates whether the output is in OCU mode or not for channel-0 [0:0] read-write SYNC_WITH_0 Indicates whether the other channel is in sync with this channel [3:1] read-write OCU_0_DMA_MODE Indicates whether the OCU DMA mode is active or not for channel 0 [4:4] read-write OCU_0_MODE_8_16 Indicates whether entire 16 bits or only 8-bits of the channel 0 are used in OCU mode [5:5] read-write MAKE_OUTPUT_0_HIGH_SEL Check counter ocus for possibilities. When this is hit output will be made high. [8:6] read-write MAKE_OUTPUT_0_LOW_SEL Check counter ocus for possibilities. When this is hit output will be made low. [11:9] read-write RESERVED1 Reserved1 [15:12] read-write OUTPUT_1_IS_OCU Indicates whether the output is in OCU mode or not for channel 1 [16:16] read-write SYNC_WITH_1 Indicates whether the other channel is in sync with this channel [19:17] read-write OCU_1_DMA_MODE Indicates whether the OCU DMA mode is active or not for channel 1 [20:20] read-write OCU_1_MODE_8_16_MODE Indicates whether entire 16 bits or only 8-bits of the channel 1 are used in OCU mode [21:21] read-write MAKE_OUTPUT_1_HIGH_SEL Check counter ocus for possibilities. When this is hit output will be made high. [24:22] read-write MAKE_OUTPUT_1_LOW_SEL Check counter ocus for possibilities. When this is hit output will be made low. [27:25] read-write RESERVED2 Reserved2 [31:28] read-write CT_OCU_COMPARE_REG OCU Compare Register 0x2C 32 read-write 0x00000000 0xFFFF OCU_COMPARE_0_REG Holds the threshold value of present OCU period which denotes the number of clock cycles for which the OCU output should be considered (counter 0) [15:0] read-write OCU_COMPARE_1_REG Holds the threshold value of present OCU period which denotes the number of clock cycles for which the OCU output should be considered (counter 1) [31:16] read-write CT_OCU_COMPARE2_REG OCU Compare2 Register 0x30 32 read-write 0x00000000 0xFFFF OCU_COMPARE2_0_REG Holds the threshold value of present OCU period2 which denotes the number of clock cycles for which the OCU output should be considered (counter 0) [15:0] read-write OCU_COMPARE2_1_REG Holds the threshold value of present OCU period2 which denotes the number of clock cycles for which the OCU output should be considered (counter 1) [31:16] read-write CT_OCU_SYNC_REG OCU Synchronization Register 0x34 32 read-write 0x00000000 0xFFFFFFFF OCU_SYNC_REG_0 Starting point of channel 0 for synchronization purpose [15:0] read-write OCU_SYNC_REG_1 Starting point of channel 1 for synchronization purpose [31:16] read-write CT_OCU_COMPARE_NXT_REG PWM compare next register 0x38 32 read-write 0x00000000 0xFFFFFFFF OCU_COMPARE_NXT_COUNTER1 OCU output should be high for counter 1 [15:0] read-write OCU_COMPARE_NXT_COUNTER0 PWM output should be high for counter 0 [31:16] read-write CT_OCU_COMPARE2_NXT_REG PWM compare next register 0x40 32 read-write 0x00000000 0xFFFFFFFF OCU_COMPARE2_NXT_COUNTER0 OCU output should be high for counter 1 [15:0] read-write OCU_COMPARE2_NXT_COUNTER1 PWM output should be high for counter 0 [31:16] read-write CT_WFG_CTRL_REG WFG control register 0x3C 32 read-write 0x00000000 0x7FFFFF MAKE_OUTPUT_0_TGL_0_SEL Check the counter ocus possibilities for description for channel 0. [2:0] read-write MAKE_OUTPUT_0_TGL_1_SEL Check the counter ocus possibilities for description for channel 0. [5:3] read-write RESERVED1 Reserved1 [7:6] read-write WFG_TGL_CNT_0_PEAK WFG mode output toggle count clock for channel 0. [15:8] read-write MAKE_OUTPUT_1_TGL_0_SEL Check the counter ocus possibilities for description for channel 1. [18:16] read-write MAKE_OUTPUT_1_TGL_1_SEL Check the counter ocus possibilities for description for channel 1. [21:19] read-write RESERVED2 Reserved2 [23:22] read-write WFG_TGL_CNT_1_PEAK WFG mode output toggle count clock for channel 1 [31:24] read-write CT_START_COUNTER_EVENT_SEL Start counter event select register 0x50 32 read-write 0x00000000 0x3F003F START_COUNTER_0_EVENT_SEL For two 16 bit counters mode: Event select for starting the Counter 0 For 32 bit counter mode: Event select for starting counter [5:0] read-write RESERVED1 Reserved1 [15:6] read-write START_COUNTER_1_EVENT_SEL For two 16 bit counters mode: Event select for starting the Counter 1. For 32 bit counter mode: Invalid. Please refer to events table for description [21:16] read-write RESERVED2 Reserved2 [31:22] read-only CT_START_COUNTER_AND_EVENT Start counter AND event register 0x54 32 read-write 0x00000000 0XF000F START_COUNTER_0_AND_EVENT For two 16 bit counter mode: AND expression valids for AND event in start Counter 0 event For 32 bit counter mode AND expression valids for AND event in start counter event [3:0] read-write RESERVED1 Reserved1 [7:4] read-write START_COUNTER_0_AND_VLD none [11:8] read-write RESERVED2 Reserved2 [15:12] read-only START_COUNTER_1_AND_EVENT For two 16 bit counters mode: AND expression valids for AND event in start counter event For 32 bit counter mode : Invalid [19:16] read-write RESERVED3 Reserved3 [23:20] read-only START_COUNTER_1_AND_VLD none [27:24] read-write RESERVED4 Reserved4 [31:28] read-only CT_START_COUNTER_OR_EVENT Start counter OR event register 0x58 32 read-write 0x00000000 0XF000F START_COUNTER_0_OR_EVENT For two 16 bit counter mode: OR expression valids for OR event in start Counter 0 event For 32 bit counter mode OR expression valids for OR event in start counter event [3:0] read-write RESERVED1 Reserved1 [7:4] read-write START_COUNTER_0_OR_VLD none [11:8] read-write RESERVED2 Reserved2 [15:12] read-write START_COUNTER_1_OR_EVENT For two 16 bit counters mode: OR expression valids for OR event in start counter event For 32 bit counter mode : Invalid. [19:16] read-write RESERVED3 Reserved3 [23:20] read-only START_COUNTER_1_OR_VLD none [27:24] read-write RESERVED4 Reserved4 [31:28] read-only CT_CONTINUE_COUNTER_EVENT_SEL Continue counter event select register 0x5C 32 read-write 0x00000000 0X3F003F CONTINUE_COUNTER_0_EVENT_SEL For two 16 bit counters mode: Event select for continuing the Counter 0 For 32 bit counter mode: Event select for continuing counter [5:0] read-write RESERVED1 Reserved1 [15:6] read-write CONTINUE_COUNTER_1_EVENT_SEL For two 16 bit counters mode: Event select for continuing the Counter 1 For 32 bit counter mode: Invalid. [21:16] read-write RESERVED2 Reserved2 [31:22] read-only CT_CONTINUE_COUNTER_AND_EVENT Continue counter AND event register 0x60 32 read-write 0x00000000 0XF000F CONTINUE_COUNTER_0_AND_EVENT For two 16 bit counter mode: AND expression valids for AND event in continue Counter 0 event For 32 bit counter mode AND expression valids for AND event in continue counter event. [3:0] read-write RESERVED1 Reserved1 [7:4] read-write CONTINUE_COUNTER_0_AND_VLD none [11:8] read-write RESERVED2 Reserved2 [15:12] read-write CONTINUE_COUNTER_1_AND_EVENT For two 16 bit counters mode: AND expression valids for AND event in continue counter event For 32 bit counter mode : Invalid [19:16] read-write RESERVED3 Reserved3 [23:20] read-only CONTINUE_COUNTER_1_AND_VLD none [27:24] read-write RESERVED4 Reserved4 [31:28] read-only CT_CONTINUE_COUNTER_OR_EVENT Continue counter OR event register 0x64 32 read-write 0x00000000 0XF000F CONTINUE_COUNTER_0_OR_EVENT For two 16 bit counter mode: OR expression valids for OR event in continue Counter 0 event For 32 bit counter mode OR expression valids for OR event in continue counter event [3:0] read-write RESERVED1 Reserved1 [7:4] read-write CONTINUE_COUNTER_0_OR_VLD none [11:8] read-write RESERVED2 Reserved2 [15:12] read-write CONTINUE_COUNTER_1_OR_EVENT For two 16 bit counters mode: OR expression valids for OR event in continue counter event For 32 bit counter mode : Invalid [19:16] read-write RESERVED3 Reserved3 [23:20] read-only CONTINUE_COUNTER_1_OR_VLD none [27:24] read-write RESERVED4 Reserved4 [31:28] read-only CT_STOP_COUNTER_EVENT_SEL Stop counter event select register 0x68 32 read-write 0x00000000 0X3F003F STOP_COUNTER_0_EVENT_SEL For two 16 bit counters mode: Event select for Stopping the Counter 0 For 32 bit counter mode: Event select for Stopping counter [5:0] read-write RESERVED1 Reserved1 [15:6] read-write STOP_COUNTER_1_EVENT_SEL For two 16 bit counters mode: Event select for Stopping the Counter 1 For 32 bit counter mode: Invalid [21:16] read-write RESERVED2 Reserved2 [31:22] read-only CT_STOP_COUNTER_AND_EVENT Stop counter AND event register 0x6C 32 read-write 0x00000000 0XF000F STOP_COUNTER_0_AND_EVENT For two 16 bit counter mode: AND expression valids for AND event in stop Counter 0 event For 32 bit counter mode AND expression valids for AND event in stop counter event [3:0] read-write RESERVED1 Reserved1 [7:4] read-write STOP_COUNTER_0_AND_VLD Indicates which bits in [3:0] are valid for considering AND event [11:8] read-write RESERVED2 Reserved2 [15:12] read-write STOP_COUNTER_1_AND_EVENT For two 16 bit counters mode: AND expression valids for AND event in stop counter event For 32 bit counter mode : Invalid [19:16] read-write RESERVED3 Reserved3 [23:20] read-only STOP_COUNTER_1_AND_VLD none [27:24] read-write RESERVED4 Reserved4 [31:28] read-only CT_STOP_COUNTER_OR_EVENT Stop counter OR event register 0x70 32 read-write 0x00000000 0XF000F STOP_COUNTER_0_OR_EVENT For two 16 bit counter mode: OR expression valids for OR event in Stop Counter 0 event For 32 bit counter mode OR expression valids for OR event in Stop counter event [3:0] read-write RESERVED1 Reserved1 [7:4] read-write STOP_COUNTER_0_OR_VLD none [11:8] read-write RESERVED2 Reserved2 [15:12] read-write STOP_COUNTER_1_OR_EVENT For two 16 bit counters mode: OR expression valids for OR event in Stop counter event For 32 bit counter mode : Invalid [19:16] read-write RESERVED3 Reserved3 [23:20] read-only STOP_COUNTER_1_OR_VLD none [27:24] read-write RESERVED4 Reserved4 [31:28] read-only CT_HALT_COUNTER_EVENT_SEL Halt counter event select register 0x74 32 read-write 0x00000000 0X3F003F HALT_COUNTER_0_EVENT_SEL For two 16 bit counters mode: Event select for Halting the Counter 0 For 32 bit counter mode: Event select for Halting counter [5:0] read-write RESUME_FROM_HALT_COUNTER_0 For two 16 bit counters mode: Event select for Halting the Counter 0 For 32 bit counter mode: Event select for Halting counter [6:6] write-only RESERVED1 Reserved1 [15:7] read-only HALT_COUNTER_1_EVENT_SEL For two 16 bit counters mode: Event select for Halting the Counter 1 For 32 bit counter mode: Invalid [21:16] read-write RESUME_FROM_HALT_COUNTER_1 For two 16 bit counters mode: Event select for Halting the Counter 0 For 32 bit counter mode: Event select for Halting counter [22:22] write-only RESERVED2 Reserved2 [31:23] read-only CT_HALT_COUNTER_AND_EVENT Halt counter AND event register 0x78 32 read-write 0x00000000 0XF000F HALT_COUNTER_0_AND_EVENT For two 16 bit counter mode: AND expression valids for AND event in stop Counter 0 event For 32 bit counter mode AND expression valids for AND event in stop counter event [3:0] read-write RESERVED1 Reserved1 [7:4] read-write HALT_COUNTER_0_AND_VLD Indicates which bits in [3:0] are valid for considering AND event [11:8] read-write RESERVED2 Reserved2 [15:12] read-only HALT_COUNTER_1_AND_EVENT For two 16 bit counters mode: AND expression valids for AND event in stop counter event For 32 bit counter mode : Invalid [19:16] read-write RESERVED3 Reserved3 [23:20] read-only HALT_COUNTER_1_AND_VLD none [27:24] read-write RESERVED4 Reserved4 [31:28] read-only CT_HALT_COUNTER_OR_EVENT Halt counter OR event register 0x7C 32 read-write 0x00000000 0XF000F HALT_COUNTER_0_OR_EVENT For two 16 bit counter mode: OR expression valids for OR event in Halt Counter 0 event For 32 bit counter mode OR expression valids for OR event in Halt counter event [3:0] read-write RESERVED1 Reserved1 [7:4] read-write HALT_COUNTER_0_OR_VLD none [11:8] read-write RESERVED2 Reserved2 [15:12] read-only HALT_COUNTER_1_OR_EVENT For two 16 bit counters mode: OR expression valids for OR event in Halt counter event For 32 bit counter mode : Invalid [19:16] read-write RESERVED3 Reserved3 [23:20] read-only HALT_COUNTER_1_OR_VLD none [27:24] read-write RESERVED4 Reserved4 [31:28] read-only CT_INCREMENT_COUNTER_EVENT_SEL Increment counter event select register 0x80 32 read-write 0x00000000 0X3F003F INCREMENT_COUNTER_0_EVENT_SEL For two 16 bit counters mode: Event select for Incrementing the Counter 0 For 32 bit counter mode: Event select for Incrementing counter [5:0] read-write RESERVED1 Reserved1 [15:6] read-only INCREMENT_COUNTER_1_EVENT_SEL For two 16 bit counters mode: Event select for Incrementing the Counter 1 For 32 bit counter mode: Invalid [21:16] read-write RESERVED2 Reserved2 [31:22] read-only CT_INCREMENT_COUNTER_AND_EVENT Increment counter AND event register 0x84 32 read-write 0x00000000 0XF000F INCREMENT_COUNTER_0_AND_EVENT For two 16 bit counter mode: AND expression valids for AND event in stop Counter 0 event For 32 bit counter mode AND expression valids for AND event in stop counter event [3:0] read-write RESERVED1 Reserved1 [7:4] read-write INCREMENT_COUNTER_0_AND_VLD none [11:8] read-write RESERVED2 Reserved2 [15:12] read-only INCREMENT_COUNTER_1_AND_EVENT For two 16 bit counters mode: AND expression valids for AND event in stop counter event For 32 bit counter mode : Invalid [19:16] read-write RESERVED3 Reserved3 [23:20] read-only INCREMENT_COUNTER_1_AND_VLD none [27:24] read-write RESERVED4 Reserved4 [31:28] read-only CT_INCREMENT_COUNTER_OR_EVENT Increment counter OR event register 0x88 32 read-write 0x00000000 0XF000F INCREMENT_COUNTER_0_OR_EVENT For two 16 bit counter mode: OR expression valids for OR event in Increment Counter 0 event For 32 bit counter mode OR expression valids for OR event in Increment counter event [3:0] read-write RESERVED1 Reserved1 [7:4] read-write INCREMENT_COUNTER_0_OR_VLD none [11:8] read-write RESERVED2 Reserved2 [15:12] read-only INCREMENT_COUNTER_1_OR_EVENT For two 16 bit counters mode: OR expression valids for OR event in Increment counter event For 32 bit counter mode : Invalid [19:16] read-write RESERVED4 Reserved4 [23:20] read-only INCREMENT_COUNTER_1_OR_VLD none [27:24] read-write RESERVED5 Reserved5 [31:28] read-only CT_CAPTURE_COUNTER_EVENT_SEL Capture counter event select register 0x8C 32 read-write 0x00000000 0X3F003F CAPTURE_COUNTER_0_EVENT_SEL For two 16 bit counters mode: Event select for Capturing the Counter 0 For 32 bit counter mode: Event select for Capturing counter [5:0] read-write RESERVED1 Reserved1 [15:6] read-only CAPTURE_COUNTER_1_EVENT_SEL For two 16 bit counters mode: Event select for Capturing the Counter 1 For 32 bit counter mode : Invalid [21:16] read-write RESERVED2 Reserved2 [31:22] read-only CT_CAPTURE_COUNTER_AND_EVENT Capture counter AND event register 0x90 32 read-write 0x00000000 0XF000F CAPTURE_COUNTER_0_AND_EVENT For two 16 bit counter mode: AND expression valids for AND event in stop Counter 0 event For 32 bit counter mode AND expression valids for AND event in stop counter event [3:0] read-write RESERVED1 Reserved1 [7:4] read-write CAPTURE_COUNTER_0_AND_VLD none [11:8] read-write RESERVED2 Reserved2 [15:12] read-only CAPTURE_COUNTER_1_AND_EVENT For two 16 bit counters mode: AND expression valids for AND event in stop counter event For 32 bit counter mode : Invalid [19:16] read-write RESERVED3 Reserved3 [23:20] read-only CAPTURE_COUNTER_1_AND_VLD none [27:24] read-write RESERVED4 Reserved4 [31:28] read-only CT_CAPTURE_COUNTER_OR_EVENT Capture counter OR event register 0x94 32 read-write 0x00000000 0XF000F CAPTURE_COUNTER_0_OR_EVENT For two 16 bit counter mode: OR expression valids for OR event in Capture Counter 0 event For 32 bit counter mode OR expression valids for OR event in Capture counter event [3:0] read-write RESERVED1 Reserved1 [7:4] read-write CAPTURE_COUNTER_0_OR_VLD none [11:8] read-write RESERVED2 Reserved2 [15:12] read-only CAPTURE_COUNTER_1_OR_EVENT For two 16 bit counters mode: OR expression valids for OR event in Capture counter event For 32 bit counter mode : Invalid [19:16] read-write RESERVED3 Reserved3 [23:20] read-only CAPTURE_COUNTER_1_OR_VLD none [27:24] read-write RESERVED4 Reserved4 [31:28] read-only CT_OUTPUT_EVENT_SEL Output event select register 0x98 32 read-write 0x00000000 0X3F003F OUTPUT_EVENT_SEL_0 For two 16 bit counters mode: Event select for output event from Counter 0 For 32 bit counter mode: Event select for output event [5:0] read-write RESERVED1 Reserved1 [15:6] read-only OUTPUT_EVENT_SEL_1 For two 16 bit counters mode: Event select for output event from counter 1 For 32 bit counter mode : Invalid [21:16] read-write RESERVED2 Reserved2 [31:22] read-only CT_OUTPUT_AND_EVENT_REG Output AND event Register 0x9C 32 read-write 0x00000000 0xFFFFFFFF OUTPUT_0_AND_EVENT AND expression for AND event in output Counter_0 event. [3:0] read-write RESERVED1 Reserved1 [7:4] read-write OUTPUT_0_AND_VLD AND expression for AND event in output Counter_0 event. [11:8] read-write RESERVED2 Reserved2 [15:12] read-only OUTPUT_1_AND_EVENT AND expression for AND event in output Counter_1 event. [19:16] read-write RESERVED3 Reserved3 [23:20] read-only OUTPUT_1_AND_VLD AND expression for AND event in output Counter_1 event. [27:24] read-write RESERVED4 Reserved4 [31:28] read-only CT_OUTPUT_OR_EVENT Output OR event Register 0xA0 32 read-write 0x00000000 0xFFFFFFFF OUTPUT_0_OR_EVENT OR expression for OR event in output Counter_0 event [3:0] read-write RESERVED1 Reserved1 [7:4] read-write OUTPUT_0_OR_VLD Indicates which bits in [3:0] are valid for considering OR event [11:8] read-write RESERVED2 Reserved2 [15:12] read-only OUTPUT_1_OR_EVENT OR expression for OR event in output Counter_0 event [19:16] read-write RESERVED3 Reserved3 [23:20] read-only OUTPUT_1_OR_VLD Indicates which bits in [3:0] are valid for considering OR event [27:24] read-write RESERVED4 Reserved4 [31:28] read-only CT_INTR_EVENT_SEL Interrupt Event Select Register 0xA4 32 read-write 0x00000000 0X3F003F INTR_EVENT_SEL_0 For two 16 bit counters mode: Event select for interrupt event from Counter 0 For 32 bit counter mode: Event select for output event [5:0] read-write RESERVED1 Reserved1 [15:6] read-only INTR_EVENT_SEL_1 For two 16 bit counters mode: Event select for interrupt event from counter 1 For 32 bit counter mode : Invalid [21:16] read-write RESERVED2 Reserved2 [31:22] read-only CT_INTR_AND_EVENT Interrupt AND Event Register 0xA8 32 read-write 0x00000000 0X3F003F INTR_0_AND_EVENT None [3:0] read-write RESERVED1 Reserved1 [7:4] read-write INTR_0_AND_VLD None [11:8] read-write RESERVED2 Reserved2 [15:12] read-only INTR_1_AND_EVENT None [19:16] read-write RESERVED3 Reserved3 [23:20] read-only INTR_1_AND_VLD None [27:24] read-write RESERVED4 Reserved4 [31:28] read-only CT_INTR_OR_EVENT_REG Interrupt OR Event Register 0xAC 32 read-write 0x00000000 0X3F003F INTR_0_OR_EVENT None [3:0] read-write RESERVED1 Reserved1 [7:4] read-write INTR_0_OR_VLD None [11:8] read-write RESERVED2 Reserved2 [15:12] read-only INTR_1_OR_EVENT None [19:16] read-write RESERVED3 Reserved3 [23:20] read-only INTR_1_OR_VLD None [27:24] read-write RESERVED4 Reserved4 [31:28] read-only CT_RE_FE_RFE_LEV0_LEV1_EVENT_ENABLE_REG Rising Edge Falling Edge Rising and Falling Edge level0 level1 event enable register 0xB0 32 read-write 0x000FFFFF 0X000FFFFF Input_Event_RE_Enable Input event rising edge enables [3:0] read-write Input_Event_FE_Enable Input event falling edge enables: [7:4] read-write Input_Event_RFE_Enable Input event rising and falling edge enables [11:8] read-write Input_Event_lev0_Enable Input event level0 enables [15:12] read-write Input_Event_lev1_Enable Input event level1 enables [19:16] read-write RESERVED Reserved [31:20] read-only CT2 1.0 Configurable timer is used in counting clocks, events and states with reference clock external clock and system clock CT 0x45061000 32 read-write 0 0xB0 registers CT 34 CT_GEN_CTRL_SET_REG General control set register 0x00 32 read-write 0x00000000 0xFFFFFFFF COUNTER_IN_32_BIT_MODE Counter_1 and Counter_0 will be merged and used as a single 32 bit counter [0:0] read-write Disable If Write: Counter will be 32 bit mode If Read: Counter is in two 16 bit mode 0 Enable If Write: Counter will be 32 bit mode If Read: Counter is in two 16 bit mode 1 SOFT_RESET_COUNTER_0_FRM_REG This is applied to 32 bits of counter only when the counter is in 32 bit counter mode otherwise this will be applied to only lower 16 bits of counter [1:1] read-write Disable If Write: No effect If Read: Always should return 0 0 Enable If Write: Counter_1 will be reset If Read: Always should return 0 1 PERIODIC_EN_COUNTER_0_FRM_REG This is applied to 32 bits of counter only when the counter is in 32 bit counter mode otherwise this will be applied to only lower 16 bits of counter [2:2] read-write Disable If Write: No effect If Read: Counter_1 is not in periodic mode 0 Enable If Write: Counter_1 will be in periodic mode If Read: Counter_1 is in periodic mode 1 COUNTER_0_TRIG_FRM_REG This enables the counter to run/active [3:3] read-write Disable If Write: No effect If Read:Read should always return 0 0 Enable If Write:Counter_1 will be active If Read:Read should always return 0 1 COUNTER_0_UP_DOWN This enables the counter to run in up/down/up-down/down-up directions [5:4] read-write 00 If Write:No effect If Read:Counter_0 is in down-up counting mode 0 01 If Write:Counter_0 will be up-counting If Read:Counter_0 is in up-counting mode 1 10 If Write:Counter down direction enable If Read:Counter_0 is in down counting mode 2 11 If Write:Both up and down directions enable. If Read:Counter_0 is in up-down counting mode 3 COUNTER_0_SYNC_TRIG This is applied to 32 bits of counter only when the counter is in 32 bit counter mode otherwise this will be applied to only lower 16 bits of counter. This enables the counter to run/active when sync is found. [6:6] read-write Disable If Write: No effect If Read:Read should always return 0 0 Enable If Write:Counter_0 will be active. If Read:Read should always return 0 1 BUF_REG_0_EN Buffer register gets enabled for MATCH REG. MATCH_BUF_REG is always available and whenever this bit is set only, gets copied to MATCH REG. [7:7] read-write Disable If Write: No effect If Read:Buffer is not enabled and not in path. 0 Enable If Write:Buffer will be enabled and in path If Read:Buffer is enabled and in path 1 RESERVED1 Reserved1 [16:8] read-write SOFT_RESET_COUNTER_1_FRM_REG This resets the counter on the write [17:17] read-write Disable If Write:No effect If Read:Always should return 0 0 Enable If Write:Counter_1 will be reset If Read:Always should return 0 1 PERIODIC_EN_COUNTER_1_FRM_REG This resets the counter on the write [18:18] read-write Disable If Write:No effect If Read:Counter_1 is not in periodic mode 0 Enable If Write:Counter_1 will be in periodic mode If Read:Counter_1 is in periodic mode 1 COUNTER_1_TRIG_FRM This enables the counter to run/active [19:19] read-write Disable If Write:No effect If Read:Always should return 0 0 Enable If Write:Counter_1 will be active If Read:Always should return 0 1 COUNTER_1_UP_DOWN This enables the counter to run in upward direction [21:20] read-write 00 If Write:No effect If Read:Counter_1 is in down-up counting mode 0 01 If Write:Counter_1 will be up-counting If Read:Counter_1 is in up-counting mode 1 10 If Write:Counter down direction enable If Read:Counter_1 is in down counting mode 2 11 If Write:Both up and down directions enable. If Read:Counter_1 is in up-down counting mode 3 COUNTER_1_SYNC_TRIG This is applied to 32 bits of counter only when the counter is in 32 bit counter mode otherwise this will be applied to only lower 16 bits of counter. This enables the counter to run/active when sync is found. [22:22] read-write Disable If Write: No effect If Read:Read should always return 0 0 Enable If Write:Counter_1 will be active. If Read:Read should always return 0 1 BUF_REG_1_EN Buffer register gets enabled for MATCH REG. MATCH_BUF_REG is always available and whenever this bit is set only, gets copied to MATCH REG. [23:23] read-write Disable If Write: No effect If Read:Buffer is not enabled and not in path. 0 Enable If Write:Buffer will be enabled and in path If Read:Buffer is enabled and in path 1 RESERVED2 Reserved2 [31:24] read-write CT_GEN_CTRL_RESET_REG General control reset register 0x04 32 read-write 0x00000000 0xFFFFFFFF COUNTER_IN_32_BIT_MODE Counter_1 and Counter_0 will be merged and used as a single 32 bit counter [0:0] read-write Disable If Write: Counter will be 32 bit mode If Read: Counter is in two 16 bit mode 0 Enable If Write: Counter will be 32 bit mode If Read: Counter is in two 16 bit mode 1 RESERVED1 Reserved1 [1:1] read-only PERIODIC_EN_COUNTER_0_FRM_REG This is applied to 32 bits of counter only when the counter is in 32 bit counter mode otherwise this will be applied to only lower 16 bits of counter [2:2] read-write Disable If Write: No effect If Read: Counter_1 is not in periodic mode 0 Enable If Write: Counter_1 will be in periodic mode If Read: Counter_1 is in periodic mode 1 RESERVED2 Reserved2 [3:3] read-only COUNTER_0_UP_DOWN This enables the counter to run in up/down/up-down/down-up directions [5:4] read-write 00 If Write:No effect If Read:Counter_0 is in down-up counting mode 0 01 If Write:Counter_0 will be up-counting If Read:Counter_0 is in up-counting mode 1 10 If Write:Counter down direction enable If Read:Counter_0 is in down counting mode 2 11 If Write:Both up and down directions enable. If Read:Counter_0 is in up-down counting mode 3 RESERVED3 Reserved3 [6:6] read-only BUF_REG_0_EN Buffer register gets enabled for MATCH REG. MATCH_BUF_REG is always available and whenever this bit is set only, gets copied to MATCH REG. [7:7] read-write Disable If Write: No effect If Read:Buffer is not enabled and not in path. 0 Enable If Write:Buffer will be enabled and in path If Read:Buffer is enabled and in path 1 RESERVED4 Reserved4 [16:8] read-only RESERVED5 Reserved5 [17:17] read-only PERIODIC_EN_COUNTER_1_FRM_REG This resets the counter on the write [18:18] read-write Disable If Write:No effect If Read:Counter_1 is not in periodic mode 0 Enable If Write:Counter_1 will be in periodic mode If Read:Counter_1 is in periodic mode 1 RESERVED6 Reserved6 [19:19] read-only COUNTER_1_UP_DOWN This enables the counter to run in upward direction [21:20] read-write 00 If Write:No effect If Read:Counter_1 is in down-up counting mode 0 01 If Write:Counter_1 will be up-counting If Read:Counter_1 is in up-counting mode 1 10 If Write:Counter down direction enable If Read:Counter_1 is in down counting mode 2 11 If Write:Both up and down directions enable. If Read:Counter_1 is in up-down counting mode 3 RESERVED7 Reserved7 [22:22] read-only BUF_REG_1_EN Buffer register gets enabled for MATCH REG. MATCH_BUF_REG is always available and whenever this bit is set only, gets copied to MATCH REG. [23:23] read-write Disable If Write: No effect If Read:Buffer is not enabled and not in path. 0 Enable If Write:Buffer will be enabled and in path If Read:Buffer is enabled and in path 1 RESERVED8 Reserved8 [31:24] read-only CT_INTR_STS Interrupt status 0x08 32 read-only 0x00000000 INTR_0_L Indicates the FIFO full signal of channel-0 [0:0] read-only FIFO_0_FULL_L Indicates the FIFO full signal of channel-0 [1:1] read-only COUNTER_0_IS_ZERO_L Counter 0 hit zero in active mode. [2:2] read-only COUNTER_0_IS_PEAK_L Counter 0 hit peak (MATCH) in active mode. [3:3] read-only RESERVED1 Reserved1 [15:4] read-only INTR_1_L Indicates the FIFO full signal of channel-1 [16:16] read-only FIFO_1_FULL_L Indicates the FIFO full signal of channel-1 [17:17] read-only COUNTER_1_IS_ZERO_L Counter 1 hit zero in active mode. [18:18] read-only COUNTER_1_IS_PEAK_L Counter 1 hit peak (MATCH) in active mode. [19:19] read-only RESERVED2 Reserved2 [31:20] read-only CT_INTR_MASK Interrupts mask 0x0C 32 read-write 0x00000000 0x0 INTR_0_L Interrupt mask signal. [0:0] read-write Disable If Write: No effect If Read:Interrupt is masked. 0 Enable If Write: Interrupt will be masked. If Read: Interrupt is unmasked. 1 FIFO_0_FULL_L Interrupt mask signal. [1:1] read-write Disable If Write: No effect If Read:Interrupt is masked. 0 Enable If Write: Interrupt will be masked. If Read: Interrupt is unmasked. 1 COUNTER_0_IS_ZERO_L Interrupt mask signal. [2:2] read-write Disable If Write: No effect If Read:Interrupt is masked. 0 Enable If Write: Interrupt will be masked. If Read: Interrupt is unmasked. 1 COUNTER_0_IS_PEAK_L Interrupt mask signal. [3:3] read-write Disable If Write: No effect If Read:Interrupt is masked. 0 Enable If Write: Interrupt will be masked. If Read: Interrupt is unmasked. 1 RESERVED1 Reserved1 [15:4] read-write INTR_1_L Interrupt mask signal. [16:16] read-write Disable If Write: No effect If Read:Interrupt is masked. 0 Enable If Write: Interrupt will be masked. If Read: Interrupt is unmasked. 1 FIFO_1_FULL_L Interrupt mask signal. [17:17] read-write Disable If Write: No effect If Read:Interrupt is masked. 0 Enable If Write: Interrupt will be masked. If Read: Interrupt is unmasked. 1 COUNTER_1_IS_ZERO_L Interrupt mask signal. [18:18] read-write Disable If Write: No effect If Read:Interrupt is masked. 0 Enable If Write: Interrupt will be masked. If Read: Interrupt is unmasked. 1 COUNTER_1_IS_PEAK_L Interrupt mask signal. [19:19] read-write Disable If Write: No effect If Read:Interrupt is masked. 0 Enable If Write: Interrupt will be masked. If Read: Interrupt is unmasked. 1 RESERVED2 Reserved2 [31:20] read-write CT_INTER_UNMASK Interrupts unmask 0x10 32 read-write 0x00000000 0x0 INTR_0_L Interrupt unmask signal. [0:0] read-write Disable If Write: No effect If Read:Interrupt is masked. 0 Enable If Write: Interrupt will be unmasked. If Read: Interrupt is unmasked. 1 FIFO_0_FULL_L Interrupt unmask signal. [1:1] read-write Disable If Write: No effect If Read:Interrupt is masked. 0 Enable If Write: Interrupt will be unmasked. If Read: Interrupt is unmasked. 1 COUNTER_0_IS_ZERO_L Interrupt unmask signal. [2:2] read-write Disable If Write: No effect If Read:Interrupt is masked. 0 Enable If Write: Interrupt will be unmasked. If Read: Interrupt is unmasked. 1 COUNTER_0_IS_PEAK_L Interrupt unmask signal. [3:3] read-write Disable If Write: No effect If Read:Interrupt is masked. 0 Enable If Write: Interrupt will be unmasked. If Read: Interrupt is unmasked. 1 RESERVED1 Reserved1 [15:4] read-only INTR_1_L Interrupt unmask signal. [16:16] read-write Disable If Write: No effect If Read:Interrupt is masked. 0 Enable If Write: Interrupt will be unmasked. If Read: Interrupt is unmasked. 1 FIFO_1_FULL_L Interrupt unmask signal [17:17] read-write Disable If Write: No effect If Read:Interrupt is masked. 0 Enable If Write: Interrupt will be unmasked. If Read: Interrupt is unmasked. 1 COUNTER_1_IS_ZERO_L Interrupt unmask signal. [18:18] read-write Disable If Write: No effect If Read:Interrupt is masked. 0 Enable If Write: Interrupt will be unmasked. If Read: Interrupt is unmasked. 1 COUNTER_1_IS_PEAK_L Interrupt unmask signal. [19:19] read-write Disable If Write: No effect If Read:Interrupt is masked. 0 Enable If Write: Interrupt will be unmasked. If Read: Interrupt is unmasked. 1 RESERVED2 Reserved2 [31:20] read-only CT_INTR_ACK Interrupt clear/ack register 0x14 32 read-write 0x00000000 0x0 INTR_0_L Interrupt ack signal. [0:0] read-write Disable If Write: No effect. If Read: should be returned as this is self clear bit 0 Enable If Write: Interrupt will be de asserted. 1 FIFO_0_FULL_L Interrupt ack signal. [1:1] read-write Disable If Write: No effect. If Read: should be returned as this is self clear bit 0 Enable If Write: Interrupt will be de asserted. 1 COUNTER_0_IS_ZERO_L Interrupt ack signal. [2:2] read-write Disable If Write: No effect. If Read: should be returned as this is self clear bit 0 Enable If Write: Interrupt will be de asserted. 1 COUNTER_0_IS_PEAK_L Interrupt ack signal. [3:3] read-write Disable If Write: No effect. If Read: should be returned as this is self clear bit 0 Enable If Write: Interrupt will be de asserted. 1 RESERVED1 Reserved1 [15:4] read-only INTR_1_L Interrupt ack signal. [16:16] read-write Disable If Write: No effect. If Read: should be returned as this is self clear bit 0 Enable If Write: Interrupt will be de asserted. 1 FIFO_1_FULL_L Interrupt ack signal. [17:17] read-write Disable If Write: No effect. If Read: should be returned as this is self clear bit 0 Enable If Write: Interrupt will be de asserted. 1 COUNTER_1_IS_ZERO_L Interrupt ack signal. [18:18] read-write Disable If Write: No effect. If Read: should be returned as this is self clear bit 0 Enable If Write: Interrupt will be de asserted. 1 COUNTER_1_IS_PEAK_L Interrupt ack signal. [19:19] read-write Disable If Write: No effect. If Read: should be returned as this is self clear bit 0 Enable If Write: Interrupt will be de asserted. 1 RESERVED2 Reserved2 [31:20] read-write CT_MATCH_REG Match value register 0x18 32 read-write 0xFFFFFFFF 0xFFFFFFFF COUNTER_0_MATCH This will be used as lower match [15:0] read-write COUNTER_1_MATCH This will be used as upper match [31:16] read-write CT_MATCH_BUF_REG Match Buffer register 0x1C 32 read-write 0xFFFFFFFF 0xFFFFFFFF COUNTER_0_MATCH_BUF This gets copied to MATCH register if bug_reg_0_en is set. Copying is done when counter 0 is active and hits 0. [15:0] read-write COUNTER_1_MATCH_BUF This gets copied to MATCH register if bug_reg_1_en is set. Copying is done when counter 1 is active and hits 0. [31:16] read-write CT_CAPTURE_REG Capture Register 0x20 32 read-only 0x00000000 COUNTER_0_CAPTURE This is a latched value of counter lower part when the selected capture_event occurs [15:0] read-only COUNTER_1_CAPTURE This is a latched value of counter upper part when the selected capture_event occurs [31:16] read-only CT_COUNTER_REG Counter Register 0x24 32 read-write 0x00000000 COUNTER0 This holds the value of counter-0 [15:0] read-only COUNTER1 This holds the value of counter-1 [31:16] read-only CT_OCU_CTRL_REG OCU control register 0x28 32 read-write 0x00000000 0x7FFFFF OUTPUT_IS_OCU_0 Indicates whether the output is in OCU mode or not for channel-0 [0:0] read-write SYNC_WITH_0 Indicates whether the other channel is in sync with this channel [3:1] read-write OCU_0_DMA_MODE Indicates whether the OCU DMA mode is active or not for channel 0 [4:4] read-write OCU_0_MODE_8_16 Indicates whether entire 16 bits or only 8-bits of the channel 0 are used in OCU mode [5:5] read-write MAKE_OUTPUT_0_HIGH_SEL Check counter ocus for possibilities. When this is hit output will be made high. [8:6] read-write MAKE_OUTPUT_0_LOW_SEL Check counter ocus for possibilities. When this is hit output will be made low. [11:9] read-write RESERVED1 Reserved1 [15:12] read-write OUTPUT_1_IS_OCU Indicates whether the output is in OCU mode or not for channel 1 [16:16] read-write SYNC_WITH_1 Indicates whether the other channel is in sync with this channel [19:17] read-write OCU_1_DMA_MODE Indicates whether the OCU DMA mode is active or not for channel 1 [20:20] read-write OCU_1_MODE_8_16_MODE Indicates whether entire 16 bits or only 8-bits of the channel 1 are used in OCU mode [21:21] read-write MAKE_OUTPUT_1_HIGH_SEL Check counter ocus for possibilities. When this is hit output will be made high. [24:22] read-write MAKE_OUTPUT_1_LOW_SEL Check counter ocus for possibilities. When this is hit output will be made low. [27:25] read-write RESERVED2 Reserved2 [31:28] read-write CT_OCU_COMPARE_REG OCU Compare Register 0x2C 32 read-write 0x00000000 0xFFFF OCU_COMPARE_0_REG Holds the threshold value of present OCU period which denotes the number of clock cycles for which the OCU output should be considered (counter 0) [15:0] read-write OCU_COMPARE_1_REG Holds the threshold value of present OCU period which denotes the number of clock cycles for which the OCU output should be considered (counter 1) [31:16] read-write CT_OCU_COMPARE2_REG OCU Compare2 Register 0x30 32 read-write 0x00000000 0xFFFF OCU_COMPARE2_0_REG Holds the threshold value of present OCU period2 which denotes the number of clock cycles for which the OCU output should be considered (counter 0) [15:0] read-write OCU_COMPARE2_1_REG Holds the threshold value of present OCU period2 which denotes the number of clock cycles for which the OCU output should be considered (counter 1) [31:16] read-write CT_OCU_SYNC_REG OCU Synchronization Register 0x34 32 read-write 0x00000000 0xFFFFFFFF OCU_SYNC_CHANNEL0_REG Starting point of channel 0 for synchronization purpose [15:0] read-write OCU_SYNC_CHANNEL1_REG Starting point of channel 1 for synchronization purpose [31:16] read-write CT_OCU_COMPARE_NXT_REG PWM compare next register 0x38 32 read-write 0x00000000 0xFFFFFFFF OCU_COMPARE_NXT_COUNTER1 OCU output should be high for counter 1 [15:0] read-write OCU_COMPARE_NXT_COUNTER0 PWM output should be high for counter 0 [31:16] read-write CT_OCU_COMPARE2_NXT_REG PWM compare next register 0x40 32 read-write 0x00000000 0xFFFFFFFF OCU_COMPARE2_NXT_COUNTER0 OCU output should be high for counter 1 [15:0] read-write OCU_COMPARE2_NXT_COUNTER1 PWM output should be high for counter 0 [31:16] read-write CT_WFG_CTRL_REG WFG control register 0x3C 32 read-write 0x00000000 0x7FFFFF MAKE_OUTPUT_0_TGL_0_SEL Check the counter ocus possibilities for description for channel 0. [2:0] read-write MAKE_OUTPUT_0_TGL_1_SEL Check the counter ocus possibilities for description for channel 0. [5:3] read-write RESERVED1 Reserved1 [7:6] read-write WFG_TGL_CNT_0_PEAK WFG mode output toggle count clock for channel 0. [15:8] read-write MAKE_OUTPUT_1_TGL_0_SEL Check the counter ocus possibilities for description for channel 1. [18:16] read-write MAKE_OUTPUT_1_TGL_1_SEL Check the counter ocus possibilities for description for channel 1. [21:19] read-write RESERVED2 Reserved2 [23:22] read-write WFG_TGL_CNT_1_PEAK WFG mode output toggle count clock for channel 1 [31:24] read-write CT_START_COUNTER_EVENT_SEL Start counter event select register 0x50 32 read-write 0x00000000 0x3F003F START_COUNTER_0_EVENT_SEL For two 16 bit counters mode: Event select for starting the Counter 0 For 32 bit counter mode: Event select for starting counter [5:0] read-write RESERVED1 Reserved1 [15:6] read-write START_COUNTER_1_EVENT_SEL For two 16 bit counters mode: Event select for starting the Counter 1. For 32 bit counter mode: Invalid. Please refer to events table for description [21:16] read-write RESERVED2 Reserved2 [31:22] read-only CT_START_COUNTER_AND_EVENT Start counter AND event register 0x54 32 read-write 0x00000000 0XF000F START_COUNTER_0_AND_EVENT For two 16 bit counter mode: AND expression valids for AND event in start Counter 0 event For 32 bit counter mode AND expression valids for AND event in start counter event [3:0] read-write RESERVED1 Reserved1 [7:4] read-write START_COUNTER_0_AND_VLD none [11:8] read-write RESERVED2 Reserved2 [15:12] read-only START_COUNTER_1_AND_EVENT For two 16 bit counters mode: AND expression valids for AND event in start counter event For 32 bit counter mode : Invalid [19:16] read-write RESERVED3 Reserved3 [23:20] read-only START_COUNTER_1_AND_VLD none [27:24] read-write RESERVED4 Reserved4 [31:28] read-only CT_START_COUNTER_OR_EVENT Start counter OR event register 0x58 32 read-write 0x00000000 0XF000F START_COUNTER_0_OR_EVENT For two 16 bit counter mode: OR expression valids for OR event in start Counter 0 event For 32 bit counter mode OR expression valids for OR event in start counter event [3:0] read-write RESERVED1 Reserved1 [7:4] read-write START_COUNTER_0_OR_VLD none [11:8] read-write RESERVED2 Reserved2 [15:12] read-write START_COUNTER_1_OR_EVENT For two 16 bit counters mode: OR expression valids for OR event in start counter event For 32 bit counter mode : Invalid. [19:16] read-write RESERVED3 Reserved3 [23:20] read-only START_COUNTER_1_OR_VLD none [27:24] read-write RESERVED4 Reserved4 [31:28] read-only CT_CONTINUE_COUNTER_EVENT_SEL Continue counter event select register 0x5C 32 read-write 0x00000000 0X3F003F CONTINUE_COUNTER_0_EVENT_SEL For two 16 bit counters mode: Event select for continuing the Counter 0 For 32 bit counter mode: Event select for continuing counter [5:0] read-write RESERVED1 Reserved1 [15:6] read-write CONTINUE_COUNTER_1_EVENT_SEL For two 16 bit counters mode: Event select for continuing the Counter 1 For 32 bit counter mode: Invalid. [21:16] read-write RESERVED2 Reserved2 [31:22] read-only CT_CONTINUE_COUNTER_AND_EVENT Continue counter AND event register 0x60 32 read-write 0x00000000 0XF000F CONTINUE_COUNTER_0_AND_EVENT For two 16 bit counter mode: AND expression valids for AND event in continue Counter 0 event For 32 bit counter mode AND expression valids for AND event in continue counter event. [3:0] read-write RESERVED1 Reserved1 [7:4] read-write CONTINUE_COUNTER_0_AND_VLD none [11:8] read-write RESERVED2 Reserved2 [15:12] read-write CONTINUE_COUNTER_1_AND_EVENT For two 16 bit counters mode: AND expression valids for AND event in continue counter event For 32 bit counter mode : Invalid [19:16] read-write RESERVED3 Reserved3 [23:20] read-only CONTINUE_COUNTER_1_AND_VLD none [27:24] read-write RESERVED4 Reserved4 [31:28] read-only CT_CONTINUE_COUNTER_OR_EVENT Continue counter OR event register 0x64 32 read-write 0x00000000 0XF000F CONTINUE_COUNTER_0_OR_EVENT For two 16 bit counter mode: OR expression valids for OR event in continue Counter 0 event For 32 bit counter mode OR expression valids for OR event in continue counter event [3:0] read-write RESERVED1 Reserved1 [7:4] read-write CONTINUE_COUNTER_0_OR_VLD none [11:8] read-write RESERVED2 Reserved2 [15:12] read-write CONTINUE_COUNTER_1_OR_EVENT For two 16 bit counters mode: OR expression valids for OR event in continue counter event For 32 bit counter mode : Invalid [19:16] read-write RESERVED3 Reserved3 [23:20] read-only CONTINUE_COUNTER_1_OR_VLD none [27:24] read-write RESERVED4 Reserved4 [31:28] read-only CT_STOP_COUNTER_EVENT_SEL Stop counter event select register 0x68 32 read-write 0x00000000 0X3F003F STOP_COUNTER_0_EVENT_SEL For two 16 bit counters mode: Event select for Stopping the Counter 0 For 32 bit counter mode: Event select for Stopping counter [5:0] read-write RESERVED1 Reserved1 [15:6] read-write STOP_COUNTER_1_EVENT_SEL For two 16 bit counters mode: Event select for Stopping the Counter 1 For 32 bit counter mode: Invalid [21:16] read-write RESERVED2 Reserved2 [31:22] read-only CT_STOP_COUNTER_AND_EVENT Stop counter AND event register 0x6C 32 read-write 0x00000000 0XF000F STOP_COUNTER_0_AND_EVENT For two 16 bit counter mode: AND expression valids for AND event in stop Counter 0 event For 32 bit counter mode AND expression valids for AND event in stop counter event [3:0] read-write RESERVED1 Reserved1 [7:4] read-write STOP_COUNTER_0_AND_VLD Indicates which bits in [3:0] are valid for considering AND event [11:8] read-write RESERVED2 Reserved2 [15:12] read-write STOP_COUNTER_1_AND_EVENT For two 16 bit counters mode: AND expression valids for AND event in stop counter event For 32 bit counter mode : Invalid [19:16] read-write RESERVED3 Reserved3 [23:20] read-only STOP_COUNTER_1_AND_VLD none [27:24] read-write RESERVED4 Reserved4 [31:28] read-only CT_STOP_COUNTER_OR_EVENT Stop counter OR event register 0x70 32 read-write 0x00000000 0XF000F STOP_COUNTER_0_OR_EVENT For two 16 bit counter mode: OR expression valids for OR event in Stop Counter 0 event For 32 bit counter mode OR expression valids for OR event in Stop counter event [3:0] read-write RESERVED1 Reserved1 [7:4] read-write STOP_COUNTER_0_OR_VLD none [11:8] read-write RESERVED2 Reserved2 [15:12] read-write STOP_COUNTER_1_OR_EVENT For two 16 bit counters mode: OR expression valids for OR event in Stop counter event For 32 bit counter mode : Invalid [19:16] read-write RESERVED3 Reserved3 [23:20] read-only STOP_COUNTER_1_OR_VLD none [27:24] read-write RESERVED4 Reserved4 [31:28] read-only CT_HALT_COUNTER_EVENT_SEL Halt counter event select register 0x74 32 read-write 0x00000000 0X3F003F HALT_COUNTER_0_EVENT_SEL For two 16 bit counters mode: Event select for Halting the Counter 0 For 32 bit counter mode: Event select for Halting counter [5:0] read-write RESUME_FROM_HALT_COUNTER_0 For two 16 bit counters mode: Event select for Halting the Counter 0 For 32 bit counter mode: Event select for Halting counter [6:6] write-only RESERVED1 Reserved1 [15:7] read-only HALT_COUNTER_1_EVENT_SEL For two 16 bit counters mode: Event select for Halting the Counter 1 For 32 bit counter mode: Invalid [21:16] read-write RESUME_FROM_HALT_COUNTER_1 For two 16 bit counters mode: Event select for Halting the Counter 0 For 32 bit counter mode: Event select for Halting counter [22:22] write-only RESERVED2 Reserved2 [31:23] read-only CT_HALT_COUNTER_AND_EVENT Halt counter AND event register 0x78 32 read-write 0x00000000 0XF000F HALT_COUNTER_0_AND_EVENT For two 16 bit counter mode: AND expression valids for AND event in stop Counter 0 event For 32 bit counter mode AND expression valids for AND event in stop counter event [3:0] read-write RESERVED1 Reserved1 [7:4] read-write HALT_COUNTER_0_AND_VLD Indicates which bits in [3:0] are valid for considering AND event [11:8] read-write RESERVED2 Reserved2 [15:12] read-only HALT_COUNTER_1_AND_EVENT For two 16 bit counters mode: AND expression valids for AND event in stop counter event For 32 bit counter mode : Invalid [19:16] read-write RESERVED3 Reserved3 [23:20] read-only HALT_COUNTER_1_AND_VLD none [27:24] read-write RESERVED4 Reserved4 [31:28] read-only CT_HALT_COUNTER_OR_EVENT Halt counter OR event register 0x7C 32 read-write 0x00000000 0XF000F HALT_COUNTER_0_OR_EVENT For two 16 bit counter mode: OR expression valids for OR event in Halt Counter 0 event For 32 bit counter mode OR expression valids for OR event in Halt counter event [3:0] read-write RESERVED1 Reserved1 [7:4] read-write HALT_COUNTER_0_OR_VLD none [11:8] read-write RESERVED2 Reserved2 [15:12] read-only HALT_COUNTER_1_OR_EVENT For two 16 bit counters mode: OR expression valids for OR event in Halt counter event For 32 bit counter mode : Invalid [19:16] read-write RESERVED3 Reserved3 [23:20] read-only HALT_COUNTER_1_OR_VLD none [27:24] read-write RESERVED4 Reserved4 [31:28] read-only CT_INCREMENT_COUNTER_EVENT_SEL Increment counter event select register 0x80 32 read-write 0x00000000 0X3F003F INCREMENT_COUNTER_0_EVENT_SEL For two 16 bit counters mode: Event select for Incrementing the Counter 0 For 32 bit counter mode: Event select for Incrementing counter [5:0] read-write RESERVED1 Reserved1 [15:6] read-only INCREMENT_COUNTER_1_EVENT_SEL For two 16 bit counters mode: Event select for Incrementing the Counter 1 For 32 bit counter mode: Invalid [21:16] read-write RESERVED2 Reserved2 [31:22] read-only CT_INCREMENT_COUNTER_AND_EVENT Increment counter AND event register 0x84 32 read-write 0x00000000 0XF000F INCREMENT_COUNTER_0_AND_EVENT For two 16 bit counter mode: AND expression valids for AND event in stop Counter 0 event For 32 bit counter mode AND expression valids for AND event in stop counter event [3:0] read-write RESERVED1 Reserved1 [7:4] read-write INCREMENT_COUNTER_0_AND_VLD none [11:8] read-write RESERVED2 Reserved2 [15:12] read-only INCREMENT_COUNTER_1_AND_EVENT For two 16 bit counters mode: AND expression valids for AND event in stop counter event For 32 bit counter mode : Invalid [19:16] read-write RESERVED3 Reserved3 [23:20] read-only INCREMENT_COUNTER_1_AND_VLD none [27:24] read-write RESERVED4 Reserved4 [31:28] read-only CT_INCREMENT_COUNTER_OR_EVENT Increment counter OR event register 0x88 32 read-write 0x00000000 0XF000F INCREMENT_COUNTER_0_OR_EVENT For two 16 bit counter mode: OR expression valids for OR event in Increment Counter 0 event For 32 bit counter mode OR expression valids for OR event in Increment counter event [3:0] read-write RESERVED1 Reserved1 [7:4] read-write INCREMENT_COUNTER_0_OR_VLD none [11:8] read-write RESERVED2 Reserved2 [15:12] read-only INCREMENT_COUNTER_1_OR_EVENT For two 16 bit counters mode: OR expression valids for OR event in Increment counter event For 32 bit counter mode : Invalid [19:16] read-write RESERVED4 Reserved4 [23:20] read-only INCREMENT_COUNTER_1_OR_VLD none [27:24] read-write RESERVED5 Reserved5 [31:28] read-only CT_CAPTURE_COUNTER_EVENT_SEL Capture counter event select register 0x8C 32 read-write 0x00000000 0X3F003F CAPTURE_COUNTER_0_EVENT_SEL For two 16 bit counters mode: Event select for Capturing the Counter 0 For 32 bit counter mode: Event select for Capturing counter [5:0] read-write RESERVED1 Reserved1 [15:6] read-only CAPTURE_COUNTER_1_EVENT_SEL For two 16 bit counters mode: Event select for Capturing the Counter 1 For 32 bit counter mode : Invalid [21:16] read-write RESERVED2 Reserved2 [31:22] read-only CT_CAPTURE_COUNTER_AND_EVENT Capture counter AND event register 0x90 32 read-write 0x00000000 0XF000F CAPTURE_COUNTER_0_AND_EVENT For two 16 bit counter mode: AND expression valids for AND event in stop Counter 0 event For 32 bit counter mode AND expression valids for AND event in stop counter event [3:0] read-write RESERVED1 Reserved1 [7:4] read-write CAPTURE_COUNTER_0_AND_VLD none [11:8] read-write RESERVED2 Reserved2 [15:12] read-only CAPTURE_COUNTER_1_AND_EVENT For two 16 bit counters mode: AND expression valids for AND event in stop counter event For 32 bit counter mode : Invalid [19:16] read-write RESERVED3 Reserved3 [23:20] read-only CAPTURE_COUNTER_1_AND_VLD none [27:24] read-write RESERVED4 Reserved4 [31:28] read-only CT_CAPTURE_COUNTER_OR_EVENT Capture counter OR event register 0x94 32 read-write 0x00000000 0XF000F CAPTURE_COUNTER_0_OR_EVENT For two 16 bit counter mode: OR expression valids for OR event in Capture Counter 0 event For 32 bit counter mode OR expression valids for OR event in Capture counter event [3:0] read-write RESERVED1 Reserved1 [7:4] read-write CAPTURE_COUNTER_0_OR_VLD none [11:8] read-write RESERVED2 Reserved2 [15:12] read-only CAPTURE_COUNTER_1_OR_EVENT For two 16 bit counters mode: OR expression valids for OR event in Capture counter event For 32 bit counter mode : Invalid [19:16] read-write RESERVED3 Reserved3 [23:20] read-only CAPTURE_COUNTER_1_OR_VLD none [27:24] read-write RESERVED4 Reserved4 [31:28] read-only CT_OUTPUT_EVENT_SEL Output event select register 0x98 32 read-write 0x00000000 0X3F003F OUTPUT_EVENT_SEL_0 For two 16 bit counters mode: Event select for output event from Counter 0 For 32 bit counter mode: Event select for output event [5:0] read-write RESERVED1 Reserved1 [15:6] read-only OUTPUT_EVENT_SEL_1 For two 16 bit counters mode: Event select for output event from counter 1 For 32 bit counter mode : Invalid [21:16] read-write RESERVED2 Reserved2 [31:22] read-only CT_OUTPUT_AND_EVENT_REG Output AND event Register 0x9C 32 read-write 0x00000000 0xFFFFFFFF OUTPUT_0_AND_EVENT AND expression for AND event in output Counter_0 event. [3:0] read-write RESERVED1 Reserved1 [7:4] read-write OUTPUT_0_AND_VLD AND expression for AND event in output Counter_0 event. [11:8] read-write RESERVED2 Reserved2 [15:12] read-only OUTPUT_1_AND_EVENT AND expression for AND event in output Counter_1 event. [19:16] read-write RESERVED3 Reserved3 [23:20] read-only OUTPUT_1_AND_VLD AND expression for AND event in output Counter_1 event. [27:24] read-write RESERVED4 Reserved4 [31:28] read-only CT_OUTPUT_OR_EVENT Output OR event Register 0xA0 32 read-write 0x00000000 0xFFFFFFFF OUTPUT_0_OR_EVENT OR expression for OR event in output Counter_0 event [3:0] read-write RESERVED1 Reserved1 [7:4] read-write OUTPUT_0_OR_VLD Indicates which bits in [3:0] are valid for considering OR event [11:8] read-write RESERVED2 Reserved2 [15:12] read-only OUTPUT_1_OR_EVENT OR expression for OR event in output Counter_0 event [19:16] read-write RESERVED3 Reserved3 [23:20] read-only OUTPUT_1_OR_VLD Indicates which bits in [3:0] are valid for considering OR event [27:24] read-write RESERVED4 Reserved4 [31:28] read-only CT_INTR_EVENT_SEL Interrupt Event Select Register 0xA4 32 read-write 0x00000000 0X3F003F INTR_EVENT_SEL_0 For two 16 bit counters mode: Event select for interrupt event from Counter 0 For 32 bit counter mode: Event select for output event [5:0] read-write RESERVED1 Reserved1 [15:6] read-only INTR_EVENT_SEL_1 For two 16 bit counters mode: Event select for interrupt event from counter 1 For 32 bit counter mode : Invalid [21:16] read-write RESERVED2 Reserved2 [31:22] read-only CT_INTR_AND_EVENT Interrupt AND Event Register 0xA8 32 read-write 0x00000000 0X3F003F INTR_0_AND_EVENT None [3:0] read-write RESERVED1 Reserved1 [7:4] read-write INTR_0_AND_VLD None [11:8] read-write RESERVED2 Reserved2 [15:12] read-only INTR_1_AND_EVENT None [19:16] read-write RESERVED3 Reserved3 [23:20] read-only INTR_1_AND_VLD None [27:24] read-write RESERVED4 Reserved4 [31:28] read-only CT_INTR_OR_EVENT_REG Interrupt OR Event Register 0xAC 32 read-write 0x00000000 0X3F003F INTR_0_OR_EVENT None [3:0] read-write RESERVED1 Reserved1 [7:4] read-write INTR_0_OR_VLD None [11:8] read-write RESERVED2 Reserved2 [15:12] read-only INTR_1_OR_EVENT None [19:16] read-write RESERVED3 Reserved3 [23:20] read-only INTR_1_OR_VLD None [27:24] read-write RESERVED4 Reserved4 [31:28] read-only CT_RE_FE_RFE_LEV0_LEV1_EVENT_ENABLE_REG Rising Edge Falling Edge Rising and Falling Edge level0 level1 event enable register 0xB0 32 read-write 0x000FFFFF 0X000FFFFF Input_Event_RE_Enable Input event rising edge enables [3:0] read-write Input_Event_FE_Enable Input event falling edge enables: [7:4] read-write Input_Event_RFE_Enable Input event rising and falling edge enables [11:8] read-write Input_Event_lev0_Enable Input event level0 enables [15:12] read-write Input_Event_lev1_Enable Input event level1 enables [19:16] read-write RESERVED Reserved [31:20] read-only CT3 1.0 Configurable timer is used in counting clocks, events and states with reference clock external clock and system clock CT 0x45061100 32 read-write 0 0xB0 registers CT 34 CT_GEN_CTRL_SET_REG General control set register 0x00 32 read-write 0x00000000 0xFFFFFFFF COUNTER_IN_32_BIT_MODE Counter_1 and Counter_0 will be merged and used as a single 32 bit counter [0:0] read-write Disable If Write: Counter will be 32 bit mode If Read: Counter is in two 16 bit mode 0 Enable If Write: Counter will be 32 bit mode If Read: Counter is in two 16 bit mode 1 SOFT_RESET_COUNTER_0_FRM_REG This is applied to 32 bits of counter only when the counter is in 32 bit counter mode otherwise this will be applied to only lower 16 bits of counter [1:1] read-write Disable If Write: No effect If Read: Always should return 0 0 Enable If Write: Counter_1 will be reset If Read: Always should return 0 1 PERIODIC_EN_COUNTER_0_FRM_REG This is applied to 32 bits of counter only when the counter is in 32 bit counter mode otherwise this will be applied to only lower 16 bits of counter [2:2] read-write Disable If Write: No effect If Read: Counter_1 is not in periodic mode 0 Enable If Write: Counter_1 will be in periodic mode If Read: Counter_1 is in periodic mode 1 COUNTER_0_TRIG_FRM_REG This enables the counter to run/active [3:3] read-write Disable If Write: No effect If Read:Read should always return 0 0 Enable If Write:Counter_1 will be active If Read:Read should always return 0 1 COUNTER_0_UP_DOWN This enables the counter to run in up/down/up-down/down-up directions [5:4] read-write 00 If Write:No effect If Read:Counter_0 is in down-up counting mode 0 01 If Write:Counter_0 will be up-counting If Read:Counter_0 is in up-counting mode 1 10 If Write:Counter down direction enable If Read:Counter_0 is in down counting mode 2 11 If Write:Both up and down directions enable. If Read:Counter_0 is in up-down counting mode 3 COUNTER_0_SYNC_TRIG This is applied to 32 bits of counter only when the counter is in 32 bit counter mode otherwise this will be applied to only lower 16 bits of counter. This enables the counter to run/active when sync is found. [6:6] read-write Disable If Write: No effect If Read:Read should always return 0 0 Enable If Write:Counter_0 will be active. If Read:Read should always return 0 1 BUF_REG_0_EN Buffer register gets enabled for MATCH REG. MATCH_BUF_REG is always available and whenever this bit is set only, gets copied to MATCH REG. [7:7] read-write Disable If Write: No effect If Read:Buffer is not enabled and not in path. 0 Enable If Write:Buffer will be enabled and in path If Read:Buffer is enabled and in path 1 RESERVED1 Reserved1 [16:8] read-write SOFT_RESET_COUNTER_1_FRM_REG This resets the counter on the write [17:17] read-write Disable If Write:No effect If Read:Always should return 0 0 Enable If Write:Counter_1 will be reset If Read:Always should return 0 1 PERIODIC_EN_COUNTER_1_FRM_REG This resets the counter on the write [18:18] read-write Disable If Write:No effect If Read:Counter_1 is not in periodic mode 0 Enable If Write:Counter_1 will be in periodic mode If Read:Counter_1 is in periodic mode 1 COUNTER_1_TRIG_FRM This enables the counter to run/active [19:19] read-write Disable If Write:No effect If Read:Always should return 0 0 Enable If Write:Counter_1 will be active If Read:Always should return 0 1 COUNTER_1_UP_DOWN This enables the counter to run in upward direction [21:20] read-write 00 If Write:No effect If Read:Counter_1 is in down-up counting mode 0 01 If Write:Counter_1 will be up-counting If Read:Counter_1 is in up-counting mode 1 10 If Write:Counter down direction enable If Read:Counter_1 is in down counting mode 2 11 If Write:Both up and down directions enable. If Read:Counter_1 is in up-down counting mode 3 COUNTER_1_SYNC_TRIG This is applied to 32 bits of counter only when the counter is in 32 bit counter mode otherwise this will be applied to only lower 16 bits of counter. This enables the counter to run/active when sync is found. [22:22] read-write Disable If Write: No effect If Read:Read should always return 0 0 Enable If Write:Counter_1 will be active. If Read:Read should always return 0 1 BUF_REG_1_EN Buffer register gets enabled for MATCH REG. MATCH_BUF_REG is always available and whenever this bit is set only, gets copied to MATCH REG. [23:23] read-write Disable If Write: No effect If Read:Buffer is not enabled and not in path. 0 Enable If Write:Buffer will be enabled and in path If Read:Buffer is enabled and in path 1 RESERVED2 Reserved2 [31:24] read-write CT_GEN_CTRL_RESET_REG General control reset register 0x04 32 read-write 0x00000000 0xFFFFFFFF COUNTER_IN_32_BIT_MODE Counter_1 and Counter_0 will be merged and used as a single 32 bit counter [0:0] read-write Disable If Write: Counter will be 32 bit mode If Read: Counter is in two 16 bit mode 0 Enable If Write: Counter will be 32 bit mode If Read: Counter is in two 16 bit mode 1 RESERVED1 Reserved1 [1:1] read-only PERIODIC_EN_COUNTER_0_FRM_REG This is applied to 32 bits of counter only when the counter is in 32 bit counter mode otherwise this will be applied to only lower 16 bits of counter [2:2] read-write Disable If Write: No effect If Read: Counter_1 is not in periodic mode 0 Enable If Write: Counter_1 will be in periodic mode If Read: Counter_1 is in periodic mode 1 RESERVED2 Reserved2 [3:3] read-only COUNTER_0_UP_DOWN This enables the counter to run in up/down/up-down/down-up directions [5:4] read-write 00 If Write:No effect If Read:Counter_0 is in down-up counting mode 0 01 If Write:Counter_0 will be up-counting If Read:Counter_0 is in up-counting mode 1 10 If Write:Counter down direction enable If Read:Counter_0 is in down counting mode 2 11 If Write:Both up and down directions enable. If Read:Counter_0 is in up-down counting mode 3 RESERVED3 Reserved3 [6:6] read-only BUF_REG_0_EN Buffer register gets enabled for MATCH REG. MATCH_BUF_REG is always available and whenever this bit is set only, gets copied to MATCH REG. [7:7] read-write Disable If Write: No effect If Read:Buffer is not enabled and not in path. 0 Enable If Write:Buffer will be enabled and in path If Read:Buffer is enabled and in path 1 RESERVED4 Reserved4 [16:8] read-only RESERVED5 Reserved5 [17:17] read-only PERIODIC_EN_COUNTER_1_FRM_REG This resets the counter on the write [18:18] read-write Disable If Write:No effect If Read:Counter_1 is not in periodic mode 0 Enable If Write:Counter_1 will be in periodic mode If Read:Counter_1 is in periodic mode 1 RESERVED6 Reserved6 [19:19] read-only COUNTER_1_UP_DOWN This enables the counter to run in upward direction [21:20] read-write 00 If Write:No effect If Read:Counter_1 is in down-up counting mode 0 01 If Write:Counter_1 will be up-counting If Read:Counter_1 is in up-counting mode 1 10 If Write:Counter down direction enable If Read:Counter_1 is in down counting mode 2 11 If Write:Both up and down directions enable. If Read:Counter_1 is in up-down counting mode 3 RESERVED7 Reserved7 [22:22] read-only BUF_REG_1_EN Buffer register gets enabled for MATCH REG. MATCH_BUF_REG is always available and whenever this bit is set only, gets copied to MATCH REG. [23:23] read-write Disable If Write: No effect If Read:Buffer is not enabled and not in path. 0 Enable If Write:Buffer will be enabled and in path If Read:Buffer is enabled and in path 1 RESERVED8 Reserved8 [31:24] read-only CT_INTR_STS Interrupt status 0x08 32 read-only 0x00000000 INTR_0_L Indicates the FIFO full signal of channel-0 [0:0] read-only FIFO_0_FULL_L Indicates the FIFO full signal of channel-0 [1:1] read-only COUNTER_0_IS_ZERO_L Counter 0 hit zero in active mode. [2:2] read-only COUNTER_0_IS_PEAK_L Counter 0 hit peak (MATCH) in active mode. [3:3] read-only RESERVED1 Reserved1 [15:4] read-only INTR_1_L Indicates the FIFO full signal of channel-1 [16:16] read-only FIFO_1_FULL_L Indicates the FIFO full signal of channel-1 [17:17] read-only COUNTER_1_IS_ZERO_L Counter 1 hit zero in active mode. [18:18] read-only COUNTER_1_IS_PEAK_L Counter 1 hit peak (MATCH) in active mode. [19:19] read-only RESERVED2 Reserved2 [31:20] read-only CT_INTR_MASK Interrupts mask 0x0C 32 read-write 0x00000000 0x0 INTR_0_L Interrupt mask signal. [0:0] read-write Disable If Write: No effect If Read:Interrupt is masked. 0 Enable If Write: Interrupt will be masked. If Read: Interrupt is unmasked. 1 FIFO_0_FULL_L Interrupt mask signal. [1:1] read-write Disable If Write: No effect If Read:Interrupt is masked. 0 Enable If Write: Interrupt will be masked. If Read: Interrupt is unmasked. 1 COUNTER_0_IS_ZERO_L Interrupt mask signal. [2:2] read-write Disable If Write: No effect If Read:Interrupt is masked. 0 Enable If Write: Interrupt will be masked. If Read: Interrupt is unmasked. 1 COUNTER_0_IS_PEAK_L Interrupt mask signal. [3:3] read-write Disable If Write: No effect If Read:Interrupt is masked. 0 Enable If Write: Interrupt will be masked. If Read: Interrupt is unmasked. 1 RESERVED1 Reserved1 [15:4] read-write INTR_1_L Interrupt mask signal. [16:16] read-write Disable If Write: No effect If Read:Interrupt is masked. 0 Enable If Write: Interrupt will be masked. If Read: Interrupt is unmasked. 1 FIFO_1_FULL_L Interrupt mask signal. [17:17] read-write Disable If Write: No effect If Read:Interrupt is masked. 0 Enable If Write: Interrupt will be masked. If Read: Interrupt is unmasked. 1 COUNTER_1_IS_ZERO_L Interrupt mask signal. [18:18] read-write Disable If Write: No effect If Read:Interrupt is masked. 0 Enable If Write: Interrupt will be masked. If Read: Interrupt is unmasked. 1 COUNTER_1_IS_PEAK_L Interrupt mask signal. [19:19] read-write Disable If Write: No effect If Read:Interrupt is masked. 0 Enable If Write: Interrupt will be masked. If Read: Interrupt is unmasked. 1 RESERVED2 Reserved2 [31:20] read-write CT_INTER_UNMASK Interrupts unmask 0x10 32 read-write 0x00000000 0x0 INTR_0_L Interrupt unmask signal. [0:0] read-write Disable If Write: No effect If Read:Interrupt is masked. 0 Enable If Write: Interrupt will be unmasked. If Read: Interrupt is unmasked. 1 FIFO_0_FULL_L Interrupt unmask signal. [1:1] read-write Disable If Write: No effect If Read:Interrupt is masked. 0 Enable If Write: Interrupt will be unmasked. If Read: Interrupt is unmasked. 1 COUNTER_0_IS_ZERO_L Interrupt unmask signal. [2:2] read-write Disable If Write: No effect If Read:Interrupt is masked. 0 Enable If Write: Interrupt will be unmasked. If Read: Interrupt is unmasked. 1 COUNTER_0_IS_PEAK_L Interrupt unmask signal. [3:3] read-write Disable If Write: No effect If Read:Interrupt is masked. 0 Enable If Write: Interrupt will be unmasked. If Read: Interrupt is unmasked. 1 RESERVED1 Reserved1 [15:4] read-only INTR_1_L Interrupt unmask signal. [16:16] read-write Disable If Write: No effect If Read:Interrupt is masked. 0 Enable If Write: Interrupt will be unmasked. If Read: Interrupt is unmasked. 1 FIFO_1_FULL_L Interrupt unmask signal [17:17] read-write Disable If Write: No effect If Read:Interrupt is masked. 0 Enable If Write: Interrupt will be unmasked. If Read: Interrupt is unmasked. 1 COUNTER_1_IS_ZERO_L Interrupt unmask signal. [18:18] read-write Disable If Write: No effect If Read:Interrupt is masked. 0 Enable If Write: Interrupt will be unmasked. If Read: Interrupt is unmasked. 1 COUNTER_1_IS_PEAK_L Interrupt unmask signal. [19:19] read-write Disable If Write: No effect If Read:Interrupt is masked. 0 Enable If Write: Interrupt will be unmasked. If Read: Interrupt is unmasked. 1 RESERVED2 Reserved2 [31:20] read-only CT_INTR_ACK Interrupt clear/ack register 0x14 32 read-write 0x00000000 0x0 INTR_0_L Interrupt ack signal. [0:0] read-write Disable If Write: No effect. If Read: should be returned as this is self clear bit 0 Enable If Write: Interrupt will be de asserted. 1 FIFO_0_FULL_L Interrupt ack signal. [1:1] read-write Disable If Write: No effect. If Read: should be returned as this is self clear bit 0 Enable If Write: Interrupt will be de asserted. 1 COUNTER_0_IS_ZERO_L Interrupt ack signal. [2:2] read-write Disable If Write: No effect. If Read: should be returned as this is self clear bit 0 Enable If Write: Interrupt will be de asserted. 1 COUNTER_0_IS_PEAK_L Interrupt ack signal. [3:3] read-write Disable If Write: No effect. If Read: should be returned as this is self clear bit 0 Enable If Write: Interrupt will be de asserted. 1 RESERVED1 Reserved1 [15:4] read-only INTR_1_L Interrupt ack signal. [16:16] read-write Disable If Write: No effect. If Read: should be returned as this is self clear bit 0 Enable If Write: Interrupt will be de asserted. 1 FIFO_1_FULL_L Interrupt ack signal. [17:17] read-write Disable If Write: No effect. If Read: should be returned as this is self clear bit 0 Enable If Write: Interrupt will be de asserted. 1 COUNTER_1_IS_ZERO_L Interrupt ack signal. [18:18] read-write Disable If Write: No effect. If Read: should be returned as this is self clear bit 0 Enable If Write: Interrupt will be de asserted. 1 COUNTER_1_IS_PEAK_L Interrupt ack signal. [19:19] read-write Disable If Write: No effect. If Read: should be returned as this is self clear bit 0 Enable If Write: Interrupt will be de asserted. 1 RESERVED2 Reserved2 [31:20] read-write CT_MATCH_REG Match value register 0x18 32 read-write 0xFFFFFFFF 0xFFFFFFFF COUNTER_0_MATCH This will be used as lower match [15:0] read-write COUNTER_1_MATCH This will be used as upper match [31:16] read-write CT_MATCH_BUF_REG Match Buffer register 0x1C 32 read-write 0xFFFFFFFF 0xFFFFFFFF COUNTER_0_MATCH_BUF This gets copied to MATCH register if bug_reg_0_en is set. Copying is done when counter 0 is active and hits 0. [15:0] read-write COUNTER_1_MATCH_BUF This gets copied to MATCH register if bug_reg_1_en is set. Copying is done when counter 1 is active and hits 0. [31:16] read-write CT_CAPTURE_REG Capture Register 0x20 32 read-only 0x00000000 COUNTER_0_CAPTURE This is a latched value of counter lower part when the selected capture_event occurs [15:0] read-only COUNTER_1_CAPTURE This is a latched value of counter upper part when the selected capture_event occurs [31:16] read-only CT_COUNTER_REG Counter Register 0x24 32 read-write 0x00000000 COUNTER0 This holds the value of counter-0 [15:0] read-only COUNTER1 This holds the value of counter-1 [31:16] read-only CT_OCU_CTRL_REG OCU control register 0x28 32 read-write 0x00000000 0x7FFFFF OUTPUT_IS_OCU_0 Indicates whether the output is in OCU mode or not for channel-0 [0:0] read-write SYNC_WITH_0 Indicates whether the other channel is in sync with this channel [3:1] read-write OCU_0_DMA_MODE Indicates whether the OCU DMA mode is active or not for channel 0 [4:4] read-write OCU_0_MODE_8_16 Indicates whether entire 16 bits or only 8-bits of the channel 0 are used in OCU mode [5:5] read-write MAKE_OUTPUT_0_HIGH_SEL Check counter ocus for possibilities. When this is hit output will be made high. [8:6] read-write MAKE_OUTPUT_0_LOW_SEL Check counter ocus for possibilities. When this is hit output will be made low. [11:9] read-write RESERVED1 Reserved1 [15:12] read-write OUTPUT_1_IS_OCU Indicates whether the output is in OCU mode or not for channel 1 [16:16] read-write SYNC_WITH_1 Indicates whether the other channel is in sync with this channel [19:17] read-write OCU_1_DMA_MODE Indicates whether the OCU DMA mode is active or not for channel 1 [20:20] read-write OCU_1_MODE_8_16_MODE Indicates whether entire 16 bits or only 8-bits of the channel 1 are used in OCU mode [21:21] read-write MAKE_OUTPUT_1_HIGH_SEL Check counter ocus for possibilities. When this is hit output will be made high. [24:22] read-write MAKE_OUTPUT_1_LOW_SEL Check counter ocus for possibilities. When this is hit output will be made low. [27:25] read-write RESERVED2 Reserved2 [31:28] read-write CT_OCU_COMPARE_REG OCU Compare Register 0x2C 32 read-write 0x00000000 0xFFFF OCU_COMPARE_0_REG Holds the threshold value of present OCU period which denotes the number of clock cycles for which the OCU output should be considered (counter 0) [15:0] read-write OCU_COMPARE_1_REG Holds the threshold value of present OCU period which denotes the number of clock cycles for which the OCU output should be considered (counter 1) [31:16] read-write CT_OCU_COMPARE2_REG OCU Compare2 Register 0x30 32 read-write 0x00000000 0xFFFF OCU_COMPARE2_0_REG Holds the threshold value of present OCU period2 which denotes the number of clock cycles for which the OCU output should be considered (counter 0) [15:0] read-write OCU_COMPARE2_1_REG Holds the threshold value of present OCU period2 which denotes the number of clock cycles for which the OCU output should be considered (counter 1) [31:16] read-write CT_OCU_SYNC_REG OCU Synchronization Register 0x34 32 read-write 0x00000000 0xFFFFFFFF OCU_SYNC_CHANNEL0_REG Starting point of channel 0 for synchronization purpose [15:0] read-write OCU_SYNC_CHANNEL1_REG Starting point of channel 1 for synchronization purpose [31:16] read-write CT_OCU_COMPARE_NXT_REG PWM compare next register 0x38 32 read-write 0x00000000 0xFFFFFFFF OCU_COMPARE_NXT_COUNTER1 OCU output should be high for counter 1 [15:0] read-write OCU_COMPARE_NXT_COUNTER0 PWM output should be high for counter 0 [31:16] read-write CT_OCU_COMPARE2_NXT_REG PWM compare next register 0x40 32 read-write 0x00000000 0xFFFFFFFF OCU_COMPARE2_NXT_COUNTER0 OCU output should be high for counter 1 [15:0] read-write OCU_COMPARE2_NXT_COUNTER1 PWM output should be high for counter 0 [31:16] read-write CT_WFG_CTRL_REG WFG control register 0x3C 32 read-write 0x00000000 0x7FFFFF MAKE_OUTPUT_0_TGL_0_SEL Check the counter ocus possibilities for description for channel 0. [2:0] read-write MAKE_OUTPUT_0_TGL_1_SEL Check the counter ocus possibilities for description for channel 0. [5:3] read-write RESERVED1 Reserved1 [7:6] read-write WFG_TGL_CNT_0_PEAK WFG mode output toggle count clock for channel 0. [15:8] read-write MAKE_OUTPUT_1_TGL_0_SEL Check the counter ocus possibilities for description for channel 1. [18:16] read-write MAKE_OUTPUT_1_TGL_1_SEL Check the counter ocus possibilities for description for channel 1. [21:19] read-write RESERVED2 Reserved2 [23:22] read-write WFG_TGL_CNT_1_PEAK WFG mode output toggle count clock for channel 1 [31:24] read-write CT_START_COUNTER_EVENT_SEL Start counter event select register 0x50 32 read-write 0x00000000 0x3F003F START_COUNTER_0_EVENT_SEL For two 16 bit counters mode: Event select for starting the Counter 0 For 32 bit counter mode: Event select for starting counter [5:0] read-write RESERVED1 Reserved1 [15:6] read-write START_COUNTER_1_EVENT_SEL For two 16 bit counters mode: Event select for starting the Counter 1. For 32 bit counter mode: Invalid. Please refer to events table for description [21:16] read-write RESERVED2 Reserved2 [31:22] read-only CT_START_COUNTER_AND_EVENT Start counter AND event register 0x54 32 read-write 0x00000000 0XF000F START_COUNTER_0_AND_EVENT For two 16 bit counter mode: AND expression valids for AND event in start Counter 0 event For 32 bit counter mode AND expression valids for AND event in start counter event [3:0] read-write RESERVED1 Reserved1 [7:4] read-write START_COUNTER_0_AND_VLD none [11:8] read-write RESERVED2 Reserved2 [15:12] read-only START_COUNTER_1_AND_EVENT For two 16 bit counters mode: AND expression valids for AND event in start counter event For 32 bit counter mode : Invalid [19:16] read-write RESERVED3 Reserved3 [23:20] read-only START_COUNTER_1_AND_VLD none [27:24] read-write RESERVED4 Reserved4 [31:28] read-only CT_START_COUNTER_OR_EVENT Start counter OR event register 0x58 32 read-write 0x00000000 0XF000F START_COUNTER_0_OR_EVENT For two 16 bit counter mode: OR expression valids for OR event in start Counter 0 event For 32 bit counter mode OR expression valids for OR event in start counter event [3:0] read-write RESERVED1 Reserved1 [7:4] read-write START_COUNTER_0_OR_VLD none [11:8] read-write RESERVED2 Reserved2 [15:12] read-write START_COUNTER_1_OR_EVENT For two 16 bit counters mode: OR expression valids for OR event in start counter event For 32 bit counter mode : Invalid. [19:16] read-write RESERVED3 Reserved3 [23:20] read-only START_COUNTER_1_OR_VLD none [27:24] read-write RESERVED4 Reserved4 [31:28] read-only CT_CONTINUE_COUNTER_EVENT_SEL Continue counter event select register 0x5C 32 read-write 0x00000000 0X3F003F CONTINUE_COUNTER_0_EVENT_SEL For two 16 bit counters mode: Event select for continuing the Counter 0 For 32 bit counter mode: Event select for continuing counter [5:0] read-write RESERVED1 Reserved1 [15:6] read-write CONTINUE_COUNTER_1_EVENT_SEL For two 16 bit counters mode: Event select for continuing the Counter 1 For 32 bit counter mode: Invalid. [21:16] read-write RESERVED2 Reserved2 [31:22] read-only CT_CONTINUE_COUNTER_AND_EVENT Continue counter AND event register 0x60 32 read-write 0x00000000 0XF000F CONTINUE_COUNTER_0_AND_EVENT For two 16 bit counter mode: AND expression valids for AND event in continue Counter 0 event For 32 bit counter mode AND expression valids for AND event in continue counter event. [3:0] read-write RESERVED1 Reserved1 [7:4] read-write CONTINUE_COUNTER_0_AND_VLD none [11:8] read-write RESERVED2 Reserved2 [15:12] read-write CONTINUE_COUNTER_1_AND_EVENT For two 16 bit counters mode: AND expression valids for AND event in continue counter event For 32 bit counter mode : Invalid [19:16] read-write RESERVED3 Reserved3 [23:20] read-only CONTINUE_COUNTER_1_AND_VLD none [27:24] read-write RESERVED4 Reserved4 [31:28] read-only CT_CONTINUE_COUNTER_OR_EVENT Continue counter OR event register 0x64 32 read-write 0x00000000 0XF000F CONTINUE_COUNTER_0_OR_EVENT For two 16 bit counter mode: OR expression valids for OR event in continue Counter 0 event For 32 bit counter mode OR expression valids for OR event in continue counter event [3:0] read-write RESERVED1 Reserved1 [7:4] read-write CONTINUE_COUNTER_0_OR_VLD none [11:8] read-write RESERVED2 Reserved2 [15:12] read-write CONTINUE_COUNTER_1_OR_EVENT For two 16 bit counters mode: OR expression valids for OR event in continue counter event For 32 bit counter mode : Invalid [19:16] read-write RESERVED3 Reserved3 [23:20] read-only CONTINUE_COUNTER_1_OR_VLD none [27:24] read-write RESERVED4 Reserved4 [31:28] read-only CT_STOP_COUNTER_EVENT_SEL Stop counter event select register 0x68 32 read-write 0x00000000 0X3F003F STOP_COUNTER_0_EVENT_SEL For two 16 bit counters mode: Event select for Stopping the Counter 0 For 32 bit counter mode: Event select for Stopping counter [5:0] read-write RESERVED1 Reserved1 [15:6] read-write STOP_COUNTER_1_EVENT_SEL For two 16 bit counters mode: Event select for Stopping the Counter 1 For 32 bit counter mode: Invalid [21:16] read-write RESERVED2 Reserved2 [31:22] read-only CT_STOP_COUNTER_AND_EVENT Stop counter AND event register 0x6C 32 read-write 0x00000000 0XF000F STOP_COUNTER_0_AND_EVENT For two 16 bit counter mode: AND expression valids for AND event in stop Counter 0 event For 32 bit counter mode AND expression valids for AND event in stop counter event [3:0] read-write RESERVED1 Reserved1 [7:4] read-write STOP_COUNTER_0_AND_VLD Indicates which bits in [3:0] are valid for considering AND event [11:8] read-write RESERVED2 Reserved2 [15:12] read-write STOP_COUNTER_1_AND_EVENT For two 16 bit counters mode: AND expression valids for AND event in stop counter event For 32 bit counter mode : Invalid [19:16] read-write RESERVED3 Reserved3 [23:20] read-only STOP_COUNTER_1_AND_VLD none [27:24] read-write RESERVED4 Reserved4 [31:28] read-only CT_STOP_COUNTER_OR_EVENT Stop counter OR event register 0x70 32 read-write 0x00000000 0XF000F STOP_COUNTER_0_OR_EVENT For two 16 bit counter mode: OR expression valids for OR event in Stop Counter 0 event For 32 bit counter mode OR expression valids for OR event in Stop counter event [3:0] read-write RESERVED1 Reserved1 [7:4] read-write STOP_COUNTER_0_OR_VLD none [11:8] read-write RESERVED2 Reserved2 [15:12] read-write STOP_COUNTER_1_OR_EVENT For two 16 bit counters mode: OR expression valids for OR event in Stop counter event For 32 bit counter mode : Invalid [19:16] read-write RESERVED3 Reserved3 [23:20] read-only STOP_COUNTER_1_OR_VLD none [27:24] read-write RESERVED4 Reserved4 [31:28] read-only CT_HALT_COUNTER_EVENT_SEL Halt counter event select register 0x74 32 read-write 0x00000000 0X3F003F HALT_COUNTER_0_EVENT_SEL For two 16 bit counters mode: Event select for Halting the Counter 0 For 32 bit counter mode: Event select for Halting counter [5:0] read-write RESUME_FROM_HALT_COUNTER_0 For two 16 bit counters mode: Event select for Halting the Counter 0 For 32 bit counter mode: Event select for Halting counter [6:6] write-only RESERVED1 Reserved1 [15:7] read-only HALT_COUNTER_1_EVENT_SEL For two 16 bit counters mode: Event select for Halting the Counter 1 For 32 bit counter mode: Invalid [21:16] read-write RESUME_FROM_HALT_COUNTER_1 For two 16 bit counters mode: Event select for Halting the Counter 0 For 32 bit counter mode: Event select for Halting counter [22:22] write-only RESERVED2 Reserved2 [31:23] read-only CT_HALT_COUNTER_AND_EVENT Halt counter AND event register 0x78 32 read-write 0x00000000 0XF000F HALT_COUNTER_0_AND_EVENT For two 16 bit counter mode: AND expression valids for AND event in stop Counter 0 event For 32 bit counter mode AND expression valids for AND event in stop counter event [3:0] read-write RESERVED1 Reserved1 [7:4] read-write HALT_COUNTER_0_AND_VLD Indicates which bits in [3:0] are valid for considering AND event [11:8] read-write RESERVED2 Reserved2 [15:12] read-only HALT_COUNTER_1_AND_EVENT For two 16 bit counters mode: AND expression valids for AND event in stop counter event For 32 bit counter mode : Invalid [19:16] read-write RESERVED3 Reserved3 [23:20] read-only HALT_COUNTER_1_AND_VLD none [27:24] read-write RESERVED4 Reserved4 [31:28] read-only CT_HALT_COUNTER_OR_EVENT Halt counter OR event register 0x7C 32 read-write 0x00000000 0XF000F HALT_COUNTER_0_OR_EVENT For two 16 bit counter mode: OR expression valids for OR event in Halt Counter 0 event For 32 bit counter mode OR expression valids for OR event in Halt counter event [3:0] read-write RESERVED1 Reserved1 [7:4] read-write HALT_COUNTER_0_OR_VLD none [11:8] read-write RESERVED2 Reserved2 [15:12] read-only HALT_COUNTER_1_OR_EVENT For two 16 bit counters mode: OR expression valids for OR event in Halt counter event For 32 bit counter mode : Invalid [19:16] read-write RESERVED3 Reserved3 [23:20] read-only HALT_COUNTER_1_OR_VLD none [27:24] read-write RESERVED4 Reserved4 [31:28] read-only CT_INCREMENT_COUNTER_EVENT_SEL Increment counter event select register 0x80 32 read-write 0x00000000 0X3F003F INCREMENT_COUNTER_0_EVENT_SEL For two 16 bit counters mode: Event select for Incrementing the Counter 0 For 32 bit counter mode: Event select for Incrementing counter [5:0] read-write RESERVED1 Reserved1 [15:6] read-only INCREMENT_COUNTER_1_EVENT_SEL For two 16 bit counters mode: Event select for Incrementing the Counter 1 For 32 bit counter mode: Invalid [21:16] read-write RESERVED2 Reserved2 [31:22] read-only CT_INCREMENT_COUNTER_AND_EVENT Increment counter AND event register 0x84 32 read-write 0x00000000 0XF000F INCREMENT_COUNTER_0_AND_EVENT For two 16 bit counter mode: AND expression valids for AND event in stop Counter 0 event For 32 bit counter mode AND expression valids for AND event in stop counter event [3:0] read-write RESERVED1 Reserved1 [7:4] read-write INCREMENT_COUNTER_0_AND_VLD none [11:8] read-write RESERVED2 Reserved2 [15:12] read-only INCREMENT_COUNTER_1_AND_EVENT For two 16 bit counters mode: AND expression valids for AND event in stop counter event For 32 bit counter mode : Invalid [19:16] read-write RESERVED3 Reserved3 [23:20] read-only INCREMENT_COUNTER_1_AND_VLD none [27:24] read-write RESERVED4 Reserved4 [31:28] read-only CT_INCREMENT_COUNTER_OR_EVENT Increment counter OR event register 0x88 32 read-write 0x00000000 0XF000F INCREMENT_COUNTER_0_OR_EVENT For two 16 bit counter mode: OR expression valids for OR event in Increment Counter 0 event For 32 bit counter mode OR expression valids for OR event in Increment counter event [3:0] read-write RESERVED1 Reserved1 [7:4] read-write INCREMENT_COUNTER_0_OR_VLD none [11:8] read-write RESERVED2 Reserved2 [15:12] read-only INCREMENT_COUNTER_1_OR_EVENT For two 16 bit counters mode: OR expression valids for OR event in Increment counter event For 32 bit counter mode : Invalid [19:16] read-write RESERVED4 Reserved4 [23:20] read-only INCREMENT_COUNTER_1_OR_VLD none [27:24] read-write RESERVED5 Reserved5 [31:28] read-only CT_CAPTURE_COUNTER_EVENT_SEL Capture counter event select register 0x8C 32 read-write 0x00000000 0X3F003F CAPTURE_COUNTER_0_EVENT_SEL For two 16 bit counters mode: Event select for Capturing the Counter 0 For 32 bit counter mode: Event select for Capturing counter [5:0] read-write RESERVED1 Reserved1 [15:6] read-only CAPTURE_COUNTER_1_EVENT_SEL For two 16 bit counters mode: Event select for Capturing the Counter 1 For 32 bit counter mode : Invalid [21:16] read-write RESERVED2 Reserved2 [31:22] read-only CT_CAPTURE_COUNTER_AND_EVENT Capture counter AND event register 0x90 32 read-write 0x00000000 0XF000F CAPTURE_COUNTER_0_AND_EVENT For two 16 bit counter mode: AND expression valids for AND event in stop Counter 0 event For 32 bit counter mode AND expression valids for AND event in stop counter event [3:0] read-write RESERVED1 Reserved1 [7:4] read-write CAPTURE_COUNTER_0_AND_VLD none [11:8] read-write RESERVED2 Reserved2 [15:12] read-only CAPTURE_COUNTER_1_AND_EVENT For two 16 bit counters mode: AND expression valids for AND event in stop counter event For 32 bit counter mode : Invalid [19:16] read-write RESERVED3 Reserved3 [23:20] read-only CAPTURE_COUNTER_1_AND_VLD none [27:24] read-write RESERVED4 Reserved4 [31:28] read-only CT_CAPTURE_COUNTER_OR_EVENT Capture counter OR event register 0x94 32 read-write 0x00000000 0XF000F CAPTURE_COUNTER_0_OR_EVENT For two 16 bit counter mode: OR expression valids for OR event in Capture Counter 0 event For 32 bit counter mode OR expression valids for OR event in Capture counter event [3:0] read-write RESERVED1 Reserved1 [7:4] read-write CAPTURE_COUNTER_0_OR_VLD none [11:8] read-write RESERVED2 Reserved2 [15:12] read-only CAPTURE_COUNTER_1_OR_EVENT For two 16 bit counters mode: OR expression valids for OR event in Capture counter event For 32 bit counter mode : Invalid [19:16] read-write RESERVED3 Reserved3 [23:20] read-only CAPTURE_COUNTER_1_OR_VLD none [27:24] read-write RESERVED4 Reserved4 [31:28] read-only CT_OUTPUT_EVENT_SEL Output event select register 0x98 32 read-write 0x00000000 0X3F003F OUTPUT_EVENT_SEL_0 For two 16 bit counters mode: Event select for output event from Counter 0 For 32 bit counter mode: Event select for output event [5:0] read-write RESERVED1 Reserved1 [15:6] read-only OUTPUT_EVENT_SEL_1 For two 16 bit counters mode: Event select for output event from counter 1 For 32 bit counter mode : Invalid [21:16] read-write RESERVED2 Reserved2 [31:22] read-only CT_OUTPUT_AND_EVENT_REG Output AND event Register 0x9C 32 read-write 0x00000000 0xFFFFFFFF OUTPUT_0_AND_EVENT AND expression for AND event in output Counter_0 event. [3:0] read-write RESERVED1 Reserved1 [7:4] read-write OUTPUT_0_AND_VLD AND expression for AND event in output Counter_0 event. [11:8] read-write RESERVED2 Reserved2 [15:12] read-only OUTPUT_1_AND_EVENT AND expression for AND event in output Counter_1 event. [19:16] read-write RESERVED3 Reserved3 [23:20] read-only OUTPUT_1_AND_VLD AND expression for AND event in output Counter_1 event. [27:24] read-write RESERVED4 Reserved4 [31:28] read-only CT_OUTPUT_OR_EVENT Output OR event Register 0xA0 32 read-write 0x00000000 0xFFFFFFFF OUTPUT_0_OR_EVENT OR expression for OR event in output Counter_0 event [3:0] read-write RESERVED1 Reserved1 [7:4] read-write OUTPUT_0_OR_VLD Indicates which bits in [3:0] are valid for considering OR event [11:8] read-write RESERVED2 Reserved2 [15:12] read-only OUTPUT_1_OR_EVENT OR expression for OR event in output Counter_0 event [19:16] read-write RESERVED3 Reserved3 [23:20] read-only OUTPUT_1_OR_VLD Indicates which bits in [3:0] are valid for considering OR event [27:24] read-write RESERVED4 Reserved4 [31:28] read-only CT_INTR_EVENT_SEL Interrupt Event Select Register 0xA4 32 read-write 0x00000000 0X3F003F INTR_EVENT_SEL_0 For two 16 bit counters mode: Event select for interrupt event from Counter 0 For 32 bit counter mode: Event select for output event [5:0] read-write RESERVED1 Reserved1 [15:6] read-only INTR_EVENT_SEL_1 For two 16 bit counters mode: Event select for interrupt event from counter 1 For 32 bit counter mode : Invalid [21:16] read-write RESERVED2 Reserved2 [31:22] read-only CT_INTR_AND_EVENT Interrupt AND Event Register 0xA8 32 read-write 0x00000000 0X3F003F INTR_0_AND_EVENT None [3:0] read-write RESERVED1 Reserved1 [7:4] read-write INTR_0_AND_VLD None [11:8] read-write RESERVED2 Reserved2 [15:12] read-only INTR_1_AND_EVENT None [19:16] read-write RESERVED3 Reserved3 [23:20] read-only INTR_1_AND_VLD None [27:24] read-write RESERVED4 Reserved4 [31:28] read-only CT_INTR_OR_EVENT_REG Interrupt OR Event Register 0xAC 32 read-write 0x00000000 0X3F003F INTR_0_OR_EVENT None [3:0] read-write RESERVED1 Reserved1 [7:4] read-write INTR_0_OR_VLD None [11:8] read-write RESERVED2 Reserved2 [15:12] read-only INTR_1_OR_EVENT None [19:16] read-write RESERVED3 Reserved3 [23:20] read-only INTR_1_OR_VLD None [27:24] read-write RESERVED4 Reserved4 [31:28] read-only CT_RE_FE_RFE_LEV0_LEV1_EVENT_ENABLE_REG Rising Edge Falling Edge Rising and Falling Edge level0 level1 event enable register 0xB0 32 read-write 0x000FFFFF 0X000FFFFF Input_Event_RE_Enable Input event rising edge enables [3:0] read-write Input_Event_FE_Enable Input event falling edge enables: [7:4] read-write Input_Event_RFE_Enable Input event rising and falling edge enables [11:8] read-write Input_Event_lev0_Enable Input event level0 enables [15:12] read-write Input_Event_lev1_Enable Input event level1 enables [19:16] read-write RESERVED Reserved [31:20] read-only CT_MUX_REG 1.0 Configurable timer is used in counting clocks, events and states with reference clock external clock and system clock CT 0x4506F000 32 read-write 0 0x20 registers CT_MUX_SEL_0_REG MUX_SEL_0_REG Register 0x00 32 read-write 0x00000000 0xF MUX_SEL_0 Select value to select first output value fifo_0_full[0] out of all the fifo_0_full_muxed signals of counter 0 [3:0] read-write RESERVED1 Reserved1 [31:4] read-write CT_MUX_SEL_1_REG MUX_SEL_1_REG Register 0x004 32 read-write 0x00000000 0xF MUX_SEL_1 Select value to select first output value fifo_0_full[1] out of all the fifo_0_full_muxed signals of counter 0 [3:0] read-write RESERVED1 Reserved1 [31:4] read-write CT_MUX_SEL_2_REG MUX_SEL_2_REG Register 0x008 32 read-write 0x00000000 0xF MUX_SEL_2 Select value to select first output value fifo_1_full[0] out of all the fifo_1_full_muxed signals of counter 1 [3:0] read-write RESERVED1 Reserved1 [31:4] read-write CT_MUX_SEL_3_REG MUX_SEL_3_REG Register 0x00C 32 read-write 0x0000FFFF 0xF MUX_SEL_3 Select value to select first output value fifo_1_full[1] out of all the fifo_1_full_muxed signals of counter 1 [3:0] read-write RESERVED1 Reserved1 [31:4] read-write CT_OUTPUT_EVENT1_ADC_SEL OUTPUT_EVENT_ADC_SEL Register 0x018 32 read-write 0x0000FFFF 0xF OUTPUT_EVENT_ADC_SEL Select signals to select one output event out of all the output events output_event_0 output_event_1, output_event_2, output_event_3 to enable ADC module [3:0] read-write RESERVED1 Reserved1 [31:4] read-write CT_OUTPUT_EVENT2_ADC_SEL OUTPUT_EVENT_ADC_SEL Register 0x01C 32 read-write 0x0000FFFF 0xF OUTPUT_EVENT_ADC_SEL Select signals to select one output event out of all the output events output_event_0 output_event_1, output_event_2, output_event_3 to enable ADC module [3:0] read-write RESERVED1 Reserved1 [31:4] read-write EGPIO 1.0 ENHANCED GENERAL PERPOSE INPUT/OUTPUT EGPIO 0x46130000 32 read-write 0x0000 0x1260 registers EGPIO_GROUP_0 50 EGPIO_GROUP_1 51 EGPIO_PIN_0 52 EGPIO_PIN_1 53 EGPIO_PIN_2 54 EGPIO_PIN_3 55 EGPIO_PIN_4 56 EGPIO_PIN_5 57 EGPIO_PIN_6 58 EGPIO_PIN_7 59 80 0x10 PIN_CONFIGn Pin configuration registers(0-79) 0x0000 GPIO_CONFIG_REG__n_ GPIO Configuration Register 0x00 32 read-write 0x0000 0xFFFF DIRECTION Direction of the GPIO pin [0:0] read-write Disable Output 0 Enable Input 1 PORTMASK Port mask value [1:1] read-write MODE GPIO Pin Mode Used for GPIO Pin Muxing [5:2] read-write Mode0 000: Mode 0 0 Mode1 001:Mode 1 1 Mode2 010:Mode 2 2 Mode3 011:Mode 3 3 Mode4 100:Mode 4 4 Mode5 101: Mode 5 5 Mode6 110:Mode 6 6 Mode7 111:Mode 7 7 RESERVED1 Reserved1 [7:6] read-write GROUP_INTERRUPT1_ENABLE When set, the corresponding GPIO is pin is selected for group intr 1 generation [8:8] read-write Enable enable the gpio group interrupt 1 Disable disable the gpio group interrupt1 0 GROUP_INTERRUPT1_POLARITY Decides the active value of the pin to be considered for group interrupt 1 generation [9:9] read-write Disable group interrupt gets generated when gpio input pin status is zero 0 Enable grp interrupt gets generated when gpio input pin status is 1 1 GROUP_INTERRUPT2_ENABLE When set, the corresponding GPIO is pin is selected for group intr 2 generation [10:10] read-write Enable enable the gpio group interrupt2 1 Disable disable the gpio group interrupt2 0 GROUP_INTERRUPT2_POLARITY Decides the active value of the pin to be considered for group interrupt 2 generation [11:11] read-write Disable group interrupt gets generated when gpio input pin status is zero 0 Enable grp interrupt gets generated when gpio input pin status is 1 1 GROUP_INTERRUPT3_ENABLE When set, the corresponding GPIO is pin is selected for group intr 3 generation [12:12] read-write Enable enable the gpio group interrupt2 1 Disable disable the gpio group interrupt2 0 GROUP_INTERRUPT3_POLARITY Decides the active value of the pin to be considered for group interrupt 3 generation [13:13] read-write Disable group interrupt gets generated when gpio input pin status is zero 0 Enable grp interrupt gets generated when gpio input pin status is 1 1 GROUP_INTERRUPT4_ENABLE When set, the corresponding GPIO is pin is selected for group intr 4 generation [14:14] read-write Enable enable the gpio group interrupt2 1 Disable disable the gpio group interrupt2 0 GROUP_INTERRUPT4_POLARITY Decides the active value of the pin to be considered for group interrupt 4 generation [15:15] read-write Disable group interrupt gets generated when gpio input pin status is zero 0 Enable grp interrupt gets generated when gpio input pin status is 1 1 RESERVED3 Reserved3 [31:16] read-write BIT_LOAD_REG__n_ Bit Load 0x04 32 read-write 0x00000000 0xFFFF BIT_LOAD Loads 0th bit on to the pin on write. And reads the value on pin on read into 0th bit [0:0] read-write RESERVED1 Reserved1 [31:1] read-write WORD_LOAD_REG__n_ Word Load 0x08 32 read-write 0x0000 0xFFFF WORD_LOAD Loads 1 on the pin when any of the bit in load value is 1. On read pass the bit status into all bits. [15:0] read-write RESERVED1 Reserved1 [31:16] read-write 6 0x40 PORT_CONFIGn Port configuration registers (0-5) 0x1000 PORT_LOAD_REG__n_ Port Load 0x00 32 read-write 0x00000000 0xFFFF PORT_LOAD Loads the value on to pin on write. And reads the value of load register on read [15:0] read-write RES RES [31:16] read-only PORT_SET_REG__n_ Port Set Register 0x04 32 write-only 0x00000000 PORT_SET Sets the pin when corresponding bit is high. Writing zero has no effect. [15:0] write-only RESERVED1 Reserved1 [31:16] write-only PORT_CLEAR_REG__n_ Port Clear Register 0x08 32 write-only 0x00000000 0xFFFF PORT_CLEAR Clears the pin when corresponding bit is high. Writing zero has no effect. [15:0] write-only RESERVED1 Reserved1 [31:16] write-only PORT_MASKED_LOAD_REG__n_ Port Masked Load Register 0x0C 32 write-only 0x00000000 0xFFFF PORT_MASKED_LOAD Only loads into pins which are not masked. On read, pass only status unmasked pins [15:0] write-only RESERVED1 Reserved1 [31:16] write-only PORT_TOGGLE_REG__n_ Port Toggle Register 0x10 32 write-only 0xFFFF PORT_TOGGLE Toggles the pin when corresponding bit is high. Writing zero has not effect. [15:0] write-only RESERVED1 Reserved1 [31:16] write-only PORT_READ_REG__n_ Port Read Register 0x14 32 read-only 0x00000000 PORT_READ Reads the value on GPIO pins irrespective of the pin mode. [15:0] read-only RESERVED1 Reserved1 [31:16] read-only 6 0x08 INTRn GPIO Interrupt related registers (0-5) 0x1200 GPIO_INTR_CTRL__n_ GPIO Interrupt Control Register 0x00 32 read-write 0x00000010 0x3F1F LEVEL_HIGH_ENABLE enables interrupt generation when pin level is 1 [0:0] read-write Disable disabled 0 Enable Interrupt enabled 1 LEVEL_LOW_ENABLE enables interrupt generation when pin level is 0 [1:1] read-write Disable disabled 0 Enable Interrupt enabled 1 RISE_EDGE_ENABLE enables interrupt generation when rising edge is detected on pin [2:2] read-write Disable disabled 0 Enable Interrupt enabled 1 FALL_EDGE_ENABLE enables interrupt generation when Falling edge is detected on pin [3:3] read-write Disable disabled 0 Enable Interrupt enabled 1 MASK Masks the interrupt. Interrupt will still be seen in status register when enabled [4:4] read-write Disable Interrupt masked 0 Enable Interrupt unmasked 1 RESERVED1 Reserved1 [7:5] read-write PIN_NUMBER GPIO Pin to be chosen for interrupt generation [11:8] read-write PORT_NUMBER GPIO Port to be chosen for interrupt generation [13:12] read-write RESERVED2 Reserved2 [31:14] read-write GPIO_INTR_STATUS__n_ GPIO Interrupt Status Register 0x04 32 read-write 0x00000000 0x1F INTERRUPT_STATUS Gets set when interrupt is enabled and occurs. [0:0] read-write Disable Writing 0 has not effect 0 Enable When 1 is written it gets cleared. Also clears rise edge and fall edge status bits 1 RISE_EDGE_STATUS Gets set when rise edge is enabled and occurs. [1:1] read-write Disable Writing 0 has not effect 0 Enable When 1 is written it gets cleared. 1 FALL_EDGE_STATUS Gets set when Fall edge is enabled and occurs. [2:2] read-write Disable Writing 0 has not effect 0 Enable When 1 is written it gets cleared. 1 MASK_SET Mask set [3:3] write-only Disable On read, this bit should result it in 0 0 Enable When 1 is written mask bit will get set 1 MASK_CLEAR Mask Clear [4:4] write-only Disable On read, this bit should result it in 0 0 Enable When 1 is written mask bit gets cleared 1 RESERVED1 Reserved1 [31:5] read-write 4 0x08 GPIO_GRP_INTRn GPIO Group interrupt related registers (0-3) 0x1240 GPIO_GRP_INTR_CTRL_REG__n_ GPIO Interrupt 0 Control Register 0x00 32 read-write 0x00000010 0x1F AND_OR AND/OR [0:0] read-write Disable AND 0 Enable OR 1 LEVEL_EDGE Level/Edge [1:1] read-write Disable Level 0 Enable Edge 1 ENABLE_WAKEUP For wakeup generation, actual pin status has to be seen(before double ranking point) [2:2] read-write ENABLE_INTERRUPT Enable Interrupt [3:3] read-write Disable Disable 0 Enable Enable 1 MASK Mask [4:4] read-write Disable Mask 0 Enable unmask 1 RESERVED1 Reserved1 [31:5] read-write GPIO_GRP_INTR_STS__n_ GPIO Interrupt 0 Status Register 0x04 32 read-write 0x00000010 0x1B INTERRUPT_STATUS Interrupt status is available in this bit when interrupt is enabled and generated. When 1 is written, interrupt gets cleared. [0:0] read-write WAKEUP Double ranked version of wakeup. Gets set when wakeup is enabled and occurs. When 1 is written it gets cleared [1:1] read-only RESERVED1 Reserved1 [2:2] read-write MASK_SET Gives zero on read [3:3] read-write MASK_CLEAR Gives zero on read [4:4] read-write RESERVED2 Reserved2 [31:5] read-write ULP_EGPIO 1.0 ENHANCED GENERAL PERPOSE INPUT/OUTPUT EGPIO 0x2404C000 32 read-write 0x0000 0x1260 registers ULP_EGPIO_GROUP 19 ULP_EGPIO_PIN 18 EGPIO_PIN_0 52 EGPIO_PIN_1 53 EGPIO_PIN_2 54 EGPIO_PIN_3 55 EGPIO_PIN_4 56 EGPIO_PIN_5 57 EGPIO_PIN_6 58 EGPIO_PIN_7 59 11 0x10 PIN_CONFIGn GPIO Pint configuration related registers(0-79) 0x0000 GPIO_CONFIG_REG__n_ GPIO Configuration Register 0x00 32 read-write 0x00000001 0xFFFFFFFF DIRECTION Direction of the GPIO pin [0:0] read-write Disable Output 0 Enable Input 1 PORTMASK Port mask value [1:1] read-write MODE GPIO Pin Mode Used for GPIO Pin Muxing [5:2] read-write Mode0 000: Mode 0 0 Mode1 001:Mode 1 1 Mode2 010:Mode 2 2 Mode3 011:Mode 3 3 Mode4 100:Mode 4 4 Mode5 101: Mode 5 5 Mode6 110:Mode 6 6 Mode7 111:Mode 7 7 RESERVED1 Reserved1 [7:6] read-write GROUP_INTERRUPT1_ENABLE When set, the corresponding GPIO is pin is selected for group intr 1 generation [8:8] read-write Enable enable the gpio group interrupt 1 Disable disable the gpio group interrupt1 0 GROUP_INTERRUPT1_POLARITY Decides the active value of the pin to be considered for group interrupt 1 generation [9:9] read-write Disable group interrupt gets generated when gpio input pin status is zero 0 Enable grp interrupt gets generated when gpio input pin status is 1 1 GROUP_INTERRUPT2_ENABLE When set, the corresponding GPIO is pin is selected for group intr 2 generation [10:10] read-write Enable enable the gpio group interrupt2 1 Disable disable the gpio group interrupt2 0 GROUP_INTERRUPT2_POLARITY Decides the active value of the pin to be considered for group interrupt 2 generation [11:11] read-write Disable group interrupt gets generated when gpio input pin status is zero 0 Enable grp interrupt gets generated when gpio input pin status is 1 1 RESERVED2 Reserved2 [15:12] read-write RESERVED3 Reserved3 [31:16] read-write BIT_LOAD_REG__n_ Bit Load 0x04 32 read-write 0x00000000 0xFFFF BIT_LOAD Loads 0th bit on to the pin on write. And reads the value on pin on read into 0th bit [0:0] read-write RESERVED1 Reserved1 [31:1] read-write WORD_LOAD_REG__n_ Word Load 0x08 32 read-write 0x0000 0xFFFF WORD_LOAD Loads 1 on the pin when any of the bit in load value is 1. On read pass the bit status into all bits. [15:0] read-write RESERVED1 Reserved1 [31:16] read-write 6 0x18 PORT_CONFIGn GPIO port configuration related registers (0-5) 0x1000 PORT_LOAD_REG__n_ Port Load 0x00 32 read-write 0x00000000 0xFFFF PORT_LOAD Loads the value on to pin on write. And reads the value of load register on read [15:0] read-write RES RES [31:16] read-only PORT_SET_REG__n_ Port Set Register 0x04 32 write-only 0x00000000 PORT_SET Sets the pin when corresponding bit is high. Writing zero has no effect. [15:0] write-only RESERVED1 Reserved1 [31:16] write-only PORT_CLEAR_REG__n_ Port Clear Register 0x08 32 write-only 0x00000000 0xFFFF PORT_CLEAR Clears the pin when corresponding bit is high. Writing zero has no effect. [15:0] write-only RESERVED1 Reserved1 [31:16] write-only PORT_MASKED_LOAD_REG__n_ Port Masked Load Register 0x0C 32 write-only 0x00000000 0xFFFF PORT_MASKED_LOAD Only loads into pins which are not masked. On read, pass only status unmasked pins [15:0] write-only RESERVED1 Reserved1 [31:16] write-only PORT_TOGGLE_REG__n_ Port Toggle Register 0x10 32 write-only 0xFFFF PORT_TOGGLE Toggles the pin when corresponding bit is high. Writing zero has not effect. [15:0] write-only RESERVED1 Reserved1 [31:16] write-only PORT_READ_REG__n_ Port Read Register 0x14 32 read-only 0x00000000 PORT_READ Reads the value on GPIO pins irrespective of the pin mode. [15:0] read-only RESERVED1 Reserved1 [31:16] read-only 6 0x08 INTRn GPIO interrupt related registers(0-5) 0x1200 GPIO_INTR_CTRL__n_ GPIO Interrupt Control Register 0x00 32 read-write 0x00000010 0x3F1F LEVEL_HIGH_ENABLE enables interrupt generation when pin level is 1 [0:0] read-write Disable disabled 0 Enable Interrupt enabled 1 LEVEL_LOW_ENABLE enables interrupt generation when pin level is 0 [1:1] read-write Disable disabled 0 Enable Interrupt enabled 1 RISE_EDGE_ENABLE enables interrupt generation when rising edge is detected on pin [2:2] read-write Disable disabled 0 Enable Interrupt enabled 1 FALL_EDGE_ENABLE enables interrupt generation when Falling edge is detected on pin [3:3] read-write Disable disabled 0 Enable Interrupt enabled 1 MASK Masks the interrupt. Interrupt will still be seen in status register when enabled [4:4] read-write Disable Interrupt masked 0 Enable Interrupt unmasked 1 RESERVED1 Reserved1 [7:5] read-write PIN_NUMBER GPIO Pin to be chosen for interrupt generation [11:8] read-write PORT_NUMBER GPIO Port to be chosen for interrupt generation [13:12] read-write RESERVED2 Reserved2 [31:14] read-write GPIO_INTR_STATUS__n_ GPIO Interrupt Status Register 0x04 32 read-write 0x00000000 0x1F INTERRUPT_STATUS Gets set when interrupt is enabled and occurs. [0:0] read-write Disable Writing 0 has not effect 0 Enable When 1 is written it gets cleared. Also clears rise edge and fall edge status bits 1 RISE_EDGE_STATUS Gets set when rise edge is enabled and occurs. [1:1] read-write Disable Writing 0 has not effect 0 Enable When 1 is written it gets cleared. 1 FALL_EDGE_STATUS Gets set when Fall edge is enabled and occurs. [2:2] read-write Disable Writing 0 has not effect 0 Enable When 1 is written it gets cleared. 1 MASK_SET Mask set [3:3] write-only Disable On read, this bit should result it in 0 0 Enable When 1 is written mask bit will get set 1 MASK_CLEAR Mask Clear [4:4] write-only Disable On read, this bit should result it in 0 0 Enable When 1 is written mask bit gets cleared 1 RESERVED1 Reserved1 [31:5] read-write 4 0x08 GPIO_GRP_INTRn GPIO Group related registers (0-3) 0x1240 GPIO_GRP_INTR_CTRL_REG__n_ GPIO Interrupt 0 Control Register 0x00 32 read-write 0x00000010 0x1F AND_OR AND/OR [0:0] read-write Disable AND 0 Enable OR 1 LEVEL_EDGE Level/Edge [1:1] read-write Disable Level 0 Enable Edge 1 ENABLE_WAKEUP For wakeup generation, actual pin status has to be seen(before double ranking point) [2:2] read-write ENABLE_INTERRUPT Enable Interrupt [3:3] read-write Disable Disable 0 Enable Enable 1 MASK Mask [4:4] read-write Disable Mask 0 Enable unmask 1 RESERVED1 Reserved1 [31:5] read-write GPIO_GRP_INTR_STS__n_ GPIO Interrupt 0 Status Register 0x04 32 read-write 0x00000010 0x1B INTERRUPT_STATUS Interrupt status is available in this bit when interrupt is enabled and generated. When 1 is written, interrupt gets cleared. [0:0] read-write WAKEUP Double ranked version of wakeup. Gets set when wakeup is enabled and occurs. When 1 is written it gets cleared [1:1] read-only RESERVED1 Reserved1 [2:2] read-write MASK_SET Gives zero on read [3:3] read-write MASK_CLEAR Gives zero on read [4:4] read-write RESERVED2 Reserved2 [31:5] read-write SDIO_Slave 1.0 The Secure Digital I/O (SDIO) Slave module implements the functionality of the SDIO card based on the SDIO specifications version 2.0. 0x20200000 32 read-write 0 0x502 registers SDIO_INTR_FN1_REG SDIO Function1 Interrupt Enable Register 0x00 32 read-write SDIO_WR_INT_CLR This bit is used to enable CMD53 write interrupt. =1 Interrupt is enabled =0 - Interrupt is disabled [0:0] read-write SDIO_RD_INT_CLR This bit is used to enable CMD53 read interrupt [1:1] read-write SDIO_CSA_INT_CLR This bit is used to enable CMD53 CSA interrupt [2:2] read-write SDIO_CMD52_INT_CLR This bit is used to enable CMD52 interrupt [3:3] read-write SDIO_PWR_LEV_INT_CLR This bit is used to enable power level change interrupt [4:4] read-write SDIO_CRC_ERR_INT_CLR This bit is used to enable CRC error interrupt [5:5] read-write SDIO_ABORT_INT_CLR This bit is used to enable abort interrupt [6:6] read-write SDIO_TOUT_INT_CLR This bit is used to enable ?read FIFO wait time over? interrupt [7:7] read-write SDIO_WR_RDZ SDIO_WR_RDZ [8:8] read-write SDIO_CSA_ACCESS csa_window_access When set, indicates that current request is for CSA window register. This is only status signal [9:9] read-write RES reserved1 [31:10] read-write SDIO_INTR_FN1_ENABLE_REG SDIO Function1 Interrupt Enable Register 0x04 32 read-write SDIO_WR_INT_EN This bit is used to enable CMD53 write interrupt. [0:0] read-write SDIO_RD_INT_EN This bit is used to enable CMD53 read interrupt [1:1] read-write SDIO_CSA_INT_EN This bit is used to enable CMD53 CSA interrupt [2:2] read-write SDIO_CMD52_INT_EN This bit is used to enable CMD52 interrupt [3:3] read-write SDIO_PWR_LEV_INT_EN This bit is used to enable power level change interrupt [4:4] read-write SDIO_CRC_ERR_INT_EN This bit is used to enable CRC error interrupt [5:5] read-write SDIO_ABORT_INT_EN This bit is used to enable abort interrupt [6:6] read-write SDIO_TOUT_INT_EN This bit is used to enable ?read FIFO wait time over? interrupt [7:7] read-write RES reserved5 [31:8] read-write SDIO_INTR_FN1_MASK_REG SDIO Function1 Interrupt Mask Register 0x08 32 read-write SDIO_WR_INT_MSK This bit is used to mask CMD53 write interrupt [0:0] read-write SDIO_RD_INT_MSK This bit is used to mask CMD53 read interrupt [1:1] read-write SDIO_CSA_MSK This bit is used to mask CMD53 CSA interrupt.Setting this bit will mask the interrupt Clearing this bit has no effect [2:2] read-write SDIO_CMD52_MSK This bit is used to mask CMD52 interrupt [3:3] read-write SDIO_PWR_LEV_MSK This bit is used to mask power level change interrupt [4:4] read-write SDIO_CRC_ERR_MSK This bit is used to mask CRC error interrupt [5:5] read-write SDIO_ABORT_MSK This bit is used to mask abort interrupt Setting this bit will mask the interrupt Clearing this bit has no effect [6:6] read-write SDIO_TOUT_MSK This bit is used to mask read FIFO wait time over interrupt [7:7] read-write RES reserved5 [31:8] read-write SDIO_INTR_FN1_UNMASK_REG SDIO Function1 Interrupt UnMask Register 0x0C 32 read-write SDIO_WR_INT_UNMSK This bit is used to unmask CMD53 write interrupt [0:0] read-write SDIO_RD_INT_UNMSK This bit is used to unmask CMD53 read interrupt [1:1] read-write SDIO_CSA_UNMSK This bit is used to unmask CMD53 CSA interrupt.Setting this bit will mask the interrupt Clearing this bit has no effect [2:2] read-write SDIO_CMD52_UNMSK This bit is used to unmask CMD52 interrupt [3:3] read-write SDIO_PWR_LEV_UNMSK This bit is used to unmask power level change interrupt [4:4] read-write SDIO_CRC_ERR_UNMSK This bit is used to unmask CRC error interrupt [5:5] read-write SDIO_ABORT_UNMSK This bit is used to unmask abort interrupt Setting this bit will mask the interrupt Clearing this bit has no effect [6:6] read-write SDIO_TOUT_UNMSK This bit is used to unmask read FIFO wait time over interrupt [7:7] read-write RES reserved5 [31:8] read-write SDIO_BLK_LEN_REG SDIO Block Length Register 0x10 32 read-only SDIO_BLK_LEN Length of each block for the last received CMD53 [11:0] read-only RES reserved5 [31:12] read-only SDIO_BLK_CNT_REG SDIO Block Length Register 0x14 32 read-only SDIO_BLK_CNT Block count for the last received CMD53 [8:0] read-only RES reserved5 [31:9] read-only SDIO_ADDRESS_REG SDIO Address Register 0x18 32 read-only SDIO_ADDR Lower 16-bits of the 17-bit address field in the last received CMD53 [15:0] read-only RES reserved5 [31:16] read-only SDIO_CMD52_RDATA_REGISTER SDIO CMD52 Read data Register 0x1C 32 read-only RDATA Data to be given to host for CMD52 slave mode access read command has to written into this register [7:0] read-only RESERVED1 reserved1 [31:8] read-only SDIO_CMD52_WDATA_REGISTER SDIO CMD52 Write data Register 0x20 32 0XFF read-only WDATA Data from host in CMD52 slave mode access write command is available in this register [7:0] read-only RESERVED1 reserved1 [31:8] read-only SDIO_INTR_REG SDIO Interrupt Status Register 0x24 32 read-only SDIO_INT_ERROR Interrupt is pending because of error condition from any of the functions [0:0] read-only SDIO_INT_FN1 Interrupt is pending for function1 [1:1] read-only SDIO_INT_FN2 Interrupt is pending for function2 [2:2] read-only SDIO_INT_FN3 Interrupt is pending for function3 [3:3] read-only SDIO_INT_FN4 Interrupt is pending for function4 [4:4] read-only SDIO_INT_FN5 Interrupt is pending for function5 [5:5] read-only RESERVED1 reserved5 [31:6] read-only SDIO_INTR_FN_NUMBER_REG SDIO Interrupt Function Number Register 0x28 32 read-only SDIO_INTR_FN_NUM Indicates the function number to which interrupt is pending. [2:0] read-only RES reserved5 [31:3] read-only SDIO_FIFO_STATUS_REG SDIO FIFO Status Register 0x2C 32 read-only SDIO_WFIFO_FULL When set, indicates that WFIFO is full WFIFO is used in SDIO reads from host for sending data from AHB to Host [0:0] read-only SDIO_WFIFO_AFULL When set, indicates that WFIFO is almost full [1:1] read-only SDIO_RFIFO_EMPTY When set, indicates that RFIFO is empty RFIFO is used in SDIO writes from host for sending data from host to AHB [2:2] read-only SDIO_RFIFO_AEMPTY When set, indicates that RFIFO is almost empty [3:3] read-only SDIO_CURRENT_FN_NUM Indicates the function number of the last received command [6:4] read-only SDIO_BUS_CONTROL_STATE Indicates the function number of the last received command [11:7] read-only RES reserved5 [31:12] read-only SDIO_FIFO_OCC_REG SDIO FIFO Occupancy Register 0x30 32 read-only SDIO_WFIFO_OCC Indicates the occupancy level of the write FIFO [7:0] read-only SDIO_RFIFO_AVAIL Indicates the available space in the read FIFO [15:8] read-only RES reserved5 [31:16] read-only SDIO_HOST_INTR_SET_REG SDIO Host Interrupt Set Register 0x34 32 read-write SDIO_INTSET_FN2 This bit is used to raise an interrupt to host for function2. Setting this bit will raise the interrupt Clearing this bit has no effect [0:0] read-write SDIO_INTSET_FN3 This bit is used to raise an interrupt to host for function3. Setting this bit will raise the interrupt Clearing this bit has no effect [1:1] read-write SDIO_INTSET_FN4 This bit is used to raise an interrupt to host for function4. Setting this bit will raise the interrupt Clearing this bit has no effect [2:2] read-write SDIO_INTSET_FN5 This bit is used to raise an interrupt to host for function5. Setting this bit will raise the interrupt Clearing this bit has no effect [3:3] read-write RES reserved5 [31:4] read-write SDIO_HOST_INTR_CLEAR_REG SDIO Host Interrupt Clear Register 0x38 32 read-write SDIO_INTCLR_FN2 This bit is used to clear the interrupt to host for function2. Setting this bit will clear the interrupt Clearing this bit has no effect [0:0] read-write SDIO_INTCLR_FN3 This bit is used to clear the interrupt to host for function3. Setting this bit will clear the interrupt Clearing this bit has no effect [1:1] read-write SDIO_INTCLR_FN4 This bit is used to clear the interrupt to host for function4. Setting this bit will clear the interrupt Clearing this bit has no effectt [2:2] read-write SDIO_INTCLR_FN5 This bit is used to clear the interrupt to host for function5. Setting this bit will clear the interrupt Clearing this bit has no effect [3:3] read-write RES reserved5 [31:4] read-write 16 0x4 0-15 SDIO_RFIFO_DATA_REGn SDIO Read FIFO Data Register (0-15) 0x40 SDIO_RFIFO_DATA_REG_n_ SDIO Read FIFO Data Register 0x00 32 write-only 0x00000000 0xFFFFFFFF SDIO_RFIFO Data to be written into SDIO Read FIFO has to be written in this register. [31:0] write-only 16 0x4 0-15 SDIO_WFIFO_DATA_REGn SDIO Write FIFO Data Register (0-15) 0x80 SDIO_WFIFO_DATA_REG_n_ SDIO Write FIFO Data Register 0x00 32 read-only 0x00000000 0xFFFFFFFF SDIO_WFIFO SDIO Write FIFO data can be read through this register. [31:0] read-only SDIO_INTR_FN2_REG SDIO interrupt Function2 0xC0 32 read-write SDIO_WR_INT This bit is used to enable CMD53 write interrupt. =1 Interrupt is enabled =0 - Interrupt is disabled [0:0] read-write SDIO_RD_INT This bit is used to enable CMD53 read interrupt [1:1] read-write SDIO_CSA_INT This bit is used to enable CMD53 CSA interrupt [2:2] read-write SDIO_CMD52_INT This bit is used to enable CMD52 interrupt [3:3] read-write SDIO_PWR_LEV_INT This bit is used to enable power level change interrupt [4:4] read-write SDIO_CRC_ERR_INT This bit is used to enable CRC error interrupt [5:5] read-write SDIO_ABORT_INT This bit is used to enable abort interrupt [6:6] read-write SDIO_TOUT_INT This bit is used to enable ?read FIFO wait time over? interrupt [7:7] read-write SDIO_WR_RDz wr_rdz, This is not an interrupt signal. This is only status signal [8:8] read-write SDIO_CSA_ACCESS csa_window_access When set, indicates that current request is for CSA window register. This is only status signal [9:9] read-write RESERVED1 reserved1 [31:10] read-write SDIO_INTR_FN2_ENABLE_REG SDIO Function1 Interrupt Enable Register 0xC4 32 read-write SDIO_WR_INT_EN This bit is used to enable CMD53 write interrupt. [0:0] read-write SDIO_RD_INT_EN This bit is used to enable CMD53 read interrupt [1:1] read-write SDIO_CSA_INT_EN This bit is used to enable CMD53 CSA interrupt [2:2] read-write SDIO_CMD52_INT_EN This bit is used to enable CMD52 interrupt [3:3] read-write SDIO_PWR_LEV_INT_EN This bit is used to enable power level change interrupt [4:4] read-write SDIO_CRC_ERR_INT_EN This bit is used to enable CRC error interrupt [5:5] read-write SDIO_ABORT_INT_EN This bit is used to enable abort interrupt [6:6] read-write SDIO_TOUT_INT_EN This bit is used to enable ?read FIFO wait time over? interrupt [7:7] read-write RES reserved5 [31:8] read-write SDIO_INTR_FN2_MASK_REG SDIO Function2 Interrupt Mask Register 0xC8 32 read-write SDIO_WR_INT_MSK This bit is used to mask CMD53 write interrupt [0:0] read-write SDIO_RD_INT_MSK This bit is used to mask CMD53 read interrupt [1:1] read-write SDIO_CSA_MSK This bit is used to mask CMD53 CSA interrupt.Setting this bit will mask the interrupt Clearing this bit has no effect [2:2] read-write SDIO_CMD52_MSK This bit is used to mask CMD52 interrupt [3:3] read-write SDIO_PWR_LEV_MSK This bit is used to mask power level change interrupt [4:4] read-write SDIO_CRC_ERR_MSK This bit is used to mask CRC error interrupt [5:5] read-write SDIO_ABORT_MSK This bit is used to mask abort interrupt Setting this bit will mask the interrupt Clearing this bit has no effect [6:6] read-write SDIO_TOUT_MSK This bit is used to mask read FIFO wait time over interrupt [7:7] read-write RES reserved5 [31:8] read-write SDIO_INTR_FN2_UNMASK_REG SDIO Function2 Interrupt Mask Register 0xCC 32 read-write SDIO_WR_INT_UNMSK This bit is used to unmask CMD53 write interrupt [0:0] read-write SDIO_RD_INT_UNMSK This bit is used to unmask CMD53 read interrupt [1:1] read-write SDIO_CSA_UNMSK This bit is used to unmask CMD53 CSA interrupt.Setting this bit will mask the interrupt Clearing this bit has no effect [2:2] read-write SDIO_CMD52_UNMSK This bit is used to unmask CMD52 interrupt [3:3] read-write SDIO_PWR_LEV_UNMSK This bit is used to unmask power level change interrupt [4:4] read-write SDIO_CRC_ERR_UNMSK This bit is used to unmask CRC error interrupt [5:5] read-write SDIO_ABORT_UNMSK This bit is used to unmask abort interrupt Setting this bit will mask the interrupt Clearing this bit has no effect [6:6] read-write SDIO_TOUT_UNMSK This bit is used to unmask read FIFO wait time over interrupt [7:7] read-write RES reserved5 [31:8] read-write SDIO_INTR_FN3_REG SDIO interrupt Function3 0xD0 32 read-write SDIO_WR_INT This bit is used to enable CMD53 write interrupt. =1 Interrupt is enabled =0 - Interrupt is disabled [0:0] read-write SDIO_RD_INT This bit is used to enable CMD53 read interrupt [1:1] read-write SDIO_CSA_INT This bit is used to enable CMD53 CSA interrupt [2:2] read-write SDIO_CMD52_INT This bit is used to enable CMD52 interrupt [3:3] read-write SDIO_PWR_LEV_INT This bit is used to enable power level change interrupt [4:4] read-write SDIO_CRC_ERR_INT This bit is used to enable CRC error interrupt [5:5] read-write SDIO_ABORT_INT This bit is used to enable abort interrupt [6:6] read-write SDIO_RD_TOUT_INT This bit is used to enable ?read FIFO wait time over? interrupt [7:7] read-write SDIO_WR_RDz wr_rdz, This is not an interrupt signal. This is only status signal [8:8] read-write SDIO_CSA_ACCESS csa_window_access When set, indicates that current request is for CSA window register. This is only status signal [9:9] read-write RESERVED1 reserved1 [31:10] read-write SDIO_INTR_FN3_ENABLE_REG SDIO Function3 Interrupt Enable Register 0xD4 32 read-write SDIO_WR_INT_EN This bit is used to enable CMD53 write interrupt. [0:0] read-write SDIO_RD_INT_EN This bit is used to enable CMD53 read interrupt [1:1] read-write SDIO_CSA_INT_EN This bit is used to enable CMD53 CSA interrupt [2:2] read-write SDIO_CMD52_INT_EN This bit is used to enable CMD52 interrupt [3:3] read-write SDIO_PWR_LEV_INT_EN This bit is used to enable power level change interrupt [4:4] read-write SDIO_CRC_ERR_INT_EN This bit is used to enable CRC error interrupt [5:5] read-write SDIO_ABORT_INT_EN This bit is used to enable abort interrupt [6:6] read-write SDIO_TOUT_INT_EN This bit is used to enable ?read FIFO wait time over? interrupt [7:7] read-write RES reserved5 [31:8] read-write SDIO_INTR_FN3_MASK_REG SDIO Function3 Interrupt Mask Register 0xD8 32 read-write SDIO_WR_INT_MSK This bit is used to mask CMD53 write interrupt [0:0] read-write SDIO_RD_INT_MSK This bit is used to mask CMD53 read interrupt [1:1] read-write SDIO_CSA_MSK This bit is used to mask CMD53 CSA interrupt.Setting this bit will mask the interrupt Clearing this bit has no effect [2:2] read-write SDIO_CMD52_MSK This bit is used to mask CMD52 interrupt [3:3] read-write SDIO_PWR_LEV_MSK This bit is used to mask power level change interrupt [4:4] read-write SDIO_CRC_ERR_MSK This bit is used to mask CRC error interrupt [5:5] read-write SDIO_ABORT_MSK This bit is used to mask abort interrupt Setting this bit will mask the interrupt Clearing this bit has no effect [6:6] read-write SDIO_TOUT_MSK This bit is used to mask read FIFO wait time over interrupt [7:7] read-write RES reserved5 [31:8] read-write SDIO_INTR_FN3_UNMASK_REG SDIO Function3 Interrupt Mask Register 0xDC 32 read-write SDIO_WR_INT_UNMSK This bit is used to unmask CMD53 write interrupt [0:0] read-write SDIO_RD_INT_UNMSK This bit is used to unmask CMD53 read interrupt [1:1] read-write SDIO_CSA_UNMSK This bit is used to unmask CMD53 CSA interrupt.Setting this bit will mask the interrupt Clearing this bit has no effect [2:2] read-write SDIO_CMD52_UNMSK This bit is used to unmask CMD52 interrupt [3:3] read-write SDIO_PWR_LEV_UNMSK This bit is used to unmask power level change interrupt [4:4] read-write SDIO_CRC_ERR_UNMSK This bit is used to unmask CRC error interrupt [5:5] read-write SDIO_ABORT_UNMSK This bit is used to unmask abort interrupt Setting this bit will mask the interrupt Clearing this bit has no effect [6:6] read-write SDIO_TOUT_UNMSK This bit is used to unmask read FIFO wait time over interrupt [7:7] read-write RES reserved5 [31:8] read-write SDIO_INTR_FN4_REG SDIO interrupt Function4 0xE0 32 read-write SDIO_WR_INT This bit is used to enable CMD53 write interrupt. =1 Interrupt is enabled =0 - Interrupt is disabled [0:0] read-write SDIO_RD_INT This bit is used to enable CMD53 read interrupt [1:1] read-write SDIO_CSA_INT This bit is used to enable CMD53 CSA interrupt [2:2] read-write SDIO_CMD52_INT This bit is used to enable CMD52 interrupt [3:3] read-write SDIO_PWR_LEV_INT This bit is used to enable power level change interrupt [4:4] read-write SDIO_CRC_ERR_INT This bit is used to enable CRC error interrupt [5:5] read-write SDIO_ABORT_INT This bit is used to enable abort interrupt [6:6] read-write SDIO_RD_TOUT_INT This bit is used to enable ?read FIFO wait time over? interrupt [7:7] read-write SDIO_WR_RDz wr_rdz, This is not an interrupt signal. This is only status signal [8:8] read-write SDIO_CSA_ACCESS csa_window_access When set, indicates that current request is for CSA window register. This is only status signal [9:9] read-write RESERVED1 reserved1 [31:10] read-write SDIO_INTR_FN4_ENABLE_REG SDIO Function4 Interrupt Enable Register 0xE4 32 read-write SDIO_WR_INT_EN This bit is used to enable CMD53 write interrupt. [0:0] read-write SDIO_RD_INT_EN This bit is used to enable CMD53 read interrupt [1:1] read-write SDIO_CSA_INT_EN This bit is used to enable CMD53 CSA interrupt [2:2] read-write SDIO_CMD52_INT_EN This bit is used to enable CMD52 interrupt [3:3] read-write SDIO_PWR_LEV_INT_EN This bit is used to enable power level change interrupt [4:4] read-write SDIO_CRC_ERR_INT_EN This bit is used to enable CRC error interrupt [5:5] read-write SDIO_ABORT_INT_EN This bit is used to enable abort interrupt [6:6] read-write SDIO_TOUT_INT_EN This bit is used to enable ?read FIFO wait time over? interrupt [7:7] read-write RES reserved5 [31:8] read-write SDIO_INTR_FN4_MASK_REG SDIO Function4 Interrupt Mask Register 0xE8 32 read-write SDIO_WR_INT_MSK This bit is used to mask CMD53 write interrupt [0:0] read-write SDIO_RD_INT_MSK This bit is used to mask CMD53 read interrupt [1:1] read-write SDIO_CSA_MSK This bit is used to mask CMD53 CSA interrupt.Setting this bit will mask the interrupt Clearing this bit has no effect [2:2] read-write SDIO_CMD52_MSK This bit is used to mask CMD52 interrupt [3:3] read-write SDIO_PWR_LEV_MSK This bit is used to mask power level change interrupt [4:4] read-write SDIO_CRC_ERR_MSK This bit is used to mask CRC error interrupt [5:5] read-write SDIO_ABORT_MSK This bit is used to mask abort interrupt Setting this bit will mask the interrupt Clearing this bit has no effect [6:6] read-write SDIO_TOUT_MSK This bit is used to mask read FIFO wait time over interrupt [7:7] read-write RES reserved5 [31:8] read-write SDIO_INTR_FN4_UNMASK_REG SDIO Function4 Interrupt Mask Register 0xEC 32 read-write SDIO_WR_INT_UNMSK This bit is used to unmask CMD53 write interrupt [0:0] read-write SDIO_RD_INT_UNMSK This bit is used to unmask CMD53 read interrupt [1:1] read-write SDIO_CSA_UNMSK This bit is used to unmask CMD53 CSA interrupt.Setting this bit will mask the interrupt Clearing this bit has no effect [2:2] read-write SDIO_CMD52_UNMSK This bit is used to unmask CMD52 interrupt [3:3] read-write SDIO_PWR_LEV_UNMSK This bit is used to unmask power level change interrupt [4:4] read-write SDIO_CRC_ERR_UNMSK This bit is used to unmask CRC error interrupt [5:5] read-write SDIO_ABORT_UNMSK This bit is used to unmask abort interrupt Setting this bit will mask the interrupt Clearing this bit has no effect [6:6] read-write SDIO_TOUT_UNMSK This bit is used to unmask read FIFO wait time over interrupt [7:7] read-write RES reserved5 [31:8] read-write SDIO_INTR_FN5_REG SDIO interrupt Function5 Register 0xF0 32 read-write SDIO_WR_INT This bit is used to enable CMD53 write interrupt. =1 Interrupt is enabled =0 - Interrupt is disabled [0:0] read-write SDIO_RD_INT This bit is used to enable CMD53 read interrupt [1:1] read-write SDIO_CSA_INT This bit is used to enable CMD53 CSA interrupt [2:2] read-write SDIO_CMD52_INT This bit is used to enable CMD52 interrupt [3:3] read-write SDIO_PWR_LEV_INT This bit is used to enable power level change interrupt [4:4] read-write SDIO_CRC_ERR_INT This bit is used to enable CRC error interrupt [5:5] read-write SDIO_ABORT_INT This bit is used to enable abort interrupt [6:6] read-write SDIO_RD_TOUT_INT This bit is used to enable ?read FIFO wait time over? interrupt [7:7] read-write SDIO_WR_RDz wr_rdz, This is not an interrupt signal. This is only status signal [8:8] read-write SDIO_CSA_ACCESS csa_window_access When set, indicates that current request is for CSA window register. This is only status signal [9:9] read-write RESERVED1 reserved1 [31:10] read-write SDIO_INTR_FN5_ENABLE_REG SDIO Function5 Interrupt Enable Register 0xF4 32 read-write SDIO_WR_INT_EN This bit is used to enable CMD53 write interrupt. [0:0] read-write SDIO_RD_INT_EN This bit is used to enable CMD53 read interrupt [1:1] read-write SDIO_CSA_INT_EN This bit is used to enable CMD53 CSA interrupt [2:2] read-write SDIO_CMD52_INT_EN This bit is used to enable CMD52 interrupt [3:3] read-write SDIO_PWR_LEV_INT_EN This bit is used to enable power level change interrupt [4:4] read-write SDIO_CRC_ERR_INT_EN This bit is used to enable CRC error interrupt [5:5] read-write SDIO_ABORT_INT_EN This bit is used to enable abort interrupt [6:6] read-write SDIO_TOUT_INT_EN This bit is used to enable ?read FIFO wait time over? interrupt [7:7] read-write RES reserved5 [31:8] read-write SDIO_INTR_FN5_MASK_REG SDIO Function5 Interrupt Mask Register 0xF8 32 read-write SDIO_WR_INT_MSK This bit is used to mask CMD53 write interrupt [0:0] read-write SDIO_RD_INT_MSK This bit is used to mask CMD53 read interrupt [1:1] read-write SDIO_CSA_MSK This bit is used to mask CMD53 CSA interrupt.Setting this bit will mask the interrupt Clearing this bit has no effect [2:2] read-write SDIO_CMD52_MSK This bit is used to mask CMD52 interrupt [3:3] read-write SDIO_PWR_LEV_MSK This bit is used to mask power level change interrupt [4:4] read-write SDIO_CRC_ERR_MSK This bit is used to mask CRC error interrupt [5:5] read-write SDIO_ABORT_MSK This bit is used to mask abort interrupt Setting this bit will mask the interrupt Clearing this bit has no effect [6:6] read-write SDIO_TOUT_MSK This bit is used to mask read FIFO wait time over interrupt [7:7] read-write RES reserved5 [31:8] read-write SDIO_INTR_FN5_UNMASK_REG SDIO Function5 Interrupt Mask Register 0xFC 32 read-write SDIO_WR_INT_UNMSK This bit is used to unmask CMD53 write interrupt [0:0] read-write SDIO_RD_INT_UNMSK This bit is used to unmask CMD53 read interrupt [1:1] read-write SDIO_CSA_UNMSK This bit is used to unmask CMD53 CSA interrupt.Setting this bit will mask the interrupt Clearing this bit has no effect [2:2] read-write SDIO_CMD52_UNMSK This bit is used to unmask CMD52 interrupt [3:3] read-write SDIO_PWR_LEV_UNMSK This bit is used to unmask power level change interrupt [4:4] read-write SDIO_CRC_ERR_UNMSK This bit is used to unmask CRC error interrupt [5:5] read-write SDIO_ABORT_UNMSK This bit is used to unmask abort interrupt Setting this bit will mask the interrupt Clearing this bit has no effect [6:6] read-write SDIO_TOUT_UNMSK This bit is used to unmask read FIFO wait time over interrupt [7:7] read-write RES reserved5 [31:8] read-write SDIO_ERROR_COND_CTRL_ENABLE_REG SDIO error condition Control enable register 0x100 32 read-write SDIO_CRC_EN When set, stops the DMA from doing data accesses till CRC error interrupt is cleared [0:0] read-write SDIO_ABORT_EN When set, stops the DMA from doing data accesses till ABORT interrupt is cleared [1:1] read-write SDIO_SPI_RD_DATA_ERROR_EN When set, stops the DMA from doing data accesses till read data error interrupt is cleared in SPI mode [2:2] read-write RESERVED1 reserved1 [31:3] read-write SDIO_ERROR_COND_BLK_CNT SDIO error condition block count register 0x104 32 read-write SDIO_ERROR_BYTE_CNT Indicates byte count when one of the error condition occurred [11:0] read-write RESERVED1 RESERVED1 [15:12] read-write SDIO_ERROR_BLK_CNT Indicates block count when one of error condition occurred [22:16] read-write RESERVED2 RESERVED2 [31:23] read-write SDIO_BOOT_CONFIG_VALS_0_REG SDIO Boot Config Values Register 0 0x108 32 0xFF800009 read-only OCR_R Operating conditions. The value written by bootloader can be read here. [7:0] read-only CSA_MSBYTE MS byre of CSA address. Lower 24 bits of CSA will come through SDIO CSA registers. Whenever CSA access is done, 32-bit address will be prepared using these fields. [31:8] read-only SDIO_BOOT_CONFIG_VALS_1_REG SDIO Boot Config Values Register 1 0x10C 32 0X00000001 read-only NO_OF_IO_FUNCTIONS Indicates number functions supported. The value written by bootloader can be read here. [2:0] read-only COMBOCARD When set, combo mode will be enabled. [3:3] read-only SDMEM_IGNOTRE_SDMEM_PRESENT When set, sdmem_present signal, coming from GPIO, will be ignored. [4:4] read-only SDMEM_DRIVE_HIZ_MB_READ When set, High will be driven in the second cycle of interrupt period during sd memory mb read transfer [5:5] read-only SDMEM_DISABLE_INTERRUPT_MB_READ When set, interrupt will be not be driven during sd memory mb read transfer [6:6] read-only IGNORE_DISABLE_HS if ignore_disable_hs is set, sdmem_disable_high_speed_switching coming from combo mode module is ignored [7:7] read-only RESERVED2 RESERVED2 [31:8] read-only HSPI 1.0 The SPI Interface is a full duplex serial host interface, which supports 8-bit and 32-bit data granularity. It also supports gated mode of SPI clock and both the low and the high frequency modes 0x20200000 32 read-write 0 0x802 registers SPI_HOST_INTR SPI Host interupt resgister. 0x00 8 read-write 0x00 SPI_HOST_INTR These bits indicate the interrupt vector value coming from system side. [7:0] read-write SPI_RFIFO_START SPI FIFO start Level Register. 0x02 8 read-write 0x10 SPI_RFIFO_ST These bits indicate the interrupt vector value coming from system side. [7:0] read-write SPI_RFIFO_AFULL_LEV SPI RFIFO AFULL Level Register. 0x04 8 read-write 0x8 SPI_RFIFO_AFULL_LEV These bits are used to program the FIFO occupancy level to trigger the Almost Full indication. [7:0] read-write SPI_RFIFO_AEMPTY_LEV SPI WFIFO Almost Empty Register. 0x06 8 read-write 0x8 SPI_RFIFO_AEMPTY_LEV These bits are used to program the occupancy level to trigger the Almost Empty indication. [7:0] read-write SPI_MODE SPI Mode Register. 0x08 8 read-write 0x8 SPI_OP_MODE This bit is used to program the mode of working of SPI Interface. [0:0] read-write SPI_FIX_EN This bit is used to enable the fix made for bus_ctrl_busy being asserted when success_state is being asserted getting deasserted when FSM has decided to move to BUSY_STATE or not. [1:1] read-write VHS_EN This bit is used to enable Very high speed mode (120Mhz). [2:2] read-write BYPASS_INIT This bit is used to bypass the SPI initialization.0 - Doesn't bypass,1 - bypasses SPI initialization [3:3] read-write RESERVED1 reserved1 [7:4] read-write SPI_INTR_STATUS SPI interrupt status register. 0x0A 16 read-write 0x0 SPI_WR_REQ Write request received. [0:0] read-write SPI_RD_REQ Read request received. [1:1] read-write SPI_CS_DEASSERT SPI chip deassert interrupt. [2:2] read-write RESERVED1 reserved1 [15:3] read-write SPI_INTR_EN SPI interrupt enable register. 0x0C 16 read-write 0x0 SPI_WR_INT_EN This bit is used to enable the write interrupt. [0:0] read-write SPI_RD_INT_EN This bit is used to enable the read interrupt. [1:1] read-write SPI_CS_DEASSERT_INT_EN This bit is used to enable the interrupt due to wrong deassertion of CS. [2:2] read-write RESERVED1 reserved1 [15:3] read-write SPI_INTR_MASK SPI interrupt Mask register 0x0E 16 read-write 0x0 SPI_WR_INTR_MSK This bit is used to mask the write interrupt. [0:0] read-write SPI_RD_INTR_MSK This bit is used to mask the read interrupt. [1:1] read-write SPI_CS_DEASSERT_INT_MSK This bit is used to mask the CS deassertion interrupt. [2:2] read-write RESERVED1 reserved1 [15:3] read-write SPI_INTR_UNMASK SPI interrupt unmask register 0x10 16 read-write 0x0 SPI_WR_INT_UNMASK This bit is used to unmask the write interrupt. [0:0] read-write SPI_RD_INTR_UNMSK This bit is used to unmask the read interrupt. [1:1] read-write SPI_CS_DEASSERT_INT_UNMSK This bit is used to unmask the CS deassertion interrupt. [2:2] read-write RESERVED1 reserved1 [15:3] read-write SPI_LENGTH SPI Length Register 0x12 16 read-only 0x0 SPI_LEN These bit indicate the length of the transfer as transmitted in the Commands C3 and C4. [15:0] read-only SPI_COMMAND SPI Command Register 0x14 16 read-only 0x0 SPI_C1 These bits store the received command C1. [7:0] read-only SPI_C2 These bits store the received command C2. [15:8] read-only SPI_DEV_ID SPI Device ID Register 0x16 16 read-only 0x0 SPI_DEVID These bits store the Device ID information. [15:0] read-only SPI_VERSION SPI Device ID Register 0x18 16 read-only 0x0 SPI_VERNO These bits store the version number. [7:0] read-only RESERVED1 reserved1 [15:8] read-only SPI_STATUS SPI Status Register 0x1A 16 read-only 0xC SPI_RFIFO_FULL This bit indicates if the read FIFO is almost full. [0:0] read-only SPI_RFIFO_AFULL This bit indicates if the read FIFO is almost full. [1:1] read-only SPI_WFIFO_EMPTY This bit indicates if write FIFO is empty. [2:2] read-only SPI_WFIFO_AEMPTY This bit indicates if write FIFO is almost empty. [3:3] read-only SPI_RFIFO_EMPTY This bit indicates if read FIFO is empty (Read from SOC to host). [4:4] read-only SPI_RFIFO_AEMPTY This bit indicates if read FIFO is empty (Read from SOC to host). [5:5] read-only SPI_WFIFO_FULL This bit indicates if write FIFO is full (Write from Host to SOC). [6:6] read-only SPI_WFIFO_AFULL This bit indicates if write FIFO is full (Write from Host to SOC). [7:7] read-only RESERVED1 reserved1 [15:8] read-only SPI_BC_STATE SPI Bus Controller State Register 0x1C 16 read-only 0x0 SPI_BC These bits indicate the Bus Controller FSM state. [13:0] read-only RESERVED1 reserved1 [15:14] read-only SPI_RFIFO_DATA SPI RFIFO Data Register 0x380 32 read-only 0x0 SPI_RFIFO These bits store the data received from the host [31:0] read-only SPI_WFIFO_DATA SPI WFIFO Data Register 0x3C0 32 write-only 0x0 SPI_WFIFO These bits are used to write, the data to be sent to the host. [31:0] write-only SPI_SYS_RESET_REQ SPI SYS Reset Req Register 0x7C 16 read-write 0x0 SPI_SYS_RESET_REQ When set generates system reset request to reset controller. This gets reset once, reset controller generates reset. Host should not reset this bit. With this reset request, reset controller generates non por reset. [0:0] read-write RESERVED1 reserved1 [15:1] read-write SPI_WAKE_UP SPI Wakeup Register 0x7E 16 read-write 0x0 SPI_WAKEUP Wakeup Interrupt,Interrupt for waking up the system from Deep Sleep. [0:0] read-write SPI_DEEP_SLEEP_ST Deep Sleep Start,Indicates the device to enter Deep Sleep state for maximum power save. [1:1] read-write RESERVED1 reserved1 [15:2] read-write M4CLK 1.0 MCU HP (High Performance) domain contains the Cortex-M4F Processor, FPU, Debugger, MCU High Speed Interfaces, MCU HP Peripherals, MCU HP DMA and MCU/SZP shareable Interfaces M4CLK 0x46000000 32 read-write 0x00 0x88 registers CLK_ENABLE_SET_REG1 Clock Enable Set Register 1 0x0 32 read-write 0x00002000 USART1_PCLK_ENABLE_b Static Clock gating Enable for usart1 pclk1'b1 => Clock is enabled 1'b0 => Invalid [0:0] read-write USART1_SCLK_ENABLE_b Static Clock gating Enable for usart1 sclk1'b1 => Clock is enabled 1'b0 => Invalid [1:1] read-write USART2_PCLK_ENABLE_b Static Clock gating Enable for usart2 pclk1'b1 => Clock is enabled 1'b0 => Invalid [2:2] read-write USART2_SCLK_ENABLE_b Static Clock gating Enable for usart2 sclk1'b1 => Clock is enabled 1'b0 => Invalid [3:3] read-write Reserved1 It is recommended to write these bits to 0. [8:4] read-write CT_CLK_ENABLE_b Static Clock gating Enable for sct clk1'b1 => Clock is enabled 1'b0 => Invalid. [9:9] read-write CT_PCLK_ENABLE_b Static Clock gating Enable for sct pclk1'b1 => Clock is enabled 1'b0 => Invalid. [10:10] read-write ICACHE_CLK_ENABLE_b Static Clock gating Enable for icache clk1'b1 => Clock is enabled 1'b0 => Invalid. [11:11] read-write ICACHE_CLK_2X_ENABLE_b Static Clock gating Enable for icache 2x clk1'b1 => Clock is enabled 1'b0 => Invalid. [12:12] read-write RPDMA_HCLK_ENABLE_b Static Clock gating Enable for rpdma hclk1'b1 => Clock is enabled 1'b0 => Invalid. [13:13] read-write SOC_PLL_SPI_CLK_ENABLE_b Static Clock gating Enable for soc pll spi clk1'b1 => Clock is enabled 1'b0 => Invalid. [14:14] read-write Reserved2 It is recommended to write these bits to 0. [15:15] read-write IID_CLK_ENABLE_b Static Clock gating Enable for iid clk1'b1 => Clock is enabled 1'b0 => Invalid. [16:16] read-write SDIO_SYS_HCLK_ENABLE_b Static Clock gating Enable for sdio sys hclk1'b1 => Clock is enabled 1'b0 => Invalid [17:17] read-write CRC_CLK_ENABLE_b Static Clock gating Enable for crc clk1'b1 => Clock is enabled 1'b0 => Invalid [18:18] read-write Reserved3 It is recommended to write these bits to 0. [21:19] read-write HWRNG_PCLK_ENABLE_b Static Clock gating Enable for HWRNG pclk1'b1 => Clock is enabled 1'b0 => Invalid. [22:22] read-write GNSS_MEM_CLK_ENABLE_b Static Clock gating Enable for GNSS mem clk1'b1 => Clock is enabled 1'b0 => Invalid [23:23] read-write Reserved4 It is recommended to write these bits to 0. [26:24] read-write MASK_HOST_CLK_WAIT_FIX_b This bit decides whether to wait for a fixed number of xtal clock cycles(based on mask31_host_clk_cnt) or wait for a internally generated signal to come out of WAIT state in host mux FSM 1'b1 => Wait for fixed number of xtal clk cycles 1'b0 => Invalid This bit along with mask_host_clk_available_fix and mask31_host_clk_cnt are to take care in case of any bugs. [27:27] read-write MASK31_HOST_CLK_CNT_b When mask_host_clk_wait_fix is 1'b1, this bit decides whether to count for 32 0r 16 xtal clock cycles to come out of WAIT state in host mux FSM 1'b1 => Wait for 32 clock cycles 1'b0 => Invalid This bit along with mask_host_clk_available_fix and mask_host_clk_wait_fix are to take care in case of any bugs. [28:28] read-write Reserved5 It is recommended to write these bits to 0. [29:29] read-write MASK_HOST_CLK_AVAILABLE_FIX_b This bit decides whether to consider negedge of host_clk_available in the generation of clock enable for host_clk gate in host mux 1'b1 => Don't consider 1'b0 => Invalid This bit along with mask_host_clk_wait_fix and mask31_host_clk_cnt are to take care in case of any bugs. [30:30] read-write ULPSS_CLK_ENABLE_b Static Clock gating Enable for m4 soc_clk to ulpss1'b1 => Clock is enabled 1'b0 => Invalid. [31:31] read-write CLK_ENABLE_CLEAR_REG1 Clock Enable Clear Register 1 0x4 32 read-write 0x00002000 USART1_PCLK_ENABLE_b Static Clock Clear for usart1 pclk1'b1 => Clock is Clear 1'b0 => Invalid [0:0] read-write USART1_SCLK_ENABLE_b Static Clock Clear for usart1 sclk1'b1 => Clock is Clear 1'b0 => Invalid [1:1] read-write USART2_PCLK_ENABLE_b Static Clock Clear for usart2 pclk 1'b1 => Clock is Clear 1'b0 => Invalid [2:2] read-write USART2_SCLK_ENABLE_b Static Clock Clear for usart2 sclk1'b1 => Clock is Clear 1'b0 => Invalid [3:3] read-write Reserved1 It is recommended to write these bits to 0. [8:4] read-write CT_CLK_ENABLE_b Static Clock Clear for sct clk1'b1 => Clock is Clear 1'b0 => Invalid. [9:9] read-write CT_PCLK_ENABLE_b Static Clock Clear for sct pclk1'b1 => Clock is Clear 1'b0 => Invalid. [10:10] read-write ICACHE_CLK_ENABLE_b Static Clock Clear for icache clk1'b1 => Clock is Clear 1'b0 => Invalid. [11:11] read-write ICACHE_CLK_2X_ENABLE_b Static Clock Clear for icache 2x clk1'b1 => Clock is Clear 1'b0 => Invalid. [12:12] read-write RPDMA_HCLK_ENABLE_b Static Clock Clear for rpdma hclk1'b1 => Clock is Clear 1'b0 => Invalid. [13:13] read-write SOC_PLL_SPI_CLK_ENABLE_b Static Clock Clear for soc pll spi clk1'b1 => Clock is Clear 1'b0 => Invalid. [14:14] read-write Reserved2 It is recommended to write these bits to 0. [15:15] read-write IID_CLK_ENABLE_b Static Clock Clear for iid clk1'b1 => Clock is Clear 1'b0 => Invalid. [16:16] read-write SDIO_SYS_HCLK_ENABLE_b Static Clock Clear for sdio sys hclk1'b1 => Clock is Clear 1'b0 => Invalid [17:17] read-write CRC_CLK_ENABLE_b Static Clock Clear for crc clk1'b1 => Clock is Clear 1'b0 => Invalid [18:18] read-write Reserved3 It is recommended to write these bits to 0. [21:19] read-write HWRNG_PCLK_ENABLE_b Static Clock Clear for HWRNG pclk1'b1 => Clock is Clear 1'b0 => Invalid. [22:22] read-write GNSS_MEM_CLK_ENABLE_b Static Clock Clear for GNSS mem clk1'b1 => Clock is Clear 1'b0 => Invalid [23:23] read-write Reserved4 It is recommended to write these bits to 0. [26:24] read-write MASK_HOST_CLK_WAIT_FIX_b This bit decides whether to wait for a fixed number of xtal clock cycles(based on mask31_host_clk_cnt) or wait for a internally generated signal to come out of WAIT state in host mux FSM 1'b1 => Wait for fixed number of xtal clk cycles 1'b0 => Invalid This bit along with mask_host_clk_available_fix and mask31_host_clk_cnt are to take care in case of any bugs. [27:27] read-write MASK31_HOST_CLK_CNT_b When mask_host_clk_wait_fix is 1'b1, this bit decides whether to count for 32 0r 16 xtal clock cycles to come out of WAIT state in host mux FSM 1'b1 => Wait for 32 clock cycles 1'b0 => Invalid This bit along with mask_host_clk_available_fix and mask_host_clk_wait_fix are to take care in case of any bugs. [28:28] read-write Reserved5 It is recommended to write these bits to 0. [29:29] read-write MASK_HOST_CLK_AVAILABLE_FIX_b This bit decides whether to consider negedge of host_clk_available in the generation of clock enable for host_clk gate in host mux 1'b1 => Don't consider 1'b0 => Invalid This bit along with mask_host_clk_wait_fix and mask31_host_clk_cnt are to take care in case of any bugs. [30:30] read-write ULPSS_CLK_ENABLE_b Static Clock gating Enable for m4 soc_clk to ulpss1'b1 => Clock is enabled 1'b0 => Invalid. [31:31] read-write CLK_ENABLE_SET_REG2 Clock Enable Set Register 2 0x8 32 read-write 0x00001800 GEN_SPI_MST1_HCLK_ENABLE_b Static Clock gating Enable for gen spi master1 hclk 1'b1 => Clock is enabled 1'b0 => Invalid [0:0] read-write Reserved1 It is recommended to write these bits to 0. [5:1] read-write UDMA_HCLK_ENABLE_b Static Clock gating Enable for udma hclk 1'b1 => Clock is enabled 1'b0 => Invalid. [6:6] read-write I2C_BUS_CLK_ENABLE_b Static Clock gating Enable for i2c-1 bus clk1'b1 => Clock is enabled 1'b0 => Invalid. [7:7] read-write I2C_2_BUS_CLK_ENABLE_b Static Clock gating Enable for i2c-2 bus clk 1'b1 => Clock is enabled 1'b0 => Invalid. [8:8] read-write SSI_SLV_PCLK_ENABLE_b Static Clock gating Enable for ssi slave pclk 1'b1 => Clock is enabled 1'b0 => Invalid. [9:9] read-write SSI_SLV_SCLK_ENABLE_b Static Clock gating Enable for ssi slave sclk 1'b1 => Clock is enabled 1'b0 => Invalid. [10:10] read-write QSPI_CLK_ENABLE_b Static Clock gating Enable for qspi clk 1'b1 => Clock is enabled 1'b0 => Invalid. [11:11] read-write QSPI_HCLK_ENABLE_b Static Clock gating Enable for qspi hclk 1'b1 => Clock is enabled 1'b0 => Invalid. [12:12] read-write I2SM_SCLK_ENABLE_b Static Clock gating Enable for sclk of I2S at Root Clock generation 1'b1 => Clock is enabled 1'b0 => Invalid. [13:13] read-write I2SM_INTF_SCLK_ENABLE_b Static Clock gating Enable for i2s interface sclk 1'b1 => Clock is enabled 1'b0 => Invalid. [14:14] read-write I2SM_PCLK_ENABLE_b Static Clock gating Enable for i2s master pclk 1'b1 => Clock is enabled 1'b0 => Invalid. [15:15] read-write Reserved2 It is recommended to write these bits to 0. [16:16] read-write QE_PCLK_ENABLE_b Static Clock gating Enable for qe pclk 1'b1 => Clock is enabled 1'b0 => Invalid. [17:17] read-write MCPWM_PCLK_ENABLE_b Static Clock gating Enable for mcpwm pclk 1'b1 => Clock is enabled 1'b0 => Invalid. [18:18] read-write Reserved3 It is recommended to write these bits to 0. [19:19] read-write SGPIO_PCLK_ENABLE_b Static Clock gating Enable for sgpio pclk 1'b1 => Clock is enabled 1'b0 => Invalid. [20:20] read-write EGPIO_PCLK_ENABLE_b Static Clock gating Enable for egpio pclk 1'b1 => Clock is enabled 1'b0 => Invalid. [21:21] read-write ARM_CLK_ENABLE_b Static Clock gating Enable for arm clk 1'b1 => Clock is enabled 1'b0 => Invalid. [22:22] read-write SSI_MST_PCLK_ENABLE_b Static Clock gating Enable for ssi master pclk 1'b1 => Clock is enabled 1'b0 => Invalid. [23:23] read-write SSI_MST_SCLK_ENABLE_b Static Clock gating Enable for ssi master sclk 1'b1 => Clock is enabled 1'b0 => Invalid. [24:24] read-write Reserved4 It is recommended to write these bits to 0. [25:25] read-write MEM_CLK_ULP_ENABLE_b Static Clock gating Enable for mem ulp clk 1'b1 => Clock is enabled 1'b0 => Invalid. [26:26] read-write ROM_CLK_ENABLE_b Static Clock gating Enable for rom clk 1'b1 => Clock is enabled 1'b0 => Invalid. [27:27] read-write PLL_INTF_CLK_ENABLE_b Static Clock gating Enable for pll intf clk 1'b1 => Clock is enabled 1'b0 => Invalid. [28:28] read-write Reserved5 It is recommended to write these bits to 0. [31:29] read-write CLK_ENABLE_CLEAR_REG2 Clock Enable Clear Register 2 0xC 32 read-write 0x00001800 GEN_SPI_MST1_HCLK_ENABLE_b Static Clock Clear for gen spi master1 hclk 1'b1 => Clock is Clear 1'b0 => Invalid [0:0] read-write Reserved1 It is recommended to write these bits to 0. [5:1] read-write UDMA_HCLK_ENABLE_b Static Clock Clear for udma hclk 1'b1 => Clock is Clear 1'b0 => Invalid. [6:6] read-write I2C_BUS_CLK_ENABLE_b Static Clock Clear for i2c-1 bus clk1'b1 => Clock is Clear 1'b0 => Invalid. [7:7] read-write I2C_2_BUS_CLK_ENABLE_b Static Clock Clear for i2c-2 bus clk 1'b1 => Clock is Clear 1'b0 => Invalid. [8:8] read-write SSI_SLV_PCLK_ENABLE_b Static Clock Clear for ssi slave pclk 1'b1 => Clock is Clear 1'b0 => Invalid. [9:9] read-write SSI_SLV_SCLK_ENABLE_b Static Clock Clear for ssi slave sclk 1'b1 => Clock is Clear 1'b0 => Invalid. [10:10] read-write QSPI_CLK_ENABLE_b Static Clock Clear for qspi clk 1'b1 => Clock is Clear 1'b0 => Invalid. [11:11] read-write QSPI_HCLK_ENABLE_b Static Clock Clear for qspi hclk 1'b1 => Clock is Clear 1'b0 => Invalid. [12:12] read-write I2SM_SCLK_ENABLE_b Static Clock Clear for sclk of I2S at Root Clock generation 1'b1 => Clock is Clear 1'b0 => Invalid. [13:13] read-write I2SM_INTF_SCLK_ENABLE_b Static Clock Clear for i2s interface sclk 1'b1 => Clock is Clear 1'b0 => Invalid. [14:14] read-write I2SM_PCLK_ENABLE_b Static Clock Clear for i2s master pclk 1'b1 => Clock is Clear 1'b0 => Invalid. [15:15] read-write Reserved2 It is recommended to write these bits to 0. [16:16] read-write QE_PCLK_ENABLE_b Static Clock Clear for qe pclk 1'b1 => Clock is Clear 1'b0 => Invalid. [17:17] read-write MCPWM_PCLK_ENABLE_b Static Clock Clear for mcpwm pclk 1'b1 => Clock is Clear 1'b0 => Invalid. [18:18] read-write Reserved3 It is recommended to write these bits to 0. [19:19] read-write SGPIO_PCLK_ENABLE_b Static Clock Clear for sgpio pclk 1'b1 => Clock is Clear 1'b0 => Invalid. [20:20] read-write EGPIO_PCLK_ENABLE_b Static Clock Clear for egpio pclk 1'b1 => Clock is Clear 1'b0 => Invalid. [21:21] read-write ARM_CLK_ENABLE_b Static Clock Clear for arm clk 1'b1 => Clock is Clear 1'b0 => Invalid. [22:22] read-write SSI_MST_PCLK_ENABLE_b Static Clock Clear for ssi master pclk 1'b1 => Clock is Clear 1'b0 => Invalid. [23:23] read-write SSI_MST_SCLK_ENABLE_b Static Clock Clear for ssi master sclk 1'b1 => Clock is Clear 1'b0 => Invalid. [24:24] read-write Reserved4 It is recommended to write these bits to 0. [25:25] read-write MEM_CLK_ULP_ENABLE_b Static Clock Clear for mem ulp clk 1'b1 => Clock is Clear 1'b0 => Invalid. [26:26] read-write ROM_CLK_ENABLE_b Static Clock Clear for rom clk 1'b1 => Clock is Clear 1'b0 => Invalid. [27:27] read-write PLL_INTF_CLK_ENABLE_b Static Clock Clear for pll intf clk 1'b1 => Clock is Clear 1'b0 => Invalid. [28:28] read-write Reserved5 It is recommended to write these bits to 0. [31:29] read-write CLK_ENABLE_SET_REG3 Clock Enable Set Register 3 0x10 32 read-write 0x08E02022 BUS_CLK_ENABLE_b Static Clock gating Enable for bus clk 1'b1 => Clock is enabled 1'b0 => Invalid [0:0] read-write M4_CORE_CLK_ENABLE_b Static Clock gating Enable for M4 Core clk 1'b1 => Clock is enabled 1'b0 => Invalid. [1:1] read-write CM_BUS_CLK_ENABLE_b Static Clock gating Enable for cm bus clk1'b1 => Clock is enabled1'b0 => Invalid. [2:2] read-write Reserved1 It is recommended to write these bits to 0. [3:3] read-write MISC_CONFIG_PCLK_ENABLE_b Static Clock gating Enable for misc config regs clk 1'b1 => Clock is enabled 1'b0 => Invalid. [4:4] read-write EFUSE_CLK_ENABLE_b Static Clock gating Enable for efuse clk 1'b1 => Clock is enabled 1'b0 => Invalid. [5:5] read-write ICM_CLK_ENABLE_b Static Clock gating Enable for icm clk 1'b1 => Clock is enabled 1'b0 => Invalid. [6:6] read-write Reserved2 It is recommended to write these bits to 0. [12:7] read-write QSPI_CLK_ONEHOT_ENABLE_b Static Clock gating Enable for QSPI clock generated from the dynamic mux 1b1 - Clock is enabled 1b0 - Invalid. [13:13] read-write QSPI_M4_SOC_SYNC_b Specifies whether QSPI clock is in sync with Soc clock. Before enabling this make sure that qspi_clk_onehot_enable is 1b0 to enable glitch free switching 1b1 - QSPI clock is in sync with M4 clock 1b0 - Invalid. [14:14] read-write Reserved3 It is recommended to write these bits to 0. [15:15] read-write EGPIO_CLK_ENABLE_b Static Clock gating enable for Enhanced-GPIO 1b1 - Clock is enabled 1b0 - Invalid. [16:16] read-write I2C_CLK_ENABLE_b Static Clock gating enable for I2C-1 Module 1b1 - Clock is enabled 1b0 - Invalid. [17:17] read-write I2C_2_CLK_ENABLE_b Static Clock gating enable for I2C-2 Module 1b1 - Clock is enabled 1b0 - Invalid. [18:18] read-write EFUSE_PCLK_ENABLE_b Static Clock gating enable for EFUSE APB Interface 1b1 - Clock is enabled 1b0 - Invalid. [19:19] read-write SGPIO_CLK_ENABLE_b Static Clock gating enable for SIO Module 1b1 - Clock is enabled 1b0 - Invalid. [20:20] read-write TASS_M4SS_64K_SWITCH_CLK_ENABLE_b Unused. [21:21] read-write TASS_M4SS_128K_SWITCH_CLK_ENABLE_b Unused. [22:22] read-write TASS_M4SS_SDIO_SWITCH_CLK_ENABLE_b Unused. [23:23] read-write Reserved4 It is recommended to write these bits to 0. [24:24] read-write ROM_MISC_STATIC_ENABLE_b Static Clock gating enable for rom ahb Clock 1b1 - Clock is enabled 1b0 - Invalid. [25:25] read-write M4_SOC_CLK_FOR_OTHER_ENABLE_b Static Clock gating enable for M4-SOC Other Clock 1b1 - Clock is enabled 1b0 - Invalid. [26:26] read-write ICACHE_ENABLE_b Static Clock gating enable for Icache. This has to be enable for Icache operations. 1b1 - Clock is enabled 1b0 - Invalid. [27:27] read-write Reserved5 It is recommended to write these bits to 0. [31:28] read-write CLK_ENABLE_CLEAR_REG3 Clock Enable Clear Register 3 0x14 32 read-write 0x08E02022 BUS_CLK_ENABLE_b Static Clock Clear for bus clk 1'b1 => Clock is Clear 1'b0 => Invalid [0:0] read-write M4_CORE_CLK_ENABLE_b Static Clock Clear for M4 Core clk 1'b1 => Clock is Clear 1'b0 => Invalid. [1:1] read-write CM_BUS_CLK_ENABLE_b Static Clock gating Enable for cm bus clk1'b1 => Clock is enabled1'b0 => Invalid. [2:2] read-write Reserved1 It is recommended to write these bits to 0. [3:3] read-write MISC_CONFIG_PCLK_ENABLE_b Static Clock Clear for misc config regs clk 1'b1 => Clock is Clear 1'b0 => Invalid. [4:4] read-write EFUSE_CLK_ENABLE_b Static Clock Clear for efuse clk 1'b1 => Clock is Clear 1'b0 => Invalid. [5:5] read-write ICM_CLK_ENABLE_b Static Clock Clear for icm clk 1'b1 => Clock is Clear 1'b0 => Invalid. [6:6] read-write Reserved2 It is recommended to write these bits to 0. [12:7] read-write QSPI_CLK_ONEHOT_ENABLE_b Static Clock Clear for QSPI clock generated from the dynamic mux 1b1 - Clock is Gated 1b0 - Invalid. [13:13] read-write QSPI_M4_SOC_SYNC_b Specifies whether QSPI clock is in sync with Soc clock. Before enabling this make sure that qspi_clk_onehot_enable is 1b0 to enable glitch free switching 1b1 - QSPI clock is in sync with M4 clock 1b0 - Invalid. [14:14] read-write Reserved3 It is recommended to write these bits to 0. [15:15] read-write EGPIO_CLK_ENABLE_b Static Clock Disable for Enhanced-GPIO 1b1 - Clock is Disable 1b0 - Invalid. [16:16] read-write I2C_CLK_ENABLE_b Static Clock Disable for I2C-1 Module 1b1 - Clock is Disable 1b0 - Invalid. [17:17] read-write I2C_2_CLK_ENABLE_b Static Clock Disable for I2C-2 Module 1b1 - Clock is Disable 1b0 - Invalid. [18:18] read-write EFUSE_PCLK_ENABLE_b Static Clock Disable for EFUSE APB Interface 1b1 - Clock is Disable 1b0 - Invalid. [19:19] read-write SGPIO_CLK_ENABLE_b Static Clock gating enable for SIO Module 1b1 - Clock is enabled 1b0 - Invalid. [20:20] read-write TASS_M4SS_64K_SWITCH_CLK_ENABLE_b Unused. [21:21] read-write TASS_M4SS_128K_SWITCH_CLK_ENABLE_b Unused. [22:22] read-write TASS_M4SS_SDIO_SWITCH_CLK_ENABLE_b Unused. [23:23] read-write Reserved4 It is recommended to write these bits to 0. [24:24] read-write ROM_MISC_STATIC_ENABLE_b Static Clock Disable for rom ahb Clock 1b1 - Clock is Disable 1b0 - Invalid. [25:25] read-write M4_SOC_CLK_FOR_OTHER_ENABLE_b Static Clock Disable for M4-SOC Other Clock 1b1 - Clock is Disable 1b0 - Invalid. [26:26] read-write ICACHE_ENABLE_b Static Clock Disable for Icache. This has to be enable for Icache operations. 1b1 - Clock is Disable 1b0 - Invalid. [27:27] read-write Reserved5 It is recommended to write these bits to 0. [31:28] read-write CLK_CONFIG_REG1 Clock Config Register 1 0x18 32 read-write 0x07138808 QSPI_CLK_SEL Selects one of the following clocks for ssi master 000 - ULP Ref Clock(generated inside M4SS based on m4ss_ref_clk_sel from NPSS) 001 - Intf PLL Clock Clock (program bypass_intf_pll_clk if the bypass clock has to be selected) 010 - Modem PLL Clock2(Not Intended for the programmer) (program bypass_modem_pll_clk if the bypass clock has to be selected) 011 - SoC PLL Clock Clock (program bypass_soc_pll_clk if the bypass clock has to be selected) 100 to 110 - Invalid 111 - Gated [2:0] read-write QSPI_CLK_DIV_FAC Clock divison factor for QSPI. If qspi_clk_enable is 1b0 clock is gated. Else 1)when qspi_clk_swallow_sel is 1b1 and qspi_odd_div_sel is 1b0 output clock is a swallowed clock with the following frequency. 6h0,6h1 => clk_out = clk_in >6h1 => clk_out = clk_in/ qspi_clk_div_fac 2)when qspi_clk_swallow_sel is 1b0 and qspi_odd_div_sel is 1b0 output clock is a 50% duty cycle clock with the following frequency. 6h0 => clk_out = clk_in/2 >6h0 => clk_out = clk_in/ (2*qspi_clk_div_fac) 3)When qspi_odd_div_sel is 1b1, output clock is a 50% duty cycle clock with the following frequency. clk_out = clk_in/qspi_clk_div_fac when qspi_clk_div_fac is an odd number >=3, else output clock is gated [8:3] read-write QSPI_CLK_SWALLOW_SEL Clock select for clock swallow or clock divider for QSPI 1b0 => 50% divider is selected with division factor qspi_clk_div_fac 1b1 => Swallowed clock is selected with division factor qspi_clk_div_fac Before Changing this ensure that the input clocks are gated [9:9] read-write SLP_RF_CLK_SEL clock select for m4_soc_rf_ref_clk 0 - m4_soc_clk 1 - rf_ref_clk. [10:10] read-write SSI_MST_SCLK_DIV_FAC Clock division factor for ssi_mst_sclk. If ssi_mst_sclk_enable is 1b0 clock is gated. Else output clock is a swallowed clock with the following frequency. 4h0,4h1 => Divider is bypassed >4h1 => clk_out = clk_in/ ssi_mst_sclk_div_fac. [14:11] read-write SSI_MST_SCLK_SEL Selects one of the following clocks for ssi master 000 - ULP Ref Clock(generated inside M4SS based on m4ss_ref_clk_sel from NPSS) 001 - SoC PLL Clock(program bypass_soc_pll_clk if the bypass clock has to be selected) 010 - Modem PLL Clock1(Not Intended for the programmer) (program bypass_modem_pll_clk if the bypass clock has to be selected) 011 - Intf PLL Clock(program bypass_intf_pll_clk if the bypass clock has to be selected) 100 - Modem PLL Clock2(Not Intended for the pragrammer) (program bypass_modem_pll_clk if the bypass clock has to be selected) 101 - m4_soc_clk_for_other_clks 110 - Invalid 111 - Gated. [17:15] read-write PLL_INTF_CLK_SEL Selects one of the following clocks for pll intf clock 0 - Intf Pll Clock(program bypass_intf_pll_clk if the bypass clock has to be selected) 1 - SoC Pll Clock(program bypass_soc_pll_clk if the bypass clock has to be selected) [18:18] read-write PLL_INTF_CLK_DIV_FAC Clock division factor for pll_intf_clk. If pll_intf_clk_enable is 1b0 clock is gated. Else, when pll_intf_clk_swallow_sel is 1b1, output clock is a swallowed clock. when pll_intf_clk_swallow_sel is 1b0, output clock is a 50 Per duty cycle clock. [22:19] read-write PLL_INTF_CLK_SWALLOW_SEL Clock select for clock swallow or clock divider for PLL INTF Clk 1b0 - 50% divider is selected with division factor 2; 1b1 - Swallowed clock is selected with division factor pll_intf_clk_div_fac [23:23] read-write GEN_SPI_MST1_SCLK_SEL Selects one of the following clocks for USART1 clk 000 - m4_soc_clk_for_other_clocks 001 - ulp ref Clock(generated inside M4SS based on m4ss_ref_clk_sel from NPSS) 010 - SoC PLL Clock(program bypass_soc_pll_clk if the bypass clock has to be selected) 011 - Modem PLL Clock2(Not Intended for the pragrammer) (program bypass_modem_pll_clk if the bypass clock has to be selected) 100 - Intf PLL Clock(program bypass_intf_pll_clk if the bypass clock has to be selected) 101 to 110 - Invalid 111 - Gated [26:24] read-write Reserved1 It is recommended to write these bits to 0. [31:27] read-write CLK_CONFIG_REG2 Clock Config Register 1 0x1C 32 read-write 0x0002078F USART1_SCLK_SEL Selects one of the following clocks for USART1 clk 000 - ulp ref Clock(generated inside M4SS based on m4ss_ref_clk_sel from NPSS) 001 - SoC PLL Clock(program bypass_soc_pll_clk if the bypass clock has to be selected) 010 - Modem PLL Clock2(Not Intended for the pragrammer)(program bypass_modem_pll_clk if the bypass clock has to be selected) 011 - Intf PLL Clock(program bypass_intf_pll_clk if the bypass clock has to be selected) 100 - m4_soc_clk_for_other_clocks 101 to 110 - Invalid 111 - Gated [2:0] read-write USART1_SCLK_DIV_FAC Clock division factor for USART1 Clock. If usart1_sclk_enable is 1b0 clock is gated. Else output clock is a swallowed clock. [6:3] read-write USART2_SCLK_SEL Selects one of the following clocks for USART2 clk 000 - ulp ref Clock(generated inside M4SS based on m4ss_ref_clk_sel from NPSS) 001 - SoC PLL Clock(program bypass_soc_pll_clk if the bypass clock has to be selected) 010 - Modem PLL Clock2(Not Intended for the pragrammer)(program bypass_modem_pll_clk if the bypass clock has to be selected) 011 - Intf PLL Clock(program bypass_intf_pll_clk if the bypass clock has to be selected) 100 - m4_soc_clk_for_other_clocks 101 to 110 - Invalid 111 - Gated [9:7] read-write USART2_SCLK_DIV_FAC Clock division factor for USART2 Clock. If usart2_sclk_enable is 1b0 clock is gated. Else output clock is a swallowed clock. [13:10] read-write Reserved1 It is recommended to write these bits to 0. [27:14] read-write QSPI_ODD_DIV_SEL Clock select for clock swallow or 50% even clock divider or 50% odd divider clock for QSPI 1b1 - 50% odd clock divider output is selected with division factor qspi_clk_div_fac 1b0 - 50% even clock divider output or swallowed is selected with division factor qspi_clk_div_fac based on qspi_clk_swallow_sel. [28:28] read-write USART1_SCLK_FRAC_SEL Selects the type of divider for uart1_clk 1b0 - Clock Swallow is selected 1b1 - Fractional Divider is selected. [29:29] read-write USART2_SCLK_FRAC_SEL Selects the type of divider for uart2_clk 1b0 - Clock Swallow is selected 1b1 - Fractional Divider is selected. [30:30] read-write USART3_SCLK_FRAC_SEL Selects the type of divider for uart3_clk 1b0 - Clock Swallow is selected 1b1 - Fractional Divider is selected. [31:31] read-write CLK_CONFIG_REG3 Clock Config Register 3 0x20 32 read-write 0x00000000 Reserved1 It is recommended to write these bits to 0. [7:0] read-write MCU_CLKOUT_SEL Clock Select for the clock on mcu_clkout (Mapped to GPIO) [11:8] read-write MCU_CLKOUT_DIV_FAC Division factor for mcu_clkout (Mapped to GPIO) [17:12] read-write MCU_CLKOUT_ENABLE Clock Enable for the clock on nwp_clkout (Mapped to GPIO) 1b0 - Clock is Gated 1b1 - Clock is Enabled [18:18] read-write Reserved2 It is recommended to write these bits to 0. [31:19] read-write CLK_CONFIG_REG4 Clock Config Register 4 0x24 32 read-write 0x0800AA1C SOC_PLL_CLK_BYP_SEL Selects one of the bypass clocks for SoC PLL Clock [1:0] read-write I2S_PLL_CLK_BYP_SEL Selects one of the bypass clocks for I2S PLL Clock [3:2] read-write MODEM_PLL_CLK_BYP_SEL Selects one of the bypass clocks for Modem PLL Clock [5:4] read-write INTF_PLL_CLK_BYP_SEL Selects one of the bypass clocks for Intf PLL Clock [7:6] read-write SOC_INTF_PLL_BYPCLK_CLKCLNR_ON Clock cleaner ON Control for SoC PLL Bypass Clock [8:8] read-write SOC_INTF_PLL_BYPCLK_CLKCLNR_OFF Clock cleaner OFF Control for SoC PLL Bypass Clock [9:9] read-write Reserved1 It is recommended to write these bits to 0. [11:10] read-write I2S_PLL_BYPCLK_CLKCLNR_ON Clock cleaner ON Control for I2S PLL Bypass Clock. [12:12] read-write I2S_PLL_BYPCLK_CLKCLNR_OFF Clock cleaner OFF Control for I2S PLL Bypass Clock. [13:13] read-write MODEM_PLL_BYPCLK_CLKCLNR_ON Clock cleaner ON Control for Modem PLL Bypass Clock. [14:14] read-write MODEM_PLL_BYPCLK_CLKCLNR_OFF Clock cleaner OFF Control for Modem PLL Bypass Clock. [15:15] read-write BYPASS_SOC_PLL_CLK Select to choose bypass clock or PLL clock 1b0 - soc_pll_clk 1b1 - One of the bypass clocks based on soc_pll_clk_byp_sel. [16:16] read-write BYPASS_I2S_PLL_CLK Select to choose bypass clock or PLL clock 1b0 - i2s_pll_clk 1b1 - One of the bypass clocks based on soc_pll_clk_byp_sel. [17:17] read-write BYPASS_MODEM_PLL_CLK1 Select to choose bypass clock or PLL clock 1b0 - modem_pll_clk1 1b1 - One of the bypass clocks based on modem_pll_clk_byp_sel. [18:18] read-write BYPASS_MODEM_PLL_CLK2 Select to choose bypass clock or PLL clock 1b0 - modem_pll_clk2 1b1 - One of the bypass clocks based on modem_pll_clk_byp_sel. [19:19] read-write BYPASS_INTF_PLL_CLK Select to choose bypass clock or PLL clock 1b0 - intf_pll_clk 1b1 - One of the bypass clocks based on soc_pll_clk_byp_sel. [20:20] read-write SLEEP_CLK_SEL Select to choose sleep clk 00 - ulp_32khz_rc_clk 01 - ulp_32khz_xtal_clk 10 - Gated 11 - ulp_32khz_ro_clk. [22:21] read-write Reserved2 It is recommended to write these bits to 0. [24:23] read-write ULPSS_CLK_DIV_FAC Clock division factor for clock to ULPSS. If ulpss_clk_enable is 1b0 clock is gated. Else output clock is a divided clock with the following frequency. 6h0 - Divider is bypassed > 6h0 - clk_out = clk_in/ 2* ulpss_clk_div_fac [30:25] read-write Reserved3 It is recommended to write these bits to 0. [31:31] read-write CLK_CONFIG_REG5 Clock Config Register 5 0x28 32 read-write 0x001E0810 M4_SOC_CLK_SEL Selects one of the clock sources for M4 SoC clock. These clocks are selected for m4_soc_clk when 1)m4_soc_host_clk_sel is 1b0 or 2)when m4_soc_host_clk_sel is 1b1, xtal is ON(xtal_off from slp_fsm should be zero) and host_clk_available(from host logic) is 1b0. 0000 - ULP Ref Clock (generated inside M4SS based on m4ss_ref_clk_sel from NPSS) 0001 - Reserved 0010 - Soc PLL Clock (program bypass_soc_pll_clk if the bypass clock has to be selected) 0011 - Modem PLL Clock1 (Not Intended for the pragrammer) (program bypass_modem_pll_clk if the bypass clock has to be selected) 0100 - Intf PLL Clock (program bypass_intf_pll_clk if the bypass clock has to be selected) 0101 - Sleep Clock(generated inside M4SS based on sleep_clk_sel. Please select the proper sleep clock select before using this) 0110 to 1111 - Invalid [3:0] read-write M4_SOC_CLK_DIV_FAC Clock divison factor for TA SoC Clock If ta_soc_clk_enable(from NPSS) is 1b0 clock is gated. Else output clock is a swallowed clock with the following frequency. 6h0,6h1 - Divider is bypassed >6h1 - clk_out = clk_in/ ta_soc_clk_div_fac [9:4] read-write I2S_CLK_SEL Selects one of the following clocks for config timer I2S interface 00/11 - I2S PLL Clock (program bypass_i2s_pll_clk if the bypass clock has to be selected) 01 - I2S PLL Clock_1 (program bypass_i2s_pll_clk_1 if the bypass clock has to be selected) 10 - m4_soc_clk_for_other_clocks [10:10] read-write I2S_CLK_DIV_FAC Clock division factor for i2s_clk. Else output clock is a 50% divided clock with the following frequency. 6h0 - Divider is bypassed >6h0 - clk_out = clk_in/ 2*i2s_clk_div_fac [16:11] read-write CT_CLK_SEL Selects one of the following clocks for config timer 000 - ulp ref Clock(generated inside M4SS based on m4ss_ref_clk_sel from NPSS) 001 - Intf PLL Clock(program bypass_intf_pll_clk if the bypass clock has to be selected) 010 - SoC PLL Clock(program bypass_soc_pll_clk if the bypass clock has to be selected) 011 - m4_soc_clk_for_other_clocks 100,110 - Invalid 111 - Gated [19:17] read-write CT_CLK_DIV_FAC Clock division factor for sct_clk. If sct_clk_enable is 1b0 clock is gated. Else output clock is a 50% divided clock with the following frequency. 6h0 - Divider is bypassed >6h0 - clk_out = clk_in/ 2*sct_clk_div_fac [25:20] read-write M4_SOC_HOST_CLK_SEL Selects the previous muxed output(xtal_clk) or host_clk as the clock source for M4 SoC clock based on the following combinations of {xtal_off(from slp fsm), host_clk_available(from host logic),m4_soc_host_clk_sel} XX0 - xtal_clk 001 - After wait time based on mask_host_clk_wait_fix ; xtal_clk X11 - host_clk 101 - No Clock [26:26] read-write Reserved1 It is recommended to write these bits to 0. [27:27] read-write ULPSS_ODD_DIV_SEL Selects the type of divider for m4_soc_clk_2ulpss 1b0 - Clock Divider(even) is selected 1b1 - Odd Divider is selected. [28:28] read-write Reserved2 It is recommended to write these bits to 0. [30:29] read-write I2S_CLK_SEL_1 Selects one of the following clocks for config timer for I2S interface 00/11 - I2S PLL Clock (program bypass_i2s_pll_clk if the bypass clock has to be selected) 01 - I2S PLL Clock_1 (program bypass_i2s_pll_clk_1 if the bypass clock has to be selected) 10 - m4_soc_clk_for_other_clocks [31:31] read-write DYN_CLK_GATE_DISABLE_REG Dynamic Clock Gate Disable Register 0x44 32 read-write 0x00000000 SDIO_SYS_HCLK_DYN_CTRL_DISABLE_b Dynamic clock gate disable control sdio sys clk1'b0 => Dynamic control of the clock is disbaled 1'b1 => Dynamic control of the clock is enabled [0:0] read-write BUS_CLK_DYN_CTRL_DISABLE_b Dynamic clock gate disable control bus clk1'b0 => Dynamic control of the clock is disbaled 1'b1 => Dynamic control of the clock is enabled [1:1] read-write Reserved1 It is recommended to write these bits to 0. [3:2] read-write GPDMA_HCLK_DYN_CTRL_DISABLE_b Dynamic clock gate disable control gpdma clk1'b0 => Dynamic control of the clock is disbaled 1'b1 => Dynamic control of the clock is enabled [4:4] read-write EGPIO_PCLK_DYN_CTRL_DISABLE_b Dynamic clock gate disable control egpio clk1'b0 => Dynamic control of the clock is disbaled 1'b1 => Dynamic control of the clock is enabled [5:5] read-write SGPIO_PCLK_DYN_CTRL_DISABLE_b Dynamic clock gate disable control sgpio clk1'b0 => Dynamic control of the clock is disbaled 1'b1 => Dynamic control of the clock is enabled [6:6] read-write TOT_CLK_DYN_CTRL_DISABLE_b Dynamic clock gate disable control tot clk1'b0 => Dynamic control of the clock is disbaled 1'b1 => Dynamic control of the clock is enabled [7:7] read-write Reserved2 It is recommended to write these bits to 0. [8:8] read-write USART1_SCLK_DYN_CTRL_DISABLE_b Dynamic clock gate disable control usart1 sclk1'b0 => Dynamic control of the clock is disbaled 1'b1 => Dynamic control of the clock is enabled. [9:9] read-write USART1_PCLK_DYN_CTRL_DISABLE_b Dynamic clock gate disable control usart1 pclk1'b0 => Dynamic control of the clock is disbaled 1'b1 => Dynamic control of the clock is enabled. [10:10] read-write USART2_SCLK_DYN_CTRL_DISABLE_b Dynamic clock gate disable control usart2 sclk1'b0 => Dynamic control of the clock is disbaled 1'b1 => Dynamic control of the clock is enabled. [11:11] read-write USART2_PCLK_DYN_CTRL_DISABLE_b Dynamic clock gate disable control usart2 pclk1'b0 => Dynamic control of the clock is disbaled 1'b1 => Dynamic control of the clock is enabled. [12:12] read-write Reserved3 It is recommended to write these bits to 0. [14:13] read-write SSI_SLV_SCLK_DYN_CTRL_DISABLE_b Dynamic clock gate disable control ssi slave sclk1'b0 => Dynamic control of the clock is disbaled 1'b1 => Dynamic control of the clock is enabled [15:15] read-write SSI_SLV_PCLK_DYN_CTRL_DISABLE_b Dynamic clock gate disable control ssi slave pclk1'b0 => Dynamic control of the clock is disbaled 1'b1 => Dynamic control of the clock is enabled [16:16] read-write Reserved4 It is recommended to write these bits to 0. [18:17] read-write SEMAPHORE_CLK_DYN_CTRL_DISABLE_b Dynamic clock gate disable control semaphore clk1'b0 => Dynamic control of the clock is disbaled 1'b1 => Dynamic control of the clock is enabled. [19:19] read-write ARM_CLK_DYN_CTRL_DISABLE_b Dynamic clock gate disable control arm clk1'b0 => Dynamic control of the clock is disbaled 1'b1 => Dynamic control of the clock is enabled. [20:20] read-write SSI_MST_SCLK_DYN_CTRL_DISABLE_b Dynamic clock gate disable control ssi mst sclk1'b0 => Dynamic control of the clock is disbaled 1'b1 => Dynamic control of the clock is enabled. [21:21] read-write Reserved5 It is recommended to write these bits to 0. [23:22] read-write MEM_CLK_ULP_DYN_CTRL_DISABLE_b Dynamic clock gate disable control mem clk1'b0 => Dynamic control of the clock is disbaled 1'b1 => Dynamic control of the clock is enabled. [24:24] read-write Reserved6 It is recommended to write these bits to 0. [27:25] read-write SSI_MST_PCLK_DYN_CTRL_DISABLE_b Dynamic clock gate disable control ssi mst pclk 1'b0 => Dynamic control of the clock is disbaled 1'b1 => Dynamic control of the clock is enabled [28:28] read-write ICACHE_DYN_GATING_DISABLE_b Dynamic clock gate disable control icache clk1'b0 => Dynamic control of the clock is disbaled 1'b1 => Dynamic control of the clock is enabled [29:29] read-write Reserved7 It is recommended to write these bits to 0. [30:30] read-write MISC_CONFIG_PCLK_DYN_CTRL_DISABLE_b Dynamic clock gate disable control miscn config pclk 1'b0 => Dynamic control of the clock is disbaled 1'b1 => Dynamic control of the clock is enabled. [31:31] read-write PLL_ENABLE_SET_REG PLL Enable Set Register 0x50 32 read-write 0x00000000 SOCPLL_SPI_SW_RESET SPI soft reset for SoC PLL1'b1 => soft reset is enabled1'b0 => Invalid [0:0] read-write Reserved1 It is recommended to write these bits to 0. [31:1] read-write PLL_ENABLE_CLEAR_REG PLL Enable Clear Register 0x54 32 read-write 0x00000000 SOCPLL_SPI_SW_RESET SPI soft reset for SoC PLL1'b1 => soft reset is disabled1'b0 => Invalid [0:0] read-write Reserved1 It is recommended to write these bits to 0. [31:1] read-write PLL_STAT_REG PLL Status Register 0x58 32 read-only 0xFFFFFF78 LCDPLL_LOCK Lock Signal from LCD PLL [0:0] read-only DDRPLL_LOCK Lock Signal from DDR PLL [1:1] read-only APPLL_LOCK Lock Signal from AP PLL [2:2] read-only INTFPLL_LOCK Lock Signal from INTF PLL [3:3] read-only I2SPLL_LOCK Lock Signal from I2S PLL [4:4] read-only SOCPLL_LOCK Lock Signal from SoC PLL [5:5] read-only MODEMPLL_LOCK Lock Signal from Modem PLL [6:6] read-only PLL_LOCK_DATA_TRIG This is set to 1'b1 when the PLL Locks are equal to pll_lock_int_data_reg [7:7] read-only M4_SOC_CLK_SWITCHED Indication from M4 SoC Clock Dynamic mux that the switching happened [8:8] read-only QSPI_CLK_SWITCHED Indication from QSPI Clock Dynamic mux that the switching happened [9:9] read-only USART1_SCLK_SWITCHED Indication from USART1 Clock Dynamic mux that the switching happened [10:10] read-only USART2_SCLK_SWITCHED Indication from USART1 Clock Dynamic mux that the switching happened [11:11] read-only GEN_SPI_MST1_SCLK_SWITCHED Indication from USART2 Clock Dynamic mux that the switching happened [12:12] read-only SSI_MST_SCLK_SWITCHED Indication from SSi Master SClock Dynamic mux that the switching happened [13:13] read-only Reserved1 It is recommended to write these bits to 0. [14:14] read-only CT_CLK_SWITCHED Indication from SCT Clock Dynamic mux that the switching happened [15:15] read-only M4_TA_SOC_CLK_SWITCHED_SDIO Indication from M4-TA Soc SDIO Clock Dynamic mux that the switching happened(TBD) [16:16] read-only I2S_CLK_SWITCHED Indication from I2S Clock Dynamic mux that the switching happened [17:17] read-only PLL_INTF_CLK_SWITCHED Indication from Pll Intf Clock Dynamic mux that the switching happened [18:18] read-only Reserved2 It is recommended to write these bits to 0. [20:19] read-only SLEEP_CLK_SWITCHED Indication from Sleep clcok Dynamic mux that the switching happened [21:21] read-only MCU_CLKOUT_SWITCHED Indication from mcu_clkout Dynamic mux that the switching happened [22:22] read-only Reserved3 It is recommended to write these bits to 0. [23:23] read-only TASS_M4SS_64K_CLK_SWITCHED Indication when TA accessing 2nd memory chunk of M4, clock to Dynamic mux switching happened [24:24] read-only CC_CLOCK_MUX_SWITCHED Indication from cc clock Dynamic mux that the switching happened [25:25] read-only TASS_M4SS_192K_CLK_SWITCHED Indication when TA accessing 0th memory chunk of M4, clock to Dynamic mux switching happened [26:26] read-only USART1_CLK_SWITCHED Indication from usart1 sclk or pclk Dynamic mux that the switching happened [27:27] read-only USART2_CLK_SWITCHED Indication from usart2 sclk or pclk Dynamic mux that the switching happened [28:28] read-only TASS_M4SS_64K0_CLK_SWITCHED Indication when TA accessing 1st memory chunk of M4, clock to Dynamic mux switching happened [29:29] read-only CLK_FREE_OR_SLP_SWITCHED Indication from clk_free_or_slp Dynamic mux that the switching happened [30:30] read-only ULP_REF_CLK_SWITCHED Indication from ulp_ref_clk Dynamic mux that the switching happened [31:31] read-only PLL_LOCK_INT_MASK_REG PLL Lock Interrupt Mask Register 0x5C 32 read-write 0x0000FFFF LCD_PLL_LOCK_MASK_BIT_OF_RISING_EDGE 1'b1 => Masked;1'b0 => Not Masked [0:0] read-write DDR_PLL_LOCK_MASK_BIT_OF_RISING_EDGE 1'b1 => Masked;1'b0 => Not Masked [1:1] read-write AP_PLL_LOCK_MASK_BIT_OF_RISING_EDGE 1'b1 => Masked;1'b0 => Not Masked [2:2] read-write INTF_PLL_LOCK_MASK_BIT_OF_RISING_EDGE 1'b1 => Masked;1'b0 => Not Masked [3:3] read-write I2S_PLL_LOCK_MASK_BIT_OF_RISING_EDGE 1'b1 => Masked;1'b0 => Not Masked [4:4] read-write SOC_PLL_LOCK_MASK_BIT_OF_RISING_EDGE 1'b1 => Masked;1'b0 => Not Masked [5:5] read-write MODEM_PLL_LOCK_MASK_BIT_OF_RISING_EDGE 1'b1 => Masked;1'b0 => Not Masked [6:6] read-write PLL_LOCK_DATA_TRIGGER_MASK_BIT_OF_RISING_EDGE 1'b1 => Masked;1'b0 => Not Masked [7:7] read-write LCD_PLL_LOCK_MASK_BIT_OF_FALLING_EDGE 1'b1 => Masked;1'b0 => Not Masked [8:8] read-write DDR_PLL_LOCK_MASK_BIT_OF_FALLING_EDGE 1'b1 => Masked;1'b0 => Not Masked [9:9] read-write AP_PLL_LOCK_MASK_BIT_OF_FALLING_EDGE 1'b1 => Masked;1'b0 => Not Masked [10:10] read-write INTF_PLL_LOCK_MASK_BIT_OF_FALLING_EDGE 1'b1 => Masked;1'b0 => Not Masked [11:11] read-write I2S_PLL_LOCK_MASK_BIT_OF_FALLING_EDGE 1'b1 => Masked;1'b0 => Not Masked [12:12] read-write SOC_PLL_LOCK_MASK_BIT_OF_FALLING_EDGE 1'b1 => Masked;1'b0 => Not Masked [13:13] read-write MODEM_PLL_LOCK_MASK_BIT_OF_FALLING_EDGE 1'b1 => Masked;1'b0 => Not Masked [14:14] read-write PLL_LOCK_DATA_TRIGGER_MASK_BIT_OF_FALLING_EDGE 1'b1 => Masked;1'b0 => Not Masked [15:15] read-write Reserved1 It is recommended to write these bits to 0. [31:16] read-write PLL_LOCK_INT_CLR_REG PLL Lock Interrupt Clear Register 0x60 32 read-write 0x00000000 LCD_PLL_LOCK_CLEAR_BIT_OF_RISING_EDGE 1'b0 => Not Cleared 1'b1 => Cleared [0:0] read-write DDR_PLL_LOCK_CLEAR_BIT_OF_RISING_EDGE 1'b0 => Not Cleared 1'b1 => Cleared [1:1] read-write AP_PLL_LOCK_CLEAR_BIT_OF_RISING_EDGE 1'b0 => Not Cleared 1'b1 => Cleared [2:2] read-write INTF_PLL_LOCK_CLEAR_BIT_OF_RISING_EDGE 1'b0 => Not Cleared 1'b1 => Cleared [3:3] read-write I2S_PLL_LOCK_CLEAR_BIT_OF_RISING_EDGE 1'b0 => Not Cleared 1'b1 => Cleared [4:4] read-write SOC_PLL_LOCK_CLEAR_BIT_OF_RISING_EDGE 1'b0 => Not Cleared 1'b1 => Cleared [5:5] read-write MODEM_PLL_LOCK_CLEAR_BIT_OF_RISING_EDGE 1'b0 => Not Cleared 1'b1 => Cleared [6:6] read-write PLL_LOCK_DATA_TRIGGER_CLEAR_BIT_OF_RISING_EDGE 1'b0 => Not Cleared 1'b1 => Cleared [7:7] read-write LCD_PLL_LOCK_CLEAR_BIT_OF_FALLING_EDGE 1'b0 => Not Cleared 1'b1 => Cleared [8:8] read-write DDR_PLL_LOCK_CLEAR_BIT_OF_FALLING_EDGE 1'b0 => Not Cleared 1'b1 => Cleared [9:9] read-write AP_PLL_LOCK_CLEAR_BIT_OF_FALLING_EDGE 1'b0 => Not Cleared 1'b1 => Cleared [10:10] read-write INTF_PLL_LOCK_CLEAR_BIT_OF_FALLING_EDGE 1'b0 => Not Cleared 1'b1 => Cleared [11:11] read-write I2S_PLL_LOCK_CLEAR_BIT_OF_FALLING_EDGE 1'b0 => Not Cleared 1'b1 => Cleared [12:12] read-write SOC_PLL_LOCK_CLEAR_BIT_OF_FALLING_EDGE 1'b0 => Not Cleared 1'b1 => Cleared [13:13] read-write MODEM_PLL_LOCK_CLEAR_BIT_OF_FALLING_EDGE 1'b0 => Not Cleared 1'b1 => Cleared [14:14] read-write PLL_LOCK_DATA_TRIGGER_CLEAR_BIT_OF_FALLING_EDGE 1'b0 => Not Cleared 1'b1 => Cleared [15:15] read-write Reserved1 It is recommended to write these bits to 0. [31:16] read-write PLL_LOCK_INT_DATA_REG PLL Lock Interrupt DATA Register 0x64 32 read-write 0x00000000 LCD_PLL_LOCK 1'b1 => LCD PLL Lock has to be used as trigger1'b0 => LCD PLL Lock not to be used as trigger [0:0] read-write DDR_PLL_LOCK 1'b1 => DDR PLL Lock has to be used as trigger1'b0 => DDR PLL Lock not to be used as trigger [1:1] read-write AP_PLL_LOCK 1'b1 => AP PLL Lock has to be used as trigger1'b0 => Ap PLL Lock not to be used as trigger [2:2] read-write INTF_PLL_LOCK 1'b1 => INTF PLL Lock has to be used as trigger1'b0 => INTF PLL Lock not to be used as trigger [3:3] read-write I2S_PLL_LOCK 1'b1 => I2S PLL Lock has to be used as trigger1'b0 => I2S PLL Lock not to be used as trigger [4:4] read-write SOC_PLL_LOCK 1'b1 => SoC PLL Lock has to be used as trigger1'b0 => SoC PLL Lock not to be used as trigger [5:5] read-write MODEM_PLL_LOCK 1'b1 => Modem PLL Lock has to be used as trigger1'b0 => Modem PLL Lock not to be used as trigger [6:6] read-write Reserved1 It is recommended to write these bits to 0. [31:7] read-write SLEEP_CALIB_REG Sleep Calib Register 0x68 32 read-write 0x00000000 SLP_CALIB_START_b This bit is used to start the calibration. 1b1 - Start calibration. slp_calib_duration should be loaded before this bit is set. This bit is self-clearing. When read, if high indicates the completion of calibration process. [0:0] read-write SLP_CALIB_CYCLES These bits are used to program the number of clock cycles over which clock calibration is to be done. [2:1] read-write SLP_CALIB_DURATION_b Duration of the sleep clock in terms of processor clocks. This has to be divided with number of calibration cycles to get number of clock cycles(reference clock) in single clock period). 1b1 - AP PLL Lock has to be used as trigger1b0 - Ap PLL Lock not to be used as trigger [18:3] read-write SLP_CALIB_DONE_b Indicates the end of calibration [19:19] read-write Reserved1 It is recommended to write these bits to 0. [31:20] read-write CLK_CALIB_CTRL_REG1 Clock Calib Control Register1 0x6C 32 read-write 0x00000000 CC_SOFT_RST_b Soft Reset for clock calibrator 1b1 - reset enabled 1b0 - reset disabled. [0:0] read-write CC_START_b start clk calibration 1b1 - start [1:1] read-write CC_CHANGE_TEST_CLK_b change test clk. Set this bit to 1'b1 only when test_clk is being changed, else this should be 1'b0. [2:2] read-write CC_CLKIN_SEL_b select the clock to be calibrated 4d0 - ulp_ref_clk 4d1 - mems_ref_clk 4d2 - ulp_20mhz_ringosc_clk 4d3 - modem_pll_clk1 4d4 - modem_pll_clk2 4d5 - intf_pll_clk 4d6 - soc_pll_clk 4d7 - i2s_pll_clk 4d8 - sleep_clk 4d9 - bus_clkby2_apss2m4ss_sram 4d10, 4d14 - Invalid 4d15 - Gated [6:3] read-write Reserved1 It is recommended to write these bits to 0. [31:7] read-write CLK_CALIB_CTRL_REG2 Clock Calib Control Register2 0x70 32 read-write 0x00000000 CC_NUM_REF_CLKS number of ref_clk cycles to be considered for calibrating. [31:0] read-write CLK_CALIB_STS_REG1 Clock Calib Status Register1 0x74 32 read-write 0x00000000 CC_DONE_b indicates clock calibratioon done1'b1 => done1'b0 => none [0:0] read-write CC_ERROR_b indicates clock calibration error1'b1 => error1'b0 => none [1:1] read-write Reserved1 It is recommended to write these bits to 0. [31:2] read-write CLK_CALIB_STS_REG2 Clock Calib Status Register2 0x78 32 read-write 0x00000000 CC_NUM_TEST_CLKS number of test clk cycles occurred for the specified number of ref_clk cycles [31:0] read-write CLK_CONFIG_REG6 Clock Config Register6 0x7C 32 read-write 0x00000080 IID_KH_CLK_DIV_FAC Clock division factor for iid_clk. [2:0] read-write Reserved1 It is recommended to write these bits to 0. [4:3] read-write PADCFG_PCLK_DIV_FAC Clock division factor for pclk_pad_config_m4ss [8:5] read-write Reserved2 It is recommended to write these bits to 0. [31:9] read-write DYN_CLK_GATE_DISABLE_REG2 Dynamic Clock Gate Disable Register2 0x80 32 read-write 0x00000000 SOC_PLL_SPI_CLK_DYN_CTRL_DISABLE_b Dynamic clock gate disable control soc pll spi clk 1b1 - Dynamic control of the clock is disbaled 1b0 - Dynamic control of the clock is enabled [0:0] read-write Reserved1 It is recommended to write these bits to 0. [2:1] read-write CT_PCLK_DYN_CTRL_DISABLE_b Dynamic clock gate disable control SCT pclk 1b1 - Dynamic control of the clock is disbaled 1b0 - Dynamic control of the clock is enabled [3:3] read-write Reserved2 It is recommended to write these bits to 0. [5:4] read-write EFUSE_CLK_DYN_CTRL_DISABLE_b Dynamic clock gate disable control efuse clk 1b1 - Dynamic control of the clock is disbaled 1b0 - Dynamic control of the clock is enabled [6:6] read-write EFUSE_PCLK_DYN_CTRL_DISABLE_b Dynamic clock gate disable control efuse pclk 1b1 - Dynamic control of the clock is disbaled 1b0 - Dynamic control of the clock is enabled [7:7] read-write Reserved3 It is recommended to write these bits to 0. [31:8] read-write PLL_LOCK_INT_STATUS_REG PLL Lock Interrupt Status Register 0x84 32 read-write 0x00000000 LCD_PLL_LOCK_OF_RISING_EDGE 1b0 - No Interrupt; 1b1 - Interrupt encountered. [0:0] read-write DDR_PLL_LOCK_OF_RISING_EDGE 1'b0 => No Interrupt;1'b1 => Interrupt encountered. [1:1] read-write AP_PLL_LOCK_OF_RISING_EDGE 1'b0 => No Interrupt;1'b1 => Interrupt encountered. [2:2] read-write INTF_PLL_LOCK_OF_RISING_EDGE 1'b0 => No Interrupt;1'b1 => Interrupt encountered. [3:3] read-write I2S_PLL_LOCK_OF_RISING_EDGE 1'b0 => No Interrupt;1'b1 => Interrupt encountered. [4:4] read-write SOC_PLL_LOCK_OF_RISING_EDGE 1'b0 => No Interrupt;1'b1 => Interrupt encountered. [5:5] read-write MODEM_PLL_LOCK_OF_RISING_EDGE 1'b0 => No Interrupt;1'b1 => Interrupt encountered. [6:6] read-write PLL_LOCK_DATA_TRIGGER_INTR_OF_RISING_EDGE 1'b0 => No Interrupt;1'b1 => Interrupt encountered. [7:7] read-write LCD_PLL_LOCK_OF_FALLING_EDGE 1'b0 => No Interrupt;1'b1 => Interrupt encountered. [8:8] read-write DDR_PLL_LOCK_OF_FALLING_EDGE 1'b0 => No Interrupt;1'b1 => Interrupt encountered. [9:9] read-write AP_PLL_LOCK_OF_FALLING_EDGE 1'b0 => No Interrupt;1'b1 => Interrupt encountered. [10:10] read-write INTF_PLL_LOCK_OF_FALLING_EDGE 1'b0 => No Interrupt;1'b1 => Interrupt encountered. [11:11] read-write I2S_PLL_LOCK_OF_FALLING_EDGE 1'b0 => No Interrupt;1'b1 => Interrupt encountered. [12:12] read-write SOC_PLL_LOCK_OF_FALLING_EDGE 1'b0 => No Interrupt;1'b1 => Interrupt encountered. [13:13] read-write MODEM_PLL_LOCK_OF_FALLING_EDGE 1'b0 => No Interrupt;1'b1 => Interrupt encountered. [14:14] read-write PLL_LOCK_DATA_TRIGGER_INTR_OF_FALLING_EDGE 1'b0 => No Interrupt;1'b1 => Interrupt encountered. [15:15] read-write Reserved1 It is recommended to write these bits to 0. [31:16] read-write Sleep_Clock_Calibrator 1.0 In this the time periods of 32KHz RC clock, 32KHz RO clock and 32KHz XTAL clock can be calibrated TIMEPERIOD_CALIBRATION 0x24048200 32 read-write 0x00 0x1C registers MCU_CAL_RO_TIMEPERIOD_READ RO timeperiod read register 0x00 32 read-write 0x00000000 TIMEPERIOD_RO Calibrated RO timeperiod [24:0] read-only RESERVED1 reser [31:25] read-only MCU_CAL_TIMER_CLOCK_PERIOD MCU calender timer clock period register 0x04 32 read-write 0x00000000 RTC_TIMER_CLK_PERIOD RTC timer clock period programmed by SOC [24:0] read-write RESERVED1 reser [30:25] read-only SPI_RTC_TIMER_CLK_PERIOD_APPLIED_b Indicated SOC programmed rtc_timer clock period is applied at KHz clock domain [31:31] read-only MCU_CAL_TEMP_PROG_REG temprature program register 0x08 32 read-write 0x00050000 BYPASS_CALIB_PG To bypass power gating and keep all the blocks always on [0:0] read-write RESERVED1 reser [15:1] read-only MAX_TEMP_CHANGE maximum temperature change after which rc calibration must be trigger [20:16] read-write TEMP_TRIGGER_TIME_SEL temperature trigger time select [22:21] read-write PERIODIC_TEMP_CALIB_EN Enable periodic checking of temperature [23:23] read-write RTC_TIMER_PERIOD_MUX_SEL rtc timer period mux select [24:24] read-write RESERVED2 reser [31:25] read-only MCU_CAL_START_REG mcu cal start register 0x0c 32 read-write 0x0000AE92 ALPHA_RO alpha = 1/2^alpha_ro , averaging factor of RO timeperiod T = alpha(t_inst) + (1- alpha )t_prev [2:0] read-write ALPHA_RC alpha = 1/2^alpha_rc , averaging factor of RC timeperiod T = alpha(t_inst) + (1- alpha )t_prev [5:3] read-write NO_OF_RO_CLKS 2^no_of_ro_clks no of clocks of ro clock counts for no of rc clocks in that time to measure timeperiod [9:6] read-write NO_OF_RC_CLKS 2^no_of_rc_clocks = no of rc clocks used in calibration [12:10] read-write RC_SETTLE_TIME no of clocks of RO for the RC clk to settle when enabled [15:13] read-write RO_TRIGGER_TIME_SEL ro trigger time select [17:16] read-write RC_TRIGGER_TIME_SEL rc trigger time select [20:18] read-write PERIODIC_RO_CALIB_EN periodically calibrate RO timeperiod based ro trigger time sel [21:21] read-write PERIODIC_RC_CALIB_EN periodically calibrate RC timeperiod based rc trigger time sel [22:22] read-write START_CALIB_RO to initiate RO calibration [23:23] write-only START_CALIB_RC to initiate RC calibration [24:24] write-only RC_XTAL_MUX_SEL xtal mux select [25:25] read-write LOW_POWER_TRIGGER_SEL power trigger select [26:26] read-write VBATT_TRIGGER_TIME_SEL trigger to ipmu block for checking vbatt status periodicaly [29:27] read-write RESERVED1 reser [31:30] read-only MCU_CAL_REF_CLK_SETTLE_REG reference clock settle register 0x10 32 read-write 0x00000040 XTAL_SETTLE no of 32khz clocks for xtal 40mhz clk to settle [6:0] read-write RESERVED1 reser [15:7] read-only VALID_RC_TIMEPERIOD Valid signal for reading RC timeperiod calibrated [16:16] read-only VALID_RO_TIMEPERIOD Valid signal for reading RO timeperiod [17:17] read-only RESERVED2 reser [31:18] read-only MCU_CAL_RC_TIMEPERIOD_READ rc timeperiod read register 0x14 32 read-write 0x00000000 TIMEPERIOD_RC Calibrated RC timeperiod [24:0] read-only RESERVED1 reser [31:25] read-only MCU_CAL_REF_CLK_TIEMPERIOD_REG reference clock timeperiod register 0x18 32 read-write 0x00333333 TIMEPERIOD_REF_CLK timeperiod of reference clk with each bit corresponding to granularity of 2^27 = 1us [23:0] read-write RESERVED1 reser [31:24] read-only WDT 1.0 A dedicated window watch dog timer for MCU applications WDT 0x24048300 32 read-write 0x00 0x1C registers MCU_WWD_INTERRUPT_TIMER WATCHDOG interrupt timer register 0x00 32 read-write 0x00000000 WWD_INTERRUPT_TIMER Watchdog Timer programming values [7:0] read-write RESERVED1 reserved,It is recommended to write these bits to 0 [31:7] read-write MCU_WWD_SYSTEM_RESET_TIMER MCU watchdog system reset register 0x04 32 read-write 0x00000000 WWD_SYSTEM_RESET_TIMER Watch dog soc reset delay timer programming values [7:0] read-write RESERVED1 reserved,It is recommended to write these bits to 0 [31:8] read-write MCU_WWD_WINDOW_TIMER watchdog window timer register 0x08 32 read-write 0x00000000 WINDOW_TIMER watchdog window timer [3:0] read-write RESERVED1 reserved [31:4] read-only MCU_WWD_PROC_STUCK_EN watchdog arm stuck enable register 0x0C 32 read-write 0x00000000 RESERVED1 reserved,It is recommended to write these bit to 0 [15:0] read-write PROCESSOR_STUCK_RESET_EN Enable to reset M4 core on seeing LOCKUP signal [16:16] write-only RESERVED2 reserved,It is recommended to write these bit to 0 [31:17] read-write MCU_WWD_TIMER_ENABLE WDT Enable register 0x10 32 read-write 0x00000000 WWD_TIMER_RSTART Writing 1 restarts WDT ,writing 0 no effect [0:0] write-only RESERVED1 reserved,It is recommended to write these bits to 0 [15:1] read-write WWD_TIMER_EN OXAA Enables WDT, OXF0 Disables WDT [23:16] write-only RESERVED2 reserved,It is recommended to write these bits 0 [31:24] read-write MCU_WWD_KEY_ENABLE watchdog key enable register 0x18 32 write-only 0x877F38E9 WWD_KEY_ENABLE Writing 0x877F38E9 enables Read access,0x0AAAAAAA disables it of WDT TIMERS [31:0] write-only Calendar 1.0 The MCU calendar acts as RTC with time in seconds, minutes, hours, days, months, years and centuries RTC 0x24048200 32 read-write 0x00 0x28 registers MCU_CAL_ALARM_PROG_1 MCU calender alarm prog register 1 0x1C 32 read-write 0x00000000 PROG_ALARM_MSEC milli seconds value of alarm time [9:0] read-write PROG_ALARM_SEC seconds value of alarm time [15:10] read-write PROG_ALARM_MIN mins value of alarm time [21:16] read-write PROG_ALARM_HOUR hours value of alarm time [26:22] read-write RESERVED1 reser [31:27] read-only MCU_CAL_ALARM_PROG_2 MCU calender alarm prog register 2 0x20 32 read-write 0x00000000 PROG_ALARM_DAY day count in alarm time 1-31 [4:0] read-write RESERVED1 reser [7:5] read-only PROG_ALARM_MONTH month count in alarm time [11:8] read-write RESERVED2 reser [15:12] read-only PROG_ALARM_YEAR year count in alarm time 0 - 99 [22:16] read-write PROG_ALARM_CENTURY century count in alarm time [24:23] read-write RESERVED3 reser [30:25] read-only ALARM_EN alarm function enable for calendar [31:31] read-write MCU_CAL_POWERGATE_REG MCU calender powergate register 0x24 32 read-write 0x00000001 PG_EN_CALENDER Start calender block [0:0] read-write ENABLE_CALENDER_COMBI Enable calender combitional logic block [1:1] read-write DISABLE_COMBI_DYN_PWRGATE_EN Disable option for dynamic combo RTC power gate [2:2] read-write STATIC_COMBI_RTC_PG_EN Enable static combo RTC power gate [3:3] read-write RESERVED1 RESERVED1 [31:4] read-only MCU_CAL_PROG_TIME_1 MCU calendar prog time 1 register 0x28 32 read-write 0x00000000 PROG_MSEC Milli seconds value to be programmed to real time in calendar when pro_time_trig is 1 [9:0] read-write PROG_SEC seconds value to be programmed to real time in calendar when pro_time_trig is 1 [15:10] read-write PROG_MIN minutes value to be programmed to real time in calendar when pro_time_trig is 1 [21:16] read-write PROG_HOUR hours value to be programmed to real time in calendar when pro_time_trig is 1 [26:22] read-write RESERVED2 reser [31:27] read-only MCU_CAL_PROG_TIME_2 MCU calendar prog time 2 register 0x2C 32 read-write 0x00000000 PROG_DAY day count value to be programmed to real time in calendar when pro_time_trig is 1 [4:0] read-write PROG_WEEK_DAY program which week day it is [7:5] read-write PROG_MONTH month value to be programmed to real time in calendar when pro_time_trig is 1 [11:8] read-write RES reser [15:12] read-only PROG_YEAR year value to be programmed to real time in calendar when pro_time_trig is 1 [22:16] read-write PROG_CENTURY century value to be programmed to real time in calendar when pro_time_trig is 1 [24:23] read-write RESERVED1 reser [30:25] read-only PROG_TIME_TRIG load the programmed to the real time in calendar block [31:31] write-only MCU_CAL_READ_TIME_MSB MCU calendar read time msb 0x30 32 read-only 0x00000000 WEEK_DAY week day [2:0] read-only MONTHS_COUNT months count [6:3] read-only YEAR_COUNT years count [13:7] read-only CENTURY_COUNT century count [15:14] read-only RESERVED1 reser [31:16] read-only MCU_CAL_READ_TIME_LSB MCU calendar read time lsb 0x34 32 read-only 0x00000000 MILLISECONDS_COUNT milliseconds count [9:0] read-only SECONDS_COUNT seconds count [15:10] read-only MINS_COUNT mins count [21:16] read-only HOURS_COUNT hours count [26:22] read-only DAYS_COUNT days count [31:27] read-only MCU_CAL_READ_COUNT_TIMER MCU calendar read count timer 0x38 32 read-only 0x00000000 READ_COUNT_TIMER Read timer which increments by time period value to reach to count milliseconds [26:0] read-only RESERVED1 reser [31:27] read-only MCU_CAL_SLEEP_CLK_COUNTERS MCU calendar sleep clock counter 0x3C 32 read-only 0x00000000 SLEEP_CLK_DURATION No of sleep clks with respect to APB clock so far from the posedge of sleep clk [11:0] read-only RESERVED1 reser [15:12] read-only PCLK_COUNT_WRT_SLEEP_CLK no. of APB clks in 1 sleep clock duration [27:16] read-only RESERVED2 reser [31:28] read-only MCU_CAL_KEY_EANBLE MCU calendar key enable 0x40 32 write-only 0x55555555 RTC_KEY enable access to program Watch dog registers [31:0] write-only High_Power_Domain 1.0 The use of this is to store some information in ULP over wake-ups to reduce wake-up time High_Power_Domain 0x24048400 32 read-write 0x00 0x100 registers M4SS_BYPASS_PWRCTRL_REG1 M4ss bypass power control register 1 0x00 32 read-write 0x00000000 RES reserved1 [2:0] read-only BYPASS_M4SS_PWRCTL_ULP_M4_ULP_AON_b Enables software based control of isolation and reset for ULP AON M4ss [3:3] read-write BYPASS_M4SS_PWRCTL_ULP_EFUSE_b Enables software based control of isolation and reset for ULP EFUSE [4:4] read-write RESERVED2 reserved2 [8:5] read-write BYPASS_M4SS_PWRCTL_ULP_RPDMA_b Enables software based control of isolation and reset for RPDMA [9:9] read-write RESERVED3 reserved3 [10:10] read-write BYPASS_M4SS_PWRCTL_ULP_HIF_SDIO_SPI_b Enables software based control of isolation and reset for HIF SDIO SPI [11:11] read-write RESERVED4 reserved4 [12:12] read-write BYPASS_M4SS_PWRCTL_ULP_QSPI_ICACHE_b Enables software based control of isolation and reset for ULP quad SPI and ICACHE [13:13] read-write BYPASS_M4SS_PWRCTL_ULP_IID_b Enables software based control of isolation and reset for ULP IID [14:14] read-write RESERVED5 reserved5 [16:15] read-write BYPASS_M4SS_PWRCTL_ULP_M4_DEBUG_b Enables software based control of isolation and reset for M4ss DEBUG [17:17] read-write BYPASS_M4SS_PWRCTL_ULP_M4_CORE_b Enables software based control of isolation and reset for M4ss CORE [18:18] read-write BYPASS_M4SS_PWRCTL_ULP_AON_b Enables software based control of isolation and reset for ULP AON [19:19] read-write RESERVED6 reserved6 [21:20] read-only BYPASS_M4SS_PWRCTL_ULP_ROM_b Enables software based control of isolation and reset for M4ss ROM [22:22] read-write RESERVED7 reserved7 [31:23] read-only M4SS_BYPASS_PWRCTRL_REG2 M4SS bypass power control register 2 0x04 32 read-write 0x00000000 BYPASS_M4SS_PWRCTL_ULP_SRAM_1 Enables software based control of isolation and reset for M4ss SRAM 1 [9:0] read-write RESERVED1 reserved1 [15:10] read-only BYPASS_M4SS_PWRCTL_ULP_SRAM_2 Enables software based control of isolation and reset for M4ss SRAM 2 [19:16] read-write RESERVED2 reserved1 [31:20] read-only M4SS_PWRCTRL_SET_REG M4SS power control set register 0x08 32 read-write 0x00466A10 RES reserved1 [3:0] read-only M4SS_PWRGATE_EN_N_ULP_EFUSE_b Power Gate control for EFUSE [4:4] read-write RESERVED2 reserved2 [8:5] read-only M4SS_PWRGATE_EN_N_ULP_RPDMA_b Power Gate control for RPDMA [9:9] read-write RESERVED3 reserved3 [10:10] read-only M4SS_PWRGATE_EN_N_ULP_HIF_SDIO_SPI_b Power Gate control for HIF SDIO SPI [11:11] read-write RESERVED4 reserved4 [12:12] read-only M4SS_PWRGATE_EN_N_ULP_QSPI_ICACHE_b Power Gate control for QSPI and ICACHE [13:13] read-write M4SS_PWRGATE_EN_N_ULP_IID_b Power Gate control for IID Block.If set, powered ON Clearing this bit has no effect [14:14] read-write RESERVED5 reserved5 [16:15] read-only M4SS_PWRGATE_EN_N_ULP_M4_DEBUG_b Power Gate control for M4 DEBUG [17:17] read-write M4SS_PWRGATE_EN_N_ULP_M4_CORE_b Power Gate control for M4 CORE [18:18] read-write RESERVED6 reserved6 [21:19] read-only M4SS_EXT_PWRGATE_EN_N_ULP_ROM_b External power gate enable signal for ROM [22:22] read-write RESERVED7 reserved7 [31:23] read-only M4SS_PWRCTRL_CLEAR_REG M4SS power control clear register 0x0c 32 read-write 0x00466A10 RES reserved1 [3:0] read-only M4SS_PWRGATE_EN_N_ULP_EFUSE_b Power Gate control for EFUSE [4:4] read-write RESERVED2 reserved2 [8:5] read-only M4SS_PWRGATE_EN_N_ULP_RPDMA_b Power Gate control for RPDMA [9:9] read-write RESERVED3 reserved3 [10:10] read-only M4SS_PWRGATE_EN_N_ULP_HIF_SDIO_SPI_b Power Gate control for HIF SDIO SPI [11:11] read-write RESERVED4 reserved4 [12:12] read-only M4SS_PWRGATE_EN_N_ULP_QSPI_ICACHE_b Power Gate control for QSPI and ICACHE [13:13] read-write M4SS_PWRGATE_EN_N_ULP_IID_b Power Gate control for IID Block.If set, powered ON Clearing this bit has no effect [14:14] read-write RESERVED5 reserved5 [16:15] read-only M4SS_PWRGATE_EN_N_ULP_M4_DEBUG_b Power Gate control for M4 DEBUG [17:17] read-write M4SS_PWRGATE_EN_N_ULP_M4_CORE_b Power Gate control for M4 CORE [18:18] read-write RESERVED6 reserved6 [21:19] read-only M4SS_EXT_PWRGATE_EN_N_ULP_ROM_b External power gate enable signal for ROM [22:22] read-write RESERVED7 reserved7 [31:23] read-only M4_SRAM_PWRCTRL_SET_REG1 M4SS power control set register 1 0x10 32 read-write 0x00ff03ff M4SS_EXT_PWRGATE_EN_N_ULP_SRAM_1 Functional Control signal for M4SS SRAM [9:0] read-write RESERVED1 reserved1 [15:10] read-only M4SS_EXT_PWRGATE_EN_N_ULP_SRAM_2 Functional Control signal for TASS SRAM shared with M4SS [19:16] read-write RESERVED2 reserved1 [31:20] read-write M4_SRAM_PWRCTRL_CLEAR_REG1 M4SS power control clear register 1 0x14 32 read-write 0x00ff03ff M4SS_EXT_PWRGATE_EN_N_ULP_SRAM_1 Functional Control signal for M4SS SRAM [9:0] read-write RESERVED1 reserved1 [15:10] read-write M4SS_EXT_PWRGATE_EN_N_ULP_SRAM_2 Functional Control signal for TASS SRAM shared with M4SS [19:16] read-write RESERVED2 reserved1 [31:20] read-write M4_SRAM_PWRCTRL_SET_REG2 M4SS power control set register 2 0x18 32 read-write 0x00ff03ff M4SS_EXT_PWRGATE_EN_N_ULP_SRAM_PERI_1 Functional Control signal for M4SS SRAM Dual Rail pins [9:0] read-write RESERVED1 reserved1 [15:10] read-write M4SS_EXT_PWRGATE_EN_N_ULP_SRAM_PERI_2 Functional Control signal for TASS SRAM Dual Rail pins shared with M4SS [19:16] read-write RESERVED2 reserved1 [31:20] read-write M4_SRAM_PWRCTRL_CLEAR_REG2 M4SS power control clear register 2 0x1C 32 read-write 0x00ff03ff M4SS_EXT_PWRGATE_EN_N_ULP_SRAM_PERI_1 Functional Control signal for M4SS SRAM Dual Rail pins [9:0] read-write RESERVED1 reserved1 [15:10] read-write M4SS_EXT_PWRGATE_EN_N_ULP_SRAM_PERI_2 Functional Control signal for TASS SRAM Dual Rail pins shared with M4SS [19:16] read-write RESERVED2 reserved1 [31:20] read-write M4_SRAM_PWRCTRL_SET_REG3 M4SS power control set register 3 0x20 32 read-write 0x00ff03ff M4SS_SRAM_INPUT_DISABLE_ISOLATION_ULP_1 Input isolation control for M4SS SRAM [9:0] read-write RESERVED1 reserved1 [15:10] read-write M4SS_SRAM_INPUT_DISABLE_ISOLATION_ULP_2 Input isolation control for TASS SRAM shared with M4SS [19:16] read-write RESERVED2 reserved1 [31:20] read-write M4_SRAM_PWRCTRL_CLEAR_REG3 M4SS power control clear register 3 0x24 32 read-write 0x000f03ff M4SS_SRAM_INPUT_DISABLE_ISOLATION_ULP_1 Input isolation control for M4SS SRAM [9:0] read-write RESERVED1 reserved1 [15:10] read-write M4SS_SRAM_INPUT_DISABLE_ISOLATION_ULP_2 Input isolation control for TASS SRAM shared with M4SS [19:16] read-write RESERVED2 reserved1 [31:20] read-write M4_SRAM_PWRCTRL_SET_REG4 M4SS power control set register 4 0x28 32 read-write 0x00000000 M4SS_SRAM_DS_1 Deep-Sleep control for M4SS SRAM [23:0] read-write RESERVED1 reserved1 [31:24] read-write M4_SRAM_PWRCTRL_CLEAR_REG4 M4SS power control clear register 4 0x2c 32 read-write 0x00000000 M4SS_SRAM_DS_1 Deep-Sleep control for M4SS SRAM [23:0] read-write RESERVED1 reserved1 [31:24] read-write M4SS_TASS_CTRL_SET_REG M4SS_TASS control set register 0x34 32 read-write 0x00000004 M4SS_CTRL_TASS_AON_PWRGATE_EN M4SS controlling Power supply for TASS AON domain [0:0] read-write M4SS_CTRL_TASS_AON_DISABLE_ISOLATION_BYPASS M4SS controlling Power supply for TASS AON domains isolation enable in bypass mode [1:1] read-write M4SS_CTRL_TASS_AON_PWR_DMN_RST_BYPASS M4SS controlling Power supply for TASS AON domains reset pin in bypass mode [2:2] read-write RESERVED1 reserved1 [31:3] read-write M4SS_TASS_CTRL_CLEAR_REG M4SS_TASS control CLEAR register 0x38 32 read-write 0x00000004 M4SS_CTRL_TASS_AON_PWRGATE_EN M4SS controlling Power supply for TASS AON domain [0:0] read-write M4SS_CTRL_TASS_AON_DISABLE_ISOLATION_BYPASS M4SS controlling Power supply for TASS AON domains isolation enable in bypass mode [1:1] read-write M4SS_CTRL_TASS_AON_PWR_DMN_RST_BYPASS M4SS controlling Power supply for TASS AON domains reset pin in bypass mode [2:2] read-write RESERVED1 reserved1 [31:3] read-write M4_ULP_MODE_CONFIG m4 ulp mode config register 0x3c 32 read-write 0x00000000 ULPMODE_ISOLATION_CTRL_ULPSS Isolation Control for ULP-Mode non-functional paths for ULPSS [0:0] read-write ULPMODE_ISOLATION_CTRL_M4SS_AON Isolation Control for ULP-Mode non-functional paths for M4SS-AON [1:1] read-write ULPMODE_ISOLATION_CTRL_M4_ULP Isolation Control for ULP-Mode non-functional paths for M4ULP_AON [2:2] read-write ULPMODE_ISOLATION_CTRL_M4_CORE Isolation Control for ULP-Mode non-functional paths for M4_CORE [3:3] read-write ULPMODE_ISOLATION_CTRL_M4_DEBUG_FPU Isolation Control for ULP-Mode non-functional paths for M4_DEBUG [4:4] read-write ULPMODE_ISOLATION_CTRL_M4_ROM Isolation Control for ULP-Mode non-functional paths for ROM [5:5] read-write RES reserved1 [31:6] read-write ULPSS_BYPASS_PWRCTRL_REG ULPSS bypass power control register 0x40 32 read-write 0x00000000 RES reserved1 [1:0] read-write BYPASS_ULPTASS_PWRCTL_ULP_AON Enables software based control of output isolation for ULPTASS AON [2:2] read-write BYPASS_ULPSDCSS_PWRCTRL_ULP_AON Enables software based control of output isolation for ULPSDCSS AON [3:3] read-write RESERVED2 reser [4:4] read-write BYPASS_ULPTASS_PWRCTL_ULP_MISC Enables software based control of output isolation for ULP MISC [5:5] read-write BYPASS_ULPTASS_PWRCTL_ULP_CAP Enables software based control of output isolation for ULP CAP [6:6] read-write BYPASS_ULPTASS_PWRCTL_ULP_VAD Enables software based control of output isolation for ULP VAD [7:7] read-write BYPASS_ULPTASS_PWRCTL_ULP_UART Enables software based control of output isolation for ULP UART [8:8] read-write BYPASS_ULPTASS_PWRCTL_ULP_SSI Enables software based control of output isolation for ULP SSI [9:9] read-write BYPASS_ULPTASS_PWRCTL_ULP_I2S Enables software based control of output isolation for ULP I2S [10:10] read-write BYPASS_ULPTASS_PWRCTL_ULP_I2C Enables software based control of output isolation for ULP I2C [11:11] read-write BYPASS_ULPTASS_PWRCTL_ULP_AUX Enables software based control of output isolation for ULP AUX [12:12] read-write BYPASS_ULPTASS_PWRCTL_ULP_IR Enables software based control of output isolation for ULP IR [13:13] read-write BYPASS_ULPTASS_PWRCTL_ULP_UDMA Enables software based control of output isolation for ULP UDMA [14:14] read-write BYPASS_ULPTASS_PWRCTL_ULP_FIM Enables software based control of output isolation for ULP FIM [15:15] read-write RESERVED3 reserved1 [18:16] read-write BYPASS_ULPTASS_PWRCTL_ULP_SRAM Enables software based control of output isolation for ULPTASS SRAM [22:19] read-write RESERVED4 reserved1 [31:23] read-write MCU_FSM_CTRL_BYPASS MCU FSM control bypass register 0x64 32 read-write 0x0000001d MCU_XTAL_EN_40MHZ_BYPASS_CTRL Xtal 40mhz enable bypass from MCU [0:0] read-write MCU_XTAL_EN_40MHZ_BYPASS Value of Xtal Enable in bypass mode [1:1] read-write MCU_PMU_SHUT_DOWN_BYPASS_CTRL Enable bypass mode to Control pmu shut down [2:2] read-write MCU_PMU_SHUT_DOWN_BYPASS Value of pmu shutdown in bypass mode [3:3] read-write MCU_BUCK_BOOST_ENABLE_BYPASS_CTRL Enable software control for buck boost enable [4:4] read-write MCU_BUCK_BOOST_ENABLE_BYPASS Value for MCU BuckBoost Enable in bypass mode [5:5] read-write RES reserved1 [31:6] read-write MCU_PMU_LDO_CTRL_SET MCU PMU LD0 control set register 0x68 32 read-write 0x00060007 MCU_FLASH_LDO_EN Enable Flash LDO from M4SS [0:0] read-write MCU_SCO_LDO_EN Enable SoC LDO from M4SS [1:1] read-write MCU_DCDC_EN Enable PMU DCDC from M4SS [2:2] read-write RESER reserved1 [16:3] read-write MCU_SOC_LDO_LVL PMU SOC LDO High and Low Voltage selection [17:17] read-write MCU_DCDC_LVL PMU DCDC High and Low Voltage selection [18:18] read-write RES reserved1 [31:19] read-write MCU_PMU_LDO_CTRL_CLEAR MCU PMU LD0 control clear register 0x6c 32 read-write 0x00060007 MCU_FLASH_LDO_EN Enable Flash LDO from M4SS [0:0] read-write MCU_SOC_LDO_EN Enable SoC LDO from M4SS [1:1] read-write MCU_DCDC_EN Enable PMU DCDC from M4SS [2:2] read-write RESER reserved1 [16:3] read-write MCU_SOC_LDO_LVL PMU SOC LDO High and Low Voltage selection [17:17] read-write MCU_DCDC_LVL PMU DCDC High and Low Voltage selection [18:18] read-write RES reserved1 [31:19] read-write PLLCCI_PWRCTRL_REG PLL CCI power control register 0x80 32 read-write 0x00000080 I2SPLL_ISO_EN Enables software based control of isolation and reset for I2SPLL [0:0] read-write I2SPLL_BYPASS_ISO_GEN Isolation value [1:1] read-write INTFPLL_ISO_EN Enables software based control of isolation and reset for INTF PLL [2:2] read-write INTFPLL_BYPASS_ISO_GEN Isolation value [3:3] read-write SOCPLL_ISO_ENABLE Enables software based control of isolation and reset for SOCPLL [4:4] read-write SOCPLL_BYPASS_ISO_GEN Isolation value [5:5] read-write SOCPLL_SPI_PG_EN SOCPLL SPI Power Control [6:6] read-write SOCPLL_VDD13_ISO_EN SOCPLL MACRO POC Control [7:7] read-write RES reserved1 [31:8] read-write DLL_PWRCTRL_REG DLL power control register 0x84 32 read-write 0x00000044 QSPI_DLL_RX_ISO_ENABLE Enables software based control of isolation and reset for QSPI_DLL_TX [0:0] read-write QSPI_DLL_RX_BYPASS_ISO_GEN Isolation value [1:1] read-write QSPI_DLL_RX_PG_EN_N QPSI DLL RX Power Control [2:2] read-write RESER reserved1 [3:3] read-write QSPI_DLL_TX_ISO_ENABLE Enables software based control of isolation and reset for QSPI_DLL_TX [4:4] read-write QSPI_DLL_TX_BYPASS_ISO_GEN Isolation value [5:5] read-write QSPI_DLL_TX_PG_EN_N QPSI DLL TX Power Control [6:6] read-write RESERVED1 reserved1 [31:7] read-write MCU_FSM 1.0 This is explain the Sleep FSM registers. MCU_FSM 0x24048100 32 read-write 0x00 0x4C registers MCU_FSM_SLEEP_CTRLS_AND_WAKEUP_MODE Sleep Control Signals and Wakeup source selection 0x00 32 read-write 0x00000000 MCUFSM_SHUTDOWN_ENABLE shutdown enable pulse. [0:0] read-write Reserved1 It is recommended to write these bits to 0. [1:1] read-write LP_SLEEP_MODE_b setting this bit enables retention of TASS-RAM, M4SS-RAM in PS2 Active/Sleep state [2:2] read-write disable Writing 1 to this enables Retention during sleep 0 enable Writing 1 to this enables Retention during sleep 1 M4SS_RAM_RETENTION_MODE_EN shutdown enable pulse. [3:3] read-write M4ULP_RAM_RETENTION_MODE_EN_b RAM retention enable for ULP M4 ram during deep sleep [4:4] read-write TA_RAM_RETENTION_MODE_EN RAM retention enable for ta ram during deep sleep [5:5] read-write ULPSS_RAM_RETENTION_MODE_EN RAM retention enable for ulpss ram during deep sleep [6:6] read-write M4ULP_RAM16K_RETENTION_MODE_EN To enable retention mode for m4ulp 16k RAM [7:7] read-write LDO_SOC_ON_b ON ldo soc during deep sleep [8:8] read-write LDO_FLASH_ON_b ON flash ldo during deep sleep [9:9] read-write PMU_DCDC_ON_b 1: PMU DCDC(BUCK) ON,0: PMU DCDC(BUCK) OFF. [10:10] read-write SKIP_XTAL_WAIT_TIME 1 : Skips Xtal Good Delay wait time. [11:11] read-write Reserved2 It is recommended to write these bits to 0. [13:12] read-write MCUFSM_WAKEUP_NWPFSM When Set, mcufsm wakeup enable will wakeup both NWP FSM and MCU FSM.Clear this BIT if this feature is not required.. [14:14] read-write SLEEP_WAKEUP Wakeup indication from Processor [15:15] read-write TIMER_BASED_WAKEUP_b wakeup enable after deep sleep counter elapses [16:16] read-write HOST_BASED_WAKEUP_b host based wakeup enable [17:17] read-write WIRELESS_BASED_WAKEUP_b wireless based wakeup enable [18:18] read-write M4_PROC_BASED_WAKEUP_b wakeup based on m4 processor enable [19:19] read-write GPIO_BASED_WAKEUP_b wakeup on gpio interrupt enable based in configuration in GPIO WAKEUP REGISTER [20:20] read-write COMPR_BASED_WAKEUP_b compartor based wakeup enable, either of any 6 comparator interrupts [21:21] read-write Reserved3 It is recommended to write these bits to 0. [22:22] read-write WIC_BASED_WAKEUP_b WIC based wakeup mask [23:23] read-write ULPSS_BASED_WAKEUP_b ULPSS peripheral based wakeup [24:24] read-write SDCSS_BASED_WAKEUP_b Sensor Data collector based wakeup [25:25] read-write ALARM_BASED_WAKEUP_b Alarm Based wakeup [26:26] read-write SEC_BASED_WAKEUP_b Second Pulse Based wakeup [27:27] read-write MSEC_BASED_WAKEUP_b Millisecond Pulse Based wakeup [28:28] read-write WDT_INTR_BASED_WAKEUP_b Millisecond Pulse Based wakeup [29:29] read-write ULPSS_BASED_SLEEP ULPSS initiated DeepSleep. [30:30] read-write SDCSS_BASED_SLEEP SDCSS initiated DeepSleep. [31:31] read-write MCU_FSM_PERI_CONFIG_REG Configuration for Ultra Low-Power Mode of the processor (PS2 State) 0x04 32 read-write 0x00000000 ULP_MCU_MODE_EN Enables voltage switching for PS2-PS4/PS3 and PS4/PS3-PS2 state transitions. [0:0] read-write disable Writing 0 to this disables voltage switching for PS2-PS4/PS3 state transition 0 enable Writing 1 to this enables voltage switching for PS4/PS3-PS2 state transition. 1 M4SS_CONTEXT_SWITCH_TOP_ULP_MODE Enable functional switching for PS2-PS4/PS3 and PS4/PS3-PS2 state transitions [2:1] read-write WICENREQ Its enable or disable maximum of 32KB of LP-SRAM for operation in PS2 state [3:3] read-write Reserved1 It is recommended to write these bits to 0. [15:4] read-write BGPMU_SAMPLING_EN_R Controls the mode of Band-Gap for DC-DC 1.35 during PS2 state. [16:16] read-write disable Writing 0 to this disables sampling mode of Band-Gap. This is described in Power Management Section. 0 enable Writing 1 to this enables sampling mode of Band-Gap. This is described in Power Management Section. 1 Reserved2 It is recommended to write these bits to 0. [31:17] read-write GPIO_WAKEUP_REGISTER GPIO Wakeup Register 0x08 32 read-write 0x00000000 GPIO_0_WAKEUP Enable gpio 0 based wakeup. [0:0] read-write GPIO_1_WAKEUP Enable gpio 1 based wakeup [1:1] read-write GPIO_2_WAKEUP Enable gpio 2 based wakeup [2:2] read-write GPIO_3_WAKEUP Enable gpio 3 based wakeup [3:3] read-write GPIO_4_WAKEUP Enable gpio 3 based wakeup [4:4] read-write Reserved1 It is recommended to write these bits to 0. [15:5] read-write CONTINIOUS_START Trigger Deep sleep timer to start counting. [16:16] read-write CONTINIOUS_TIMER_ENABLE Enable Deep sleep timer mode continuous. [17:17] read-write DS_TIMER_SOFT_RESET Enable Deep sleep timer mode continuous. [18:18] read-write Reserved2 It is recommended to write these bits to 0. [31:19] read-write MCU_FSM_DEEP_SLEEP_DURATION_LSB_REG MCU FSM DEEP SLEEP DURATION LSB Register 0x0C 32 read-write 0x00000000 MCUFSM_DEEPSLEEP_DURATION_COUNT LSB bits of deep sleep duration counter after which system wakes up is timeout wakeup is enabled. [31:0] read-write MCU_FSM_XTAL_AND_PMU_GOOD_COUNT_REG MCU FSM XTAL AND PMU GOOD COUNT Register 0x10 32 read-write 0x000F000F MCUFSM_PMU_POWERGOOD_DURATION_COUNT Wait Delay for PMU POWER GOOD 0 - 5us 1 - 10us 2 - 12.5us 3 - 25us 4 - 50us 5 - 75us. [4:0] read-write Reserved1 It is recommended to write these bits to 0. [15:5] read-write MCUFSM_XTAL_GOODTIME_DURATION_COUNT Wait Delay for XTAL GOOD Time 0 - 5us 1 - 10us. [20:16] read-write Reserved2 It is recommended to write these bits to 0. [31:21] read-write MCU_FSM_POWER_CTRL_AND_DELAY Power Control and Delay Configuration for Ultra Low-Power Mode of the processor (PS2 State) 0x14 32 read-write 0x0FF80000 PS2_PMU_LDO_OFF_DELAY PMU BUCK And LDO Turn-OFF Delay. [4:0] read-write Reserved1 It is recommended to write these bits to 0. [7:5] read-write PS4_SOCLDO_ON_DELAY PMU SOCLDO Turn-ON Delay. [11:8] read-write 50 Configure switching 50us ON time of LDO Soc. 0 100 Configure switching 100us ON time of LDO Soc. 1 200 Configure switching 200us ON time of LDO Soc. 2 300 Configure switching 300us ON time of LDO Soc. 3 400 Configure switching 400us ON time of LDO Soc. 4 500 Configure switching 500us ON time of LDO Soc. 5 600 Configure switching 600us ON time of LDO Soc. 6 700 Configure switching 700us ON time of LDO Soc. 7 800 Configure switching 800us ON time of LDO Soc. 8 900 Configure switching 900us ON time of LDO Soc. 9 1000 Configure switching 1000us ON time of LDO Soc. 10 1100 Configure switching 1100us ON time of LDO Soc. 11 1200 Configure switching 1200us ON time of LDO Soc. 12 1300 Configure switching 1300us ON time of LDO Soc. 13 1400 Configure switching 1400us ON time of LDO Soc. 14 1500 Configure switching 1400us ON time of LDO Soc. 15 PG4_BUCK_ON_DELAY PMU Buck Turn-ON Delay. [15:12] read-write 50 Configure switching 50us ON time of DC-DC. 0 100 Configure switching 100us ON time of DC-DC. 1 200 Configure switching 200us ON time of DC-DC. 2 300 Configure switching 300us ON time of DC-DC. 3 400 Configure switching 400us ON time of DC-DC. 4 500 Configure switching 500us ON time of DC-DC. 5 600 Configure switching 600us ON time of DC-DC. 6 700 Configure switching 700us ON time of DC-DC. 7 800 Configure switching 800us ON time of DC-DC. 8 900 Configure switching 900us ON time of DC-DC. 9 1000 Configure switching 1000us ON time of DC-DC. 10 1100 Configure switching 1100us ON time of DC-DC. 11 1200 Configure switching 1200us ON time of DC-DC. 12 1300 Configure switching 1300us ON time of DC-DC. 13 1400 Configure switching 1400us ON time of DC-DC. 14 1500 Configure switching 1400us ON time of DC-DC. 15 FSM_PERI_SOC_LDO_EN Enable SOCLDO in Peri mode. [16:16] read-write OFF Writing 0 to this configures LDO SoC 1.1 in OFF state during PS2. 0 ON Writing 1 to this configures LDO SoC 1.1 to ON state during PS2. 1 FSM_PERI_DCDC_EN Enable DCDC in Peri mode. [17:17] read-write OFF Writing 0 to this configures DC-DC 1.35 in OFF state during PS2. 0 ON Writing 1 to this configures DC-DC 1.35 to ON state during PS2. 1 Reserved2 It is recommended to write these bits to 0. [18:18] read-write POWER_MUX_SEL_ULPSS Select value for ULPSS(Peripherals) Power Mux [19:19] read-write 0 DC-DC 0.95. 0 1 LDO SoC 1.1 1 POWER_MUX_SEL_M4_ULP Select value for M4 ULP (Peripherals + Cortex Core )Power Mux. [21:20] read-write 0 LDO 0.7V 0 1 DC-DC 0.95 1 3 LDO SoC 1.1 3 POWER_MUX_SEL_M4_ULP_RAM_16K Select value for M4 ULP RAM 16K Power Mux [23:22] read-write 0 LDO 0.7V 0 1 DC-DC 0.95 1 3 LDO SoC 1.1 3 POWER_MUX_SEL_M4_ULP_RAM Select value for M4 ULP RAM Power Mux. [25:24] read-write POWER_MUX_SEL_ULPSS_RAM Select value for ULPSS RAM Power Mux. [27:26] read-write Reserved3 It is recommended to write these bits to 0. [31:28] read-write MCU_FSM_CLKS_REG MCU FSM Clocks Register 0x18 32 read-write 0x02D48000 Reserved1 It is recommended to write these bits to 0. [1:0] read-write HF_FSM_CLK_SELECT Disable signal for m4ss reference clock. [4:2] read-write Reserved2 It is recommended to write these bits to 0. [14:5] read-write HF_FSM_CLK_SWITCHED_SYNC If high freq fsm clock select is modified. [15:15] read-write HF_FSM_CLK_FREQ High Frequency Source Clock value in MHz. [21:16] read-write US_DIV_COUNT One Micro second division factor. Program value to 3. If hf_fsm_gen_2mhz is 0 Program value to 1. If hf_fsm_gen_2mhz is 1. [23:22] read-write HF_FSM_GEN_2MHZ Enable 2Mhz clock for FSM 1 -Enable 2Mhz option 0- Enable 4MHz option. [24:24] read-write HF_FSM_CLK_EN high frequency mcu fsm clock enable. [25:25] read-write Reserved3 It is recommended to write these bits to 0. [31:26] read-write MCU_FSM_REF_CLK_REG MCU FSM Clocks Register 0x1C 32 read-write 0x01011101 M4SS_REF_CLK_SEL Dynamic Reference Clock Mux select of M4SS 0 - Clock will be gated at dynamic mux output of M4SS 1 - ulp_mhz_rc_byp_clk 2 - ulp_mhz_rc_clk 3 - rf_ref_clk 4 - mems_ref_clk 5 - ulp_20mhz_ringosc_clk 6 - ulp_doubler_clk 7 - ref_byp_clk to TASS. [2:0] read-write Reserved1 It is recommended to write these bits to 0. [6:3] read-write M4SS_REF_CLK_CLEANER_OFF_b Disable signal for m4ss reference clock. [7:7] read-write M4SS_REF_CLK_CLEANER_ON_b Enable clk cleaner for m4ss reference clock. [8:8] read-write Reserved2 It is recommended to write these bits to 0. [11:9] read-write TASS_REF_CLK_SEL Dynamic Reference Clock Mux select of TASS controlled by M4. 0 : Clock will be gated at dynamic mux output of TASS 1 : ulp_mhz_rc_byp_clk 2 : ulp_mhz_rc_clk 3 : rf_ref_clk 4 : mems_ref_clk 5 : ulp_20mhz_ringosc_clk 6 : ref_byp_clk to TASS. [14:12] read-write Reserved3 It is recommended to write these bits to 0. [15:15] read-write ULPSS_REF_CLK_SEL_b Dynamic Reference Clock Mux select of TASS controlled by M4. 0 : Clock will be gated at dynamic mux output of TASS 1 : ulp_mhz_rc_byp_clk 2 : ulp_mhz_rc_clk 3 : rf_ref_clk 4 : mems_ref_clk 5 : ulp_20mhz_ringosc_clk 6 : ref_byp_clk to TASS. [18:16] read-write Reserved4 It is recommended to write these bits to 0. [22:19] read-write ULPSS_REF_CLK_CLEANER_OFF_b Clock cleaner Off signal for ulpss ref clock. [23:23] read-write ULPSS_REF_CLK_CLEANER_ON_b Clock cleaner Off signal for ulpss ref clock. [24:24] read-write Reserved5 It is recommended to write these bits to 0. [27:25] read-write SDCSS_CLK_SEL_b select between RC / RO 32KHz clk in sdcss 01 - 32MHz RC Clock 10- 20MHz RO Clock. [29:28] read-write SDCSS_CLK_EN_b To enable dynamic clock for sdcss [30:30] read-write SDCSS_STATIC_CLK_EN_b To enable static clk for sensor data collector subsystem [31:31] read-write MCU_FSM_CLK_ENS_AND_FIRST_BOOTUP MCU FSM And First Bootup 0x20 32 read-write 0x004B0000 FIRST_BOOTUP_MCU_N_b Indication for S/W to distinguish b/w First Power or ULP wakeup.S/W need to set this Bit after first power .. [0:0] read-write RAM_RETENTION_STATUS_M4SS_b Indicates to S/W that RAM's were in retention mode during Sleep time. 1 - RAM are in retention mode during sleep. 0 - RAM are not in retention mode during sleep.Domain is OFF.. [1:1] read-only RETENTION_DOMAIN_ON_b Indicates to S/W that Retention domain is ON. 1 - Domain is ON. 0 - Domain is OFF.. [2:2] read-write CHIP_MODE_VALID_b Indicates to S/W that ChipMode programming are valid and need not read EFUSE. 1 - ChipMode are Valid. 0 - ChipModes are invalid. [3:3] read-write STORAGE_DOMAIN_ON_b Indicates to S/W that MCU Data Storage 1 domain is ON. 1 - Domain is ON. 0 - Domain is OFF.. [4:4] read-write Reserved1 It is recommended to write these bits to 0. [14:5] read-write MCU_FSM_RESET_N_SYNC_b Indicated MCU FSM is out of reset. 1 : Indicated MCU FSM is out of reset 0 : Indicated MCU FSM is in reset. [15:15] read-write MCU_ULP_32KHZ_RC_CLK_EN_b Enables ULP 32KHz Rc Clock. [16:16] read-write MCU_ULP_32KHZ_RO_CLK_EN_b Enables ULP 32KHz RO Clock. [17:17] read-write MCU_ULP_32KHZ_XTAL_CLK_EN_b Enables ULP 32KHz Xtal Clock. [18:18] read-write MCU_ULP_MHZ_RC_CLK_EN_b Enables ULP 32MHz RC Clock. [19:19] read-write MCU_ULP_20MHZ_RING_OSC_CLK_EN_b Enables ULP 20mhz RO Clock. [20:20] read-write MCU_ULP_DOUBLER_CLK_EN_b Enables ULP Doubler Clock. [21:21] read-write MCU_ULP_40MHZ_CLK_EN_b Enables 40MHz XTAL clock. [22:22] read-write Reserved2 It is recommended to write these bits to 0. [31:23] read-write MCU_FSM_CRTL_PDM_AND_ENABLES Power Domains Controlled by Sleep FSM. 0x24 32 read-write 0x000F0018 ENABLE_WDT_IN_SLEEP_b Its enable or disable WDT during Sleep/Shutdown states. [0:0] read-write disable Writing 0 to this enables WDT during Sleep/Shutdown states. 0 enable Writing 1 to this enables WDT during Sleep/Shutdown states. 1 ENABLE_WURX_DETECTION_b Its enable or disable detection of On-Air Pattern using Wake-Fi Rx. [1:1] read-write disable Writing 0 to this disables detection of On-Air Pattern using Wake-Fi Rx. 0 enable Writing 1 to this enables detection of On-Air Pattern using Wake-Fi Rx. 1 RESET_MCU_BBF_DM_EN_b Its enable or disable reset of Power Domain Control Battery FF's on wakeup. [2:2] read-write disable Writing 0 to this disables reset of Power Domain Control Battery FF's on wakeup. 0 enable Writing 1 to this enables reset of Power Domain Control Battery FF's on wakeup 1 DISABLE_TURNOFF_SRAM_PERI_b Enable MCU SRAM periphery during Deepsleep 1 - Enable SRAM periphery during Deepsleep 0 - Disable SRAM periphery during Deepsleep. [3:3] read-write ENABLE_SRAM_DS_CRTL_b Enable signal for controlling Deepsleep signal of all SRAM used by M4 1- Enable SRAM Deepsleep Signal 0- Disable SRAM Deepsleep Signal. [4:4] read-write Reserved1 It is recommended to write these bits to 0. [15:5] read-write POWER_ENABLE_FSM_PERI_b Its enable or disable Power to Low-Power FSM. [16:16] read-write disable Writing 0 to this disables Power to Low-Power FSM. 0 enable Writing 1 to this enables Power to Low-Power FSM. 1 POWER_ENABLE_TIMESTAMPING_b Its enable or disable Power to TIMESTAMP. [17:17] read-write disable Writing 0 to this disables Power to TIMESTAMP. 0 enable Writing 1 to this enables Power to TIMESTAMP. 1 POWER_ENABLE_DEEPSLEEP_TIMER_b Its enable or disable Power to DEEP SLEEP Timer. [18:18] read-write disable Writing 0 to this disables Power to DEEP SLEEP Timer. 0 enable Writing 1 to this enables Power to DEEP SLEEP Timer. 1 POWER_ENABLE_RETENTION_DM_b Its enable or disable Power to Retention Flops during SHIP state.These Flops are used for storing Chip Configuration. [19:19] read-write disable Writing 0 to this disables Power to Retention Flops during SHIP state. These Flops are used for storing Chip Configuration. 0 enable Writing 1 to this enables Power to Retention Flops during SHIP state. These Flops are used for storing Chip Configuration. 1 Reserved2 It is recommended to write these bits to 0. [31:20] read-write MCU_GPIO_TIMESTAMPING_CONFIG MCU GPIO TIMESTAMPING CONFIG. 0x28 32 read-write 0x00000000 ENABLE_GPIO_TIMESTAMPING_b Enable GPIO time stamping Feature.. [0:0] read-write TIMESTAMPING_ON_GPIO0_b Enable GPIO time stamping on GPIO0. [1:1] read-write TIMESTAMPING_ON_GPIO1_b Enable GPIO time stamping on GPIO1. [2:2] read-write TIMESTAMPING_ON_GPIO2_b Enable GPIO time stamping on GPIO2. [3:3] read-write TIMESTAMPING_ON_GPIO3_b Enable GPIO time stamping on GPIO3. [4:4] read-write TIMESTAMPING_ON_GPIO4_b Enable GPIO time stamping on GPIO4. [5:5] read-write Reserved1 It is recommended to write these bits to 0. [31:6] read-write MCU_GPIO_TIMESTAMP_READ MCU GPIO TIMESTAMPING READ. 0x2C 32 read-only 0x00000000 GPIO_EVENT_COUNT_PARTIAL Counter value indicating the duration from GPIO going high to first Sleep clock( MCU FSM Clock) posedge from GPIO going high with respect to 32MHz clock. [10:0] read-only Reserved1 It is recommended to write these bits to 0. [15:11] read-only GPIO_EVENT_COUNT_FULL Counter value indicating number for 32MHz clock present in 1 Sleep clock (MCU FSM Clock). [26:16] read-only Reserved2 It is recommended to write these bits to 0. [31:27] read-only MCU_SLEEPHOLD_REQ MCU SLEEP HOLD REQ. 0x30 32 read-write 0x00000003 SLEEPHOLDREQn Sleepholdreq when enable will gate the clock to M4. 1 - Sleepholdreq is Disabled. 0 - Sleepholdreq is Enabled. [0:0] read-write SLEEPHOLDACKn SLEEPHOLDACK response to SLEEPHOLDREQ. [1:1] read-only Reserved1 It is recommended to write these bits to 0. [15:2] read-write SELECT_FSM_MODE Enable for selecting secondary FSM. 1 - Select Secondary FSM 0 - Select Primary FSM. [16:16] read-write Reserved2 It is recommended to write these bits to 0. [31:17] read-write MCU_FSM_WAKEUP_STATUS_REG MCU FSM Wakeup Status Register. 0x38 32 read-write 0x00000000 WAKEUP_STATUS To know the wakeup source. [10:0] read-write Reserved1 It is recommended to write these bits to 0. [15:11] read-write MCU_FIRST_POWERUP_POR Indication to Processor that system came out first power up. [16:16] read-write MCU_FIRST_POWERUP_RESET_N Indication to Processor that system came out of Reset. [17:17] read-write Reserve2 It is recommended to write these bits to 0. [31:18] read-write MCU_FSM_WAKEUP_STATUS_CLEAR MCU FSM Wakeup Status Clear. 0x3C 32 read-write 0x00000000 WWD_INTERRUPT_STATUS_CLEAR_b To Clear WatchDog Interrupt status indication. [0:0] read-write MILLI_SEC_BASED_STATUS_CLEAR_b To Clear Milli-Second Wakeup status indication. [1:1] read-write RTC_SEC_BASED_STATUS_CLEAR_b To Clear Second Tick wakeup status indication. [2:2] read-write RTC_ALARM_BASED_WAKEUP_STATUS_CLEAR_b To Clear RTC Alarm wakeup status indicaition. [3:3] read-write COMP1_BASED_WAKEUP_STATUS_CLEAR_b To Clear comp1 wakeup (Analog IP1 and Analog IP2) status indication. [4:4] read-write COMP2_BASED_WAKEUP_STATUS_CLEAR_b To Clear comp2 wakeup (Analog IP1 and BandGap Scale) status indication. [5:5] read-write COMP3_BASED_WAKEUP_STATUS_CLEAR_b To Clear comp3 wakeup (Analog IP1 and VBatt Scale) status indication. [6:6] read-write COMP4_BASED_WAKEUP_STATUS_CLEAR_b To Clear Comp4 wakeup (Bandgap En and VBatt Scale) status indication. [7:7] read-write COMP5_BASED_WAKEUP_STATUS_CLEAR_b To Clear BOD Wakeup status indication. [8:8] read-write COMP6_BASED_WAKEUP_STATUS_CLEAR_b To Clear Button-wake status indication. [9:9] read-write RF_WAKEUP_CLEAR_b To Clear WuRX status indication. [10:10] read-write Reserved1 It is recommended to write these bits to 0. [31:11] read-write MCU_FSM_PMU_STATUS_REG MCU FSM PMU Status Register. 0x40 32 read-write 0x00000000 SCDCDC_LP_MODE_EN SCDC in LP mode. [0:0] read-write BGPMU_SLEEP_EN_R_b Sleep en for BG PMU. [1:1] read-write Reserved1 It is recommended to write these bits to 0. [16:2] read-write STANDBY_LDORF_R Standby state for LDO RF. [17:17] read-write STANDBY_LDOSOC_R Standby state for LDO soc. [18:18] read-write STANDBY_DC1P3_R Standby state for DC1p3. [19:19] read-write POWERGOOD_LDOSOC Powergood signal from ldosoc. [20:20] read-only LEVEL_OK_DC1P3 Powergood signal from LDORF. [21:21] read-only CL_FLAG_DC1P3 Powergood signal read for DC 1.3V. [22:22] read-only Reserved2 It is recommended to write these bits to 0. [31:23] read-write MCU_FSM_PMUX_CTRLS_RET MCU FSM PMUX Controls Retention. 0x44 32 read-write 0x00000000 POWER_SW_CTRL_TASS_RAM_IN_RETAIN Select value for TASS RAM Power Mux In Retention mode [0:0] read-write POWER_SW_CTRL_M4SS_RAM_IN_RETAIN Select value for M4SS RAM Power Mux In Retention mode [1:1] read-write POWER_SW_CTRL_M4ULP_RAM_IN_RETAIN Select value for M4ULP RAM Power Mux In Retention mode [3:2] read-write POWER_SW_CTRL_M4ULP_RAM16K_IN_RETAIN Select value for M4ULP 16K RAM Power Mux In Retention mode [5:4] read-write POWER_SW_CTRL_ULPSS_RAM_IN_RETAIN Select value for ULPSS RAM Power Mux In Retention mode [7:6] read-write Reserved1 It is recommended to write these bits to 0. [31:8] read-write MCU_FSM_TOGGLE_COUNT MCU FSM Toggle Count. 0x48 32 read-write 0x00000000 TOGGLE_COUNT_RSTART Start counting GIPO Toggles. [0:0] write-only Reserved1 It is recommended to write these bits to 0. [14:1] read-write LATCH_TOGGLE_DATA Trigger indication to read GPIO toggle data. [15:15] write-only GPIO_TOGGLE_COUNT GPIO toogle data count. [27:16] read-only Reserved2 It is recommended to write these bits to 0. [30:28] read-write TOGGLE_DATA_READY GPIO toogle data count. [31:31] read-only MCU_ProcessSensor 1.0 The process sensor module, count the process clock (high frequency ring clock) over one MCU FSM clock and divide this clock by programmable value. ProcessSensor 0x24048540 32 read-write 0x00 0x04 registers PROCESS_SENSOR_ENABLE_AND_READ Process sensor enable and read for operation 0x00 32 read-write 0x00000040 PROCESS_SENSOR_EN enable or on the process sensor,if this bit is set the sensor enable else sensor is disable. [0:0] read-write PS_RING_CLK_START Start Ring-Oscillator clock for estimating process corner. [1:1] read-write PS_CLK_SW_ON Clock cleaner on signal to clock cleaner block on clock generated by delay chain. [2:2] read-write PS_CLK_SW_OFF Clock cleaner off signal to clock cleaner block on clock generated by delay chain. [3:3] read-write NUM_CYCLES Number of MCU FSM clock(32KHz)for which measurement need to be done.if bits is 1 then 1 clock, 2 then 2 clocks,3 then 3 clocks,4 then 4 clocks. [5:4] read-write PS_MEAS_DONE_SYNC Processor sensor measurement done. [6:6] read-only RESERVED1 Reserved1 [15:7] read-write PS_COUNT Processor sensor read back [31:16] read-only MCU_RET 1.0 NPSS has Retention domain logic which is a power domain . This domain consisted all logic which will turned off if none of the M4 memories are retained. MCU_RET 0x24048600 32 read-write 0x00 0x30 registers MCURET_QSPI_WR_OP_DIS MCURET QSPI WR OP DIS 0x00 32 read-write 0x00000000 M4SS_QSPI_WRSR_WR_OP_DISABLE M4SS Write operation disable to Flash. 1 - Write Operation to Flash is not allowed. 0 - Write Operation to Flash is allowed. [0:0] read-write TASS_QSPI_WRSR_WR_OP_DISABLE TASS Write operation disable to Flash. 1 - Write Operation to Flash is not allowed. 0 - Write Operation to Flash is allowed. [1:1] read-only RESERVED1 Reserved1 [31:2] read-write MCURET_BOOTSTATUS MCURET BOOT Status 0x04 32 read-only 0x00000000 BOOT_STATUS Boot Status/Configuration information to MCU [0:0] read-only RESERVED1 Reserved1 [31:1] read-only CHIP_CONFIG_MCU_READ MCURET BOOT Status 0x0C 32 read-only 0x00000000 DISABLE_M4 When set, disables the M4 by clock gating and putting M4 in reset [0:0] read-only LIMIT_M4_FREQ_110MHZ_b When set, limits the M4SS SoC clock to Max clock/2 [1:1] read-only DISABLE_M4_ULP_MODE When set, limits the M4SS SoC clock to Max clock/2 [2:2] read-only RESERVED1 Reserved1 [9:3] read-only M4_FLASH_SIZE 0xx - Unrestricted 100 - Auto mode accesses to flash are restricted to 4 MBit 101 - Auto mode accesses to flash are restricted to 8 MBit 110 - Auto mode accesses to flash are restricted to 16 MBit 111 - Auto mode accesses to flash are restricted to 32 MBit [12:10] read-only DISABLE_FIM_COP When set, disable FIMV [13:13] read-only DISABLE_VAP When set, disables VAD [14:14] read-only DISABLE_TOUCH When set, disables touch interface [15:15] read-only RESERVED2 Reserved2 [16:16] read-only DISABLE_ANALOG_PERIPH When set, disables analog peripherals [17:17] read-only DISABLE_JTAG When set, disable JTAG interface(both M4 and TA) [18:18] read-only DISABLE_M4SS_KH_ACCESS When set, disables access to key in the key holder from M4SS QSPI [19:19] read-only DISABLE_M4SS_ACCESS_FRM_TASS_SEC When set, M4 can not access TASS memory or registers except for host communication registers [20:20] read-only RESERVED3 Reserved3 [31:21] read-only MCUAON_CTRL_REG4 MCURET Control Register4 0x10 32 read-write 0x00000000 RESERVED1 Reserved1 [15:0] read-write ULP_GPIO_2_TEST_MODE_OUT_SEL NPSS Test modes [19:16] read-write ULP_GPIO_1_TEST_MODE_OUT_SEL NPSS Test modes [23:20] read-write ULP_GPIO_0_TEST_MODE_OUT_SEL NPSS Test modes [27:24] read-write ULP_GPIOS_IN_TEST_MODE NPSS Test modes [28:28] read-write RESERVED2 Reserved2 [31:29] read-write 5 0x04 0-4 NPSS_GPIO_CNTRLn NPSS GPIO related registers (0-4) 0x001C NPSS_GPIO_n__CTRLS NPSS GPIO Control register 0x00 32 read-write 0x00000000 NPSS_GPIO_MODE NPSS GPIO 0 mode select. [2:0] read-write NPSS_GPIO_REN NPSS GPIO 0 Input Buffer Enable. 1- Enable 0- Disable. [3:3] read-write NPSS_GPIO_OEN NPSS GPIO 0 Output Buffer Enable. 1- Input Direction 0- Output Direction. [4:4] read-write NPSS_GPIO_OUT NPSS GPIO 0 Output value. [5:5] read-write RESERVED1 Reserved1 [7:6] read-write NPSS_GPIO_POLARITY NPSS GPIO 0 Polarity 1 - When signal is High 0 - When signal is Ligh. [8:8] read-write RESERVED2 Reserved2 [15:9] read-write USE_ULPSS_PAD Input from ULPSS GPIOs. [16:16] read-write RESERVED3 Reserved3 [31:17] read-write MCU_TEMP 1.0 The temperature sensor is used to read the temperature by using APB registers, which is access through direct to ULPSS system. TEMPSENSOR 0x24048500 32 read-write 0x00 0x14 registers TS_ENABLE_AND_TEMPERATURE_DONE Temperature sensor enable and measurement calculation done indication register 0x00 32 read-write 0x000003FC TEMP_SENS_EN Temperature sensing enable,self clearing register [0:0] write-only REF_CLK_SEL if this bit is zero then reference RO clock from analog,else this bit is one then MCU FSM clock [1:1] read-write CONT_COUNT_FREEZE Count of reference clock on which ptat clock counts [11:2] read-write TEMP_MEASUREMENT_DONE temperature measurement done indication. [12:12] read-only RESERVED1 reserved1 [31:13] read-write TS_SLOPE_SET temperature sensor slope set(slope will be change with respect to temperature change) 0x04 32 read-write 0x0000003B SLOPE This is one time measurement for one package after chip arrives from fab,this is signed bit. [9:0] read-write RESERVED1 Reserved1 [15:10] read-write TEMPERATURE_SPI temperature known [26:16] read-write TEMP_UPDATED temperature updated signal for the reg to capture this temperature. [27:27] write-only BJT_BASED_TEMP Temperature is updated through which is calculated using bjt based if bit is high(1) through spi and bit is low(0) then through calculation RO based [28:28] read-write RESERVED2 Reserved2 [31:29] read-write TS_FE_COUNTS_NOMINAL_SETTINGS determine calibrated temperature 0x08 32 read-write 0x0019010E F2_NOMINAL ptat clock count during calibration,This will vary with chip to chip. [9:0] read-write RESERVED1 Reserved1 [15:10] read-write NOMINAL_TEMPERATURE calibrated temperature [22:16] read-write RESERVED2 Reserved2 [31:23] read-write TS_COUNTS_READ temperature sensor count read. 0xC 32 read-only 0x00000000 COUNT_F2 [9:0] read-only RESERVED1 Reserved1 [15:10] read-only COUNT_F1 [25:16] read-only RESERVED2 Reserved2 [31:26] read-only TEMPERATURE_READ read the temperature 0x10 32 read-write 0x00000000 TEMPERATURE_RD Temperature value for read in signed format [10:0] read-only RES10 reserved10 [31:11] read-write UULP_Domain_Ctrl_REGs 1.0 NPSS has always ON domain logic which is not power gatable Which consistes of power, reset, isolation controls for different power domains in NPSS. MCU_AON 0x24048000 32 read-write 0x00 0x24 registers MCUAON_NPSS_PWRCTRL_SET_REG This register used for NPSS power control set register. 0x00 32 read-write 0x000003FE RES bit is reserved [0:0] read-write SLPSS_PWRGATE_EN_N_ULP_MCUBFFS MCU domain battery FF's power gate enable.If set,Power Supply is On clearing this bit has no effect. [1:1] read-write SLPSS_PWRGATE_EN_N_ULP_MCUFSM MCU FSM power gate enable,If set power supply is on clearing this bit has no effect. [2:2] read-write SLPSS_PWRGATE_EN_N_ULP_MCURTC MCU RTC power gate enable if set,power supply is on clearing this bit has no effect. [3:3] read-write SLPSS_PWRGATE_EN_N_ULP_MCUWDT MCU WDT power gate enable if set,power supply is on clearing this bit has no effect [4:4] read-write SLPSS_PWRGATE_EN_N_ULP_MCUPS MCU PS power gate enable.if set,power supply is on clearing this bit has no effect. [5:5] read-write SLPSS_PWRGATE_EN_N_ULP_MCUTS MCU temperature sensor power gate enable if set,power supply is on.clearing this bit has no effect [6:6] read-write SLPSS_PWRGATE_EN_N_ULP_MCUSTORE1 MCU Storage 1 power gate enable for 64-bit.if set,power supply is on,clearing this bit has no effect. [7:7] read-write SLPSS_PWRGATE_EN_N_ULP_MCUSTORE2 MCU Storage 2 power gate enable for 64-bit.if set,power supply is on,clearing this bit has no effect. [8:8] read-write SLPSS_PWRGATE_EN_N_ULP_MCUSTORE3 MCU Storage 3 power gate enable for 64-bit.if set,power supply is on,clearing this bit has no effect. [9:9] read-write SLPSS_PWRGATE_EN_N_ULP_TIMEPERIOD TIMEPERIOD power gate enable. [10:10] read-write RESERVED1 reserved1 [15:11] read-write SLPSS_PWRGATE_EN_N_ULP_NWPAPB_MCU_CTRL NWPAPB MCU control power gate enable [16:16] read-write RESERVED2 reserved2 [31:17] read-write MCUAON_NPSS_PWRCTRL_CLEAR_REG This register used for NPSS power control clear register. 0x04 32 read-write 0x000107FE RES bit is reserved [0:0] read-write SLPSS_PWRGATE_EN_N_ULP_MCUBFFS MCU domain battery FF's power gate enable.If set,Power Supply is OFF clearing this bit has no effect. [1:1] read-write SLPSS_PWRGATE_EN_N_ULP_MCUFSM MCU FSM power gate enable,If set power supply is OFF clearing this bit has no effect. [2:2] read-write SLPSS_PWRGATE_EN_N_ULP_MCURTC MCU RTC power gate enable if set,power supply is OFF clearing this bit has no effect. [3:3] read-write SLPSS_PWRGATE_EN_N_ULP_MCUWDT MCU WDT power gate enable if set,power supply is OFF clearing this bit has no effect [4:4] read-write SLPSS_PWRGATE_EN_N_ULP_MCUPS MCU PS power gate enable.if set,power supply is OFF clearing this bit has no effect. [5:5] read-write SLPSS_PWRGATE_EN_N_ULP_MCUTS MCU temperature sensor power gate enable if set,power supply is OFF.clearing this bit has no effect [6:6] read-write SLPSS_PWRGATE_EN_N_ULP_MCUSTORE1 MCU Storage 1 power gate enable for 64-bit.if set,power supply is OFF,clearing this bit has no effect. [7:7] read-write SLPSS_PWRGATE_EN_N_ULP_MCUSTORE2 MCU Storage 2 power gate enable for 64-bit.if set,power supply is OFF,clearing this bit has no effect. [8:8] read-write SLPSS_PWRGATE_EN_N_ULP_MCUSTORE3 MCU Storage 3 power gate enable for 64-bit.if set,power supply is OFF,clearing this bit has no effect. [9:9] read-write SLPSS_PWRGATE_EN_N_ULP_TIMEPERIOD TIMEPERIOD power gate enable. [10:10] read-write RESERVED1 reserved1 [15:11] read-write SLPSS_PWRGATE_EN_N_ULP_NWPAPB_MCU_CTRL NWPAPB MCU control power gate enable [16:16] read-write RESERVED2 reserved2 [31:17] read-write MCUAON_IPMU_RESET_CTRL This register used for ipmu reset control register 0x0C 32 read-write 0x00000003 ULP_ANALOG_SPI_RESET_N ULP Analog SPI Reset Signal, if bit is 1 then outoff reset,else in reset [0:0] read-write IPMU_SPI_RESET_N IPMU SPI Reset Signal,if bit is 1 then outoff reset,else in reset [1:1] read-write RESERVED1 reserved1 [31:2] read-write MCUAON_SHELF_MODE This register used for control shelf mode. 0x10 32 read-write 0x00280000 ENTER_SHELF_MODE Program 0xAAAA for entering shelf mode. [15:0] write-only SHUTDOWN_WAKEUP_MODE GPIO based wakeup mode configuration. [17:16] read-write SHELF_MODE_GPIOBASED GPIO based shelf mode entering,If set 1 by processor, On Falling edge of GPIO (Based on the option used in shutdown_wakeup_mode register) chip will enter Shelf mode. [18:18] read-write SHELF_MODE_WAKEUP_DELAY Programmable delay for resetting Chip during exit phase of shelf mode. [21:19] read-write RESERVED1 reserved1 [31:22] read-write MCUAON_GEN_CTRLS This register used for MCUON gen control mode. 0x14 32 read-write 0x00020000 XTAL_CLK_FROM_GPIO Select external 32KHz clock from NPSS GPIO's,if bit is 1 then select XTAL clock from GPIO Pins. Please refer to NPSS GPIO Pin muxing for configuration.else select XTAL clock from IPMU clock sources. [0:0] read-write ULP_ANALOG_WAKEUP_ACCESS ULP analog wakeup Source Access,if bit is 1 then TASS else bit is 0 then M4SS. [1:1] read-write RES reser [15:2] read-write ENABLE_PDO Enable turning Off POD power domain when SOC_LDO EN is low,When Set to 1, Up on SoC LDO Enable going low, IO supply (3.3v)to SOC Pads will be tuned-off. [16:16] read-write NPSS_SUPPLY_0P9 keep npss supply always at 0.9V,if bit is 1 then npss supply always at 0.9V else bit is zero then npss supply will switch from 0.6V to 0.9V based on high frequency enables. [17:17] read-write RESERVED1 reser [31:18] read-write MCUAON_PDO_CTRLS This register used for MCUON PDO control mode. 0x18 32 read-write 0x00000000 SOC_B_IO_DOMAIN_EN_B Turn-Off IO supply of SOC domain on bottom side,if bit is 1 then turn-off and 0 then turn on [0:0] read-write SOC_L_IO_DOMAIN_EN_B Turn-Off IO supply of SOC domain on left side,if bit is 1 then turn-off and 0 then turn on [1:1] read-write SOC_T_IO_DOMAIN_EN_B Turn-Off IO supply of SOC domain on top side,if bit is 1 then turn-off and 0 then turn on [2:2] read-write QSPI_IO_DOMAIN_EN_B Turn-Off IO supply of QSPI domain,if bit is 1 then turn-off and 0 then turn on [3:3] read-write SDIO_IO_DOMAIN_EN_B Turn-Off IO supply of SDIO domain.,if bit is 1 then turn-off and 0 then turn on [4:4] read-write RES reser [31:5] read-write MCUAON_WDT_CHIP_RST This register used for wdt chip reset purpose. 0x1C 32 read-write 0x00000001 MCU_WDT_BASED_CHIP_RESET When cleared, Up on host reset request.Power-On Reset (POR) will be generated [0:0] read-write RESERVED1 reserved1 [31:1] read-write MCUAON_KHZ_CLK_SEL_POR_RESET_STATUS This register used for khz clock select and reset status 0x20 32 read-write 0x00000008 AON_KHZ_CLK_SEL NPSS AON KHz clock selection,if 001 Khz RO clock select,else if 010 - Khz RC clock select,else 100 Khz Xtal clock select [2:0] read-write AON_KHZ_CLK_SEL_CLOCK_SWITCHED If Khz clock mux select is modified,please poll this bit and wait till it becomes one. [3:3] read-only RES reser [15:4] read-write MCU_FIRST_POWERUP_POR Program this bit to '1' upon power_up.It will be clear when Vbatt power is removed [16:16] read-write MCU_FIRST_POWERUP_RESET_N Program this bit to '1' upon power_up,It will be clear when reset pin is pulled low. [17:17] read-write RESERVED1 reserved1 [31:18] read-write ULPCLK 1.0 This block provides programming support for miscellaneous blocks in the chip. Various features in the chip are enabled using this. ULPSSCLOCKS 0x24041400 32 read-write 0x00 0xA8 registers ULP_MISC_SOFT_SET_REG ULP MISC soft register set. 0x00 32 read-write 0x00000000 PCM_ENABLE_b Used in pcm [0:0] read-write PCM_FSYNC_START_b Used in pcm [1:1] read-write BIT_RES Used in pcm [3:2] read-write IR_PCLK_EN_b Static clock enable for IR APB Interface [4:4] read-write PCLK_ENABLE_I2C_b This bit is used as Static enable for APB clock to I2C module,if bit is zero then clock is disabled else bit is one then clock is enabled. [5:5] read-write CLK_ENABLE_I2S_b This bit is used to enable clock to I2S module if bit is set(1)then clock is enabled is bit is zero then clock disabled. [6:6] read-write PCLK_ENABLE_SSI_MASTER_b This bit is used to enable APB bus clock to SSI master,if bit is zero clock will be available only when the request from the module is present.else bit is one then clock is enabled. [7:7] read-write SCLK_ENABLE_SSI_MASTER_b This bit is used to enable clock serial clock to SSI master,if bit is zero clock will be available only when the request from the module is present.else bit is one then clock is enabled. [8:8] read-write PCLK_ENABLE_UART_b This bit is used to enable peripheral bus clock to UART4,if bit zero then clock will be available only when the request from the module is present or a transaction is pending on the APB bus,else bit is one then clock is enabled. [9:9] read-write SCLK_ENABLE_UART_b This bit is used to enable asynchronous serial clock to UART4,if bit is zero clock will be available only when the request from the module is present.else bit is one then clock is enabled. [10:10] read-write FIM_PCLK_ENABLE_b This bit is used to enable clock to FIM reg file,if this bit is zero then clock will be available only when the request from the module is present else bit is set(1)then clock is enabled. [11:11] read-write VAD_PCLK_ENABLE_b This bit is used to enable clock to FIM reg file,if this bit is zero then clock will be available only when the request from the module is present else bit is set(1)then clock is enabled. [12:12] read-write CLK_ENABLE_TIMER_b This bit is used to enable clock to Timer,if this bit is zero then clock will be available only when the request from the module is present else bit is set(1)then clock is enabled. [13:13] read-write EGPIO_CLK_EN_b This bit is used to enable clock to gpio,if this bit is zero then clock will be available only when the request from the module is present else bit is set(1)then clock is enabled. [14:14] read-write REG_ACCESS_SPI_CLK_EN_b This bit is used to enable clock to register access spi,if this bit is zero then clock will be available only when the request from the module is present else bit is set(1)then clock is enabled. [15:15] read-write FIM_CLK_EN_b This bit is used to enable clock to FIM module,if this bit is zero then clock will be gated,else bit is one then clock is enabled. [16:16] read-write VAD_CLK_EN_b This bit is used to enable clock to vad module,if this bit is zero then clock will be gated,else bit is one then clock is enabled. [17:17] read-write CLK_ENABLE_ULP_MEMORIES_b This bit is used to enable clock to memories,if this bit is zero then clock will be available only when the request from the module is present else bit is set(1)then clock is enabled. [18:18] read-write EGPIO_PCLK_DYN_CTRL_DISABLE_b This bit is used to disable dynamic clock gating on APB clock to egpio [19:19] read-write EGPIO_PCLK_ENABLE_b This bit is used to enable static clock to egpio APB interface [20:20] read-write TIMER_PCLK_EN_b This bit is used to enable static clock to Timer APB Interface [21:21] read-write AUX_ULP_EXT_TRIG_1_SEL_b aux adc dac controller external trigger2 mux select, to choose between ulp gpio aux ext trigger2 and timer interrupt. [22:22] read-write AUX_ULP_EXT_TRIG_2_SEL_b aux adc dac controller external trigger2 mux select, to choose between ulp gpio aux ext trigger2 and timer interrupt. [23:23] read-write AUX_SOC_EXT_TRIG_1_SEL_b aux adc dac controller external trigger3 mux select, to choose between soc aux ext trigger1and soc aux ext trigger3. [24:24] read-write AUX_SOC_EXT_TRIG_2_SEL_b aux adc dac controller external trigger4 mux select, to choose between soc aux ext trigger2and soc aux ext trigger4. [25:25] read-write ULPSS_M4SS_SLV_SEL_b select slave [26:26] read-write ULPSS_TASS_QUASI_SYNC_b TASS quasi sync [27:27] read-write RESERVED1 reserved1 [29:28] read-write FIM_AHB_CLK_ENABLE_b static clock enable for FIM AHB interface [30:30] read-write TOUCH_SENSOR_PCLK_ENABLE_b Static clock enable for touch APB interface [31:31] read-write ULP_TA_PERI_ISO_REG ULP TA isolation register. 0x04 32 read-write 0x00000000 UDMA_ISO_CNTRL_b UDMA module isolation enable,if bit is set(1) then enable else bit is zero then disable. [0:0] read-write IR_ISO_CNTRL_b IR module isolation enable,if bit is set(1) then enable else bit is zero then disable. [1:1] read-write I2C_ISO_CNTRL_b I2C module isolation enable,if bit is set(1) then enable else bit is zero then disable. [2:2] read-write I2S_ISO_CNTRL_b I2S module isolation enable,if bit is set(1) then enable else bit is zero then disable. [3:3] read-write SSI_ISO_CNTRL_b SSI module isolation enable ,if bit is set(1) then enable else bit is zero then disable. [4:4] read-write UART_ISO_CNTRL_b UART module isolation enable,if bit is set(1) then enable else bit is zero then disable. [5:5] read-write AUX_A2D_ISO_CNTRL_b AUX a2d module isolation enable,if bit is set(1) then enable else bit is zero then disable. [6:6] read-write VAD_ISO_CNTRL_b VAD module isolation enable,if bit is set(1) then enable else bit is zero then disable. [7:7] read-write TOUCH_ISO_CNTRL_b CAP sensor module isolation enable,if bit is set(1) then enable else bit is zero then disable. [8:8] read-write PROC_MISC_ISO_CNTRL_b mis top(TOT, semaphore, interrupt cntrl, Timer) module isolation enable ,if bit is set(1) then enable else bit is zero then disable. [9:9] read-write RESERVED0 reserved0 [10:10] read-write RESERVED1 reserved1 [11:11] read-write RESERVED2 reserved2 [12:12] read-write RESERVED3 reserved3 [13:13] read-write FIM_ISO_CNTRL_b FIM module isolation enable ,if bit is set(1) then enable else bit is zero then disable. [14:14] read-write MEM_2K_1_ISO_CNTRL_b 2k SRAM memory isolation enable ,if bit is set(1) then enable else bit is zero then disable. [15:15] read-write MEM_2K_2_ISO_CNTRL_b 2k SRAM memory isolation enable ,if bit is set(1) then enable else bit is zero then disable. [16:16] read-write MEM_2K_3_ISO_CNTRL_b 2k SRAM memory isolation enable ,if bit is set(1) then enable else bit is zero then disable. [17:17] read-write MEM_2K_4_ISO_CNTRL_b 2k SRAM memory isolation enable ,if bit is set(1) then enable else bit is zero then disable. [18:18] read-write RESERVED4 reserved4 [31:19] read-write ULP_TA_PERI_RESET_REG ULP TA peri reset register. 0x08 32 read-write 0x00000000 UDMA_SOFT_RESET_CNTRL_b UDMA module soft reset enable,if bit is set(1) then out of soft reset else bit is zero then in reset. [0:0] read-write IR_SOFT_RESET_CNTRL_b IR module soft reset enable,if bit is set(1) then out of soft reset else bit is zero then in reset. [1:1] read-write I2C_SOFT_RESET_CNTRL_b I2C module soft reset enable ,if bit is set(1) then out of soft reset else bit is zero then in reset. [2:2] read-write I2S_SOFT_RESET_CNTRL_b I2S module soft reset enable ,if bit is set(1) then out of soft reset else bit is zero then in reset. [3:3] read-write SSI_SOFT_RESET_CNTRL_b SSI module soft reset enable ,if bit is set(1) then out of soft reset else bit is zero then in reset. [4:4] read-write UART_SOFT_RESET_CNTRL_b UART module soft reset enable ,if bit is set(1) then out of soft reset else bit is zero then in reset. [5:5] read-write AUX_A2D_SOFT_RESET_CNTRL_b AUX a2d module soft reset enable,if bit is set(1) then out of soft reset else bit is zero then in reset. [6:6] read-write VAD_SOFT_RESET_CNTRL_b VAD module soft reset enable,if bit is set(1) then out of soft reset else bit is zero then in reset. [7:7] read-write TOUCH_SOFT_RESET_CNTRL_b CAP Sensor module soft reset enable,if bit is set(1) then out of soft reset else bit is zero then in reset. [8:8] read-write PROC_MISC_SOFT_RESET_CNTRL_b mis top(TOT, semaphore, interrupt control, Timer) module soft reset enable,if bit is set(1) then out of soft reset else bit is zero then in reset [9:9] read-write COMP1_OUTPUT_CNTRL_b This is ULP comparator1 interrupt unmasking signal. 0 means comparator1 interrupt is masked and 1 means unmasking. It is masked at power-on time. [10:10] read-write COMP2_OUTPUT_CNTRL_b This is ULP comparator2 interrupt unmasking signal. 0 means comparator2 interrupt is masked and 1 means unmasking. It is masked at power-on time. [11:11] read-write RESERVED1 reserved1 [13:12] read-write FIM_SOFT_RESET_CNTRL_b FIM module soft reset enable,if bit is set(1) then out of soft reset else bit is zero then in reset [14:14] read-write RESERVED2 reserved2 [31:15] read-write ULP_TA_CLK_GEN_REG ULP TA clock generation register. 0x14 32 read-write 0x00000001 ULP2M4_A2A_BRDG_CLK_EN_b Clock enable for ULP-M4SS AHB-AHB bridge,if bit is set(1) then enable else bit is zero then in disable [0:0] read-write ULP_PROC_CLK_SEL ulp bus clock select. [4:1] read-write ULP_PROC_CLK_DIV_FACTOR ulp bus clock division factor [12:5] read-write RES reserved1 [31:13] read-write ULP_I2C_SSI_CLK_GEN_REG ULP I2C SSI clock generation register. 0x18 32 read-write 0xF0000000 ULP_I2C_CLK_EN_b ulp i2c clock enable,if bit is set(1) then enable else bit is zero then in disable [0:0] read-write RESERVED1 reserved1 [4:1] read-write RESERVED2 reserved2 [12:5] read-write RESERVED3 reserved3 [15:13] read-write ULP_SSI_CLK_EN_b ssi clk enable if set(1) then enable else bit is zero then disable [16:16] read-write ULP_SSI_CLK_DIV_FACTOR ssi clk enable if set(1) then enable else bit is zero then disable [23:17] read-write RESERVED4 reserved4 [27:24] read-write ULP_SSI_CLK_SEL Ulp ssi clock select. [31:28] read-write ULP_I2S_CLK_GEN_REG ULP I2S clock generation register. 0x1C 32 read-write 0x000000F0 ULP_I2S_CLK_EN_b ulp i2s clk enable,if bit is set(1) then enable else bit is zero then in disable [0:0] read-write ULP_I2S_CLK_SEL_b ulp i2s clock select. [4:1] read-write ULP_I2S_CLKDIV_FACTOR ulp i2s clock division factor. [12:5] read-write ULP_I2S_MASTER_SLAVE_MODE_b i2s master slave mode decide field. [13:13] read-write ULP_I2S_SCLK_DYN_CTRL_DISABLE_b Disable dynamic clock gating of System clock in I2S [14:14] read-write RESERVED1 reserved1 [15:15] read-write ULP_I2S_LOOP_BACK_MODE_b Enables loop back mode in I2S. [16:16] read-write ULP_I2S_PCLK_DYN_CTRL_DISABLE_b Disable dynamic clock gating of APB clock in I2S [17:17] read-write ULP_I2S_PCLK_EN_b Static clock enable for APB clock in I2S [18:18] read-write RESERVED2 reserved2 [31:19] read-write ULP_UART_CLK_GEN_REG ulp uart clock generation register. 0x20 32 read-write 0x000000F0 ULP_UART_FRAC_CLK_SEL_b ulp uart clk selection,if bit is set(1) then fractional divider output is selected else swallow divider output is selected [0:0] read-write ULP_UART_CLK_SEL ulp uart clock select. [4:1] read-write ULP_UART_CLKDIV_FACTOR ulp uart clock division factor [7:5] read-write RESERVED1 reserved1 [31:8] read-write M4LP_CTRL_REG m4 ulp control register 0x24 32 read-write 0x00000040 RESERVED0 reserved0 [1:0] read-write ULP_M4_CORE_CLK_ENABLE_b Static clock enable m4 core in ULP mode,if bit is set(1) then clock enable else clock is disable [2:2] read-write ULP_MEM_CLK_ULP_ENABLE_b Static clock enable for M4 memories in ULP mode,if bit is set(1) then clock enable else dynamic control [3:3] read-write ULP_MEM_CLK_ULP_DYN_CTRL_DISABLE_b Disable the dynamic clock gating for M4 memories in ULP mode,if bit is set(1) then dynamic control disabled else dynamic control enabled. [4:4] read-write RESERVED1 reserved1 [31:5] read-write CLOCK_STAUS_REG read clock status register 0x28 32 read-write 0x00000000 CLOCK_SWITCHED_UART_CLK_b status of clock mux for uart,if bit is set(1) then clock is switched,else bit is zero then clock not switched. [0:0] read-only CLOCK_SWITCHED_I2S_CLK_b Status of clock mux for i2s,if bit is set(1) then clock is switched,else bit is zero then clock not switched. [1:1] read-only CLOCK_SWITCHED_CORTEX_SLEEP_CLK_b Status of clock mux for m4 sleep clk,if bit is set(1) then clock is switched,else bit is zero then clock not switched. [2:2] read-only CLOCK_SWITCHED_PROC_CLK_b Status of clock mux for pclk,if bit is set(1) then clock is switched,else bit is zero then clock not switched. [3:3] read-only CLOCK_SWITCHED_I2C_b Status of clock mux for i2c,if bit is set(1) then clock is switched,else bit is zero then clock not switched. [4:4] read-only CLOCK_SWITCHED_SSI_b Status of clock mux for ssi,if bit is set(1) then clock is switched,else bit is zero then clock not switched. [5:5] read-only CLOCK_SWITCHED_VAD_b Status of clock mux for vad,if bit is set(1) then clock is switched,else bit is zero then clock not switched. [6:6] read-only CLOCK_SWITCHED_AUXADC_b Status of clock mux for aux adc dac clock,if bit is set(1) then clock is switched,else bit is zero then clock not switched. [7:7] read-only CLOCK_SWITCHED_TIMER_b Status of clock mux for async timers,if bit is set(1) then clock is switched,else bit is zero then clock not switched. [8:8] read-only CLOCK_SWITCHED_TOUCH_SENSOR_b Status of clock mux for touch sensor,if bit is set(1) then clock is switched,else bit is zero then clock not switched. [9:9] read-only CLOCK_SWITCHED_FCLK_VAD_b Status of clock mux for vad fast clock,if bit is set(1) then clock is switched,else bit is zero then clock not switched. [10:10] read-only CLOCK_SWITCHED_SCLK_VAD_b Status of clock mux for vad slow clock,if bit is set(1) then clock is switched,else bit is zero then clock not switched. [11:11] read-only CLOCK_SWITCHED_SYSTICK_b Status of clock mux for systick clock,if bit is set(1) then clock is switched,else bit is zero then clock not switched. [12:12] read-only RESERVED1 reserved1 [31:13] read-write ULP_TOUCH_CLK_GEN_REG ULP touch clock generation register 0x2C 32 read-write 0x000000F0 ULP_TOUCH_CLK_EN_b ulp touch clk enable,if bit is set(1) then enable,else bit is zero then disable. [0:0] read-write ULP_TOUCH_CLK_SEL ulp touch clock select. [4:1] read-write ULP_TOUCH_CLKDIV_FACTOR ulp touch clock division factor. [12:5] read-write RESERVED1 reserved1 [31:13] read-write ULP_TIMER_CLK_GEN_REG ULP clock generation for timer 0x30 32 read-write 0x000000F0 RESERVED1 reserved1 [0:0] read-write ULP_TIMER_CLK_SEL ulp timer clock select. [4:1] read-write RESERVED2 reserved2 [12:5] read-write ULP_TIMER_IN_SYNC_b Ulp timer in synchronous mode to ULPSS pclk [13:13] read-write RESERVED3 reserved3 [31:14] read-write ULP_AUXADC_CLK_GEN_REG ULP AUX clock generation register 0x34 32 read-write 0x000000F0 ULP_AUX_CLK_EN_b ulp aux clk enable,if bit is one then clock enable else bit is zero then clock disable. [0:0] read-write ULP_AUX_CLK_SEL ulp aux clock select. [4:1] read-write RESERVED1 reserved1 [31:5] read-write ULP_VAD_CLK_GEN_REG ULP vad clock generation register 0x38 32 read-write 0x000001EE ULP_VAD_CLK_EN_b ulp vad clk enable ,if bit is one then clock enable else bit is zero then clock disable. [0:0] read-write ULP_VAD_CLK_SEL ulp vad clock select. [3:1] read-write ULP_VAD_FCLK_EN Enables Fast clock to VAD. [4:4] read-write ULP_VAD_FCLK_SEL ulp vad Fast clock select. [8:5] read-write ULP_VAD_CLKDIV_FACTOR ulp vad clock division factor [16:9] read-write RESERVED1 reserved1 [31:17] read-write BYPASS_I2S_CLK_REG bypass i2s clock register 0x3C 32 read-write 0x00000004 BYPASS_I2S_PLL_SEL Bypass_I2S PLL clock,if bit is one bypass clock is used else bit is zero then I2S Clock is used. [0:0] read-write BYPASS_I2S_PLL_CLK_CLN_ON I2S PLL Bypass clock cleaner ON [1:1] read-write BYPASS_I2S_PLL_CLK_CLN_OFF I2S PLL Bypass clock cleaner OFF [2:2] read-write RESERVED3 reserved3 [31:3] read-write ULP_RM_RME_REG ulp rm rem register 0x44 32 read-write 0x00000022 ULP_MEM_RME_b RM enable signal for memories internal tp peripherals. This needs to be programmed when the peripheral memories are not active. [0:0] read-write ULP_MEM_RM RM ports for memories internal to peripheral. This needs to be programmed when the peripheral memories are not active. [2:1] read-write RESERVED1 reserved1 [3:3] read-only ULP_MEM_RME_SRAM_b RM enable signal for sram memories. This needs to be programmed when the SRAM is not active. [4:4] read-write ULP_MEM_RM_SRAM RM ports for sram memories. This needs to be programmed when the SRAM is not active [6:5] read-write RESERVED2 reserved2 [31:7] read-write ULP_CLK_ENABLE_REG ulp clock enable register. 0x48 32 read-write 0x00000000 ULP_32KHZ_RO_CLK_EN_PROG_b Static Clock enable to iPMU for 32KHz RO Clock,if bit is one(set) then clock enable else not enable. [0:0] read-write ULP_32KHZ_RC_CLK_EN_PROG_b Static Clock enable to iPMU for 32KHz RC Clock,if bit is one(set) then clock enable else not enable. [1:1] read-write ULP_32KHZ_XTAL_CLK_EN_PROG_b Static Clock enable to iPMU for 32KHz XTAL Clock,if bit is one(set) then clock enable else not enable. [2:2] read-write ULP_DOUBLER_CLK_EN_PROG_b Static Clock enable to iPMU for Doubler Clock,if bit is one(set) then clock enable else not enable. [3:3] read-write ULP_20MHZ_RO_CLK_EN_PROG_b Static Clock enable to iPMU for 20MHz RO clock,if bit is one(set) then clock enable else not enable. [4:4] read-write ULP_MHZ_RC_CLK_EN_PROG_b Static Clock enable to iPMU for 32MHz RC Clock,if bit is one(set) then clock enable else not enable. [5:5] read-write SOC_CLK_EN_PROG_b Static Clock enable to iPMU for PLL-500 Clock,if bit is one(set) then clock enable else not enable. [6:6] read-write I2S_PLLCLK_EN_PROG_b Static clock enable to iPMU for I2S-PLL Clock,if bit is one(set) then clock enable else not enable. [7:7] read-write REF_CLK_EN_IPS_PROG_b Static Clock enable to iPMU for REF Clock,if bit is one(set) then clock enable else not enable. [8:8] read-write RESERVED1 reserved1 [31:9] read-write SYSTICK_CLK_GEN_REG sys tick clock generation register. 0x50 32 read-write 0x0000000E SYSTICK_CLK_EN_b sys tick clock enable ,if bit is one(set) then clock enable else not enable. [0:0] read-write SYSTICK_CLK_SEL sys tick clock select [4:1] read-write SYSTICK_CLKDIV_FACTOR sys tick clock division factor [12:5] read-write RESERVED1 reserved1 [31:13] read-write 16 0x04 0-15 ULP_SOC_GPIO_MODE_REG[%s] ULP SOC gpio related registers(0-15) 0x0060 ULP_SOC_GPIO_MODE_REG ulp soc gpio mode register 0x00 32 read-write 0x00000000 ULP_SOC_GPIO_MODE_REG mode bits for soc gpio. [2:0] read-write RESERVED1 reserved1 [31:3] read-write ULP_DYN_CLK_CTRL_DISABLE this register used for ULP dynamic clock control disable. 0xA0 32 read-write 0x00000000 I2C_PCLK_DYN_CTRL_DISABLE_b Dynamic clock control disable for APB interface in i2c module,if bit is one(set) then dynamic control disabled else bit is zero then Dynamic control enabled. [0:0] read-write I2S_CLK_DYN_CTRL_DISABLE_b Dynamic clock control disable for i2s module,if bit is one(set) then dynamic control disabled else bit is zero then Dynamic control enabled. [1:1] read-write SSI_MST_PCLK_DYN_CTRL_DISABLE_b Dynamic clock control disable for pclk ssi module,if bit is one(set) then dynamic control disabled else bit is zero then Dynamic control enabled. [2:2] read-write SSI_MST_SCLK_DYN_CTRL_DISABLE_b Dynamic clock control disable for ssi module,if bit is one(set) then dynamic control disabled else bit is zero then Dynamic control enabled. [3:3] read-write UART_CLK_DYN_CTRL_DISABLE_b Dynamic clock control disable for pclk uart module ,if bit is one(set) then dynamic control disabled else bit is zero then Dynamic control enabled. [4:4] read-write UART_SCLK_DYN_CTRL_DISABLE_b Dynamic clock control disable for uart module,if bit is one(set) then dynamic control disabled else bit is zero then Dynamic control enabled. [5:5] read-write TIMER_PCLK_DYN_CTRL_DISABLE_b Dynamic clock control disable for timer pclk module,if bit is one(set) then dynamic control disabled else bit is zero then Dynamic control enabled. [6:6] read-write TIMER_SCLK_DYN_CTRL_DISABLE_b Dynamic clock control disable for timer sclk module,if bit is one(set) then dynamic control disabled else bit is zero then Dynamic control enabled. [7:7] read-write REG_ACCESS_SPI_CLK_DYN_CTRL_DISABLE_b Dynamic clock control disable for reg access spi module,if bit is one(set) then dynamic control disabled else bit is zero then Dynamic control enabled. [8:8] read-write FIM_CLK_DYN_CTRL_DISABLE_b Dynamic clock control disable for fim module,if bit is one(set) then dynamic control disabled else bit is zero then Dynamic control enabled. [9:9] read-write VAD_CLK_DYN_CTRL_DISABLE_b Dynamic clock control disable for vad module,if bit is one(set) then dynamic control disabled else bit is zero then Dynamic control enabled. [10:10] read-write AUX_PCLK_EN_b Static Enable for Aux adc pclk. [11:11] read-write AUX_CLK_EN_b Static Enable for Aux adc clk. [12:12] read-write AUX_MEM_EN_b Static Enable for Aux adc mem. [13:13] read-write AUX_PCLK_DYN_CTRL_DISABLE_b Dynamic clock control disable for aux adc module,if bit is one(set) then dynamic control disabled else bit is zero then Dynamic control enabled. [14:14] read-write AUX_CLK_DYN_CTRL_DISABLE_b Dynamic clock control disable for aux adc module,if bit is one(set) then dynamic control disabled else bit is zero then Dynamic control enabled. [15:15] read-write AUX_CLK_MEM_DYN_CTRL_DISABLE_b Dynamic clock control disable for aux adc mem,if bit is one(set) then dynamic control disabled else bit is zero then Dynamic control enabled. [16:16] read-write UDMA_CLK_ENABLE_b Static Enable for UDMA. [17:17] read-write IR_CLK_ENABLE_b Static Enable for IR. [18:18] read-write IR_CLK_DYN_CTRL_DISABLE_b Dynamic clock control disable for ir module ,if bit is one(set) then dynamic control disabled else bit is zero then Dynamic control enabled. [19:19] read-write RESERVED1 reserved1 [31:20] read-write SLP_SENSOR_CLK_REG this register used for SLP sensor clock register. 0xA4 32 read-write 0x00000102 DIVISON_FACTOR Division factor for apb interface clock to sleep sensor subsystem. [7:0] read-write ENABLE_b Enable for APB clock to SLPSS [8:8] read-write RESERVED1 reserved1 [31:9] read-write FIM 1.0 FIM support fixed point Multiplications implemented through programmable shifting. 0x24070000 32 read-write 0 0x24 registers FIM 17 FIM_MODE_INTERRUPT Configuration for FIM Operation Mode and Interrupt Control 0x00 32 read-write LATCH_MODE Enable latch mode [0:0] read-write Enable Enable latch mode enable of FIM 1 Disable Disable latch mode enable of FIM 0 OPER_MODE Indicates the Mode of Operation to be performed. [8:1] read-write RESERVED1 reserved1 [9:9] read-only INTR_CLEAR Writing 1 to this bit clears the interrupt [10:10] write-only Enable Enable to clear interrupt 1 Disable Disable to clear interrupt 0 RESERVED2 reserved2 [31:11] read-only FIM_INP1_ADDR This register used for COP input address for 0 register. 0x04 32 read-write INP1_ADDR Indicates the Start Address of 1st Input Data for FIM Operations [31:0] read-write FIM_INP2_ADDR This register used for COP input address for 1 register 0x08 32 read-write INP2_ADDR Indicates the Start Address of 2nd Input Data for FIM Operations [31:0] read-write FIM_OUT_ADDR Memory Offset Address for Output from FIM Operations 0x0C 32 read-write OUT_ADDR Indicates the Start Address of Output Data for FIM Operations [31:0] read-write FIM_SCALAR_POLE_DATA1 Indicates the Input Scalar Data for Scalar Operations indicates the feedback coefficient for IIR Operations 0x10 32 read-write SCALAR_POLE_DATA1 Pole 0/Scalar Value [31:0] read-write FIM_POLE_DATA2 Feedback coefficient for IIR filter operation 0x14 32 read-write POLE_DATA2 Indicates the feedback coefficient for IIR Operations [31:0] read-write FIM_SAT_SHIFT Configuration for precision of Output Data for FIM Operations 0x18 32 read-write SAT_VAL Indicates the number of MSB's to be saturated for Output Data [4:0] read-write TRUNCATE Truncate [9:5] read-write SHIFT_VAL Indicates the number of bits to be right-shifted for Output Data [15:10] read-write ROUND Round [17:16] read-write SAT_EN Saturation enable bit [18:18] read-write RESERVED2 reserved2 [31:19] read-only FIM_CONFIG_REG1 Configuration Register for FIM Operations. 0x1C 32 read-write MAT_LEN Indicates the number of columns in 1st input for Matrix Multiplication. This is same as number of rows in 2nd input for Matrix Multiplication. [5:0] read-write INP1_LEN Indicates the length of 1st input for FIM Operations other than filtering (FIR, IIR) and Interpolation [15:6] read-write INP2_LEN Indicates the length of 2nd input for FIM Operations other than filtering (FIR, IIR) and Interpolation. [25:16] read-write DECIM_FAC Decimation Factor [31:26] read-write FIM_CONFIG_REG2 Configuration Register for FIM Operations 0x20 32 read-write START_OPER Start trigger for the FIM operations,this is reset upon write register [0:0] write-only Enable Enable start operation 1 Disable Disable start operation 0 INSTR_BUFF_ENABLE Instruction buffer enable [1:1] read-write RES reserved5 [7:2] read-only CPLX_FLAG Complex Flag,not valid in matrix mode [9:8] read-write Real_Real input1 and input2 both are real 0x0 Real_Complex input1 is real and input2 is complex 0x1 Complex_Real input1 is complex and input2 is real 0x2 Complex_Complex input1 and input2 both are complex 0x3 COL_M2 Indicates the number of columns in 2nd input for Matrix Multiplication [15:10] read-write ROW_M1 Indicates the number of rows in 1st input for Matrix Multiplication [21:16] read-write INTRP_FAC Indicates the Interpolation Factor [27:22] read-write RESERVED1 reserved1 [31:28] read-only NWP_FSM 1.0 NWP FSM one register Structure NWP_FSM 0x41300110 32 read-write 0x00 0x4 registers TASS_REF_CLOCK_SELECT TASS REF CLOCK SELECT 0x00 32 read-write 0x00000000 M4SS_REF_CLK_SEL_NWP M4SS REF CLK SEL NWP [2:0] read-write RESERVED1 reserved1 [3:3] read-write ULPSS_REF_CLK_SEL_NWP ULPSS REF CLK SEL NWP [6:4] read-write RESERVED2 reserved2 [15:7] read-write TASS_REF_CLK_SEL_NWP TASS REF CLK SEL NWP [18:16] read-write RESERVED3 reserved3 [21:19] read-write TASS_REF_CLK_CLEANER_OFF_NWP TASS REF CLK CLEANER OFF NWP [22:22] read-write TASS_REF_CLK_CLEANER_ON_NWP TASS REF CLK CLEANER ON NWP [23:23] read-write RESERVED4 reserved4 [31:24] read-write OPAMP 1.0 The opamps top consists of 3 general purpose Operational Amplifiers (OPAMP) offering rail-to-rail inputs and outputs OPAMP 0x24043A14 32 read-write 0x00 0x0C registers OPAMP_1 Programs opamp1 0x00 32 read-write 0x00000004 OPAMP1_ENABLE To enable opamp 1 [0:0] read-write Disable Disable opamp1 0 Enable Enable opamp1 1 OPAMP1_LP_MODE Enable or disable low power mode [1:1] read-write Disable Disable opamp1 low power mode 0 Enable Enable opamp1 low power mode 1 OPAMP1_R1_SEL Programmability to select resister bank R1 [3:2] read-write Zero_ohm R1 as short 0 Twenty_ohm R1 as Twenty_ohm 1 Sixty_ohm R1 as Sixty_ohm 2 Oneforty_ohm R1 as Oneforty_ohm 3 OPAMP1_R2_SEL Programmability to select resister bank R2 [6:4] read-write Twenty_ohm R2 as Twenty_ohm 0 Thirty_ohm R1 as Thirty_ohm 1 forty_ohm R1 as forty_ohm 2 Sixty_ohm R1 as Sixty_ohm 3 Onetwenty_ohm R1 as Onetwenty_ohm 4 twofifty_ohm R1 as twofifty_ohm 5 fivehundred_ohm R1 as fivehundred_ohm 6 Onethousand_ohm R1 as Onethousand_ohm 7 OPAMP1_EN_RES_BANK enables the resistor bank 1 for enable 0 for disable [7:7] read-write Disable Disable opamp1 resister bank 0 Enable Enable opamp1 resister bank 1 OPAMP1_RES_MUX_SEL selecting input for registor bank [10:8] read-write OPAMP1_RES_TO_OUT_VDD connect resistor bank to out or vdd i.e 0-out and 1-vdd [11:11] read-write res_out connect resister bank to out 0 res_vdd connect resbank to vdd 1 OPAMP1_OUT_MUX_EN out mux enable [12:12] read-write Disable Disable opamp1 out mux 0 Enable Enable opamp1 out mux 1 OPAMP1_INN_SEL selecting -ve input of opamp [15:13] read-write Input0_Negative External pin0 as negative input for OPAMP1 0 Input1_Negative External pin1 as negative input for OPAMP1 1 DAC DAC as negative input for OPAMP1 2 res_tap register tap as negative input for OPAMP1 3 opamp1_out opamp1_out as negative input for OPAMP1 4 OPAMP1_INP_SEL selecting +ve input of opamp [19:16] read-write Input0_positive External pin0 as positive input for OPAMP1 0 Input1_positive External pin1 as positive input for OPAMP1 1 Input2_positive External pin2 as positive input for OPAMP1 2 Input3_positive External pin3 as positive input for OPAMP1 3 Input4_positive External pin4 as positive input for OPAMP1 4 Input5_positive External pin5 as positive input for OPAMP1 5 DAC DAC as positive input for OPAMP1 6 res_tap register tap as positive input for OPAMP1 7 opamp1_out opamp1_out as positive input for OPAMP1 8 OPAMP1_OUT_MUX_SEL to connect opamp1 output to pad [20:20] read-write Dis_select Dis select opamp1 out mux 0 Select Select opamp1 out mux 1 MEMS_RES_BANK_EN enables mems res bank [21:21] read-write Disable Disable the memory register bank 0 Enable Enable the memory register bank 1 VREF_MUX_EN vref mux enable [25:22] read-write MUX_EN Mux Enable [26:26] read-write VREF_MUX_SEL vref mux enable [30:27] read-write OPAMP1_DYN_EN dynamic enable for opamp1 [31:31] read-write Disable Disable the opamp1 dynamic mode 0 Enable Enable the opamp1 dynamic mode 1 OPAMP_2 Programs opamp2 0x04 32 read-write 0x00000004 OPAMP2_ENABLE enables the opamp2 [0:0] read-write Disable Disable opamp2 0 Enable Enable opamp2 1 OPAMP2_LP_MODE select the power mode 0-normal mode and 1-low power mode [1:1] read-write Disable Disable opamp2 low power mode 0 Enable Enable opamp2 low power mode 1 OPAMP2_R1_SEL Programmability to select resister bank R1 [3:2] read-write Zero_ohm R1 as short 0 Twenty_ohm R1 as Twenty_ohm 1 Sixty_ohm R1 as Sixty_ohm 2 Oneforty_ohm R1 as Oneforty_ohm 3 OPAMP2_R2_SEL Programmability to select resister bank R2 [6:4] read-write Twenty_ohm R2 as Twenty_ohm 0 Thirty_ohm R1 as Thirty_ohm 1 forty_ohm R1 as forty_ohm 2 Sixty_ohm R1 as Sixty_ohm 3 Onetwenty_ohm R1 as Onetwenty_ohm 4 twofifty_ohm R1 as twofifty_ohm 5 fivehundred_ohm R1 as fivehundred_ohm 6 Onethousand_ohm R1 as Onethousand_ohm 7 OPAMP2_EN_RES_BANK enables the resistor bank 1 for enable 0 for disable [7:7] read-write Disable Disable opamp2 resister bank 0 Enable Enable opamp2 resister bank 1 OPAMP2_RES_MUX_SEL selecting input for registor bank [10:8] read-write OPAMP2_RES_TO_OUT_VDD connect resistor bank to out or vdd or gnd or DAC i.e 0-out and 1-vdd 2-DAC 3-gnd [12:11] read-write resbank_out connect resbank to out 0 resbank_vdd connect resbank to vdd 1 resbank_DAC connect resbank to DAC 2 resbank_GND connect resbank to gnd 3 OPAMP2_OUT_MUX_EN out mux enable [13:13] read-write Disable Disable opamp2 out mux 0 Enable Enable opamp2 out mux 1 OPAMP2_INN_SEL selecting -ve input of opamp [15:14] read-write Input0_Negative External pin0 as negative input for OPAMP2 0 DAC DAC as negative input for OPAMP2 1 res_tap register tap as negative input for OPAMP2 2 opamp1_out opamp1_out as negative input for OPAMP2 3 OPAMP2_INP_SEL selecting +ve input of opamp2 [18:16] read-write Input0_Positive External pin0 as positive input for OPAMP2 0 Input1_Positive External pin1 as positive input for OPAMP2 1 Input2_Positive External pin2 as positive input for OPAMP2 2 DAC DAC as positive input for OPAMP2 3 res_tap register tap as positive input for OPAMP2 4 gnd ground as positive input for OPAMP2 5 OPAMP1_out OPAMP1_out as positive input for OPAMP2 6 OPAMP2_DYN_EN dynamic enable for opamp2 [19:19] read-write Disable Disable the opamp2 dynamic mode 0 Enable Enable the opamp2 dynamic mode 1 RESERVED1 res [31:20] read-write OPAMP_3 Programs opamp3 0x08 32 read-write 0x00000004 OPAMP3_ENABLE enables the opamp3 1 for enable 0 for disable [0:0] read-write Disable Disable opamp3 0 Enable Enable opamp3 1 OPAMP3_LP_MODE select the power mode 0-normal mode and 1-low power mode [1:1] read-write Disable Disable opamp3 low power mode 0 Enable Enable opamp3 low power mode 1 OPAMP3_R1_SEL Programmability to select resister bank R1 [3:2] read-write Zero_ohm R1 as short 0 Twenty_ohm R1 as Twenty_ohm 1 Sixty_ohm R1 as Sixty_ohm 2 Oneforty_ohm R1 as Oneforty_ohm 3 OPAMP3_R2_SEL Programmability to select resister bank R2 [6:4] read-write Twenty_ohm R2 as Twenty_ohm 0 Thirty_ohm R1 as Thirty_ohm 1 forty_ohm R1 as forty_ohm 2 Sixty_ohm R1 as Sixty_ohm 3 Onetwenty_ohm R1 as Onetwenty_ohm 4 twofifty_ohm R1 as twofifty_ohm 5 fivehundred_ohm R1 as fivehundred_ohm 6 Onethousand_ohm R1 as Onethousand_ohm 7 OPAMP3_EN_RES_BANK enables the resistor bank 1 for enable 0 for disable [7:7] read-write Disable Disable opamp3 resister bank 0 Enable Enable opamp3 resister bank 1 OPAMP3_RES_MUX_SEL selecting input for registor bank [10:8] read-write OPAMP3_RES_TO_OUT_VDD connect resistor bank to out or vdd i.e 0-out and 1-vdd [11:11] read-write res_out connect resister bank to out 0 res_vdd connect resbank to vdd 1 OPAMP3_OUT_MUX_EN out mux enable [12:12] read-write Disable Disable opamp3 out mux 0 Enable Enable opamp3 out mux 1 OPAMP3_INN_SEL selecting -ve input of opamp [14:13] read-write Input0_Negative External pin0 as negative input for OPAMP3 0 DAC DAC as negative input for OPAMP3 1 res_tap register tap as negative input for OPAMP3 2 opamp2_out opamp2_out as negative input for OPAMP3 3 OPAMP3_INP_SEL selecting +ve input of opamp [17:15] read-write Input0_Positive External pin0 as positive input for OPAMP3 0 Input1_Positive External pin1 as positive input for OPAMP3 1 DAC DAC as positive input for OPAMP3 2 res_tap register tap as positive input for OPAMP3 3 gnd ground as positive input for OPAMP3 4 OPAMP2_out OPAMP2_out as positive input for OPAMP3 5 OPAMP2_restap OPAMP2_restap as positive input for OPAMP3 6 OPAMP3_DYN_EN dynamic enable for opamp2 [18:18] read-write Disable Disable the opamp3 dynamic mode 0 Enable Enable the opamp3 dynamic mode 1 RESERVED1 res [31:19] read-write AUX_ADC_DAC_COMP 1.0 The ADC-DAC Controller works on a ADC with a resolution of 12bits at 5Mega sample per second when ADC reference Voltage is greater than 2.8v or 5Mega sample per second when ADC reference Voltage is less than 2.8v. ADC_DAC_COMP 0x24043800 32 read-write 0x00 0x214 registers ADC 11 COMP1 8 COMP2 7 AUXDAC_CTRL_1 Control register1 for DAC 0x00 32 read-write 0x0001E200 ENDAC_FIFO_CONFIG This bit activates the DAC path in Aux ADC-DAC controller. Data samples will be played on DAC only when this bit is set. [0:0] read-write Enable Enable fifo configuration of DAC 1 Disable Disable fifo configuration of DAC 0 DAC_STATIC_MODE This bit is used to select non-FIFO mode in DAC. [1:1] read-write Enable Static mode is enabled. Data written to the DAC_DATA_REG will not be written to the FIFO. It will be played on DAC directly. Only single sample can be held at a time 1 Disable FIFO mode enabled. Data written to the DAC_DATA_REG is written to the FIFO in this mode. In either of these modes, data will be driven to the DAC only when dac_enable is set. 0 DAC_FIFO_FLUSH This bit is used to flush the DAC FIFO. [2:2] read-write Enable Flush dac FIFO 1 Disable Do not flush 0 RESERVED1 Reserved [5:3] read-write DAC_ENABLE_F This bit is used to enable AUX DAC controller ,valid only when DAC enable is happpen [6:6] read-write Enable Enable DAC Controller 1 Disable Disable DAC Controller 0 RESERVED2 Reserved2 [8:7] read-write DAC_FIFO_AEMPTY_THRESHOLD It is recommended to write these bits to 0 [12:9] read-write DAC_FIFO_AFULL_THRESHOLD It is recommended to write these bits to 0 [16:13] read-write RESERVED3 Reserved3 [31:17] read-write AUXADC_CTRL_1 Control register1 for ADC 0x04 32 read-write 0x00000010 ADC_ENABLE This bits activates the ADC path in Aux ADC-DAC controller. [0:0] read-write Enable Enable ADC 1 Disable Disable ADC 0 ADC_STATIC_MODE This bit is used to select non-FIFO mode in ADC. [1:1] read-write Enable Static mode enable here data directly to register not in FIFO 1 Disable FIFO mode enabled here data directly to FIFO. 0 ADC_FIFO_FLUSH This bit is used to flush the ADC FIFO [2:2] read-write Enable Flush ADC FIFO 1 Disable Do not flush 0 RESERVED1 RESERVED1 [5:3] read-write ADC_MULTIPLE_CHAN_ACTIVE This bit is used to control the auxadc sel signal going to the Aux ADC. [6:6] read-write Enable Data will be sampled from four ADC channels in sequential order and written to the receive FIFO in the same order. 1 Disable Data will be sampled from the programmed ADC channel 0 ADC_CH_SEL_MSB Upper 2-bits of adc channel select.When the channel number is greater than 3, these have to be used.It is recommended to write these bits to 0 [8:7] read-write BYPASS_NOISE_AVG ADC in Bypass noise avg mode. [9:9] read-write EN_ADC_CLK Enable AUX ADC Divider output clock [10:10] read-write RESERVED2 Reserved2 [11:11] read-write ADC_CH_SEL_LS Aux ADC channel number from which the data has to be sampled This is valid only when adc multiple channel active is zero. When channel number is greater than three, upper bits should also be programmed ADC CHANNEL SELECT MS to bits in this register [13:12] read-write CHANNEL_0 channel 0 0 CHANNEL_1 channel 1 1 CHANNEL_2 channel 2 2 CHANNEL_3 channel 3 3 RESERVED3 Reserved3 [26:14] read-write ADC_NUM_PHASE ADC number of phase [27:27] read-write RESERVED3 Reserved3 [31:28] read-write AUXDAC_CLK_DIV_FAC DAC clock division register 0x08 32 read-write 0x00000000 DAC_CLK_DIV_FAC These bits control the DAC clock division factor [9:0] read-write RESERVED1 Reserved1 [31:10] read-write AUXADC_CLK_DIV_FAC ADC clock division register 0x0C 32 read-write 0x00000000 ADC_CLK_DIV_FAC These bits control the Total-Duration of the ADC clock [9:0] read-write RESERVED1 Reserved1 [15:10] read-write ADC_CLK_ON_DUR These bits control the On-Duration of the ADC clock [24:16] read-write RESERVED2 Reserved2 [31:25] read-write AUXDAC_DATA Writing to this register will fill DAC FIFO for streaming Data to DAC 0x10 32 read-write 0x00000000 AUXDAC_DATA Writing to this register will fill DAC FIFO for streaming Data to DAC [9:0] read-write RESERVED1 Reserved1 [31:10] read-write AUXADC_DATA AUXADC Data Read through Register. 0x14 32 read-write 0x00000000 AUXADC_DATA AUXADC Data Read through Register [11:0] read-only AUXADC_CH_ID AUXADC Channel ID [15:12] read-only RESERVED1 Reserved1 [31:16] read-write ADC_DET_THR_CTRL_0 ADC detection threshold control 0 0x18 32 read-write 0x00000000 ADC_INPUT_DETECTION_THRESHOLD_0 The value against which the ADC output has to be compared is to be programmed in this register [7:0] read-write COMP_LESS_THAN_EN When set, Aux ADC-DAC controller raises an interrupt to processor when the Aux ADC output falls below the programmed Aux ADC detection threshold. [8:8] read-write Enable Enable less than mode 1 Disable Disable less than mode 0 COMP_GRTR_THAN_EN When set, Aux ADC-DAC controller raises an interrupt to processor when the Aux ADC output is greater than the programmed Aux ADC detection threshold.. [9:9] read-write Enable Enable grater than mode 1 Disable Disable grater than mode 0 COMP_EQ_EN When set, Aux ADC-DAC controller raises an interrupt to processor when the Aux ADC output is equal to the programmed Aux ADC detection threshold [10:10] read-write Enable Enable compare equal bit 1 Disable Disable compare equal bit 0 RANGE_COMPARISON_ENABLE When set, Aux ADC-DAC controller raises an interrupt to processor when the Aux ADC output falls within the range specified in AUX ADC Detection threshold0 and AUX ADC Detection threshold1 [11:11] read-write Enable Enable range comparison 1 Disable Disable range comparison 0 ADC_INPUT_DETECTION_THRESHOLD_1 Carries upper four bits of ADC detection threshold [15:12] read-write RESERVED1 Reserved1 [31:16] read-write ADC_DET_THR_CTRL_1 ADC detection threshold control 1 0x1C 32 read-write 0x00000000 ADC_INPUT_DETECTION_THRESHOLD_2 The value against which the ADC output has to be compared is to be programmed in this register. [7:0] read-write COMP_LESS_THAN_EN When set, Aux ADC-DAC controller raises an interrupt to TA when the Aux ADC output falls below the programmed Aux ADC detection threshold. [8:8] read-write Enable Enable less than mode 1 Disable Disable less than mode 0 COMP_GRTR_THAN_EN When set, Aux ADC-DAC controller raises an interrupt to TA when the Aux ADC output is greater than the programmed Aux ADC detection threshold. [9:9] read-write Enable Enable grater than mode 1 Disable Disable grater than mode 0 COMP_EQ_EN When set, Aux ADC-DAC controller raises an interrupt to TA when the Aux ADC output is equal to the programmed Aux ADC detection threshold. [10:10] read-write Enable Enable compare equal bit 1 Disable Disable compare equal bit 0 ADC_DETECTION_THRESHOLD_4_UPPER_BITS Upper 4 bits of ADC detection threshold 2 for ADC [14:11] read-write RESERVED1 Reserved1 [31:15] read-write INTR_CLEAR_REG ADC detection threshold control 1 0x20 32 read-write 0x00000000 CLR_INTR This bit is used to clear threshold detection interrupt [0:0] read-write CLEAR_INTERRUPT Clear the interrupt 1 NO_EFFECT Disable compare equal bit 0 RESERVED1 Reserved1 [7:1] read-write INTR_CLEAR_REG If enabled, corresponding first_mem_switch_intr bits will be cleared. [23:8] read-write RESERVED2 Reserved2 [31:24] read-write INTR_MASK_REG Mask interrupt register 0x24 32 read-write 0x01FFFFFF THRESHOLD_DETECTION_INTR_EN When Cleared, threshold detection interrupt will be unmasked [0:0] read-write MASK_INTERRUPT When bit is set mask the interrupt 1 UNMASK_EFFECT When bit is clear unmask the interrupt 0 DAC_FIFO_EMPTY_INTR_MASK When Cleared, dac_FIFO_empty interrupt will be unmasked [1:1] read-write MASK_INTERRUPT When bit is set mask the interrupt 1 UNMASK_EFFECT When bit is clear unmask the interrupt 0 DAC_FIFO_AEMPTY_INTR_MASK When Cleared, adc FIFO full interrupt will be unmasked [2:2] read-write MASK_INTERRUPT When bit is set mask the interrupt 1 UNMASK_EFFECT When bit is clear unmask the interrupt 0 ADC_FIFO_FULL_INTR_MASK When Cleared, adc FIFO full interrupt will be unmasked [3:3] read-write MASK_INTERRUPT When bit is set mask the interrupt 1 UNMASK_EFFECT When bit is clear unmask the interrupt 0 ADC_FIFO_AFULL_INTR_MASK When Cleared, adc FIFO afull interrupt will be unmasked [4:4] read-write MASK_INTERRUPT When bit is set mask the interrupt 1 UNMASK_EFFECT When bit is clear unmask the interrupt 0 ADC_FIFO_OVERFLOW_INTR_MASK When Cleared, dac FIFO underrun interrupt will be unmasked [5:5] read-write MASK_INTERRUPT When bit is set mask the interrupt 1 UNMASK_EFFECT When bit is clear unmask the interrupt 0 DAC_FIFO_UNDERRUN_INTR_MASK When Cleared, dac FIFO underrun interrupt will be unmasked [6:6] read-write MASK_INTERRUPT When bit is set mask the interrupt 1 UNMASK_EFFECT When bit is clear unmask the interrupt 0 DMA_Channel_intr_mask_0_to_15_Bits When Cleared, first_mem_switch_intr will be unmasked [22:7] read-write ADC_STATIC_MODE_DATA_INTR_MASK When Cleared, adc static_mode_data_intr will be unmasked [23:23] read-write DAC_STATIC_MODE_DATA_INTR_MASK When Cleared, dac static_mode_data_intr will be unmasked [24:24] read-write RESERVED1 Reserved1 [31:25] read-write INTR_STATUS_REG Status interrupt register 0x28 32 read-only 0x00000006 ADC_THRESHOLD_DETECTION_INTR This bit is set when ADC threshold matches with the programmed conditions This will be be cleared as soon as this interrupt is acknowledged by processor [0:0] read-only DAC_FIFO_EMPTY Set when DAC FIFO is empty. This bit gets cleared when the DAC FIFO at least a single sample is available in DAC FIFO [1:1] read-only DAC_FIFO_AEMPTY Set when the FIFO occupancy grater than or equal to DAC FIFO threshold. [2:2] read-only ADC_FIFO_FULL Set when ADC FIFO is full,This bit gets cleared when data is read from the FIFO [3:3] read-only ADC_FIFO_AFULL Set when ADC FIFO occupancy less than or equal to ADC FIFO threshold [4:4] read-only ADC_FIFO_OVERFLOW Set when a write attempt is made to ADC FIFO when the FIFO is already full [5:5] read-only DAC_FIFO_UNDERRUN Set when a read is done on DAC FIFO when the FIFO is empty [6:6] read-only DMA_Channel_intr_0_to_15_Bits Interrupt indicating the first memory has been filled and the DMA write is being shifted to second memory chunk for ping-pong operation [22:7] read-only ADC_STATIC_MODE_DATA_INTR Set when a proper data packet is ready to read in static mode for ADC [23:23] read-only DAC_STATIC_MODE_DATA_INTR Set when a proper data packet is ready to read in static mode for DAC [24:24] read-only RESERVED1 Reserved1 [31:25] read-only INTR_MASKED_STATUS_REG Interrupt masked status register 0x2C 32 read-only 0x00000006 ADC_THRESHOLD_DETECTION_INTR_MASKED Masked Interrupt. This bit is set when ADC threshold matches with the programmed conditions [0:0] read-only DAC_FIFO_EMPTY_MASKED Masked Interrupt.Set when DAC FIFO is empty [1:1] read-only DAC_FIFO_AEMPTY_MASKED Masked Interrupt. Set when the FIFO occupancy less than equal to DAC FIFO threshold. [2:2] read-only ADC_FIFO_FULL_MASKED Masked Interrupt. Set when ADC FIFO is full. [3:3] read-only ADC_FIFO_AFULL_MASKED Masked Interrupt. Set when ADC FIFO occupancy greater than ADC FIFO threshold [4:4] read-only ADC_FIFO_OVERFLOW_MASKED Masked Interrupt. Set when a write attempt is made to ADC FIFO when the FIFO is already full. [5:5] read-only DAC_FIFO_UNDERRUN_MASKED Masked Interrupt. Set when a read is done on DAC FIFO when the FIFO is empty. [6:6] read-only DMA_Channel_intr_masked_0_to_15_Bits Masked Interrupt status indicating the first memory has been filled and the DMA write is being shifted to second memory chunk for ping-pong operation [22:7] read-only ADC_STATIC_MODE_DATA_INTR_MASKED Masked Interrupt. Set when a proper data packet is ready to read in static mode for ADC [23:23] read-only DAC_STATIC_MODE_DATA_INTR_MASKED Masked Interrupt. Set when a proper data packet is ready to read in static mode for DAC [24:24] read-only RESERVED1 Reserved1 [31:25] read-only FIFO_STATUS_REG Interrupt masked status register 0x30 32 read-only 0x0000003C DAC_FIFO_FULL Set when DAC FIFO is full. In word mode, FIFO will be shown as full unless there is space for 16-bits. [0:0] read-only DAC_FIFO_AFULL Set when DAC FIFO occupancy greater than FIFO threshold [1:1] read-only ADC_FIFO_EMPTY Set when FIFO is empty. This bit gets cleared when the ADC FIFO is not empty. [2:2] read-only ADC_FIFO_AEMPTY Set when the FIFO occupancy less than ADC FIFO threshold [3:3] read-only DAC_FIFO_EMPTY Set when FIFO is empty. This bit gets cleared when the DAC FIFO is not empty. [4:4] read-only DAC_FIFO_AEMPTY Set when the FIFO occupancy less than DAC FIFO threshold [5:5] read-only ADC_FIFO_FULL Set when ADC FIFO is full. This bit gets cleared when data is read from the FIFO. [6:6] read-only ADC_FIFO_AFULL Set when ADC FIFO occupancy greater than ADC FIFO threshold. [7:7] read-only RESERVED1 Reserved1 [31:8] read-only ADC_CTRL_REG_2 ADC Control register2 0x34 32 read-write 0x00000000 EXT_TRIG_DETECT_1 Condition to detect event on external trigger 1 00: None (trigger disabled) 01: Positive edge 10: Negative edge 11: Positive or negative edge. [1:0] read-write EXT_TRIG_DETECT_2 Condition to detect event on external trigger 2 00: None (trigger disabled) 01: Positive edge 10: Negative edge 11: Positive or negative edge. [3:2] read-write EXT_TRIG_DETECT_3 Condition to detect event on external trigger 3 00: None (trigger disabled) 01: Positive edge 10: Negative edge 11: Positive or negative edge. [5:4] read-write EXT_TRIG_DETECT_4 Condition to detect event on external trigger 4 00: None (trigger disabled) 01: Positive edge 10: Negative edge 11: Positive or negative edge. [7:6] read-write EXT_TRIGGER_SEL_4 4-bit Channel ID corresponding to external trigger 4. [11:8] read-write EXT_TRIGGER_SEL_3 4-bit Channel ID corresponding to external trigger 3. [15:12] read-write EXT_TRIGGER_SEL_2 Enable bit corresponding to channel id selected for trigger 2. [19:16] read-write EXT_TRIGGER_SEL_1 4-bit Channel ID corresponding to external trigger 1. [23:20] read-write RESERVED1 Reserved1 [31:24] read-write 16 0x10 ADC_CHn_BIT_MAP_CONFIG ADC Channel bit map configuration registers(0-15) 0x00000038 ADC_CH_n__BIT_MAP_CONFIG_0 This is configuration register0 to explain the bit map for ADC channels 0x00 32 read-write 0x00000000 CHANNEL__n__BITMAP ADC Channels bit map [31:0] read-write ADC_CH_n__BIT_MAP_CONFIG_1 This is configuration register1 to explain the bit map for ADC channels 0x04 32 read-write 0x00000000 CHANNEL__n__BITMAP ADC Channels bit map [31:0] read-write ADC_CH_n__BIT_MAP_CONFIG_2 This is configuration register2 to explain the bit map for ADC channels 0x08 32 read-write 0x00000000 CHANNEL__n__BITMAP ADC Channels bit map [31:0] read-write ADC_CH_n__BIT_MAP_CONFIG_3 This is configuration register3 to explain the bit map for ADC channels 0x0C 32 read-write 0x00000000 CHANNEL__n__BITMAP ADC Channels bit map [4:0] read-write RESERVED1 Reserved1 [31:5] read-write 16 0x4 ADC_CHn_OFFSET Initial offset value with respect to AUX_ADC clock after which Channel(0-15)should be sampled 0x138 ADC_CH_n1__OFFSET This Register specifies initial offset value with respect to AUX_ADC clock after which should sample channel. 0x00 32 read-write 0x00000000 CH_n__OFFSET This Register field specifies initial offset value with respect to AUX_ADC clock after which Channel(0-16)should be sampled. [15:0] read-write RESERVED1 Reserved1 [31:16] read-write 16 0x4 ADC_CHn_FREQ This register specifies Sampling frequency rate at which AUX ADC Date is sampled for Channel(1 to 16 ) 0x178 ADC_CH_n1__FREQ This register specifies Sampling frequency rate at which AUX ADC Date is sampled for Channel 0x00 32 read-write 0x00000000 CH_n__FREQ_VALUE This register specifies Sampling frequency rate at which AUX ADC Date is sampled for Channel all respective channel (1-16) [15:0] read-write RESERVED1 Reserved1 [31:16] read-write ADC_CH_PHASE_1 ADC Channel Phase 1 0x1B8 32 read-write 0x00000000 CH1_PHASE Phase corresponding to channel-1 [3:0] read-write CH2_PHASE Phase corresponding to channel-2 [7:4] read-write CH3_PHASE Phase corresponding to channel-3 [11:8] read-write CH4_PHASE Phase corresponding to channel-4 [15:12] read-write CH5_PHASE Phase corresponding to channel-5 [19:16] read-write CH6_PHASE Phase corresponding to channel-6 [23:20] read-write CH7_PHASE Phase corresponding to channel-7 [27:24] read-write CH8_PHASE Phase corresponding to channel-8 [31:28] read-write ADC_CH_PHASE_2 ADC Channel Phase 2 0x1BC 32 read-write 0x00000000 CH9_PHASE Phase corresponding to channel-9 [3:0] read-write CH10_PHASE Phase corresponding to channel-10 [7:4] read-write CH11_PHASE Phase corresponding to channel-11 [11:8] read-write CH12_PHASE Phase corresponding to channel-12 [15:12] read-write CH13_PHASE Phase corresponding to channel-13 [19:16] read-write CH14_PHASE Phase corresponding to channel-14 [23:20] read-write CH15_PHASE Phase corresponding to channel-15 [27:24] read-write CH16_PHASE Phase corresponding to channel-16 [31:28] read-write ADC_SINGLE_CH_CTRL_1 ADC SINGLE Channel Configuration 0x1C4 32 read-write 0x00000000 ADC_CH_INDEX_SINGLE_CHAN_1 [31:0]out of total 48 bits of bit map for single channel mode of a particular channel. [31:0] read-write ADC_SINGLE_CH_CTRL_2 ADC SINGLE Channel Configuration 0x1C8 32 read-write 0x00000000 ADC_CH_INDEX_SINGLE_CHAN_2 [47:32] out of total 48 bits of bit map for single channel mode of a particular channel. [15:0] read-write RESERVED1 Reserved1 [31:16] read-write ADC_SEQ_CTRL This register explain configuration parameter for AUXADC 0x1CC 32 read-write 0x00000000 ADC_SEQ_CTRL_PING_PONG To enable/disable per channel DAM mode (One-hot coding) [15:0] read-write ADC_SEQ_CTRL_DMA_MODE To enable/disable per channel ping-pong operation (One-hot coding). [31:16] read-write VAD_BBP_ID This register explain VDD BBP ID 0x1D0 32 read-write 0x00000000 RESERVED1 Reserved1 [5:0] read-write RESERVED2 Reserved2 [15:6] read-write DISCONNET_MODE Per channel discontinuous mode enable signal. When discontinuous mode is enabled,data is sampled only once from that channel and the enable bit is reset to 0. [31:16] read-write ADC_INT_MEM_1 This register explain start address of first/second buffer corresponding to the channel location ADC INT MEM 2 0x1D4 32 read-write 0x00000000 PROG_WR_DATA These 32-bits specifies the start address of first/second buffer corresponding to the channel location ADC INT MEM [31:0] read-write ADC_INT_MEM_2 This register explain ADC INT MEM2. 0x1D8 32 read-write 0x00000000 PROG_WR_DATA These 10-bits specify the buffer length of first/second buffer corresponding to the channel location ADC INT MEM2 [9:0] read-write PROG_WR_ADDR These bits correspond to the address of the internal memory basing on the channel number, whose information we want to program [14:10] read-write PROG_WR_DATA1 Valid bit for first/second buffers corresponding to ADC INT MEM2 [15:15] read-write RESERVED3 Reserved3 [31:16] read-write INTERNAL_DMA_CH_ENABLE This register is internal channel enable 0x1DC 32 read-write 0x00000000 PER_CHANNEL_ENABLE Enable bit for Each channel,like channel0 for bit0 to channel15 for bit15 etc [15:0] read-write RESERVED3 Reserved3 [30:16] read-write INTERNAL_DMA_ENABLE When Set, Internal DMA will be used for reading ADC samples from ADC FIFO and writing them to ULP SRAM Memories. [31:31] read-write TS_PTAT_ENABLE This register is enable PTAT for temperature sensor 0x1E0 32 read-write 0x00000000 TS_PTAT_EN BJT based Temperature sensor [0:0] read-write Enable Enable PTAT bit 1 Disable Disable PTAT bit 0 RESERVED1 Reserved1 [31:1] read-write ADC_FIFO_THRESHOLD Configured FIFO to ADC 0x1E4 32 write-only 0x00000000 ADC_FIFO_AEMPTY_THRESHOLD FIFO almost empty threshold for ADC [3:0] write-only ADC_FIFO_AFULL_THRESHOLD FIFO almost full threshold for ADC [7:4] write-only RESERVED1 Reserved1 [31:8] write-only BOD Programs resistor bank, reference buffer and scaler 0x200 32 read-write 0x00003E00 EN_BOD_TEST_MUX 1 - To enable test mux [0:0] read-write BOD_TEST_SEL Select bits for test mux [2:1] read-write REFBUF_EN Reference buffer configuration 1 for enable 0 for disable [3:3] read-write Disable Disable reference buffer enable bit 0 Enable Enable reference buffer enable bit 1 LVL_SEL selection of voltage of reference buffer [7:4] read-write BOD_RES_ENABLE configuration of register bank 1 for enable and 0 for disable [8:8] read-write Disable Disable register bank bit 0 Enable Enable register bank bit 1 BOD_THRESHOLD Programmability for resistor bank [13:9] read-write RESERVED1 Reserved1 [31:14] read-write COMPARATOR1 Programs comparators1 and comparators2 0x204 32 read-write 0x00000000 CMP1_EN To enable comparator1 [0:0] read-write Disable Disable comparator1 0 Enable Enable comparator1 1 CMP1_EN_FILTER To enable filter for comparator 1 [1:1] read-write Disable Disable filter for comparator1 0 Enable Enable filter to comparator1 1 CMP1_HYST Programmability to control hysteresis of comparator1 [3:2] read-write CMP1_MUX_SEL_P Select for positive input of comparator_1 [7:4] read-write comp1_p0 external pin as positive input for comparator1 0 comp1_p1 external pin as positive input for comparator1 1 DAC DAC as positive input for comparator1 2 reference_buffer_out reference_buffer_out as positive input for comparator1 3 reference_scaler_out reference_scaler_out as positive input for comparator1 4 register_bank_out register_bank_out as positive input for comparator1 5 opamp1 opamp1 as positive input for comparator1 6 opamp2 opamp2 as positive input for comparator1 7 opamp3 opamp3 as positive input for comparator1 8 CMP1_MUX_SEL_N Select for negative input of comparator_1 [11:8] read-write comp1_n0 external pin as negative input for comparator1 0 comp1_n1 external pin as negative input for comparator1 1 DAC DAC as negative input for comparator1 2 reference_buffer_out reference_buffer_out as negative input for comparator1 3 reference_scaler_out reference_scaler_out as negative input for comparator1 4 register_bank_out register_bank_out as negative input for comparator1 5 opamp1 opamp1 as negative input for comparator1 6 opamp2 opamp2 as negative input for comparator1 7 opamp3 opamp3 as negative input for comparator1 8 CMP2_EN To enable comparator 2 [12:12] read-write Disable Disable comparator2 0 Enable Enable comparator2 1 CMP2_EN_FILTER To enable filter for comparator 2 [13:13] read-write Disable Disable filter for comparator2 0 Enable Enable filter to comparator2 1 CMP2_HYST Programmability to control hysteresis of comparator2 [15:14] read-write CMP2_MUX_SEL_P Select for positive input of comparator_2 [19:16] read-write comp2_p0 external pin as positive input for comparator2 0 comp2_p1 external pin as positive input for comparator2 1 DAC DAC as positive input for comparator2 2 reference_buffer_out reference_buffer_out as positive input for comparator2 3 reference_scaler_out reference_scaler_out as positive input for comparator2 4 register_bank_out register_bank_out as positive input for comparator2 5 opamp1 opamp1 as positive input for comparator2 6 opamp2 opamp2 as positive input for comparator2 7 opamp3 opamp3 as positive input for comparator2 8 CMP2_MUX_SEL_N Select for negative input of comparator_2 [23:20] read-write comp2_n0 external pin as negative input for comparator2 0 comp2_n1 external pin as negative input for comparator2 1 DAC DAC as negative input for comparator2 2 reference_buffer_out reference_buffer_out as negative input for comparator2 3 reference_scaler_out reference_scaler_out as negative input for comparator2 4 register_bank_out register_bank_out as negative input for comparator2 5 opamp1 opamp1 as negative input for comparator2 6 opamp2 opamp2 as negative input for comparator2 7 opamp3 opamp3 as negative input for comparator2 8 COM_DYN_EN Dynamic enable for registers [24:24] read-write RESERVED1 Reserved1 [31:25] read-write AUXADC_CONFIG_2 This register is AUX-ADC config2 0x208 32 read-write 0x00000000 RESERVED1 Reserved1 [10:0] read-write AUXADC_DYN_ENABLE Aux ADC Configuration Enable [11:11] read-write RESERVED2 Reserved2 [31:12] read-write AUXDAC_CONIG_1 This register is AUX-DAC config1 0x20C 32 read-write 0x00000000 AUXDAC_EN_S Enable signal DAC [0:0] read-write AUXDAC_OUT_MUX_EN Aux OUT mux Enable [1:1] read-write Enable DAC output is connected to PAD 1 Disable DAC output is not connected to PAD 0 AUXDAC_OUT_MUX_SEL AUXDAC OUT MUX SELECT Enable [2:2] read-write Enable DAC Output is connected to AGPIO15 1 Disable DAC Output is connected to AGPIO4 0 RESERVED1 Reserved1 [3:3] read-write AUXDAC_DATA_S Satatic AUX Dac Data [13:4] read-write AUXDAC_DYN_EN Satatic AUX Dac Data [14:14] read-write RESERVED2 Reserved2 [31:15] read-write AUX_LDO This register is AUX-LDO configuration 0x210 32 read-write 0x00000053 LDO_CTRL Enable ldo control field [3:0] read-write LDO_DEFAULT_MODE ldo default mode enable [4:4] read-write BYPASS_LDO bypass the LDO [5:5] read-write ENABLE_LDO Turn LDO [6:6] read-write DYN_EN Dynamic Enable [7:7] read-write RESERVED1 Reserved [31:8] read-write IR_Decoder 1.0 IR Decoder are used for the decoding the external ir sensor input. 0x24040C00 32 read-write 0 0x1C registers IR_DECODER 15 IR_OFF_TIME_DURATION This register used for IR sleep duration timer value. 0x00 32 read-write IR_OFF_TIME_DURATION This field define ir off time [16:0] read-write RES reserved5 [31:17] read-only IR_ON_TIME_DURATION This register used for IR Detection duration timer value. 0x04 32 read-write IR_ON_TIME_DURATION This field define ir on time for ir detection on [11:0] read-write RES reserved5 [31:12] read-only IR_FRAME_DONE_THRESHOLD This register used count with respect to 32KHz clock after not more toggle are expected to a given pattern. 0x08 32 read-write IR_FRAME_DONE_THRESHOLD count with respect to 32KHz clock after not more toggle are expected to a given pattern [14:0] read-write RES reserved5 [31:15] read-only IR_DET_THRESHOLD This register used Minimum Number of edges to detected during on-time failing which IR detection is re-stated. 0x0C 32 read-write IR_DET_THRESHOLD Minimum Number of edges to detected during on-time failing which IR detection is re-stated. [6:0] read-write RES reserved5 [31:7] read-only IR_CONFIG This register used to configure the ir structure for application purpose. 0x10 32 read-write EN_IR_DET Enable IR detection logic bit if bit 1 then detection enable if 0 then not enable. [0:0] read-write IR_DET_RSTART Enable IR detection re-start logic bit if bit 1 then re-start. [1:1] read-write EN_CLK_IR_CORE Enable 32KHz clock to IR Core bit ,if bit 1 then clock gating disable and bit is 0 then clock gating Enable [2:2] read-write RES reserved5 [7:3] read-only EN_CONT_IR_DET This bit is Enable continues IR detection,When enabled there will be no power cycling on External IR Sensor. [8:8] read-write RES1 reserved6 [15:9] read-only SREST_IR_CORE This bit is used soft reset IR core block [16:16] read-write RES2 reserved7 [31:17] read-only IR_MEM_ADDR_ACCESS This register used to access memory address for application purpose. 0x14 32 read-write IR_MEM_ADDR This field is used to IR read address. [6:0] read-write RES reserved5 [7:7] read-write IR_MEM_WR_EN IR memory write enable. [8:8] read-write IR_MEM_RD_EN This field used to IR memory read enable. [9:9] read-write RES1 reserved1 [15:10] read-write IR_MEM_WR_TEST_MODE IR memory write enable in test mode.. [16:16] read-write RES2 reserved2 [31:17] read-write IR_MEM_READ This register used to IR Read data from memory. 0x18 32 read-only IR_MEM_DATA_OUT This field is used to IR Read data from memory. [15:0] read-only RES reserved5 [23:16] read-only IR_DATA_MEM_DEPTH This field used to indicated valid number of IR Address in the memory to be read. [30:24] read-only RES1 reserved6 [31:31] read-only CTS 1.0 The capacitive touch sensor (CTS) controller is used to detect the position of the touch from the user on the capacitive touch screen CAPACITIVE_TOUCH_SENSOR 0x24042C00 32 read-write 0x00 0x124 registers CAP_SENSOR 6 CTS_CONFIG_REG_0_0 Configuration Register 0_0 0x00 32 read-write 0x00000000 CLK_SEL1 Mux select for clock_mux_1 [1:0] read-write PRE_SCALAR_1 Division factor for clock divider [9:2] read-write PRE_SCALAR_2 Division factor for clock divider [13:10] read-write CLK_SEL2 Mux select for clock_mux_2 [14:14] read-write CTS_STATIC_CLK_EN Enable static for capacitive touch sensor [15:15] read-write disable Clocks are gated 0 enable Clocks are not gated 1 FIFO_AFULL_THRLD Threshold for fifo afull [21:16] read-write FIFO_AEMPTY_THRLD Threshold for fifo aempty [27:22] read-write FIFO_EMPTY FIFO empty status bit [28:28] read-only RESERVED1 Reserved1 [31:29] read-only CTS_CONFIG_REG_1_1 Configuration Register 1_1 0x100 32 read-write 0x00000000 POLYNOMIAL_LEN Length of polynomial [1:0] read-write SEED_LOAD Seed of polynomial [2:2] read-write disable loading of seed is not allowed 0 enable to load the seed 1 BUFFER_DELAY Delay of buffer. Delay programmed will be equal to delay in nano seconds. Max delay value is 32.Default delay should be programmed before using Capacitive touch sensor module. [7:3] read-write WAKE_UP_ACK Ack for wake up interrupt. This is a level signal. To acknowledge wake up , set this bit to one and reset it . [8:8] read-write ENABLE1 Enable signal [9:9] read-write disable disable the cap sensor module 0 enable enable the cap sensor module 1 SOFT_RESET_2 Reset the FIFO write and FIFO read occupancy pointers [10:10] read-write CNT_ONEHOT_MODE Continuous or One hot mode [11:11] read-write One_hot disable the cap sensor module 0 Continuous enable the cap sensor module 1 SAMPLE_MODE Select bits for FIFO write and FIFO average [13:12] read-write RESET_WR_FIFO Resets the signal fifo_wr_int [14:14] read-write Reset Reset 0 Out_of_reset Out of reset 1 BYPASS Bypass signal [15:15] write-only Disable Use Random number generator output bit as input to Non-Overlapping stream generator. 0 Enable Bypass the Random number generator output to the Non-overlapping stream generator and to give clock as input to the Non-Overlapping stream generator. 1 BIT_SEL Selects different set of 12 bits to be stored in FIFO [17:16] read-write EXT_TRIG_SEL Select bit for NPSS clock or Enable [18:18] read-write EXT_TRIG_EN Select bit for NPSS clock or Enable [19:19] read-write Enable Enable 0 Clock NPSS clock 1 RESERVED2 Reserved2 [31:20] read-write CTS_CONFIG_REG_1_2 Configuration Register 1_2 0x104 32 read-write 0x00000000 PWM_ON_PERIOD PWM ON period [15:0] read-write PWM_OFF_PERIOD PWM OFF period [31:16] read-write CTS_CONFIG_REG_1_3 Configuration Register 1_3 0x108 32 read-write 0x00000000 PRS_SEED Pseudo random generator (PRS) seed value [31:0] read-write CTS_CONFIG_REG_1_4 Configuration Register 1_4 0x10C 32 read-write 0x00000000 PRS_POLY Polynomial programming register for PRS generator [31:0] read-write CTS_CONFIG_REG_1_5 Configuration Register 1_5 0x110 32 read-write 0x000000FF INTER_SENSOR_DELAY Inter-sensor scan delay value [15:0] read-write N_SAMPLE_COUNT Number of repetitions of sensor scan [31:16] read-write CTS_CONFIG_REG_1_6 Configuration Register 1_6 0x114 32 read-write 0x00000000 SENSOR_CFG Register of scan controller containing the programmed bit map [31:0] read-write CTS_CONFIG_REG_1_7 Configuration Register 1_7 0x118 32 read-write 0x00000080 VALID_SENSORS Value of number of sensors valid in the bit map [3:0] read-write RESERVED1 Reserved1 [5:4] read-write REF_VOLT_CONFIG This is given as an input voltage to analog model as comparator reference voltage. [14:6] read-write WAKEUP_MODE Select bit for high/low mode. [15:15] read-write Greater_Than Wakeup if count is greater than threshold 1 Less_Than Wakeup if count is lesser than threshold 0 WAKE_UP_THRESHOLD Wakeup threshold. [31:16] read-write CTS_CONFIG_REG_1_8 Configuration Register 1_8 0x11C 32 read-only 0x00000000 PRS_STATE Current state of PRS [31:0] read-only CTS_CONFIG_REG_1_9 Configuration Register 1_9 0x120 32 read-write 0x00000000 TRIG_DIV Allows one pulse for every 'trig_div' no. of pulses of 1 ms clock [9:0] read-write RESERVED1 Reserved1 [31:10] read-write CTS_FIFO_ADDRESS FIFO Address Register 0x004 32 read-write 0x00000000 FIFO Used for FIFO reads and write operations [31:0] read-write MCU_CONFIG 1.0 MISC CONFIG Register MISC_CONFIG 0x46008000 0x00 0x1F8 registers NPSS_TO_MCU_WDT_INTR 20 NPSS_TO_MCU_GPIO_INTR 21 NPSS_TO_MCU_CMP_RF_WKP_INTR 22 NPSS_TO_MCU_BOD_INTR 23 NPSS_TO_MCU_BUTTON_INTR 24 NPSS_TO_MCU_SDC_INTR 25 NPSS_TO_MCU_WIRELESS_INTR 26 NPSS_MCU_INTR 27 MCU_CAL_ALARM 28 MCU_CAL_RTC 29 MCU_CAL_RTC 29 HIF0 35 HIF1 36 EGPIO_WAKEUP 41 PLL_CLOCK 69 TASS_P2P 74 MCR_HOST_SPI_INTR_MASK_REG MISC CFG HOST INTR MASK 0x00 32 read-write 0x00000000 HOST_INTR_MSK Writing 1 in any bit masks the corresponding interrupt in HOST_INTR_STATUS. [7:0] read-write HOST_SPI_INTR_OPEN_DRAIN_MODE Writing 1 to this bit configures the host SPI interrupt in open drain mode. When open drain mode is enabled and interrupt is configured in active high mode, external PULLDOWN has to be used on the board. [8:8] read-write HOST_SPI_INTR_ACTIVE_LOW_MODE Writing 1 to this bit configures the host SPI interrupt in active low mode. By default, it will be active high. [9:9] read-write RESERVED1 reserved1 [31:10] read-write MCR_HOST_SPI_INTR_SET_REG MCU host spi interrupt set register 0x04 32 read-write 0x00000000 HOST_SPI_INTR_STATUS Writing '1' to any bit raises an interrupt to SPI host. Writing '1' at the corresponding bit position in MCR_HOST_SPI_INTR_CLR clears the interrupt. Performing read gives HOST_SPI_INTR_STATUS always. [7:0] read-write RESERVED1 reserved1 [31:8] read-write MCR_HOST_SPI_INTR_CLR_REG MCU host spi interrupt clear register 0x08 32 read-write 0x00000000 HOST_SPI_INTR_CLEAR Writing '1' to this bit clears the MCR_HOST_SPI_INTR_SET_REG. This register gets cleared in the next clock cycle. Performing read gives HOST_SPI_INTR_STATUS always [7:0] read-write RESERVED1 reserved1 [31:8] read-write MCR_HOST_CTRL_REG MCU host control register 0x0C 32 read-write 0x00008004 ready_from_core Indication to the host that bootloading is done. When the reset latch bootload_en is '0' , firmware sets this bit. When hardware bootloading is enabled , this gets set only after bootloading is done. When hardware bootloading is enabled and bootloader is programmed to release the PC from soft reset, firmware sets this bit. [0:0] read-write host_spi_poweron_rst This is an active high reset which is used to generate host reset. This has to be enabled only in SPI Host Mode. [1:1] read-write host_spi_bus_err_oen Host SPI Bus error output enable. It is active low signal. [2:2] read-write Enabled SPI Bus error output is enabled 0 Disabled SPI Bus error output is disabled. 1 host_spi_bus_err_out Host SPI Bus error output. [3:3] read-write No_Error There is no error on Host SPI receive transaction 0 Error There is error in Host SPI receive transaction 1 host_spi_bus_err_in Host SPI Bus error input. [4:4] read-only No_Error There is no error on Host SPI transmit transaction 0 Error There is error in Host SPI transmit transaction 1 Reserved Reserved [7:5] read-write host_sel Selects the Host on 1st Interface [9:8] read-write load_host_mode Overrides the Hardware detected Host on 1st interface. [10:10] read-write H_W_Host_detection H/W based host detection 0 S_W_Host_detection S/W based host detection 1 Reserved Reserved [11:11] read-write host_sel_2 Selects the Host on 2nd Interface [13:12] read-write load_host_mode_2 Overrides the Hardware detected Host on 2nd interface. [14:14] read-write sdio_spi_prog_sel Used to select to use SDIO/ High speed SPI slave [15:15] read-write SELECT_SDIO MCU can access SDIO registers 1 SELECT_SPI MCU can access SPI registers 0 RESERVED1 reserved1 [31:16] read-write MCR_RST_LATCH_STATUS_REG MCU reset latch status register 0x10 32 read-only 0x0000000E Boot_mode_en This bit is used to indicate if boot mode is enabled. [0:0] read-only boot_mode Reserved [2:1] read-only sdio_sel This bit indicates the SDIO slave host select [3:3] read-only SDIO_SELECTED SDIO is selected 1 SDIO_NOT_SELECTED SDIO is not selected 0 spi_sel This bit indicates the High speed SPI slave host select [4:4] read-only SPI_SELECTED SPI is selected 1 SPI_NOT_SELECTED SPI is not selected 0 Reserved Reserved [5:5] read-only ram_retention_status This bit indicates whether RAM is retained or not. [6:6] read-only RAM_RETAINED Ram Retained 1 RAM_NOT_RETAINED Ram is not retained 0 mcu_first_powerup_por This bit indicates MCU first power up status [7:7] read-only ulp_wakeup This bit differentiates between normal power up and ULP wakeup state [8:8] read-only ULP_WAKEUP ULP Based wakeup 1 NOT_ULP_WAKEUP Not ULP based wakeup(first powerup) 0 Reserved Reserved [9:9] read-only Reserved Reserved [15:10] read-only NA NA [31:16] read-only MCR_MCU_P2P_INTR_SET_REG MCU to NWP P2P Interrupt Set Register 0x16C 32 read-write 0x00000000 MCU_P2P_INTR_SET 16 P2P interrupts for communication from MCU to NWP,Each bit is used to clear the interrupt to NWP [15:0] read-write WRITE_1 Raises the Interrupt 1 WRITE_0 No effect 0 READ_1 Interrupt is raised 1 READ_0 Interrupt not raised 0 RESERVED1 reserved1 [31:16] read-only MCR_NWP_P2P_INTR_MASK_SET_REG NWP to MCU P2P Interrupt Mask Register 0x178 32 read-write 0x0000FFFF 0x0000FFFF NWP_P2P_INTR_MASK 16 P2P interrupts for communication from MCU to NWP,Each bit is used to mask the NWP P2P interrupt [15:0] read-write Mask_NWP_P2P_Interrupt Masks the NWP P2P Interrupt 1 Not_Raised Not Raised 0 RESERVED1 reserved1 [31:16] read-only MCR_NWP_P2P_INTR_MASK_CLR_REG NWP to MCU P2P Interrupt Unmask Register 0x17C 32 read-write 0x0000FFFF 0x0000FFFF NWP_P2P_INTR_UNMASK 16 P2P interrupts for communication from MCU to NWP,Each bit is used to unmask the NWP P2P interrupt [15:0] read-write Unmask_NWP_P2P_Interrupt unmasks the NWP P2P Interrupt 1 Not_Raised Not raised 0 RESERVED1 reserved1 [31:16] read-only MCR_MCU_P2P_INTR_CLR_REG MCU to NWP P2P Interrupt Clear Register 0x170 32 read-write 0x00000000 MCU_P2P_INTR_CLR 16 P2P interrupts for communication from MCU to NWP,Each bit is used to clear the interrupt to NWP [15:0] read-write WRITE_1 Clears the Interrupt 1 WRITE_0 No effect 0 READ_1 Interrupt is raised 1 READ_0 Interrupt not raised 0 RESERVED1 reserved1 [31:16] read-only MCR_NWP_P2P_INTR_CLR_REG NWP to MCU P2P Interrupt Clear Register 0x180 32 read-write 0x00000000 NWP_P2P_INTR_CLR 16 P2P interrupts for communication from MCU to NWP,Each bit is used to clear the interrupt to NWP [15:0] read-write WRITE_1 Clears the Interrupt for MCU instantly 1 WRITE_0 No effect 0 READ_1 Interrupt is raised 1 READ_0 Interrupt not raised 0 RESERVED1 reserved1 [31:16] read-only MCR_MCU_P2P_COMM_STATUS_REG MCU to NWP P2P Communication Status Register 0x174 32 read-write 0x00000000 MCU_Wakeup_NWP This bit is used to wakeup NWP from sleep. [0:0] read-write HIGH MCU wakesup NWP 1 LOW No Operation 0 MCU_Active_Status This bit is used to indicate NWP that MCU is active [1:1] read-write MCU_Active MCU is active 1 MCU_Sleeping MCU is sleeping 0 NWP_Wakeup_MCU This bit is used to indicate MCU that it should wakeup from sleep [2:2] read-only NWP_Wakesup_MCU NWP wakes up MCU 1 No_Operation MCU is sleeping 0 NWP_Active_Status This bit is used to indicate MCU that NWP is active [3:3] read-only NWP_Active NWP is active 1 NWP_Sleeping NWP is sleeping 0 RESERVED1 reserved1 [31:4] read-only 4 0x8 MCR_PERI_INTR_MASK_REGn MCR_PERI_INTR_MASK_SET_TH0_REG (0-3) and MCR_PERI_INTR_MASK_CLR_TH0_REG (0-3) 0x184 MCR_PERI_INTR_MASK_SET_TH_n__REG Mask Register for MCU HP Peripheral Interrupts going to NWP on Thread 0x00 32 read-write 0x1FFFFFFF 0x1FFFFFFF MCU_PERI_MSK_SET Each bit is used to mask the respective MCU HP peripheral interrupt. [28:0] read-write No_Effect_Write Writing a zero into this has no effect. 0 Masks_Interrupts_write Masks the interrupt 1 Interrupt_masked_read Interrupt is masked 1 Interrupt_Not_Masked_read Interrupt not masked 0 RESERVED1 reserved1 [31:29] read-only MCR_PERI_INTR_MASK_CLR_TH_n__REG Unmask Register for MCU HP Peripheral Interrupts going to NWP on Thread 0x04 32 read-write 0x1FFFFFFF 0x1FFFFFFF MCU_PERI_MSK_CLR Each bit is used to unmask the respective MCU HP peripheral interrupt. [28:0] read-write No_Effect_Write Writing a zero into this has no effect. 0 Unmasks_Interrupt_write Unmasks the interrupt 1 Interrupt_masked_read Interrupt is masked 1 Interrupt_Not_Masked_read Interrupt not masked 0 RESERVED1 reserved1 [31:29] read-only 4 0x4 MCR_PERI_INTR_STS_THn_REG MCR_PERI_INTR_STS_TH_REG (0-3) 0x1A4 MCR_PERI_INTR_STS_TH_n__REG Status Register for MCU HP Peripheral Interrupts going to NWP on Thread 0x00 32 read-only 0x00 0x00 MCU_PERI_INTR_STATUS If bit m of (28:0) is 1, then the mth MCU HP peripheral interrupt is not masked and is been raised in thread [28:0] read-only MCU_HP_Peripheral_1_Not_Masked MCU HP peripheral 1 interrupt not masked 0x00000001 MCU_HP_Peripheral_2_Not_Masked MCU HP peripheral 2 interrupt not masked 0x00000002 MCU_HP_Peripheral_3_Not_Masked MCU HP peripheral 3 interrupt not masked 0x00000004 MCU_HP_Peripheral_4_Not_Masked MCU HP peripheral 4 interrupt not masked 0x00000008 MCU_HP_Peripheral_5_Not_Masked MCU HP peripheral 5 interrupt not masked 0x00000010 MCU_HP_Peripheral_6_Not_Masked MCU HP peripheral 6 interrupt not masked 0x00000020 MCU_HP_Peripheral_7_Not_Masked MCU HP peripheral 7 interrupt not masked 0x00000040 MCU_HP_Peripheral_8_Not_Masked MCU HP peripheral 8 interrupt not masked 0x00000080 MCU_HP_Peripheral_9_Not_Masked MCU HP peripheral 9 interrupt not masked 0x00000100 MCU_HP_Peripheral_10_Not_Masked MCU HP peripheral 10 interrupt not masked 0x00000200 MCU_HP_Peripheral_11_Not_Masked MCU HP peripheral 11 interrupt not masked 0x00000400 MCU_HP_Peripheral_12_Not_Masked MCU HP peripheral 12 interrupt not masked 0x00000800 MCU_HP_Peripheral_13_Not_Masked MCU HP peripheral 13 interrupt not masked 0x00001000 MCU_HP_Peripheral_14_Not_Masked MCU HP peripheral 14 interrupt not masked 0x00002000 MCU_HP_Peripheral_15_Not_Masked MCU HP peripheral 15 interrupt not masked 0x00004000 MCU_HP_Peripheral_16_Not_Masked MCU HP peripheral 16 interrupt not masked 0x00008000 MCU_HP_Peripheral_17_Not_Masked MCU HP peripheral 17 interrupt not masked 0x00010000 MCU_HP_Peripheral_18_Not_Masked MCU HP peripheral 18 interrupt not masked 0x00020000 MCU_HP_Peripheral_19_Not_Masked MCU HP peripheral 19 interrupt not masked 0x00040000 MCU_HP_Peripheral_20_Not_Masked MCU HP peripheral 20 interrupt not masked 0x00080000 MCU_HP_Peripheral_21_Not_Masked MCU HP peripheral 21 interrupt not masked 0x00100000 MCU_HP_Peripheral_22_Not_Masked MCU HP peripheral 22 interrupt not masked 0x00200000 MCU_HP_Peripheral_23_Not_Masked MCU HP peripheral 23 interrupt not masked 0x00400000 MCU_HP_Peripheral_24_Not_Masked MCU HP peripheral 24 interrupt not masked 0x00800000 MCU_HP_Peripheral_25_Not_Masked MCU HP peripheral 25 interrupt not masked 0x01000000 MCU_HP_Peripheral_26_Not_Masked MCU HP peripheral 26 interrupt not masked 0x02000000 MCU_HP_Peripheral_27_Not_Masked MCU HP peripheral 27 interrupt not masked 0x04000000 MCU_HP_Peripheral_28_Not_Masked MCU HP peripheral 28 interrupt not masked 0x08000000 RESERVED1 reserved1 [31:29] read-only MCR_MEM_RM_RME_REG Memory RM and RME Control Register 0x1B8 32 read-write 0x00020002 MCU_ram_rom_rm_rme [2:1] bits are used as RM ports for SRAM memories,[0] bit is used as RM enable (RME) for SRAM memories. [2:0] read-write Reserved Reserved [15:3] read-only MCU_fifo_rm_rme [18:17] bits are used as RM ports for fifo memories which are internal to peripherals.[16] bit is used as RM enable (RME) for fifo memories which are internal to peripherals. [18:16] read-write Enabled SPI Bus error output is enabled 0 Disabled SPI Bus error output is disabled. 1 RESERVED1 reserved1 [31:19] read-only MCR_ULP_AHB_BRIDGE_CLK_ENABLE_REG ULP AHB-AHB bridge static clock enable register 0x1FC 32 read-write 0x00000001 ULP_AHB_bridge_clk_enable Used to enable static clock gating ULP AHB-AHB bridge. Only 32-bit write is allowed into this register. [0:0] read-write RESERVED1 reserved1 [31:1] read-only MCR_AHB_MASTER_TRAP_ENABLE_64K1 AHB Master Trap Enable Register for memory set 64K1 0x1C8 32 read-write 0x00000000 Reserved Reserved [15:0] read-only Trap_enable_bits_per_master_64K1 '1' on a particular bit position indicates that access by that master to a trap enable bank will generate trap otherwise if it is '0' it won't generate a trap if it is accessing a trap enable bank. The masking is for UM1 transactions indicated in DMA_WR_TRAP_ENABLE_REG_64K1, DMA_WR_TRAP_ENABLE_REG_64K1 [31:16] read-write MCR_DM_TRAP_STATUS_64K1 DM Trap Status Register for memory set 64K1 0x1D0 32 read-only 0x00000000 Gnt The grant signal for pm port of unified memory. [0:0] read-only Write_or_read to check whether its read or write request [1:1] read-only Read_Request Read request 0 Write_request write request 1 master_number The number of the master which requested the transaction. [5:2] read-only Address The address for which the read or write request came on dm port. [24:6] read-only MCR_DMA0_TRAP_STATUS_64K1 DMA0 Trap Status Register for memory set 64K1 0x1D4 32 read-only 0x00000000 Gnt The grant signal for pm port of unified memory. [0:0] read-only Write_or_read to check whether its read or write request [1:1] read-only Read_Request Read request 0 Write_request write request 1 master_number The number of the master which requested the transaction. [5:2] read-only Address The address for which the read or write request came on dm0 port. [24:6] read-only MCR_DMA1_TRAP_STATUS_64K1 DMA1 Trap Status Register for memory set 64K1 0x1D8 32 read-only 0x00000000 Gnt The grant signal for pm port of unified memory. [0:0] read-only Write_or_read to check whether its read or write request [1:1] read-only Read_Request Read request 0 Write_request write request 1 master_number The number of the master which requested the transaction. [5:2] read-only Address The address for which the read or write request came on dm1 port. [24:6] read-only MCR_DMA2_TRAP_STATUS_64K1 DMA2 Trap Status Register for memory set 64K1 0x1DC 32 read-only 0x00000000 Gnt The grant signal for pm port of unified memory. [0:0] read-only Write_or_read to check whether its read or write request [1:1] read-only Read_Request Read request 0 Write_request write request 1 master_number The number of the master which requested the transaction. [5:2] read-only Address The address for which the read or write request came on dm2 port. [24:6] read-only MCR_DM_TRAP_ENABLE_REG_64K1 DM Trap Enable Register for memory set 64K1 0x1E0 32 read-write 0x00000000 Enable_Bits_Per_Bank_Memory_Set_4 LSB corresponds to 0th bank in the particular set. A '1' in any bit position indicates that if through that port that bank access , a trap will be generated [3:0] read-write Reserved Reserved [31:4] read-only MCR_DM_TRAP_ENABLE_REG_64K0 DM Trap Enable Register for memory set 64K0 0x118 32 read-write 0x00000000 Enable_Bits_Per_Bank_Memory_Set_4 LSB corresponds to 0th bank in the particular set. A '1' in any bit position indicates that if through that port that bank access , a trap will be generated [3:0] read-write Reserved Reserved [31:4] read-only MCR_DMA_RD_TRAP_ENABLE_REG_64K1 DMA Read Trap Enable Register for memory set 64K1 0x1E4 32 read-write 0x00000000 Enable_Bits_Per_Bank_Memory_Set_4 LSB corresponds to 0th bank in the particular set. A '1' in any bit position indicates that if through that port that bank access , a trap will be generated [7:0] read-write Reserved Reserved [31:8] read-only MCR_DMA_RD_TRAP_ENABLE_REG_64K0 DMA Read Trap Enable Register for memory set 64K0 0x124 32 read-write 0x00000000 Enable_Bits_Per_Bank_Memory_Set_4 LSB corresponds to 0th bank in the particular set. A '1' in any bit position indicates that if through that port that bank access , a trap will be generated [7:0] read-write Reserved Reserved [31:8] read-only MCR_DMA_WR_TRAP_ENABLE_REG_64K1 DMA Write Trap Enable Register for memory set 64K1 0x1E8 32 read-write 0x00000000 Enable_Bits_Per_Bank_Memory_Set_4 LSB corresponds to 0th bank in the particular set. A '1' in any bit position indicates that if through that port that bank access , a trap will be generated [7:0] read-write Reserved Reserved [31:8] read-only MCR_DMA_WR_TRAP_ENABLE_REG_64K0 DMA Write Trap Enable Register for memory set 64K0 0x130 32 read-write 0x00000000 Enable_Bits_Per_Bank_Memory_Set_4 LSB corresponds to 0th bank in the particular set. A '1' in any bit position indicates that if through that port that bank access , a trap will be generated [7:0] read-write Reserved Reserved [31:8] read-only MCR_ASYNC_TRAP_STATUS_64K1 Async Trap Status Register for memory set 64K1 0x1EC 32 read-only 0x00000000 Reserved Reserved [0:0] read-only DM_Trap Async trap is detected from cortex IM port [1:1] read-only AHB_Read_Trap Async read is detected from other AHB ports [2:2] read-only AHB_Write_Trap Async write trap is detected from other AHB ports [3:3] read-only Reserved Reserved [31:5] read-only MCR_ASYNC_TRAP_STATUS_160K Async Trap Status Register for memory set 160K 0x13C 32 read-only 0x00000000 Reserved Reserved [0:0] read-only DM_Trap Async trap is detected from cortex IM port [1:1] read-only AHB_Read_Trap Async read is detected from other AHB ports [2:2] read-only AHB_Write_Trap Async write trap is detected from other AHB ports [3:3] read-only Reserved Reserved [31:5] read-only MCR_ASYNC_TRAP_STATUS_64K0 Async Trap Status Register for memory set 64k0 0x148 32 read-only 0x00000000 Reserved Reserved [0:0] read-only DM_Trap Async trap is detected from cortex IM port [1:1] read-only AHB_Read_Trap Async read is detected from other AHB ports [2:2] read-only AHB_Write_Trap Async write trap is detected from other AHB ports [3:3] read-only Reserved Reserved [31:5] read-only MCR_ASYNC_TRAP_CLEAR_64K1 Async Trap Clear Register for memory set 64K1 0x1F0 32 read-only 0x00000000 Reserved Reserved [0:0] read-only DM_Trap Reading 1 Indicates Async trap is cleared from cortex IM port [1:1] read-only Aynch_Trap_Cleared Async trap is cleared from cortex IM port 1 AHB_Read_Trap Reading 1 indiacates Async read is cleared from other AHB ports [2:2] read-only Aynch_Read_Cleared Async read is cleared from other AHB ports 1 AHB_Write_Trap Reading 1 indicates Async write trap is cleared from other AHB ports [3:3] read-only Aynch_Write_Trap_Cleared Async read is cleared from other AHB ports 1 Reserved Reserved [31:5] read-only MCR_ASYNC_TRAP_CLEAR_160K Async Trap Clear Register for memory set 160K 0x150 32 read-only 0x00000000 Reserved Reserved [0:0] read-only DM_Trap Reading 1 Indicates Async trap is cleared from cortex IM port [1:1] read-only Aynch_Trap_Cleared Async trap is cleared from cortex IM port 1 AHB_Read_Trap Reading 1 indiacates Async read is cleared from other AHB ports [2:2] read-only Aynch_Read_Cleared Async read is cleared from other AHB ports 1 AHB_Write_Trap Reading 1 indicates Async write trap is cleared from other AHB ports [3:3] read-only Aynch_Write_Trap_Cleared Async read is cleared from other AHB ports 1 Reserved Reserved [31:5] read-only MCR_ASYNC_TRAP_CLEAR_64K0 Async Trap Clear Register for memory set 64K0 0x15C 32 read-only 0x00000000 Reserved Reserved [0:0] read-only DM_Trap Reading 1 Indicates Async trap is cleared from cortex IM port [1:1] read-only Aynch_Trap_Cleared Async trap is cleared from cortex IM port 1 AHB_Read_Trap Reading 1 indiacates Async read is cleared from other AHB ports [2:2] read-only Aynch_Read_Cleared Async read is cleared from other AHB ports 1 AHB_Write_Trap Reading 1 indicates Async write trap is cleared from other AHB ports [3:3] read-only Aynch_Write_Trap_Cleared Async read is cleared from other AHB ports 1 Reserved Reserved [31:5] read-only MCR_ASYNC_TRAP_DETECTED_64K1 Async Trap Detected Register for memory set 64K1 0x1F4 32 read-write 0x00000000 Async_Trap_Detected_Cortex This will give you the indication that trap has been detected by cortex. Firmware has to write this bit as '1' so that the asyn_trap can be cleared. [0:0] read-write Reserved Reserved [15:1] read-only MCR_ASYNC_TRAP_DETECTED_64K0 Async Trap Detected Register for memory set 64K0 0x164 32 read-write 0x00000000 Async_Trap_Detected_Cortex This will give you the indication that trap has been detected by cortex. Firmware has to write this bit as '1' so that the asyn_trap can be cleared. [0:0] read-write Reserved Reserved [15:1] read-only MCR_DCACHE_CTRL_AND_STATUS_REG Dcache Control and Status Register 0x1F8 32 read-write 0x60064EBB pwr_qreqn Active-LOW quiescence request signal driven by the power controller. [0:0] read-write pwr_qacceptn When 0, indicates that the AHB Cache accepts the quiescence request from the power controller [1:1] read-only pwr_qdeny When 1, indicates that the AHB Cache denies the quiescence request from the power controller [2:2] read-only pwr_qactive 1 indicates to the controller that the AHB Cache needs power,0 indicates the AHB Cache might accept a quiescence request [3:3] read-only clk_qreqn Active-LOW quiescence request signal driven by the clock controller. [4:4] read-write clk_qacceptn When 0, indicates that the AHB Cache accepts the quiescence request from the clock controller. [5:5] read-only clk_qdeny When 1 indicates that the AHB Cache denies the quiescence request from the clock controller. [6:6] read-only clk_qactive when 1, indicates to the controller that the AHB Cache requires the clock. When 0, the AHB Cache might accept a quiescence request. [7:7] read-only hnonsec_s Non-secure transfer indicator,Asserted for a Non-secure transfer and Deasserted for a Secure transfer [8:8] read-write hprot Since Dcache is AHB 5 compatible, The remaining signals are included in this register as configurable. [11:9] read-write hnonsec_m Assertion indicates for a Non-secure transfer and Deasserted for a Secure transfer [12:12] read-only pslverr Indicates a transfer failure [13:13] read-only pclken The clock enable signal. This signal allows the APB to run on a divided frequency. [17:17] read-write pwakeup Wake up signal,Indicates that there is ongoing activity that is associated with the APB interface [18:18] read-write pwr_maintenance deasserted indicates cache powerdown preparation done.Asserted if powerdown maintenance is ongoing [19:19] read-only pmsnapshotreq A trigger signal which initiates the capture of the current value of the statistics counters. Must be a synchronous pulse. [20:20] read-write apb_violation_resp If HIGH,indicates the AHB Cache responds with errors to failed APB accesses by asserting pslverr [21:21] read-write power_on_enable This signal enables the cache automatically after powerup. [22:22] read-write dis_pwr_down_maint This signal turns off powerdown maintenance. [23:23] read-write dis_cache_en_maint This signal turns off cache enable maintenance. [24:24] read-write dis_cache_dis_maint This signal turns off cache disable maintenance. [25:25] read-write hprot_old This signal represents the ahb3 hprot description [29:26] read-write mvp_qreqn This input is for the MVP q channel interface. (MVP is not using qchannel active low signal) [30:30] read-write Reserved Reserved [31:31] read-only MCR_DMA_DEVICE_SEL_REG MCU DMA device select register 0x108 32 read-write 0x00000000 RESERVED Reserved [0:0] read-write I2S_RF_SPI_DMA_SEL To select between i2s and rf spi dma flow control signals [1:0] read-write SDIO_MULTI_FN_SSI_DMA_SEL To select between SSI master and sdio flow control signals [2:2] read-write SSI_MASTER_SELECT SSI Master select 1 SDIO_FLOW_CONTROL SDIO Multifunctional 0 UART2_I2S_DMA_SEL To select between I2S and UART2 flow control signals [3:3] read-write UART2_Flow_Control selects UART 2 flow control 0 I2S_Flow_Control selects I2S flow control 1 SIO_SSI_SLAVE2_DMA_SEL To select between sio and ssi slave 2 flow control signals [4:4] read-write SIO_Flow_Control selects SIO flow control 1 SSI2_SLAVE_FLOW_CONTROL Selects SSI2 slave flow control 0 SCT1_MVP_DMA_SEL To select between sct and mvp flow control signals [5:5] read-write SCT_Flow_Control Selects SCT flow control 0 MVP_Flow_Control Selects MVP flow control 1 QSPI_CRC_DMA_SEL To select between qspi and crc slave 2 flow control signals [6:6] read-write CRC_Flow_Control CRC 0 QSPI_Flow_Control Selects QSPI flow control 1 RESERVED Reserved [31:7] read-write Disabled CRC 0 Enabled QSPI(q2) 1 MCR_DMA2_TRAP_STATUS_64K0 MCU DMA2 trap status register for memory set 64K0 0xE4 32 read-only 0x00000000 GNT The grant signal for dma2 port of unified memory. [0:0] read-only WRITE_OR_READ_REQUEST 1=write request,0=read request [1:1] read-only MASTER_NUMBER The number of the master which requested the transaction. [5:2] read-only ADDRESS The address for which the read or write request came on dma2 port. [24:6] read-only MCR_MVP_PSRAM_TRAP_CLEAR MCU MVP PSRAM trap clear register 0xE0 32 read-write 0x00000000 MVP_TRAP_INTERRUPT_CLEAR Clears the interrupt for MVP trap [0:0] read-write PSRAM_TRAP_INTERRUPT_CLEAR Clears the interrupt for PSRAM trap [1:1] read-write RESERVED Reserved [31:2] read-only MCR_MVP_PSRAM_TRAP_STATUS MCU MVP PSRAM trap status register 0xDC 32 read-only 0x00000000 STATUS_MVP Tells the status of unauthorized access to MVP [0:0] read-only STATUS_PSRAM Tells the status of unauthorized access to PSRAM [1:1] read-only RESERVED Reserved [31:2] read-only MCR_DMA2_TRAP_STATUS_160K MCU DMA2 trap status register for memory set 160K 0xD8 32 read-only 0x00000000 GNT The grant signal for dma2 port of unified memory. [0:0] read-only WRITE_OR_READ_REQUEST 1=write request,0=read request [1:1] read-only MASTER_NUMBER The number of the master which requested the transaction. [5:2] read-only ADDRESS The address for which the read or write request came on dma2 port. [24:6] read-only MCR_DMA1_TRAP_STATUS_64K0 MCU DMA1 trap status register for memory set 64K0 0xD4 32 read-only 0x00000000 GNT The grant signal for dma1 port of unified memory. [0:0] read-only WRITE_READ 1=write request,0=read request [1:1] read-only MASTER_NUMBER The number of the master which requested the transaction. [5:2] read-only ADDRESS The address for which the read or write request came on dma1 port. [24:6] read-only MCR_DMA1_TRAP_STATUS_160K MCU DMA1 trap status register for memory set 160K 0xC8 32 read-only 0x00000000 GNT The grant signal for dma1 port of unified memory. [0:0] read-only WRITE_OR_READ_REQUEST 1=write request,0=read request [1:1] read-only MASTER_NUMBER The number of the master which requested the transaction. [5:2] read-only ADDRESS The address for which the read or write request came on dma1 port. [24:6] read-only MCR_DMA0_TRAP_STATUS_64K0 MCU DMA0 Trap Status Register for memory set 64K0 0xC4 32 read-only 0x00000000 GNT The grant signal for dma0 port of unified memory. [0:0] read-only WRITE_OR_READ_REQUEST 1=write request,0=read request [1:1] read-only MASTER_NUMBER The number of the master which requested the transaction. [5:2] read-only ADDRESS The address for which the read or write request came on dma0 port. [24:6] read-only MCR_DMA0_TRAP_STATUS_160K MCU DMA0 Trap Status Register for memory set 160K 0xB8 32 read-only 0x00000000 GNT The grant signal for dma0 port of unified memory. [0:0] read-only WRITE_OR_READ_REQUEST 1=write request, 0=read request [1:1] read-only MASTER_NUMBER The number of the master which requested the transaction. [5:2] read-only ADDRESS The address for which the read or write request came on dm port. [24:6] read-only MCR_DM_TRAP_STATUS_64K0 MCU DM trap status register for memory set 64K0 0xB4 32 read-only 0x00000000 GNT The grant signal for pm port of unified memory [0:0] read-only WRITE_OR_READ_REQUEST 1=write request, 0=read request [1:1] read-only MASTER_NUMBER The number of the master which requested the transaction. [5:2] read-only ADDRESS The address for which the read or write request came on dm port. [24:6] read-only MCR_DM_TRAP_STATUS_160K MCU DM trap status register for memory set 160K 0xA8 32 read-only 0x00000000 GNT The grant signal for pm port of unified memory [0:0] read-only WRITE_OR_READ 1=write request,0=read request [1:1] read-only MASTER_NUMBER The number of the master which requested the transaction. [5:2] read-only ADDRESS The address for which the read or write request came on dm port. [24:6] read-only MCR_ASYNC_TRAP_DETECTED_160K MCU Async trap detected register for memory set 160K 0xA4 32 read-write 0x00000000 Async_trap_detected_cortex if set indiacates trap has been detected by cortex,firmware should write this as 1 to clear it [0:0] read-write RESERVED Reserved [15:1] read-write MCR_AHB_MASTER_TRAP_ENABLE_REG_64K0 MCU AHB master trap enable register for memory set 64K0 0xA0 32 read-write 0x00000000 RESERVED Reserved [15:0] read-only TRAP_ENABLE_BITS_PER_MASTER_FOR_MEMORY_SET_64K0 '1' on a particular bit position indicates that access by that master to a trap enable bank will generate trap otherwise if it is '0' it won't generate a trap if it is accessing a trap enable bank. The masking is for UM1 transactions indicated in DMA_WR_TRAP_ENABLE_REG_64K0, DMA_WR_TRAP_ENABLE_REG_64K0 [31:16] read-write MCR_AHB_MASTER_TRAP_ENABLE_REG_160K MCU AHB master trap enable register for memory set 160K 0x9C 32 read-write 0x000000 TRAP_ENABLE_BITS_PER_MASTER_FOR_MEMORY_SET_160K '1' on a particular bit position indicates that access by that master to a trap enable bank will generate trap otherwise if it is '0' it won't generate a trap if it is accessing a trap enable bank. The masking is for UM1 transactions indicated in DMA_WR_TRAP_ENABLE_REG_160K , DMA_WR_TRAP_ENABLE_REG_160K . [15:0] read-only RESERVED Reserved [31:16] read-only MCR_DMA_RD_TRAP_ENABLE_REG_160K MCU DM read trap enable register for memory set 160K 0x98 32 read-write 0x00000000 ENABLE_BITS LSB corresponds to oth bank in the particular set. A '1' in any bit position indicates that if through that port that bank access , a trap will be generated [11:0] read-write RESERVED Reserved [31:12] read-write MCR_DMA_WR_TRAP_ENABLE_REG_160K MCU DM write trap enable register for memory set 160K 0x94 32 read-write 0x00000000 ENABLE_BITS LSB corresponds to oth bank in the particular set. A '1' in any bit position indicates that if through that port that bank access , a trap will be generated [11:0] read-write RESERVED Reserved [31:12] read-write MCR_DM_TRAP_ENABLE_REG_160K MCU DM trap enable register for memory set 160K 0x90 32 read-write 0x00000000 ENABLE_BITS LSB corresponds to 0th bank in the particular set. A '1' in any bit position indicates that if through that port that bank access , a trap will be generated [11:0] read-write RESERVED Reserved [31:12] read-write MCR_MEM_LS_ENABLE_REG MCU memory light sleep enable register 0x8C 32 read-write 0x00000000 MCU_MEM_LIGHTSLEEP_ENABLE Must set this bit to enable Light Sleep mode for any memory in MCU [0:0] read-write RESERVED Reserved [2:1] read-write GEN_SPI_MASTER_MEM_LIGHTSLEEP_ENABLE Must set this bit along with bit[0] of this register to make GSPI FIFO memories enter into light sleep [3:3] read-write RESERVED Reserved [31:4] read-only MCR_SOC_ICM_CTRL_REG MCU SOC ICM control register 0x7C 32 read-write 0x00000000 REMAP[0] When remap[0] == 1, the address space for rom will be reduced from 0x003F_FC00 to 0x003F_FFFF and qspi address space will add become 0x0800_0000 to 0x0BFF_FFFF and 0x0030_0000 to 0x003F_FBFF [0:0] read-write RESERVED Reserved [3:1] read-write REMAP_VALID Need to set If remap feature is required, along with remap[0]. [4:4] read-write RESERVED Reserved [4:4] read-write REMAP Internal logic signal for (remap_valid && remap[0]),This bit is going to AHB ICM input [12:12] read-only RESERVED Reserved [31:5] read-only MCR_SPARE_REG MCU M4SS spare register 0x74 32 read-write 0x00000000 RESERVED Reserved [15:0] read-write RESERVED Reserved [31:16] read-only MCR_ENABLE_TRAP MCU enable trap register 0x70 32 read-write 0x0000003C AHB_DUMMY_SLAVE AHB dummy slave is selected in cortex [0:0] read-only TRAP_ENABLE_REGISTER_CORTEX Enable the trap for cortex. [1:1] read-write RESERVED Reserved [5:2] read-write RESERVED Reserved [7:6] read-write APB_DUMMY_SLAVE_SELECTED When set, any of the master is trying to access the wrong peripheral address. [8:8] read-write AHB_ERROR_TRAP_ENABLE When set, ahb error trap is enabled [9:9] read-write RESERVED reserved [15:10] read-write MCR_RESET_TO_CORE_CNT MCU reset to core register 0x6C 32 read-write 0x00000001 RESET_TO_CORE_CNT This fields hold the reset active duration in number of clocks. [7:0] read-write RESET_TO_CORE_SEL 1: host/debugger reset will be synchronized to sleep clock and used 0: host/debugger reset will be synchronized to soc clock and used [8:8] read-write RESERVED Reserved [31:9] read-only MCR_I2S_LOOP_BACK_REG MCU I2S loopback enable register 0x68 32 read-write 0x00000000 RESERVED Reserved [7:0] read-write RESERVED Reserved [13:8] read-write I2S_LOOP_BACK_MODE Enables MCU I2S loop back mode [14:14] read-write RESERVED reserved [31:15] read-write MCR_AHB_ERROR_PER_MASTER_STATUS_REG Hardware sets bit in this register,Firmware resets bits in this register by writing zero 0x60 32 read-write 0x00000000 GPDMA_M1 Bit is set,When the GPDMA AHB master1 is getting error response. [0:0] read-write HIF Bit is set, When the HIF AHB master is getting error response. [1:1] read-write M4_I_PORT Bit is set, When the Cortex M4 I-port AHB master is getting error response. [2:2] read-write M4_D_PORT Bit is set,When the Cortex M4 D-port AHB master is getting error response. [3:3] read-write M4_S_PORT Bit is set, When the Cortex M4 S-port AHB master is getting error response. [4:4] read-write ICACHE Bit is set, When the MCU Icache AHB master is getting error response. [5:5] read-write UDMA Bit is set, When the uDMA AHB master is getting error response. [6:6] read-write RESERVED Reserved [7:7] read-write RESERVED Reserved [8:8] read-write RESERVED Reserved [9:9] read-write ULP_AHB_BRIDGE Bit is set, When the ULP AHB-AHB bridge master is getting error response. [10:10] read-write RESERVED Reserved [11:11] read-write RESERVED Reserved [12:12] read-write GPDMA_M2 Bit is set, When the GPDMA AHB master2 is getting error response. [13:13] read-write RESERVED Reserved [14:14] read-write NWP_AHB-AHB_MASTER Bit is set, When the NWP AHB-AHB bridge master is getting error response. [15:15] read-write RESERVED Reserved [31:16] read-write MCR_AHB_DUMMY_SLAVE_SELECTED_MASTER_REG Hardware sets bit in this register,Firmware resets bits in this register by writing zero 0x5C 32 read-write 0x00000000 GPDMA_M1 Bit is set When the GPDMA AHB master1 is trying to access the wrong slave address. [0:0] read-write HIF Bit is set,When the HIF AHB master is trying to access the wrong slave address. [1:1] read-write M4_I_PORT Bit is set,When the Cortex M4 I-port AHB master is trying to access the wrong slave address. [2:2] read-write M4_D_PORT Bit is set,When the Cortex M4 D-port AHB master is trying to access the wrong slave address. [3:3] read-write M4_S_PORT Bit is set,When the Cortex M4 S-port AHB master is trying to access the wrong slave address. [4:4] read-write ICACHE Bit is set,When the MCU Icache AHB master is trying to access the wrong slave address. [5:5] read-write UDMA Bit is set, When the uDMA AHB master is trying to access the wrong slave address [6:6] read-write RESERVED Reserved [7:7] read-write ULP_AHB_BRIDGE Bit is set, when ULP AHB is trying to access the wrong slave address. [8:8] read-write RPDMA_2 Bit is set,when RPDMA M2 is trying to access the wrong slave address. [9:9] read-write TASS_AHB-AHB_MASTER Bit is set, when TASS AHB is trying to access the wrong slave address. [10:10] read-write RESERVED Reserved [11:11] read-write RESERVED Reserved [12:12] read-write GPDMA_M2 Bit is set, When the GPDMA AHB master2 is trying to access the wrong slave address [13:13] read-write RESERVED Reserved [14:14] read-write NWP_AHB-AHB_MASTER Bit is set, When the NWP AHB-AHB bridge master is trying to access the wrong slave address. [15:15] read-write RESERVED Reserved [31:16] read-write MCR_PERIPHERAL_UDMA_DMA_SEL_REG MCU DMA peripheral selection register 0x58 32 read-write 0x00000000 USART1 When set, ack from udma will go to the uart1, else ack from GPDMA will go. [0:0] read-write NOT_SET ACK from udma will go to GPDMA 0 SET ACK from udma will go to UART1 1 UART2 When set, ack from udma will go to the uart2, else ack from GPDMA will go. [1:1] read-write NOT_SET ACK from udma will go to GPDMA 0 SET ACK from udma will go to UART2 1 RESERVED Reserved [3:2] read-write SSI_SLAVE When set, ack from udma will go to the SSI, else ack from GPDMA will go. [4:4] read-write NOT_SET ACK from udma will go to GPDMA 0 SET ACK from udma will go to SSI 1 SSI_MASTER When set, ack from udma will go to the SSI master, else ack from GPDMA will go. [5:5] read-write NOT_SET ACK from udma will go to GPDMA 0 SET ACK from udma will go to SSI Master 1 RESERVED Rserved [6:6] read-write I2C When set, ack from udma will go to the I2C, else ack from GPDMA will go. [7:7] read-write NOT_SET ACK from udma will go to GPDMA 0 SET ACK from udma will go to I2C 1 RESERVED reserved [31:8] read-write MCR_CHIP_VER_NO_REG MCU chip version ID register 0x54 32 read-only 0X00000000 VER_NO Indicates the revision number of the chip. [7:0] read-only RESERVED1 reserved1 [31:8] read-only MCR_CHIP_DEVICE_ID_REG MCU chip device ID register 0x50 32 read-only 0X00009117 DEVICE_ID It gives the device ID of the chip. Device ID is 9117. [15:0] read-only RESERVED1 reserved1 [31:16] read-only MCR_CM_STATUS_REG MCU cortex M4 status register 0x4C 32 read-only 0X00000000 CM_LOCKUP When high, indicates the Cortex M4 is in LOCKUP state [0:0] read-only SLEEPDEEP When high, indicates the Cortex M4 is in deep sleep state [1:1] read-only SLEEPING When high, indicates the Cortex M4 is in sleeping state [2:2] read-only RESERVED1 reserved1 [31:3] read-only MCR_CM_CTRL_REG MCU cortex M4 control register 0x48 32 read-write 0x00000000 CM_RESET Writing 1 both POR and non regions of M4 will be under reset,writing 0 both out of reset [0:0] read-write CM_RESET_POR Status of cm_reset_por can be seen on this bit. [1:1] read-only RESERVED reserved [31:2] read-write MCR_GENERIC_CTRL_1_REG MCU generic control register1 0x44 32 read-write 0x00000000 RESERVED reserved [3:0] read-write REGISTER_ROM_OUTPUT When set, the ready and read data from ROM will be registered. It should be asserted when MCU clock is greater than 100MHz. [4:4] read-write RESERVED Reserved [6:5] read-only PROVIDE_SOC_CLK_2x_TO_ICACHE_DRAM When set, twice the frequency of soc clk will be provided to icache dram,. When zero, normal soc_clk is given. [7:7] read-only RESERVED Reserved [13:8] read-only HOST_PADS_GPIO_MODE Control bit for 5 pins to use it either as host pin or gpio pin. Pins from 30 to 26 are controlled by these bits respectively. [18:14] read-write Disabled HOST mode 0 Enabled GPIO mode 1 RESERVED Reserved [19:19] read-write ICACHE_DRAM_POWER_SAVE_MODE When this bit is set, only half performance is valid with 1x clock.(Data two cycles after clock). Full performance is valid with 2x clock to icache dram [20:20] read-write ENABLE_ICACHE_SEQ_ACESS_PS_MODE When this bit is set, power save is enabled and a icache read that is sequential to the previous cache read of the same line is saved in local buffer and accessed [21:21] read-write RESERVED Reserved [22:22] read-only I2S_MASTER_SLAVE_MODE 0 – I2S/I2S PCM act as slave,1 I2S/I2S PCM act as master [23:23] read-only RESERVED reserved1 [31:24] read-write MCR_PCM_CTRL_CLEAR_REG MCU PCM interface control clear register 0x38 32 read-write 0X00000000 PCM_ENABLE_M Setting bit clears the pcm_enable_m. Writing '0' has no effect [0:0] read-write PCM_FSYNC_START_M Setting bit 1 clear the pcm_fsync_start. Writing '0' has no effect [1:1] read-write PCM_BIT_RES Setting the bits clear the pcm_bit_res. Writing '0' has no effect. [4:2] read-write RESERVED reserved [31:5] read-write MCR_PCM_CTRL_SET_REG MCU PCM interface control set register 0x34 32 read-write 0X00000000 PCM_ENABLE_M Enable/disable PCM mode of I2S interface. When PCM is enabled,I2S is disabled and vice versa [0:0] read-write READ_0 PCM mode is disabled and I2S mode is enabled. This programming is in addition to the other GPIO level programming to enable I2S mode. 0 READ_1 PCM mode is enabled and I2S mode is disabled. This programming is valid only when the GPIO signals are programmed for I2S mode. 1 WRITE_0 has no effect on this register. 0 WRITE_1 Writing a '1' to any of the bits sets the corresponding bit in the soft register 1 PCM_FSYNC_START_M This bit has to be programmed according to when the MS bit of the PCM data is driven w.r.t. the fsync signal of PCM. [1:1] read-write READ_0 The MS bit of data is driven one clock cycle after fsync goes high. 0 READ_1 The MS bit of data is driven in the same clock cycle as fsync going high. 1 WRITE_0 has no effect on this register. 0 WRITE_1 Writing a '1' to any of the bits sets the corresponding bit in the soft register 1 PCM_BIT_RES The bit-resolution of the data on PCM. 3'b000 - 8-bit 3'b001 - 12-bit 3'b010 - 16-bit, 3'b011 - 24-bit 3'b1xx - 32-bit [4:2] read-write RESERVED1 reserved1 [31:5] read-write MCR_SW_SCRATCHPAD_CLEAR_REG MCU software scratch pad clear register 0x30 32 read-write 0x00000000 SOFTWARE_SCRATCHPAD_CLEAR This register is used by software for storing information. It does not affect anything in the hardware. [31:0] read-write Writing_1 to any of the bits clears the corresponding bit in the soft register. 1 Writing_0 has no effect on this register. 0 MCR_SW_SCRATCHPAD_SET_REG MCU software scratch pad set register 0x2C 32 read-write 0x00000000 SOFTWARE_SCRATCHPAD_SET This register is used by software for storing information. It does not affect anything in the hardware. [31:0] read-write Writing_1 To any of the bits sets the corresponding bit in the soft register. 1 Writing_0 has no effect on this register. 0 MCR_XTAL_ON_CTRL_REG MCU Crystal Control register 0x28 32 read-write 0X00000092 40MNZ_XTAL_ON_FW_SEL This bit determines the source of 40MHz CRYSTAL ON indication. [0:0] read-write Enabled CRYSTAL ON is controlled by firmware through BIT(3) of this register. 1 Disabled CRYSTAL ON is controlled by the sleep state machine and the XTAL_ON_IN coming to the chip. It is asserted whenever there is an indication from either of the clients. 0 RESERVED Reserved [2:1] read-write 40MNZ_XTAL_ON_FW This bit drives the 40MHz crystal ON indication. This bit is considered only if the firmware based driving is enabled using BIT(0) of this register [3:3] read-write Crystal_On_Set crystal ON is set 1 Crystal_On_Reset crystal ON is reset 0 RESERVED reserved [31:4] read-only MCR_SDIO_STATE_REG MCU SDIO status register 0x24 32 read-write 0x00000000 SDIO_STATE_LOWER Lower 16-bits of the SDIO state that is to be loaded into the SDIO block. [15:0] read-write SDIO_STATE_UPPER Upper 16-bits of the SDIO state that is to be loaded into the SDIO block. [31:16] read-write MCR_SDIO_STATE_CTRL_REG MCU SDIO state control register 0x20 32 write-only 0x00000000 LATCH_SDIO_STATE When this bit is set, hardware latches the SDIO state into MCR_SDIO_STATE register. This is done by firmware while going to sleep. It is used for ULP Mode State Retention. [0:0] write-only LOAD_SDIO_STATE When this bit is set, hardware loads the value in MCR_SDIO_STATE register to SDIO block. The state to be restored has to be loaded to MCR_SDIO_STATE register before setting this. This is done by firmware after coming out of sleep. It is used for ULP Mode State Retention. [1:1] write-only RESERVED reserved [31:2] read-only MCR_GENERIC_CTRL_REG MCU generic control register 0x14 32 read-write 0x00000100 Reserved reserved [5:0] read-write AHB_Invalid_Access_Trap_Enable When this bit is set, trap will be generated to processor in the case an invalid access is done on AHB. [6:6] read-write Reserved Reserved [7:7] read-write I2S_SSI_GPIO_Mode_Sel When set, GPIO 11,12,13 & 14 are used for SSI in GPIO mode 2.Else I2S [8:8] read-write For_SSI GPIO 11,12,13,14 are used for SSI when configured in GPIO mode 2. 1 For_I2S GPIO 11,12,13,14 are used for I2S when configured in GPIO mode 2. 0 HSPI_SSI_Sel Selects if Host spi interface pins are intended for SSI slave else Host SPI [9:9] read-write For_SSI_Slave Host SPI pins used for SSI slave. Host SPI inactive. 1 For_Host_SPI Host SPI active 0 Reserved Reserved [13:10] read-write JTAG_Daisy_Chain_EN This bit has to be set to enable daisy chaining in JTAG [14:14] read-write Reserved Reserved [31:15] read-only MCR_AHB_BRIDGE_CTRL_REG AHB bridge Control Register 0x18 32 read-write 0x00000000 Reserved reserved [3:0] read-write Bypass_Registering_For_AHB_Bridge When this bit is set, bypass the AHB bus registering in AHB bridge, which is present in between MCU and NWP subsystems. It should be asserted when MCU clock is less than 100MHz [4:4] read-write Reserved Reserved [31:5] read-only SYSRTC 1.0 SYSRTC Register structure SYSRTC 0x24048C00 32 read-write 0x00 0x7c registers SYSRTC_IPVERSION Shows SYSRTC IPVERSION 0x00 32 read-only 0x00000001 IP_VERSION IP Version [31:0] read-only SYSRTC_EN SYSRTC Enable and disabling status 0x04 32 read-write ENABLE SYSRTC Enable, Enable the SYSRTC by requesting Clock [0:0] read-write DISABLING Disablement busy status. Set when EN cleared and cleared when the peripheral core reset is finished [1:1] read-only Reserved reserved [31:2] read-write SYSRTC_SWRST SYSRTC software reset 0x08 32 read-write SWRST Software reset command [0:0] write-only RESETTING Software reset busy status [1:1] read-only Reserved reserved [31:2] read-write SYSRTC_CFG SYSRTC configuration register 0x0C 32 read-write DEBUG_RUN Debug Mode run Enable [0:0] read-write Reserved reserved [31:1] read-write SYSRTC_CMD SYSRTC start or stop command register 0x010 32 write-only START Start SYSRTC [0:0] write-only STOP Stop SYSRTC [1:1] write-only Reserved reserved [31:2] write-only SYSRTC_STATUS SYSRTC lock or running status register 0x014 32 read-only RUNNING SYSRTC running status [0:0] read-only LOCK_STATUS Lock status [1:1] read-only Reserved reserved [31:2] read-only SYSRTC_CNT SYSRTC counter value register 0x018 32 read-write CNT Counter value [31:0] read-write SYSRTC_SYNCBUSY SYSRTC sync busy register 0x01C 32 read-only START Sync busy for START bitfield [0:0] read-only STOP Sync busy for STOP bitfield [1:1] read-only CNT Sync busy for CNT bitfield [2:2] read-only Reserved reserved [31:3] read-only SYSRTC_LOCK SYSRTC lock key configuration register 0x020 32 write-only LOCK_KEY Configuration Lock Key [15:0] write-only Reserved reserved [31:16] write-only SYSRTC_GRP0_IF SYSRTC Group 0 interrupt flag register 0x040 32 read-write OVFI_IF Overflow Interrupt Flag [0:0] read-write CMP_0_IF Compare 0 Interrupt Flag [1:1] read-write CMP_1_IF Compare 1 Interrupt Flag [2:2] read-write CAP_0_IF Capture 0 Interrupt Flag [3:3] read-write Reserved reserved [31:4] read-write SYSRTC_GRP0_IEN SYSRTC Group 0 interrupt enable register 0x044 32 read-write OVFI_EN Overflow Interrupt Enable [0:0] read-write CMP_0_EN Compare 0 Interrupt Enable [1:1] read-write CMP_1_EN Compare 1 Interrupt Enable [2:2] read-write CAP_0_EN Capture 0 Interrupt Enable [3:3] read-write Reserved reserved [31:4] read-write SYSRTC_GRP0_CTRL SYSRTC Group 0 control register 0x048 32 read-write CMP_0_EN Compare 0 Enable [0:0] read-write CMP_1_EN Compare 1 Enable [1:1] read-write CAP_0_EN Capture 0 Enable [2:2] read-write CMP_0_CM_OA Compare 0 Compare Match Output Action [5:3] read-write CMP_1_CM_OA Compare 1 Compare Match Output Action [8:6] read-write CAP_0_EDGE Capture 0 Edge Select [10:9] read-write Reserved reserved [31:11] read-write SYSRTC_GRP0_CMP0VALUE SYSRTC group 0 compare 0 value Register 0x04C 32 read-write CMP_0_VALUE Compare 0 Value [31:0] read-write SYSRTC_GRP0_CMP1VALUE SYSRTC group 0 compare 1 value Register 0x050 32 read-write CMP_1_VALUE Compare 1 Value [31:0] read-write SYSRTC_GRP0_CAP0VALUE SYSRTC group 0 capture 0 value Register 0x054 32 read-only CAP_0_VALUE Capture 0 Value [31:0] read-only SYSRTC_GRP0_SYNCBUSY SYSRTC group 0 sync busy status register 0x058 32 read-only CTRL Sync busy for CTRL register [0:0] read-only CMP_0_VALUE Sync busy for CMP 0 VALUE register [1:1] read-only CMP_1_VALUE Sync busy for CMP 1 VALUE register [2:2] read-only Reserved reserved [31:3] read-only SYSRTC_GRP1_IF SYSRTC Group 1 interrupt flag register 0x060 32 read-write OVF_IF Overflow Interrupt Flag [0:0] read-write CMP_0_IF Compare 0 Interrupt Flag [1:1] read-write CMP_1_IF Compare 1 Interrupt Flag [2:2] read-write CAP_0_IF Capture 0 Interrupt Flag [3:3] read-write ALTOVF_IF Alternate Overflow Interrupt Flag [4:4] read-write ALTCMP_0_IF Alternate Compare 0 interrupt Flag [5:5] read-write ALTCMP_1_IF Alternate Compare 1 interrupt Flag [6:6] read-write ALTCAP_0_IF Alternate Capture 0 interrupt Flag [7:7] read-write Reserved reserved [31:8] read-write SYSRTC_GRP1_IE SYSRTC Group 1 interrupt flag enable register 0x064 32 read-write OVF_IE Overflow Interrupt Enable [0:0] read-write CMP_0_IE Compare 0 Interrupt Enable [1:1] read-write CMP_1_IE Compare 1 Interrupt Enable [2:2] read-write CAP_0_IE Capture 0 Interrupt Enable [3:3] read-write ALTOVF_IE Alternate Overflow Interrupt Enable [4:4] read-write ALTCMP_0_IE Alternate Compare 0 interrupt Enable [5:5] read-write ALTCMP_1_IE Alternate Compare 1 interrupt Enable [6:6] read-write ALTCAP_0_IE Alternate Capture 0 interrupt Enable [7:7] read-write Reserved reserved [31:8] read-write SYSRTC_GRP1_CTRL SYSRTC Group 1 control register 0x068 32 read-write CMP_0_EN Compare 0 Enable [0:0] read-write CMP_1_EN Compare 1 Enable [1:1] read-write CAP_0_EN Capture 0 Enable [2:2] read-write CMP_0_CM_OA Compare 0 Compare Match Output Action [5:3] read-write CMP_1_CM_OA Compare 1 Compare Match Output Action [8:6] read-write CAP_0_EDGE Capture 0 Edge Select [10:9] read-write Reserved reserved [31:11] read-write SYSRTC_GRP1_CMP0VALUE SYSRTC group 1 compare 0 value Register 0x06C 32 read-write CMP_0_VALUE Compare 0 Value [31:0] read-write SYSRTC_GRP1_CMP1VALUE SYSRTC group 1 compare 1 value Register 0x070 32 read-write CMP_1_VALUE Compare 1 Value [31:0] read-write SYSRTC_GRP1_CAP0VALUE SYSRTC group 1 capture 0 value Register 0x074 32 read-only CAP_0_VALUE Capture 0 Value [31:0] read-only SYSRTC_GRP1_SYNCBUSY SYSRTC group 0 sync busy status register 0x078 32 read-only CTRL Sync busy for CTRL register [0:0] read-only CMP_0_VALUE Sync busy for CMP 0 VALUE register [1:1] read-only CMP_1_VALUE Sync busy for CMP 1 VALUE register [2:2] read-only Reserved reserved [31:3] read-only MCUSYSRTC_REG1 Input/Output Register 0x3FC 32 read-write PRS_SELECT Selects whether PRS is from GPIO or register bits [0:0] read-write PRS_IN Input to SYSRTC module [2:1] write-only PRS_OUT Output from SYSRTC module [6:3] read-only Reserved Reserved [31:7] read-only MVP 1.0 Matrix Vector Processor Register structure MVP 0x24000000 32 read-write 0x00 0x210 registers MVP_IPVERSION MVP IPVERSION register 0x00 32 read-only 0x00000002 IP_VERSION IP Version [31:0] read-only MVP_EN Block enable register 0x04 32 read-write 0x0 ENABLE Enable [0:0] read-write DISABLING Disablement Busy Status [1:1] read-only Reserved reserved [31:2] read-write MVP_SWRST software reset register 0x08 32 read-write 0x0 SWRST Software reset command [0:0] write-only RESETTING Software reset busy status [1:1] read-only Reserved reserved [31:2] read-write MVP_CFG configuration register 0x0C 32 read-write 0x0 PERFCNTEN Performance counter enable [0:0] read-write OUTCOMPRESSDIS ALU Output stream compression disable [1:1] read-write INCACHEDIS ALU Input word cache disable [2:2] read-write LOOPERRHALTDIS Loop Error Halt disable [3:3] read-write INFENCEDIS Fence Disable [5:4] read-write Reserved Reserved [15:6] read-write PERF0CNTSEL Performence counter select [19:16] read-write PERF1CNTSEL Performence counter select [23:20] read-write Reserved reserved [31:24] read-write MVP_STATUS Status register 0x10 32 read-write 0x00000004 RUNNING Running Status [0:0] read-only PAUSED Paused Status [1:1] read-only IDLE Idle Status [2:2] read-only Reserved reserved [31:3] read-write MVP_PERF0CNT Run counter 0x14 32 read-only 0x00000000 COUNT Performance counter [23:0] read-only Reserved reserved [31:24] read-only MVP_PERF1CNT Run counter 0x18 32 read-only 0x00000000 COUNT Performance counter [23:0] read-only Reserved reserved [31:24] read-only MVP_IF Interrupt flags 0x1C 32 read-write 0x00000000 PROGDONREIF Programme done interrupt flag [0:0] read-write LOOP0DONEIF Loop done interrupt flag [1:1] read-write LOOP1DONEIF Loop done interrupt flag [2:2] read-write LOOP2DONEIF Loop done interrupt flag [3:3] read-write LOOP3DONEIF Loop done interrupt flag [4:4] read-write LOOP4DONEIF Loop done interrupt flag [5:5] read-write LOOP5DONEIF Loop done interrupt flag [6:6] read-write LOOP6DONEIF Loop done interrupt flag [7:7] read-write LOOP7DONEIF Loop done interrupt flag [8:8] read-write Reserved Reserved [9:9] read-write ALUNANIF Not A number interrupt flag [10:10] read-write R0POSREALIF R0 Non Zero interrupt flag [11:11] read-write ALUOFIF ALU Overflow on result [12:12] read-write ALUUFIF ALU Underflow on result [13:13] read-write STORECONVERTOFIF Overflow during array store Conversion [14:14] read-write STORECONVERTUFIF Underflow during array store conversion [15:15] read-write STORECONVERTINFIF Infinity encounterd during array store conversion [16:16] read-write STORECONVERTNANFIF NaN encountered during array store conversion [17:17] read-write PERFCNT0IF Run count overflow interrupt flag [18:18] read-write PERFCNT1IF Stall count overflow interrupt flag [19:19] read-write Reserved Reserved [23:20] read-write LOOPFAULTIF Loop Fault interrupt flag [24:24] read-write BUSERRFAULTIF Bus error fault interrupt flag [25:25] read-write BUSALIGNFAULTIF Bus error fault interrupt flag [26:26] read-write ALUFAULTIF ALU Fault fault interrupt flag [27:27] read-write ARRAYFAULTIF Array fault interrupt flag [28:28] read-write Reserved reserved [31:29] read-write MVP_IEN Interrupt Enable 0x20 32 read-write 0x00000000 PROGDONREIE Programme done interrupt enable [0:0] read-write LOOP0DONEIE Loop done interrupt enable [1:1] read-write LOOP1DONEIE Loop done interrupt enable [2:2] read-write LOOP2DONEIE Loop done interrupt enable [3:3] read-write LOOP3DONEIE Loop done interrupt enable [4:4] read-write LOOP4DONEIE Loop done interrupt enable [5:5] read-write LOOP5DONEIE Loop done interrupt enable [6:6] read-write LOOP6DONEIE Loop done interrupt enable [7:7] read-write LOOP7DONEIE Loop done interrupt enable [8:8] read-write Reserved Reserved [9:9] read-write ALUNANIE Not a Number interrupt enable [10:10] read-write R0POSREALIF R0 Non Zero Interrupt enable [11:11] read-write ALUOFIE ALU Overflow Interrupt enable [12:12] read-write ALUUFIE ALU Underflow Interrupt enable [13:13] read-write STORECONVERTOFIE store Conversion overflow interrupt enable [14:14] read-write STORECONVERTUFIE store conversion Underflow interrupt enable [15:15] read-write STORECONVERTINFIE store conversion Infinity interrupt enable [16:16] read-write STORECONVERTNANFIE NaN encountered during array store conversion [17:17] read-write PERFCNT0IE Run count overflow interrupt enable [18:18] read-write PERFCNT1IE Stall count overflow interrupt enable [19:19] read-write Reserved Reserved [23:20] read-write LOOPFAULTIE Loop Fault interrupt enable [24:24] read-write BUSERRFAULTIE Bus error fault interrupt enable [25:25] read-write BUSALIGNFAULTIE Bus error fault interrupt enable [26:26] read-write ALUFAULTIE ALU Fault fault interrupt flag [27:27] read-write ARRAYFAULTIE Array fault interrupt enable [28:28] read-write Reserved reserved [31:29] read-write MVP_FAULTSTATUS Fault status register 0x24 32 read-only 0x00000000 FAULTPC PC when fault occured [2:0] read-only Reserved Reserved [7:3] read-only FAULTARRAY Array access that generated a fault [10:8] read-only Reserved Reserved [11:11] read-only FAULTBUS Bus when fault occured [13:12] read-only Reserved Reserved [15:14] read-only FAULTLOOP Loop fault indicator [19:16] read-only Reserved reserved [31:20] read-only MVP_FAULTADDR Fault Address register 0x28 32 read-only 0x00000000 FAULTADDR Bus Fault Address Register [31:0] read-only MVP_PROGRAMSTATE Program state register 0x2C 32 read-write 0x00000000 PC Programme Counter [2:0] read-write Reserved Reserved [31:3] read-write 5 0x4 MVP_ARRAYnINDEXSTATE Array N Index State Registers 0x30 MVP_ARRAY_n_INDEXSTATE Array _n_ index state register 0x00 32 read-write 0x0 0x0 DIM0INDEX Current Index [9:0] read-write DIM1INDEX Current Index [19:10] read-write DIM2INDEX Current Index [29:20] read-write RESERVED1 reserved1 [31:30] read-write 8 0x4 MVP_LOOPnSTATE Loop N State Registers 0x44 MVP_LOOP_n_STATE Loop _n_ state register 0x00 32 read-write 0x0 0x0 CNT Loop Counter [9:0] read-write Reserved Reserved [11:10] read-write ACTIVE Loop Active [12:12] read-write Reserevd Reserved [15:13] read-write PCBEGIN Loop Start [18:16] read-write RESERVED1 reserved1 [31:19] read-write 8 0x4 MVP_ALUnREGSTATE ALU N Registers State 0x64 MVP_ALU_n_REGSTATE ALU _n_ register State 0x00 32 read-write 0x0 0x0 FREAL Float Real value [15:0] read-write FIMAG Float Imaginary value [31:16] read-write 5 0x10 MVP_ARRAYnDIMCFG Array N base address and dimension config Registers 0x84 MVP_ARRAY_n_ADDRCFG Array _n_ base address register 0x00 32 read-write 0x0 0x0 BASE Array Base Address [31:0] read-write MVP_ARRAY_n_DIM0CFG Array _n_ Dimension 0 configuration register 0x04 32 read-write 0x00002000 SIZE Array Dimesion Size [9:0] read-write Reserevd Reserved [11:10] read-write BASETYPE Element Type [13:12] read-write COMPLEX Complex Data Type [14:14] read-write Reserved Reserevd [15:15] read-write STRIDE Dimension stride step [27:16] read-write Reserved Reserved [31:28] read-write MVP_ARRAY_n_DIM1CFG Array _n_ Dimension 1 configuration register 0x08 32 read-write 0x00000000 SIZE Array Dimesion Size [9:0] read-write Reserevd Reserved [15:10] read-write STRIDE Dimension stride step [27:16] read-write Reserved Reserved [31:28] read-write MVP_ARRAY_n_DIM2CFG Array _n_ Dimension 2 configuration register 0x0C 32 read-write 0x00000000 SIZE Array Dimesion Size [9:0] read-write Reserevd Reserved [15:10] read-write STRIDE Dimension stride step [27:16] read-write Reserved Reserved [31:28] read-write 8 0x8 MVP_LOOPnCFG_RST loop N config and reset registers 0xD4 MVP_LOOP_n_CFG Loop _n_ configuration register 0x00 32 read-write 0x0 0x0 NUMITERS Number of Iterations [9:0] read-write Reserved Reserved [11:10] read-write ARRAY0INCRDIM0 Increment Dimesion 0 [12:12] read-write ARRAY0INCRDIM1 Increment Dimesion 1 [13:13] read-write ARRAY0INCRDIM2 Increment Dimesion 2 [14:14] read-write Reserved Reserved [15:15] read-write ARRAY1INCRDIM0 Increment dimension 0 [16:16] read-write ARRAY1INCRDIM1 Increment dimension 1 [17:17] read-write ARRAY1INCRDIM2 Increment dimension 2 [18:18] read-write Reserved Reserved [19:19] read-write ARRAY2INCRDIM0 Increment dimension 0 [20:20] read-write ARRAY2INCRDIM1 Increment dimension 1 [21:21] read-write ARRAY2INCRDIM2 Increment dimension 2 [22:22] read-write Reserved Reserved [23:23] read-write ARRAY3INCRDIM0 Increment dimension 0 [24:24] read-write ARRAY3INCRDIM1 Increment dimension 1 [25:25] read-write ARRAY3INCRDIM2 Increment dimension 2 [26:26] read-write Reserevd Reserved [27:27] read-write ARRAY4INCRDIM0 Increment dimension 0 [28:28] read-write ARRAY4INCRDIM1 Increment dimension 1 [29:29] read-write ARRAY4INCRDIM2 Increment dimension 2 [30:30] read-write Reserved Reserved [31:31] read-write MVP_LOOP_n_RST Loop _n_ reset configuration register 0x04 32 read-write 0x0 0x0 Reserved Reserved [11:0] read-write ARRAY0RESETDIM0 Reset Dimesion 0 [12:12] read-write ARRAY0RESETDIM1 Reset Dimesion 1 [13:13] read-write ARRAY0RESETDIM2 Reset Dimesion 2 [14:14] read-write Reserved Reserved [15:15] read-write ARRAY1RESETDIM0 Reset dimension 0 [16:16] read-write ARRAY1RESETDIM1 Reset dimension 1 [17:17] read-write ARRAY1RESETDIM2 Reset dimension 2 [18:18] read-write Reserved Reserved [19:19] read-write ARRAY2RESETDIM0 Reset dimension 0 [20:20] read-write ARRAY2RESETDIM1 Reset dimension 1 [21:21] read-write ARRAY2RESETDIM2 Reset dimension 2 [22:22] read-write Reserved Reserved [23:23] read-write ARRAY3RESETDIM0 Reset dimension 0 [24:24] read-write ARRAY3RESETDIM1 Reset dimension 1 [25:25] read-write ARRAY3RESETDIM2 Reset dimension 2 [26:26] read-write Reserevd Reserved [27:27] read-write ARRAY4RESETDIM0 Reset dimension 0 [28:28] read-write ARRAY4RESETDIM1 Reset dimension 1 [29:29] read-write ARRAY4RESETDIM2 Reset dimension 2 [30:30] read-write Reserved Reserved [31:31] read-write 8 0xC MVP_INSTRnCFG Instruction n word 0, 1 ,2, 0x114 MVP_INSTR_n_CFG0 Instruction _n_ word 0 0x00 32 read-write 0x0 0x0 ALUIN0REGID Register Id [2:0] read-write Reserved Reserved [3:3] read-write ALUIN0REALZERO Real Zero [4:4] read-write ALUIN0REALNEGATE Real Negate [5:5] read-write ALUINOIMAGZERO Imaginary Not Zero [6:6] read-write ALUINOIMAGNEGATE Imaginary Negate [7:7] read-write ALUIN1REGID Register ID [10:8] read-write Reserved Reserved [11:11] read-write ALUIN1REALZERO Real Zero [12:12] read-write ALUIN1REALNEGATE Real Negate [13:13] read-write ALUIN1IMAGZERO Imaginary Not Zero [14:14] read-write ALUIN1IMAGNEGATE Imaginary Negate [15:15] read-write ALUIN2REGID Register ID [18:16] read-write Reserved Reserved [19:19] read-write ALUIN2REALZERO Real Zero [20:20] read-write ALUIN2REALNEGATE Real Negate [21:21] read-write ALUIN2IMAGZERO Imaginary Not Zero [22:22] read-write ALUIN2IMAGNEGATE Imaginary Negate [23:23] read-write Reserved Reserved [27:24] read-write ALUOUTREGID Regsiter ID [30:28] read-write Reserved Reserved [31:31] read-write MVP_INSTR_n_CFG1 Instruction _n_ word 1 0x04 32 read-write 0x0 0x0 ISTREAM0REGID Register Id [2:0] read-write ISTREAM0LOAD Load Register [3:3] read-write ISTREAM0ARRAYID Array ID [6:4] read-write ISTREAM0ARRAYINCRDIM0 Increament Array Dimension 0 [7:7] read-write ISTREAM0ARRAYINCRDIM1 Increament Array Dimension 1 [8:8] read-write ISTREAM0ARRAYINCRDIM2 Increament Array Dimension 2 [9:9] read-write ISTREAM1REGID Register ID [12:10] read-write ISTREAM1LOAD Load Register [13:13] read-write ISTREAM1ARRAYID Array ID [16:14] read-write ISTREAM1ARRAYINCRDIM0 Increament Array Dimension 0 [17:17] read-write ISTREAM1ARRAYINCRDIM1 Increament Array Dimension 1 [18:18] read-write ISTREAM1ARRAYINCRDIM2 Increament Array Dimension 2 [19:19] read-write OSTREAMREGID Register ID [22:20] read-write OSTREAMSTORE Store to Register [23:23] read-write OSTREAMARRAYID Array ID [26:24] read-write OSTREAMARRAYINCRDIM0 Increament Array Dimension 0 [27:27] read-write OSTREAMARRAYINCRDIM1 Increament Array Dimension 1 [28:28] read-write OSTREAMARRAYINCRDIM2 Increament Array Dimension 2 [29:29] read-write Reserved Reserved [31:30] read-write MVP_INSTR_n_CFG2 Instruction _n_ word 2 0x08 32 read-write 0x0 0x0 LOOP0BEGIN Loop Begin [0:0] read-write LOOP0END Loop End [1:1] read-write LOOP1BEGIN Loop Begin [2:2] read-write LOOP1END Loop End [3:3] read-write LOOP2BEGIN Loop Begin [4:4] read-write LOOP2END Loop End [5:5] read-write LOOP3BEGIN Loop Begin [6:6] read-write LOOP3END Loop End [7:7] read-write LOOP4BEGIN Loop Begin [8:8] read-write LOOP4END Loop End [9:9] read-write LOOP5BEGIN Loop Begin [10:10] read-write LOOP5END Loop End [11:11] read-write LOOP6BEGIN Loop Begin [12:12] read-write LOOP6END Loop End [13:13] read-write LOOP7BEGIN Loop Begin [14:14] read-write LOOP7END Loop End [15:15] read-write Reserved Reserved [19:16] read-write ALUOP ALU OPcode [28:20] read-write Reserved Reserved [30:29] read-write ENDPROG Reserved [31:31] read-write MVP_CMD Command Register 0x174 32 write-only 0x00000000 START Start Command [0:0] write-only HALT Halt Command [1:1] write-only STEP Step Command [2:2] write-only INIT Initialization Command/Qualifier [3:3] write-only Reserved Reserved [31:4] write-only MVP_DEBUGGEN Debug control register 0x200 32 read-write 0x00000000 Reserevd Reserevd [0:0] read-write BKPTLOOP0DONE Enable Breakpoint on loop Done [1:1] read-write BKPTLOOP1DONE Enable Breakpoint on loop Done [2:2] read-write BKPTLOOP2DONE Enable Breakpoint on loop Done [3:3] read-write BKPTLOOP3DONE Enable Breakpoint on loop Done [4:4] read-write BKPTLOOP4DONE Enable Breakpoint on loop Done [5:5] read-write BKPTLOOP5DONE Enable Breakpoint on loop Done [6:6] read-write BKPTLOOP6DONE Enable Breakpoint on loop Done [7:7] read-write BKPTLOOP7DONE Enable Breakpoint on loop Done [8:8] read-write Reserved Reserved [9:9] read-write BKPTALUNAN Enable break point on ALUNAN [10:10] read-write BKPTR0POSREAL Enable breakpoint on R0POSREL [11:11] read-write BKPTALUOF Enable breakpoint on ALUOF [12:12] read-write BKPTALUUF Enable breakpoint on ALUUF [13:13] read-write BKPTSTORECONVERTOF Enable breakpoint on STORECONVERTOF [14:14] read-write BKPTSTORECONVERTUF Enable breakpoint on STORECONVERTUF [15:15] read-write BKPTSTORECONVERTINF Enable breakpoint on STORECONVERTINF [16:16] read-write BKPTSTORECONVERTNAN Enable breakpoint on STORECONVERTNAN [17:17] read-write Reserved Reserved [27:18] read-write DEBUGSTEPCNTEN Debug step count enable [28:28] read-write DEBUGBKPTALLEN Trigger Breakpoint when ALL conditions match [29:29] read-write DEBUGBKPTANYEN Trigger Breakpoint when ANY conditions match [30:30] read-write Reserved Reserved [31:31] read-write MVP_DEBUGSTEPCNT Debug control register 0x204 32 read-write 0x00000000 DEBUGSTEPCNT Debug Step Counter [23:0] read-write Reserved Reserved [31:24] read-write MVP_LOAD0ADDR Cuurent load 0 address 0x208 32 read-only 0x00000000 ADDR Array Address [31:0] read-only MVP_LOAD1ADDR Cuurent load 1 address 0x20C 32 read-only 0x00000000 ADDR Array Address [31:0] read-only MVP_STOREADDR Cuurent store address 0x210 32 read-only 0x00000000 ADDR Array Address [31:0] read-only MVP_INTR 62 MVP_WAKEUP_INTR 63 SDC 1.0 Sensor Data Collector Register structure SDC 0x24042400 32 read-write 0x00 0x78 registers SDC_GEN_CONFIG_0 SDC general configuration 0 0x00 32 read-write 0x00000000 INTR_STATUS_CLEAR Writing 1 clears interrupt, reading gives SDC Interrupt status [0:0] read-write Reserved Reserevd [31:1] read-write SDC_GEN_CONFIG_1 SDC general configuration 1 0x04 32 read-write 0x00000000 RST_WRT_PTR Writing 1 will resets the write pointer so that new samples can be filled in Buffer. [0:0] read-write WRT_PTR Write pointer Value [4:1] read-only SAMP_THRESH Number of data sampled to be collected from Aux-ADC and stored in Buffer before interrupt is raised/wakeup is initialed [8:5] read-write Reserved Reserevd [31:9] read-write SDC_GEN_CONFIG_2 SDC general configuration 2 0x08 32 read-write 0x00000000 SDC_SAMP_EN SDC Data Sampling mode [0:0] read-write Enable Enable 1 Disable Disable 0 NUM_CH_SEL Number of Channels to be used [3:1] read-write Reserved Reserevd [31:4] read-write SDC_GEN_CONFIG_3 SDC general configuration 3 0x12 32 read-write 0x00000000 SAMP_TRIG_SEL select the trigger event on which AUX-ADC Data is sampled [0:0] read-write Enable Enable 1 Disable Disable 0 CNT_TRIG_EVNT which trigger event AUX-ADC Data will sampled [10:1] read-write Enable Enable 1 Disable Disable 0 SDC_CLK_DIV SDCSS clock division factor [20:11] read-write Reserved Reserevd [31:21] read-write SDC_AUXADC_CONFIG_1 SDC AUX ADC configuration 1 0x18 32 read-write 0x00000000 SDC_AUXADC_INPUT_P_SEL_CH1 AUXADC's Positive Input Mux Select for Channel-1 [4:0] read-write SDC_AUXADC_INPUT_N_SEL_CH1 AUXADC's Negative Input Mux Select for Channel-1 [8:5] read-write SDC_AUXADC_DIFF_MODE_CH1 Enable Differential Mode in AUX ADC for Channel -1 [9:9] read-write SDC_AUXADC_EN AUXADC Enable from SDC Block [10:10] read-write SDC_ADC_CONFIG_EN On Enabling this register, SDC ADC Configuration will be Applied. [11:11] read-write Reserved Reserevd [31:12] read-write SDC_AUXDAC_CONFIG_1 SDC AUX DAC configuration 1 0x1C 32 read-write 0x00000000 SDC_DAC_EN Enable signal DAC [0:0] read-write SDC_DAC_OUT_MUX_EN Enable signal for Connecting DAC Output to GPIO [1:1] read-write SDC_DAC_OUT_MUX_SEL Programming register for choosing GPIO in which DAC Output is connected [2:2] read-write Reserved Reserved [3:3] read-write SDC_DAC_DATA SDC Aux DAC Data [13:4] read-write SDC_DAC_CONFIG_EN On Enabling this register, SDC DAC Configuration will be Applied. [14:14] read-write Reserved Reserevd [31:15] read-write SDC_AUXLDO_CONFIG SDC AUX LDO configuration 0x20 32 read-write 0x00000000 SDC_AUXLDO_VOLT_CTRL SDC AUX LDO Voltage Control Selection [3:0] read-write SDC_AUXLDO_BYP_EB Configure AUXLDO in Buypass mode.When Enabled, Ouput supply of LDO will be same as Input supply. [5:5] read-write SDC_AUXLDO_EN Turn-On AUX LDO [6:6] read-write SDC_AUXLDO_CONFIG_EN SDC Aux LDO Configuration Control Enable [7:7] read-write Reserved Reserevd [31:8] read-write SDC_AUXOPAMP_CONFIG_1 SDC AUX OPAMP configuration 1 0x24 32 read-write 0x00000000 SDC_OPAMP_EN_CH1 Enable signal for turning OPAMP to used for Channel-1 Operation [0:0] read-write SDC_OPAMP_LP_MODE Configuration of OPAMP1 Operation mode [1:1] read-write SDC_OPAMP_R1_SEL Configuration for Resistor Ladder R1 of OPAMP1 for controlling it gain. [3:2] read-write SDC_OPAMP_R2_SEL Configuration for Resistor Ladder R2 of OPAMP1 for controlling it gain. [6:4] read-write SDC_OPAMP_RES_BACK_EN Configuration register for controlling Resistor Bank of OPAMP [7:7] read-write SDC_OPAMP_RES_MUX_SEL Configuration register for Connecting R1 Resistor Ladder input [10:8] read-write SDC_OPAMP_RES_TO_OUT_VDD Configuration register for Connecting R2 Resistor Ladder input [11:11] read-write SDC_OPAMP_OUT_MUX_EN Configur this register to OPAMP1 Output will be connected to GPIO [12:12] read-write SDC_OPAMP_IN_N_SEL Configuration register for selecting N Input of OPAMP1. [15:13] read-write SDC_OPAMP_IN_P_SEL_CH1 Configuration register for selecting P Input of OPAMP1.,for CH1 [19:16] read-write SDC_OPAMP_OUT_MUX_SEL Configuration register for connecting OPAMP1 output to GPIO [20:20] read-write Reserved Reserved [21:21] read-only SDC_VREF_MUX_1_EN Connect Low Drive Strength voltage reference for ULP GPIO 1 For external use [22:22] read-write SDC_VREF_MUX_2_EN Connect Low Drive Strength voltage reference for ULP GPIO 3 For external use [23:23] read-write SDC_VREF_MUX_3_EN Connect Low Drive Strength voltage reference for ULP GPIO 4 For external use [24:24] read-write SDC_VREF_MUX_4_EN Connect Low Drive Strength voltage reference for ULP GPIO 15 For external use [25:25] read-write SDC_VREF_MUX_1_SEL Selection register for choosing Voltage reference to external use on ULP_GPIO_1 [27:27] read-write SDC_VREF_MUX_2_SEL Selection register for choosing Voltage reference to external use on ULP_GPIO_3 [28:28] read-write SDC_VREF_MUX_3_SEL Selection register for choosing Voltage reference to external use on ULP_GPIO_4 [29:29] read-write SDC_VREF_MUX_4_SEL Selection register for choosing Voltage reference to external use on ULP_GPIO_15 [30:30] read-write SDC_OPAMP_CONFIG_EN On Enabling this register, SDC OPAMP Configuration will be Applied. [31:31] read-write SDC_AUXADC_CONFIG_2 SDC AUX ADC configuration 2 0x28 32 read-write 0x00000000 SDC_AUXADC_INPUT_P_SEL_CH2 AUXADC's Positive Input Mux Select for Channel-2 [4:0] read-write SDC_AUXADC_INPUT_N_SEL_CH2 AUXADC's Negative Input Mux Select for Channel-2 [8:5] read-write SDC_AUXADC_DIFF_MODE_CH2 1-AUX ADC Differencial mode, 0 - Single Ended Mode [9:9] read-write Reserved Reserevd [31:10] read-write SDC_AUXADC_CONFIG_3 SDC AUX ADC configuration 3 0x2C 32 read-write 0x00000000 SDC_AUXADC_INPUT_P_SEL_CH3 AUXADC's Positive Input Mux Select for Channel-3 [4:0] read-write SDC_AUXADC_INPUT_N_SEL_CH3 AUXADC's Negative Input Mux Select for Channel-3 [8:5] read-write SDC_AUXADC_DIFF_MODE_CH3 1-AUX ADC Differencial mode, 0 - Single Ended Mode [9:9] read-write Reserved Reserved [31:10] read-write SDC_AUXADC_CONFIG_4 SDC AUX ADC configuration 4 0x30 32 read-write 0x00000000 SDC_AUXADC_INPUT_P_SEL_CH4 AUXADC's Positive Input Mux Select for Channel-4 [4:0] read-write SDC_AUXADC_INPUT_N_SEL_CH4 AUXADC's Negative Input Mux Select for Channel-4 [8:5] read-write SDC_AUXADC_DIFF_MODE_CH4 1-AUX ADC Differencial mode, 0 - Single Ended Mode [9:9] read-write Reserved Reserved [31:10] read-write SDC_AUXOPAMP_CONFIG_2 SDC AUX OPAMP Configuration 2 0x34 32 read-write 0x00000000 SDC_OPAMP_EN_CH2 Enable signal for turning OPAMP to used for Channel-2 Operation [0:0] read-write SDC_OPAMP_IN_P_SEL_CH2 Configuration register for selecting P Input of OPAMP1 for Channel-2 [4:1] read-write SDC_OPAMP_EN_CH3 Enable signal for turning OPAMP to used for Channel-4 Operation [5:5] read-write SDC_OPAMP_IN_P_SEL_CH3 Configuration register for selecting P Input of OPAMP1 for Channel-3 [9:6] read-write SDC_OPAMP_EN_CH4 Enable signal for turning OPAMP to used for Channel-4 Operation [10:10] read-write SDC_OPAMP_IN_P_SEL_CH4 Configuration register for selecting P Input of OPAMP1 for Channel-4 [11:11] read-write Reserved Reserved [31:15] read-write 16 0x4 SDC_DATA_REGn SDC Data registers (0-15) 0x38 SDC_DATA_REG_n_ SDC Data register _n_ 0x00 32 read-only 0x00000000 0x00000000 SDC_DATA_SAMPLE__n_ Sample 0 collected from Sensor through Aux ADC. [11:0] read-only SMP_ID_CH__n_ Channel iD for sample _n_ [13:12] read-only RESERVED1 reserved1 [31:16] read-only PAD_SELECTION 1.0 PAD selection register PAD_SELECTION 0x41300000 32 read-write 0x00 0x16 registers MEM_GPIO_ACCESS_CTRL_SET Indicates the PAD Configuration Control for GPIO_25-GPIO_30. 0x00 32 read-write 0x00000020 Reserved Reserved [4:0] read-write SZP_MCUHP_GPIO_CTRL2 Write 1 enables SZP to configure GPIO_25 TO GPIO_30 [5:5] read-write ENABLE_SZP_CONFIG_GPIO_25_TO_30 Writing 1 to this ensables SZP to configure the GPIO_25 to GPIO_30 1 No_Effect No Effect 0 Reserved Reserved [31:6] read-write MEM_GPIO_ACCESS_CTRL_CLEAR Indicates the PAD Configuration Control for GPIO_25-GPIO_30. 0x04 32 read-write 0x00000020 Reserved Reserved [4:0] read-write SZP_MCUHP_GPIO_CTRL2 Write 1 enables MCUHP to configure GPIO_25 TO GPIO_30 [5:5] read-write ENABLE_MCUHP_CONFIG_GPIO_25_TO_30 Writing 1 to this ensables SZP to configure the GPIO_25 to GPIO_30 1 No_Effect No Effect 0 Reserved Reserved [31:6] read-write MCUHP_PAD_SELECTION Indicates the PAD Configuration Control for GPIO_0 to GPIO_57 pads except for GPIO_25-GPIO_30. 0x610 32 read-write 0x00000000 SZP_MCUHP_GPIO_CTRL1_0_to_21 PAD Configuration Controls between NWP and MCU HP. [21:0] read-write WRITE_1 Writing 1 to a particular bit enables the MCU HP to configure the corresponding PADs 1 WRITE_0 Writing 0 to a particular bit enables the SZP/NWP to configure the corresponding PADs 0 Reserved Reserved,It is recommended to write these bits to 0. [31:21] read-write MCUHP_PAD_SELECTION_1 Indicates the PAD Configuration Control for ULP_GPIO_0 to ULP_GPIO_11 pads when used as SoC GPIO function for SoC_GPIO_64 to SoC_GPIO_75 0x618 32 read-write 0x00000000 SZP_MCUHP_GPIO_CTRL1_22_to_33 PAD Configuration Controls between NWP and MCU HP. [11:0] read-write WRITE_1 Writing 1 to a particular bit enables the MCU HP to configure the corresponding PADs 1 WRITE_0 Writing 0 to a particular bit enables the SZP/NWP to configure the corresponding PADs 0 Reserved Reserved,It is recommended to write these bits to 0. [31:12] read-write PAD_CONFIGURATIONs 1.0 PAD Configuration registers PAD_CONFIGURATION 0x46006000 32 read-write 0x00 0x16 registers 64 0x4 MCU_HP_GPIO_PAD_CONFIGs PAD Configuration Register for GPIO_n; n = 0,1,2, ..... 63 0x0 PAD_CONFIG_REG__n_ PAD Configuration for _n_ 0x00 32 read-write 0x00000008 0x00000008 PADCONFIG_E1 E[2,1] – Drive strength selector, 0-2 mA / 1-4 mA / 2-8 mA / 3-12 ma [0:0] read-write PADCONFIG_E2 E[2,1] – Drive strength selector, 0-2 mA / 1-4 mA / 2-8 mA / 3-12 ma [1:1] read-write PADCONFIG_POS Power-on-Start enable; [2:2] read-write PADCONFIG_SMT Active high Schmitt trigger (Hysteresis) select; SMT=0 – No hysteres [3:3] read-write PADCONFIG_REN Active high receiver enable [4:4] read-write PADCONFIG_SR Slew Rate Control [5:5] read-write PADCONFIG_P1 P[2,1]–Driver disabled state control,0-Hi-Z/1-Pull-up/2-Pull-down/3-Repeater [6:6] read-write PADCONFIG_P2 P[2,1]–Driver disabled state control,0-Hi-Z/1-Pull-up/2-Pull-down/3-Repeater [7:7] read-write RESERVED1 reserved1 [31:8] read-write Secure_Storage 1.0 Secure storage Secure_Storage 0x24048500 32 read-write 0x00 0x24 registers 8 0x4 MCU_STORAGE_REGn MCU storage registers (0-7) 0x0 MCU_STORAGE_REG_n_ MCU STorage register _n_ 0x00 32 read-write 0x00000000 0x00000000 MCU_STORAGE_WORD__n_ This register Can be used to storing 32bits of Data. [31:0] read-write MCU_STORAGE_WRITE_KEY Programming the key will enable or disable access to program MCU storage register 0x200 32 read-write 0x00000000 0x00000000 MCU_STORAGE_KEY By default the Access to MCU storage Register is enabled [31:0] read-write HF_PLL_Clocks 1.0 High frequency PLL clocks registers Clock_Architecture 0x46180000 32 read-write 0x00 0x38 registers PLL_REF_CLK_CONFIG_REG Reference Clock Configuration Register 0x004 32 read-write 0x00000000 0x00000000 Reserved Reserved [13:0] read-write REF_CLK_SEL Specified the input reference clock for the PLL's [15:14] read-write Reserved Reserved [31:16] read-write PLL_LDO_CONFIG_REG LDO Configuration Register 0x008 32 read-write 0x00009200 Reserved Reserved [6:0] read-write I2SPLL_LDO_PROG Specified the configuration of I2S-PLL LDO output voltage [9:7] read-write INTFPLL_LDO_PROG Specified the configuration of Interface-PLL LDO output voltage [12:10] read-write SOCPLL_LDO_PROG Specified the configuration of SoC-PLL LDO output voltage [15:13] read-write Reserved Reserved [31:16] read-write SOCPLL_CONFIG_REG1 SoC-PLL Configuration Register1 0x040 32 read-write 0x00002CC9 SOCPLL_RANGE_SEL Specifies the range for the Output frequency. [1:0] read-write Reserved Reserved,It is recommended to write these bits to 0. [2:2] read-write SOCPLL_CLK_EN Writing 1 enables SOC-PLL output clock ,0 disables it [3:3] read-write SOCPLL_PD Writing 1 disables power to SOC-PLL,1 enables it [4:4] read-write Reserved Reserved [5:5] read-write SOCPLL_M Specifies the SoC-PLL Multiplication Factor. [15:6] read-write Reserved Reserved,It is recommended to write these bits to 0. [31:16] read-write SOCPLL_CONFIG_REG2 SoC-PLL Configuration Register2 0x044 32 read-write 0x00000138 Reserved Reserved,It is recommended to write these bits to 0. [2:0] read-write SOCPLL_N Specifies the SoC-PLL Input Division Factor [8:3] read-write SOCPLL_P Specifies the SoC-PLL Output Division Factor [15:9] read-write Reserved Reserved [31:16] read-write SOCPLL_CONFIG_REG3 SoC-PLL Configuration Register3 0x048 32 read-write 0x00000000 Reserved Reserved,It is recommended to write these bits to 0. [1:0] read-write SOCPLL_FCW Specifies the SoC-PLL Fractional Frequency Control Word [15:2] read-write Reserved Reserved,It is recommended to write these bits to 0. [31:16] read-write SOCPLL_STATUS_REG SoC-PLL Status Register 0x070 32 read-only 0x00000000 Reserved Reserved [14:0] read-only SOCPLL_LOCK Indicates the SoC-PLL Status 1 locked, 0 notlocked [15:15] read-only Reserved Reserved [31:16] read-only INTFPLL_CONFIG_REG1 INTF-PLL Configuration Register1 0x080 32 read-write 0x00002CC9 INTFPLL_RANGE_SEL Specifies the range for the Output frequency. [1:0] read-write Reserved Reserved,It is recommended to write these bits to 0. [2:2] read-write INTFPLL_CLK_EN Writing 1 enables SOC-PLL output clock ,0 disables it [3:3] read-write INTFPLL_PD Writing 1 disables power to INTF-PLL,1 enables it [4:4] read-write Reserved Reserved [5:5] read-write INTFPLL_M Specifies the INTF-PLL Multiplication Factor. [15:6] read-write Reserved Reserved,It is recommended to write these bits to 0. [31:16] read-write INTFPLL_CONFIG_REG2 INTF-PLL Configuration Register2 0x084 32 read-write 0x00000138 Reserved Reserved,It is recommended to write these bits to 0. [2:0] read-write INTFPLL_N Specifies the INTF-PLL Input Division Factor [8:3] read-write INTFPLL_P Specifies the SoC-PLL Output Division Factor [15:9] read-write Reserved Reserved [31:16] read-write INTFPLL_CONFIG_REG3 INTF-PLL Configuration Register3 0x088 32 read-write 0x00000000 Reserved Reserved,It is recommended to write these bits to 0. [1:0] read-write INTFPLL_FCW Specifies the INTF-PLL Fractional Frequency Control Word [15:2] read-write Reserved Reserved,It is recommended to write these bits to 0. [31:16] read-write INTFPLL_STATUS_REG INTF-PLL Status Register 0x0A0 32 read-only 0x00000000 Reserved Reserved [14:0] read-write INTFPLL_LOCK Indicates the INTF-PLL Status 1 locked, 0 notlocked [15:15] read-only Reserved Reserved [31:16] read-write I2SPLL_CONFIG_REG1 I2S-PLL Configuration Register1 0x0C0 32 read-write 0x00001244 Reserved Reserved,It is recommended to write these bits to 0. [1:0] read-write I2SPLL_CLK_EN Writing 1 enables I2S-PLL output clock ,0 disables it [2:2] read-write Reserved Reserved,It is recommended to write these bits to 0. [3:3] read-write I2SPLL_PD Writing 1 disables power to I2S-PLL,1 enables it [4:4] read-write Reserved Reserved,It is recommended to write these bits to 0. [5:5] read-write INTFPLL_M Specifies the I2S-PLL Multiplication Factor. [15:6] read-write Reserved Reserved [31:16] read-write I2SPLL_CONFIG_REG2 I2S-PLL Configuration Register2 0x0C4 32 read-write 0x00005850 Reserved Reserved,It is recommended to write these bits to 0. [0:0] read-write I2SPLL_N Specifies the I2S-PLL Input Division Factor [7:1] read-write I2SPLL_P2 Specifies the I2S-PLL Output Division Factor [10:8] read-write I2SPLL_P1 Specifies the I2S-PLL Output Division Factor [15:11] read-write Reserved Reserved [31:16] read-write I2SPLL_CONFIG_REG3 I2S-PLL Configuration Register3 0x0C8 32 read-write 0x0000BA60 Reserved Reserved,It is recommended to write these bits to 0. [1:0] read-write I2SPLL_FCW Specifies the I2SF-PLL Fractional Frequency Control Word [15:2] read-write Reserved Reserved,It is recommended to write these bits to 0. [31:16] read-write I2SPLL_STATUS_REG I2S-PLL Status Register 0x0F0 32 read-only 0x00000000 Reserved Reserved [14:0] read-write I2SPLL_LOCK Indicates the I2S-PLL Status 1 locked, 0 notlocked [15:15] read-only Reserved Reserved [31:16] read-write Instruction_Cache_Controller 1.0 The Instruction Cache Controller controls the instruction fetching from External Memory into Local Cache for access to the processor. Instruction_cache_controller 0x20280000 32 read-write 0x00 0x48 registers RAM_CTRL_REG Rams control register 0x04 32 read-write 0x00000000 0x00000000 Rams_Ownership_of_Second_set This bit controls the ownership of second set of rams when number of ways is 4 and 32k memory is enabled. [0:0] read-write Reserved Reserved [31:1] read-write ICACHE_CTRL_REG Icache control register 0x14 32 read-write 0x00000000 0x00000000 icache_enable Tells if an icache is enables or not for ICC 'n' [0:0] read-write ICache_Enabled Icache is enabled and cache access can take place via ICC ‘n’ 1 Ichache_Not_Enabled Icache is not enabled for icc ‘n’ 0 bypass_cache Tells where fectch requests are served through,valid only when ichache is enable [1:1] read-write via_ahb Fetch Requests are served via ahb, bypassing the cache rams 1 Through_Icache_Rams Fetch Requests are served through icache rams 0 mode32_128bit_line selects 128bit or 32 bit for AHB requests, valid only when Cache is disable [2:2] read-write 32_Bit 32 bit mode is enabled for icc ‘n’. AHB requests will be 32 bit 1 128_Bit 128 bit mode enabled for icc ‘n’. AHB requests will be 128 bit 0 icache_ahb_wrap_mode Enables or disables wrap mode [3:3] read-write Wrap_Enabled wrap mode is enabled for icc ‘n’ 1 Wrap_Disabled wrap mode is disabled for icc ‘n’. 0 icache_line_buf_invalid Selects wheter line buffer is valid or invalid [4:4] read-write Invalid line buffer invalid for icc ‘n’ 1 Valid line buffer valid for icc ‘n’ 0 lru_8ways Selects whether 8 ways logic is disabled or enabled in controller [5:5] read-write Disabled 8 ways logic is disabled in controller 0 Enabled 8 ways logic is enabled in controller 1 mode_256bit_line selects 1 or 2 128 bit buffer lines used [6:6] read-write One_128bit_Line One 128 bit line buffer is used. Four beat AHB transaction is initiated with the external memory 0 Two_128bit_Line Two 128 bit line buffers are used. Eight beat AHB transaction is initiated with the external memory 1 disable_fetch_256bit_lb When set, disables fetching from line buffer which is present in 256-bit mode prefetch module [7:7] read-write Reserved Reserved [30:8] read-only 15 0x4 ADDR_TRANSLATE_SEGn_CTRL_REG Address Translate Value Segment Registers (1-15) 0x24 ADDR_TRANSLATE_SEG_n1__CTRL_REG Address Translate Value Segment Register__n1_ 0x00 32 read-write 0x00000000 0x00000000 Reserved Reserved [20:0] read-only Segment_Address_Value Segment address value register [31:21] read-write Data_Cache_Controller 1.0 Data Cache controller register map Data_cache_controller 0x44040000 32 read-write 0x00 0x108 registers HWPARAMS Specifies Implementation options of the AHB Cache 0x00 32 read-only ENDIANNESS Endianness of the module,0 - LE, 1 - BE8 , 2 - BE32 [1:0] read-only XOM XOM Support ,1 - On, 2 - Off [2:2] read-only XOM_SUPPORT_ON XOM Support is on 1 XOM_SUPPORT_OFF XOM Support is off 0 SNAPSHOTTING SNAPSHOTTING Support ,1 - On, 2 - Off [3:3] read-only SNAPSHOTTING_SUPPORT_ON SNAPSHOTTING Support is on 1 SNAPSHOTTING_SUPPORT_OFF SNAPSHOTTING Support is off 0 RESERVED RESERVED [7:4] read-only CACHE_MEM_SIZE Cache memory size in address bits.the actual size is 2 power of this value [15:8] read-only MASTER_ID The Cachegenerates transactions with this ID [23:16] read-only DIS_CACHE_EN_MAINT Value of the input configuration port that controls the function to turn off cache enable automatic maintenance. [24:24] read-only DIS_CACHE_DIS_MAINT Value of the input configuration port that controls the function to turn off cache disable automatic maintenance. [25:25] read-only DIS_CACHE_DOWN_MAINT Value of the input configuration port that controls the function to turn off powerdown maintenance. [26:26] read-only POWER_ON_ENABLE Value of the input configuration port that controls the function that enables the cache automatically after powerup. [27:27] read-only RESERVED1 RESERVED1 [29:28] read-only APB_VIOLATION_RESP Respond with error (1) or RAZ/WI (0) to illegal APB operations. [30:30] read-only AHB_VIOLATION_RESP Respond with error (1) or RAZ/WI (0) to illegal AHB operations on XOM. Fixed to 0 if the XOM render parameter is OFF. [31:31] read-only CTRL Control register cache on/off 0x010 32 read-write 0x00000000 ENABLE Request to enable or disable cache 1- enable , 0 - disable [0:0] read-write Enable Enable 1 Disable Disable 0 FORCE_WT Forces write through policy [1:1] read-write RESERVED_0 Reserved [7:2] read-write DENY_POWERDOWN When set, power down LPI requests are denied. Does not affect clock LPI requests. [8:8] read-write RESERVED_1 RESERVED [15:9] read-write ALLOW_NSEC_ENABLE_READ Allow Non-secure software to see if the cache is enabled. [16:16] read-write ALLOW_NSEC_MAINT_LINES Allow Non-secure software to trigger maintenance (only for lines and only Non-secure views of cache lines). [17:17] read-write ALLOW_NSEC_NSECSTAT Allow Non-secure software to read and control Non-secure statistics counter registers and receive saturation interrupt. [18:18] read-write RESERVED_2 Reserved [31:19] read-write NSEC_ACCESS Non-secure access information register : Non-secure software can check its access level 0x014 32 read-only 0x00000000 CACHE_ENABLED Shows if the cache is enabled or disabled [0:0] read-only Enable Enable 1 Disable Disable 0 RESEREVED_0 Reserved [15:1] read-only NSEC_ENABLE_READ_ALLOWED Non-secure software is allowed to see the cache enabled state. [16:16] read-only NSEC_MAINT_LINES_ALLOWED Non-secure software is allowed to trigger maintenance (only for lines). [17:17] read-only NSEC_NSECSTAT_ALLOWED Non-secure software is allowed to read and control Non-secure statistics counters and receives saturation interrupt. [18:18] read-only RESEREVED_1 Reserved [31:19] read-only MAINT_CTRL_ALL Maintenance control for the entire cache register :For maintenance operations 0x020 32 write-only 0x00000000 TRIG_CLEAN_ALL Trigger clean all maintenance. This can be used together with TRIG_INVALIDATE_ALL. [0:0] write-only TRIG_INVALIDATE_ALL Trigger invalidate all maintenance. It can be used together with TRIG_CLEAN_ALL. TRIG_INVALIDATE_ALL can be used even if the cache is not enabled, but only if used without clean. [1:1] write-only RESERVED_0 Reserved [31:2] write-only MAINT_CTRL_LINES Maintenance control for individual lines register:maintenance operations for a specific address 0x024 32 write-only 0x00000000 TRIG_CLEAN Trigger clean by address on the addressed cache line. [0:0] write-only TRIG_INVALIDATE Trigger invalidate by address on the addressed cache line. It can be used together with TRIG_CLEAN. [1:1] write-only SECURITY Cache maintenance is performed on the Secure or Non-secure view of the address [2:2] write-only SECURE Secure 1 Non_Secure Non secure 0 Reserved Reserevd [4:3] write-only ADDR Address to look up in the cache and perform invalidate or cleaning on matching cache line. Use bits [31:5] of the address. [31:5] write-only MAINT_STATUS Maintenance status for the cache register:Indicates if any maintenance is already in progress 0x028 32 read-only 0x00000000 CACHE_ENABLED Cache enable status [0:0] read-only ENABLED Enable 1 DISABLE Disable 0 ONGOING_EN_DIS Ongoing enable or disable, reading 1 means cache is in progress of being enable or disable [1:1] read-only ONGOING_MAINT Reading 1 means that a cache maintenance operation is in progress (clean, invalidate, or cache enable or cache disable). [2:2] read-only ONGOING_PWR_MAINT Reading 1 means low-power request automatic maintenance is in progress. [3:3] read-only RESEREVD_0 Reserved [7:4] read-only CACHE_IS_CLEAN Reading 1 means that the cache has no dirty data. The AHB Cache uses a simplified model to check for dirty data. [8:8] read-only RESERVED_1 Reserved [31:9] read-only SECIRQSTAT Secure interrupt request status register :source of a Secure interrupt 0x100 32 read-only 0x00000000 ENABLE_DONE The enable operation is complete. The AHB Cache is operational. [0:0] read-only DISABLE_DONE The disable operation is complete. The AHB Cache is bypassed. [1:1] read-only MAINT_DONE Manual maintenance operation (either or both of clean or invalidate) started by Secure software finished. [2:2] read-only MAINT_IGNORED Secure software attempted maintenance or enable or disable of the cache. One of those operations was already in progress and the new request was ignored. [3:3] read-only TR_ERR Secure transaction error on master side (any bus error, data type access to XOM) [4:4] read-only SECURE_CNT_SAT Secure statistics counters are saturated and stopped. [5:5] read-only NSECURE_CNT_SAT Non-secure statistics counters are saturated and stopped (when ALLOW_NSEC_NSECSTAT is not set). [6:6] read-only XOM_ERR A data, write, locked, or exclusive access was attempted to an XOM by a Secure transfer. [7:7] read-only RESERVED_0 Reserved [31:8] read-only SECIRQSCLR Secure interrupt status clear register:clears sources for Secure interrupt. 0x104 32 write-only 0x00000000 ENABLE_DONE Clear ENABLE_DONE interrupt [0:0] write-only DISABLE_DONE clear DISABLE_DONE interrupt [1:1] write-only MAINT_DONE Clear secure MAINT_DONE interrupt [2:2] write-only MAINT_IGNORED clear MAINT_IGNORED interrupt [3:3] write-only TR_ERR clear TR_ERR interrupt [4:4] write-only SECURE_CNT_SAT clear SECURE_CNT_SAT [5:5] write-only NSECURE_CNT_SAT clear NSECURE_CNT_SAT interrupt [6:6] write-only XOM_ERR clear XOM_ERR interrupt [7:7] write-only RESERVED_0 Reserved [31:8] write-only SECIRQEN Secure interrupt Enable register :enable sources for Secure interrupt. 0x108 32 read-write 0x00000000 ENABLE_DONE enable ENABLE_DONE interrupt [0:0] read-write DISABLE_DONE enable DISABLE_DONE interrupt [1:1] read-write MAINT_DONE Enable secure MAINT_DONE interrupt [2:2] read-write MAINT_IGNORED enable MAINT_IGNORED interrupt [3:3] read-write TR_ERR enable TR_ERR interrupt [4:4] read-write SECURE_CNT_SAT enable SECURE_CNT_SAT [5:5] read-write NSECURE_CNT_SAT enable NSECURE_CNT_SAT interrupt [6:6] read-write XOM_ERR enable XOM_ERR interrupt [7:7] read-write RESERVED_0 Reserved [31:8] read-write SECIRQINFO1 Secure transfer error information register 1:shows the address of the operation when Secure TR_ERR interrupt occurred 0x10C 32 read-only 0x00000000 ADDR Address used by the Secure transfer that caused the Secure TR_ERR [31:0] read-only SECIRQINFO2 Secure transfer error information register 2:contains the master ID of the operation when Secure TR_ERR interrupt occurred 0x110 32 read-only 0x00000000 MASTER The HMASTER ID of the Secure transfer that caused the error. [7:0] read-only ERROR_SRC Origin of the Secure transfer that received the bus error: [9:8] read-only RESERVED_0 Reserved [31:10] read-only NSECIRQSTAT Non-secure interrupt request status register:source of a Non-secure interrupt 0x140 32 read-only 0x00000000 RESERVED_0 Reserved [1:0] read-only MAINT_DONE Manual maintenance operations (either or both of clean or invalidate) started by Non- secure software have finished. [2:2] read-only MAINT_IGNORED Non-secure software attempted maintenance or enabling or disabling of the cache while such an operation was already in progress and the new request was ignored. [3:3] read-only TR_ERR Non-secure transaction error on master side. The details of the transaction are saved in the NSECIRQINFOx registers. [4:4] read-only RESERVED_1 Reserved [5:5] read-only NSECURE_CNT_SAT Non-secure statistics counters are saturated and stopped (when ALLOW_NSEC_NSECSTAT is not set). [6:6] read-only XOM_ERR A data, write, locked, or exclusive access was attempted to an XOM by a Non-secure transfer [7:7] read-only RESERVED_2 Reserved [31:8] read-only NSECIRQCLR Non-secure interrupt status clear register:clear sources for Non-secure interrupt. 0x144 32 write-only 0x00000000 RESERVED_0 Reserved [1:0] write-only MAINT_DONE Clear non secure MAINT_DONE interrupt [2:2] write-only MAINT_IGNORED clear non secure MAINT_IGNORED interrupt [3:3] write-only TR_ERR clear non secure TR_ERR interrupt [4:4] write-only RESERVED_1 Reserved [5:5] write-only NSECURE_CNT_SAT clear NSECURE_CNT_SAT interrupt [6:6] write-only XOM_ERR clear non secure XOM_ERR interrupt [7:7] write-only RESERVED_2 Reserved [31:8] write-only NSECIRQEN Non-secure interrupt enable register:enable sources for Non-secure interrupt 0x148 32 read-write 0x00000000 RESERVED_0 Reserved [1:0] read-write MAINT_DONE Enable non secure MAINT_DONE interrupt [2:2] read-write MAINT_IGNORED Enable non secure MAINT_IGNORED interrupt [3:3] read-write TR_ERR enable non secure TR_ERR interrupt [4:4] read-write RESERVED_1 Reserved [5:5] read-write NSECURE_CNT_SAT enable NSECURE_CNT_SAT interrupt [6:6] read-write XOM_ERR enable non secure XOM_ERR interrupt [7:7] read-write RESERVED_2 Reserved [31:8] read-write NSECIRQINFO1 Non-secure transfer error information register 1:address of the operation when Non-secure TR_ERR interrupt occurred 0x14C 32 read-only 0x00000000 ADDR Address used by the Non-secure transfer that caused Non-secure TR_ERR. [31:0] read-only NSECIRQINFO2 Non-secure transfer error information register 2:master ID of the operation when Non-secure TR_ERR interrupt occurred 0x150 32 read-only 0x00000000 MASTER The HMASTER ID of the Non-secure transfer that caused the error. [7:0] read-only ERROR_SRC The origin of the Non-secure transfer that received the bus error. 0 = Early write response [9:8] read-only RESERVED_0 Reserved [31:10] read-only SECHIT Secure transfers hit register:displays the value of the Secure hit counter 0x300 32 read-only 0x00000000 SECHITCNT The number of Secure transfers that have hit the cache. [31:0] read-only SECMISS Secure transfers miss register:displays the value of the Secure miss counter 0x304 32 read-only 0x00000000 SECMISSCNT The number of Secure transfers that have missed the cache. [31:0] read-only SECSTATCTRL Secure transfers statistic counters control:provides control over the Secure counters. 0x308 32 read-write 0x00000000 ENABLE Enable statistics counters for Secure transactions [0:0] read-write RESET Reset statistics counters for Secure transactions. [1:1] read-write RESERVED_0 Reserved [31:2] read-write NSECHIT Non-secure transfers hit register:displays the value of the Non-secure hit counter 0x310 32 read-only 0x00000000 NSECHITCNT The number of Non-secure transfers that have hit the cache. [31:0] read-only NSECMISS Non-secure transfers miss register:displays the value of the Non-secure miss counter. 0x314 32 read-only 0x00000000 NSECMISSCNT The number of Non-secure transfers that have missed the cache. [31:0] read-only NSECSTATCTRL Non-secure transfers statistic counters control register:provides control over the Non-secure counters 0x318 32 read-write 0x00000000 ENABLE Enable statistics counters for Non-secure transactions. [0:0] read-write RESET Reset statistics counters for Non-secure transactions [1:1] read-write RESERVED_0 Reserved [31:2] read-write PMSVR0 saved value register 0 - Secure hit:Secure hit counter snapshot register 0x600 32 read-only 0x00000000 SCHS Secure hit counter snapshot [31:0] read-only PMSVR1 saved value register 1 - Secure miss:Secure miss counter snapshot register 0x604 32 read-only 0x00000000 SMCS Secure miss counter snapshot [31:0] read-only PMSVR2 saved value register 2 - non Secure hit:non Secure hit counter snapshot register 0x608 32 read-only 0x00000000 NSHCS Non secure hit counter snapshot [31:0] read-only PMSVR3 saved value register 3 - non Secure miss:non Secure miss counter snapshot register 0x60C 32 read-only 0x00000000 NSMCS Non secure miss counter snapshot [31:0] read-only PMSSR PMU snapshot status register 0x680 32 read-only 0x00000001 NC No capture. Indicates whether the PMU counters have been captured. [0:0] read-only RESERVED_0 Reserved [31:1] read-only PMSCR PMU snapshot capture register 0x6F0 32 write-only 0x00000000 SS Provides a mechanism for software to initiate a snapshot. [0:0] write-only RESERVED_0 Reserved [31:1] write-only PMSSRR PMU snapshot reset register 0x6F4 32 read-write 0x00000000 RP_SHC Reset Secure hit counter when making snapshot. The miss counter copies this value. [0:0] read-write RP_SMC Reset Secure miss counter when making snapshot. Mirrors RP_SHC as the two counters are grouped and should not be reset separately. [1:1] read-only RP_NSHC Reset Non-secure hit counter when making snapshot. The miss counter copies this value. [2:2] read-write RP_NSMC Reset Non-secure miss counter when making snapshot. Mirrors RP_NSHC as the two counters are grouped and should not be reset separately. [3:3] read-only RESERVED_0 Reserved [31:4] read-write PIDR4 Peripheral ID register 4 0xFD0 32 read-only 0x00000004 DES_2 JEP 106 Continuation code [3:0] read-only SIZE 4KB Count [7:4] read-only RESERVED_0 Reserved [31:8] read-only PIDR5 Peripheral ID register 5 0xFD4 32 read-only 0x00000000 RESERVED_0 Reserved [31:0] read-only PIDR6 Peripheral ID register 6 0xFD8 32 read-only 0x00000000 RESERVED_0 Reserved [31:0] read-only PIDR7 Peripheral ID register 7 0xFDC 32 read-only 0x00000000 RESERVED_0 Reserved [31:0] read-only PIDR0 Peripheral ID register 0 0xFE0 32 read-only 0x00000031 PART_0 Part Number [7:0] [7:0] read-only RESERVED_0 Reserved [31:8] read-only PIDR1 Peripheral ID register 1 0xFE4 32 read-only 0x000000b8 PART_1 Part Number [11:8] [3:0] read-only DES_0 JEP 106 Identity Code [3:0] [7:4] read-only RESERVED_0 Reserved [31:8] read-only PIDR2 Peripheral ID register 2 0xFE8 32 read-only 0x0000000b DES_1 JEP 106 Identity Code [6:4] [2:0] read-only JEDEC JEDEC [3:3] read-only REVISION Revision Code [7:4] read-only RESERVED_0 Reserved [31:8] read-only PIDR3 Peripheral ID register 3 0xFEC 32 read-only 0x00000000 CMOD Customer Modified [3:0] read-only REVAND Manufacturer revision number [7:4] read-only RESERVED_0 Reserved [31:8] read-only CIDR0 Component ID register 0 0xFF0 32 read-only 0x0000000D PRMBL_0 Preamble [7:0] read-only RESERVED_0 Reserved [31:8] read-only CIDR1 Component ID register 1 0xFF4 32 read-only 0x000000F0 PRMBL_1 Preamble [3:0] read-only CLASS Component Class [7:4] read-only RESERVED_0 Reserved [31:8] read-only CIDR2 Component ID register 2 0xFF8 32 read-only 0x00000005 PRMBL_2 Preamble [7:0] read-only RESERVED_0 Reserved [31:8] read-only CIDR3 Component ID register 1 0xFFC 32 read-only 0x000000B1 PRMBL_3 Preamble [7:0] read-only RESERVED_0 Reserved [31:8] read-only MCU_ULP_VBAT_CLOCK_ARCHITECTURE 1.0 clock select registers for the ULP VBAT peripherals CLOCK_ARCHITECTURE 0x24048000 32 read-write 0x00 0x3 registers MCUULP_VBAT_LFCLK_REG Low frequency clock select register 0x20 32 read-write 0x00000028 MCUULP_VBAT_LF_CLK_SEL mcuulp vbat low frequecy clock select [2:0] read-write MCUULP_VBAT_LF_CLK_SWITCHED Status of NPSS Low Frequency Clock Dynamic Clock Mux [3:3] read-only RESERVED Reserved [8:4] read-only MCUULP_VBAT_SYS_RTC_CLK_SEL mcuulp vbat sysrtc clock select [12:9] read-write MCUULP_VBAT_SYS_RTC_CLK_SWITCHED Status of Dynamic Clock Mux in Reference Clock Generation [13:13] read-only MCUULP_VBAT_SYS_RTC_CLK_EN Writing 1 to this enables clock to SYSRTC from dynamic mux.Writing 0 to this has no effect. [14:14] read-write RESERVED Reserved [17:15] read-write MCUULP_VBAT_SYS_RTC_CLK_DIV_FAC Division factor for RC_32_MHZ_CLK [23:18] read-write RESERVED Reserved [31:24] read-write MCUULP_VBAT_HFCLK_REG High frequency clock select register 0x118 32 read-write 0x00008000 RESERVED Reserved [1:0] read-only MCUULP_VBAT_HF_CLK_SEL mcuulp high frequency clock select [4:2] read-write RESERVED Reserved [14:5] read-only MCUULP_VBAT_HF_CLK_SWITCHED Status of NPSS High Frequency Clock Dynamic Clock Mux [15:15] read-only RESERVED Reserved [31:16] read-only MCU_ULP_CLOCK_OSCILLATORS 1.0 ULP Clock Oscillators Control Registers CLOCK_ARCHITECTURE 0x24048100 32 read-write 0x00 0x2 registers ULP_CLKOSC_CTRL_REG ULP Clock Oscillators Control Registers 0x20 32 read-write 0x008B0000 RESERVED Reserved [15:0] read-write RC_32KHZ_CLK_EN 1-Enable RC 32khz clock, 0-disable RC 32 khz clock [16:16] read-write Enable Enable RC 32khz clock 1 Disable Disable RC 32khz clock 0 RO_32KHZ_CLK_EN 1-Enable RO 32khz clock, 0-disable RO 32 khz clock [17:17] read-write Enable Enable RO 32khz clock 1 Disable Disable RO 32khz clock 0 XTAL_32KHZ_CLK_EN 1-Enable XTAL 32khz clock, 0-disable XTAL 32 khz clock [18:18] read-write Enable Enable XTAL 32khz clock 1 Disable Disable XTAL 32khz clock 0 RC_MHZ_CLK_EN 1-Enable RC 32Mhz clock, 0-disable RC 32 Mhz clock [19:19] read-write Enable Enable RC 32Mhz clock 1 Disable Disable RC 32Mhz clock 0 RO_HF_CLK_EN 1-Enable RO High Frequency clock, 0-disable RO High Frequency clock [20:20] read-write Enable Enable RC 32Mhz clock 1 Disable Disable RC 32Mhz clock 0 DOUBLER_CLK_EN 1-Enable Doubler clock, 0-disable Doubler clock [21:21] read-write Enable Enable Doubler clock 1 Disable Disable Doubler clock 0 XTAL_40MHZ_CLK_EN 1-Enable XTAL 40MHz clock, 0-disable XTAL 40 MHz clock [22:22] read-write Enable Enable XTAL 40MHz clock 1 Disable Disable XTAL 40MHz clock 0 RESERVED Reserved [31:23] read-only MCU_MULTI_CHANNEL_INTERRUPT_SELECT 1.0 MCU Multi channel interrupt select registers INTERRUPTS 0x46110000 32 read-write 0x00 0x24 registers RESERVED RESERVED 0x00 32 read-only 0x00000000 M4SS_GPDMA_INTR_SEL MCU GPDMA interrupt selection register 0x04 32 read-write 0x00000000 dma_m_interrupt_sel This bit unmasks m th the GPDMA channel interrupt [7:0] read-write UNMASKED Interrupt is not masked 1 MASKED Interrupt is masked 0 RESERVED Reserved [31:8] read-only RESERVED RESERVED 0x08 32 read-only 0x00000000 M4SS_UDMA_INTR_SEL MCU HP uDMA interrupt selection register 0x0C 32 read-write 0x00000000 udma_m_interrupt_sel This bit unmasks the m th UDMA channel interrupt [31:0] read-write UNMASKED Interrupt is not masked 1 MASKED Interrupt is masked 0 M4SS_SCT_INTR_SEL SCT interrupt selection register 0x010 32 read-write 0x00000000 sct_m_interrupt_sel This bit unmasks the m th SCT channel interrupt [31:0] read-write UNMASKED Interrupt is not masked 1 MASKED Interrupt is masked 0 BAND_GAP_TOP 1.0 Band Gap Top BAND_GAP_TOP 0x2405A400 32 read-write 0x00 0x20 registers BG_SLEEP_TIMER_REG BG sleep timer register 0x094 32 read-write 0x00290008 bgs_clk_en bandgap sampling enable through spi [0:0] read-write bg_sampling_spi_sel enable bandgap sampling through spi / pin [1:1] read-write Through_SPI Bandgap sampling through spi 1 Through_Pin Band gap sampling through pin(sleep_en) 0 bypass_pwrgating_combi Powergating is disabled for combi logic . It will always be ON. [2:2] read-write bg_ctrl_auto bg_en , bg_sh_en automatically enables or take values though SPI [3:3] read-write Enable bg_en and bg_sh_en are automatically controlled 1 Disable bg_en and sh_en take values from SPI. 0 RESERVED Reserved [15:4] read-write bgs_active_timer_sel Active timer select [17:16] read-write mask_sw_active 1: disable comp clock in between sleep duration [18:18] read-write bgs_active_timer_sel[0] taking one bit of bgs_active_timer_sel[17:16] [19:19] read-only bgs_sleep_timer_sel sleep timer count is 2'd0: active_timer_count * 2^6 2'd1: active timer_count * 2^7 2'd2: active_timer_count * 2^8 2'd3: active_timer_count * 2^9 [21:20] read-write RESERVED Reserved [31:22] read-write SCDC_CTRL_REG_0 SCDC Control register 0x098 32 read-write 0x000F002F count_reset Count reset value, count threshold will be doubler this value [3:0] read-write max_mode maximum mode it can go to [5:4] read-write fixed_mode fixed mode [6:6] read-write fixed_trim_ro Manual trim word [11:7] read-write bypass_trim_ro To program the trim value manually, irrespective of the fsm [12:12] read-write fixed_curr_prog_low Current prog value to take when ext cap en is high and sel_high freq_ext_b is 1 [16:13] read-write fixed_curr_prog_high Current prog value to take when ext cap en is high and sel_high freq_ext_b is 0 [20:17] read-write ext_cap_en To change current trim bits to high or low through spi, based on high power or low power mode.When 0, curr prog value is 0. [21:21] read-write RESERVED RESERVED [31:22] read-write BG_SCDC_PROG_REG_1 BG SCDC programme register 0x09C 32 read-write 0x00020498 ref_sel_PMU 3'd0 - 1.2V, 3'd1 - 1.15V, 3'd2 - 1.1V, 3'd3 - 1.05V 3'd4 - 1.0V 3'd5 - 0.95V,3'd6 - 0.9V,3'd7 - 0.85V [2:0] read-write an_perif_ptat_en 1 - To enable ptat currents to analog peripherals [3:3] read-write bod_clks_ptat_en 1 - To enable ptat currents to clocks and bod(cmp_npss) [4:4] read-write RESERVED RESERVED [6:5] read-write ref_sel_lp_dcdc DCDC output programming in LDO high/low power mode [9:7] read-write ref_sel_dcdc DCDC output programming vref_1p1/vref_1p05 [12:10] read-write RESERVED RESERVED [13:13] read-write bg_sh_en bg_sh_en from spi [14:14] read-write bg_en bg_en from spi [15:15] read-write bg_r Bandgap voltage programming [18:16] read-write bg_r_ptat Bandgap voltage programming [21:19] read-write RESERVED RESERVED [31:22] read-write BG_SCDC_PROG_REG_2 BG SCDC programme register 2 0x0A0 32 read-write 0x00000060 scdcdc_soft_reset soft reset signal for scdcdc fsm [0:0] read-write trim_clamp_hp trim value lower clamp value when sel high freq_b is 0 [5:1] read-write trim_clamp_lp trim value lower clamp value when sel high freq_b is 1 [10:6] read-write testmode_2_sel test mode 2 select [13:11] read-write testmode_2_en To enable testmux for BG_TESTMODE2 [14:14] read-write testmode_1_sel testmode 1 select [16:15] read-write testmode_1_en To enable test mux for BG_TESTMODE1 [17:17] read-write testmode_0_sel Test mode 0 select [19:18] read-write testmode_0_en Enable for output on to BG_TESTMODE0 [20:20] read-write scdcdc_sel To switch to SCDCDC mode from LDO mode.1 - SCDC mode,0 - LDO mode [21:21] read-write SCDC_Mode SCDC mode 1 LDO_Mode LDO mode 0 RESERVED RESERVED [31:22] read-write BG_LDO_REG BG LDO Register 0x0A4 32 read-write 0x00021000 RESERVED RESERVED [0:0] read-write test_amux_sel Select for analog mux [3:1] read-write test_amux_en Enable analog mux to test reference voltages [4:4] read-write RESERVED RESERVED [14:5] read-write LDO_0P6_ENABLE enable digital LDO [15:15] read-write LDO_0P6_LP_MODE enable low power mode, otherwise in high power mode [16:16] read-write RESERVED RESERVED [17:17] read-write LDO_0P6_CTRL vref for DCDC1p1_lp_500uA [20:18] read-write LDO_0P6_BYPASS bypass signal for DCDC1p1_lp_500uA [21:21] read-write RESERVED RESERVED [31:22] read-write BG_SCDC_READ_BACK BG SCDC READ BACK 0x0A8 32 read-only 0x00020000 sync_reset_read Read back for sync reset with ro clock [0:0] read-only RESERVED RESERVED [12:1] read-only trim_4mhz_ro Trim value for scdcdc ring oscillator [17:13] read-only scdcdc_curr_prog Scdcdc curr prog read back [21:18] read-only RESERVED RESERVED [31:22] read-only BLACKOUT_MON_EN_REG BLACKOUT MON EN REG 0x0A8 32 read-write 0x00000030 0X003FFFFF bg_r Bandgap Voltage Programming [4:0] read-write blackout_en Control signal for blackout monitor from SPI [5:5] read-write RESERVED RESERVED [31:6] read-only QSPI_2 1.0 The queued serial peripheral interface module provides a serial peripheral interface with queued transfer capability QSPI 2 0x12040000 32 read-write 0 0x184 registers QSPI_2 60 QSPI_CLK_CONFIG QSPI Clock Configuration Register 0x000 32 read-write 0x0000011F QSPI_AUTO_CSN_HIGH_CNT Minimum SOC clock cycles, during which QSPI auto csn should be high between consecutive CSN assertions [4:0] read-write QSPI_CLK_SYNC If the clock frequency to FLASH(spi_clk) and QSPI(hclk) controller is same,this bit can be set to one to by-pass the syncros results in time consumption [5:5] read-write Disable Sync logic is enabled 0 Enable Sync (synchros) logic is bypassed 1 RESERVED1 reserved1 [7:6] read-write QSPI_CLK_EN_SCLK QSPI clock enable for sclock [8:8] read-write Disable Dynamic clock gating is enabled in side QSPI controller 0 Enable Full time clock is enabled for QSPI controller. 1 RESERVED2 reserved2 [11:9] read-write SPI_CLK_DELAY_VAL Delay value programmed to RX QSPI DLL on read side. This delay is used to delay the pad clock/DQS according to the requirement [17:12] read-write OCTA_MODE_ENABLE_WITH_DQS Enables SPI octa mode along with DQS in DDR mode [18:18] read-write QSPI_DLL_ENABLE Enable for RX QSPI DLL in read mode.This is used in M4SS QSPI DDR pads to delay the pad clock DQS input [19:19] read-write Disable DLL is disabled/bypassed 0 Enable DLL is enabled 1 DDR_CLK_POLARITY_FROM_REG Used this bit to sample the data at posedge negedge after interface FFs with internal qspi clock [20:20] read-write Disable Sample at negedge 0 Enable Sample at posedge 1 QSPI_DLL_ENABLE_TX Enable for TX QSPI DLL in write path. This is used in M4SS QSPI DDR pads to delay the qspi clock output. 0–DLL is disabled bypassed 1–DLL is enabled [21:21] read-write Disable DLL is disabled/bypassed. 0 Enable DLL is enabled 1 SPI_CLK_DELAY_VAL_TX Delay value programmed to TX QSPI DLL in write path. This delay is used to delay the qspi clock output according to the requirement [27:22] read-write QSPI_RX_DQS_DLL_CALIB Delay value programmed to TX QSPI DLL in write path. This delay is used to delay the qspi clock output according to the requirement [28:28] read-write RESERVED3 reserved3 [31:29] read-write QSPI_BUS_MODE QSPI Bus Mode Register 0x004 32 read-write 0x00000000 0xFFFFFFFF RESERVED Reserved [0:0] read-write QSPI_MAN_MODE_CONF_CSN0 Configures the QSPI flash for Single/Dual/Quad mode operation in manual mode [2:1] read-write Single Mode Single Mode 0 Dual Mode Dual Mode 1 Quad Mode Quad Mode 2 Reserved Reserved 3 AUTO_MODE_RESET QSPI Auto controller reset. This is not a Self clearing bit [3:3] read-write Disable Auto mode is active 0 Enable Auto mode is inactive(In soft-reset). Auto mode FIFO also get reset. Prefetch should be disabled while going to reset. The controller should be in normal (Not a HW_mode) Manual mode. 1 QSPI_PREFETCH_EN Pre-fetch of data from the model which is connected to QSPI, automatically with out reading on AHB and is supplied to AHB, when address is matched with AHB read transaction address. Note : Pre-fetch mode is common in AUTO_MODE for both Flashes connected to csn0 and csn1. [4:4] read-write Disable Pre-fetch mode is disabled. 0 Enable Pre-fetch mode is enabled 1 QSPI_WRAP_EN Model wrap is considered with this bit and uses wrap instruction to read from FLASH, loaded into corresponding auto_config (csn0, csn1) register. Note : Wrap mode is common in AUTO_MODE for both Flashes connected to csn0 and csn1. [5:5] read-write Disable Wrap mode is disabled (AHB WRAP can be used). 0 Enable Wrap mode is enabled 1 QSPI_AUTO_MODE_FRM_REG QSPI Mode of Operation. This is valid only when HW_CTRLD_QSPI_MODE_CTRL is zero. Before switching from MANUAL to AUTO_MODE, MANUAL should be IDLE. During transition from AUTO_MODE to MANUAL_MODE(After resetting this bit to zero) we have to make sure AUTO mode operations should be completed by checking the STATUS bit in MANUAL_STATUS register[12] (0 - Idle). [6:6] read-write Disable Manual Mode is selected 0 Enable Auto Mode is selected. 1 PROGRAMMABLE_AUTO_CSN_BASE_ADDR_EN Programmable auto csn mode enable [7:7] read-write Enable Programmable auto csn mode is enabled. 1 Disable Programmable auto csn mode is diabled 0 QSPI_D2_OEN_CSN0 Direction Control for SPI_IO2 in case of dual/single mode for chip select0 csn0.It is used both in Auto and Manual Mode [8:8] read-write QSPI_D3_OEN_CSN0 Direction Control for SPI_IO3 in case of dual/single mode for chip select0 csn0.It is used both in Auto and Manual Mode. [9:9] read-write QSPI_D2_DATA_CSN0 Value of SPI_IO2 in case of dual/single mode for chip select0 csn0.It is used both in Auto and Manual Mode. [10:10] read-write QSPI_D3_DATA_CSN0 Value of SPI_IO3 in case of dual/single mode for chip select0 csn0.It is used both in Auto and Manual Mode [11:11] read-write QSPI_D2_OEN_CSN1 Direction Control for SPI_IO2 in case of dual/single mode for chip select1 (cs_n1). It is used both in Auto and Manual Mode. [12:12] read-write QSPI_D3_OEN_CSN1 Direction Control for SPI_IO3 in case of dual/single mode for chip select1 (cs_n1). It is used both in Auto and Manual Mode. [13:13] read-write QSPI_D2_DATA_CSN1 Value of SPI_IO2 in case of dual/single mode for chip select1 (cs_n1). It is used both in Auto and Manual Mode. [14:14] read-write QSPI_D3_DATA_CSN1 Value of SPI_IO3 in case of dual/single mode for chip select1 (cs_n1). It is used both in Auto and Manual Mode. [15:15] read-write QSPI_DATA_SAMPLE_EDGE Samples MISO data on clock edges. This should be ZERO for mode3 clock. [16:16] read-write Disable Pos edge of loop back spi_pad_clk. Use for low speed mode (sclk freq =< 40 MHz) 0 Enable Neg edge of loop back spi_pad_clk. Use for high speed mode (sclk freq >= 40 MHz) 1 QSPI_CLK_MODE_CSN0 QSPI Clock Mode [17:17] read-write Mode0 Mode 0, QSPI_CLK is low when QSPI_CS is high for chip select0 csn0 0 Mode3 Mode 3, QSPI_CLK is high when QSPI_CS is high for chip select0 csn0 1 QSPI_CLK_MODE_CSN1 QSPI Clock Mode [18:18] read-write Mode0 Mode 0, QSPI_CLK is low when QSPI_CS is high for chip select1 csn1 0 Mode3 Mode 3, QSPI_CLK is high when QSPI_CS is high for chip select1 csn1 1 QSPI_CLK_MODE_CSN2 QSPI Clock Mode [19:19] read-write Mode0 Mode 0 QSPI_CLK is low when QSPI_CS is high for chip select2 csn2 0 Mode3 Mode 3 QSPI_CLK is high when QSPI_CS is high for chip select2 csn2 1 QSPI_CLK_MODE_CSN3 QSPI Clock Mode [20:20] read-write Mode0 Mode 0, QSPI_CLK is low when QSPI_CS is high for chip select3 csn3 0 Mode3 Mode 3, QSPI_CLK is high when QSPI_CS is high for chip select3 csn3 1 FLASH_AW_FIFO_LS_EN Qspi flash auto write fifo light sleep enable [21:21] read-write FLASH_SEC_AES_LS_EN Qspi flash auto write fifo light sleep enable [22:22] read-write RESERVED1 reserved1 [23:23] read-write QSPI_D2_OEN_CSN2 Direction Control for SPI_IO2 in case of dual/single mode for chip select2 (cs_n2). It is used both in Auto and Manual Mode. [24:24] read-write QSPI_D3_OEN_CSN2 Direction Control for SPI_IO3 in case of dual/single mode for chip select2 (cs_n2). It is used both in Auto and Manual Mode. [25:25] read-write QSPI_D2_DATA_CSN2 Value of SPI_IO2 in case of dual/single mode for chip select2 (cs_n2). It is used both in Auto and Manual Mode. [26:26] read-write QSPI_D3_DATA_CSN2 Value of SPI_IO3 in case of dual/single mode for chip select2 (cs_n2). It is used both in Auto and Manual Mode. [27:27] read-write QSPI_D2_OEN_CSN3 Direction Control for SPI_IO2 in case of dual/single mode for chip select3 (cs_n3). It is used both in Auto and Manual Mode. [28:28] read-write QSPI_D3_OEN_CSN3 Direction Control for SPI_IO3 in case of dual/single mode for chip select3 (cs_n3). It is used both in Auto and Manual Mode. [29:29] read-write QSPI_D2_DATA_CSN3 Value of SPI_IO2 in case of dual/single mode for chip select3 (cs_n3). It is used both in Auto and Manual Mode. [30:30] read-write QSPI_D3_DATA_CSN3 Value of SPI_IO3 in case of dual/single mode for chip select3 (cs_n3). It is used both in Auto and Manual Mode. [31:31] read-write QSPI_AUTO_CONFIG_1 QSPI Auto Controller Configuration 1 Register 0x008 32 read-write 0x00000000 0xFF8FFFFF QSPI_EXT_BYTE_MODE_CSN0 Mode of operation of QSPI in the extra byte phase [1:0] read-write SPI SPI 0 Dual SPI Dual SPI 1 Quad SPI Quad SPI 2 Reserved Reserved 3 QSPI_DUMMY_MODE_CSN0 Mode of operation of QSPI in instruction phase [3:2] read-write SPI SPI 0 Dual SPI Dual SPI 1 Quad SPI Quad SPI 2 Reserved Reserved 3 QSPI_ADDR_MODE_CSN0 Mode of operation of QSPI in instruction phase [5:4] read-write SPI SPI 0 Dual SPI Dual SPI 1 Quad SPI Quad SPI 2 Reserved Reserved 3 QSPI_CMD_MODE_CSN0 Mode of operation of QSPI in instruction phase [7:6] read-write SPI SPI 0 Dual SPI Dual SPI 1 Quad SPI Quad SPI 2 Reserved Reserved 3 QSPI_DATA_MODE_CSN0 Mode of operation of QSPI in DATA phase [9:8] read-write SPI SPI 0 Dual SPI Dual SPI 1 Quad SPI Quad SPI 2 Reserved Reserved 3 QSPI_EXTRA_BYTE_CSN0 Value of the extra byte to be transmitted, if the extra byte mode is enabled [17:10] read-write QSPI_EXTRA_BYTE_EN_CSN0 Value of the extra byte to be transmitted, if the extra byte mode is enabled [19:18] read-write Not transmit byte Do not transmit extra byte. 0 Transmit byte Transmit Extra byte after address phase 1 Transmit first nibble Transmit only first nibble of the byte and maintain Hi-Z on the IO bus for next nibble 2 Reserved Reserved 3 QSPI_WRAP_SIZE Qspi auto wrap size [21:20] read-write RESERVED1 reserved1 [22:22] read-write QSPI_PG_JUMP_CSN0 Index Jump instruction [23:23] read-write Disable Do not use Index jump instruction 0 Enable Use Index jump instruction specified by QSPI_PG_JUMP_INST 1 QSPI_DUMMY_BYTES_INCR_CSN0 Specifies the number of dummy bytes 0 to 7 for the selected SPI mode [27:24] read-write QSPI_DUMMY_BYTES_WRAP_CSN0 Specifies the number of dummy bytes 0 to 7 for the selected SPI mode in case of wrap instruction [31:28] read-write QSPI_AUTO_CONFIG_2 QSPI Auto Controller Configuration 2 Register 0x00C 32 read-write 0x00000301 0xFFFFFFFF QSPI_RD_DATA_SWAP_AUTO_CSN0 Auto read data [0:0] read-write Disable Do not swap the read data in auto mode 0 Enable Swap the auto read data in auto mode 1 QSPI_ADR_SIZE_16_BIT_AUTO_MODE_CSN0 Bit address sent to model [1:1] read-write Disable 24 bit address is sent to model 0 Enable 16 Bit address is sent to model 1 QSPI_CONTI_RD_EN_CSN0 Continuous read enable bit [2:2] read-write Disable Continuous read disabled. 0 Enable Continuous read enabled. 1 DUMMY_BYTES_WR_RD_CSN0 Dummy bytes to the model to be read or to be write [3:3] read-write Disable Dummy bytes will be read 0 Enable Dummy bytes to be write. 1 QSPI_DUMMY_BYTES_JMP_CSN0 Dummy cycles to be selected in case of JUMP [7:4] read-write QSPI_RD_INST_CNS0_LSB Read instruction LS byte to be used for the selected SPI modes and when wrap is not needed or supported. [15:8] read-write QSPI_RD_WRAP_INT_CSN0 Read instruction to be used, when wrap mode is supported by QSPI flash [23:16] read-write QSPI_PG_JUMP_INST_CSN0 Read instruction to be used, when Page jump is to be used [31:24] read-write QSPI_MANUAL_CONFIG1 QSPI Manual Configuration 1 Register 0x10 32 read-write 0x00180001 0xFFFFFFFF QSPI_MANUAL_CSN SPI CS in manual mode [0:0] read-write QSPI_MANUAL_WR Write enable for manual mode when CS is low [1:1] read-write QSPI_MANUAL_RD Read enable for manual mode when CS is low [2:2] read-write QSPI_MANUAL_RD_CNT Indicates total number of bytes to be read along with [31:27] bits of this register.Maximum length supported is 32k bytes [12:3] read-write QSPI_MANUAL_CSN_SELECT Indicates which CSn is valid. Can be programmable in manual mode. Note : In auto mode csn select is decoded from the address itself, AHB_addr [25:24]. [14:13] read-write RESERVED1 reserved1 [18:15] read-write QSPI_MANUAL_SIZE_FRM_REG Manual reads and manual writes(If take_manual_size_from_reg bit is 1) [20:19] read-write 1 Byte 8 – bit mode 0 2 Bytes 16 – bit mode 1 3 Bytes 24 – bit mode 2 4 Bytes 32 – bit mode 3 TAKE_QSPI_MANUAL_WR_SIZE_FRM_REG QSPI take write size [21:21] read-write Disable No action. Takes write size from fifo 0 Enable Take write size from Manual config register1 1 QSPI_FULL_DUPLEX_EN Full duplex mode enable. [22:22] read-write Disable Full duplex mode disabled. 0 Enable Full duplex mode enabled 1 RESERVED2 reserved2 [24:23] read-write HW_CTRLD_QSPI_MODE_CTRL Hardware controlled qspi mode in between AUTO and manual [25:25] read-write Disable Hardware control is disabled 0 Enable Hardware control is enabled. 1 QSPI_MANUAL_QSPI_MODE Internally the priority is given to manual mode [26:26] read-write Disable SPI mode 0 Enable Host SPI mode. 1 QSPI_MANUAL_RD_CNT Indicates total number of bytes or bits (depending on Qspi_manual_dummy_byte_or_bit_mode bit) to be read along with 12:3 bits of this register. Maximum length supported is 32k bytes. [31:27] read-write QSPI_MANUAL_CONFIG2 QSPI Manual Configuration 2 Register 0x14 32 read-write 0x000000F0 0xFFF QSPI_WR_DATA_SWAP_MNL_CSN0 Swap the write data inside the QSPI controller it-self [0:0] read-write Disable Manual write data swap is disabled for csn0. 0 Enable Manual write data swap is enabled for csn0. 1 QSPI_WR_DATA_SWAP_MNL_CSN1 Swap the write data inside the QSPI controller it-self. [1:1] read-write Disable Manual write data swap is disabled for csn1. 0 Enable Manual write data swap is enabled for csn1. 1 QSPI_WR_DATA_SWAP_MNL_CSN2 Swap the write data inside the QSPI controller itself. [2:2] read-write Disable Manual write data swap is disabled for csn2. 0 Enable Manual write data swap is enabled for csn2. 1 QSPI_WR_DATA_SWAP_MNL_CSN3 Swap the write data inside the QSPI controller itself. [3:3] read-write Disable Manual write data swap is disabled for csn3. 0 Enable Manual write data swap is enabled for csn3. 1 QSPI_RD_DATA_SWAP_MNL_CSN0 Swap the read data inside the QSPIcontroller it self. [4:4] read-write Disable Manual read data swap is disabled for csn0. 0 Enable Manual read data swap is enabled for csn0. 1 QSPI_RD_DATA_SWAP_MNL_CSN1 Swap the read data inside the QSPIcontroller itself. [5:5] read-write Disable Manual read data swap is disabled for csn1 0 Enable Manual read data swap is enabled for csn1 1 QSPI_RD_DATA_SWAP_MNL_CSN2 Swap the read data inside the QSPIcontroller it-self [6:6] read-write Disable Manual read data swap is disabled for csn2 0 Enable Manual read data swap is enabled for csn2 1 QSPI_RD_DATA_SWAP_MNL_CSN3 Swap the read data inside the QSPIcontroller itself [7:7] read-write Disable Manual read data swap is disabled for csn3 0 Enable Manual read data swap is enabled for csn3 1 QSPI_MAN_MODE_CONF_CSN1 Configures the QSPI flash for Single/Dual/Quad mode operation in manual mode for chip select1 csn1 [9:8] read-write Single Single 0 Dual Dual 1 Quad Quad 2 Reserved Reserved 3 QSPI_MAN_MODE_CONF_CSN2 Configures the QSPI flash for Single or Dual or Quad mode operation in manual mode for chip select2 csn2 [11:10] read-write Single Single 0 Dual Dual 1 Quad Quad 2 Reserved Reserved 3 QSPI_MAN_MODE_CONF_CSN3 Configures the QSPI flash for Single or Dual or Quad mode operation in manual mode for chip select3 csn3 [13:12] read-write Single Single 0 Dual Dual 1 Quad Quad 2 Reserved Reserved 3 LOOP_BACK_MODE_EN Internal loop back test mode. When this is enabled, what ever data driven out will be sampled in to DOUT fifo. [14:14] read-write QSPI_MANUAL_DDR_PHASE DDR operations can be performed even in manual mode [15:15] read-write Enable Manual mode DDR operation enabled. 1 Disable Manual mode DDR operation disabled 0 RESERVED1 Reserved [16:16] read-write QSPI_RD_DATA_SWAP_WORD_LVL_MNL_CSN0 Set this bit for read data byte swapping within the word. It is valid only for octa ddr mode. It is valid for csn0. [17:17] read-write QSPI_RD_DATA_SWAP_WORD_LVL_MNL_CSN1 Set this bit for read data byte swapping within the word. It is valid only for octa ddr mode. It is valid for csn1. [18:18] read-write QSPI_RD_DATA_SWAP_WORD_LVL_MNL_CSN2 Set this bit for read data byte swapping within the word. It is valid only for octa ddr mode. It is valid for csn2. [19:19] read-write QSPI_RD_DATA_SWAP_WORD_LVL_MNL_CSN3 Set this bit for read data byte swapping within the word. It is valid only for octa ddr mode. It is valid for csn3. [20:20] read-write QSPI_WR_DATA_SWAP_WORD_LVL_MNL_CSN0 Set this bit for write data byte swapping within the word. It is valid only for octa ddr mode. It is valid for csn0. [21:21] read-write QSPI_WR_DATA_SWAP_WORD_LVL_MNL_CSN1 Set this bit for write data byte swapping within the word. It is valid only for octa ddr mode. It is valid for csn1. [22:22] read-write QSPI_WR_DATA_SWAP_WORD_LVL_MNL_CSN2 Set this bit for write data byte swapping within the word. It is valid only for octa ddr mode. It is valid for csn2. [23:23] read-write QSPI_WR_DATA_SWAP_WORD_LVL_MNL_CSN3 Set this bit for write data byte swapping within the word. It is valid only for octa ddr mode. It is valid for csn3. [24:24] read-write QSPI_MANUAL_DUMMY_BYTE_OR_BIT_MODE Indicates qspi_manual_rd_cnt values are dummy bytes or bits in manual mode.It is used to provide proper dummy cycles in manual read mode. [25:25] read-write Enable Dummy bits mode 1 Disable Dummy bytes mode 0 RESERVED2 reserved2 [31:26] read-write QSPI_MANUAL_WRITE_DATA2 QSPI Manual Write Data 2 Register 0x80 32 read-write 0x00000100 0xFF QSPI_MANUAL_WRITE_DATA2 Number of bits to be written in write mode [4:0] read-write RESERVED1 reserved1 [6:5] read-write USE_PREV_LENGTH Use previous length. [7:7] read-write Disable No action 0 Enable Uses previously programmed length in [4:0] of this register for next writes 1 QSPI_CLK_ENABLE_HCLK Static clock enable for qspi hclock [8:8] read-write RESERVED2 reserved2 [31:9] read-write QSPI_FIFO_THRLD QSPI FIFO Threshold Register 0x1C 32 read-write 0x00000C7 0x1FF FIFO_AEMPTY_THRLD FIFO almost empty threshold [3:0] read-write FIFO_AFULL_THRLD FIFO almost full threshold [7:4] read-write WFIFO_RESET Write fifo reset [8:8] read-write RFIFO_RESET Read fifo reset [9:9] read-write RESERVED1 reserved1 [31:10] read-write QSPI_MANUAL_STATUS QSPI Manual Status Register 0x20 32 read-only 0x00000598 0x7FFF QSPI_BUSY State of Manual mode. [0:0] read-only Disable QSPI controller is IDLE in Manual mode. 0 Enable A read, write or dummy cycle operation is in process in manual mode. 1 FIFO_FULL_WFIFO_S Status indication for Wfifo in manual mode [1:1] read-only FIFO_AFULL_WFIFO_S Status indication for Wfifo in manual mode [2:2] read-only FIFO_EMPTY_WFIFO Status indication for Wfifo in manual mode [3:3] read-only FIFO_AEMPTY_WFIFO Status indication for Wfifo in manual mode [4:4] read-only FIFO_FULL_RFIFO Status indication for Rfifo in manual mode [5:5] read-only FIFO_AFULL_RFIFO Status indication for Rfifo in manual mode [6:6] read-only FIFO_EMPTY_RFIFO_S Status indication for Rfifo in manual mode [7:7] read-only FIFO_AEMPTY_RFIFO_S Status indication for Rfifo in manual mode [8:8] read-only QSPI_MANUAL_RD_CNT This is a result of 10 bits ORing counter [9:9] read-only Disable No read transactions are in pending 0 Enable Read transactions are in pending ( to be done) 1 AUTO_MODE_FSM_IDLE_SCLK Auto mode idle signal to track auto controller is busy or idle. [10:10] read-only Disable Auto mode is busy 0 Enable Auto mode is idle 1 QSPI_AUTO_MODE QSPI controller status. [11:11] read-only Disable QSPI controller is in manual mode. 0 Enable QSPI controller is in auto mode. 1 QSPI_AUTO_MODE_FRM_REG_SCLK QSPI auto mode status. Valid only when HW_CTRLD_QSPI_MODE_CTRL is zero. [12:12] read-only Disable QSPI controller is hot coded to manual mode operations. 0 Enable QSPI controller is hot coded to AUTO mode operations 1 HW_CTRLD_MODE_SCLK QSPI mode status in HW_CTRLD_MODE [13:13] read-only Disable QSPI controller is in MANUAL mode. 0 Enable QSPI controller is working in AUTO MODE. 1 HW_CTRLD_MODE_CTRL_SCLK HW_CTRLD_MODE status [14:14] read-only Disable HW_CTRL_MODE is disabled. 0 Enable HW_CTRL_MODE is enabled 1 AW_CTRL_BUSY Auto write busy indication. [15:15] read-only AUTO_RD_BUSY Auto read busy indication. [16:16] read-only RESERVED1 reserved1 [31:17] read-only QSPI_INTR_MASK QSPI Interrupt Mask Register 0x24 32 read-write 0x00000000 0x6F QSPI_INTR_MASK Interrupt Status bit [0:0] read-write Disable Do not touch 0 Enable mask the qspi intr 1 FIFO_AEMPTY_RFIFO_MASK Read FIFO almost empty interrupt mask [1:1] read-write Disable Do not touch 0 Enable Read fifo almost empty intr mask. 1 FIFO_AFULL_RFIFO_MASK Read FIFO almost full interrupt mask [2:2] read-write Disable Do not touch 0 Enable read fifo almost full intr mask 1 FIFO_AEMPTY_WFIFO_MASK Write FIFO almost empty interrupt mask [3:3] read-write Disable Do not touch 0 Enable write fifo almost empty intr mask. 1 FIFO_AFULL_WFIFO_MASK Write FIFO almost full interrupt mask [4:4] read-write Disable Do not touch 0 Enable Write fifo almost full intr mask 1 FIFO_FULL_WFIFO_MASK Write FIFO full interrupt mask [5:5] read-write Disable Do not touch 2 Enable write fifo full intr mask 1 FIFO_EMPTY_RFIFO_MASK Read FIFO empty interrupt mask [6:6] read-write Disable Do not touch 0 Enable Read fifo is empty intr mask 1 AHB_AUTO_WRITE_INTR_MASK Rising interrupt for any auto write operation on AHB bus. This bit is a mask for this interrupt [7:7] read-write QSPI_AUTO_BASE_ADDR_ERR_INTR_MASK Rising interrupt when no csn is selected using programmable auto base address. This bit is a mask for this interrupt. [8:8] read-write M4QSPI_MANUAL_BLOCKED_INTR_MASK Rising interrupt when M4 QSPI tries to do manual mode transactions in Common flash mode (3). This bit is a mask for this interrupt. [9:9] read-write M4_AUTO_READ_OUT_RANGE_INTR_MASK Rising interrupt when M4 QSPI tries to read TA locations in Common flash mode (3). This bit is a mask for this interrupt. [10:10] read-write RESERVED1 reserved1 [31:11] read-write QSPI_INTR_UNMASK QSPI Interrupt Unmask Register 0x28 32 read-write 0x00000000 0x7F QSPI_INTR_UNMASK Interrupt Status bit [0:0] read-write Disable Do not touch 0 Enable unmask the qspi intr 1 FIFO_AEMPTY_RFIFO_UN Read FIFO almost empty interrupt unamsk [1:1] read-write Disable Do not touch 0 Enable Read fifo almost empty intr unmask 1 FIFO_AFULL_RFIFO_UNMASK Read FIFO almost full interrupt unamsk [2:2] read-write Disable Do not touch 0 Enable read fifo almost full intr unmask. 1 FIFO_AEMPTY_WFIFO_UNMASK Write FIFO almost empty interrupt unamsk [3:3] read-write Disable Do not touch 0 Enable write fifo almost empty intr unmask 1 FIFO_AFULL_WFIFO_UNMASK Write FIFO almost full interrupt unamsk [4:4] read-write Disable Do not touch 0 Enable Write fifo almost full intr unmask. 1 FIFO_FULL_WFIFO_UNMASK Write FIFO full interrupt unamsk [5:5] read-write Disable Do not touch 4 Enable write fifo full intr unmask 3 FIFO_EMPTY_RFIFO_UNMASK Read FIFO empty interrupt unamsk [6:6] read-write Disable Do not touch 0 Enable Read fifo is empty intr unmask 1 AHB_AUTO_WRITE_INTR_UNMASK Rising interrupt for any auto write operation on AHB bus. This bit is a unmask for this interrupt. [7:7] read-write QSPI_AUTO_BASE_ADDR_ERR_INTR_UNMASK Rising interrupt when M4 QSPI tries to do manual mode transactions in Common flash mode (3). This bit is a unmask for this interrupt. [8:8] read-write M4QSPI_MANUAL_BLOCKED_INTR_UNMASK Rising interrupt when M4 QSPI tries to do manual mode transactions in Common flash mode (3). This bit is a unmask for this interrupt. [9:9] read-write M4_AUTO_READ_OUT_RANGE_INTR_UNMASK Rising interrupt when M4 QSPI tries to read TA locations in Common flash mode (3). This bit is a unmask for this interrupt. [10:10] read-write RESERVED1 reserved1 [31:11] read-write QSPI_INTR_STS QSPI Interrupt Status Register 0x2C 32 read-only 0x00000000 0x7F QSPI_INTR_LVL Interrupt Status bit [0:0] read-only Disable no interrupt 0 Enable qspi raised a interrupt 1 FIFO_AEMPTY_RFIFO_LVL Read FIFO reached almost empty threshold [1:1] read-only Disable Read fifo does not reached almost empty threshold 0 Enable Read fifo reached almost empty threshold 1 FIFO_AFULL_RFIFO_LVL Read FIFO reached almost full threshold [2:2] read-only Disable read FIFO do not reached almost full threshold 0 Enable read FIFO reached almost full threshold 1 FIFO_AEMPTY_WFIFO_LVL Write FIFO reached almost empty threshold [3:3] read-only Disable write FIFO not reached almost full threshold. 0 Enable write FIFO reached almost empty threshold. 1 FIFO_AFULL_WFIFO_LVL Write FIFO reached almost full threshold [4:4] read-only Disable write FIFO not reached almost full threshold 0 Enable Write FIFO reached almost full threshold 1 FIFO_FULL_WFIFO_LVL Write FIFO reached full threshold [5:5] read-only Disable Write fifo not got full 0 Enable write fifo got full. 1 FIFO_EMPTY_RFIFO_LVL Read FIFO reached empty threshold [6:6] read-only Disable Read FIFO is not empty 0 Enable Read FIFO is empty 1 AHB_AUTO_WRITE_INTR_LEV rising interrupt for any auto write operation on AHB bus. [7:7] read-only QSPI_AUTO_BASE_ADDR_ERR_INTR_LVL Rising interrupt when no csn is selected using programmable auto base address. [8:8] read-only M4QSPI_MANUAL_BLOCKED_LVL Rising interrupt when M4 QSPI tries to do manual mode transactions in Common flash mode (3). [9:9] read-only M4_AUTO_READ_OUT_RANGE_LVL Rising interrupt when M4 QSPI tries to read TA locations in Common flash mode (3). [10:10] read-only RESERVED1 reserved1 [31:11] read-only QSPI_INTR_ACK QSPI Interrupt Acknowledge Register 0x30 32 read-write 0x00000000 0x7F QSPI_INTR_ACK Interrupt Status bit [0:0] write-only Disable Do not touch 0 Enable unmask the qspi intr. 1 FIFO_AEMPTY_RFIFO_ACK Read fifo almost empty interrupt unmask [1:1] write-only Disable Do not touch 0 Enable Read fifo almost empty intr unmask 1 FIFO_AFULL_RFIFO_ACK Read fifo almost full interrupt unmask [2:2] write-only Disable Do not touch 0 Enable read fifo almost full intr unmask. 1 FIFO_AEMPTY_WFIFO_ACK Write fifo almost empty interrupt unmask [3:3] write-only Disable Do not touch 0 Enable write fifo almost empty intr unmask. 1 FIFO_AFULL_WFIFO_ACK Write fifo almost full interrupt unmask [4:4] write-only Disable Do not touch 0 Enable Write fifo almost full intr unmask. 1 FIFO_FULL_WFIFO_ACK Write fifo full interrupt unmask [5:5] write-only Disable Do not touch 0 Enable write fifo full intr unmask 1 FIFO_EMPTY_RFIFO_ACK Read fifo empty interrupt unmask [6:6] write-only Disable Do not touch 0 Enable Read fifo is empty intr unmask 1 AHB_AUTO_WRITE_INTR_ACK Rising interrupt for any auto write operation on AHB bus. This bit is an ack for this interrupt. [7:7] write-only QSPI_AUTO_BASE_ADDR_ERR_INTR_ACK Rising interrupt when no csn is selected using programmable auto base address. This bit is an ack for this interrupt. [8:8] write-only M4QSPI_MANUAL_BLOCKED_INTR_ACK Rising interrupt when M4 QSPI tries to do manual mode transactions in Common flash mode (3).This bit is an ack for this interrupt. [9:9] read-write M4_AUTO_READ_OUT_RANGE_INTR_ACK Rising interrupt when M4 QSPI tries to read TA locations in Common flash mode (3). This bit is an ack for this interrupt. [10:10] read-write RESERVED1 reserved1 [31:11] write-only QSPI_STS_MC QSPI State Machine Monitor Register 0x34 32 read-only 0x00000000 0x6FF BUS_CTRL_PSTATE Bus controller present state [3:0] read-only AUTO_CTRL_PSTATE Auto controller present state [6:4] read-only QSPI_MASTER_PSTATE Qspi master present state [9:7] read-only QSPI_MANUAL_RD_CNT Qspi manual read counter value [24:10] read-only RESERVED1 reserved1 [31:25] read-only QSPI_AUTO_CONFIG_1_CSN1 QSPI Auto Controller Configuration 1 CSN1 Register 0x38 32 read-write 0x00000000 0x87FFFF QSPI_EXT_BYTE_MODE_CSN1 Mode of operation of QSPI in instruction phase. [1:0] read-write SPI SPI 0 Dual SPI Dual SPI 1 Quad SPI Quad SPI 2 Reserved Reserved 3 QSPI_DUMMY_MODE_CSN1 Mode of operation of QSPI in instruction phase [3:2] read-write SPI SPI 0 Dual SPI Dual SPI 1 Quad SPI Quad SPI 2 Reserved Reserved 3 QSPI_ADDR_MODE_CSN1 Mode of operation of QSPI in instruction phase. [5:4] read-write SPI SPI 0 Dual SPI Dual SPI 1 Quad SPI Quad SPI 2 Reserved Reserved 3 QSPI_CMD_MODE_CSN1 Mode of operation of QSPI in instruction phase. [7:6] read-write SPI SPI 0 Dual SPI Dual SPI 1 Quad SPI Quad SPI 2 Reserved Reserved 3 QSPI_DATA_MODE_CSN1 Mode of operation of QSPI in DATA phase. [9:8] read-write SPI SPI 0 Dual SPI Dual SPI 1 Quad SPI Quad SPI 2 Reserved Reserved 3 QSPI_EXTRA_BYTE_CSN1 Value of the extra byte to be transmitted, if the extra byte mode is enabled. [17:10] read-write QSPI_EXTRA_BYTE_EN_CSN1 Mode of operation of QSPI in DATA phase. [19:18] read-write Not transmit Do not transmit extra byte. 0 Transmit extra byte Transmit Extra byte after address phase 1 Transmit nibble Transmit only first nibble of the byte and maintain Hi-Z on the IO bus for next nibble. 2 Reserved Reserved 3 QSPI_WRAP_SIZE Qspi auto wrap size [21:20] read-write RESERVED1 reserved1 [22:22] read-write QSPI_PG_JUMP_CSN1 QSPI index jump instruction [23:23] write-only Disable Do not use Index jump instruction. 0 Enable Use Index jump instruction specified by QSPI_PG_JUMP_INST 1 QSPI_DUMMY_BYTES_INCR_CSN1 Specifies the number of dummy bytes 0 to 7 for the selected SPI mode. [27:24] read-only QSPI_DUMMY_BYTES_WRAP_CSN1 Specifies the number of dummy bytes 0 to 7 for the selected SPI mode in case of wrap instruction. [31:28] read-only QSPI_AUTO_CONFIG_2_CSN1 QSPI Auto Controller Configuration 2 CSN1 Register 0x3C 32 read-write 0x00000001 0xFFFFFFFF QSPI_RD_SWAP_AUTO_CSN1 Swap the read data from the flash in byte order for chip select1 csn1 in auto mode. [0:0] read-write Swap_Disable Swap is disabled. 0 Swap_Enable Swap is enabled 1 QSPI_ADR_SIZE_16BIT_AUTO_MODE_CSN1 Bit address sent to model [1:1] read-write Disable 24 Bit address is sent to model. 0 Enable 16 Bit address is sent to model 1 QSPI_CONTI_RD_EN_CSN1 Continuous read enable bit. [2:2] read-write Disable Continuous read disabled 0 Enable Continuous read enabled. 1 DUMMY_BYTES_WR_RD Dummy bytes to the model to be read or to be write. [3:3] read-write Disable Dummy bytes will be read 0 Enable Dummy bytes to be write 1 QSPI_DUMMY_BYTES_JMP_CSN1 Dummy cycles to be selected in case of JUMP [7:4] read-write QSPI_RD_INST_CSN1 Read instruction to be used for the selected SPI modes and when wrap is not needed or supported [15:8] read-write QSPI_RD_WRAP_INST_CSN1 Read instruction to be used for the selected SPI modes and when wrap is not needed or supported [23:16] read-write QSPI_PG_JMP_INST_CSN1 Read instruction to be used, when Page jump is to be used. [31:24] read-write QSPI_AUTO_CONFIG_3_CSN0 QSPI Auto Controller Configuration 3 CSN0 Register 0x90 32 read-write 0x00000000 0xFFFFFFFF QSPI_DUMMY_BYTE_OR_BIT_CSN0 Indicates all above mention values are dummy bytes or bits in auto mode. [0:0] read-write Disable dummy bytes mode 0 Enable dummy bits mode 1 QSPI_DUMMY_BYTES_INCR_CSN0 Specifies the number of dummy bytes for the selected SPI mode. It contains MS nibble for byte. [4:1] read-write QSPI_DUMMY_BYTES_WRAP_CSN0 Specifies the number of dummy bytes for the selected SPI mode in case of wrap instruction. It contains MS nibble for byte. [8:5] read-write QSPI_DUMMY_BYTES_JMP_CSN0 Dummy cycles to be selected in case of JUMP. It contains MS nibble of byte. [12:9] read-write QSPI_DDR_ADDR_MODE_CSN0 DDR Address mode. In the SPI operation (cmd, addr, extra, dummy, data) [13:13] read-write Disable Address bytes are driven in SDR fashion 0 Enable Address bytes are driven in DDR fashion 1 QSPI_DDR_DUMMY_MODE_CSN0 DDR dummy byte mode.In the SPI operation (cmd, addr, extra, dummy, data) [14:14] read-write Disable Extra byte is driven in SDR fashion. 0 Enable Extra byte is driven in DDR fashion. 1 QSPI_DDR_EXTRA_MODE_CSN0 DDR extra byte mode.In the SPI operation (cmd, addr, extra, dummy, data) [15:15] read-write Disable Dummy bytes are driven in SDR fashion. 0 Enable Dummy bytes are driven in DDR fashion. 1 QSPI_DDR_DATA_MODE_CSN0 DDR data mode.In the SPI operation (cmd, addr, extra, dummy, data) [16:16] read-write Disable Data are sampled in SDR fashion 0 Enable Data are sampled in DDR fashion 1 QSPI_AUTO_DDR_CMD_MODE_CSN0 DDR data mode.In the SPI operation (cmd, addr, extra, dummy, data) [17:17] read-write Disable Command byte is driven in SDR fashion. 0 Enable Command byte is driven in DDR fashion. 1 QSPI_CMD_SIZE_16BIT_CSN0 Enable for 16 read cmd size for csn0. [18:18] read-write Disable 8 bit read command 0 Enable 16 bit read command 1 QSPI_ADR_SIZE_32BIT_AUTO_MODE 32 bit addressing support enable. [19:19] read-write Disable 24/16 Bit address is sent to model. 0 Enable 32 Bit address is sent to model. 1 QSPI_RD_DATA_SWAP_WORD_LVL_AUTO_CSN0 Rd data swap at word level in auto mode for csn0. It is valid for octa mode. [20:20] read-write RESERVED3 reserved3 [23:21] read-write QSPI_RD_INST_CSN0_MSB Read instruction MS byte to be used the selected SPI modes and when wrap is not needed or supported. [31:24] read-write QSPI_AUTO_CONFIG_3_CSN1 QSPI Auto Controller Configuration 3 CSN1 Register 0x94 32 read-write 0x00000000 0xFFFFFFFF QSPI_DUMMY_BYTE_OR_BIT_CSN1 Indicates all above mention values are dummy bytes or bits in auto mode. [0:0] read-write QSPI_DUMMY_BYTES_INCR_CSN1 Specifies the number of dummy bytes for the selected SPI mode. It contains MS nibble for byte. [4:1] read-write QSPI_DUMMY_BYTES_WRAP_CSN1 Specifies the number of dummy bytes for the selected SPI mode in case of wrap instruction. It contains MS nibble for byte. [8:5] read-write QSPI_DUMMY_BYTES_JMP_CSN1 Dummy cycles to be selected in case of JUMP. It contains MS nibble of byte. [12:9] read-write QSPI_DDR_ADDR_MODE_CSN1 DDR address mode for csn1.In the SPI operation (cmd, addr, extra, dummy, data) [13:13] read-write Disable Address bytes are driven in SDR fashion 0 Enable Address bytes are driven in DDR fashion 6 QSPI_DDR_DUMMY_MODE_CSN1 DDR dummy byte mode for csn1.In the SPI operation (cmd, addr, extra, dummy, data) [14:14] read-write Disable Extra byte is driven in SDR fashion 0 Enable Extra byte is driven in DDR fashion 5 QSPI_DDR_EXTRA_MODE_CSN1 DDR extra byte mode for csn1.In the SPI operation (cmd, addr, extra, dummy, data) [15:15] read-write Disable Dummy bytes are driven in SDR fashion 0 Enable Dummy bytes are driven in DDR fashion 4 QSPI_DDR_DATA_MODE_CSN1 DDR data mode for csn1.In the SPI operation (cmd, addr, extra, dummy, data) [16:16] read-write Disable Data are sampled in SDR fashion 0 Enable Data are sampled in DDR fashion 3 QSPI_AUTO_DDR_CMD_MODE_CSN1 DDR data mode for csn1.In the SPI operation (cmd, addr, extra, dummy, data) [17:17] read-write Disable Command byte is driven in SDR fashion 0 Enable Command byte is driven in DDR fashion 2 QSPI_CMD_SIZE_16BIT_CSN1 Enable for 16 read cmd size for csn1. [18:18] read-write Disable 8 bit read command 0 Enable 16 bit read command 1 RESERVED1 Reseerved1 [19:19] read-write QSPI_RD_DATA_SWAP_WORD_LVL_AUTO_CSN1 Rd data swap at word level in auto mode for csn1. It is valid for octa mode. [20:20] read-write RESERVED2 Reserved2 [23:21] read-write QSPI_RD_INST_CSN1_MSB Read instruction MS byte to be used the selected SPI modes and when wrap is not needed or supported. [31:24] read-write QSPI_AUTO_BASE_ADDR_CSN0 QSPI Controller auto Base address configuration CSN0 Register 0xA0 32 read-write 0x00000000 0xFFFFFFFF QSPI_AUTO_BASE_ADDR_CSN0 Holds the 32 bit base address for select chip select0 in programmable auto csn mode.It is valid only programmable auto csn mode is enabled. [31:0] read-write QSPI_AUTO_BASE_ADDR_CSN1 QSPI Controller auto Base address configuration CSN1 Register 0xA4 32 read-write 0x00000000 0xFFFFFFFF QSPI_AUTO_BASE_ADDR_CSN1 Holds the 32 bit base address for select chip select1 in programmable auto csn mode.It is valid only programmable auto csn mode is enabled. [31:0] read-write OCTASPI_BUS_CONTROLLER none 0xB0 32 read-write 0x00000000 0xFFFFFFFF QSPI_D7TOD4_DATA_CSN0 Value of SPI_IO7,6,5 and 4 in case of quad/dual/single mode for chip select1 (cs_n0). It is used both in Auto and Manual Mode. [3:0] read-write QSPI_D7TOD4_OEN_CSN0 Direction Control for SPI_IO 7,6,5 and 4 in case of quad/dual/single mode for chip select0 (cs_n0). It is used both in Auto and Manual Mode. [7:4] read-write QSPI_D7TOD4_DATA_CSN1 Value of SPI_IO7,6,5 and 4 in case of quad/dual/single mode for chip select1 (cs_n1). It is used both in Auto and Manual Mode. [11:8] read-write QSPI_D7TOD4_OEN_CSN1 Direction Control for SPI_IO 7,6,5 and 4 in case of quad/dual/single mode for chip select1 (cs_n1). It is used both in Auto and Manual Mode. [15:12] read-write QSPI_D7TOD4_DATA_CSN2 Value of SPI_IO7,6,5 and 4 in case of quad/dual/single mode for chip select2 (cs_n2). It is used both in Auto and Manual Mode. [19:16] read-write QSPI_D7TOD4_OEN_CSN2 Direction Control for SPI_IO 7,6,5 and 4 in case of quad/dual/single mode for chip select2 (cs_n2). It is used both in Auto and Manual Mode. [23:20] read-write QSPI_D7TOD4_DATA_CSN3 Value of SPI_IO7,6,5 and 4 in case of quad/dual/single mode for chip select3 (cs_n3). It is used both in Auto and Manual Mode. [27:24] read-write QSPI_D7TOD4_OEN_CSN3 Direction Control for SPI_IO 7,6,5 and 4 in case of quad/dual/single mode for chip select3 (cs_n3). It is used both in Auto and Manual Mode. [31:28] read-write QSPI_AUTO_BASE_ADDR_UNMASK_CSN0 QSPI in Auto Base address mode for unmasking CSN0 Register 0xB4 32 read-write 0xFFFFFFFF QSPI_AUTO_BASE_ADDR_UNMASK_CSN0 Holds the 32 bit base address unmask value for select chip select0 in programmable auto csn mode. It is valid only programmable auto csn mode is enabled. [31:0] read-write QSPI_AUTO_BASE_ADDR_UNMASK_CSN1 QSPI in Auto Base address mode for unmasking CSN1 Register 0xB8 32 read-write 0xFFFFFFFF QSPI_AUTO_BASE_ADDR_UNMASK_CSN1 Holds the 32 bit base address unmask value for select chip select1 in programmable auto csn mode. It is valid only programmable auto csn mode is enabled. [31:0] read-write OCTASPI_BUS_CONTROLLER_2 QSPI Controller2 in OCTA SPI Mode. 0xC4 32 read-write 0x00020000 0xFFFFFFFF SET_IP_MODE This bit enables the qspi interface pins into HiZ mode [0:0] read-write RESERVED1 Reserved1 [1:1] read-write AES_SEC_ENABLE This bit enables the AES security enable or not [2:2] read-write DUAL_MODE_EN Dual flash mode enable control. If two csns are cmnnected with the same kind of flash, QSPI can read data (4bit data each flash) from both the flashes at the same point of time (Not in TDM fashion). If set, both the flashes are accessed at the same point time, otherwise normal operation. [3:3] read-write CSN0_2_CSN Map csn0 to the programmed csn. It is valid for both manual and auto modes [5:4] read-write NOT_VALID Not valid 00 CSN0_TO_CSN1 Map csn0 to csn1. Reads on csn0 will have data from csn1 also 13 CSN0_TO_CSN2 Map csn0 to csn2. Reads on csn0 will have data from csn2 also 14 CSN0_TO_CSN3 Map csn0 to csn3. Reads on csn0 will have data from csn3 also 3 CSN1_2_CSN Map csn1 to the programmed csn. It is valid for both manual and auto modes [7:6] read-write CSN1_TO_CSN0 Map csn1 to csn0. Reads on csn1 will have data from csn1 also 0 NOT_VALID Not valid 11 CSN1_TO_CSN2 Map csn1 to csn2. Reads on csn1 will have data from csn2 also 12 CSN1_TO_CSN3 Map csn1 to csn3. Reads on csn1 will have data from csn3 also 3 CSN2_2_CSN Map csn2 to the programmed csn. It is valid for both manual and auto modes [9:8] read-write CSN2_TO_CSN1 Map csn2 to csn1. Reads on csn2 will have data from csn0 also 0 CSN2_TO_CSN1 Map csn2 to csn1. Reads on csn2 will have data from csn1 also 9 NOT_VALID Not valid 10 CSN2_TO_CSN3 Map csn2 to csn3. Reads on csn2 will have data from csn3 also. 3 CSN3_2_CSN Map csn3 to the programmed csn. It is valid for both manual and auto modes [11:10] read-write CSN3_TO_CSN0 Map csn3 to csn0. Reads on csn3 will have data from csn0 also. 0 CSN3_TO_CSN1 Map csn3 to csn1. Reads on csn3 will have data from csn0 also 7 CSN3_TO_CSN2 Map csn3 to csn2. Reads on csn3 will have data from csn0 also. 8 NOT_VALID Not valid 3 AES_SEC_ENABLE_SG1 This bit enables the AES security enable or not for segment 1 [12:12] read-write AES_SEC_ENABLE_SG2 This bit enables the AES security enable or not for segment 2 [13:13] read-write AES_SEC_ENABLE_SG3 This bit enables the AES security enable or not for segment 3 [14:14] read-write AES_SEC_ENABLE_SG4 This bit enables the AES security enable or not for segment 4 [15:15] read-write DUAL_MODE_SWAP_LINES This bit controls the 8 lines of qspi with 4 bit swap manner. If this is set, upper 4 lines are swapped with lower 4 lines. [16:16] read-write AUTO_MODE_IN_DEFAULT_EN Qspi works in auto mode if set this is bit by default. [17:17] read-write OTP_KEY_LOAD Enable to load key from OTP/KH [18:18] read-write DUAL_STAGE_EN_MANUAL Dual stage en for dual flash mode. It is valid only if dual_mode_en is set to high. This bit be one, while sending command, address, dummy bytes, and etc. It sends same command & address to both flashes. It should be zero while reading or writing data into flash in dual quad flash mode. [19:19] read-write RESERVED2 reserved2 [31:20] read-write QSPI_AES_CONFIG QSPI Controller AES Mode, Key Size and Context switching 0xC8 32 read-write 0x00000000 0xFFFFFFFF QSPI_AES_MODE AES mode of decryption CTR/XTS 0x80 - XTS 0x04 - CTR others not supported [8:0] read-write QSPI_AES_DECKEYCAL Enables pre-calculation of KEY before decryption operation. Set 1 fot XTS and 0 for CTR In encryption operations, it is 0. 1 not supported. [9:9] read-write Disable use the input key for decryption operations. 0 Enable the pre-calculation of the key (K’=KeyExp(K)) is done before starting any data decryption operation 1 FLIP_KEY_FRM_REG writing 1 to this Flips the 32-bit endian key taken from kh [10:10] read-write FLIP_KEY_FRM_KH writing 1 to this Flips the 32-bit endian key taken from kh [11:11] read-write QSPI_AES_SRST Synchronous soft reset for AES Module. Write only bit. Reading this bit gives alway 0 [12:12] write-only FLIP_LB_DATA writing 1 to this Flips the 32-bit endian for data in standalone mode [13:13] read-write QSPI_AES_LB_DECRYPT QSPI standalone mode [14:14] read-write Disable Enables encryption mode in standalone mode 0 Enable Enables decryption mode in standalone mode 1 QSPI_AES_LB_MODE_EN QSPI AES LB mode (Standalone mode ) enable. [15:15] read-write Disable Inline mode 0 Enable Standalone mode 1 KEY_SIZE QSPI key size [16:16] read-write Disable 124 bit key 0 Enable 256 bit key 1 RESERVED1 reserved1 [31:17] read-write QSPI_AES_KEY_IV_VALID QSPI Controller AES write Enables for Keys and IVs 0xCC 32 read-write 0x00000000 0xFFFFFFFF QSPI_AES_KEY1_VALID Write enables for AES KEY 1. Denotes which bytes of key1 is valid [7:0] read-write QSPI_AES_LB_IV_VALID Write enables for AES IV1 in standalone mode. Denotes which bytes of IV1 is valid. [11:8] read-write QSPI_AES_KEY2_VALID Write enables for AES KEY 2. Denotes which bytes of key2 is valid [19:12] read-write RESERVED1 Reserved1 [31:20] read-write QSPI_CMNFLASH_STS QSPI Status in Common flash modes 0xD0 32 read-only 0x00000000 0xFFFFFFFF QSPI_MANUAL_BLOCKED QSPI manual transactions [0:0] read-only Disable No manual transactions 0 Enable Manual read/write transaction initiated is blocked. 1 AUTO_READ_OUT_RANGE Auto read transaction of address [1:1] read-only Disable Auto read transaction is in Address range 0 Enable Auto read transaction is out of M4 Address range 1 QSPI_AUTO_RD_BUSY Auto read transactions [2:2] read-only Disable No Auto read transactions 0 Enable Auto read transactions in progress. 1 RESERVED1 reserved1 [31:3] read-only QSPI_AES_LB_DATA_0_3 QSPI AES in LB (Standalone mode ) for [31:0] 0xD4 32 read-write 0x00000000 0xFFFFFFFF QSPI_AES_LB_DIN_0_3 write 3-0 bytes of aes standalone mode input data as 0 referred as lsb in the data in [31:0] write-only QSPI_AES_LB_DOUT_0_3 read 3-0 bytes of aes standalone mode output data as 0 referred as lsb in the data out Inline mode input data is loop back as out data [31:0] read-only QSPI_AES_LB_DATA_4_7 QSPI AES in LB (Standalone mode ) for [63:32] 0xD8 32 read-writeOnce 0x00000000 0xFFFFFFFF QSPI_AES_LB_DIN_4_7 write 7-4 bytes of aes standalone mode input data as 0 referred as lsb in the data in [31:0] write-only QSPI_AES_LB_DOUT_4_7 read 7-4 bytes of aes standalone mode output data as 0 referred as lsb in the data out Inline mode input data is loop back as out data [31:0] read-only QSPI_AES_LB_DATA_8_B QSPI AES in LB (Standalone mode ) for [95:64] 0xDC 32 read-writeOnce 0x00000000 0xFFFFFFFF QSPI_AES_LB_DIN_8_B write 11-8 bytes of aes standalone mode input data as 0 referred as lsb in the data in [31:0] write-only QSPI_AES_LB_DOUT_8_B read 11-8 bytes of aes standalone mode output data as 0 referred as lsb in the data out Inline mode input data is loop back as out data [31:0] read-only QSPI_AES_LB_DATA_C_F QSPI AES in LB (Standalone mode ) for [127:96] 0xE0 32 read-writeOnce 0x00000000 0xFFFFFFFF QSPI_AES_LB_DIN_C_F write 15-12 bytes of aes standalone mode input data as 0 referred as lsb in the data in [31:0] write-only QSPI_AES_LB_DOUT_C_F read 15-12 bytes of aes standalone mode output data as 0 referred as lsb in the data out Inline mode input data is loop back as out data [31:0] read-only QSPI_AES_SEC_SEG_LS_ADDR_1 QSPI Controller AES lower boundary address of 1st segment 0xE4 32 read-write 0x00000000 0xFFFFFFFF QSPI_AES_SEC_SEG_LS_ADDR_1 This register specifies the lower boundary address of 1st segment [31:0] read-write QSPI_AES_SEC_SEG_MS_ADDR_1 QSPI Controller AES upper boundary address of 1st segment 0xE8 32 read-write 0x00000000 0xFFFFFFFF QSPI_AES_SEC_SEG_MS_ADDR_1 This register specifies the upper boundary address of 1st segment [31:0] read-write QSPI_AES_SEC_SEG_LS_ADDR_2 QSPI Controller AES lower boundary address of 2nd segment 0xEC 32 read-write 0x00000000 0xFFFFFFFF QSPI_AES_SEC_SEG_LS_ADDR_2 This register specifies the lower boundary address of 2nd segment [31:0] read-write QSPI_AES_SEC_SEG_MS_ADDR_2 QSPI Controller AES upper boundary address of 2nd segment 0xF0 32 read-write 0x00000000 0xFFFFFFFF QSPI_AES_SEC_SEG_MS_ADDR_2 This register specifies the upper boundary address of 2nd segment [31:0] read-write QSPI_AES_SEC_SEG_LS_ADDR_3 QSPI Controller AES lower boundary address of 3rd segment 0xF4 32 read-write 0x00000000 0xFFFFFFFF QSPI_AES_SEC_SEG_LS_ADDR_3 This register specifies the lower boundary address of 3rd segment [31:0] read-write QSPI_AES_SEC_SEG_MS_ADDR_3 QSPI Controller AES upper boundary address of 3rd segment 0xF8 32 read-write 0x00000000 0xFFFFFFFF QSPI_AES_SEC_SEG_MS_ADDR_3 This register specifies the upper boundary address of 3rd segment [31:0] read-write QSPI_AES_SEC_SEG_LS_ADDR_4 QSPI Controller AES lower boundary address of 4th segment 0xFC 32 read-write 0x00000000 0xFFFFFFFF QSPI_AES_SEC_SEG_LS_ADDR_4 This register specifies the lower boundary address of 4th segment [31:0] read-write QSPI_AES_SEC_SEG_MS_ADDR_4 QSPI Controller AES upper boundary address of 4th segment 0x100 32 read-write 0x00000000 0xFFFFFFFF QSPI_AES_SEC_SEG_MS_ADDR_4 This register specifies the upper boundary address of 4th segment [31:0] read-write QSPI_SRAM_CTRL_CSN0_REG SRAM CTRL register of the QSPI Controller CSN0 register 0x104 32 read-write 0x00004000 0xFFFFFFFF BIT_8_MODE Flash 8bit (1 byte) boundary mode. [0:0] read-write Disable Flash is not with 8bit (1 byte) boundary. 0 Enable Flash is with 8bit (1 byte) boundary. 23 BIT_32_MODE Flash 32 byte boundary mode. [1:1] read-write Disable Flash is not with 32 byte boundary. 0 Enable Flash is with 32 byte boundary. 22 ADDR_16BIT_MODE Send only lower 16bits of Address enable. [2:2] read-write Disable 24 address bit flash is connected. 0 Enable 16 address bit flash is connected. 21 RESERVED1 Reserved1 [7:3] read-write CMD_MODE writing cmd mode [9:8] read-write Single SPI Single SPI 0 Dual SPI Dual SPI 19 Quad SPI Quad SPI 20 OCTA SPI OCTA SPI 3 ADDR_MODE writing address mode [11:10] read-write Single SPI Single SPI 0 Dual SPI Dual SPI 17 Quad SPI Quad SPI 18 OCTA SPI OCTA SPI 3 DATA_MODE writing data mode [13:12] read-write Single SPI Single SPI 0 Dual SPI Dual SPI 15 Quad SPI Quad SPI 16 OCTA SPI OCTA SPI 3 WR_DATA_SWAP writing data swap [14:14] read-write Disable WR DATA is not swapped 0 Enable WR DATA is swapped 1 RESERVED2 Reserved2 [15:15] read-write WR_CMD Command to be used for writing. [23:16] read-write RESERVED3 Reserved3 [31:24] read-write QSPI_SRAM_CTRL_CSN1_REG SRAM CTRL register of the QSPI Controller CSN1 register 0x108 32 read-write 0x00004000 0xFFFFFFFF BIT_8_MODE Flash 8bit (1 byte) boundary mode. [0:0] read-write Disable Flash is not with 8bit (1 byte) boundary. 0 Enable Flash is with 8bit (1 byte) boundary. 23 BIT_32_MODE Flash 32 byte boundary mode. [1:1] read-write Disable Flash is not with 32 byte boundary. 0 Enable Flash is with 32 byte boundary. 22 ADDR_16BIT_MODE Send only lower 16bits of Address enable. [2:2] read-write Disable 24 address bit flash is connected. 0 Enable 16 address bit flash is connected. 21 RESERVED1 Reserved1 [7:3] read-write CMD_MODE writing cmd mode [9:8] read-write Single SPI Single SPI 0 Dual SPI Dual SPI 19 Quad SPI Quad SPI 20 OCTA SPI OCTA SPI 3 ADDR_MODE writing address mode [11:10] read-write Single SPI Single SPI 0 Dual SPI Dual SPI 17 Quad SPI Quad SPI 18 OCTA SPI OCTA SPI 3 DATA_MODE writing data mode [13:12] read-write Single SPI Single SPI 0 Dual SPI Dual SPI 15 Quad SPI Quad SPI 16 OCTA SPI OCTA SPI 3 WR_DATA_SWAP writing data swap [14:14] read-write Disable WR DATA is not swapped 0 Enable WR DATA is swapped 1 RESERVED2 Reserved2 [15:15] read-write WR_CMD Command to be used for writing. [23:16] read-write RESERVED3 Reserved3 [31:24] read-write SEMI_AUTO_MODE_ADDR_REG QSPI Controller in SEMI AUTO mode for address 0x11C 32 read-write 0x00000000 0xFFFFFFFF SEMI_AUTO_MODE_ADDR Byte address to read the data from flash in semi auto mode. It is valid only semi auto mode enable bit is asserted. [31:0] read-write SEMI_AUTO_MODE_CONFIG_REG QSPI Controller in SEMI AUTO mode for Configuration 0x120 32 read-write 0x00000210 0xFFFFFFFF QSPI_SEMI_AUTO_BSIZE This is burst size to read data from flash in semi auto mode. To get burst size in bytes, consider qspi_semi_auto_hsize also. qspi_semi_auto_bsize is non-zero value. 0x00 is not supported and invalid. [5:0] read-write B_SIZE qspi_semi_auto_bsize 4 H_SIZE qspi_semi_auto_hsize 2 RESERVED1 Reserved1 [7:6] read-write QSPI_SEMI_AUTO_HSIZE Indicates number of bytes valid in each transaction.24bytes mode is not supported because this hsize to be similar to ahb ahb hsize signal. It is valid only semi auto mode enable bit is asserted. [9:8] read-write 1_BYTE 1 byte valid 0 2_BYTES 2 bytes valid 1 4_BYTES 4 bytes valid 2 Reserved Reserved 3 RESERVED2 Reserved2 [31:10] read-write SEMI_AUTO_MODE_CONFIG2_REG QSPI Controller in SEMI AUTO mode for Configuration 2 0x124 32 read-write 0x00000000 0xFFFFFFFF QSPI_SEMI_AUTO_RD_CNT Total number of bytes to be read flash continuously from the address given by SEMI_AUTO_MODE_ADDR_REG. After reading complete data according to this count, qspi_semi_auto_rd_busy is de-asserted. [11:0] read-write QSPI_SEMI_AUTO_MODE_EN Enable for semi auto mode read operation. Make sure manual mode read/write operation is completed before asserting this bit. Either manual mode or semi auto mode will work at a time. Don’t start any manual mode operation when this bit is asserted. Qspi_auto_mode and semi_auto_mode share qspi bus bandwidth and work simultaneously. [12:12] read-write QSPI_SEMI_AUTO_RD_BUSY Indicates status of semi auto mode read status. If it is high, semi auto mode read operation is progressing. It is It is valid only semi auto mode enable bit is asserted. [13:13] read-only RESERVED1 Reserved1 [31:14] read-write QSPI_BUS_MODE2_REG QSPI Controller Bus in mode2. 0x128 32 read-write 0x00000000 0xFFFFFFFF PREFETCH_ENBLD_MSTR_ID Holds the programmable prefetch enabled AHB master ID. This is commonly used for enabling prefetch for icache master. [3:0] read-write PREFETCH_EN_FOR_ICACHE_MSTR Prefetch enable for icache AHB master. [4:4] read-write RESERVED1 Reserved1 [7:5] read-write QSPI_PREFETCH_ENBLD_TRANS_BYTES Programmable prefetch enabled AHB master transfer bytes. Assume this is used for icache and dma ahb master access in auto mode. [15:8] read-write RESERVED2 Reserved2 [31:16] read-write QSPI_AES_SEC_KEY_FRM_KH_REG QSPI Controller AES SEC KEY FRM_KH mode. 0x12C 32 read-write 0x00000012 0xFFFFFFFF START_LOADING_SEC_KEY_FRM_KH Start Security key loading from KH. It self-clear bit. After setting the key loading bit, wait for de-assertion of this bit. Hardware resets this bit after key loading done. [0:0] write-only LOADING_SEC_KEY_FRM_KH Indicates security key loading status from KH [0:0] read-only SEC_KEY_READING_INTERVAL Security key reading interval KH key reading will happened at this rate, which is soc clock divided by this value. default reading rate is soc clock divided by 10. [4:1] read-write RESERVED1 Reserved1 [31:5] read-write QSPI_AUTO_CONITNUE_FETCH_CTRL_REG QSPI Controller in Auto Continue Fetch mode. 0x130 32 read-write 0x00000010 0xFFFFFFFF CONTINUE_FETCH_WAIT_TIMEOUT_VALUE_FRM_REG Maximum Continue fetch wait time between two qspi auto reads. After this time out, qspi auto controller will deassert the CSN. [11:0] read-write CONTINUE_FETCH_EN Continue fetch feature enable. If this mode is enabled & consecutive address is issued, It will continue reading of data in auto mode without de-asserting CSN. It saves command, address and dummy cycles phases. It has timeout option also. If consecutive address is given in the programmable specified time or non consecutive address is given, it deassert the CSN. It is valid only for auto mode. Disable this bit before any manual mode transactions. It is taken care automatically by qspi controller in hardware controlled auto mode. If continuous mode is enable, clock ratio between qspi clock and soc clock should 2:1, 1:1, 1:2, 1:3, .. 1:x. [12:12] read-write RESERVED1 Reserved1 [31:13] read-write QSPI_AES_KEY1_0_3 QSPI Controller AES KEY1 from 0 to 3 bytes 0x134 32 read-write 0x00000000 0xFFFFFFFF QSPI_AES_KEY1_0_3 To hold first 3-0 bytes of aes key1 as 0 referred as lsb in the key [31:0] read-write QSPI_AES_KEY1_4_7 QSPI Controller AES KEY1 from 4 to 7 bytes 0x138 32 read-write 0x00000000 0xFFFFFFFF QSPI_AES_KEY1_4_7 To hold first 7-4 bytes of aes key1 as 0 referred as lsb [31:0] read-write QSPI_AES_KEY1_8_B QSPI Controller AES KEY1 from 8 to B bytes 0x13C 32 read-write 0x00000000 0xFFFFFFFF QSPI_AES_KEY1_8_B To hold first 11-8 bytes of aes key1 as 0 referred as lsb [31:0] read-write QSPI_AES_KEY1_C_F QSPI Controller AES KEY1 from C to F bytes 0x140 32 read-write 0x00000000 0xFFFFFFFF QSPI_AES_KEY1_C_F To hold first 11-8 bytes of aes key1 as 0 referred as lsb [31:0] read-write QSPI_AES_KEY1_10_13 QSPI Controller AES KEY1 from 10 to 13 bytes 0x144 32 read-write 0x00000000 0xFFFFFFFF QSPI_AES_KEY1_10_13 To hold first 19-16 bytes of aes key1 as 0 referred as lsb in the key [31:0] read-write QSPI_AES_KEY1_14_17 QSPI Controller AES KEY1 from 14 to 17 bytes 0x148 32 read-write 0x00000000 0xFFFFFFFF QSPI_AES_KEY1_14_17 To hold first 23-20 bytes of aes key1 as 0 referred as lsb [31:0] read-write QSPI_AES_KEY1_18_1B QSPI Controller AES KEY1 from 18 to 1B bytes 0x14C 32 read-write 0x00000000 0xFFFFFFFF QSPI_AES_KEY1_18_1B To hold first 27-24 bytes of aes key1 as 0 referred as lsb [31:0] read-write QSPI_AES_KEY1_1C_1F QSPI Controller AES KEY1 from 1C to 1F bytes 0x150 32 read-write 0x00000000 0xFFFFFFFF QSPI_AES_KEY1_1C_1F To hold first 31-28 bytes of aes key1 as 0 referred as lsb [31:0] read-write QSPI_AES_KEY2_0_3 QSPI Controller AES KEY2 from 0 to 3 bytes 0x154 32 read-write 0x00000000 0xFFFFFFFF QSPI_AES_KEY2_0_3 To hold first 3-0 bytes of aes key2 as 0 referred as lsb in the key [31:0] read-write QSPI_AES_KEY2_4_7 QSPI Controller AES KEY2 from 4 to 7 bytes 0x158 32 read-write 0x00000000 0xFFFFFFFF QSPI_AES_KEY2_4_7 To hold first 7-4 bytes of aes key2 as 0 referred as lsb [31:0] read-write QSPI_AES_KEY2_8_B QSPI Controller AES KEY2 from 8 to B bytes 0x15C 32 read-write 0x00000000 0xFFFFFFFF QSPI_AES_KEY2_8_B To hold first 11-8 bytes of aes key2 as 0 referred as lsb [31:0] read-write QSPI_AES_KEY2_C_F QSPI Controller AES KEY2 from C to F bytes 0x160 32 read-write 0x00000000 0xFFFFFFFF QSPI_AES_KEY2_C_F To hold first 15-12 bytes of aes key2 as 0 referred as lsb [31:0] read-write QSPI_AES_KEY2_10_13 QSPI Controller AES KEY2 from 10 to 13 bytes 0x164 32 read-write 0x00000000 0xFFFFFFFF QSPI_AES_KEY2_10_13 To hold first 19-16 bytes of aes KEY2 as 0 referred as lsb in the key [31:0] read-write QSPI_AES_KEY2_14_17 QSPI Controller AES KEY2 from 14 to 17 bytes 0x168 32 read-write 0x00000000 0xFFFFFFFF QSPI_AES_KEY2_14_17 To hold first 23-20 bytes of aes KEY2 as 0 referred as lsb [31:0] read-write QSPI_AES_KEY2_18_1B QSPI Controller AES KEY2 from 18 to 1B bytes 0x16C 32 read-write 0x00000000 0xFFFFFFFF QSPI_AES_KEY2_18_1B To hold first 27-24 bytes of aes KEY2 as 0 referred as lsb [31:0] read-write QSPI_AES_KEY2_1C_1F QSPI Controller AES KEY2 from 1C to 1F bytes 0x170 32 read-write 0x00000000 0xFFFFFFFF QSPI_AES_KEY2_1C_1F To hold first 31-28 bytes of aes KEY2 as 0 referred as lsb [31:0] read-write QSPI_AES_IV1_0_3 QSPI Controller AES IV1 from 0 to 3 bytes in LB mode 0x174 32 read-write 0x00000000 0xFFFFFFFF QSPI_AES_LB_IV To hold first 3-0 bytes of QSPI AES IV1 as 0 referred as lsb in the IV in stadalone mode [31:0] read-write QSPI_AES_IV1_4_7 QSPI Controller AES IV1 from 4 to 7 bytes in LB mode 0x178 32 read-write 0x00000000 0xFFFFFFFF QSPI_AES_LB_IV To hold first 7-4 bytes of QSPI AES IV1 as 0 referred as lsb in the IV in stadalone mode [31:0] read-write QSPI_AES_IV1_8_B QSPI Controller AES IV1 from 8 to B bytes in LB mode 0x17C 32 read-write 0x00000000 0xFFFFFFFF QSPI_AES_LB_IV To hold first B-8 bytes of QSPI AES IV1 as 0 referred as lsb in the IV in stadalone mode [31:0] read-write QSPI_AES_IV1_C_F QSPI Controller AES IV1 from 8 to B bytes in LB mode 0x180 32 read-write 0x00000000 0xFFFFFFFF QSPI_AES_LB_IV To hold first F-C bytes of QSPI AES IV1 as F referred as msb in the IV in stadalone mode [31:0] read-write QSPI_AES_LB_STATUS QSPI Controller AES IV1 from 8 to B bytes in LB mode 0x184 32 read-writeOnce 0x00000001 0xFFFFFFFF QSPI_AES_LB_DOUT_READY Denotes the firmware is ready to read to output data. [0:0] read-write AES_LB_DOUT_VALID Denotes validity of out data of QSPI AES in loop back mode [1:1] read-only QSPI_AES_LB_DIN_READY Denotes ready status of QSPI AES in loop back mode [2:2] read-only QSPI_AES_LB_BUSY Denotes busy status of QSPI AES in loop back mode [3:3] read-only RESERVED1 Reserved1 [7:4] read-write QSPI_AES_LB_INVALID_BYTES Denotes number of invalid bytes in data input in loop back mode. [12:8] read-write RESERVED2 Reserved2 [31:13] read-write Low_Power_Domain 1.0 The use of this is to store some information in ULP over wake-ups to reduce wake-up time Low_Power_Domain 0x24048400 32 read-write 0x00 0x100 registers ULPSS_PWRCTRL_SET_REG ULPSS power control set register 0x44 32 read-write 0x0fec0000 RESERVED1 reserved1 [17:0] read-write PWRGATE_EN_N_ULP_MISC Enables power to the MISC. [18:18] read-write Disable This has no effect. 0 Enable This enables power to the MISC. 1 PWRGATE_EN_N_ULP_CAP Enables power to the ULPSS CAP [19:19] read-write Disable This has no effect. 0 Enable this enables power to the ULPSS CAP. 1 RESERVED2 reserved2 [20:20] read-write PWRCTRL_UART Enables power to the UART [21:21] read-write Disable This has no effect. 0 Enable this enables power to the UART. 1 PWRCTRL_SSI Enables power to the SPI/SSI [22:22] read-write Disable This has no effect. 0 Enable this enables power to the SPI/SSI. 1 PWRCTRL_I2S Enables power to the I2S [23:23] read-write Disable This has no effect. 0 Enable this enables power to the I2S. 1 PWRCTRL_I2C Enables power to the I2C [24:24] read-write Disable This has no effect. 0 Enable this enables power to the I2C. 1 PWRCTRL_ADC_DAC Enables power to the ADC/DAC [25:25] read-write Disable This has no effect. 0 Enable this enables power to the ADC/DAC. 1 PWRCTRL_IR Enables power to the IR [26:26] read-write Disable This has no effect. 0 Enable this enables power to the IR. 1 PWRCTRL_DMA Enables power to the DMA [27:27] read-write Disable This has no effect. 0 Enable this enables power to the DMA 1 RESERVED3 RESERVED3 [31:28] read-write ULPSS_PWRCTRL_CLEAR_REG ULPSS power control clear register 0x48 32 read-write 0x0fec0000 RESERVED1 reserved1 [17:0] read-write PWRGATE_EN_N_ULP_MISC Disables power to the MISC. [18:18] read-write Disable This has no effect. 0 Enable This disables power to the MISC 1 PWRGATE_EN_N_ULP_CAP Disables power to the ULPSS CAP. [19:19] read-write Disable This has no effect. 0 Enable This disables power to the ULPSS CAP 1 RESERVED2 reserved2 [20:20] read-write PWRCTRL_UART Disables power to the UART [21:21] read-write Disable This has no effect. 0 Enable This disables power to the UART 1 PWRCTRL_SSI Disables power to the SPI/SSI [22:22] read-write Disable This has no effect. 0 Enable This disables power to the SPI/SSI 1 PWRCTRL_I2S Disables power to the I2S [23:23] read-write Disable This has no effect. 0 Enable This disables power to the I2S 1 PWRCTRL_I2C Disables power to the I2C [24:24] read-write Disable This has no effect. 0 Enable This disables power to the I2C 1 PWRCTRL_ADC_DAC Disables power to the ADC/DAC [25:25] read-write Disable This has no effect. 0 Enable This disables power to the ADC/DAC 1 PWRCTRL_IR Disables power to the IR [26:26] read-write Disable This has no effect. 0 Enable This disables power to the IR 1 PWRCTRL_DMA Disables power to the DMA [27:27] read-write Disable This has no effect. 0 Enable This disables power to the DMA 1 RESERVED3 RESERVED3 [31:28] read-write ULPSS_RAM_PWRCTRL_SET_REG1 ULPSS ram power control set register1 0x4C 32 read-write 0x0000000F PWRCTRL1_ULP_SRAM Enables power to the ULP SRAM. [3:0] read-write Disable This has no effect. 0 Enable this enables power to ULP-SRAM 1 RESERVED1 reserved1 [31:4] read-write ULPSS_RAM_PWRCTRL_CLEAR_REG1 ULPSS ram power control clear register1 0x50 32 read-write 0x0000000F PWRCTRL1_ULP_SRAM Disables power to the ULP SRAM. [3:0] read-write Disable This has no effect. 0 Enable this disables power to the ULP-SRAM 1 RESERVED1 reserved1 [31:4] read-write ULPSS_RAM_PWRCTRL_SET_REG2 ULPSS ram power control set register2 0x54 32 read-write 0x0000000F INP_ISO_SRAM Input isolation control for ULPTASS SRAM [3:0] read-write Disable This has no effect. 0 Enable This enables isolation to ULPTASS SRAM. 1 RESERVED1 reserved1 [15:4] read-write DS_ULPSRAM__PROC_1 Deep-Sleep control for ULPTASS SRAM [19:16] read-write Disable This has no effect. 0 Enable This enables deep sleep mode ULPTASS SRAM. 1 RESERVED2 reserved2 [31:20] read-write ULPSS_RAM_PWRCTRL_CLEAR_REG2 ULPSS ram power control clear register2 0x58 32 read-write 0x0000000F INP_ISO_SRAM Input isolation control for ULPTASS SRAM [3:0] read-write Disable This has no effect. 0 Enable This disables isolation to ULPTASS SRAM. 1 RESERVED1 reserved1 [15:4] read-write DS_ULPSRAM__PROC_1 Deep-Sleep control for ULPTASS SRAM [19:16] read-write Disable This has no effect. 0 Enable This disables deep sleep mode ULPTASS SRAM. 1 RESERVED2 reserved2 [31:20] read-write ULPSS_RAM_PWRCTRL_SET_REG3 ULPSS ram power control set register3 0x5C 32 read-write 0x0000000F PWRCTRL_ULPTASS_SRAM_PERI_1 Power Control signal for ULPTASS SRAM Dual Rail pins [3:0] read-write Disable This has no effect. 0 Enable This enables power to ULPTASS SRAM dual rail pins 1 RESERVED1 reserved1 [31:4] read-write ULPSS_RAM_PWRCTRL_CLEAR_REG3 ULPSS ram power control clear register3 0x60 32 read-write 0x0000000F PWRCTRL_ULPTASS_SRAM_PERI_1 Power Control signal for ULPTASS SRAM Dual Rail pins [3:0] read-write Disable This has no effect. 0 Enable This disables power to ULPTASS SRAM dual rail pins 1 RESERVED1 reserved1 [31:4] read-write