/* Copyright (c) 2019 Alibaba Group Holding Limited Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ `define PRODUCT_ID 16'h0000 `define RESET_VAL 16'hABCD `define GATED_CELL `define SMIC `define PROCESS55LL `ifdef USER_MODE `define MACHINE_SP `endif `define CLIC_MODE `ifdef CSKY_TEE `define USER_MODE `define MACHINE_SP `endif `define GPR_16 `define VEC_BASE `define LOAD_FAST_RETIRE `define WB_LOAD_FWD_TO_EX `define MAD_SMALL `define IAHB_LITE `ifdef IAHB_LITE `define IBUS_32 `endif `ifdef DAHB_LITE `define DBUS_32 `endif `define SYS_AHB_LITE `define BIU_32 `ifdef FLOP_OUT_BIU `define FLOP_OUT_BUS `else `ifdef FLOP_OUT_IBUS `define FLOP_OUT_BUS `else `ifdef FLOP_OUT_DBUS `define FLOP_OUT_BUS `else `endif `endif `endif `ifdef IAHB_LITE `endif `ifdef PMP `define PMP_REGION_16 `endif `ifdef PMP_REGION_2 `define REGION_ENTRY0 `define REGION_ENTRY1 `endif `ifdef PMP_REGION_4 `define REGION_ENTRY0 `define REGION_ENTRY1 `define REGION_ENTRY2 `define REGION_ENTRY3 `endif `ifdef PMP_REGION_8 `define REGION_ENTRY0 `define REGION_ENTRY1 `define REGION_ENTRY2 `define REGION_ENTRY3 `define REGION_ENTRY4 `define REGION_ENTRY5 `define REGION_ENTRY6 `define REGION_ENTRY7 `endif `ifdef PMP_REGION_16 `define REGION_ENTRY0 `define REGION_ENTRY1 `define REGION_ENTRY2 `define REGION_ENTRY3 `define REGION_ENTRY4 `define REGION_ENTRY5 `define REGION_ENTRY6 `define REGION_ENTRY7 `define REGION_ENTRY8 `define REGION_ENTRY9 `define REGION_ENTRY10 `define REGION_ENTRY11 `define REGION_ENTRY12 `define REGION_ENTRY13 `define REGION_ENTRY14 `define REGION_ENTRY15 `endif `define TCIPIF `ifdef TCIPIF `define CTIM `ifdef CLIC_MODE `define CLIC `endif `endif `ifdef CLIC `define CLICINTBITS_3 `define INT_NUM_64 `endif `ifdef SEU `define SEU_VERIFY_PARITY `define SEU_FIX_BRANCH `define SEU_HARDWARE_RANDOM_INSTRUCTION_INSERTION `define SEU_GPR_CHECK `define SEU_PC_CHECK `define SEU_BUS_PARITY `endif `ifdef SEU_VERIFY_PARITY `define SEU_VB_WIDTH 1 `define SEU_VB_RESET_00000000 1'b0 `define SEU_VB_RESET_80000000 1'b1 `endif `ifdef SEU_VERIFY_HAMMING `define SEU_VB_WIDTH 6 `define SEU_VB_RESET_00000000 6'b0 `define SEU_VB_RESET_80000000 6'b100110 `endif `ifdef INT_NUM_8 `define VIC_IPR1 `endif `ifdef INT_NUM_16 `define VIC_IPR1 `define VIC_IPR3 `endif `ifdef INT_NUM_24 `define VIC_IPR1 `define VIC_IPR3 `define VIC_IPR5 `endif `ifdef INT_NUM_32 `define VIC_IPR1 `define VIC_IPR3 `define VIC_IPR5 `define VIC_IPR7 `endif `ifdef INT_NUM_64 `define VIC_IPR64 `endif `ifdef INT_NUM_96 `define VIC_IPR64 `define VIC_IPR96 `endif `ifdef INT_NUM_128 `define VIC_IPR64 `define VIC_IPR96 `define VIC_IPR128 `endif `ifdef CACHE `define CACHE_8K `endif `ifdef CACHE `define CACHE_2WAY `endif `ifdef CACHE `define CACHE_LINE_16B `endif `ifdef CACHE `define CACHE_REGION_2 `endif `ifdef CACHE_REGION_4 `define REGION_REG3 `define REGION_REG2 `define REGION_REG1 `define REGION_REG0 `endif `ifdef CACHE_REGION_3 `define REGION_REG2 `define REGION_REG1 `define REGION_REG0 `endif `ifdef CACHE_REGION_2 `define REGION_REG1 `define REGION_REG0 `endif `ifdef CACHE_REGION_1 `define REGION_REG0 `endif `ifdef CACHE `endif `ifdef CACHE `endif `ifdef CACHE `endif `define HAD_IM `ifdef HAD_IM `define HAD_JTAG_2 `define HAD_MBKPTB `ifdef HAD_MBKPTB // `define HAD_MBKPT_9 `endif `ifdef TCIPIF //`define DBG_EXP `endif `endif `define NO_PRE_DECODE module cr_ahbl_if( ahbLif_ahbl_haddr, ahbLif_ahbl_hburst, ahbLif_ahbl_hprot, ahbLif_ahbl_hsize, ahbLif_ahbl_htrans, ahbLif_ahbl_hwdata, ahbLif_ahbl_hwrite, ahbLif_ahbl_vec_redrct, ahbl_ahbLif_hrdata, ahbl_ahbLif_hready, ahbl_ahbLif_hresp, ahbl_clk_en, ahbl_gated_clk, ahblif_busy, ahblif_idle, ahblif_power_mask, cpu_acc_err, cpu_addr, cpu_data_vld, cpu_prot, cpu_rdata, cpu_req, cpu_req_grnt, cpu_req_power_masked, cpu_sec, cpu_size, cpu_trans_cmplt, cpu_vec_redirect, cpu_wdata_sel, cpu_wr_data, cpu_write, cpurst_b, pad_cpu_halt_ff2 ); input [31:0] ahbl_ahbLif_hrdata; input ahbl_ahbLif_hready; input ahbl_ahbLif_hresp; input ahbl_gated_clk; input ahblif_power_mask; input [31:0] cpu_addr; input [3 :0] cpu_prot; input cpu_req; input cpu_req_power_masked; input [1 :0] cpu_size; input cpu_vec_redirect; input [31:0] cpu_wr_data; input cpu_write; input cpurst_b; input pad_cpu_halt_ff2; output [31:0] ahbLif_ahbl_haddr; output [2 :0] ahbLif_ahbl_hburst; output [3 :0] ahbLif_ahbl_hprot; output [2 :0] ahbLif_ahbl_hsize; output [1 :0] ahbLif_ahbl_htrans; output [31:0] ahbLif_ahbl_hwdata; output ahbLif_ahbl_hwrite; output ahbLif_ahbl_vec_redrct; output ahbl_clk_en; output ahblif_busy; output ahblif_idle; output cpu_acc_err; output cpu_data_vld; output [31:0] cpu_rdata; output cpu_req_grnt; output cpu_sec; output cpu_trans_cmplt; output cpu_wdata_sel; reg [2 :0] ahbLif_cur_state; reg [2 :0] ahbLif_nxt_state; reg buf_write; wire acc_err; wire [31:0] ahbLif_ahbl_haddr; wire [2 :0] ahbLif_ahbl_hburst; wire [3 :0] ahbLif_ahbl_hprot; wire [2 :0] ahbLif_ahbl_hsize; wire [1 :0] ahbLif_ahbl_htrans; wire [31:0] ahbLif_ahbl_hwdata; wire ahbLif_ahbl_hwrite; wire ahbLif_ahbl_vec_redrct; wire [31:0] ahbl_ahbLif_hrdata; wire ahbl_ahbLif_hready; wire ahbl_ahbLif_hresp; wire ahbl_ahbLif_hsec; wire ahbl_clk_en; wire ahbl_gated_clk; wire ahblif_busy; wire ahblif_idle; wire ahblif_power_mask; wire [31:0] bus_rdata; wire bus_ready; wire bus_resp; wire bus_sec; wire cpu_acc_err; wire [31:0] cpu_addr; wire cpu_data_vld; wire [3 :0] cpu_prot; wire [31:0] cpu_rdata; wire cpu_req; wire cpu_req_grnt; wire cpu_req_power_masked; wire cpu_sec; wire [1 :0] cpu_size; wire cpu_trans_cmplt; wire cpu_vec_redirect; wire cpu_wdata_sel; wire [31:0] cpu_wr_data; wire cpu_write; wire cpurst_b; wire data_vld; wire [31:0] hwdata; wire pad_cpu_halt_ff2; wire req_grnt; wire trans_cmplt; parameter DATA_WIDTH = 32; parameter IDLE = 3'b000, WFD = 3'b001, WFG = 3'b010, ERROR1 = 3'b110, ERROR2 = 3'b111; always@(posedge ahbl_gated_clk or negedge cpurst_b) begin if(!cpurst_b) ahbLif_cur_state[2:0] <= IDLE; else begin ahbLif_cur_state[2:0] <= ahbLif_nxt_state[2:0]; end end always @( cpu_req_power_masked or bus_ready or ahbLif_cur_state or cpu_req or bus_resp or pad_cpu_halt_ff2) begin case(ahbLif_cur_state) IDLE: begin if(cpu_req_power_masked && !pad_cpu_halt_ff2) if(bus_ready) ahbLif_nxt_state = WFD; else ahbLif_nxt_state = WFG; else ahbLif_nxt_state = IDLE; end WFG: begin if(cpu_req) if(bus_ready) ahbLif_nxt_state = WFD; else ahbLif_nxt_state = WFG; else ahbLif_nxt_state = IDLE; end WFD: begin if(bus_resp) ahbLif_nxt_state = ERROR1; else if(!bus_ready) ahbLif_nxt_state = WFD; else begin if(cpu_req) ahbLif_nxt_state = WFD; else ahbLif_nxt_state = IDLE; end end ERROR1: begin if(bus_resp) if(!bus_ready) ahbLif_nxt_state = ERROR1; else ahbLif_nxt_state = ERROR2; else ahbLif_nxt_state = ERROR2; end ERROR2: begin ahbLif_nxt_state = IDLE; end default: ahbLif_nxt_state = IDLE; endcase end always @( posedge ahbl_gated_clk or negedge cpurst_b) begin if(!cpurst_b) buf_write <= 1'b0; else if(cpu_req && req_grnt) buf_write <= cpu_write; end assign cpu_wdata_sel = buf_write; assign req_grnt = ((ahbLif_cur_state[2:0]==IDLE && !ahblif_power_mask && !pad_cpu_halt_ff2) || ahbLif_cur_state[2:0]==WFG || ahbLif_cur_state[2:0]==WFD) && bus_ready && !bus_resp; assign trans_cmplt = (ahbLif_cur_state[2:0]==WFD) && bus_ready && !bus_resp || (ahbLif_cur_state[2:0]==ERROR2); assign data_vld = (ahbLif_cur_state[2:0]==WFD) && !buf_write && bus_ready && !bus_resp; assign acc_err = (ahbLif_cur_state[2:0]==ERROR2); assign bus_ready = ahbl_ahbLif_hready; assign bus_resp = ahbl_ahbLif_hresp; assign bus_rdata[DATA_WIDTH-1:0] = ahbl_ahbLif_hrdata[DATA_WIDTH-1:0]; assign ahbl_ahbLif_hsec = 1'b0; assign bus_sec = ahbl_ahbLif_hsec; assign ahbLif_ahbl_haddr[31:0] = cpu_addr[31:0]; assign hwdata[DATA_WIDTH-1:0] = cpu_wr_data[DATA_WIDTH-1:0]; assign ahbLif_ahbl_hwdata[DATA_WIDTH-1:0] = hwdata[DATA_WIDTH-1:0]; assign ahbLif_ahbl_htrans[1] = ahbLif_cur_state[2:0]==IDLE && !pad_cpu_halt_ff2 && cpu_req_power_masked || (ahbLif_cur_state[2:0]==WFG || ahbLif_cur_state[2:0]==WFD) && cpu_req; assign ahbLif_ahbl_htrans[0] = 1'b0; assign ahbLif_ahbl_hwrite = cpu_write; assign ahbLif_ahbl_hsize[2:0] = { 1'b0, cpu_size[1:0]}; assign ahbLif_ahbl_hprot[3:0] = cpu_prot[3:0]; assign ahbLif_ahbl_hburst[2:0] = 3'b0; assign ahbLif_ahbl_vec_redrct = cpu_vec_redirect; assign cpu_req_grnt = req_grnt; assign cpu_trans_cmplt = trans_cmplt; assign cpu_data_vld = data_vld; assign cpu_rdata[DATA_WIDTH-1:0] = bus_rdata[DATA_WIDTH-1:0]; assign cpu_acc_err = acc_err; assign cpu_sec = bus_sec; assign ahbl_clk_en = !(ahbLif_cur_state[2:0]==IDLE) || cpu_req; assign ahblif_busy = !(ahbLif_cur_state[2:0]==IDLE); assign ahblif_idle = ahbLif_cur_state[2:0]==IDLE; endmodule module cr_ahbl_req_arb( ahbl_bmu_dbus_acc_err, ahbl_bmu_dbus_data, ahbl_bmu_dbus_data_vld, ahbl_bmu_dbus_grnt, ahbl_bmu_dbus_trans_cmplt, ahbl_bmu_ibus_acc_err, ahbl_bmu_ibus_data, ahbl_bmu_ibus_data_vld, ahbl_bmu_ibus_grnt, ahbl_bmu_ibus_trans_cmplt, ahbl_gated_clk, bmu_ahbl_dbus_acc_deny, bmu_ahbl_dbus_addr, bmu_ahbl_dbus_chk_fail, bmu_ahbl_dbus_prot, bmu_ahbl_dbus_req, bmu_ahbl_dbus_req_without_cmplt, bmu_ahbl_dbus_req_without_deny_chk_fail, bmu_ahbl_dbus_size, bmu_ahbl_dbus_write, bmu_ahbl_ibus_acc_deny, bmu_ahbl_ibus_addr, bmu_ahbl_ibus_hit, bmu_ahbl_ibus_prot, bmu_ahbl_ibus_req, bmu_ahbl_ibus_req_no_hit, bmu_ahbl_ibus_size, bmu_ahbl_ibus_vec_redirect, bmu_ahbl_ibus_write, bmu_ahbl_wdata, cpu_acc_err, cpu_addr, cpu_data_vld, cpu_prot, cpu_rdata, cpu_req, cpu_req_for_grnt, cpu_req_for_peak_power, cpu_req_grnt, cpu_sec, cpu_size, cpu_trans_cmplt, cpu_vec_redirect, cpu_wdata, cpu_write, cpurst_b, ibus_not_granted ); input ahbl_gated_clk; input bmu_ahbl_dbus_acc_deny; input [31:0] bmu_ahbl_dbus_addr; input bmu_ahbl_dbus_chk_fail; input [3 :0] bmu_ahbl_dbus_prot; input bmu_ahbl_dbus_req; input bmu_ahbl_dbus_req_without_cmplt; input bmu_ahbl_dbus_req_without_deny_chk_fail; input [1 :0] bmu_ahbl_dbus_size; input bmu_ahbl_dbus_write; input bmu_ahbl_ibus_acc_deny; input [31:0] bmu_ahbl_ibus_addr; input bmu_ahbl_ibus_hit; input [3 :0] bmu_ahbl_ibus_prot; input bmu_ahbl_ibus_req; input bmu_ahbl_ibus_req_no_hit; input [1 :0] bmu_ahbl_ibus_size; input bmu_ahbl_ibus_vec_redirect; input bmu_ahbl_ibus_write; input [31:0] bmu_ahbl_wdata; input cpu_acc_err; input cpu_data_vld; input [31:0] cpu_rdata; input cpu_req_grnt; input cpu_sec; input cpu_trans_cmplt; input cpurst_b; output ahbl_bmu_dbus_acc_err; output [31:0] ahbl_bmu_dbus_data; output ahbl_bmu_dbus_data_vld; output ahbl_bmu_dbus_grnt; output ahbl_bmu_dbus_trans_cmplt; output ahbl_bmu_ibus_acc_err; output [31:0] ahbl_bmu_ibus_data; output ahbl_bmu_ibus_data_vld; output ahbl_bmu_ibus_grnt; output ahbl_bmu_ibus_trans_cmplt; output [31:0] cpu_addr; output [3 :0] cpu_prot; output cpu_req; output cpu_req_for_grnt; output cpu_req_for_peak_power; output [1 :0] cpu_size; output cpu_vec_redirect; output [31:0] cpu_wdata; output cpu_write; output ibus_not_granted; reg [1 :0] cpu_req_bus_grnt; reg [1 :0] cpu_req_type; reg ibus_not_granted; wire ahbl_bmu_dbus_acc_err; wire [31:0] ahbl_bmu_dbus_data; wire ahbl_bmu_dbus_data_vld; wire ahbl_bmu_dbus_grnt; wire ahbl_bmu_dbus_trans_cmplt; wire ahbl_bmu_ibus_acc_err; wire [31:0] ahbl_bmu_ibus_data; wire ahbl_bmu_ibus_data_vld; wire ahbl_bmu_ibus_grnt; wire ahbl_bmu_ibus_trans_cmplt; wire ahbl_gated_clk; wire bmu_ahbl_dbus_acc_deny; wire [31:0] bmu_ahbl_dbus_addr; wire bmu_ahbl_dbus_chk_fail; wire [3 :0] bmu_ahbl_dbus_prot; wire bmu_ahbl_dbus_req; wire bmu_ahbl_dbus_req_without_cmplt; wire bmu_ahbl_dbus_req_without_deny_chk_fail; wire [1 :0] bmu_ahbl_dbus_size; wire bmu_ahbl_dbus_write; wire [31:0] bmu_ahbl_had_addr; wire [3 :0] bmu_ahbl_had_prot; wire [1 :0] bmu_ahbl_had_size; wire [31:0] bmu_ahbl_had_wdata; wire bmu_ahbl_had_write; wire bmu_ahbl_ibus_acc_deny; wire [31:0] bmu_ahbl_ibus_addr; wire bmu_ahbl_ibus_hit; wire [3 :0] bmu_ahbl_ibus_prot; wire bmu_ahbl_ibus_req; wire bmu_ahbl_ibus_req_no_hit; wire [1 :0] bmu_ahbl_ibus_size; wire bmu_ahbl_ibus_vec_redirect; wire bmu_ahbl_ibus_write; wire [31:0] bmu_ahbl_wdata; wire cpu_acc_err; wire [31:0] cpu_addr; wire cpu_data_vld; wire [3 :0] cpu_prot; wire [31:0] cpu_rdata; wire cpu_req; wire cpu_req_dbus_grnt; wire cpu_req_for_grnt; wire cpu_req_for_peak_power; wire cpu_req_grnt; wire cpu_req_ibus_grnt; wire [1 :0] cpu_size; wire cpu_trans_cmplt; wire cpu_vec_redirect; wire [31:0] cpu_wdata; wire cpu_write; wire cpurst_b; wire dbus_req; wire dbus_req_without_deny_chk_fail; wire dbus_req_without_deny_chk_fail_cmplt; wire dbus_sel; wire had_req; wire had_req_without_cmplt; wire had_sel; wire ibus_req; wire ibus_req_only; wire ibus_req_without_deny; wire ibus_sel; assign had_req = 1'b0; assign had_req_without_cmplt = 1'b0; assign had_sel = 1'b0; assign bmu_ahbl_had_addr[31:0] = 32'b0; assign bmu_ahbl_had_prot[3:0] = 4'b0; assign bmu_ahbl_had_size[1:0] = 2'b0; assign bmu_ahbl_had_wdata[31:0] = 32'b0; assign bmu_ahbl_had_write = 1'b0; assign ibus_req = bmu_ahbl_ibus_req && !bmu_ahbl_ibus_acc_deny; assign ibus_req_without_deny = bmu_ahbl_ibus_req; assign dbus_req = bmu_ahbl_dbus_req && !bmu_ahbl_dbus_acc_deny && !bmu_ahbl_dbus_chk_fail && !ibus_not_granted; assign dbus_req_without_deny_chk_fail = bmu_ahbl_dbus_req_without_deny_chk_fail && !ibus_not_granted; assign dbus_req_without_deny_chk_fail_cmplt = bmu_ahbl_dbus_req_without_cmplt && !ibus_not_granted; assign ibus_sel = bmu_ahbl_ibus_hit && !dbus_req_without_deny_chk_fail_cmplt && !had_req_without_cmplt; assign dbus_sel = dbus_req_without_deny_chk_fail_cmplt && !had_req_without_cmplt; assign cpu_req = (ibus_req && !dbus_req_without_deny_chk_fail_cmplt && !had_req_without_cmplt) || dbus_req && !had_req_without_cmplt || had_req; assign cpu_req_for_grnt = ibus_req_without_deny || dbus_req_without_deny_chk_fail_cmplt || had_req_without_cmplt; assign cpu_req_for_peak_power = bmu_ahbl_ibus_req_no_hit && bmu_ahbl_ibus_hit || dbus_req_without_deny_chk_fail_cmplt || had_req_without_cmplt; assign cpu_addr[31:0] = {32{dbus_sel}} & bmu_ahbl_dbus_addr[31:0] | {32{ibus_sel}} & bmu_ahbl_ibus_addr[31:0] | {32{had_sel}} & bmu_ahbl_had_addr[31:0]; assign cpu_prot[3:0] = {4{dbus_sel}} & bmu_ahbl_dbus_prot[3:0] | {4{ibus_sel}} & bmu_ahbl_ibus_prot[3:0] | {4{had_sel}} & bmu_ahbl_had_prot[3:0]; assign cpu_size[1:0] = {2{dbus_sel}} & bmu_ahbl_dbus_size[1:0] | {2{ibus_sel}} & bmu_ahbl_ibus_size[1:0] | {2{had_sel}} & bmu_ahbl_had_size[1:0]; assign cpu_write = dbus_sel & bmu_ahbl_dbus_write | ibus_sel & bmu_ahbl_ibus_write | had_sel & bmu_ahbl_had_write; assign cpu_vec_redirect = bmu_ahbl_ibus_vec_redirect; assign cpu_wdata[31:0] = (cpu_req_bus_grnt[1:0] == 2'b1) ? bmu_ahbl_wdata[31:0] : bmu_ahbl_had_wdata[31:0]; always @( had_req or dbus_req or ibus_req) begin casez({had_req, dbus_req, ibus_req}) 3'b1?? : cpu_req_type[1:0] = 2'b10; 3'b01? : cpu_req_type[1:0] = 2'b01; default: cpu_req_type[1:0] = 2'b0; endcase end always @(posedge ahbl_gated_clk or negedge cpurst_b) begin if(!cpurst_b) cpu_req_bus_grnt[1:0] <= 2'b0; else if(cpu_req && cpu_req_grnt) cpu_req_bus_grnt[1:0] <= cpu_req_type[1:0]; else cpu_req_bus_grnt[1:0] <= cpu_req_bus_grnt[1:0]; end assign ibus_req_only = ibus_req && !dbus_req_without_deny_chk_fail_cmplt && !had_req_without_cmplt; always @(posedge ahbl_gated_clk or negedge cpurst_b) begin if(!cpurst_b) ibus_not_granted <= 1'b0; else if(ibus_req_only && !cpu_req_grnt) ibus_not_granted <= 1'b1; else if(cpu_req_grnt && ibus_not_granted) ibus_not_granted <= 1'b0; end assign ahbl_bmu_ibus_grnt = !dbus_req_without_deny_chk_fail_cmplt && ibus_req_without_deny && cpu_req_grnt && !had_req_without_cmplt; assign ahbl_bmu_dbus_grnt = dbus_req_without_deny_chk_fail && cpu_req_grnt && !had_req_without_cmplt; assign cpu_req_ibus_grnt = (cpu_req_bus_grnt[1:0] == 2'b00); assign cpu_req_dbus_grnt = (cpu_req_bus_grnt[1:0] == 2'b01); assign ahbl_bmu_ibus_trans_cmplt = cpu_req_ibus_grnt && cpu_trans_cmplt; assign ahbl_bmu_dbus_trans_cmplt = cpu_req_dbus_grnt && cpu_trans_cmplt; assign ahbl_bmu_ibus_data_vld = cpu_req_ibus_grnt && cpu_data_vld; assign ahbl_bmu_dbus_data_vld = cpu_req_dbus_grnt && cpu_data_vld; assign ahbl_bmu_ibus_acc_err = cpu_req_ibus_grnt && cpu_acc_err; assign ahbl_bmu_dbus_acc_err = cpu_req_dbus_grnt && cpu_acc_err; assign ahbl_bmu_ibus_data[31:0] = cpu_rdata[31:0]; assign ahbl_bmu_dbus_data[31:0] = cpu_rdata[31:0]; endmodule module cr_bmu_dbus_if( biu_bmu_dbus_acc_err, biu_bmu_dbus_data, biu_bmu_dbus_data_vld, biu_bmu_dbus_grnt, biu_bmu_dbus_trans_cmplt, bmu_biu_dbus_acc_deny, bmu_biu_dbus_addr, bmu_biu_dbus_chk_fail, bmu_biu_dbus_prot, bmu_biu_dbus_req, bmu_biu_dbus_req_without_cmplt, bmu_biu_dbus_size, bmu_biu_dbus_wdata, bmu_biu_dbus_write, bmu_iahbl_dbus_acc_deny, bmu_iahbl_dbus_addr, bmu_iahbl_dbus_chk_fail, bmu_iahbl_dbus_prot, bmu_iahbl_dbus_req, bmu_iahbl_dbus_req_without_cmplt, bmu_iahbl_dbus_size, bmu_iahbl_dbus_wdata, bmu_iahbl_dbus_write, bmu_lsu_acc_err, bmu_lsu_bstack_chk_fail, bmu_lsu_data, bmu_lsu_data_vld, bmu_lsu_grnt, bmu_lsu_trans_cmplt, bmu_tcipif_dbus_acc_deny, bmu_tcipif_dbus_addr, bmu_tcipif_dbus_chk_fail, bmu_tcipif_dbus_req, bmu_tcipif_dbus_size, bmu_tcipif_dbus_supv_mode, bmu_tcipif_dbus_wdata, bmu_tcipif_dbus_write, cp0_yy_machine_mode_aft_dbg, cpurst_b, dbus_deny_clk_en, deny_clk, iahbl_bmu_dbus_acc_err, iahbl_bmu_dbus_data, iahbl_bmu_dbus_data_vld, iahbl_bmu_dbus_grnt, iahbl_bmu_dbus_trans_cmplt, lsu_bmu_addr, lsu_bmu_addr_check_fail, lsu_bmu_idle, lsu_bmu_prot, lsu_bmu_req, lsu_bmu_req_without_cmplt, lsu_bmu_sg_chk_fail, lsu_bmu_size, lsu_bmu_store_error, lsu_bmu_wdata, lsu_bmu_wfd1, lsu_bmu_write, pad_bmu_iahbl_base, pad_bmu_iahbl_mask, pmp_bmu_dbus_acc_deny, tcipif_bmu_dbus_acc_err, tcipif_bmu_dbus_data, tcipif_bmu_dbus_data_vld, tcipif_bmu_dbus_grnt, tcipif_bmu_dbus_trans_cmplt ); input biu_bmu_dbus_acc_err; input [31:0] biu_bmu_dbus_data; input biu_bmu_dbus_data_vld; input biu_bmu_dbus_grnt; input biu_bmu_dbus_trans_cmplt; input cp0_yy_machine_mode_aft_dbg; input cpurst_b; input deny_clk; input iahbl_bmu_dbus_acc_err; input [31:0] iahbl_bmu_dbus_data; input iahbl_bmu_dbus_data_vld; input iahbl_bmu_dbus_grnt; input iahbl_bmu_dbus_trans_cmplt; input [31:0] lsu_bmu_addr; input lsu_bmu_addr_check_fail; input lsu_bmu_idle; input [3 :0] lsu_bmu_prot; input lsu_bmu_req; input lsu_bmu_req_without_cmplt; input lsu_bmu_sg_chk_fail; input [1 :0] lsu_bmu_size; input lsu_bmu_store_error; input [31:0] lsu_bmu_wdata; input lsu_bmu_wfd1; input lsu_bmu_write; input [11:0] pad_bmu_iahbl_base; input [11:0] pad_bmu_iahbl_mask; input pmp_bmu_dbus_acc_deny; input tcipif_bmu_dbus_acc_err; input [31:0] tcipif_bmu_dbus_data; input tcipif_bmu_dbus_data_vld; input tcipif_bmu_dbus_grnt; input tcipif_bmu_dbus_trans_cmplt; output bmu_biu_dbus_acc_deny; output [31:0] bmu_biu_dbus_addr; output bmu_biu_dbus_chk_fail; output [3 :0] bmu_biu_dbus_prot; output bmu_biu_dbus_req; output bmu_biu_dbus_req_without_cmplt; output [1 :0] bmu_biu_dbus_size; output [31:0] bmu_biu_dbus_wdata; output bmu_biu_dbus_write; output bmu_iahbl_dbus_acc_deny; output [31:0] bmu_iahbl_dbus_addr; output bmu_iahbl_dbus_chk_fail; output [3 :0] bmu_iahbl_dbus_prot; output bmu_iahbl_dbus_req; output bmu_iahbl_dbus_req_without_cmplt; output [1 :0] bmu_iahbl_dbus_size; output [31:0] bmu_iahbl_dbus_wdata; output bmu_iahbl_dbus_write; output bmu_lsu_acc_err; output bmu_lsu_bstack_chk_fail; output [31:0] bmu_lsu_data; output bmu_lsu_data_vld; output bmu_lsu_grnt; output bmu_lsu_trans_cmplt; output bmu_tcipif_dbus_acc_deny; output [31:0] bmu_tcipif_dbus_addr; output bmu_tcipif_dbus_chk_fail; output bmu_tcipif_dbus_req; output [1 :0] bmu_tcipif_dbus_size; output bmu_tcipif_dbus_supv_mode; output [31:0] bmu_tcipif_dbus_wdata; output bmu_tcipif_dbus_write; output dbus_deny_clk_en; reg [2 :0] cross_cur_st; reg [2 :0] cross_nxt_st; reg [1 :0] cur_state; reg iahbl_lrw_hit_ff; reg iahbl_norm_hit_ff; reg [1 :0] next_state; reg [2 :0] req_bus; wire acc_deny; wire acc_err_for_deny; wire biu_bmu_dbus_acc_err; wire [31:0] biu_bmu_dbus_data; wire biu_bmu_dbus_data_vld; wire biu_bmu_dbus_grnt; wire biu_bmu_dbus_trans_cmplt; wire biu_data_vld; wire bmu_biu_dbus_acc_deny; wire [31:0] bmu_biu_dbus_addr; wire bmu_biu_dbus_chk_fail; wire [3 :0] bmu_biu_dbus_prot; wire bmu_biu_dbus_req; wire bmu_biu_dbus_req_without_cmplt; wire [1 :0] bmu_biu_dbus_size; wire [31:0] bmu_biu_dbus_wdata; wire bmu_biu_dbus_write; wire bmu_iahbl_dbus_acc_deny; wire [31:0] bmu_iahbl_dbus_addr; wire bmu_iahbl_dbus_chk_fail; wire [3 :0] bmu_iahbl_dbus_prot; wire bmu_iahbl_dbus_req; wire bmu_iahbl_dbus_req_without_cmplt; wire [1 :0] bmu_iahbl_dbus_size; wire [31:0] bmu_iahbl_dbus_wdata; wire bmu_iahbl_dbus_write; wire bmu_lsu_acc_err; wire bmu_lsu_bstack_chk_fail; wire [31:0] bmu_lsu_data; wire bmu_lsu_data_vld; wire bmu_lsu_grnt; wire bmu_lsu_trans_cmplt; wire bmu_tcipif_dbus_acc_deny; wire [31:0] bmu_tcipif_dbus_addr; wire bmu_tcipif_dbus_chk_fail; wire bmu_tcipif_dbus_req; wire [1 :0] bmu_tcipif_dbus_size; wire bmu_tcipif_dbus_supv_mode; wire [31:0] bmu_tcipif_dbus_wdata; wire bmu_tcipif_dbus_write; wire bstck_chk_fail; wire cp0_yy_machine_mode_aft_dbg; wire cpurst_b; wire cross_fsm_upd; wire cross_iahbl; wire cross_idle; wire cross_sahbl; wire cross_tcip; wire dahbl_bmu_dbus_acc_err; wire [31:0] dahbl_bmu_dbus_data; wire dahbl_bmu_dbus_data_vld; wire dahbl_bmu_dbus_grnt; wire dahbl_bmu_dbus_trans_cmplt; wire dahbl_data_vld; wire dahbl_hit; wire dahbl_hit_ff; wire dahbl_hit_upd; wire dahbl_req; wire dbus_deny_clk_en; wire dbus_grnt; wire deny_clk; wire iahbl_bmu_dbus_acc_err; wire [31:0] iahbl_bmu_dbus_data; wire iahbl_bmu_dbus_data_vld; wire iahbl_bmu_dbus_grnt; wire iahbl_bmu_dbus_trans_cmplt; wire iahbl_data_vld; wire iahbl_hit; wire iahbl_hit_ff; wire iahbl_hit_upd; wire iahbl_lrw_hit; wire iahbl_lrw_hit_upd; wire iahbl_norm_hit_upd; wire iahbl_req; wire iahbl_vld; wire [31:0] lsu_bmu_addr; wire lsu_bmu_addr_check_fail; wire lsu_bmu_idle; wire [3 :0] lsu_bmu_prot; wire lsu_bmu_req; wire lsu_bmu_req_without_cmplt; wire lsu_bmu_sg_chk_fail; wire [1 :0] lsu_bmu_size; wire lsu_bmu_store_error; wire [31:0] lsu_bmu_wdata; wire lsu_bmu_wfd1; wire lsu_bmu_write; wire lsu_inst_lrw; wire lsu_inst_norm; wire [11:0] pad_bmu_iahbl_base; wire [11:0] pad_bmu_iahbl_mask; wire pmp_bmu_dbus_acc_deny; wire sahbl_req; wire sahbl_vld; wire tcip_req; wire tcip_vld; wire [15:0] tcipif_addr_low; wire tcipif_bmu_dbus_acc_err; wire [31:0] tcipif_bmu_dbus_data; wire tcipif_bmu_dbus_data_vld; wire tcipif_bmu_dbus_grnt; wire tcipif_bmu_dbus_trans_cmplt; wire tcipif_data_vld; wire tcipif_hit; parameter TCIPIF_BASE = 4'b1110; assign acc_deny = pmp_bmu_dbus_acc_deny || lsu_bmu_sg_chk_fail || lsu_bmu_store_error; assign lsu_inst_norm = lsu_bmu_req & lsu_bmu_prot[0] & !tcipif_hit; assign lsu_inst_lrw = lsu_bmu_req & !lsu_bmu_prot[0]; assign dahbl_hit = 1'b0; assign dahbl_hit_ff = 1'b0; assign dahbl_hit_upd = 1'b0; assign iahbl_hit = ((lsu_bmu_addr[31:20] & pad_bmu_iahbl_mask[11:0]) == pad_bmu_iahbl_base[11:0]); assign iahbl_lrw_hit = iahbl_hit; assign iahbl_norm_hit_upd = (iahbl_norm_hit_ff ^ iahbl_hit) & lsu_inst_norm; always @(posedge deny_clk or negedge cpurst_b) begin if(!cpurst_b) iahbl_norm_hit_ff <= 1'b0; else if(iahbl_norm_hit_upd) iahbl_norm_hit_ff <= iahbl_hit; else iahbl_norm_hit_ff <= iahbl_norm_hit_ff; end assign iahbl_lrw_hit_upd = (iahbl_lrw_hit_ff ^ iahbl_lrw_hit) & lsu_inst_lrw; always @(posedge deny_clk or negedge cpurst_b) begin if(!cpurst_b) iahbl_lrw_hit_ff <= 1'b1; else if(iahbl_lrw_hit_upd) iahbl_lrw_hit_ff <= iahbl_lrw_hit; else iahbl_lrw_hit_ff <= iahbl_lrw_hit_ff; end assign iahbl_hit_ff = !lsu_bmu_prot[0] ? iahbl_lrw_hit_ff : iahbl_norm_hit_ff; assign iahbl_hit_upd = iahbl_norm_hit_upd || iahbl_lrw_hit_upd; parameter CIDLE = 3'b000; parameter SAHBL = 3'b001; parameter CTCIP = 3'b010; parameter IAHBL = 3'b011; parameter DAHBL = 3'b100; always @(posedge deny_clk or negedge cpurst_b) begin if(!cpurst_b) cross_cur_st[2:0] <= CIDLE; else cross_cur_st[2:0] <= cross_nxt_st[2:0]; end assign sahbl_req = lsu_bmu_req && !iahbl_hit && !dahbl_hit && !tcipif_hit; assign iahbl_req = lsu_bmu_req && iahbl_hit; assign dahbl_req = lsu_bmu_req && dahbl_hit; assign tcip_req = lsu_bmu_req && tcipif_hit; assign cross_fsm_upd = cross_nxt_st[2:0] != cross_cur_st[2:0]; always @( sahbl_req or iahbl_req or dahbl_req or tcip_req) begin case({sahbl_req, tcip_req, iahbl_req, dahbl_req}) 4'b1000: req_bus[2:0] = SAHBL; 4'b0100: req_bus[2:0] = CTCIP; 4'b0010: req_bus[2:0] = IAHBL; 4'b0001: req_bus[2:0] = DAHBL; default: req_bus[2:0] = CIDLE; endcase end always @( sahbl_req or lsu_bmu_idle or req_bus or iahbl_req or dahbl_req or tcip_req or cross_cur_st) begin case(cross_cur_st) CIDLE: begin case({sahbl_req, tcip_req, iahbl_req, dahbl_req}) 4'b1000: cross_nxt_st = SAHBL; 4'b0100: cross_nxt_st = CTCIP; 4'b0010: cross_nxt_st = IAHBL; 4'b0001: cross_nxt_st = DAHBL; default: cross_nxt_st = CIDLE; endcase end SAHBL: begin if(lsu_bmu_idle) cross_nxt_st = req_bus; else cross_nxt_st = SAHBL; end CTCIP: begin if(lsu_bmu_idle) cross_nxt_st = req_bus; else cross_nxt_st = CTCIP; end IAHBL: begin if(lsu_bmu_idle) cross_nxt_st = req_bus; else cross_nxt_st = IAHBL; end DAHBL: begin if(lsu_bmu_idle) cross_nxt_st = req_bus; else cross_nxt_st = DAHBL; end default: begin cross_nxt_st = CIDLE; end endcase end assign cross_idle = cross_cur_st == CIDLE; assign cross_sahbl = cross_cur_st == SAHBL; assign sahbl_vld = cross_idle || cross_sahbl; assign cross_tcip = cross_cur_st == CTCIP; assign tcip_vld = cross_idle || cross_tcip; assign cross_iahbl = cross_cur_st == IAHBL; assign iahbl_vld = cross_idle || cross_iahbl; assign dahbl_bmu_dbus_acc_err = 1'b0; assign dahbl_bmu_dbus_data[31:0] = 32'b0; assign dahbl_bmu_dbus_data_vld = 1'b0; assign dahbl_bmu_dbus_grnt = 1'b0; assign dahbl_bmu_dbus_trans_cmplt = 1'b0; assign bmu_iahbl_dbus_req = lsu_bmu_req & iahbl_hit & iahbl_hit_ff & iahbl_vld; assign bmu_iahbl_dbus_req_without_cmplt = lsu_bmu_req_without_cmplt & iahbl_hit_ff & iahbl_vld; assign bmu_iahbl_dbus_acc_deny = acc_deny; assign bmu_iahbl_dbus_chk_fail = lsu_bmu_addr_check_fail; assign bmu_iahbl_dbus_write = lsu_bmu_write; assign bmu_iahbl_dbus_size[1:0] = lsu_bmu_size[1:0]; assign bmu_iahbl_dbus_wdata[31:0] = lsu_bmu_wdata[31:0]; assign bmu_iahbl_dbus_addr[31:0] = lsu_bmu_addr[31:0]; assign bmu_iahbl_dbus_prot[3:0] = lsu_bmu_prot[3:0]; assign tcipif_hit = (lsu_bmu_addr[31:28] == TCIPIF_BASE); assign bmu_tcipif_dbus_req = lsu_bmu_req & tcipif_hit & tcip_vld; assign bmu_tcipif_dbus_acc_deny = acc_deny; assign bmu_tcipif_dbus_chk_fail = lsu_bmu_addr_check_fail; assign bmu_tcipif_dbus_write = lsu_bmu_write; assign bmu_tcipif_dbus_size[1:0] = lsu_bmu_size[1:0]; assign bmu_tcipif_dbus_supv_mode = cp0_yy_machine_mode_aft_dbg; assign bmu_tcipif_dbus_wdata[31:0] = lsu_bmu_wdata[31:0]; assign tcipif_addr_low[15:0] = {16{tcipif_hit}} & lsu_bmu_addr[15:0]; assign bmu_tcipif_dbus_addr[31:0] = {lsu_bmu_addr[31:16], tcipif_addr_low[15:0]}; assign bmu_biu_dbus_req = lsu_bmu_req & ~iahbl_hit & ~dahbl_hit & ~iahbl_hit_ff & ~dahbl_hit_ff & ~tcipif_hit & sahbl_vld; assign bmu_biu_dbus_req_without_cmplt = lsu_bmu_req_without_cmplt & ~iahbl_hit_ff & ~dahbl_hit_ff & sahbl_vld; assign bmu_biu_dbus_acc_deny = acc_deny; assign bmu_biu_dbus_chk_fail = lsu_bmu_addr_check_fail; assign bmu_biu_dbus_write = lsu_bmu_write; assign bmu_biu_dbus_size[1:0] = lsu_bmu_size[1:0]; assign bmu_biu_dbus_wdata[31:0] = lsu_bmu_wdata[31:0]; assign bmu_biu_dbus_addr[31:0] = lsu_bmu_addr[31:0]; assign bmu_biu_dbus_prot[3:0] = lsu_bmu_prot[3:0]; assign dbus_grnt = dahbl_bmu_dbus_grnt | iahbl_bmu_dbus_grnt | tcipif_bmu_dbus_grnt | biu_bmu_dbus_grnt; assign bmu_lsu_grnt = dbus_grnt; parameter IDLE = 2'b00; parameter BSTACK_FAIL = 2'b01; parameter DENY = 2'b10; assign dbus_deny_clk_en = (cur_state != IDLE) || lsu_bmu_addr_check_fail || acc_deny || iahbl_hit_upd || dahbl_hit_upd || cross_fsm_upd; always @(posedge deny_clk or negedge cpurst_b) begin if(!cpurst_b) cur_state[1:0] <= IDLE; else cur_state[1:0] <= next_state[1:0]; end always @( cur_state or dbus_grnt or acc_deny or lsu_bmu_wfd1 or lsu_bmu_addr_check_fail) begin case(cur_state) IDLE : if(dbus_grnt && lsu_bmu_addr_check_fail) next_state = BSTACK_FAIL; else if(dbus_grnt && acc_deny) next_state = DENY; else next_state = IDLE; BSTACK_FAIL : if(lsu_bmu_wfd1) next_state = IDLE; else next_state = BSTACK_FAIL; DENY : if(lsu_bmu_wfd1) next_state = IDLE; else next_state = DENY; default : next_state = IDLE; endcase end assign bstck_chk_fail = (cur_state == BSTACK_FAIL) && lsu_bmu_wfd1; assign acc_err_for_deny = (cur_state == DENY) && lsu_bmu_wfd1; assign bmu_lsu_trans_cmplt = dahbl_bmu_dbus_trans_cmplt | iahbl_bmu_dbus_trans_cmplt | tcipif_bmu_dbus_trans_cmplt | biu_bmu_dbus_trans_cmplt | acc_err_for_deny | bstck_chk_fail; assign bmu_lsu_data_vld = dahbl_bmu_dbus_data_vld | iahbl_bmu_dbus_data_vld | tcipif_bmu_dbus_data_vld | biu_bmu_dbus_data_vld; assign dahbl_data_vld = dahbl_bmu_dbus_data_vld; assign iahbl_data_vld = iahbl_bmu_dbus_data_vld; assign biu_data_vld = biu_bmu_dbus_data_vld; assign tcipif_data_vld = tcipif_bmu_dbus_data_vld; assign bmu_lsu_data[31:0] = ({32{dahbl_data_vld}} & dahbl_bmu_dbus_data[31:0]) | ({32{iahbl_data_vld}} & iahbl_bmu_dbus_data[31:0]) | ({32{tcipif_data_vld}} & tcipif_bmu_dbus_data[31:0]) | ({32{biu_data_vld}} & biu_bmu_dbus_data[31:0]); assign bmu_lsu_acc_err = dahbl_bmu_dbus_acc_err | iahbl_bmu_dbus_acc_err | tcipif_bmu_dbus_acc_err | biu_bmu_dbus_acc_err | acc_err_for_deny; assign bmu_lsu_bstack_chk_fail = bstck_chk_fail; endmodule module cr_bmu_ibus_if( biu_bmu_ibus_acc_err, biu_bmu_ibus_data, biu_bmu_ibus_data_vld, biu_bmu_ibus_grnt, biu_bmu_ibus_trans_cmplt, bmu_biu_ibus_acc_deny, bmu_biu_ibus_addr, bmu_biu_ibus_hit, bmu_biu_ibus_prot, bmu_biu_ibus_req, bmu_biu_ibus_req_no_hit, bmu_biu_ibus_size, bmu_biu_ibus_vec_redirect, bmu_iahbl_ibus_acc_deny, bmu_iahbl_ibus_addr, bmu_iahbl_ibus_hit, bmu_iahbl_ibus_prot, bmu_iahbl_ibus_req, bmu_iahbl_ibus_req_no_hit, bmu_iahbl_ibus_size, bmu_iahbl_ibus_vec_redirect, bmu_tcipif_ibus_acc_deny, bmu_tcipif_ibus_addr, bmu_tcipif_ibus_req, bmu_tcipif_ibus_write, bmu_xx_ibus_acc_err, bmu_xx_ibus_data, bmu_xx_ibus_data_vld, bmu_xx_ibus_grnt, bmu_xx_ibus_trans_cmplt, cpurst_b, deny_clk, iahbl_bmu_ibus_acc_err, iahbl_bmu_ibus_data, iahbl_bmu_ibus_data_vld, iahbl_bmu_ibus_grnt, iahbl_bmu_ibus_trans_cmplt, ibus_deny_clk_en, ifu_bmu_addr, ifu_bmu_idle, ifu_bmu_prot, ifu_bmu_req, ifu_bmu_wfd1, iu_bmu_vec_redirect, pad_bmu_iahbl_base, pad_bmu_iahbl_mask, pmp_bmu_ibus_acc_deny, tcipif_bmu_ibus_acc_err, tcipif_bmu_ibus_data, tcipif_bmu_ibus_data_vld, tcipif_bmu_ibus_grnt, tcipif_bmu_ibus_trans_cmplt ); input biu_bmu_ibus_acc_err; input [31:0] biu_bmu_ibus_data; input biu_bmu_ibus_data_vld; input biu_bmu_ibus_grnt; input biu_bmu_ibus_trans_cmplt; input cpurst_b; input deny_clk; input iahbl_bmu_ibus_acc_err; input [31:0] iahbl_bmu_ibus_data; input iahbl_bmu_ibus_data_vld; input iahbl_bmu_ibus_grnt; input iahbl_bmu_ibus_trans_cmplt; input [31:0] ifu_bmu_addr; input ifu_bmu_idle; input [3 :0] ifu_bmu_prot; input ifu_bmu_req; input ifu_bmu_wfd1; input iu_bmu_vec_redirect; input [11:0] pad_bmu_iahbl_base; input [11:0] pad_bmu_iahbl_mask; input pmp_bmu_ibus_acc_deny; input tcipif_bmu_ibus_acc_err; input [31:0] tcipif_bmu_ibus_data; input tcipif_bmu_ibus_data_vld; input tcipif_bmu_ibus_grnt; input tcipif_bmu_ibus_trans_cmplt; output bmu_biu_ibus_acc_deny; output [31:0] bmu_biu_ibus_addr; output bmu_biu_ibus_hit; output [3 :0] bmu_biu_ibus_prot; output bmu_biu_ibus_req; output bmu_biu_ibus_req_no_hit; output [1 :0] bmu_biu_ibus_size; output bmu_biu_ibus_vec_redirect; output bmu_iahbl_ibus_acc_deny; output [31:0] bmu_iahbl_ibus_addr; output bmu_iahbl_ibus_hit; output [3 :0] bmu_iahbl_ibus_prot; output bmu_iahbl_ibus_req; output bmu_iahbl_ibus_req_no_hit; output [1 :0] bmu_iahbl_ibus_size; output bmu_iahbl_ibus_vec_redirect; output bmu_tcipif_ibus_acc_deny; output [31:0] bmu_tcipif_ibus_addr; output bmu_tcipif_ibus_req; output bmu_tcipif_ibus_write; output bmu_xx_ibus_acc_err; output [31:0] bmu_xx_ibus_data; output bmu_xx_ibus_data_vld; output bmu_xx_ibus_grnt; output bmu_xx_ibus_trans_cmplt; output ibus_deny_clk_en; reg acc_err_for_deny; reg iahbl_hit_ff; reg tcipif_hit_ff; wire biu_bmu_ibus_acc_err; wire [31:0] biu_bmu_ibus_data; wire biu_bmu_ibus_data_vld; wire biu_bmu_ibus_grnt; wire biu_bmu_ibus_trans_cmplt; wire biu_data_vld; wire bmu_biu_ibus_acc_deny; wire [31:0] bmu_biu_ibus_addr; wire bmu_biu_ibus_hit; wire [3 :0] bmu_biu_ibus_prot; wire bmu_biu_ibus_req; wire bmu_biu_ibus_req_no_hit; wire [1 :0] bmu_biu_ibus_size; wire bmu_biu_ibus_vec_redirect; wire bmu_iahbl_ibus_acc_deny; wire [31:0] bmu_iahbl_ibus_addr; wire bmu_iahbl_ibus_hit; wire [3 :0] bmu_iahbl_ibus_prot; wire bmu_iahbl_ibus_req; wire bmu_iahbl_ibus_req_no_hit; wire [1 :0] bmu_iahbl_ibus_size; wire bmu_iahbl_ibus_vec_redirect; wire bmu_tcipif_ibus_acc_deny; wire [31:0] bmu_tcipif_ibus_addr; wire bmu_tcipif_ibus_req; wire bmu_tcipif_ibus_write; wire bmu_xx_ibus_acc_err; wire [31:0] bmu_xx_ibus_data; wire bmu_xx_ibus_data_vld; wire bmu_xx_ibus_grnt; wire bmu_xx_ibus_trans_cmplt; wire cpurst_b; wire dahbl_bmu_ibus_acc_err; wire [31:0] dahbl_bmu_ibus_data; wire dahbl_bmu_ibus_data_vld; wire dahbl_bmu_ibus_grnt; wire dahbl_bmu_ibus_trans_cmplt; wire dahbl_data_vld; wire dahbl_hit; wire dahbl_hit_ff; wire dahbl_hit_upd; wire deny_clk; wire iahbl_bmu_ibus_acc_err; wire [31:0] iahbl_bmu_ibus_data; wire iahbl_bmu_ibus_data_vld; wire iahbl_bmu_ibus_grnt; wire iahbl_bmu_ibus_trans_cmplt; wire iahbl_data_vld; wire iahbl_hit; wire iahbl_hit_upd; wire ibus_deny_clk_en; wire ibus_grnt; wire [31:0] ifu_bmu_addr; wire ifu_bmu_idle; wire [3 :0] ifu_bmu_prot; wire ifu_bmu_req; wire ifu_bmu_wfd1; wire iu_bmu_vec_redirect; wire [11:0] pad_bmu_iahbl_base; wire [11:0] pad_bmu_iahbl_mask; wire pmp_bmu_ibus_acc_deny; wire tcipif_bmu_ibus_acc_err; wire [31:0] tcipif_bmu_ibus_data; wire tcipif_bmu_ibus_data_vld; wire tcipif_bmu_ibus_grnt; wire tcipif_bmu_ibus_trans_cmplt; wire tcipif_data_vld; wire tcipif_hit; wire tcipif_hit_upd; parameter TCIPIF_BASE = 4'b1110; assign iahbl_hit = ((ifu_bmu_addr[31:20] & pad_bmu_iahbl_mask[11:0]) == pad_bmu_iahbl_base[11:0]); assign iahbl_hit_upd = (iahbl_hit_ff ^ iahbl_hit) & ifu_bmu_req & ifu_bmu_idle; always @(posedge deny_clk or negedge cpurst_b) begin if(!cpurst_b) iahbl_hit_ff <= 1'b1; else if(iahbl_hit_upd) iahbl_hit_ff <= iahbl_hit; else iahbl_hit_ff <= iahbl_hit_ff; end assign dahbl_hit = 1'b0; assign dahbl_hit_ff = 1'b0; assign dahbl_hit_upd = 1'b0; assign bmu_iahbl_ibus_req = ifu_bmu_req & iahbl_hit & iahbl_hit_ff; assign bmu_iahbl_ibus_req_no_hit = ifu_bmu_req & iahbl_hit_ff; assign bmu_iahbl_ibus_hit = iahbl_hit_ff; assign bmu_iahbl_ibus_acc_deny = pmp_bmu_ibus_acc_deny; assign bmu_iahbl_ibus_size[1:0] = 2'b10; assign bmu_iahbl_ibus_addr[31:0] = ifu_bmu_addr[31:0]; assign bmu_iahbl_ibus_vec_redirect= iu_bmu_vec_redirect; assign bmu_iahbl_ibus_prot[3:0] = ifu_bmu_prot[3:0]; assign dahbl_bmu_ibus_acc_err = 1'b0; assign dahbl_bmu_ibus_data[31:0] = 32'b0; assign dahbl_bmu_ibus_data_vld = 1'b0; assign dahbl_bmu_ibus_grnt = 1'b0; assign dahbl_bmu_ibus_trans_cmplt = 1'b0; assign tcipif_hit = (ifu_bmu_addr[31:28] == TCIPIF_BASE); assign tcipif_hit_upd = (tcipif_hit_ff ^ tcipif_hit) & ifu_bmu_req & ifu_bmu_idle; always @(posedge deny_clk or negedge cpurst_b) begin if(!cpurst_b) tcipif_hit_ff <= 1'b0; else if(tcipif_hit_upd) tcipif_hit_ff <= tcipif_hit; else tcipif_hit_ff <= tcipif_hit_ff; end assign bmu_tcipif_ibus_req = ifu_bmu_req & tcipif_hit & tcipif_hit_ff; assign bmu_tcipif_ibus_acc_deny = pmp_bmu_ibus_acc_deny; assign bmu_tcipif_ibus_write = 1'b0; assign bmu_tcipif_ibus_addr[31:0] = ifu_bmu_addr[31:0]; assign bmu_biu_ibus_req = ifu_bmu_req & ~iahbl_hit & ~dahbl_hit & ~tcipif_hit & ~iahbl_hit_ff & ~dahbl_hit_ff & ~tcipif_hit_ff; assign bmu_biu_ibus_req_no_hit = ifu_bmu_req & ~iahbl_hit_ff & ~dahbl_hit_ff & ~tcipif_hit_ff; assign bmu_biu_ibus_hit = ~iahbl_hit_ff & ~dahbl_hit_ff & ~tcipif_hit_ff; assign bmu_biu_ibus_acc_deny = pmp_bmu_ibus_acc_deny; assign bmu_biu_ibus_size[1:0] = 2'b10; assign bmu_biu_ibus_addr[31:0] = ifu_bmu_addr[31:0]; assign bmu_biu_ibus_vec_redirect = iu_bmu_vec_redirect; assign bmu_biu_ibus_prot[3:0] = ifu_bmu_prot[3:0]; assign ibus_grnt = iahbl_bmu_ibus_grnt | dahbl_bmu_ibus_grnt | tcipif_bmu_ibus_grnt | biu_bmu_ibus_grnt; assign bmu_xx_ibus_grnt = ibus_grnt; assign ibus_deny_clk_en = acc_err_for_deny || pmp_bmu_ibus_acc_deny || iahbl_hit_upd || dahbl_hit_upd || tcipif_hit_upd; always @(posedge deny_clk or negedge cpurst_b) begin if(!cpurst_b) acc_err_for_deny <= 1'b0; else if(ibus_grnt) acc_err_for_deny <= pmp_bmu_ibus_acc_deny; else if(acc_err_for_deny && ifu_bmu_wfd1) acc_err_for_deny <= 1'b0; end assign bmu_xx_ibus_trans_cmplt = iahbl_bmu_ibus_trans_cmplt | dahbl_bmu_ibus_trans_cmplt | tcipif_bmu_ibus_trans_cmplt | biu_bmu_ibus_trans_cmplt | acc_err_for_deny & ifu_bmu_wfd1; assign bmu_xx_ibus_data_vld = iahbl_bmu_ibus_data_vld | dahbl_bmu_ibus_data_vld | tcipif_bmu_ibus_data_vld | biu_bmu_ibus_data_vld; assign iahbl_data_vld = iahbl_bmu_ibus_data_vld; assign dahbl_data_vld = dahbl_bmu_ibus_data_vld; assign biu_data_vld = biu_bmu_ibus_data_vld; assign tcipif_data_vld = tcipif_bmu_ibus_data_vld; assign bmu_xx_ibus_data[31:0] = ({32{iahbl_data_vld}} & iahbl_bmu_ibus_data[31:0]) | ({32{dahbl_data_vld}} & dahbl_bmu_ibus_data[31:0]) | ({32{tcipif_data_vld}} & tcipif_bmu_ibus_data[31:0]) | ({32{biu_data_vld}} & biu_bmu_ibus_data[31:0]); assign bmu_xx_ibus_acc_err = iahbl_bmu_ibus_acc_err | dahbl_bmu_ibus_acc_err | tcipif_bmu_ibus_acc_err | biu_bmu_ibus_acc_err | acc_err_for_deny & ifu_bmu_wfd1; endmodule module cr_bmu_top( biu_bmu_dbus_acc_err, biu_bmu_dbus_data, biu_bmu_dbus_data_vld, biu_bmu_dbus_grnt, biu_bmu_dbus_trans_cmplt, biu_bmu_ibus_acc_err, biu_bmu_ibus_data, biu_bmu_ibus_data_vld, biu_bmu_ibus_grnt, biu_bmu_ibus_trans_cmplt, bmu_biu_dbus_acc_deny, bmu_biu_dbus_addr, bmu_biu_dbus_chk_fail, bmu_biu_dbus_prot, bmu_biu_dbus_req, bmu_biu_dbus_req_without_cmplt, bmu_biu_dbus_size, bmu_biu_dbus_wdata, bmu_biu_dbus_write, bmu_biu_ibus_acc_deny, bmu_biu_ibus_addr, bmu_biu_ibus_hit, bmu_biu_ibus_prot, bmu_biu_ibus_req, bmu_biu_ibus_req_no_hit, bmu_biu_ibus_size, bmu_biu_ibus_vec_redirect, bmu_iahbl_dbus_acc_deny, bmu_iahbl_dbus_addr, bmu_iahbl_dbus_chk_fail, bmu_iahbl_dbus_prot, bmu_iahbl_dbus_req, bmu_iahbl_dbus_req_without_cmplt, bmu_iahbl_dbus_size, bmu_iahbl_dbus_wdata, bmu_iahbl_dbus_write, bmu_iahbl_ibus_acc_deny, bmu_iahbl_ibus_addr, bmu_iahbl_ibus_hit, bmu_iahbl_ibus_prot, bmu_iahbl_ibus_req, bmu_iahbl_ibus_req_no_hit, bmu_iahbl_ibus_size, bmu_iahbl_ibus_vec_redirect, bmu_lsu_acc_err, bmu_lsu_bstack_chk_fail, bmu_lsu_data, bmu_lsu_data_vld, bmu_lsu_grnt, bmu_lsu_trans_cmplt, bmu_tcipif_dbus_acc_deny, bmu_tcipif_dbus_addr, bmu_tcipif_dbus_chk_fail, bmu_tcipif_dbus_req, bmu_tcipif_dbus_size, bmu_tcipif_dbus_supv_mode, bmu_tcipif_dbus_wdata, bmu_tcipif_dbus_write, bmu_tcipif_ibus_acc_deny, bmu_tcipif_ibus_addr, bmu_tcipif_ibus_req, bmu_tcipif_ibus_write, bmu_xx_ibus_acc_err, bmu_xx_ibus_data, bmu_xx_ibus_data_vld, bmu_xx_ibus_grnt, bmu_xx_ibus_trans_cmplt, cp0_yy_clk_en, cp0_yy_machine_mode_aft_dbg, cpurst_b, forever_cpuclk, iahbl_bmu_dbus_acc_err, iahbl_bmu_dbus_data, iahbl_bmu_dbus_data_vld, iahbl_bmu_dbus_grnt, iahbl_bmu_dbus_trans_cmplt, iahbl_bmu_ibus_acc_err, iahbl_bmu_ibus_data, iahbl_bmu_ibus_data_vld, iahbl_bmu_ibus_grnt, iahbl_bmu_ibus_trans_cmplt, ifu_bmu_addr, ifu_bmu_idle, ifu_bmu_prot, ifu_bmu_req, ifu_bmu_wfd1, iu_bmu_vec_redirect, lsu_bmu_addr, lsu_bmu_addr_check_fail, lsu_bmu_idle, lsu_bmu_prot, lsu_bmu_req, lsu_bmu_req_without_cmplt, lsu_bmu_sg_chk_fail, lsu_bmu_size, lsu_bmu_store_error, lsu_bmu_wdata, lsu_bmu_wfd1, lsu_bmu_write, pad_bmu_iahbl_base, pad_bmu_iahbl_mask, pad_yy_gate_clk_en_b, pad_yy_test_mode, tcipif_bmu_dbus_acc_err, tcipif_bmu_dbus_data, tcipif_bmu_dbus_data_vld, tcipif_bmu_dbus_grnt, tcipif_bmu_dbus_trans_cmplt, tcipif_bmu_ibus_acc_err, tcipif_bmu_ibus_data, tcipif_bmu_ibus_data_vld, tcipif_bmu_ibus_grnt, tcipif_bmu_ibus_trans_cmplt ); input biu_bmu_dbus_acc_err; input [31:0] biu_bmu_dbus_data; input biu_bmu_dbus_data_vld; input biu_bmu_dbus_grnt; input biu_bmu_dbus_trans_cmplt; input biu_bmu_ibus_acc_err; input [31:0] biu_bmu_ibus_data; input biu_bmu_ibus_data_vld; input biu_bmu_ibus_grnt; input biu_bmu_ibus_trans_cmplt; input cp0_yy_clk_en; input cp0_yy_machine_mode_aft_dbg; input cpurst_b; input forever_cpuclk; input iahbl_bmu_dbus_acc_err; input [31:0] iahbl_bmu_dbus_data; input iahbl_bmu_dbus_data_vld; input iahbl_bmu_dbus_grnt; input iahbl_bmu_dbus_trans_cmplt; input iahbl_bmu_ibus_acc_err; input [31:0] iahbl_bmu_ibus_data; input iahbl_bmu_ibus_data_vld; input iahbl_bmu_ibus_grnt; input iahbl_bmu_ibus_trans_cmplt; input [31:0] ifu_bmu_addr; input ifu_bmu_idle; input [3 :0] ifu_bmu_prot; input ifu_bmu_req; input ifu_bmu_wfd1; input iu_bmu_vec_redirect; input [31:0] lsu_bmu_addr; input lsu_bmu_addr_check_fail; input lsu_bmu_idle; input [3 :0] lsu_bmu_prot; input lsu_bmu_req; input lsu_bmu_req_without_cmplt; input lsu_bmu_sg_chk_fail; input [1 :0] lsu_bmu_size; input lsu_bmu_store_error; input [31:0] lsu_bmu_wdata; input lsu_bmu_wfd1; input lsu_bmu_write; input [11:0] pad_bmu_iahbl_base; input [11:0] pad_bmu_iahbl_mask; input pad_yy_gate_clk_en_b; input pad_yy_test_mode; input tcipif_bmu_dbus_acc_err; input [31:0] tcipif_bmu_dbus_data; input tcipif_bmu_dbus_data_vld; input tcipif_bmu_dbus_grnt; input tcipif_bmu_dbus_trans_cmplt; input tcipif_bmu_ibus_acc_err; input [31:0] tcipif_bmu_ibus_data; input tcipif_bmu_ibus_data_vld; input tcipif_bmu_ibus_grnt; input tcipif_bmu_ibus_trans_cmplt; output bmu_biu_dbus_acc_deny; output [31:0] bmu_biu_dbus_addr; output bmu_biu_dbus_chk_fail; output [3 :0] bmu_biu_dbus_prot; output bmu_biu_dbus_req; output bmu_biu_dbus_req_without_cmplt; output [1 :0] bmu_biu_dbus_size; output [31:0] bmu_biu_dbus_wdata; output bmu_biu_dbus_write; output bmu_biu_ibus_acc_deny; output [31:0] bmu_biu_ibus_addr; output bmu_biu_ibus_hit; output [3 :0] bmu_biu_ibus_prot; output bmu_biu_ibus_req; output bmu_biu_ibus_req_no_hit; output [1 :0] bmu_biu_ibus_size; output bmu_biu_ibus_vec_redirect; output bmu_iahbl_dbus_acc_deny; output [31:0] bmu_iahbl_dbus_addr; output bmu_iahbl_dbus_chk_fail; output [3 :0] bmu_iahbl_dbus_prot; output bmu_iahbl_dbus_req; output bmu_iahbl_dbus_req_without_cmplt; output [1 :0] bmu_iahbl_dbus_size; output [31:0] bmu_iahbl_dbus_wdata; output bmu_iahbl_dbus_write; output bmu_iahbl_ibus_acc_deny; output [31:0] bmu_iahbl_ibus_addr; output bmu_iahbl_ibus_hit; output [3 :0] bmu_iahbl_ibus_prot; output bmu_iahbl_ibus_req; output bmu_iahbl_ibus_req_no_hit; output [1 :0] bmu_iahbl_ibus_size; output bmu_iahbl_ibus_vec_redirect; output bmu_lsu_acc_err; output bmu_lsu_bstack_chk_fail; output [31:0] bmu_lsu_data; output bmu_lsu_data_vld; output bmu_lsu_grnt; output bmu_lsu_trans_cmplt; output bmu_tcipif_dbus_acc_deny; output [31:0] bmu_tcipif_dbus_addr; output bmu_tcipif_dbus_chk_fail; output bmu_tcipif_dbus_req; output [1 :0] bmu_tcipif_dbus_size; output bmu_tcipif_dbus_supv_mode; output [31:0] bmu_tcipif_dbus_wdata; output bmu_tcipif_dbus_write; output bmu_tcipif_ibus_acc_deny; output [31:0] bmu_tcipif_ibus_addr; output bmu_tcipif_ibus_req; output bmu_tcipif_ibus_write; output bmu_xx_ibus_acc_err; output [31:0] bmu_xx_ibus_data; output bmu_xx_ibus_data_vld; output bmu_xx_ibus_grnt; output bmu_xx_ibus_trans_cmplt; wire biu_bmu_dbus_acc_err; wire [31:0] biu_bmu_dbus_data; wire biu_bmu_dbus_data_vld; wire biu_bmu_dbus_grnt; wire biu_bmu_dbus_trans_cmplt; wire biu_bmu_ibus_acc_err; wire [31:0] biu_bmu_ibus_data; wire biu_bmu_ibus_data_vld; wire biu_bmu_ibus_grnt; wire biu_bmu_ibus_trans_cmplt; wire bmu_biu_dbus_acc_deny; wire [31:0] bmu_biu_dbus_addr; wire bmu_biu_dbus_chk_fail; wire [3 :0] bmu_biu_dbus_prot; wire bmu_biu_dbus_req; wire bmu_biu_dbus_req_without_cmplt; wire [1 :0] bmu_biu_dbus_size; wire [31:0] bmu_biu_dbus_wdata; wire bmu_biu_dbus_write; wire bmu_biu_ibus_acc_deny; wire [31:0] bmu_biu_ibus_addr; wire bmu_biu_ibus_hit; wire [3 :0] bmu_biu_ibus_prot; wire bmu_biu_ibus_req; wire bmu_biu_ibus_req_no_hit; wire [1 :0] bmu_biu_ibus_size; wire bmu_biu_ibus_vec_redirect; wire bmu_iahbl_dbus_acc_deny; wire [31:0] bmu_iahbl_dbus_addr; wire bmu_iahbl_dbus_chk_fail; wire [3 :0] bmu_iahbl_dbus_prot; wire bmu_iahbl_dbus_req; wire bmu_iahbl_dbus_req_without_cmplt; wire [1 :0] bmu_iahbl_dbus_size; wire [31:0] bmu_iahbl_dbus_wdata; wire bmu_iahbl_dbus_write; wire bmu_iahbl_ibus_acc_deny; wire [31:0] bmu_iahbl_ibus_addr; wire bmu_iahbl_ibus_hit; wire [3 :0] bmu_iahbl_ibus_prot; wire bmu_iahbl_ibus_req; wire bmu_iahbl_ibus_req_no_hit; wire [1 :0] bmu_iahbl_ibus_size; wire bmu_iahbl_ibus_vec_redirect; wire bmu_lsu_acc_err; wire bmu_lsu_bstack_chk_fail; wire [31:0] bmu_lsu_data; wire bmu_lsu_data_vld; wire bmu_lsu_grnt; wire bmu_lsu_trans_cmplt; wire bmu_tcipif_dbus_acc_deny; wire [31:0] bmu_tcipif_dbus_addr; wire bmu_tcipif_dbus_chk_fail; wire bmu_tcipif_dbus_req; wire [1 :0] bmu_tcipif_dbus_size; wire bmu_tcipif_dbus_supv_mode; wire [31:0] bmu_tcipif_dbus_wdata; wire bmu_tcipif_dbus_write; wire bmu_tcipif_ibus_acc_deny; wire [31:0] bmu_tcipif_ibus_addr; wire bmu_tcipif_ibus_req; wire bmu_tcipif_ibus_write; wire bmu_xx_ibus_acc_err; wire [31:0] bmu_xx_ibus_data; wire bmu_xx_ibus_data_vld; wire bmu_xx_ibus_grnt; wire bmu_xx_ibus_trans_cmplt; wire cp0_yy_clk_en; wire cp0_yy_machine_mode_aft_dbg; wire cpurst_b; wire dbus_deny_clk_en; wire deny_clk; wire deny_en; wire forever_cpuclk; wire iahbl_bmu_dbus_acc_err; wire [31:0] iahbl_bmu_dbus_data; wire iahbl_bmu_dbus_data_vld; wire iahbl_bmu_dbus_grnt; wire iahbl_bmu_dbus_trans_cmplt; wire iahbl_bmu_ibus_acc_err; wire [31:0] iahbl_bmu_ibus_data; wire iahbl_bmu_ibus_data_vld; wire iahbl_bmu_ibus_grnt; wire iahbl_bmu_ibus_trans_cmplt; wire ibus_deny_clk_en; wire [31:0] ifu_bmu_addr; wire ifu_bmu_idle; wire [3 :0] ifu_bmu_prot; wire ifu_bmu_req; wire ifu_bmu_wfd1; wire iu_bmu_vec_redirect; wire [31:0] lsu_bmu_addr; wire lsu_bmu_addr_check_fail; wire lsu_bmu_idle; wire [3 :0] lsu_bmu_prot; wire lsu_bmu_req; wire lsu_bmu_req_without_cmplt; wire lsu_bmu_sg_chk_fail; wire [1 :0] lsu_bmu_size; wire lsu_bmu_store_error; wire [31:0] lsu_bmu_wdata; wire lsu_bmu_wfd1; wire lsu_bmu_write; wire [11:0] pad_bmu_iahbl_base; wire [11:0] pad_bmu_iahbl_mask; wire pad_yy_gate_clk_en_b; wire pad_yy_test_mode; wire tcipif_bmu_dbus_acc_err; wire [31:0] tcipif_bmu_dbus_data; wire tcipif_bmu_dbus_data_vld; wire tcipif_bmu_dbus_grnt; wire tcipif_bmu_dbus_trans_cmplt; wire tcipif_bmu_ibus_acc_err; wire [31:0] tcipif_bmu_ibus_data; wire tcipif_bmu_ibus_data_vld; wire tcipif_bmu_ibus_grnt; wire tcipif_bmu_ibus_trans_cmplt; assign deny_en = ibus_deny_clk_en || dbus_deny_clk_en; gated_clk_cell x_deny_gated_clk ( .clk_in (forever_cpuclk ), .clk_out (deny_clk ), .external_en (1'b0 ), .global_en (cp0_yy_clk_en ), .local_en (deny_en ), .module_en (1'b0 ), .pad_yy_gate_clk_en_b (pad_yy_gate_clk_en_b), .pad_yy_test_mode (pad_yy_test_mode ) ); cr_bmu_dbus_if x_cr_bmu_dbus_if ( .biu_bmu_dbus_acc_err (biu_bmu_dbus_acc_err ), .biu_bmu_dbus_data (biu_bmu_dbus_data ), .biu_bmu_dbus_data_vld (biu_bmu_dbus_data_vld ), .biu_bmu_dbus_grnt (biu_bmu_dbus_grnt ), .biu_bmu_dbus_trans_cmplt (biu_bmu_dbus_trans_cmplt ), .bmu_biu_dbus_acc_deny (bmu_biu_dbus_acc_deny ), .bmu_biu_dbus_addr (bmu_biu_dbus_addr ), .bmu_biu_dbus_chk_fail (bmu_biu_dbus_chk_fail ), .bmu_biu_dbus_prot (bmu_biu_dbus_prot ), .bmu_biu_dbus_req (bmu_biu_dbus_req ), .bmu_biu_dbus_req_without_cmplt (bmu_biu_dbus_req_without_cmplt ), .bmu_biu_dbus_size (bmu_biu_dbus_size ), .bmu_biu_dbus_wdata (bmu_biu_dbus_wdata ), .bmu_biu_dbus_write (bmu_biu_dbus_write ), .bmu_iahbl_dbus_acc_deny (bmu_iahbl_dbus_acc_deny ), .bmu_iahbl_dbus_addr (bmu_iahbl_dbus_addr ), .bmu_iahbl_dbus_chk_fail (bmu_iahbl_dbus_chk_fail ), .bmu_iahbl_dbus_prot (bmu_iahbl_dbus_prot ), .bmu_iahbl_dbus_req (bmu_iahbl_dbus_req ), .bmu_iahbl_dbus_req_without_cmplt (bmu_iahbl_dbus_req_without_cmplt), .bmu_iahbl_dbus_size (bmu_iahbl_dbus_size ), .bmu_iahbl_dbus_wdata (bmu_iahbl_dbus_wdata ), .bmu_iahbl_dbus_write (bmu_iahbl_dbus_write ), .bmu_lsu_acc_err (bmu_lsu_acc_err ), .bmu_lsu_bstack_chk_fail (bmu_lsu_bstack_chk_fail ), .bmu_lsu_data (bmu_lsu_data ), .bmu_lsu_data_vld (bmu_lsu_data_vld ), .bmu_lsu_grnt (bmu_lsu_grnt ), .bmu_lsu_trans_cmplt (bmu_lsu_trans_cmplt ), .bmu_tcipif_dbus_acc_deny (bmu_tcipif_dbus_acc_deny ), .bmu_tcipif_dbus_addr (bmu_tcipif_dbus_addr ), .bmu_tcipif_dbus_chk_fail (bmu_tcipif_dbus_chk_fail ), .bmu_tcipif_dbus_req (bmu_tcipif_dbus_req ), .bmu_tcipif_dbus_size (bmu_tcipif_dbus_size ), .bmu_tcipif_dbus_supv_mode (bmu_tcipif_dbus_supv_mode ), .bmu_tcipif_dbus_wdata (bmu_tcipif_dbus_wdata ), .bmu_tcipif_dbus_write (bmu_tcipif_dbus_write ), .cp0_yy_machine_mode_aft_dbg (cp0_yy_machine_mode_aft_dbg ), .cpurst_b (cpurst_b ), .dbus_deny_clk_en (dbus_deny_clk_en ), .deny_clk (deny_clk ), .iahbl_bmu_dbus_acc_err (iahbl_bmu_dbus_acc_err ), .iahbl_bmu_dbus_data (iahbl_bmu_dbus_data ), .iahbl_bmu_dbus_data_vld (iahbl_bmu_dbus_data_vld ), .iahbl_bmu_dbus_grnt (iahbl_bmu_dbus_grnt ), .iahbl_bmu_dbus_trans_cmplt (iahbl_bmu_dbus_trans_cmplt ), .lsu_bmu_addr (lsu_bmu_addr ), .lsu_bmu_addr_check_fail (lsu_bmu_addr_check_fail ), .lsu_bmu_idle (lsu_bmu_idle ), .lsu_bmu_prot (lsu_bmu_prot ), .lsu_bmu_req (lsu_bmu_req ), .lsu_bmu_req_without_cmplt (lsu_bmu_req_without_cmplt ), .lsu_bmu_sg_chk_fail (lsu_bmu_sg_chk_fail ), .lsu_bmu_size (lsu_bmu_size ), .lsu_bmu_store_error (lsu_bmu_store_error ), .lsu_bmu_wdata (lsu_bmu_wdata ), .lsu_bmu_wfd1 (lsu_bmu_wfd1 ), .lsu_bmu_write (lsu_bmu_write ), .pad_bmu_iahbl_base (pad_bmu_iahbl_base ), .pad_bmu_iahbl_mask (pad_bmu_iahbl_mask ), .pmp_bmu_dbus_acc_deny (1'b0 ), .tcipif_bmu_dbus_acc_err (tcipif_bmu_dbus_acc_err ), .tcipif_bmu_dbus_data (tcipif_bmu_dbus_data ), .tcipif_bmu_dbus_data_vld (tcipif_bmu_dbus_data_vld ), .tcipif_bmu_dbus_grnt (tcipif_bmu_dbus_grnt ), .tcipif_bmu_dbus_trans_cmplt (tcipif_bmu_dbus_trans_cmplt ) ); cr_bmu_ibus_if x_cr_bmu_ibus_if ( .biu_bmu_ibus_acc_err (biu_bmu_ibus_acc_err ), .biu_bmu_ibus_data (biu_bmu_ibus_data ), .biu_bmu_ibus_data_vld (biu_bmu_ibus_data_vld ), .biu_bmu_ibus_grnt (biu_bmu_ibus_grnt ), .biu_bmu_ibus_trans_cmplt (biu_bmu_ibus_trans_cmplt ), .bmu_biu_ibus_acc_deny (bmu_biu_ibus_acc_deny ), .bmu_biu_ibus_addr (bmu_biu_ibus_addr ), .bmu_biu_ibus_hit (bmu_biu_ibus_hit ), .bmu_biu_ibus_prot (bmu_biu_ibus_prot ), .bmu_biu_ibus_req (bmu_biu_ibus_req ), .bmu_biu_ibus_req_no_hit (bmu_biu_ibus_req_no_hit ), .bmu_biu_ibus_size (bmu_biu_ibus_size ), .bmu_biu_ibus_vec_redirect (bmu_biu_ibus_vec_redirect ), .bmu_iahbl_ibus_acc_deny (bmu_iahbl_ibus_acc_deny ), .bmu_iahbl_ibus_addr (bmu_iahbl_ibus_addr ), .bmu_iahbl_ibus_hit (bmu_iahbl_ibus_hit ), .bmu_iahbl_ibus_prot (bmu_iahbl_ibus_prot ), .bmu_iahbl_ibus_req (bmu_iahbl_ibus_req ), .bmu_iahbl_ibus_req_no_hit (bmu_iahbl_ibus_req_no_hit ), .bmu_iahbl_ibus_size (bmu_iahbl_ibus_size ), .bmu_iahbl_ibus_vec_redirect (bmu_iahbl_ibus_vec_redirect), .bmu_tcipif_ibus_acc_deny (bmu_tcipif_ibus_acc_deny ), .bmu_tcipif_ibus_addr (bmu_tcipif_ibus_addr ), .bmu_tcipif_ibus_req (bmu_tcipif_ibus_req ), .bmu_tcipif_ibus_write (bmu_tcipif_ibus_write ), .bmu_xx_ibus_acc_err (bmu_xx_ibus_acc_err ), .bmu_xx_ibus_data (bmu_xx_ibus_data ), .bmu_xx_ibus_data_vld (bmu_xx_ibus_data_vld ), .bmu_xx_ibus_grnt (bmu_xx_ibus_grnt ), .bmu_xx_ibus_trans_cmplt (bmu_xx_ibus_trans_cmplt ), .cpurst_b (cpurst_b ), .deny_clk (deny_clk ), .iahbl_bmu_ibus_acc_err (iahbl_bmu_ibus_acc_err ), .iahbl_bmu_ibus_data (iahbl_bmu_ibus_data ), .iahbl_bmu_ibus_data_vld (iahbl_bmu_ibus_data_vld ), .iahbl_bmu_ibus_grnt (iahbl_bmu_ibus_grnt ), .iahbl_bmu_ibus_trans_cmplt (iahbl_bmu_ibus_trans_cmplt ), .ibus_deny_clk_en (ibus_deny_clk_en ), .ifu_bmu_addr (ifu_bmu_addr ), .ifu_bmu_idle (ifu_bmu_idle ), .ifu_bmu_prot (ifu_bmu_prot ), .ifu_bmu_req (ifu_bmu_req ), .ifu_bmu_wfd1 (ifu_bmu_wfd1 ), .iu_bmu_vec_redirect (iu_bmu_vec_redirect ), .pad_bmu_iahbl_base (pad_bmu_iahbl_base ), .pad_bmu_iahbl_mask (pad_bmu_iahbl_mask ), .pmp_bmu_ibus_acc_deny (1'b0 ), .tcipif_bmu_ibus_acc_err (tcipif_bmu_ibus_acc_err ), .tcipif_bmu_ibus_data (tcipif_bmu_ibus_data ), .tcipif_bmu_ibus_data_vld (tcipif_bmu_ibus_data_vld ), .tcipif_bmu_ibus_grnt (tcipif_bmu_ibus_grnt ), .tcipif_bmu_ibus_trans_cmplt (tcipif_bmu_ibus_trans_cmplt) ); endmodule module cr_clic_arb( arb_ctrl_output_clk_en, clic_pad_int_hv, clic_pad_int_id, clic_pad_int_il, clic_pad_int_priv, cliccfg_cpuclk, cliccfg_data, clicth_data, clicthcfg_data, cpu_clic_curid, cpu_clic_int_exit, cpurst_b, ctrl_arb_int_sec, ctrl_arb_prio0_mask, ctrl_arb_prio10_mask, ctrl_arb_prio11_mask, ctrl_arb_prio12_mask, ctrl_arb_prio13_mask, ctrl_arb_prio14_mask, ctrl_arb_prio15_mask, ctrl_arb_prio1_mask, ctrl_arb_prio2_mask, ctrl_arb_prio3_mask, ctrl_arb_prio4_mask, ctrl_arb_prio5_mask, ctrl_arb_prio6_mask, ctrl_arb_prio7_mask, ctrl_arb_prio8_mask, ctrl_arb_prio9_mask, ctrl_xx_cliccfg_updt_val, ctrl_xx_cliccfg_updt_vld, ctrl_xx_clicth_updt_val, ctrl_xx_clicth_updt_vld, ctrl_xx_clicthcfg_hi_updt_vld, ctrl_xx_clicthcfg_lo_updt_vld, ctrl_xx_clicthcfg_updt_val, ctrl_xx_int_req, m_th_clr_clk_en, out_clk ); input cliccfg_cpuclk; input [9 :0] cpu_clic_curid; input cpu_clic_int_exit; input cpurst_b; input [63:0] ctrl_arb_int_sec; input [63:0] ctrl_arb_prio0_mask; input [63:0] ctrl_arb_prio10_mask; input [63:0] ctrl_arb_prio11_mask; input [63:0] ctrl_arb_prio12_mask; input [63:0] ctrl_arb_prio13_mask; input [63:0] ctrl_arb_prio14_mask; input [63:0] ctrl_arb_prio15_mask; input [63:0] ctrl_arb_prio1_mask; input [63:0] ctrl_arb_prio2_mask; input [63:0] ctrl_arb_prio3_mask; input [63:0] ctrl_arb_prio4_mask; input [63:0] ctrl_arb_prio5_mask; input [63:0] ctrl_arb_prio6_mask; input [63:0] ctrl_arb_prio7_mask; input [63:0] ctrl_arb_prio8_mask; input [63:0] ctrl_arb_prio9_mask; input [7 :0] ctrl_xx_cliccfg_updt_val; input ctrl_xx_cliccfg_updt_vld; input [7 :0] ctrl_xx_clicth_updt_val; input ctrl_xx_clicth_updt_vld; input ctrl_xx_clicthcfg_hi_updt_vld; input ctrl_xx_clicthcfg_lo_updt_vld; input [9 :0] ctrl_xx_clicthcfg_updt_val; input [63:0] ctrl_xx_int_req; input out_clk; output arb_ctrl_output_clk_en; output clic_pad_int_hv; output [9 :0] clic_pad_int_id; output [7 :0] clic_pad_int_il; output [1 :0] clic_pad_int_priv; output [7 :0] cliccfg_data; output [7 :0] clicth_data; output [9 :0] clicthcfg_data; output m_th_clr_clk_en; reg clic_pad_int_hv; reg [9 :0] clic_pad_int_id; reg [7 :0] clic_pad_int_il; reg [1 :0] clic_pad_int_priv; reg [9 :0] int_sel_id; reg int_vld_flop; reg [7 :0] m_th; reg [9 :0] m_thcfg; reg [5 :0] nlbits; reg [1 :0] nmbits; reg nvbits; reg [7 :0] post_8arb_int_levl; reg [63:0] post_8arb_int_req; reg [7 :0] sel_out_il; wire arb_ctrl_output_clk_en; wire cliccfg_cpuclk; wire [7 :0] cliccfg_data; wire [7 :0] clicth_data; wire [9 :0] clicthcfg_data; wire [9 :0] cpu_clic_curid; wire cpu_clic_int_exit; wire cpurst_b; wire [63:0] ctrl_arb_prio0_mask; wire [63:0] ctrl_arb_prio1_mask; wire [63:0] ctrl_arb_prio2_mask; wire [63:0] ctrl_arb_prio3_mask; wire [63:0] ctrl_arb_prio4_mask; wire [63:0] ctrl_arb_prio5_mask; wire [63:0] ctrl_arb_prio6_mask; wire [63:0] ctrl_arb_prio7_mask; wire [7 :0] ctrl_xx_cliccfg_updt_val; wire ctrl_xx_cliccfg_updt_vld; wire [7 :0] ctrl_xx_clicth_updt_val; wire ctrl_xx_clicth_updt_vld; wire ctrl_xx_clicthcfg_hi_updt_vld; wire ctrl_xx_clicthcfg_lo_updt_vld; wire [9 :0] ctrl_xx_clicthcfg_updt_val; wire [63:0] ctrl_xx_int_req; wire get_int_pri0_req; wire get_int_pri1_req; wire get_int_pri2_req; wire get_int_pri3_req; wire get_int_pri4_req; wire get_int_pri5_req; wire get_int_pri6_req; wire get_int_pri7_req; wire [7 :0] get_int_prio; wire int_flop_on; wire [63:0] int_prio0_req; wire [63:0] int_prio1_req; wire [63:0] int_prio2_req; wire [63:0] int_prio3_req; wire [63:0] int_prio4_req; wire [63:0] int_prio5_req; wire [63:0] int_prio6_req; wire [63:0] int_prio7_req; wire int_vld; wire m_th_clr; wire m_th_clr_clk_en; wire [1 :0] mode_mask; wire op_en; wire out_clk; wire pre_clic_pad_int_hv; wire [9 :0] pre_clic_pad_int_id; wire [7 :0] pre_clic_pad_int_il; wire [1 :0] pre_clic_pad_int_priv; wire [7 :0] sel_arb_int_levl; wire sel_arb_int_nvbit; wire [63:0] sel_arb_int_req; wire vld_int_vld; parameter CLICINTNUM = 64; parameter CLICMASK = 8; parameter CLICINTBITS = 3; parameter NLMASK = 3; assign int_prio0_req = ctrl_arb_prio0_mask[63:0] & ctrl_xx_int_req[63:0]; assign int_prio1_req = ctrl_arb_prio1_mask[63:0] & ctrl_xx_int_req[63:0]; assign int_prio2_req = ctrl_arb_prio2_mask[63:0] & ctrl_xx_int_req[63:0]; assign int_prio3_req = ctrl_arb_prio3_mask[63:0] & ctrl_xx_int_req[63:0]; assign int_prio4_req = ctrl_arb_prio4_mask[63:0] & ctrl_xx_int_req[63:0]; assign int_prio5_req = ctrl_arb_prio5_mask[63:0] & ctrl_xx_int_req[63:0]; assign int_prio6_req = ctrl_arb_prio6_mask[63:0] & ctrl_xx_int_req[63:0]; assign int_prio7_req = ctrl_arb_prio7_mask[63:0] & ctrl_xx_int_req[63:0]; assign get_int_pri0_req = (|int_prio0_req[CLICINTNUM-1:0]); assign get_int_pri1_req = (|int_prio1_req[CLICINTNUM-1:0]); assign get_int_pri2_req = (|int_prio2_req[CLICINTNUM-1:0]); assign get_int_pri3_req = (|int_prio3_req[CLICINTNUM-1:0]); assign get_int_pri4_req = (|int_prio4_req[CLICINTNUM-1:0]); assign get_int_pri5_req = (|int_prio5_req[CLICINTNUM-1:0]); assign get_int_pri6_req = (|int_prio6_req[CLICINTNUM-1:0]); assign get_int_pri7_req = (|int_prio7_req[CLICINTNUM-1:0]); assign int_vld = |ctrl_xx_int_req[63:0]; assign get_int_prio[7:0] = {get_int_pri7_req,get_int_pri6_req,get_int_pri5_req,get_int_pri4_req, get_int_pri3_req,get_int_pri2_req,get_int_pri1_req,get_int_pri0_req}; always @( int_prio1_req[63:0] or int_prio2_req[63:0] or get_int_prio[7:0] or int_prio5_req[63:0] or int_prio4_req[63:0] or int_prio7_req[63:0] or int_prio6_req[63:0] or int_prio3_req[63:0] or int_prio0_req[63:0]) begin casez(get_int_prio[7:0]) 8'b1???????: post_8arb_int_req[CLICINTNUM-1:0] = int_prio7_req[CLICINTNUM-1:0]; 8'b01??????: post_8arb_int_req[CLICINTNUM-1:0] = int_prio6_req[CLICINTNUM-1:0]; 8'b001?????: post_8arb_int_req[CLICINTNUM-1:0] = int_prio5_req[CLICINTNUM-1:0]; 8'b0001????: post_8arb_int_req[CLICINTNUM-1:0] = int_prio4_req[CLICINTNUM-1:0]; 8'b00001???: post_8arb_int_req[CLICINTNUM-1:0] = int_prio3_req[CLICINTNUM-1:0]; 8'b000001??: post_8arb_int_req[CLICINTNUM-1:0] = int_prio2_req[CLICINTNUM-1:0]; 8'b0000001?: post_8arb_int_req[CLICINTNUM-1:0] = int_prio1_req[CLICINTNUM-1:0]; 8'b00000001: post_8arb_int_req[CLICINTNUM-1:0] = int_prio0_req[CLICINTNUM-1:0]; default : post_8arb_int_req[CLICINTNUM-1:0] = int_prio0_req[CLICINTNUM-1:0]; endcase end always @( get_int_prio[7:0]) begin casez(get_int_prio[7:0]) 8'b1???????: post_8arb_int_levl[7:0] = {3'b111,5'b11111}; 8'b01??????: post_8arb_int_levl[7:0] = {3'b110,5'b11111}; 8'b001?????: post_8arb_int_levl[7:0] = {3'b101,5'b11111}; 8'b0001????: post_8arb_int_levl[7:0] = {3'b100,5'b11111}; 8'b00001???: post_8arb_int_levl[7:0] = {3'b011,5'b11111}; 8'b000001??: post_8arb_int_levl[7:0] = {3'b010,5'b11111}; 8'b0000001?: post_8arb_int_levl[7:0] = {3'b001,5'b11111}; 8'b00000001: post_8arb_int_levl[7:0] = {3'b000,5'b11111}; default: post_8arb_int_levl[7:0] = {3'b000,5'b11111}; endcase end assign sel_arb_int_req[CLICINTNUM-1:0] = post_8arb_int_req[CLICINTNUM-1:0]; assign sel_arb_int_levl[7:0] = post_8arb_int_levl[7:0]; assign sel_arb_int_nvbit = post_8arb_int_levl[5]; always @( sel_arb_int_req[63:0]) begin casez(sel_arb_int_req[63:0]) 64'b1???????????????????????????????????????????????????????????????:int_sel_id[9:0] = 10'h3F; 64'b01??????????????????????????????????????????????????????????????:int_sel_id[9:0] = 10'h3E; 64'b001?????????????????????????????????????????????????????????????:int_sel_id[9:0] = 10'h3D; 64'b0001????????????????????????????????????????????????????????????:int_sel_id[9:0] = 10'h3C; 64'b00001???????????????????????????????????????????????????????????:int_sel_id[9:0] = 10'h3B; 64'b000001??????????????????????????????????????????????????????????:int_sel_id[9:0] = 10'h3A; 64'b0000001?????????????????????????????????????????????????????????:int_sel_id[9:0] = 10'h39; 64'b00000001????????????????????????????????????????????????????????:int_sel_id[9:0] = 10'h38; 64'b000000001???????????????????????????????????????????????????????:int_sel_id[9:0] = 10'h37; 64'b0000000001??????????????????????????????????????????????????????:int_sel_id[9:0] = 10'h36; 64'b00000000001?????????????????????????????????????????????????????:int_sel_id[9:0] = 10'h35; 64'b000000000001????????????????????????????????????????????????????:int_sel_id[9:0] = 10'h34; 64'b0000000000001???????????????????????????????????????????????????:int_sel_id[9:0] = 10'h33; 64'b00000000000001??????????????????????????????????????????????????:int_sel_id[9:0] = 10'h32; 64'b000000000000001?????????????????????????????????????????????????:int_sel_id[9:0] = 10'h31; 64'b0000000000000001????????????????????????????????????????????????:int_sel_id[9:0] = 10'h30; 64'b00000000000000001???????????????????????????????????????????????:int_sel_id[9:0] = 10'h2F; 64'b000000000000000001??????????????????????????????????????????????:int_sel_id[9:0] = 10'h2E; 64'b0000000000000000001?????????????????????????????????????????????:int_sel_id[9:0] = 10'h2D; 64'b00000000000000000001????????????????????????????????????????????:int_sel_id[9:0] = 10'h2C; 64'b000000000000000000001???????????????????????????????????????????:int_sel_id[9:0] = 10'h2B; 64'b0000000000000000000001??????????????????????????????????????????:int_sel_id[9:0] = 10'h2A; 64'b00000000000000000000001?????????????????????????????????????????:int_sel_id[9:0] = 10'h29; 64'b000000000000000000000001????????????????????????????????????????:int_sel_id[9:0] = 10'h28; 64'b0000000000000000000000001???????????????????????????????????????:int_sel_id[9:0] = 10'h27; 64'b00000000000000000000000001??????????????????????????????????????:int_sel_id[9:0] = 10'h26; 64'b000000000000000000000000001?????????????????????????????????????:int_sel_id[9:0] = 10'h25; 64'b0000000000000000000000000001????????????????????????????????????:int_sel_id[9:0] = 10'h24; 64'b00000000000000000000000000001???????????????????????????????????:int_sel_id[9:0] = 10'h23; 64'b000000000000000000000000000001??????????????????????????????????:int_sel_id[9:0] = 10'h22; 64'b0000000000000000000000000000001?????????????????????????????????:int_sel_id[9:0] = 10'h21; 64'b00000000000000000000000000000001????????????????????????????????:int_sel_id[9:0] = 10'h20; 64'b000000000000000000000000000000001???????????????????????????????:int_sel_id[9:0] = 10'h1F; 64'b0000000000000000000000000000000001??????????????????????????????:int_sel_id[9:0] = 10'h1E; 64'b00000000000000000000000000000000001?????????????????????????????:int_sel_id[9:0] = 10'h1D; 64'b000000000000000000000000000000000001????????????????????????????:int_sel_id[9:0] = 10'h1C; 64'b0000000000000000000000000000000000001???????????????????????????:int_sel_id[9:0] = 10'h1B; 64'b00000000000000000000000000000000000001??????????????????????????:int_sel_id[9:0] = 10'h1A; 64'b000000000000000000000000000000000000001?????????????????????????:int_sel_id[9:0] = 10'h19; 64'b0000000000000000000000000000000000000001????????????????????????:int_sel_id[9:0] = 10'h18; 64'b00000000000000000000000000000000000000001???????????????????????:int_sel_id[9:0] = 10'h17; 64'b000000000000000000000000000000000000000001??????????????????????:int_sel_id[9:0] = 10'h16; 64'b0000000000000000000000000000000000000000001?????????????????????:int_sel_id[9:0] = 10'h15; 64'b00000000000000000000000000000000000000000001????????????????????:int_sel_id[9:0] = 10'h14; 64'b000000000000000000000000000000000000000000001???????????????????:int_sel_id[9:0] = 10'h13; 64'b0000000000000000000000000000000000000000000001??????????????????:int_sel_id[9:0] = 10'h12; 64'b00000000000000000000000000000000000000000000001?????????????????:int_sel_id[9:0] = 10'h11; 64'b000000000000000000000000000000000000000000000001????????????????:int_sel_id[9:0] = 10'h10; 64'b0000000000000000000000000000000000000000000000001???????????????:int_sel_id[9:0] = 10'h0F; 64'b00000000000000000000000000000000000000000000000001??????????????:int_sel_id[9:0] = 10'h0E; 64'b000000000000000000000000000000000000000000000000001?????????????:int_sel_id[9:0] = 10'h0D; 64'b0000000000000000000000000000000000000000000000000001????????????:int_sel_id[9:0] = 10'h0C; 64'b00000000000000000000000000000000000000000000000000001???????????:int_sel_id[9:0] = 10'h0B; 64'b000000000000000000000000000000000000000000000000000001??????????:int_sel_id[9:0] = 10'h0A; 64'b0000000000000000000000000000000000000000000000000000001?????????:int_sel_id[9:0] = 10'h09; 64'b00000000000000000000000000000000000000000000000000000001????????:int_sel_id[9:0] = 10'h08; 64'b000000000000000000000000000000000000000000000000000000001???????:int_sel_id[9:0] = 10'h07; 64'b0000000000000000000000000000000000000000000000000000000001??????:int_sel_id[9:0] = 10'h06; 64'b00000000000000000000000000000000000000000000000000000000001?????:int_sel_id[9:0] = 10'h05; 64'b000000000000000000000000000000000000000000000000000000000001????:int_sel_id[9:0] = 10'h04; 64'b0000000000000000000000000000000000000000000000000000000000001???:int_sel_id[9:0] = 10'h03; 64'b00000000000000000000000000000000000000000000000000000000000001??:int_sel_id[9:0] = 10'h02; 64'b000000000000000000000000000000000000000000000000000000000000001?:int_sel_id[9:0] = 10'h01; 64'b0000000000000000000000000000000000000000000000000000000000000001:int_sel_id[9:0] = 10'h00; default: int_sel_id[9:0] = 10'bx; endcase end always@(posedge cliccfg_cpuclk or negedge cpurst_b) begin if(!cpurst_b) begin nmbits[1:0] <= {2{1'b0}}; nlbits[3:0] <= {4{1'b0}}; nlbits[5:4] <= {2{1'b0}}; nvbits <= {1{1'b0}}; end else if(ctrl_xx_cliccfg_updt_vld && op_en)begin nmbits[1:0] <= ctrl_xx_cliccfg_updt_val[6:5] & mode_mask[1:0]; nlbits[3:0] <= ctrl_xx_cliccfg_updt_val[4:1] & NLMASK; nlbits[5:4] <= {2{1'b0}}; nvbits <= ctrl_xx_cliccfg_updt_val[0]; end end always@(posedge cliccfg_cpuclk or negedge cpurst_b) begin if(!cpurst_b) m_th[7:0] <= 8'b0; else if(ctrl_xx_clicth_updt_vld) m_th[7:0] <= ctrl_xx_clicth_updt_val[7:0]; else if(m_th_clr) m_th[7:0] <= 8'b0; end assign clicth_data[7:0] = m_th[7:0]; always@(posedge cliccfg_cpuclk or negedge cpurst_b) begin if(!cpurst_b) m_thcfg[7:0] <= 8'b0; else if(ctrl_xx_clicthcfg_lo_updt_vld) m_thcfg[7:0] <= ctrl_xx_clicthcfg_updt_val[7:0]; end always@(posedge cliccfg_cpuclk or negedge cpurst_b) begin if(!cpurst_b) m_thcfg[9:8] <= 2'b0; else if(ctrl_xx_clicthcfg_hi_updt_vld) m_thcfg[9:8] <= ctrl_xx_clicthcfg_updt_val[9:8]; end assign m_th_clr = (cpu_clic_int_exit && (cpu_clic_curid[9:0] == m_thcfg[9:0])); assign clicthcfg_data[9:0] = m_thcfg[9:0]; assign m_th_clr_clk_en = m_th_clr; assign op_en = 1'b1; assign mode_mask[1:0] = 2'b00; assign pre_clic_pad_int_priv[1:0] = 2'b11; assign pre_clic_pad_int_il[7:0] = {8{|sel_arb_int_req[CLICINTNUM-1:0]}} & sel_out_il[7:0]; always@(*) begin case(nlbits[3:0]) 4'd0: sel_out_il[7:0] = 8'hff; 4'd1: sel_out_il[7:0] = {sel_arb_int_levl[7],7'h7f}; 4'd2: sel_out_il[7:0] = {sel_arb_int_levl[7:6],6'h3f}; 4'd3: sel_out_il[7:0] = {sel_arb_int_levl[7:5],5'h1f}; default:sel_out_il[7:0] = {sel_arb_int_levl[7:5],5'h1f}; endcase end assign cliccfg_data[7:0] = {8{op_en}} & {1'b0,nmbits[1:0],nlbits[3:0],nvbits}; assign pre_clic_pad_int_hv = nvbits ? sel_arb_int_nvbit : 1'b0; assign pre_clic_pad_int_id[9:0] = int_sel_id[9:0]; always @(posedge out_clk or negedge cpurst_b) begin if(!cpurst_b) int_vld_flop <=1'b0; else int_vld_flop <= int_vld && vld_int_vld; end assign int_flop_on = int_vld_flop || int_vld && vld_int_vld; assign vld_int_vld = (pre_clic_pad_int_priv[1:0] == 2'b11) && (pre_clic_pad_int_il[7:0] > m_th[7:0]); always @(posedge out_clk or negedge cpurst_b) begin if(!cpurst_b) begin clic_pad_int_priv[1:0] <= 2'b00; clic_pad_int_il[7:0] <= 8'b0; clic_pad_int_id[9:0] <= 10'b0; clic_pad_int_hv <= 1'b0; end else if(int_flop_on) begin clic_pad_int_priv[1:0] <= pre_clic_pad_int_priv[1:0]; clic_pad_int_il[7:0] <= pre_clic_pad_int_il[7:0]; clic_pad_int_id[9:0] <= pre_clic_pad_int_id[9:0]; clic_pad_int_hv <= pre_clic_pad_int_hv; end end assign arb_ctrl_output_clk_en = int_flop_on; endmodule module cr_clic_kid( clicintie_updt_vld, cpurst_b, ctl_xx_prot_sec, int_enable_updt_val, int_sec_updt_val, intcfg_updt_value, intcfg_updt_vld, kid_arb_int_req, kid_arb_int_sec, kid_arb_pending_en, kid_arb_prio0_mask, kid_arb_prio10_mask, kid_arb_prio11_mask, kid_arb_prio12_mask, kid_arb_prio13_mask, kid_arb_prio14_mask, kid_arb_prio15_mask, kid_arb_prio1_mask, kid_arb_prio2_mask, kid_arb_prio3_mask, kid_arb_prio4_mask, kid_arb_prio5_mask, kid_arb_prio6_mask, kid_arb_prio7_mask, kid_arb_prio8_mask, kid_arb_prio9_mask, kid_arb_sample_en, kid_xx_ie, kid_xx_intcfg, kid_xx_ip, pad_clic_int_cfg, pad_clic_int_vld, pending_cpuclk, pri_cpuclk, regs_cpuclk, sample_cpuclk, sw_clear_pending, sw_set_pending ); input clicintie_updt_vld; input cpurst_b; input ctl_xx_prot_sec; input int_enable_updt_val; input int_sec_updt_val; input [7:0] intcfg_updt_value; input intcfg_updt_vld; input pad_clic_int_cfg; input pad_clic_int_vld; input pending_cpuclk; input pri_cpuclk; input regs_cpuclk; input sample_cpuclk; input sw_clear_pending; input sw_set_pending; output kid_arb_int_req; output kid_arb_int_sec; output kid_arb_pending_en; output kid_arb_prio0_mask; output kid_arb_prio10_mask; output kid_arb_prio11_mask; output kid_arb_prio12_mask; output kid_arb_prio13_mask; output kid_arb_prio14_mask; output kid_arb_prio15_mask; output kid_arb_prio1_mask; output kid_arb_prio2_mask; output kid_arb_prio3_mask; output kid_arb_prio4_mask; output kid_arb_prio5_mask; output kid_arb_prio6_mask; output kid_arb_prio7_mask; output kid_arb_prio8_mask; output kid_arb_prio9_mask; output kid_arb_sample_en; output [7:0] kid_xx_ie; output [7:0] kid_xx_intcfg; output [7:0] kid_xx_ip; reg int_enable; reg int_pending; reg int_pending_updt_val; reg [2:0] int_priority; reg int_vld_ff; wire clicintie_updt_vld; wire cpurst_b; wire int_cfg; wire int_enable_updt_val; wire int_enable_updt_vld; wire int_level; wire int_pending_updt_vld; wire int_pulse; wire int_vld; wire [7:0] intcfg_updt_value; wire intcfg_updt_vld; wire kid_arb_int_req; wire kid_arb_int_sec; wire kid_arb_pending_en; wire kid_arb_prio0_mask; wire kid_arb_prio10_mask; wire kid_arb_prio11_mask; wire kid_arb_prio12_mask; wire kid_arb_prio13_mask; wire kid_arb_prio14_mask; wire kid_arb_prio15_mask; wire kid_arb_prio1_mask; wire kid_arb_prio2_mask; wire kid_arb_prio3_mask; wire kid_arb_prio4_mask; wire kid_arb_prio5_mask; wire kid_arb_prio6_mask; wire kid_arb_prio7_mask; wire kid_arb_prio8_mask; wire kid_arb_prio9_mask; wire [7:0] kid_arb_prio_mask; wire kid_arb_sample_en; wire [7:0] kid_xx_ie; wire [7:0] kid_xx_intcfg; wire [7:0] kid_xx_ip; wire op_en; wire pad_clic_int_cfg; wire pad_clic_int_vld; wire pending_clear; wire pending_cpuclk; wire pending_set; wire pri_cpuclk; wire regs_cpuclk; wire sample_cpuclk; wire sw_clear_pending; wire sw_set_pending; parameter CLICMASK = 8; parameter CLICINTBITS = 3; assign int_vld = pad_clic_int_vld; assign int_cfg = pad_clic_int_cfg; assign int_level = int_vld && !int_cfg; assign kid_arb_sample_en = (int_vld ^ int_vld_ff); always@(posedge sample_cpuclk or negedge cpurst_b) begin if(!cpurst_b) int_vld_ff <= 1'b0; else int_vld_ff <= int_vld; end assign int_pulse = int_vld && !int_vld_ff; assign op_en = 1'b1; assign int_enable_updt_vld = op_en && clicintie_updt_vld; always@(posedge regs_cpuclk or negedge cpurst_b) begin if(!cpurst_b) int_enable <= 1'b0; else if(int_enable_updt_vld) int_enable <= int_enable_updt_val; else int_enable <= int_enable; end assign pending_set = op_en && (sw_set_pending) && int_cfg || int_pulse && int_cfg || int_level ; assign pending_clear = op_en && sw_clear_pending && int_cfg || (!int_cfg && !int_vld); assign kid_arb_pending_en = !int_pending & pending_set || int_pending & pending_clear & !pending_set; assign int_pending_updt_vld = pending_set || pending_clear; always @( pending_set or pending_clear or int_pending) begin if (pending_set) int_pending_updt_val = 1'b1; else if (pending_clear) int_pending_updt_val = 1'b0; else int_pending_updt_val = int_pending; end always@(posedge pending_cpuclk or negedge cpurst_b) begin if (!cpurst_b) int_pending <= 1'b0; else if (int_pending_updt_vld) int_pending <= int_pending_updt_val; else int_pending <= int_pending; end always@(posedge pri_cpuclk or negedge cpurst_b) begin if(!cpurst_b) int_priority[CLICINTBITS-1:0] <= {CLICINTBITS{1'b0}}; else if(intcfg_updt_vld && op_en) int_priority[CLICINTBITS-1:0] <= intcfg_updt_value[7:8-CLICINTBITS]; end assign kid_arb_int_req = int_enable & int_pending; assign kid_arb_int_sec = 1'b0; assign kid_arb_prio_mask[CLICMASK-1:0] = 1'b1 << ({int_priority[CLICINTBITS-1:0]}); assign kid_arb_prio0_mask = kid_arb_prio_mask[0]; assign kid_arb_prio1_mask = kid_arb_prio_mask[1]; assign kid_arb_prio2_mask = kid_arb_prio_mask[2]; assign kid_arb_prio3_mask = kid_arb_prio_mask[3]; assign kid_arb_prio4_mask = kid_arb_prio_mask[4]; assign kid_arb_prio5_mask = kid_arb_prio_mask[5]; assign kid_arb_prio6_mask = kid_arb_prio_mask[6]; assign kid_arb_prio7_mask = kid_arb_prio_mask[7]; assign kid_arb_prio8_mask = 1'b0; assign kid_arb_prio9_mask = 1'b0; assign kid_arb_prio10_mask = 1'b0; assign kid_arb_prio11_mask = 1'b0; assign kid_arb_prio12_mask = 1'b0; assign kid_arb_prio13_mask = 1'b0; assign kid_arb_prio14_mask = 1'b0; assign kid_arb_prio15_mask = 1'b0; assign kid_xx_ie[7:0] = {7'b0,int_enable && op_en}; assign kid_xx_ip[7:0] = {7'b0,int_pending && op_en}; assign kid_xx_intcfg[7:0] = {int_priority[CLICINTBITS-1:0] & {CLICINTBITS{op_en}},{(8-CLICINTBITS){1'b1}}&{(8-CLICINTBITS){op_en}}}; endmodule module cr_clic_reg_if( clic_tcipif_cmplt, clic_tcipif_rdata, cliccfg_data, clicth_data, clicthcfg_data, ctrl_xx_cliccfg_updt_val, ctrl_xx_cliccfg_updt_vld, ctrl_xx_clicth_updt_val, ctrl_xx_clicth_updt_vld, ctrl_xx_clicthcfg_hi_updt_vld, ctrl_xx_clicthcfg_lo_updt_vld, ctrl_xx_clicthcfg_updt_val, ctrl_xx_clicthcfg_updt_vld, ctrl_xx_intcfg_updt_val, ctrl_xx_intcfg_updt_vld, ctrl_xx_intie_updt_val, ctrl_xx_intie_updt_vld, ctrl_xx_intip_sw_clear_pending, ctrl_xx_intip_sw_set_pending, ctrl_xx_intip_updt_vld, ctrl_xx_intsec_updt_val, ctrl_xx_prot_sec, intcfg_read_data_0, intcfg_read_data_1, intcfg_read_data_10, intcfg_read_data_11, intcfg_read_data_12, intcfg_read_data_13, intcfg_read_data_14, intcfg_read_data_15, intcfg_read_data_2, intcfg_read_data_3, intcfg_read_data_4, intcfg_read_data_5, intcfg_read_data_6, intcfg_read_data_7, intcfg_read_data_8, intcfg_read_data_9, intie_read_data_0, intie_read_data_1, intie_read_data_10, intie_read_data_11, intie_read_data_12, intie_read_data_13, intie_read_data_14, intie_read_data_15, intie_read_data_2, intie_read_data_3, intie_read_data_4, intie_read_data_5, intie_read_data_6, intie_read_data_7, intie_read_data_8, intie_read_data_9, intip_read_data_0, intip_read_data_1, intip_read_data_10, intip_read_data_11, intip_read_data_12, intip_read_data_13, intip_read_data_14, intip_read_data_15, intip_read_data_2, intip_read_data_3, intip_read_data_4, intip_read_data_5, intip_read_data_6, intip_read_data_7, intip_read_data_8, intip_read_data_9, tcipif_clic_addr, tcipif_clic_sel, tcipif_clic_size, tcipif_clic_wdata, tcipif_clic_write ); input [7 :0] cliccfg_data; input [7 :0] clicth_data; input [9 :0] clicthcfg_data; input [31 :0] intcfg_read_data_0; input [31 :0] intcfg_read_data_1; input [31 :0] intcfg_read_data_10; input [31 :0] intcfg_read_data_11; input [31 :0] intcfg_read_data_12; input [31 :0] intcfg_read_data_13; input [31 :0] intcfg_read_data_14; input [31 :0] intcfg_read_data_15; input [31 :0] intcfg_read_data_2; input [31 :0] intcfg_read_data_3; input [31 :0] intcfg_read_data_4; input [31 :0] intcfg_read_data_5; input [31 :0] intcfg_read_data_6; input [31 :0] intcfg_read_data_7; input [31 :0] intcfg_read_data_8; input [31 :0] intcfg_read_data_9; input [31 :0] intie_read_data_0; input [31 :0] intie_read_data_1; input [31 :0] intie_read_data_10; input [31 :0] intie_read_data_11; input [31 :0] intie_read_data_12; input [31 :0] intie_read_data_13; input [31 :0] intie_read_data_14; input [31 :0] intie_read_data_15; input [31 :0] intie_read_data_2; input [31 :0] intie_read_data_3; input [31 :0] intie_read_data_4; input [31 :0] intie_read_data_5; input [31 :0] intie_read_data_6; input [31 :0] intie_read_data_7; input [31 :0] intie_read_data_8; input [31 :0] intie_read_data_9; input [31 :0] intip_read_data_0; input [31 :0] intip_read_data_1; input [31 :0] intip_read_data_10; input [31 :0] intip_read_data_11; input [31 :0] intip_read_data_12; input [31 :0] intip_read_data_13; input [31 :0] intip_read_data_14; input [31 :0] intip_read_data_15; input [31 :0] intip_read_data_2; input [31 :0] intip_read_data_3; input [31 :0] intip_read_data_4; input [31 :0] intip_read_data_5; input [31 :0] intip_read_data_6; input [31 :0] intip_read_data_7; input [31 :0] intip_read_data_8; input [31 :0] intip_read_data_9; input [15 :0] tcipif_clic_addr; input tcipif_clic_sel; input [1 :0] tcipif_clic_size; input [31 :0] tcipif_clic_wdata; input tcipif_clic_write; output clic_tcipif_cmplt; output [31 :0] clic_tcipif_rdata; output [7 :0] ctrl_xx_cliccfg_updt_val; output ctrl_xx_cliccfg_updt_vld; output [7 :0] ctrl_xx_clicth_updt_val; output ctrl_xx_clicth_updt_vld; output ctrl_xx_clicthcfg_hi_updt_vld; output ctrl_xx_clicthcfg_lo_updt_vld; output [9 :0] ctrl_xx_clicthcfg_updt_val; output ctrl_xx_clicthcfg_updt_vld; output [511:0] ctrl_xx_intcfg_updt_val; output [63 :0] ctrl_xx_intcfg_updt_vld; output [63 :0] ctrl_xx_intie_updt_val; output [63 :0] ctrl_xx_intie_updt_vld; output [63 :0] ctrl_xx_intip_sw_clear_pending; output [63 :0] ctrl_xx_intip_sw_set_pending; output [15 :0] ctrl_xx_intip_updt_vld; output [63 :0] ctrl_xx_intsec_updt_val; output ctrl_xx_prot_sec; reg [3 :0] ctrl_reg_size_msk; wire [31 :0] clic_intcfg_rdata; wire [31 :0] clic_intie_rdata; wire [31 :0] clic_intip_rdata; wire clic_tcipif_cmplt; wire [31 :0] clic_tcipif_rdata; wire [7 :0] cliccfg_data; wire [31 :0] cliccfg_rdata; wire clicintcfg_rd_sel; wire clicintcfg_wr_sel; wire clicintie_rd_sel; wire clicintie_wr_sel; wire clicintip_rd_sel; wire clicintip_wr_sel; wire [7 :0] clicth_data; wire [31 :0] clicth_rdata; wire [9 :0] clicthcfg_data; wire [31 :0] clicthcfg_rdata; wire [11 :0] ctrl_reg_addr; wire ctrl_xx_cliccfg_read_vld; wire [7 :0] ctrl_xx_cliccfg_updt_val; wire ctrl_xx_cliccfg_updt_vld; wire ctrl_xx_clicth_read_vld; wire [7 :0] ctrl_xx_clicth_updt_val; wire ctrl_xx_clicth_updt_vld; wire ctrl_xx_clicthcfg_hi_updt_vld; wire ctrl_xx_clicthcfg_lo_updt_vld; wire ctrl_xx_clicthcfg_read_vld; wire [9 :0] ctrl_xx_clicthcfg_updt_val; wire ctrl_xx_clicthcfg_updt_vld; wire [15 :0] ctrl_xx_intcfg_read_vld; wire [15 :0] ctrl_xx_intie_read_vld; wire [15 :0] ctrl_xx_intip_read_vld; wire ctrl_xx_prot_sec; wire [31 :0] intcfg_read_data_0; wire [31 :0] intcfg_read_data_1; wire [31 :0] intcfg_read_data_10; wire [31 :0] intcfg_read_data_11; wire [31 :0] intcfg_read_data_12; wire [31 :0] intcfg_read_data_13; wire [31 :0] intcfg_read_data_14; wire [31 :0] intcfg_read_data_15; wire [31 :0] intcfg_read_data_2; wire [31 :0] intcfg_read_data_3; wire [31 :0] intcfg_read_data_4; wire [31 :0] intcfg_read_data_5; wire [31 :0] intcfg_read_data_6; wire [31 :0] intcfg_read_data_7; wire [31 :0] intcfg_read_data_8; wire [31 :0] intcfg_read_data_9; wire [31 :0] intie_read_data_0; wire [31 :0] intie_read_data_1; wire [31 :0] intie_read_data_10; wire [31 :0] intie_read_data_11; wire [31 :0] intie_read_data_12; wire [31 :0] intie_read_data_13; wire [31 :0] intie_read_data_14; wire [31 :0] intie_read_data_15; wire [31 :0] intie_read_data_2; wire [31 :0] intie_read_data_3; wire [31 :0] intie_read_data_4; wire [31 :0] intie_read_data_5; wire [31 :0] intie_read_data_6; wire [31 :0] intie_read_data_7; wire [31 :0] intie_read_data_8; wire [31 :0] intie_read_data_9; wire [31 :0] intip_read_data_0; wire [31 :0] intip_read_data_1; wire [31 :0] intip_read_data_10; wire [31 :0] intip_read_data_11; wire [31 :0] intip_read_data_12; wire [31 :0] intip_read_data_13; wire [31 :0] intip_read_data_14; wire [31 :0] intip_read_data_15; wire [31 :0] intip_read_data_2; wire [31 :0] intip_read_data_3; wire [31 :0] intip_read_data_4; wire [31 :0] intip_read_data_5; wire [31 :0] intip_read_data_6; wire [31 :0] intip_read_data_7; wire [31 :0] intip_read_data_8; wire [31 :0] intip_read_data_9; wire [15 :0] tcipif_clic_addr; wire tcipif_clic_sel; wire [1 :0] tcipif_clic_size; wire [31 :0] tcipif_clic_wdata; wire tcipif_clic_write; parameter CLICINTIP_BASE = 2'b00; parameter CLICINTIE_BASE = 2'b01; parameter CLICINTCFG_BASE = 2'b10; parameter CLICCFG = 10'h300; parameter CLICTH = 10'h301; parameter CLICTHCFG = 10'h302; parameter CLICINTNUM = 64; assign clic_tcipif_cmplt = tcipif_clic_sel; assign ctrl_reg_addr[11:0] = {12{tcipif_clic_sel}} & tcipif_clic_addr[11:0]; assign clicintip_wr_sel = tcipif_clic_write && (ctrl_reg_addr[11:10] == CLICINTIP_BASE); assign clicintie_wr_sel = tcipif_clic_write && (ctrl_reg_addr[11:10] == CLICINTIE_BASE); assign clicintcfg_wr_sel = tcipif_clic_write && (ctrl_reg_addr[11:10] == CLICINTCFG_BASE); assign clicintip_rd_sel = !tcipif_clic_write && (ctrl_reg_addr[11:10] == CLICINTIP_BASE); assign clicintie_rd_sel = !tcipif_clic_write && (ctrl_reg_addr[11:10] == CLICINTIE_BASE); assign clicintcfg_rd_sel = !tcipif_clic_write && (ctrl_reg_addr[11:10] == CLICINTCFG_BASE); always @( ctrl_reg_addr[1:0] or tcipif_clic_size[1:0]) begin casez({ctrl_reg_addr[1:0],tcipif_clic_size[1:0]}) 4'b0000:ctrl_reg_size_msk[3:0] = 4'b0001; 4'b0100:ctrl_reg_size_msk[3:0] = 4'b0010; 4'b1000:ctrl_reg_size_msk[3:0] = 4'b0100; 4'b1100:ctrl_reg_size_msk[3:0] = 4'b1000; 4'b0?01:ctrl_reg_size_msk[3:0] = 4'b0011; 4'b1?01:ctrl_reg_size_msk[3:0] = 4'b1100; 4'b??10:ctrl_reg_size_msk[3:0] = 4'b1111; default:ctrl_reg_size_msk[3:0] = 4'b1111; endcase end wire [CLICINTNUM-1:0] ctrl_xx_intie_updt_vld; wire [CLICINTNUM-1:0] ctrl_xx_intie_updt_val; wire [CLICINTNUM-1:0] ctrl_xx_intsec_updt_val; wire [CLICINTNUM/4-1:0] ctrl_xx_intip_updt_vld; wire [CLICINTNUM-1:0] ctrl_xx_intip_sw_clear_pending; wire [CLICINTNUM-1:0] ctrl_xx_intip_sw_set_pending; wire [CLICINTNUM-1:0] ctrl_xx_intcfg_updt_vld; wire [CLICINTNUM*8-1:0] ctrl_xx_intcfg_updt_val; genvar i; generate for(i=0;i mpil[7:0]) && (iu_yy_xx_int_pending_priv[1:0] == 2'b11) && !iu_yy_xx_int_pending_hv; assign mnxti_vld_int_pending = vld_int_pending; assign mpil[7:0] = status_oreg_mpil[7:0]; assign mtval_expt_update[31:0] = (iu_cp0_int_vld || iu_cp0_ecall && iu_cp0_ex_sel) ? 32'b0 : iui_oreg_expt ? iui_oreg_tval[31:0] : iu_cp0_expt_tval[31:0]; always @(posedge oreg_clk or negedge cpurst_b) begin if(!cpurst_b) mtval_value[31:0] <= 32'b0; else if(iu_cp0_mtval_updt_vld) mtval_value[31:0] <= mtval_expt_update[31:0]; else if(mtval_local_en) mtval_value[31:0] <= iui_oreg_rs1[31:0]; else mtval_value[31:0] <= mtval_value[31:0]; end always @(posedge oreg_clk or negedge cpurst_b) begin if(!cpurst_b) nt_meie <= 1'b0; else if((mode[1] == 1'b0) && nt_mie_local_en) nt_meie <= iui_oreg_rs1[11]; else nt_meie <= nt_meie; end assign mie_value[31:0] = mode[1] ? 32'b0 : {20'b0, nt_meie, 3'b0, 1'b0 , 3'b0, 1'b0, 3'b0}; assign meie = nt_meie; assign nt_meip = iu_cp0_nt_int_pending_vld && (mode[1] == 1'b0); assign mip_value[31:0] = mode[1] ? 32'b0 : {20'b0, nt_meip, 3'b0, 1'b0 , 3'b0, 1'b0, 3'b0}; assign pad_cpu_secu_dbg_en = 1'b0; always @(posedge forever_cpuclk or negedge cpurst_b) begin if(!cpurst_b) mcycle[63:0] <= 64'b0; else if(mcycle_local_en) mcycle[63:0] <= {mcycle[63:32], iui_oreg_rs1[31:0]}; else if(mcycleh_local_en) mcycle[63:0] <= {iui_oreg_rs1[31:0], mcycle[31:0]}; else mcycle[63:0] <= mcycle[63:0] + 1'b1; end assign mcycle_value[31:0] = mcycle[31:0]; assign mcycleh_value[31:0] = mcycle[63:32]; assign minstret_value[31:0] = 32'b0; assign minstreth_value[31:0] = 32'b0; assign mvendorid_value[31:0] = 32'h5B7; assign mimpid_value[31:0] = 32'b0; assign mhartid_value[31:0] = 32'b0; assign marchid_value[31:0] = 32'b0; assign index_max = (index[1:0] == 2'd2); assign index_next_val[1:0] = (index_max) ? 2'd0 : index[1:0] + 2'd1; assign mcpuid_wen = iui_oreg_csr_acc && iu_cp0_syc_rst_b && ((oreg_iui_priv_mode[1:0] == 2'b11) || iu_yy_xx_dbgon); always @(posedge oreg_clk or negedge cpurst_b) begin if(!cpurst_b) begin index[1:0] <= 2'b0; end else if (mcpuid_wen && mcpuid_local_en) begin index[1:0] <= index_next_val[1:0]; end else begin index[1:0] <= index[1:0]; end end always @( cpuid_index1_value[31:0] or cpuid_index0_value[31:0] or index[1:0] or cpuid_index2_value[31:0]) begin case(index[1:0]) 2'b00 : cpuid_value[31:0] = cpuid_index0_value[31:0]; 2'b01 : cpuid_value[31:0] = cpuid_index1_value[31:0]; 2'b10 : cpuid_value[31:0] = cpuid_index2_value[31:0]; default : cpuid_value[31:0] = 32'bx; endcase end assign cpuid_index0_value[31:28] = 4'b0000; assign cpuid_index0_value[27:26] = 2'b10; assign cpuid_index0_value[25:22] = 4'b0000; assign cpuid_index0_value[21:18] = 4'b0001; assign cpuid_index0_value[17:10] = 8'b0; assign cpuid_index0_value[9] = 1'b0; assign cpuid_index0_value[8] = 1'b0; assign cpuid_index0_value[7:3] = 5'b00001; assign cpuid_index0_value[2:0] = 3'b100; assign cpuid_index1_value[31:28] = 4'b0001; assign cpuid_index1_value[27:24] = 4'b0; assign cpuid_index1_value[23:16] = 8'b0; assign cpuid_index1_value[15:0] = `PRODUCT_ID; assign cpuid_index2_value[31:28] = 4'b0010; assign cpuid_index2_value[27:26] = 2'b01; assign cpuid_index2_value[25:24] = 2'b00; assign cpuid_index2_value[23:21] = 3'b001; assign cpuid_index2_value[20:16] = 5'b0; assign cpuid_index2_value[15:12] = 4'b0100; assign cpuid_index2_value[11:9] = 3'b0; assign cpuid_index2_value[8:6] = 3'b0; assign cpuid_index2_value[5:3] = 3'b111; assign cpuid_index2_value[2:0] = 3'b0; assign mcpuid_value[31:0] = cpuid_value[31:0]; assign cp0_iu_meie = meie; assign vector[9:0] = status_oreg_vector[9:0]; assign intr = status_oreg_intr; always @(posedge oreg_clk or negedge cpurst_b) begin if(!cpurst_b) int_hv <= 1'b0; else if(iu_cp0_expt_vld) int_hv <= iu_yy_xx_int_hv; else int_hv <= int_hv; end always @( intr or vec_adder_vbr[29:0] or base[29:0] or mode[1:0] or int_hv) begin case({intr,mode[1:0]}) 3'b100:cp0_iu_vbr[29:0] = base[29:0]; 3'b101:cp0_iu_vbr[29:0] = vec_adder_vbr[29:0]; 3'b110:cp0_iu_vbr[29:0] = int_hv ? vec_adder_vbr[29:0] : {base[29:4],4'b0}; 3'b111:cp0_iu_vbr[29:0] = vec_adder_vbr[29:0]; 3'b000:cp0_iu_vbr[29:0] = base[29:0]; 3'b001:cp0_iu_vbr[29:0] = base[29:0]; 3'b010:cp0_iu_vbr[29:0] = {base[29:4],4'b0}; 3'b011:cp0_iu_vbr[29:0] = {base[29:4],4'b0}; endcase end assign vec_adder_base[29:0] = mode[1] ? {mtvt[25:0],4'b0} : base[29:0]; assign vec_adder_vec[9:0] = mode[1] ? vld_int_pending ? iu_yy_xx_int_pending_id[9:0] : vector[9:0] : {6'b0,vector[3:0]}; assign vec_adder_vbr[29:0] = vec_adder_base[29:0] + vec_adder_vec[9:0]; assign hv_base[29:0] = vec_adder_vbr[29:0]; assign cp0_vector_vec_err_vbr[29:0] = {base[29:4],4'b0}; assign cp0_iu_epc_for_chgflw[30:0] = mepc[30:0]; assign oreg_status_mode[1:0] = mode[1:0]; assign cp0_iu_vec_mode[1:0] = mode[1:0]; assign mxstatus_t = status_oreg_mxstatus_t; assign cp0_had_cpuid_idx0[31:0] = cpuid_index0_value[31:0]; assign cp0_pad_psr[31:0] = mstatus_value[31:0]; assign cp0_yy_be_v1 = 1'b0; assign cp0_yy_be_v2 = 1'b0; endmodule module cr_cp0_randclk( randclk_psr_mod_en_w13 ); output randclk_psr_mod_en_w13; wire randclk_psr_mod_en_w13; assign randclk_psr_mod_en_w13 = 1'b0; endmodule module cr_cp0_status( cp0_had_int_exit, cp0_had_mcause_data, cp0_iu_il, cp0_iu_mie_for_int, cp0_pad_mintstatus, cp0_pad_mstatus, cp0_yy_machine_mode_aft_dbg, cp0_yy_priv_mode, cpu_clic_curid, cpu_clic_int_exit, cpurst_b, iu_cp0_expt_vld, iu_cp0_int_vld, iu_cp0_syc_rst_b, iu_yy_xx_dbgon, iu_yy_xx_expt_vec, iu_yy_xx_int_hv, iu_yy_xx_int_il, iu_yy_xx_int_pending_id, iu_yy_xx_int_pending_il, iui_oreg_imm, iui_oreg_inst_csr, iui_oreg_inst_mret, iui_oreg_rd_x0, iui_oreg_rs1, iui_oreg_rs1_x0, mcause_value, mintstatus_value, mnxti_vld_int_pending, mstatus_value, oreg_clk, oreg_iui_priv_mode, oreg_status_mode, status_oreg_intr, status_oreg_mpil, status_oreg_mxstatus_t, status_oreg_vector, vector_cp0_vec_succeed ); input cpurst_b; input iu_cp0_expt_vld; input iu_cp0_int_vld; input iu_cp0_syc_rst_b; input iu_yy_xx_dbgon; input [9 :0] iu_yy_xx_expt_vec; input iu_yy_xx_int_hv; input [7 :0] iu_yy_xx_int_il; input [9 :0] iu_yy_xx_int_pending_id; input [7 :0] iu_yy_xx_int_pending_il; input [11:0] iui_oreg_imm; input iui_oreg_inst_csr; input iui_oreg_inst_mret; input iui_oreg_rd_x0; input [31:0] iui_oreg_rs1; input iui_oreg_rs1_x0; input mnxti_vld_int_pending; input oreg_clk; input [1 :0] oreg_status_mode; input vector_cp0_vec_succeed; output cp0_had_int_exit; output [31:0] cp0_had_mcause_data; output [7 :0] cp0_iu_il; output cp0_iu_mie_for_int; output [31:0] cp0_pad_mintstatus; output [31:0] cp0_pad_mstatus; output cp0_yy_machine_mode_aft_dbg; output [1 :0] cp0_yy_priv_mode; output [9 :0] cpu_clic_curid; output cpu_clic_int_exit; output [31:0] mcause_value; output [31:0] mintstatus_value; output [31:0] mstatus_value; output [1 :0] oreg_iui_priv_mode; output status_oreg_intr; output [7 :0] status_oreg_mpil; output status_oreg_mxstatus_t; output [9 :0] status_oreg_vector; reg intr; reg mie; reg [7 :0] mil; reg minhv; reg mpie; reg [7 :0] mpil; reg mprv; reg [1 :0] pm; reg [9 :0] vector; wire cp0_had_int_exit; wire [31:0] cp0_had_mcause_data; wire [7 :0] cp0_iu_il; wire cp0_iu_mie_for_int; wire [31:0] cp0_pad_mintstatus; wire [31:0] cp0_pad_mstatus; wire cp0_yy_machine_mode_aft_dbg; wire [1 :0] cp0_yy_priv_mode; wire [9 :0] cpu_clic_curid; wire cpu_clic_int_exit; wire cpurst_b; wire csr_wen; wire hw_vector_clic_on; wire iu_cp0_expt_vld; wire iu_cp0_int_vld; wire iu_cp0_syc_rst_b; wire iu_yy_xx_dbgon; wire [9 :0] iu_yy_xx_expt_vec; wire iu_yy_xx_int_hv; wire [7 :0] iu_yy_xx_int_il; wire [9 :0] iu_yy_xx_int_pending_id; wire [7 :0] iu_yy_xx_int_pending_il; wire [11:0] iui_oreg_imm; wire iui_oreg_inst_csr; wire iui_oreg_inst_mret; wire iui_oreg_rd_x0; wire [31:0] iui_oreg_rs1; wire iui_oreg_rs1_x0; wire mcause_local_en; wire [31:0] mcause_value; wire [31:0] mintstatus_value; wire mnxti_local_en; wire mnxti_mstatus_local_en; wire mnxti_vld_int_pending; wire [1 :0] mode; wire [1 :0] mpp; wire mstatus_local_en; wire [31:0] mstatus_value; wire mxstatus_t; wire oreg_clk; wire [1 :0] oreg_iui_priv_mode; wire [1 :0] oreg_status_mode; wire status_oreg_intr; wire [7 :0] status_oreg_mpil; wire status_oreg_mxstatus_t; wire [9 :0] status_oreg_vector; wire vector_cp0_vec_succeed; parameter MSTATUS = 12'h300; parameter MCAUSE = 12'h342; parameter MNXTI = 12'h345; assign csr_wen = iui_oreg_inst_csr && iu_cp0_syc_rst_b && ((pm[1:0] == 2'b11) || iu_yy_xx_dbgon); assign mstatus_local_en = (csr_wen && iui_oreg_imm[11:0] == MSTATUS) || (mnxti_mstatus_local_en); assign mnxti_local_en = mnxti_mstatus_local_en && !iui_oreg_rd_x0; assign mnxti_mstatus_local_en = csr_wen && (iui_oreg_imm[11:0] == MNXTI) && !iui_oreg_rs1_x0; assign mode[1:0] = oreg_status_mode[1:0]; assign mcause_local_en = csr_wen && iui_oreg_imm[11:0] == MCAUSE; always @(posedge oreg_clk or negedge cpurst_b) begin if(!cpurst_b) mpie <= 1'b0; else if(mstatus_local_en && iu_cp0_int_vld) mpie <= iui_oreg_rs1[3]; else if(iui_oreg_inst_mret && iu_cp0_int_vld) mpie <= mpie; else if(iu_cp0_expt_vld) mpie <= mie; else if(iui_oreg_inst_mret) mpie <= 1'b1; else if(mstatus_local_en) mpie <= iui_oreg_rs1[7]; else if((mode[1]==1'b1) && mcause_local_en) mpie <=iui_oreg_rs1[27]; else mpie <= mpie; end assign mpp[1:0] = 2'b11; always @(posedge oreg_clk or negedge cpurst_b) begin if(!cpurst_b) mprv <= 1'b0; else mprv <= mprv; end always @(posedge oreg_clk or negedge cpurst_b) begin if(!cpurst_b) pm[1:0] <= 2'b11; else if(iu_cp0_expt_vld) pm[1:0] <= 2'b11; else if(iui_oreg_inst_mret) pm[1:0] <= mpp[1:0]; else pm[1:0] <= pm[1:0]; end always @(posedge oreg_clk or negedge cpurst_b) begin if(!cpurst_b) mie <= 1'b0; else if(iu_cp0_expt_vld) mie <= 1'b0; else if(iui_oreg_inst_mret) mie <= mpie; else if(mstatus_local_en) mie <= iui_oreg_rs1[3]; else mie <= mie; end assign mstatus_value[31:0] = {13'b0,1'b0,mprv,4'b0,mpp[1:0],3'b0, mpie, 3'b0, mie, 3'b0}; always @(posedge oreg_clk or negedge cpurst_b) begin if(!cpurst_b) intr <= 1'b0; else if(iu_cp0_int_vld) intr <= 1'b1; else if(iu_cp0_expt_vld) intr <= 1'b0; else if(mcause_local_en) intr <= iui_oreg_rs1[31]; else intr <= intr; end assign status_oreg_intr = intr; always @(posedge oreg_clk or negedge cpurst_b) begin if(!cpurst_b) vector[9:0] <= 9'b0; else if(iu_cp0_expt_vld) vector[9:0] <= {iu_yy_xx_expt_vec[9:0]}; else if(mcause_local_en) vector[9:0] <= (mode[1]==1'b1) ? iui_oreg_rs1[9:0] : {6'b0,iui_oreg_rs1[3:0]}; else if(mnxti_local_en && mnxti_vld_int_pending && (mode[1:0]==2'b10)) vector[9:0] <= iu_yy_xx_int_pending_id[9:0]; else vector[9:0] <= vector[9:0]; end assign status_oreg_vector[9:0] = (mode[1]==1'b1) ? vector[9:0] :{6'b0,vector[3:0]}; always @(posedge oreg_clk or negedge cpurst_b) begin if(!cpurst_b) minhv <= 1'b0; else if(mode[1]==1'b0) minhv <=1'b0; else if(mcause_local_en) minhv <= iui_oreg_rs1[30]; else if(hw_vector_clic_on) minhv <= 1'b1; else if(vector_cp0_vec_succeed) minhv <= 1'b0; end assign hw_vector_clic_on = ((mode[1:0]==2'b11) || iu_yy_xx_int_hv) && iu_cp0_int_vld; always @(posedge oreg_clk or negedge cpurst_b) begin if(!cpurst_b) mpil[7:0] <= 8'b0; else if(mode[1]==1'b0) mpil[7:0] <= 8'b0; else if(iu_cp0_int_vld ) mpil[7:0] <= mil[7:0]; else if(mcause_local_en) mpil[7:0] <= iui_oreg_rs1[23:16]; else mpil[7:0] <= mpil[7:0]; end assign status_oreg_mpil[7:0] = mpil[7:0]; assign mcause_value[31:0] = mode[1] ? {intr, minhv, mpp[1:0], mpie, 3'b0, mpil[7:0], 6'b0, vector[9:0]} : {intr,27'b0,vector[3:0]}; always @(posedge oreg_clk or negedge cpurst_b) begin if(!cpurst_b) mil[7:0] <= 8'b0; else if(mode[1]==1'b0) mil[7:0] <= 8'b0; else if(iu_cp0_int_vld) mil[7:0] <= iu_yy_xx_int_il[7:0]; else if(iui_oreg_inst_mret && intr) mil[7:0] <= mpil[7:0]; else if(mnxti_local_en && (mode[1:0]==2'b10) && mnxti_vld_int_pending) mil[7:0] <= iu_yy_xx_int_pending_il[7:0]; else mil[7:0] <= mil[7:0]; end assign mintstatus_value[31:0] = {mil[7:0],24'b0}; assign cp0_iu_mie_for_int = mie || (pm[1:0] != 2'b11); assign cp0_iu_il[7:0] = mil[7:0]; assign cp0_yy_priv_mode[1:0] = pm[1:0]; assign cp0_yy_machine_mode_aft_dbg = pm[0]; assign cp0_had_mcause_data[31:0] = 32'b0; assign cp0_had_int_exit = 1'b0; assign cp0_pad_mstatus[31:0] = mstatus_value[31:0]; assign cp0_pad_mintstatus[31:0] = mintstatus_value[31:0]; assign status_oreg_mxstatus_t = mxstatus_t; assign oreg_iui_priv_mode[1:0] = pm[1:0]; assign mxstatus_t = 1'b0; assign cpu_clic_int_exit = intr && iui_oreg_inst_mret; assign cpu_clic_curid[9:0] = vector[9:0]; endmodule module cr_cp0_top( cache_cp0_lpmd_ack, cp0_cache_lpmd_req, cp0_had_cpuid_idx0, cp0_had_int_exit, cp0_had_lpmd_b, cp0_had_mcause_data, cp0_ifu_in_lpmd, cp0_ifu_lpmd_req, cp0_iu_data, cp0_iu_data_vld, cp0_iu_dbg_disable_for_tee, cp0_iu_epc_for_chgflw, cp0_iu_expt_vec, cp0_iu_expt_vld, cp0_iu_flush, cp0_iu_flush_chgflw_vld, cp0_iu_il, cp0_iu_meie, cp0_iu_mie_for_int, cp0_iu_req, cp0_iu_rte_chgflw_vld, cp0_iu_rte_chgflw_vld_for_data, cp0_iu_stall, cp0_iu_vbr, cp0_iu_vec_mode, cp0_pad_mintstatus, cp0_pad_mstatus, cp0_pad_psr, cp0_sysio_ipend_b, cp0_sysio_lpmd_b, cp0_vector_vec_err_vbr, cp0_yy_be_v1, cp0_yy_be_v2, cp0_yy_clk_en, cp0_yy_machine_mode_aft_dbg, cp0_yy_priv_mode, cpu_clic_curid, cpu_clic_int_exit, cpurst_b, forever_cpuclk, had_iu_force_dbg_en, had_yy_xx_dbg, ifu_cp0_lpmd_ack, iu_cp0_ecall, iu_cp0_epc, iu_cp0_epc_update, iu_cp0_ex_csrrc, iu_cp0_ex_csrrci, iu_cp0_ex_csrrs, iu_cp0_ex_csrrsi, iu_cp0_ex_csrrw, iu_cp0_ex_csrrwi, iu_cp0_ex_data_sel, iu_cp0_ex_func3, iu_cp0_ex_mret, iu_cp0_ex_rd_reg, iu_cp0_ex_rs1_reg, iu_cp0_ex_sel, iu_cp0_ex_wfi, iu_cp0_expt_tval, iu_cp0_expt_vld, iu_cp0_imm, iu_cp0_int_vld, iu_cp0_lp_wk_int, iu_cp0_mtval_updt_vld, iu_cp0_nt_int_pending_vld, iu_cp0_oper_mux_en, iu_cp0_rs1, iu_cp0_syc_rst_b, iu_yy_xx_dbgon, iu_yy_xx_expt_vec, iu_yy_xx_flush, iu_yy_xx_int_hv, iu_yy_xx_int_il, iu_yy_xx_int_pending_hv, iu_yy_xx_int_pending_id, iu_yy_xx_int_pending_il, iu_yy_xx_int_pending_priv, pad_yy_gate_clk_en_b, pad_yy_test_mode, sysio_cp0_bigend, sysio_cp0_clkratio, sysio_cp0_endian_v2, sysio_cp0_sys_view_lpmd_b, vector_cp0_vec_err, vector_cp0_vec_err_epc, vector_cp0_vec_succeed ); input cache_cp0_lpmd_ack; input cpurst_b; input forever_cpuclk; input had_iu_force_dbg_en; input had_yy_xx_dbg; input ifu_cp0_lpmd_ack; input iu_cp0_ecall; input [30:0] iu_cp0_epc; input iu_cp0_epc_update; input iu_cp0_ex_csrrc; input iu_cp0_ex_csrrci; input iu_cp0_ex_csrrs; input iu_cp0_ex_csrrsi; input iu_cp0_ex_csrrw; input iu_cp0_ex_csrrwi; input iu_cp0_ex_data_sel; input [2 :0] iu_cp0_ex_func3; input iu_cp0_ex_mret; input [4 :0] iu_cp0_ex_rd_reg; input [4 :0] iu_cp0_ex_rs1_reg; input iu_cp0_ex_sel; input iu_cp0_ex_wfi; input [31:0] iu_cp0_expt_tval; input iu_cp0_expt_vld; input [11:0] iu_cp0_imm; input iu_cp0_int_vld; input iu_cp0_lp_wk_int; input iu_cp0_mtval_updt_vld; input iu_cp0_nt_int_pending_vld; input iu_cp0_oper_mux_en; input [31:0] iu_cp0_rs1; input iu_cp0_syc_rst_b; input iu_yy_xx_dbgon; input [9 :0] iu_yy_xx_expt_vec; input iu_yy_xx_flush; input iu_yy_xx_int_hv; input [7 :0] iu_yy_xx_int_il; input iu_yy_xx_int_pending_hv; input [9 :0] iu_yy_xx_int_pending_id; input [7 :0] iu_yy_xx_int_pending_il; input [1 :0] iu_yy_xx_int_pending_priv; input pad_yy_gate_clk_en_b; input pad_yy_test_mode; input sysio_cp0_bigend; input [2 :0] sysio_cp0_clkratio; input sysio_cp0_endian_v2; input [1 :0] sysio_cp0_sys_view_lpmd_b; input vector_cp0_vec_err; input [29:0] vector_cp0_vec_err_epc; input vector_cp0_vec_succeed; output cp0_cache_lpmd_req; output [31:0] cp0_had_cpuid_idx0; output cp0_had_int_exit; output [1 :0] cp0_had_lpmd_b; output [31:0] cp0_had_mcause_data; output cp0_ifu_in_lpmd; output cp0_ifu_lpmd_req; output [31:0] cp0_iu_data; output cp0_iu_data_vld; output cp0_iu_dbg_disable_for_tee; output [30:0] cp0_iu_epc_for_chgflw; output [4 :0] cp0_iu_expt_vec; output cp0_iu_expt_vld; output cp0_iu_flush; output cp0_iu_flush_chgflw_vld; output [7 :0] cp0_iu_il; output cp0_iu_meie; output cp0_iu_mie_for_int; output cp0_iu_req; output cp0_iu_rte_chgflw_vld; output cp0_iu_rte_chgflw_vld_for_data; output cp0_iu_stall; output [29:0] cp0_iu_vbr; output [1 :0] cp0_iu_vec_mode; output [31:0] cp0_pad_mintstatus; output [31:0] cp0_pad_mstatus; output [31:0] cp0_pad_psr; output cp0_sysio_ipend_b; output [1 :0] cp0_sysio_lpmd_b; output [29:0] cp0_vector_vec_err_vbr; output cp0_yy_be_v1; output cp0_yy_be_v2; output cp0_yy_clk_en; output cp0_yy_machine_mode_aft_dbg; output [1 :0] cp0_yy_priv_mode; output [9 :0] cpu_clic_curid; output cpu_clic_int_exit; wire cache_cp0_lpmd_ack; wire cp0_cache_lpmd_req; wire [31:0] cp0_had_cpuid_idx0; wire cp0_had_int_exit; wire [1 :0] cp0_had_lpmd_b; wire [31:0] cp0_had_mcause_data; wire cp0_ifu_in_lpmd; wire cp0_ifu_lpmd_req; wire [31:0] cp0_iu_data; wire cp0_iu_data_vld; wire cp0_iu_dbg_disable_for_tee; wire [30:0] cp0_iu_epc_for_chgflw; wire [4 :0] cp0_iu_expt_vec; wire cp0_iu_expt_vld; wire cp0_iu_flush; wire cp0_iu_flush_chgflw_vld; wire [7 :0] cp0_iu_il; wire cp0_iu_meie; wire cp0_iu_mie_for_int; wire cp0_iu_req; wire cp0_iu_rte_chgflw_vld; wire cp0_iu_rte_chgflw_vld_for_data; wire cp0_iu_stall; wire [29:0] cp0_iu_vbr; wire [1 :0] cp0_iu_vec_mode; wire [31:0] cp0_pad_mintstatus; wire [31:0] cp0_pad_mstatus; wire [31:0] cp0_pad_psr; wire cp0_sysio_ipend_b; wire [1 :0] cp0_sysio_lpmd_b; wire [29:0] cp0_vector_vec_err_vbr; wire cp0_yy_be_v1; wire cp0_yy_be_v2; wire cp0_yy_clk_en; wire cp0_yy_machine_mode_aft_dbg; wire [1 :0] cp0_yy_priv_mode; wire [9 :0] cpu_clic_curid; wire cpu_clic_int_exit; wire cpurst_b; wire forever_cpuclk; wire had_iu_force_dbg_en; wire had_yy_xx_dbg; wire ifu_cp0_lpmd_ack; wire inst_lpmd; wire iu_cp0_ecall; wire [30:0] iu_cp0_epc; wire iu_cp0_epc_update; wire iu_cp0_ex_csrrc; wire iu_cp0_ex_csrrci; wire iu_cp0_ex_csrrs; wire iu_cp0_ex_csrrsi; wire iu_cp0_ex_csrrw; wire iu_cp0_ex_csrrwi; wire iu_cp0_ex_data_sel; wire [2 :0] iu_cp0_ex_func3; wire iu_cp0_ex_mret; wire [4 :0] iu_cp0_ex_rd_reg; wire [4 :0] iu_cp0_ex_rs1_reg; wire iu_cp0_ex_sel; wire iu_cp0_ex_wfi; wire [31:0] iu_cp0_expt_tval; wire iu_cp0_expt_vld; wire [11:0] iu_cp0_imm; wire iu_cp0_int_vld; wire iu_cp0_lp_wk_int; wire iu_cp0_mtval_updt_vld; wire iu_cp0_nt_int_pending_vld; wire iu_cp0_oper_mux_en; wire [31:0] iu_cp0_rs1; wire iu_cp0_syc_rst_b; wire iu_yy_xx_dbgon; wire [9 :0] iu_yy_xx_expt_vec; wire iu_yy_xx_flush; wire iu_yy_xx_int_hv; wire [7 :0] iu_yy_xx_int_il; wire iu_yy_xx_int_pending_hv; wire [9 :0] iu_yy_xx_int_pending_id; wire [7 :0] iu_yy_xx_int_pending_il; wire [1 :0] iu_yy_xx_int_pending_priv; wire iui_lpmd_inst_lpmd_for_data; wire iui_oreg_csr_acc; wire iui_oreg_expt; wire [11:0] iui_oreg_imm; wire iui_oreg_inst_csr; wire iui_oreg_inst_mret; wire iui_oreg_rd_x0; wire [31:0] iui_oreg_rs1; wire iui_oreg_rs1_x0; wire [31:0] iui_oreg_tval; wire lpmd_iui_stall; wire lpmd_sm_clk; wire lpmd_sm_clk_en; wire [31:0] marchid_value; wire [31:0] mcause_value; wire [31:0] mcpuid_value; wire [31:0] mcycle_value; wire [31:0] mcycleh_value; wire [31:0] mepc_value; wire [31:0] mhartid_value; wire [31:0] mie_value; wire [31:0] mimpid_value; wire [31:0] minstret_value; wire [31:0] minstreth_value; wire [31:0] mintstatus_value; wire [31:0] mip_value; wire [31:0] misa_value; wire [31:0] mnxti_value; wire mnxti_vld_int_pending; wire [31:0] mscratch_value; wire [31:0] mstatus_value; wire [31:0] mtval_value; wire [31:0] mtvec_value; wire [31:0] mtvt_value; wire [31:0] mvendorid_value; wire oreg_clk; wire oreg_clk_en; wire [1 :0] oreg_iui_priv_mode; wire oreg_iui_wr_rdonly; wire [1 :0] oreg_status_mode; wire pad_yy_gate_clk_en_b; wire pad_yy_test_mode; wire psr_oreg_lpmd_sm_clk; wire psr_oreg_lpmd_sm_clk_en; wire randclk_psr_mod_en_w13; wire status_oreg_intr; wire [7 :0] status_oreg_mpil; wire status_oreg_mxstatus_t; wire [9 :0] status_oreg_vector; wire sysio_cp0_bigend; wire [2 :0] sysio_cp0_clkratio; wire sysio_cp0_endian_v2; wire [1 :0] sysio_cp0_sys_view_lpmd_b; wire vector_cp0_vec_err; wire [29:0] vector_cp0_vec_err_epc; wire vector_cp0_vec_succeed; assign psr_oreg_lpmd_sm_clk_en = oreg_clk_en || lpmd_sm_clk_en; gated_clk_cell x_psr_lpmd_gated_clk ( .clk_in (forever_cpuclk ), .clk_out (psr_oreg_lpmd_sm_clk ), .external_en (1'b0 ), .global_en (cp0_yy_clk_en ), .local_en (psr_oreg_lpmd_sm_clk_en), .module_en (randclk_psr_mod_en_w13 ), .pad_yy_gate_clk_en_b (pad_yy_gate_clk_en_b ), .pad_yy_test_mode (pad_yy_test_mode ) ); assign oreg_clk = psr_oreg_lpmd_sm_clk; assign lpmd_sm_clk = psr_oreg_lpmd_sm_clk; cr_cp0_iui x_cr_cp0_iui ( .cp0_iu_data (cp0_iu_data ), .cp0_iu_data_vld (cp0_iu_data_vld ), .cp0_iu_dbg_disable_for_tee (cp0_iu_dbg_disable_for_tee ), .cp0_iu_expt_vec (cp0_iu_expt_vec ), .cp0_iu_expt_vld (cp0_iu_expt_vld ), .cp0_iu_flush (cp0_iu_flush ), .cp0_iu_flush_chgflw_vld (cp0_iu_flush_chgflw_vld ), .cp0_iu_req (cp0_iu_req ), .cp0_iu_rte_chgflw_vld (cp0_iu_rte_chgflw_vld ), .cp0_iu_rte_chgflw_vld_for_data (cp0_iu_rte_chgflw_vld_for_data), .cp0_iu_stall (cp0_iu_stall ), .inst_lpmd (inst_lpmd ), .iu_cp0_ex_csrrc (iu_cp0_ex_csrrc ), .iu_cp0_ex_csrrci (iu_cp0_ex_csrrci ), .iu_cp0_ex_csrrs (iu_cp0_ex_csrrs ), .iu_cp0_ex_csrrsi (iu_cp0_ex_csrrsi ), .iu_cp0_ex_csrrw (iu_cp0_ex_csrrw ), .iu_cp0_ex_csrrwi (iu_cp0_ex_csrrwi ), .iu_cp0_ex_data_sel (iu_cp0_ex_data_sel ), .iu_cp0_ex_func3 (iu_cp0_ex_func3 ), .iu_cp0_ex_mret (iu_cp0_ex_mret ), .iu_cp0_ex_rd_reg (iu_cp0_ex_rd_reg ), .iu_cp0_ex_rs1_reg (iu_cp0_ex_rs1_reg ), .iu_cp0_ex_sel (iu_cp0_ex_sel ), .iu_cp0_ex_wfi (iu_cp0_ex_wfi ), .iu_cp0_imm (iu_cp0_imm ), .iu_cp0_oper_mux_en (iu_cp0_oper_mux_en ), .iu_cp0_rs1 (iu_cp0_rs1 ), .iu_cp0_syc_rst_b (iu_cp0_syc_rst_b ), .iu_yy_xx_dbgon (iu_yy_xx_dbgon ), .iui_lpmd_inst_lpmd_for_data (iui_lpmd_inst_lpmd_for_data ), .iui_oreg_csr_acc (iui_oreg_csr_acc ), .iui_oreg_expt (iui_oreg_expt ), .iui_oreg_imm (iui_oreg_imm ), .iui_oreg_inst_csr (iui_oreg_inst_csr ), .iui_oreg_inst_mret (iui_oreg_inst_mret ), .iui_oreg_rd_x0 (iui_oreg_rd_x0 ), .iui_oreg_rs1 (iui_oreg_rs1 ), .iui_oreg_rs1_x0 (iui_oreg_rs1_x0 ), .iui_oreg_tval (iui_oreg_tval ), .lpmd_iui_stall (lpmd_iui_stall ), .marchid_value (marchid_value ), .mcause_value (mcause_value ), .mcpuid_value (mcpuid_value ), .mcycle_value (mcycle_value ), .mcycleh_value (mcycleh_value ), .mepc_value (mepc_value ), .mhartid_value (mhartid_value ), .mie_value (mie_value ), .mimpid_value (mimpid_value ), .minstret_value (minstret_value ), .minstreth_value (minstreth_value ), .mintstatus_value (mintstatus_value ), .mip_value (mip_value ), .misa_value (misa_value ), .mnxti_value (mnxti_value ), .mscratch_value (mscratch_value ), .mstatus_value (mstatus_value ), .mtval_value (mtval_value ), .mtvec_value (mtvec_value ), .mtvt_value (mtvt_value ), .mvendorid_value (mvendorid_value ), .oreg_iui_priv_mode (oreg_iui_priv_mode ), .oreg_iui_wr_rdonly (oreg_iui_wr_rdonly ) ); cr_cp0_oreg x_cr_cp0_oreg ( .cp0_had_cpuid_idx0 (cp0_had_cpuid_idx0 ), .cp0_iu_epc_for_chgflw (cp0_iu_epc_for_chgflw ), .cp0_iu_meie (cp0_iu_meie ), .cp0_iu_vbr (cp0_iu_vbr ), .cp0_iu_vec_mode (cp0_iu_vec_mode ), .cp0_pad_psr (cp0_pad_psr ), .cp0_vector_vec_err_vbr (cp0_vector_vec_err_vbr ), .cp0_yy_be_v1 (cp0_yy_be_v1 ), .cp0_yy_be_v2 (cp0_yy_be_v2 ), .cpurst_b (cpurst_b ), .forever_cpuclk (forever_cpuclk ), .had_iu_force_dbg_en (had_iu_force_dbg_en ), .iu_cp0_ecall (iu_cp0_ecall ), .iu_cp0_epc (iu_cp0_epc ), .iu_cp0_epc_update (iu_cp0_epc_update ), .iu_cp0_ex_sel (iu_cp0_ex_sel ), .iu_cp0_expt_tval (iu_cp0_expt_tval ), .iu_cp0_expt_vld (iu_cp0_expt_vld ), .iu_cp0_int_vld (iu_cp0_int_vld ), .iu_cp0_mtval_updt_vld (iu_cp0_mtval_updt_vld ), .iu_cp0_nt_int_pending_vld (iu_cp0_nt_int_pending_vld), .iu_cp0_syc_rst_b (iu_cp0_syc_rst_b ), .iu_yy_xx_dbgon (iu_yy_xx_dbgon ), .iu_yy_xx_int_hv (iu_yy_xx_int_hv ), .iu_yy_xx_int_pending_hv (iu_yy_xx_int_pending_hv ), .iu_yy_xx_int_pending_id (iu_yy_xx_int_pending_id ), .iu_yy_xx_int_pending_il (iu_yy_xx_int_pending_il ), .iu_yy_xx_int_pending_priv (iu_yy_xx_int_pending_priv), .iui_oreg_csr_acc (iui_oreg_csr_acc ), .iui_oreg_expt (iui_oreg_expt ), .iui_oreg_imm (iui_oreg_imm ), .iui_oreg_inst_csr (iui_oreg_inst_csr ), .iui_oreg_inst_mret (iui_oreg_inst_mret ), .iui_oreg_rs1 (iui_oreg_rs1 ), .iui_oreg_tval (iui_oreg_tval ), .marchid_value (marchid_value ), .mcpuid_value (mcpuid_value ), .mcycle_value (mcycle_value ), .mcycleh_value (mcycleh_value ), .mepc_value (mepc_value ), .mhartid_value (mhartid_value ), .mie_value (mie_value ), .mimpid_value (mimpid_value ), .minstret_value (minstret_value ), .minstreth_value (minstreth_value ), .mip_value (mip_value ), .misa_value (misa_value ), .mnxti_value (mnxti_value ), .mnxti_vld_int_pending (mnxti_vld_int_pending ), .mscratch_value (mscratch_value ), .mstatus_value (mstatus_value ), .mtval_value (mtval_value ), .mtvec_value (mtvec_value ), .mtvt_value (mtvt_value ), .mvendorid_value (mvendorid_value ), .oreg_clk (oreg_clk ), .oreg_clk_en (oreg_clk_en ), .oreg_iui_priv_mode (oreg_iui_priv_mode ), .oreg_iui_wr_rdonly (oreg_iui_wr_rdonly ), .oreg_status_mode (oreg_status_mode ), .status_oreg_intr (status_oreg_intr ), .status_oreg_mpil (status_oreg_mpil ), .status_oreg_mxstatus_t (status_oreg_mxstatus_t ), .status_oreg_vector (status_oreg_vector ), .sysio_cp0_bigend (sysio_cp0_bigend ), .sysio_cp0_clkratio (sysio_cp0_clkratio ), .sysio_cp0_endian_v2 (sysio_cp0_endian_v2 ), .vector_cp0_vec_err (vector_cp0_vec_err ), .vector_cp0_vec_err_epc (vector_cp0_vec_err_epc ), .vector_cp0_vec_succeed (vector_cp0_vec_succeed ) ); cr_cp0_status x_cr_cp0_status ( .cp0_had_int_exit (cp0_had_int_exit ), .cp0_had_mcause_data (cp0_had_mcause_data ), .cp0_iu_il (cp0_iu_il ), .cp0_iu_mie_for_int (cp0_iu_mie_for_int ), .cp0_pad_mintstatus (cp0_pad_mintstatus ), .cp0_pad_mstatus (cp0_pad_mstatus ), .cp0_yy_machine_mode_aft_dbg (cp0_yy_machine_mode_aft_dbg), .cp0_yy_priv_mode (cp0_yy_priv_mode ), .cpu_clic_curid (cpu_clic_curid ), .cpu_clic_int_exit (cpu_clic_int_exit ), .cpurst_b (cpurst_b ), .iu_cp0_expt_vld (iu_cp0_expt_vld ), .iu_cp0_int_vld (iu_cp0_int_vld ), .iu_cp0_syc_rst_b (iu_cp0_syc_rst_b ), .iu_yy_xx_dbgon (iu_yy_xx_dbgon ), .iu_yy_xx_expt_vec (iu_yy_xx_expt_vec ), .iu_yy_xx_int_hv (iu_yy_xx_int_hv ), .iu_yy_xx_int_il (iu_yy_xx_int_il ), .iu_yy_xx_int_pending_id (iu_yy_xx_int_pending_id ), .iu_yy_xx_int_pending_il (iu_yy_xx_int_pending_il ), .iui_oreg_imm (iui_oreg_imm ), .iui_oreg_inst_csr (iui_oreg_inst_csr ), .iui_oreg_inst_mret (iui_oreg_inst_mret ), .iui_oreg_rd_x0 (iui_oreg_rd_x0 ), .iui_oreg_rs1 (iui_oreg_rs1 ), .iui_oreg_rs1_x0 (iui_oreg_rs1_x0 ), .mcause_value (mcause_value ), .mintstatus_value (mintstatus_value ), .mnxti_vld_int_pending (mnxti_vld_int_pending ), .mstatus_value (mstatus_value ), .oreg_clk (oreg_clk ), .oreg_iui_priv_mode (oreg_iui_priv_mode ), .oreg_status_mode (oreg_status_mode ), .status_oreg_intr (status_oreg_intr ), .status_oreg_mpil (status_oreg_mpil ), .status_oreg_mxstatus_t (status_oreg_mxstatus_t ), .status_oreg_vector (status_oreg_vector ), .vector_cp0_vec_succeed (vector_cp0_vec_succeed ) ); cr_cp0_lpmd x_cr_cp0_lpmd ( .cache_cp0_lpmd_ack (cache_cp0_lpmd_ack ), .cp0_cache_lpmd_req (cp0_cache_lpmd_req ), .cp0_had_lpmd_b (cp0_had_lpmd_b ), .cp0_ifu_in_lpmd (cp0_ifu_in_lpmd ), .cp0_ifu_lpmd_req (cp0_ifu_lpmd_req ), .cp0_sysio_ipend_b (cp0_sysio_ipend_b ), .cp0_sysio_lpmd_b (cp0_sysio_lpmd_b ), .cp0_yy_clk_en (cp0_yy_clk_en ), .cpurst_b (cpurst_b ), .forever_cpuclk (forever_cpuclk ), .had_yy_xx_dbg (had_yy_xx_dbg ), .ifu_cp0_lpmd_ack (ifu_cp0_lpmd_ack ), .inst_lpmd (inst_lpmd ), .iu_cp0_ex_sel (iu_cp0_ex_sel ), .iu_cp0_lp_wk_int (iu_cp0_lp_wk_int ), .iu_yy_xx_dbgon (iu_yy_xx_dbgon ), .iu_yy_xx_flush (iu_yy_xx_flush ), .iui_lpmd_inst_lpmd_for_data (iui_lpmd_inst_lpmd_for_data), .lpmd_iui_stall (lpmd_iui_stall ), .lpmd_sm_clk (lpmd_sm_clk ), .lpmd_sm_clk_en (lpmd_sm_clk_en ), .pad_yy_gate_clk_en_b (pad_yy_gate_clk_en_b ), .pad_yy_test_mode (pad_yy_test_mode ), .sysio_cp0_sys_view_lpmd_b (sysio_cp0_sys_view_lpmd_b ) ); cr_cp0_randclk x_cr_cp0_randclk ( .randclk_psr_mod_en_w13 (randclk_psr_mod_en_w13) ); endmodule module E902_20191018( biu_pad_haddr, biu_pad_hburst, biu_pad_hprot, biu_pad_hsize, biu_pad_htrans, biu_pad_hwdata, biu_pad_hwrite, biu_pad_vec_redrct, clk_en, cp0_pad_mintstatus, cp0_pad_mstatus, cp0_pad_psr, cpu_pad_dfs_ack, ctim_pad_int_vld, had_pad_jdb_ack_b, had_pad_jdb_pm, had_pad_jtg_tap_on, had_pad_jtg_tms_o, had_pad_jtg_tms_oe, had_pad_wakeup_req_b, iahbl_pad_haddr, iahbl_pad_hburst, iahbl_pad_hprot, iahbl_pad_hsize, iahbl_pad_htrans, iahbl_pad_hwdata, iahbl_pad_hwrite, iahbl_pad_vec_redrct, iu_pad_gpr_data, iu_pad_gpr_index, iu_pad_gpr_we, iu_pad_inst_retire, iu_pad_inst_split, iu_pad_retire_pc, pad_biu_hrdata, pad_biu_hready, pad_biu_hresp, pad_bmu_iahbl_base, pad_bmu_iahbl_mask, pad_clic_int_cfg, pad_clic_int_vld, pad_cpu_dfs_req, pad_cpu_ext_int_b, pad_cpu_rst_b, pad_ctim_calib, pad_ctim_refclk, pad_had_jdb_req_b, pad_had_jtg_tap_en, pad_had_jtg_tclk, pad_had_jtg_tms_i, pad_had_jtg_trst_b, pad_had_rst_b, pad_iahbl_hrdata, pad_iahbl_hready, pad_iahbl_hresp, pad_sysio_bigend_b, pad_sysio_clkratio, pad_sysio_endian_v2, pad_yy_gate_clk_en_b, pad_yy_test_mode, pll_core_cpuclk, sysio_pad_dbg_b, sysio_pad_ipend_b, sysio_pad_lpmd_b, sysio_pad_srst, sysio_pad_wakeup_b ); input clk_en; input [31:0] pad_biu_hrdata; input pad_biu_hready; input pad_biu_hresp; input [11:0] pad_bmu_iahbl_base; input [11:0] pad_bmu_iahbl_mask; input [63:0] pad_clic_int_cfg; input [63:0] pad_clic_int_vld; input pad_cpu_dfs_req; input pad_cpu_ext_int_b; input pad_cpu_rst_b; input [25:0] pad_ctim_calib; input pad_ctim_refclk; input pad_had_jdb_req_b; input pad_had_jtg_tap_en; input pad_had_jtg_tclk; input pad_had_jtg_tms_i; input pad_had_jtg_trst_b; input pad_had_rst_b; input [31:0] pad_iahbl_hrdata; input pad_iahbl_hready; input pad_iahbl_hresp; input pad_sysio_bigend_b; input [2 :0] pad_sysio_clkratio; input pad_sysio_endian_v2; input pad_yy_gate_clk_en_b; input pad_yy_test_mode; input pll_core_cpuclk; output [31:0] biu_pad_haddr; output [2 :0] biu_pad_hburst; output [3 :0] biu_pad_hprot; output [2 :0] biu_pad_hsize; output [1 :0] biu_pad_htrans; output [31:0] biu_pad_hwdata; output biu_pad_hwrite; output biu_pad_vec_redrct; output [31:0] cp0_pad_mintstatus; output [31:0] cp0_pad_mstatus; output [31:0] cp0_pad_psr; output cpu_pad_dfs_ack; output ctim_pad_int_vld; output had_pad_jdb_ack_b; output [1 :0] had_pad_jdb_pm; output had_pad_jtg_tap_on; output had_pad_jtg_tms_o; output had_pad_jtg_tms_oe; output had_pad_wakeup_req_b; output [31:0] iahbl_pad_haddr; output [2 :0] iahbl_pad_hburst; output [3 :0] iahbl_pad_hprot; output [2 :0] iahbl_pad_hsize; output [1 :0] iahbl_pad_htrans; output [31:0] iahbl_pad_hwdata; output iahbl_pad_hwrite; output iahbl_pad_vec_redrct; output [31:0] iu_pad_gpr_data; output [4 :0] iu_pad_gpr_index; output iu_pad_gpr_we; output iu_pad_inst_retire; output iu_pad_inst_split; output [31:0] iu_pad_retire_pc; output sysio_pad_dbg_b; output sysio_pad_ipend_b; output [1 :0] sysio_pad_lpmd_b; output sysio_pad_srst; output sysio_pad_wakeup_b; wire [31:0] biu_pad_haddr; wire [2 :0] biu_pad_hburst; wire [3 :0] biu_pad_hprot; wire [2 :0] biu_pad_hsize; wire [1 :0] biu_pad_htrans; wire [31:0] biu_pad_hwdata; wire biu_pad_hwrite; wire biu_pad_vec_redrct; wire bmu_tcipif_dbus_acc_deny; wire [31:0] bmu_tcipif_dbus_addr; wire bmu_tcipif_dbus_chk_fail; wire bmu_tcipif_dbus_req; wire [1 :0] bmu_tcipif_dbus_size; wire bmu_tcipif_dbus_supv_mode; wire [31:0] bmu_tcipif_dbus_wdata; wire bmu_tcipif_dbus_write; wire bmu_tcipif_ibus_acc_deny; wire [31:0] bmu_tcipif_ibus_addr; wire bmu_tcipif_ibus_req; wire bmu_tcipif_ibus_write; wire clic_cpu_int_hv; wire [9 :0] clic_cpu_int_id; wire [7 :0] clic_cpu_int_il; wire [1 :0] clic_cpu_int_priv; wire clk_en; wire [31:0] cp0_had_cpuid_idx0; wire cp0_had_int_exit; wire [1 :0] cp0_had_lpmd_b; wire [31:0] cp0_had_mcause_data; wire [31:0] cp0_pad_mintstatus; wire [31:0] cp0_pad_mstatus; wire [31:0] cp0_pad_psr; wire cp0_yy_be_v2; wire [9 :0] cpu_clic_curid; wire cpu_clic_int_exit; wire cpu_pad_dfs_ack; wire cpurst_b; wire ctim_pad_int_vld; wire forever_cpuclk; wire forever_cpuclk_nogated; wire forever_jtgclk; wire had_core_dbg_mode_req; wire had_core_exit_dbg; wire [31:0] had_idu_wbbr_data; wire had_idu_wbbr_vld; wire had_ifu_inst_bkpt_dbq_req; wire had_ifu_inst_bkpt_dbqexp_req; wire [31:0] had_ifu_ir; wire had_ifu_ir_vld; wire had_iu_bkpt_trace_en; wire had_iu_dr_set_req; wire had_iu_force_dbg_en; wire had_iu_int_vld; wire had_iu_mbkpt_fsm_index_mbee; wire had_iu_mem_bkpt_exp_req; wire had_iu_mem_bkpt_mask; wire had_iu_mem_bkpt_req; wire [30:0] had_iu_pc; wire had_iu_rte_pc_sel; wire had_iu_trace_req; wire had_iu_trace_req_for_dbg_disable; wire had_iu_xx_fdb; wire had_iu_xx_jdbreq; wire had_pad_jdb_ack_b; wire [1 :0] had_pad_jdb_pm; wire had_pad_jtg_tap_on; wire had_pad_jtg_tms_o; wire had_pad_jtg_tms_oe; wire had_pad_wakeup_req_b; wire had_tcipif_cmplt; wire [31:0] had_tcipif_rdata; wire had_yy_xx_dbg; wire had_yy_xx_dp_index_mbee; wire hadrst_b; wire [31:0] iahbl_pad_haddr; wire [2 :0] iahbl_pad_hburst; wire [3 :0] iahbl_pad_hprot; wire [2 :0] iahbl_pad_hsize; wire [1 :0] iahbl_pad_htrans; wire [31:0] iahbl_pad_hwdata; wire iahbl_pad_hwrite; wire iahbl_pad_vec_redrct; wire ifu_had_chg_flw_inst; wire ifu_had_fetch_expt_vld; wire ifu_had_inst_dbg_disable; wire [31:0] ifu_had_match_pc; wire ifu_had_split_first; wire iu_had_adr_dbg_ack; wire [31:0] iu_had_chgflw_dst_pc; wire iu_had_chgflw_vld; wire iu_had_data_bkpt_occur_vld; wire iu_had_dbg_disable_for_tee; wire iu_had_dr_dbg_ack; wire iu_had_expt_vld; wire iu_had_fast_retire_acc_err_pc_update; wire [30:0] iu_had_fast_retire_acc_err_pc_val; wire iu_had_flush; wire iu_had_inst_bkpt_occur_vld; wire iu_had_int_ack; wire iu_had_retire_with_had_int; wire iu_had_trace_occur_vld; wire iu_had_xx_bkpt_inst; wire [31:0] iu_had_xx_data; wire iu_had_xx_data_vld; wire iu_had_xx_dbg_ack; wire iu_had_xx_mldst; wire iu_had_xx_retire; wire iu_had_xx_retire_normal; wire [31:0] iu_had_xx_retire_pc; wire [31:0] iu_pad_gpr_data; wire [4 :0] iu_pad_gpr_index; wire iu_pad_gpr_we; wire iu_pad_inst_retire; wire iu_pad_inst_split; wire [31:0] iu_pad_retire_pc; wire iu_yy_xx_dbgon; wire [31:0] lsu_had_addr; wire lsu_had_addr_vld; wire lsu_had_ex_cmplt; wire lsu_had_st; wire [31:0] pad_biu_hrdata; wire pad_biu_hready; wire pad_biu_hresp; wire [11:0] pad_bmu_iahbl_base; wire [11:0] pad_bmu_iahbl_mask; wire [63:0] pad_clic_int_cfg; wire [63:0] pad_clic_int_vld; wire pad_cpu_dfs_req; wire pad_cpu_ext_int_b; wire pad_cpu_rst_b; wire [25:0] pad_ctim_calib; wire pad_ctim_refclk; wire pad_had_jdb_req_b; wire pad_had_jtg_tap_en; wire pad_had_jtg_tclk; wire pad_had_jtg_tms_i; wire pad_had_jtg_trst_b; wire pad_had_rst_b; wire [31:0] pad_iahbl_hrdata; wire pad_iahbl_hready; wire pad_iahbl_hresp; wire pad_sysio_bigend_b; wire [2 :0] pad_sysio_clkratio; wire pad_sysio_endian_v2; wire pad_yy_gate_clk_en_b; wire pad_yy_test_mode; wire pll_core_cpuclk; wire pwrm_cpu_bus_peak_power_limit_en; wire sysio_pad_dbg_b; wire sysio_pad_ipend_b; wire [1 :0] sysio_pad_lpmd_b; wire sysio_pad_srst; wire sysio_pad_wakeup_b; wire tcipif_bmu_dbus_acc_err; wire [31:0] tcipif_bmu_dbus_data; wire tcipif_bmu_dbus_data_vld; wire tcipif_bmu_dbus_grnt; wire tcipif_bmu_dbus_trans_cmplt; wire tcipif_bmu_ibus_acc_err; wire [31:0] tcipif_bmu_ibus_data; wire tcipif_bmu_ibus_data_vld; wire tcipif_bmu_ibus_grnt; wire tcipif_bmu_ibus_trans_cmplt; wire [15:0] tcipif_had_addr; wire tcipif_had_sel; wire [31:0] tcipif_had_wdata; wire tcipif_had_write; wire trst_b; cr_core_top x_cr_core_top ( .biu_pad_haddr (biu_pad_haddr ), .biu_pad_hburst (biu_pad_hburst ), .biu_pad_hprot (biu_pad_hprot ), .biu_pad_hsize (biu_pad_hsize ), .biu_pad_htrans (biu_pad_htrans ), .biu_pad_hwdata (biu_pad_hwdata ), .biu_pad_hwrite (biu_pad_hwrite ), .biu_pad_vec_redrct (biu_pad_vec_redrct ), .bmu_tcipif_dbus_acc_deny (bmu_tcipif_dbus_acc_deny ), .bmu_tcipif_dbus_addr (bmu_tcipif_dbus_addr ), .bmu_tcipif_dbus_chk_fail (bmu_tcipif_dbus_chk_fail ), .bmu_tcipif_dbus_req (bmu_tcipif_dbus_req ), .bmu_tcipif_dbus_size (bmu_tcipif_dbus_size ), .bmu_tcipif_dbus_supv_mode (bmu_tcipif_dbus_supv_mode ), .bmu_tcipif_dbus_wdata (bmu_tcipif_dbus_wdata ), .bmu_tcipif_dbus_write (bmu_tcipif_dbus_write ), .bmu_tcipif_ibus_acc_deny (bmu_tcipif_ibus_acc_deny ), .bmu_tcipif_ibus_addr (bmu_tcipif_ibus_addr ), .bmu_tcipif_ibus_req (bmu_tcipif_ibus_req ), .bmu_tcipif_ibus_write (bmu_tcipif_ibus_write ), .clic_cpu_int_hv (clic_cpu_int_hv ), .clic_cpu_int_id (clic_cpu_int_id ), .clic_cpu_int_il (clic_cpu_int_il ), .clic_cpu_int_priv (clic_cpu_int_priv ), .clk_en (clk_en ), .cp0_had_cpuid_idx0 (cp0_had_cpuid_idx0 ), .cp0_had_int_exit (cp0_had_int_exit ), .cp0_had_lpmd_b (cp0_had_lpmd_b ), .cp0_had_mcause_data (cp0_had_mcause_data ), .cp0_pad_mintstatus (cp0_pad_mintstatus ), .cp0_pad_mstatus (cp0_pad_mstatus ), .cp0_pad_psr (cp0_pad_psr ), .cp0_yy_be_v2 (cp0_yy_be_v2 ), .cpu_clic_curid (cpu_clic_curid ), .cpu_clic_int_exit (cpu_clic_int_exit ), .cpu_pad_dfs_ack (cpu_pad_dfs_ack ), .cpurst_b (cpurst_b ), .forever_cpuclk (forever_cpuclk ), .had_core_dbg_mode_req (had_core_dbg_mode_req ), .had_core_exit_dbg (had_core_exit_dbg ), .had_idu_wbbr_data (had_idu_wbbr_data ), .had_idu_wbbr_vld (had_idu_wbbr_vld ), .had_ifu_inst_bkpt_dbq_req (had_ifu_inst_bkpt_dbq_req ), .had_ifu_inst_bkpt_dbqexp_req (had_ifu_inst_bkpt_dbqexp_req ), .had_ifu_ir (had_ifu_ir ), .had_ifu_ir_vld (had_ifu_ir_vld ), .had_iu_bkpt_trace_en (had_iu_bkpt_trace_en ), .had_iu_dr_set_req (had_iu_dr_set_req ), .had_iu_force_dbg_en (had_iu_force_dbg_en ), .had_iu_int_vld (had_iu_int_vld ), .had_iu_mbkpt_fsm_index_mbee (had_iu_mbkpt_fsm_index_mbee ), .had_iu_mem_bkpt_exp_req (had_iu_mem_bkpt_exp_req ), .had_iu_mem_bkpt_mask (had_iu_mem_bkpt_mask ), .had_iu_mem_bkpt_req (had_iu_mem_bkpt_req ), .had_iu_pc (had_iu_pc ), .had_iu_rte_pc_sel (had_iu_rte_pc_sel ), .had_iu_trace_req (had_iu_trace_req ), .had_iu_trace_req_for_dbg_disable (had_iu_trace_req_for_dbg_disable ), .had_iu_xx_fdb (had_iu_xx_fdb ), .had_iu_xx_jdbreq (had_iu_xx_jdbreq ), .had_yy_xx_dbg (had_yy_xx_dbg ), .had_yy_xx_dp_index_mbee (had_yy_xx_dp_index_mbee ), .iahbl_pad_haddr (iahbl_pad_haddr ), .iahbl_pad_hburst (iahbl_pad_hburst ), .iahbl_pad_hprot (iahbl_pad_hprot ), .iahbl_pad_hsize (iahbl_pad_hsize ), .iahbl_pad_htrans (iahbl_pad_htrans ), .iahbl_pad_hwdata (iahbl_pad_hwdata ), .iahbl_pad_hwrite (iahbl_pad_hwrite ), .iahbl_pad_vec_redrct (iahbl_pad_vec_redrct ), .ifu_had_chg_flw_inst (ifu_had_chg_flw_inst ), .ifu_had_fetch_expt_vld (ifu_had_fetch_expt_vld ), .ifu_had_inst_dbg_disable (ifu_had_inst_dbg_disable ), .ifu_had_match_pc (ifu_had_match_pc ), .ifu_had_split_first (ifu_had_split_first ), .iu_had_adr_dbg_ack (iu_had_adr_dbg_ack ), .iu_had_chgflw_dst_pc (iu_had_chgflw_dst_pc ), .iu_had_chgflw_vld (iu_had_chgflw_vld ), .iu_had_data_bkpt_occur_vld (iu_had_data_bkpt_occur_vld ), .iu_had_dbg_disable_for_tee (iu_had_dbg_disable_for_tee ), .iu_had_dr_dbg_ack (iu_had_dr_dbg_ack ), .iu_had_expt_vld (iu_had_expt_vld ), .iu_had_fast_retire_acc_err_pc_update (iu_had_fast_retire_acc_err_pc_update), .iu_had_fast_retire_acc_err_pc_val (iu_had_fast_retire_acc_err_pc_val ), .iu_had_flush (iu_had_flush ), .iu_had_inst_bkpt_occur_vld (iu_had_inst_bkpt_occur_vld ), .iu_had_int_ack (iu_had_int_ack ), .iu_had_retire_with_had_int (iu_had_retire_with_had_int ), .iu_had_trace_occur_vld (iu_had_trace_occur_vld ), .iu_had_xx_bkpt_inst (iu_had_xx_bkpt_inst ), .iu_had_xx_data (iu_had_xx_data ), .iu_had_xx_data_vld (iu_had_xx_data_vld ), .iu_had_xx_dbg_ack (iu_had_xx_dbg_ack ), .iu_had_xx_mldst (iu_had_xx_mldst ), .iu_had_xx_retire (iu_had_xx_retire ), .iu_had_xx_retire_normal (iu_had_xx_retire_normal ), .iu_had_xx_retire_pc (iu_had_xx_retire_pc ), .iu_pad_gpr_data (iu_pad_gpr_data ), .iu_pad_gpr_index (iu_pad_gpr_index ), .iu_pad_gpr_we (iu_pad_gpr_we ), .iu_pad_inst_retire (iu_pad_inst_retire ), .iu_pad_inst_split (iu_pad_inst_split ), .iu_pad_retire_pc (iu_pad_retire_pc ), .iu_yy_xx_dbgon (iu_yy_xx_dbgon ), .lsu_had_addr (lsu_had_addr ), .lsu_had_addr_vld (lsu_had_addr_vld ), .lsu_had_ex_cmplt (lsu_had_ex_cmplt ), .lsu_had_st (lsu_had_st ), .pad_biu_hrdata (pad_biu_hrdata ), .pad_biu_hready (pad_biu_hready ), .pad_biu_hresp (pad_biu_hresp ), .pad_bmu_iahbl_base (pad_bmu_iahbl_base ), .pad_bmu_iahbl_mask (pad_bmu_iahbl_mask ), .pad_cpu_dfs_req (pad_cpu_dfs_req ), .pad_cpu_ext_int_b (pad_cpu_ext_int_b ), .pad_iahbl_hrdata (pad_iahbl_hrdata ), .pad_iahbl_hready (pad_iahbl_hready ), .pad_iahbl_hresp (pad_iahbl_hresp ), .pad_sysio_bigend_b (pad_sysio_bigend_b ), .pad_sysio_clkratio (pad_sysio_clkratio ), .pad_sysio_endian_v2 (pad_sysio_endian_v2 ), .pad_yy_gate_clk_en_b (pad_yy_gate_clk_en_b ), .pad_yy_test_mode (pad_yy_test_mode ), .pwrm_cpu_bus_peak_power_limit_en (pwrm_cpu_bus_peak_power_limit_en ), .sysio_pad_dbg_b (sysio_pad_dbg_b ), .sysio_pad_ipend_b (sysio_pad_ipend_b ), .sysio_pad_lpmd_b (sysio_pad_lpmd_b ), .sysio_pad_srst (sysio_pad_srst ), .sysio_pad_wakeup_b (sysio_pad_wakeup_b ), .tcipif_bmu_dbus_acc_err (tcipif_bmu_dbus_acc_err ), .tcipif_bmu_dbus_data (tcipif_bmu_dbus_data ), .tcipif_bmu_dbus_data_vld (tcipif_bmu_dbus_data_vld ), .tcipif_bmu_dbus_grnt (tcipif_bmu_dbus_grnt ), .tcipif_bmu_dbus_trans_cmplt (tcipif_bmu_dbus_trans_cmplt ), .tcipif_bmu_ibus_acc_err (tcipif_bmu_ibus_acc_err ), .tcipif_bmu_ibus_data (tcipif_bmu_ibus_data ), .tcipif_bmu_ibus_data_vld (tcipif_bmu_ibus_data_vld ), .tcipif_bmu_ibus_grnt (tcipif_bmu_ibus_grnt ), .tcipif_bmu_ibus_trans_cmplt (tcipif_bmu_ibus_trans_cmplt ) ); cr_had_top x_cr_had_top ( .cp0_had_cpuid_idx0 (cp0_had_cpuid_idx0 ), .cp0_had_int_exit (cp0_had_int_exit ), .cp0_had_lpmd_b (cp0_had_lpmd_b ), .cp0_had_mcause_data (cp0_had_mcause_data ), .forever_cpuclk_nogated (forever_cpuclk_nogated ), .had_core_dbg_mode_req (had_core_dbg_mode_req ), .had_idu_wbbr_data (had_idu_wbbr_data ), .had_idu_wbbr_vld (had_idu_wbbr_vld ), .had_ifu_inst_bkpt_dbq_req (had_ifu_inst_bkpt_dbq_req ), .had_ifu_inst_bkpt_dbqexp_req (had_ifu_inst_bkpt_dbqexp_req ), .had_ifu_ir (had_ifu_ir ), .had_ifu_ir_vld (had_ifu_ir_vld ), .had_iu_bkpt_trace_en (had_iu_bkpt_trace_en ), .had_iu_dr_set_req (had_iu_dr_set_req ), .had_iu_force_dbg_en (had_iu_force_dbg_en ), .had_iu_int_vld (had_iu_int_vld ), .had_iu_mbkpt_fsm_index_mbee (had_iu_mbkpt_fsm_index_mbee ), .had_iu_mem_bkpt_exp_req (had_iu_mem_bkpt_exp_req ), .had_iu_mem_bkpt_mask (had_iu_mem_bkpt_mask ), .had_iu_mem_bkpt_req (had_iu_mem_bkpt_req ), .had_iu_pc (had_iu_pc ), .had_iu_rte_pc_sel (had_iu_rte_pc_sel ), .had_iu_trace_req (had_iu_trace_req ), .had_iu_trace_req_for_dbg_disable (had_iu_trace_req_for_dbg_disable ), .had_iu_xx_fdb (had_iu_xx_fdb ), .had_iu_xx_jdbreq (had_iu_xx_jdbreq ), .had_pad_jdb_ack_b (had_pad_jdb_ack_b ), .had_pad_jdb_pm (had_pad_jdb_pm ), .had_pad_jtg_tap_on (had_pad_jtg_tap_on ), .had_pad_jtg_tms_o (had_pad_jtg_tms_o ), .had_pad_jtg_tms_oe (had_pad_jtg_tms_oe ), .had_pad_wakeup_req_b (had_pad_wakeup_req_b ), .had_tcipif_cmplt (had_tcipif_cmplt ), .had_tcipif_rdata (had_tcipif_rdata ), .had_yy_xx_dbg (had_yy_xx_dbg ), .had_yy_xx_dp_index_mbee (had_yy_xx_dp_index_mbee ), .had_yy_xx_exit_dbg (had_core_exit_dbg ), .hadrst_b (hadrst_b ), .ifu_had_chg_flw_inst (ifu_had_chg_flw_inst ), .ifu_had_fetch_expt_vld (ifu_had_fetch_expt_vld ), .ifu_had_inst_dbg_disable (ifu_had_inst_dbg_disable ), .ifu_had_match_pc (ifu_had_match_pc ), .ifu_had_split_first (ifu_had_split_first ), .iu_had_adr_dbg_ack (iu_had_adr_dbg_ack ), .iu_had_chgflw_dst_pc (iu_had_chgflw_dst_pc ), .iu_had_chgflw_vld (iu_had_chgflw_vld ), .iu_had_data_bkpt_occur_vld (iu_had_data_bkpt_occur_vld ), .iu_had_dbg_disable_for_tee (iu_had_dbg_disable_for_tee ), .iu_had_dr_dbg_ack (iu_had_dr_dbg_ack ), .iu_had_expt_vld (iu_had_expt_vld ), .iu_had_fast_retire_acc_err_pc_update (iu_had_fast_retire_acc_err_pc_update), .iu_had_fast_retire_acc_err_pc_val (iu_had_fast_retire_acc_err_pc_val ), .iu_had_flush (iu_had_flush ), .iu_had_inst_bkpt_occur_vld (iu_had_inst_bkpt_occur_vld ), .iu_had_int_ack (iu_had_int_ack ), .iu_had_retire_with_had_int (iu_had_retire_with_had_int ), .iu_had_trace_occur_vld (iu_had_trace_occur_vld ), .iu_had_xx_bkpt_inst (iu_had_xx_bkpt_inst ), .iu_had_xx_data (iu_had_xx_data ), .iu_had_xx_data_vld (iu_had_xx_data_vld ), .iu_had_xx_dbg_ack (iu_had_xx_dbg_ack ), .iu_had_xx_mldst (iu_had_xx_mldst ), .iu_had_xx_retire (iu_had_xx_retire ), .iu_had_xx_retire_normal (iu_had_xx_retire_normal ), .iu_had_xx_retire_pc (iu_had_xx_retire_pc ), .iu_yy_xx_dbgon (iu_yy_xx_dbgon ), .lsu_had_addr (lsu_had_addr ), .lsu_had_addr_vld (lsu_had_addr_vld ), .lsu_had_ex_cmplt (lsu_had_ex_cmplt ), .lsu_had_st (lsu_had_st ), .pad_had_jdb_req_b (pad_had_jdb_req_b ), .pad_had_jtg_tap_en (pad_had_jtg_tap_en ), .pad_had_jtg_tms_i (pad_had_jtg_tms_i ), .pad_yy_gate_clk_en_b (pad_yy_gate_clk_en_b ), .pad_yy_test_mode (pad_yy_test_mode ), .tcipif_had_addr (tcipif_had_addr ), .tcipif_had_sel (tcipif_had_sel ), .tcipif_had_wdata (tcipif_had_wdata ), .tcipif_had_write (tcipif_had_write ), .tclk (forever_jtgclk ), .trst_b (trst_b ) ); cr_clkrst_top x_cr_clkrst_top ( .cpurst_b (cpurst_b ), .forever_cpuclk (forever_cpuclk ), .forever_cpuclk_nogated (forever_cpuclk_nogated), .forever_jtgclk (forever_jtgclk ), .hadrst_b (hadrst_b ), .pad_cpu_rst_b (pad_cpu_rst_b ), .pad_had_jtg_tclk (pad_had_jtg_tclk ), .pad_had_jtg_trst_b (pad_had_jtg_trst_b ), .pad_had_rst_b (pad_had_rst_b ), .pad_yy_test_mode (pad_yy_test_mode ), .pll_core_cpuclk (pll_core_cpuclk ), .trst_b (trst_b ) ); cr_tcipif_top x_cr_tcipif_top ( .bmu_tcipif_dbus_acc_deny (bmu_tcipif_dbus_acc_deny ), .bmu_tcipif_dbus_addr (bmu_tcipif_dbus_addr ), .bmu_tcipif_dbus_chk_fail (bmu_tcipif_dbus_chk_fail ), .bmu_tcipif_dbus_req (bmu_tcipif_dbus_req ), .bmu_tcipif_dbus_size (bmu_tcipif_dbus_size ), .bmu_tcipif_dbus_supv_mode (bmu_tcipif_dbus_supv_mode ), .bmu_tcipif_dbus_wdata (bmu_tcipif_dbus_wdata ), .bmu_tcipif_dbus_write (bmu_tcipif_dbus_write ), .bmu_tcipif_ibus_acc_deny (bmu_tcipif_ibus_acc_deny ), .bmu_tcipif_ibus_addr (bmu_tcipif_ibus_addr ), .bmu_tcipif_ibus_req (bmu_tcipif_ibus_req ), .bmu_tcipif_ibus_write (bmu_tcipif_ibus_write ), .clic_cpu_int_hv (clic_cpu_int_hv ), .clic_cpu_int_id (clic_cpu_int_id ), .clic_cpu_int_il (clic_cpu_int_il ), .clic_cpu_int_priv (clic_cpu_int_priv ), .cp0_yy_be_v2 (cp0_yy_be_v2 ), .cpu_clic_curid (cpu_clic_curid ), .cpu_clic_int_exit (cpu_clic_int_exit ), .cpurst_b (cpurst_b ), .ctim_pad_int_vld (ctim_pad_int_vld ), .forever_cpuclk (forever_cpuclk ), .forever_cpuclk_nogated (forever_cpuclk_nogated ), .had_tcipif_cmplt (had_tcipif_cmplt ), .had_tcipif_rdata (had_tcipif_rdata ), .iu_yy_xx_dbgon (iu_yy_xx_dbgon ), .pad_clic_int_cfg (pad_clic_int_cfg ), .pad_clic_int_vld (pad_clic_int_vld ), .pad_ctim_calib (pad_ctim_calib ), .pad_ctim_refclk (pad_ctim_refclk ), .pad_yy_gate_clk_en_b (pad_yy_gate_clk_en_b ), .pad_yy_test_mode (pad_yy_test_mode ), .pwrm_cpu_bus_peak_power_limit_en (pwrm_cpu_bus_peak_power_limit_en), .tcipif_bmu_dbus_acc_err (tcipif_bmu_dbus_acc_err ), .tcipif_bmu_dbus_data (tcipif_bmu_dbus_data ), .tcipif_bmu_dbus_data_vld (tcipif_bmu_dbus_data_vld ), .tcipif_bmu_dbus_grnt (tcipif_bmu_dbus_grnt ), .tcipif_bmu_dbus_trans_cmplt (tcipif_bmu_dbus_trans_cmplt ), .tcipif_bmu_ibus_acc_err (tcipif_bmu_ibus_acc_err ), .tcipif_bmu_ibus_data (tcipif_bmu_ibus_data ), .tcipif_bmu_ibus_data_vld (tcipif_bmu_ibus_data_vld ), .tcipif_bmu_ibus_grnt (tcipif_bmu_ibus_grnt ), .tcipif_bmu_ibus_trans_cmplt (tcipif_bmu_ibus_trans_cmplt ), .tcipif_had_addr (tcipif_had_addr ), .tcipif_had_sel (tcipif_had_sel ), .tcipif_had_wdata (tcipif_had_wdata ), .tcipif_had_write (tcipif_had_write ) ); endmodule module cr_iahbl_top( ahblif_idle, bmu_iahbl_dbus_acc_deny, bmu_iahbl_dbus_addr, bmu_iahbl_dbus_chk_fail, bmu_iahbl_dbus_prot, bmu_iahbl_dbus_req, bmu_iahbl_dbus_req_without_cmplt, bmu_iahbl_dbus_size, bmu_iahbl_dbus_wdata, bmu_iahbl_dbus_write, bmu_iahbl_ibus_acc_deny, bmu_iahbl_ibus_addr, bmu_iahbl_ibus_hit, bmu_iahbl_ibus_prot, bmu_iahbl_ibus_req, bmu_iahbl_ibus_req_no_hit, bmu_iahbl_ibus_size, bmu_iahbl_ibus_vec_redirect, cpurst_b, dahblif_other_mask, forever_cpuclk, iahbl_bmu_dbus_acc_err, iahbl_bmu_dbus_data, iahbl_bmu_dbus_data_vld, iahbl_bmu_dbus_grnt, iahbl_bmu_dbus_trans_cmplt, iahbl_bmu_ibus_acc_err, iahbl_bmu_ibus_data, iahbl_bmu_ibus_data_vld, iahbl_bmu_ibus_grnt, iahbl_bmu_ibus_trans_cmplt, iahbl_pad_haddr, iahbl_pad_hburst, iahbl_pad_hprot, iahbl_pad_hsize, iahbl_pad_htrans, iahbl_pad_hwdata, iahbl_pad_hwrite, iahbl_pad_vec_redrct, iahblif_other_mask, pad_cpu_halt_ff2, pad_iahbl_hrdata, pad_iahbl_hready, pad_iahbl_hresp, pad_yy_gate_clk_en_b, pad_yy_test_mode, pwrm_cpu_bus_peak_power_limit_en, sahblif_iahblif_mask ); input bmu_iahbl_dbus_acc_deny; input [31:0] bmu_iahbl_dbus_addr; input bmu_iahbl_dbus_chk_fail; input [3 :0] bmu_iahbl_dbus_prot; input bmu_iahbl_dbus_req; input bmu_iahbl_dbus_req_without_cmplt; input [1 :0] bmu_iahbl_dbus_size; input [31:0] bmu_iahbl_dbus_wdata; input bmu_iahbl_dbus_write; input bmu_iahbl_ibus_acc_deny; input [31:0] bmu_iahbl_ibus_addr; input bmu_iahbl_ibus_hit; input [3 :0] bmu_iahbl_ibus_prot; input bmu_iahbl_ibus_req; input bmu_iahbl_ibus_req_no_hit; input [1 :0] bmu_iahbl_ibus_size; input bmu_iahbl_ibus_vec_redirect; input cpurst_b; input dahblif_other_mask; input forever_cpuclk; input pad_cpu_halt_ff2; input [31:0] pad_iahbl_hrdata; input pad_iahbl_hready; input pad_iahbl_hresp; input pad_yy_gate_clk_en_b; input pad_yy_test_mode; input pwrm_cpu_bus_peak_power_limit_en; input sahblif_iahblif_mask; output ahblif_idle; output iahbl_bmu_dbus_acc_err; output [31:0] iahbl_bmu_dbus_data; output iahbl_bmu_dbus_data_vld; output iahbl_bmu_dbus_grnt; output iahbl_bmu_dbus_trans_cmplt; output iahbl_bmu_ibus_acc_err; output [31:0] iahbl_bmu_ibus_data; output iahbl_bmu_ibus_data_vld; output iahbl_bmu_ibus_grnt; output iahbl_bmu_ibus_trans_cmplt; output [31:0] iahbl_pad_haddr; output [2 :0] iahbl_pad_hburst; output [3 :0] iahbl_pad_hprot; output [2 :0] iahbl_pad_hsize; output [1 :0] iahbl_pad_htrans; output [31:0] iahbl_pad_hwdata; output iahbl_pad_hwrite; output iahbl_pad_vec_redrct; output iahblif_other_mask; wire ahbl_clk_en; wire ahbl_gated_clk; wire ahblif_busy; wire ahblif_idle; wire ahblif_power_mask; wire bmu_iahbl_dbus_acc_deny; wire [31:0] bmu_iahbl_dbus_addr; wire bmu_iahbl_dbus_chk_fail; wire [3 :0] bmu_iahbl_dbus_prot; wire bmu_iahbl_dbus_req; wire bmu_iahbl_dbus_req_without_cmplt; wire [1 :0] bmu_iahbl_dbus_size; wire [31:0] bmu_iahbl_dbus_wdata; wire bmu_iahbl_dbus_write; wire bmu_iahbl_ibus_acc_deny; wire [31:0] bmu_iahbl_ibus_addr; wire bmu_iahbl_ibus_hit; wire [3 :0] bmu_iahbl_ibus_prot; wire bmu_iahbl_ibus_req; wire bmu_iahbl_ibus_req_no_hit; wire [1 :0] bmu_iahbl_ibus_size; wire bmu_iahbl_ibus_vec_redirect; wire cpu_acc_err; wire [31:0] cpu_addr; wire cpu_data_vld; wire [3 :0] cpu_prot; wire [31:0] cpu_rdata; wire cpu_req; wire cpu_req_for_grnt; wire cpu_req_for_peak_power; wire cpu_req_grnt; wire cpu_req_power_masked; wire cpu_sec; wire [1 :0] cpu_size; wire cpu_trans_cmplt; wire cpu_vec_redirect; wire [31:0] cpu_wdata; wire cpu_wdata_sel; wire [31:0] cpu_wr_data; wire cpu_write; wire cpurst_b; wire dahblif_other_mask; wire dbus_mask; wire forever_cpuclk; wire iahbl_bmu_dbus_acc_err; wire [31:0] iahbl_bmu_dbus_data; wire iahbl_bmu_dbus_data_vld; wire iahbl_bmu_dbus_grnt; wire iahbl_bmu_dbus_trans_cmplt; wire iahbl_bmu_ibus_acc_err; wire [31:0] iahbl_bmu_ibus_data; wire iahbl_bmu_ibus_data_vld; wire iahbl_bmu_ibus_grnt; wire iahbl_bmu_ibus_trans_cmplt; wire [31:0] iahbl_pad_haddr; wire [2 :0] iahbl_pad_hburst; wire [3 :0] iahbl_pad_hprot; wire [2 :0] iahbl_pad_hsize; wire [1 :0] iahbl_pad_htrans; wire [31:0] iahbl_pad_hwdata; wire iahbl_pad_hwrite; wire iahbl_pad_vec_redrct; wire iahblif_other_mask; wire ibus_not_granted; wire pad_cpu_halt_ff2; wire [31:0] pad_iahbl_hrdata; wire pad_iahbl_hready; wire pad_iahbl_hresp; wire pad_yy_gate_clk_en_b; wire pad_yy_test_mode; wire pwrm_cpu_bus_peak_power_limit_en; wire sahblif_iahblif_mask; gated_clk_cell x_gated_ahbl_cpuclk_cell ( .clk_in (forever_cpuclk ), .clk_out (ahbl_gated_clk ), .external_en (1'b0 ), .global_en (1'b1 ), .local_en (dbus_mask ), .module_en (ahbl_clk_en ), .pad_yy_gate_clk_en_b (pad_yy_gate_clk_en_b), .pad_yy_test_mode (pad_yy_test_mode ) ); cr_ahbl_req_arb x_cr_ahbl_req_arb ( .ahbl_bmu_dbus_acc_err (iahbl_bmu_dbus_acc_err ), .ahbl_bmu_dbus_data (iahbl_bmu_dbus_data ), .ahbl_bmu_dbus_data_vld (iahbl_bmu_dbus_data_vld ), .ahbl_bmu_dbus_grnt (iahbl_bmu_dbus_grnt ), .ahbl_bmu_dbus_trans_cmplt (iahbl_bmu_dbus_trans_cmplt ), .ahbl_bmu_ibus_acc_err (iahbl_bmu_ibus_acc_err ), .ahbl_bmu_ibus_data (iahbl_bmu_ibus_data ), .ahbl_bmu_ibus_data_vld (iahbl_bmu_ibus_data_vld ), .ahbl_bmu_ibus_grnt (iahbl_bmu_ibus_grnt ), .ahbl_bmu_ibus_trans_cmplt (iahbl_bmu_ibus_trans_cmplt ), .ahbl_gated_clk (ahbl_gated_clk ), .bmu_ahbl_dbus_acc_deny (bmu_iahbl_dbus_acc_deny ), .bmu_ahbl_dbus_addr (bmu_iahbl_dbus_addr ), .bmu_ahbl_dbus_chk_fail (bmu_iahbl_dbus_chk_fail ), .bmu_ahbl_dbus_prot (bmu_iahbl_dbus_prot ), .bmu_ahbl_dbus_req (bmu_iahbl_dbus_req ), .bmu_ahbl_dbus_req_without_cmplt (bmu_iahbl_dbus_req_without_cmplt ), .bmu_ahbl_dbus_req_without_deny_chk_fail (bmu_iahbl_dbus_req ), .bmu_ahbl_dbus_size (bmu_iahbl_dbus_size ), .bmu_ahbl_dbus_write (bmu_iahbl_dbus_write ), .bmu_ahbl_ibus_acc_deny (bmu_iahbl_ibus_acc_deny ), .bmu_ahbl_ibus_addr (bmu_iahbl_ibus_addr ), .bmu_ahbl_ibus_hit (bmu_iahbl_ibus_hit ), .bmu_ahbl_ibus_prot (bmu_iahbl_ibus_prot ), .bmu_ahbl_ibus_req (bmu_iahbl_ibus_req ), .bmu_ahbl_ibus_req_no_hit (bmu_iahbl_ibus_req_no_hit ), .bmu_ahbl_ibus_size (bmu_iahbl_ibus_size ), .bmu_ahbl_ibus_vec_redirect (bmu_iahbl_ibus_vec_redirect ), .bmu_ahbl_ibus_write (1'b0 ), .bmu_ahbl_wdata (bmu_iahbl_dbus_wdata ), .cpu_acc_err (cpu_acc_err ), .cpu_addr (cpu_addr ), .cpu_data_vld (cpu_data_vld ), .cpu_prot (cpu_prot ), .cpu_rdata (cpu_rdata ), .cpu_req (cpu_req ), .cpu_req_for_grnt (cpu_req_for_grnt ), .cpu_req_for_peak_power (cpu_req_for_peak_power ), .cpu_req_grnt (cpu_req_grnt ), .cpu_sec (cpu_sec ), .cpu_size (cpu_size ), .cpu_trans_cmplt (cpu_trans_cmplt ), .cpu_vec_redirect (cpu_vec_redirect ), .cpu_wdata (cpu_wdata ), .cpu_write (cpu_write ), .cpurst_b (cpurst_b ), .ibus_not_granted (ibus_not_granted ) ); assign dbus_mask = ibus_not_granted; cr_ahbl_if x_cr_ahbl_if ( .ahbLif_ahbl_haddr (iahbl_pad_haddr ), .ahbLif_ahbl_hburst (iahbl_pad_hburst ), .ahbLif_ahbl_hprot (iahbl_pad_hprot ), .ahbLif_ahbl_hsize (iahbl_pad_hsize ), .ahbLif_ahbl_htrans (iahbl_pad_htrans ), .ahbLif_ahbl_hwdata (iahbl_pad_hwdata ), .ahbLif_ahbl_hwrite (iahbl_pad_hwrite ), .ahbLif_ahbl_vec_redrct (iahbl_pad_vec_redrct ), .ahbl_ahbLif_hrdata (pad_iahbl_hrdata ), .ahbl_ahbLif_hready (pad_iahbl_hready ), .ahbl_ahbLif_hresp (pad_iahbl_hresp ), .ahbl_clk_en (ahbl_clk_en ), .ahbl_gated_clk (ahbl_gated_clk ), .ahblif_busy (ahblif_busy ), .ahblif_idle (ahblif_idle ), .ahblif_power_mask (ahblif_power_mask ), .cpu_acc_err (cpu_acc_err ), .cpu_addr (cpu_addr ), .cpu_data_vld (cpu_data_vld ), .cpu_prot (cpu_prot ), .cpu_rdata (cpu_rdata ), .cpu_req (cpu_req ), .cpu_req_grnt (cpu_req_grnt ), .cpu_req_power_masked (cpu_req_power_masked ), .cpu_sec (cpu_sec ), .cpu_size (cpu_size ), .cpu_trans_cmplt (cpu_trans_cmplt ), .cpu_vec_redirect (cpu_vec_redirect ), .cpu_wdata_sel (cpu_wdata_sel ), .cpu_wr_data (cpu_wr_data ), .cpu_write (cpu_write ), .cpurst_b (cpurst_b ), .pad_cpu_halt_ff2 (pad_cpu_halt_ff2 ) ); assign cpu_wr_data[31:0] = {32{cpu_wdata_sel}} & cpu_wdata[31:0]; assign iahblif_other_mask = ahblif_busy && pwrm_cpu_bus_peak_power_limit_en; assign ahblif_power_mask = sahblif_iahblif_mask || dahblif_other_mask; assign cpu_req_power_masked = cpu_req && !ahblif_power_mask; endmodule module cr_ifu_ibuf( cp0_yy_clk_en, cpuclk, cpurst_b, forever_cpuclk, had_ifu_ir, had_ifu_ir_vld, ibuf_ibusif_inst_fetch, ibuf_ifctrl_inst32_low, ibuf_ifctrl_inst_vld, ibuf_ifctrl_pop0_mad32_low, ibuf_ifdp_inst_dbg_disable, ibuf_top_clk_en, ibuf_xx_empty, ibusif_ibuf_no_trans, ibusif_xx_16bit_inst, ibusif_xx_acc_err, ibusif_xx_data, ibusif_xx_ibus_idle, ibusif_xx_trans_cmplt, ibusif_xx_unalign_fetch, ifctrl_ibuf_bypass_vld, ifctrl_ibuf_inst_pipe_down, ifctrl_ibuf_pop_en, ifctrl_xx_ifcancel, ifu_had_fetch_expt_vld, ifu_iu_ex_expt_cur, ifu_iu_ex_expt_vld, ifu_iu_ex_inst, ifu_misc_clk, iu_ifu_ex_stall_noinput, iu_ifu_ex_vld, iu_ifu_inst_fetch, iu_ifu_lsu_inst, iu_ifu_wb_ldst, iu_ifu_wb_stall, iu_yy_xx_dbgon, pad_yy_gate_clk_en_b, pad_yy_test_mode, randclk_ibuf_entry_data_mod_en_w16, randclk_ibuf_pop_mod_en_w3, randclk_ibuf_push_mod_en_w3 ); input cp0_yy_clk_en; input cpuclk; input cpurst_b; input forever_cpuclk; input [31:0] had_ifu_ir; input had_ifu_ir_vld; input ibusif_ibuf_no_trans; input ibusif_xx_16bit_inst; input ibusif_xx_acc_err; input [31:0] ibusif_xx_data; input ibusif_xx_ibus_idle; input ibusif_xx_trans_cmplt; input ibusif_xx_unalign_fetch; input ifctrl_ibuf_bypass_vld; input ifctrl_ibuf_inst_pipe_down; input ifctrl_ibuf_pop_en; input ifctrl_xx_ifcancel; input ifu_misc_clk; input iu_ifu_ex_stall_noinput; input iu_ifu_ex_vld; input iu_ifu_inst_fetch; input iu_ifu_lsu_inst; input iu_ifu_wb_ldst; input iu_ifu_wb_stall; input iu_yy_xx_dbgon; input pad_yy_gate_clk_en_b; input pad_yy_test_mode; input [3 :0] randclk_ibuf_entry_data_mod_en_w16; input randclk_ibuf_pop_mod_en_w3; input randclk_ibuf_push_mod_en_w3; output ibuf_ibusif_inst_fetch; output ibuf_ifctrl_inst32_low; output ibuf_ifctrl_inst_vld; output ibuf_ifctrl_pop0_mad32_low; output ibuf_ifdp_inst_dbg_disable; output ibuf_top_clk_en; output ibuf_xx_empty; output ifu_had_fetch_expt_vld; output ifu_iu_ex_expt_cur; output ifu_iu_ex_expt_vld; output [31:0] ifu_iu_ex_inst; reg [5 :0] pop0; reg pop0_acc_err; reg [15:0] pop0_inst; reg [5 :0] pop0_shift; reg [15:0] pop0_shift_inst; reg pop0_shift_vld; reg pop0_vld; reg pop1_acc_err; reg [15:0] pop1_inst; reg pop1_shift_vld; reg pop1_vld; reg [5 :0] push0; reg [5 :0] push0_shift; wire acc_err_upd_en; wire align_fetch_bypass_32bit; wire cp0_yy_clk_en; wire cpuclk; wire cpurst_b; wire entry0_acc_err; wire entry0_create0_en; wire entry0_create1_en; wire [16:0] entry0_inst; wire entry0_part_flush; wire entry0_randclk_data_mod_en_w16; wire entry0_retire0_en; wire entry0_retire1_en; wire entry0_vld; wire entry1_acc_err; wire entry1_create0_en; wire entry1_create1_en; wire [16:0] entry1_inst; wire entry1_part_flush; wire entry1_randclk_data_mod_en_w16; wire entry1_retire0_en; wire entry1_retire1_en; wire entry1_vld; wire entry2_acc_err; wire entry2_create0_en; wire entry2_create1_en; wire [16:0] entry2_inst; wire entry2_part_flush; wire entry2_randclk_data_mod_en_w16; wire entry2_retire0_en; wire entry2_retire1_en; wire entry2_vld; wire entry3_acc_err; wire entry3_create0_en; wire entry3_create1_en; wire [16:0] entry3_inst; wire entry3_part_flush; wire entry3_randclk_data_mod_en_w16; wire entry3_retire0_en; wire entry3_retire1_en; wire entry3_vld; wire entry4_acc_err; wire entry4_create0_en; wire entry4_create1_en; wire [16:0] entry4_inst; wire entry4_part_flush; wire entry4_randclk_data_mod_en_w16; wire entry4_retire0_en; wire entry4_retire1_en; wire entry4_vld; wire entry5_acc_err; wire entry5_create0_en; wire entry5_create1_en; wire [16:0] entry5_inst; wire entry5_part_flush; wire entry5_randclk_data_mod_en_w16; wire entry5_retire0_en; wire entry5_retire1_en; wire entry5_vld; wire [5 :0] flush_4_entry_ptr; wire [5 :0] flush_5_entry_ptr; wire forever_cpuclk; wire had_create0_en; wire had_create1_en; wire [31:0] had_ifu_ir; wire had_ifu_ir_vld; wire ibuf_acc_err; wire ibuf_create0_en; wire ibuf_create1_en; wire ibuf_empty; wire ibuf_fetch_empty; wire ibuf_fetch_full; wire ibuf_fetch_more_than_two; wire ibuf_fetch_one; wire ibuf_five_avalbe; wire ibuf_flush; wire ibuf_four_avalbe; wire ibuf_full; wire ibuf_ibusif_inst_fetch; wire ibuf_ifctrl_inst32_low; wire ibuf_ifctrl_inst_vld; wire ibuf_ifctrl_pop0_mad32_low; wire ibuf_ifdp_inst_dbg_disable; wire ibuf_inst16; wire ibuf_inst32; wire ibuf_inst_32_vld; wire ibuf_inst_fetch; wire ibuf_no_inst; wire ibuf_no_inst_during_pipe_down; wire ibuf_one_avalbe; wire [5 :0] ibuf_part_flush_ptr; wire ibuf_pop0_mad32_low; wire ibuf_pop0_sys32_low; wire ibuf_pop_upd_clk; wire ibuf_pop_upd_en; wire ibuf_push_upd_clk; wire ibuf_push_upd_en; wire ibuf_retire0_en; wire ibuf_retire0_en_vld; wire ibuf_retire1_en; wire ibuf_three_avalbe; wire ibuf_top_clk_en; wire ibuf_two_avalbe; wire [2 :0] ibuf_vld_num; wire ibuf_xx_empty; wire ibus_create0_en; wire ibus_create1_en; wire ibusif_ibuf_no_trans; wire ibusif_xx_16bit_inst; wire ibusif_xx_acc_err; wire [31:0] ibusif_xx_data; wire ibusif_xx_ibus_idle; wire ibusif_xx_trans_cmplt; wire ibusif_xx_unalign_fetch; wire ifctrl_ibuf_bypass_vld; wire ifctrl_ibuf_inst_pipe_down; wire ifctrl_ibuf_pop_en; wire ifctrl_xx_ifcancel; wire ifu_had_fetch_expt_vld; wire ifu_iu_ex_expt_cur; wire ifu_iu_ex_expt_vld; wire [31:0] ifu_iu_ex_inst; wire ifu_misc_clk; wire iu_ifu_ex_stall_noinput; wire iu_ifu_ex_vld; wire iu_ifu_inst_fetch; wire iu_ifu_lsu_inst; wire iu_ifu_wb_ldst; wire iu_ifu_wb_stall; wire iu_yy_xx_dbgon; wire pad_yy_gate_clk_en_b; wire pad_yy_test_mode; wire pop0_inst_32; wire pop0_shift_lsu_inst; wire pop0_shift_mad_low; wire pop0_shift_sys_low; wire [5 :0] pop1; wire [5 :0] pop1_shift; wire [5 :0] push1; wire [3 :0] randclk_ibuf_entry_data_mod_en_w16; wire randclk_ibuf_pop_mod_en_w3; wire randclk_ibuf_push_mod_en_w3; wire unalign_fetch_bypass_16bit; parameter IDLE = 2'b00, POP1_EN = 2'b01, POP2_EN = 2'b10, FLUSH = 2'b11; gated_clk_cell x_ibuf_push_upd_clkhdr ( .clk_in (forever_cpuclk ), .clk_out (ibuf_push_upd_clk ), .external_en (1'b0 ), .global_en (cp0_yy_clk_en ), .local_en (ibuf_push_upd_en ), .module_en (randclk_ibuf_push_mod_en_w3), .pad_yy_gate_clk_en_b (pad_yy_gate_clk_en_b ), .pad_yy_test_mode (pad_yy_test_mode ) ); assign ibuf_push_upd_en = ibuf_flush || ibuf_create0_en || iu_ifu_inst_fetch; gated_clk_cell x_ibuf_pop_upd_clkhdr ( .clk_in (forever_cpuclk ), .clk_out (ibuf_pop_upd_clk ), .external_en (1'b0 ), .global_en (cp0_yy_clk_en ), .local_en (ibuf_pop_upd_en ), .module_en (randclk_ibuf_pop_mod_en_w3), .pad_yy_gate_clk_en_b (pad_yy_gate_clk_en_b ), .pad_yy_test_mode (pad_yy_test_mode ) ); assign ibuf_pop_upd_en = ibuf_retire0_en_vld && !ibuf_flush; assign acc_err_upd_en = iu_yy_xx_dbgon || ibusif_xx_trans_cmplt && (ibusif_xx_acc_err || entry0_acc_err || entry1_acc_err || entry2_acc_err || entry3_acc_err || entry4_acc_err || entry5_acc_err ); assign ibuf_top_clk_en = acc_err_upd_en; parameter ENTRY_NUM = 6; cr_ifu_ibuf_entry x_ibuf_entry_0 ( .cp0_yy_clk_en (cp0_yy_clk_en ), .cpuclk (cpuclk ), .cpurst_b (cpurst_b ), .entry_acc_err (entry0_acc_err ), .entry_create0_en (entry0_create0_en ), .entry_create1_en (entry0_create1_en ), .entry_inst (entry0_inst ), .entry_part_flush (entry0_part_flush ), .entry_randclk_data_mod_en_w16 (entry0_randclk_data_mod_en_w16), .entry_retire0_en (entry0_retire0_en ), .entry_retire1_en (entry0_retire1_en ), .entry_vld (entry0_vld ), .forever_cpuclk (forever_cpuclk ), .had_ifu_ir (had_ifu_ir ), .ibuf_flush (ibuf_flush ), .ibuf_no_inst_during_pipe_down (ibuf_no_inst_during_pipe_down ), .ibusif_xx_acc_err (ibusif_xx_acc_err ), .ibusif_xx_data (ibusif_xx_data ), .ifu_misc_clk (ifu_misc_clk ), .iu_yy_xx_dbgon (iu_yy_xx_dbgon ), .pad_yy_gate_clk_en_b (pad_yy_gate_clk_en_b ), .pad_yy_test_mode (pad_yy_test_mode ) ); cr_ifu_ibuf_entry x_ibuf_entry_1 ( .cp0_yy_clk_en (cp0_yy_clk_en ), .cpuclk (cpuclk ), .cpurst_b (cpurst_b ), .entry_acc_err (entry1_acc_err ), .entry_create0_en (entry1_create0_en ), .entry_create1_en (entry1_create1_en ), .entry_inst (entry1_inst ), .entry_part_flush (entry1_part_flush ), .entry_randclk_data_mod_en_w16 (entry1_randclk_data_mod_en_w16), .entry_retire0_en (entry1_retire0_en ), .entry_retire1_en (entry1_retire1_en ), .entry_vld (entry1_vld ), .forever_cpuclk (forever_cpuclk ), .had_ifu_ir (had_ifu_ir ), .ibuf_flush (ibuf_flush ), .ibuf_no_inst_during_pipe_down (ibuf_no_inst_during_pipe_down ), .ibusif_xx_acc_err (ibusif_xx_acc_err ), .ibusif_xx_data (ibusif_xx_data ), .ifu_misc_clk (ifu_misc_clk ), .iu_yy_xx_dbgon (iu_yy_xx_dbgon ), .pad_yy_gate_clk_en_b (pad_yy_gate_clk_en_b ), .pad_yy_test_mode (pad_yy_test_mode ) ); cr_ifu_ibuf_entry x_ibuf_entry_2 ( .cp0_yy_clk_en (cp0_yy_clk_en ), .cpuclk (cpuclk ), .cpurst_b (cpurst_b ), .entry_acc_err (entry2_acc_err ), .entry_create0_en (entry2_create0_en ), .entry_create1_en (entry2_create1_en ), .entry_inst (entry2_inst ), .entry_part_flush (entry2_part_flush ), .entry_randclk_data_mod_en_w16 (entry2_randclk_data_mod_en_w16), .entry_retire0_en (entry2_retire0_en ), .entry_retire1_en (entry2_retire1_en ), .entry_vld (entry2_vld ), .forever_cpuclk (forever_cpuclk ), .had_ifu_ir (had_ifu_ir ), .ibuf_flush (ibuf_flush ), .ibuf_no_inst_during_pipe_down (ibuf_no_inst_during_pipe_down ), .ibusif_xx_acc_err (ibusif_xx_acc_err ), .ibusif_xx_data (ibusif_xx_data ), .ifu_misc_clk (ifu_misc_clk ), .iu_yy_xx_dbgon (iu_yy_xx_dbgon ), .pad_yy_gate_clk_en_b (pad_yy_gate_clk_en_b ), .pad_yy_test_mode (pad_yy_test_mode ) ); cr_ifu_ibuf_entry x_ibuf_entry_3 ( .cp0_yy_clk_en (cp0_yy_clk_en ), .cpuclk (cpuclk ), .cpurst_b (cpurst_b ), .entry_acc_err (entry3_acc_err ), .entry_create0_en (entry3_create0_en ), .entry_create1_en (entry3_create1_en ), .entry_inst (entry3_inst ), .entry_part_flush (entry3_part_flush ), .entry_randclk_data_mod_en_w16 (entry3_randclk_data_mod_en_w16), .entry_retire0_en (entry3_retire0_en ), .entry_retire1_en (entry3_retire1_en ), .entry_vld (entry3_vld ), .forever_cpuclk (forever_cpuclk ), .had_ifu_ir (had_ifu_ir ), .ibuf_flush (ibuf_flush ), .ibuf_no_inst_during_pipe_down (ibuf_no_inst_during_pipe_down ), .ibusif_xx_acc_err (ibusif_xx_acc_err ), .ibusif_xx_data (ibusif_xx_data ), .ifu_misc_clk (ifu_misc_clk ), .iu_yy_xx_dbgon (iu_yy_xx_dbgon ), .pad_yy_gate_clk_en_b (pad_yy_gate_clk_en_b ), .pad_yy_test_mode (pad_yy_test_mode ) ); cr_ifu_ibuf_entry x_ibuf_entry_4 ( .cp0_yy_clk_en (cp0_yy_clk_en ), .cpuclk (cpuclk ), .cpurst_b (cpurst_b ), .entry_acc_err (entry4_acc_err ), .entry_create0_en (entry4_create0_en ), .entry_create1_en (entry4_create1_en ), .entry_inst (entry4_inst ), .entry_part_flush (entry4_part_flush ), .entry_randclk_data_mod_en_w16 (entry4_randclk_data_mod_en_w16), .entry_retire0_en (entry4_retire0_en ), .entry_retire1_en (entry4_retire1_en ), .entry_vld (entry4_vld ), .forever_cpuclk (forever_cpuclk ), .had_ifu_ir (had_ifu_ir ), .ibuf_flush (ibuf_flush ), .ibuf_no_inst_during_pipe_down (ibuf_no_inst_during_pipe_down ), .ibusif_xx_acc_err (ibusif_xx_acc_err ), .ibusif_xx_data (ibusif_xx_data ), .ifu_misc_clk (ifu_misc_clk ), .iu_yy_xx_dbgon (iu_yy_xx_dbgon ), .pad_yy_gate_clk_en_b (pad_yy_gate_clk_en_b ), .pad_yy_test_mode (pad_yy_test_mode ) ); cr_ifu_ibuf_entry x_ibuf_entry_5 ( .cp0_yy_clk_en (cp0_yy_clk_en ), .cpuclk (cpuclk ), .cpurst_b (cpurst_b ), .entry_acc_err (entry5_acc_err ), .entry_create0_en (entry5_create0_en ), .entry_create1_en (entry5_create1_en ), .entry_inst (entry5_inst ), .entry_part_flush (entry5_part_flush ), .entry_randclk_data_mod_en_w16 (entry5_randclk_data_mod_en_w16), .entry_retire0_en (entry5_retire0_en ), .entry_retire1_en (entry5_retire1_en ), .entry_vld (entry5_vld ), .forever_cpuclk (forever_cpuclk ), .had_ifu_ir (had_ifu_ir ), .ibuf_flush (ibuf_flush ), .ibuf_no_inst_during_pipe_down (ibuf_no_inst_during_pipe_down ), .ibusif_xx_acc_err (ibusif_xx_acc_err ), .ibusif_xx_data (ibusif_xx_data ), .ifu_misc_clk (ifu_misc_clk ), .iu_yy_xx_dbgon (iu_yy_xx_dbgon ), .pad_yy_gate_clk_en_b (pad_yy_gate_clk_en_b ), .pad_yy_test_mode (pad_yy_test_mode ) ); assign entry0_randclk_data_mod_en_w16 = randclk_ibuf_entry_data_mod_en_w16[0]; assign entry1_randclk_data_mod_en_w16 = randclk_ibuf_entry_data_mod_en_w16[1]; assign entry2_randclk_data_mod_en_w16 = randclk_ibuf_entry_data_mod_en_w16[2]; assign entry3_randclk_data_mod_en_w16 = randclk_ibuf_entry_data_mod_en_w16[3]; assign entry4_randclk_data_mod_en_w16 = randclk_ibuf_entry_data_mod_en_w16[3]; assign entry5_randclk_data_mod_en_w16 = randclk_ibuf_entry_data_mod_en_w16[3]; always @( entry3_acc_err or entry1_vld or entry1_acc_err or entry2_inst[15:0] or entry5_inst[15:0] or entry4_acc_err or entry0_acc_err or entry5_acc_err or entry5_vld or entry4_inst[15:0] or entry0_vld or entry2_vld or entry1_inst[15:0] or entry3_vld or entry2_acc_err or entry4_vld or entry3_inst[15:0] or pop0[5:0] or entry0_inst[15:0]) begin case(pop0[ENTRY_NUM-1:0]) 6'b0001: begin pop0_vld = entry0_vld; pop0_inst[15:0] = entry0_inst[15:0]; pop0_acc_err = entry0_acc_err; end 6'b0010: begin pop0_vld = entry1_vld; pop0_inst[15:0] = entry1_inst[15:0]; pop0_acc_err = entry1_acc_err; end 6'b0100: begin pop0_vld = entry2_vld; pop0_inst[15:0] = entry2_inst[15:0]; pop0_acc_err = entry2_acc_err; end 6'b1000: begin pop0_vld = entry3_vld; pop0_inst[15:0] = entry3_inst[15:0]; pop0_acc_err = entry3_acc_err; end 6'b10000: begin pop0_vld = entry4_vld; pop0_inst[15:0] = entry4_inst[15:0]; pop0_acc_err = entry4_acc_err; end 6'b100000: begin pop0_vld = entry5_vld; pop0_inst[15:0] = entry5_inst[15:0]; pop0_acc_err = entry5_acc_err; end default: begin pop0_vld = 1'bx; pop0_inst[15:0] = 16'bx; pop0_acc_err = 1'bx; end endcase end always @( entry3_acc_err or entry1_vld or entry1_acc_err or entry2_inst[15:0] or entry5_inst[15:0] or entry4_acc_err or entry0_acc_err or entry5_vld or entry5_acc_err or entry4_inst[15:0] or entry2_vld or entry0_vld or entry1_inst[15:0] or entry3_vld or entry4_vld or entry2_acc_err or entry3_inst[15:0] or pop1[5:0] or entry0_inst[15:0]) begin case(pop1[ENTRY_NUM-1:0]) 6'b0001: begin pop1_vld = entry0_vld; pop1_inst[15:0] = entry0_inst[15:0]; pop1_acc_err = entry0_acc_err; end 6'b0010: begin pop1_vld = entry1_vld; pop1_inst[15:0] = entry1_inst[15:0]; pop1_acc_err = entry1_acc_err; end 6'b0100: begin pop1_vld = entry2_vld; pop1_inst[15:0] = entry2_inst[15:0]; pop1_acc_err = entry2_acc_err; end 6'b1000: begin pop1_vld = entry3_vld; pop1_inst[15:0] = entry3_inst[15:0]; pop1_acc_err = entry3_acc_err; end 6'b10000: begin pop1_vld = entry4_vld; pop1_inst[15:0] = entry4_inst[15:0]; pop1_acc_err = entry4_acc_err; end 6'b100000: begin pop1_vld = entry5_vld; pop1_inst[15:0] = entry5_inst[15:0]; pop1_acc_err = entry5_acc_err; end default: begin pop1_vld = 1'bx; pop1_inst[15:0] = 16'bx; pop1_acc_err = 1'bx; end endcase end assign align_fetch_bypass_32bit = ibuf_empty && !ibusif_xx_16bit_inst; assign unalign_fetch_bypass_16bit = ibusif_xx_unalign_fetch; assign ibus_create0_en = ibusif_xx_trans_cmplt && !(ifctrl_ibuf_bypass_vld && (align_fetch_bypass_32bit || unalign_fetch_bypass_16bit)); assign had_create0_en = iu_yy_xx_dbgon && had_ifu_ir_vld; assign ibuf_create0_en = ibus_create0_en || had_create0_en; assign ibus_create1_en = ibusif_xx_trans_cmplt && !ifctrl_ibuf_bypass_vld && !ibusif_xx_unalign_fetch; assign had_create1_en = had_create0_en && had_ifu_ir[1:0] == 2'b11; assign ibuf_create1_en = ibus_create1_en || had_create1_en; always @(posedge ibuf_push_upd_clk or negedge cpurst_b) begin if(!cpurst_b) push0[ENTRY_NUM-1:0] <= {{(ENTRY_NUM-1){1'b0}}, 1'b1}; else if(iu_ifu_inst_fetch && iu_ifu_wb_stall) push0[ENTRY_NUM-1:0] <= pop0_shift[ENTRY_NUM-1:0]; else if(ibuf_flush) push0[ENTRY_NUM-1:0] <= pop0[ENTRY_NUM-1:0]; else if(ibuf_create0_en) push0[ENTRY_NUM-1:0] <= push0_shift[ENTRY_NUM-1:0]; end always @( push0[5:0] or ibuf_create1_en) begin if(ibuf_create1_en) push0_shift[ENTRY_NUM-1:0] = {push0[ENTRY_NUM-3:0], push0[ENTRY_NUM-1:ENTRY_NUM-2]}; else push0_shift[ENTRY_NUM-1:0] = {push0[ENTRY_NUM-2:0], push0[ENTRY_NUM-1]}; end assign {entry5_create0_en, entry4_create0_en, entry3_create0_en, entry2_create0_en, entry1_create0_en, entry0_create0_en} = push0[ENTRY_NUM-1:0] & {ENTRY_NUM{ibuf_create0_en}}; assign push1[ENTRY_NUM-1:0] = {push0[ENTRY_NUM-2:0], push0[ENTRY_NUM-1]}; assign {entry5_create1_en, entry4_create1_en, entry3_create1_en, entry2_create1_en, entry1_create1_en, entry0_create1_en} = push1[ENTRY_NUM-1:0] & {ENTRY_NUM{ibuf_create1_en}}; assign ibuf_retire0_en = pop0_vld && ifctrl_ibuf_pop_en; assign ibuf_retire1_en = ibuf_inst32 && ifctrl_ibuf_pop_en; assign ibuf_retire0_en_vld = ibuf_retire0_en; assign ibuf_inst_32_vld = ibuf_inst32; always @(posedge ibuf_pop_upd_clk or negedge cpurst_b) begin if(!cpurst_b) pop0[ENTRY_NUM-1:0] <= {{(ENTRY_NUM-1){1'b0}}, 1'b1}; else if(ibuf_flush) pop0[ENTRY_NUM-1:0] <= pop0[ENTRY_NUM-1:0]; else if(ibuf_retire0_en_vld) pop0[ENTRY_NUM-1:0] <= pop0_shift[ENTRY_NUM-1:0]; end always @( pop0[5:0] or ibuf_inst_32_vld) begin if(ibuf_inst_32_vld) pop0_shift[ENTRY_NUM-1:0] = {pop0[ENTRY_NUM-3:0], pop0[ENTRY_NUM-1:ENTRY_NUM-2]}; else pop0_shift[ENTRY_NUM-1:0] = {pop0[ENTRY_NUM-2:0], pop0[ENTRY_NUM-1]}; end assign {entry5_retire0_en, entry4_retire0_en, entry3_retire0_en, entry2_retire0_en, entry1_retire0_en, entry0_retire0_en} = pop0[ENTRY_NUM-1:0] & {ENTRY_NUM{ibuf_retire0_en}}; assign pop1[ENTRY_NUM-1:0] = {pop0[ENTRY_NUM-2:0], pop0[ENTRY_NUM-1]}; assign {entry5_retire1_en, entry4_retire1_en, entry3_retire1_en, entry2_retire1_en, entry1_retire1_en, entry0_retire1_en} = pop1[ENTRY_NUM-1:0] & {ENTRY_NUM{ibuf_retire1_en}}; assign flush_4_entry_ptr[ENTRY_NUM-1:0] = ~(pop0[ENTRY_NUM-1:0] | pop1[ENTRY_NUM-1:0]); assign flush_5_entry_ptr[ENTRY_NUM-1:0] = ~pop0[ENTRY_NUM-1:0]; assign ibuf_part_flush_ptr[ENTRY_NUM-1:0] = ibuf_inst32 ? flush_4_entry_ptr[ENTRY_NUM-1:0] : flush_5_entry_ptr[ENTRY_NUM-1:0]; assign {entry5_part_flush, entry4_part_flush, entry3_part_flush, entry2_part_flush, entry1_part_flush, entry0_part_flush} = ibuf_part_flush_ptr[ENTRY_NUM-1:0] & {ENTRY_NUM{iu_ifu_inst_fetch && iu_ifu_wb_stall}}; assign pop0_inst_32 = pop0_inst[1:0] == 2'b11; assign ibuf_inst32 = pop0_vld && pop1_vld && pop0_inst_32; assign ibuf_inst16 = pop0_vld && !pop0_inst_32; assign ibuf_flush = ifctrl_xx_ifcancel; assign ibuf_vld_num[2:0] = entry0_vld + entry1_vld + entry2_vld + entry3_vld + entry4_vld + entry5_vld; assign ibuf_one_avalbe = (ibuf_vld_num[2:0] == 3'b101); assign ibuf_full = (ibuf_vld_num[2:0] == 3'b110); assign ibuf_no_inst_during_pipe_down = ifctrl_ibuf_inst_pipe_down && ibuf_no_inst && 1'b0; assign ibuf_two_avalbe = ibuf_vld_num[2:0] == 3'b100; assign ibuf_three_avalbe = ibuf_vld_num[2:0] == 3'b011; assign ibuf_four_avalbe = ibuf_vld_num[2:0] == 3'b010; assign ibuf_five_avalbe = ibuf_vld_num[2:0] == 3'b001; assign ibuf_empty = ibuf_vld_num[2:0] == 3'b000; assign ibuf_no_inst = !ibuf_inst32 && !ibuf_inst16; assign ibuf_acc_err = (ibuf_inst32 && (pop0_acc_err || pop1_acc_err)) || (ibuf_inst16 && pop0_acc_err); assign ibuf_fetch_empty = ibuf_empty; always @( entry1_vld or pop0_shift[5:0] or entry2_inst[15:0] or entry5_inst[15:0] or entry5_vld or entry4_inst[15:0] or entry0_vld or entry2_vld or entry1_inst[15:0] or entry3_vld or entry4_vld or entry3_inst[15:0] or entry0_inst[15:0]) begin case(pop0_shift[ENTRY_NUM-1:0]) 6'b0001: begin pop0_shift_vld = entry0_vld; pop0_shift_inst[15:0] = entry0_inst[15:0]; end 6'b0010: begin pop0_shift_vld = entry1_vld; pop0_shift_inst[15:0] = entry1_inst[15:0]; end 6'b0100: begin pop0_shift_vld = entry2_vld; pop0_shift_inst[15:0] = entry2_inst[15:0]; end 6'b1000: begin pop0_shift_vld = entry3_vld; pop0_shift_inst[15:0] = entry3_inst[15:0]; end 6'b10000: begin pop0_shift_vld = entry4_vld; pop0_shift_inst[15:0] = entry4_inst[15:0]; end 6'b100000: begin pop0_shift_vld = entry5_vld; pop0_shift_inst[15:0] = entry5_inst[15:0]; end default: begin pop0_shift_vld = 1'bx; pop0_shift_inst[15:0] = 16'bx; end endcase end assign pop1_shift[ENTRY_NUM-1:0] = {pop0_shift[ENTRY_NUM-2:0], pop0_shift[ENTRY_NUM-1]}; always @( entry1_vld or pop1_shift[5:0] or entry5_vld or entry0_vld or entry2_vld or entry3_vld or entry4_vld) begin case(pop1_shift[ENTRY_NUM-1:0]) 6'b0001: begin pop1_shift_vld = entry0_vld; end 6'b0010: begin pop1_shift_vld = entry1_vld; end 6'b0100: begin pop1_shift_vld = entry2_vld; end 6'b1000: begin pop1_shift_vld = entry3_vld; end 6'b10000: begin pop1_shift_vld = entry4_vld; end 6'b100000: begin pop1_shift_vld = entry5_vld; end default: begin pop1_shift_vld = 1'bx; end endcase end assign pop0_shift_mad_low = pop0_shift_vld && pop0_shift_inst[6:0] == 7'b0110011; assign pop0_shift_sys_low = pop0_shift_vld && pop0_shift_inst[6:0] == 7'b1110011; assign pop0_shift_lsu_inst = pop0_shift_vld && (pop0_shift_inst[6:0] == 7'b0100011 || pop0_shift_inst[6:0] == 7'b0000011 || {pop0_shift_inst[14:13],pop0_shift_inst[0]} == 3'b100); assign ibuf_fetch_more_than_two = ibuf_two_avalbe && ibusif_ibuf_no_trans || ibuf_two_avalbe && ibusif_xx_ibus_idle && !iu_ifu_wb_ldst && !iu_ifu_ex_stall_noinput && !(pop0_shift_lsu_inst && ibuf_inst16) && !(pop0_shift_mad_low && ibuf_inst16) && !(pop0_shift_sys_low && ibuf_inst16) || ibuf_three_avalbe && ibusif_ibuf_no_trans || ibuf_three_avalbe && ibusif_xx_ibus_idle && !ibuf_pop0_mad32_low && !ibuf_pop0_sys32_low && !(iu_ifu_lsu_inst && iu_ifu_ex_stall_noinput) && (!iu_ifu_wb_ldst && !iu_ifu_ex_stall_noinput ); assign ibuf_fetch_one = ibuf_one_avalbe && ibusif_ibuf_no_trans && (!iu_ifu_wb_ldst && !iu_ifu_ex_stall_noinput || !iu_ifu_ex_vld) || ibuf_one_avalbe && ibusif_xx_ibus_idle && (ibuf_inst32 || pop0_shift_vld && pop0_shift_inst[1:0] == 2'b11) && !iu_ifu_lsu_inst && !pop0_shift_sys_low && !pop0_shift_lsu_inst && !pop0_shift_mad_low && (!iu_ifu_wb_ldst && !iu_ifu_ex_stall_noinput ); assign ibuf_fetch_full = ibuf_full && ibusif_ibuf_no_trans && (ibuf_inst32 || pop0_shift_vld && pop0_shift_inst[1:0] == 2'b11) && !iu_ifu_lsu_inst && !pop0_shift_sys_low && !pop0_shift_lsu_inst && !pop0_shift_mad_low && !iu_ifu_wb_ldst && !iu_ifu_ex_stall_noinput; assign ibuf_inst_fetch = ibuf_fetch_empty || ibuf_five_avalbe || ibuf_four_avalbe || ibuf_fetch_one || ibuf_fetch_full || ibuf_fetch_more_than_two; assign ibuf_pop0_mad32_low = pop0_inst[6:2] == 5'b01100; assign ibuf_pop0_sys32_low = pop0_inst[6:2] == 5'b11100; assign ibuf_xx_empty = iu_ifu_ex_vld ? !pop0_shift_vld : ibuf_empty; assign ibuf_ibusif_inst_fetch = ibuf_inst_fetch; assign ibuf_ifctrl_inst_vld = pop0_shift_vld && pop1_shift_vld && pop0_shift_inst[1:0] == 2'b11 || pop0_shift_vld && pop0_shift_inst[1:0] != 2'b11; assign ibuf_ifctrl_inst32_low = iu_ifu_ex_vld ? pop0_shift_vld && !pop1_shift_vld && pop0_shift_inst[1:0] == 2'b11 : pop0_vld && !pop1_vld && !ibuf_inst16; assign ibuf_ifctrl_pop0_mad32_low = ibuf_pop0_mad32_low; assign ifu_iu_ex_inst[31:0] = {pop1_inst[15:0], pop0_inst[15:0]}; assign ifu_iu_ex_expt_vld = ibuf_acc_err; assign ifu_iu_ex_expt_cur = pop0_acc_err; assign ifu_had_fetch_expt_vld = ibuf_acc_err; assign ibuf_ifdp_inst_dbg_disable = 1'b0; endmodule module cr_ifu_ibuf_entry( cp0_yy_clk_en, cpuclk, cpurst_b, entry_acc_err, entry_create0_en, entry_create1_en, entry_inst, entry_part_flush, entry_randclk_data_mod_en_w16, entry_retire0_en, entry_retire1_en, entry_vld, forever_cpuclk, had_ifu_ir, ibuf_flush, ibuf_no_inst_during_pipe_down, ibusif_xx_acc_err, ibusif_xx_data, ifu_misc_clk, iu_yy_xx_dbgon, pad_yy_gate_clk_en_b, pad_yy_test_mode ); input cp0_yy_clk_en; input cpuclk; input cpurst_b; input entry_create0_en; input entry_create1_en; input entry_part_flush; input entry_randclk_data_mod_en_w16; input entry_retire0_en; input entry_retire1_en; input forever_cpuclk; input [31:0] had_ifu_ir; input ibuf_flush; input ibuf_no_inst_during_pipe_down; input ibusif_xx_acc_err; input [31:0] ibusif_xx_data; input ifu_misc_clk; input iu_yy_xx_dbgon; input pad_yy_gate_clk_en_b; input pad_yy_test_mode; output entry_acc_err; output [16:0] entry_inst; output entry_vld; reg entry_acc_err; reg [16:0] entry_inst; reg entry_vld; wire cp0_yy_clk_en; wire cpuclk; wire cpurst_b; wire entry_create; wire entry_create0_en; wire entry_create1_en; wire entry_part_flush; wire entry_randclk_data_mod_en_w16; wire entry_retire; wire entry_retire0_en; wire entry_retire1_en; wire forever_cpuclk; wire [31:0] had_ifu_ir; wire ibuf_data_upd_clk; wire ibuf_data_upd_en; wire ibuf_flush; wire ibuf_no_inst_during_pipe_down; wire [16:0] ibus_inst_info_high; wire [16:0] ibus_inst_info_low; wire ibusif_xx_acc_err; wire [31:0] ibusif_xx_data; wire ifu_misc_clk; wire iu_yy_xx_dbgon; wire pad_yy_gate_clk_en_b; wire pad_yy_test_mode; gated_clk_cell x_ibuf_data_upd_clkhdr ( .clk_in (forever_cpuclk ), .clk_out (ibuf_data_upd_clk ), .external_en (1'b0 ), .global_en (cp0_yy_clk_en ), .local_en (ibuf_data_upd_en ), .module_en (entry_randclk_data_mod_en_w16), .pad_yy_gate_clk_en_b (pad_yy_gate_clk_en_b ), .pad_yy_test_mode (pad_yy_test_mode ) ); assign ibuf_data_upd_en = entry_create0_en || entry_create1_en; assign entry_create = entry_create0_en || entry_create1_en; assign entry_retire = entry_retire0_en || entry_retire1_en; always @(posedge cpuclk or negedge cpurst_b) begin if(!cpurst_b) entry_vld <= 1'b0; else if(entry_part_flush) entry_vld <= 1'b0; else if(ibuf_flush) entry_vld <= 1'b0; else if(entry_create) entry_vld <= 1'b1; else if(entry_retire) entry_vld <= 1'b0; else entry_vld <= entry_vld; end assign ibus_inst_info_high[16:0] = {1'b0, ibusif_xx_data[15:0]}; assign ibus_inst_info_low[16:0] = {1'b0, ibusif_xx_data[31:16]}; always @(posedge ibuf_data_upd_clk) begin if(iu_yy_xx_dbgon) begin if(entry_create0_en) entry_inst[16:0] <= {1'b0, had_ifu_ir[15:0]}; else if(entry_create1_en) entry_inst[16:0] <= {1'b0, had_ifu_ir[31:16]}; else entry_inst[16:0] <= entry_inst[16:0]; end else begin if(entry_create0_en) begin if(ibuf_no_inst_during_pipe_down) entry_inst[16:0] <= ibus_inst_info_low[16:0]; else entry_inst[16:0] <= ibus_inst_info_high[16:0]; end else if(entry_create1_en) entry_inst[16:0] <= ibus_inst_info_low[16:0]; else entry_inst[16:0] <= entry_inst[16:0]; end end always @(posedge ifu_misc_clk or negedge cpurst_b) begin if(!cpurst_b) entry_acc_err <= 1'b0; else if(entry_create) entry_acc_err <= ibusif_xx_acc_err; else entry_acc_err <= entry_acc_err; end endmodule module cr_ifu_ibusif( bmu_xx_ibus_acc_err, bmu_xx_ibus_data, bmu_xx_ibus_grnt, bmu_xx_ibus_trans_cmplt, cp0_ifu_in_lpmd, cp0_ifu_lpmd_req, cp0_yy_clk_en, cp0_yy_machine_mode_aft_dbg, cpurst_b, cru_ifu_acc_ca, forever_cpuclk, ibuf_ibusif_inst_fetch, ibusif_ibuf_no_trans, ibusif_ifctrl_inst_mad32_high, ibusif_ifctrl_inst_no_bypass, ibusif_top_clk_en, ibusif_xx_16bit_inst, ibusif_xx_acc_err, ibusif_xx_data, ibusif_xx_ibus_idle, ibusif_xx_trans_cmplt, ibusif_xx_unalign_fetch, ifu_bmu_addr, ifu_bmu_idle, ifu_bmu_prot, ifu_bmu_req, ifu_bmu_wfd1, ifu_cp0_lpmd_ack, ifu_iu_ibus_idle, ifu_iu_vector_ibus_in_idle, ifu_iu_xx_ibus_data, ifu_misc_clk, iu_ifu_addr, iu_ifu_data_fetch, iu_ifu_data_fetch_for_data, iu_ifu_inst_fetch, iu_ifu_inst_fetch_for_data, iu_ifu_inst_fetch_mask, iu_ifu_security_violation, iu_yy_xx_dbgon, pad_yy_gate_clk_en_b, pad_yy_test_mode, pmp_ifu_acc_scu ); input bmu_xx_ibus_acc_err; input [31:0] bmu_xx_ibus_data; input bmu_xx_ibus_grnt; input bmu_xx_ibus_trans_cmplt; input cp0_ifu_in_lpmd; input cp0_ifu_lpmd_req; input cp0_yy_clk_en; input cp0_yy_machine_mode_aft_dbg; input cpurst_b; input cru_ifu_acc_ca; input forever_cpuclk; input ibuf_ibusif_inst_fetch; input ifu_misc_clk; input [30:0] iu_ifu_addr; input iu_ifu_data_fetch; input iu_ifu_data_fetch_for_data; input iu_ifu_inst_fetch; input iu_ifu_inst_fetch_for_data; input iu_ifu_inst_fetch_mask; input iu_ifu_security_violation; input iu_yy_xx_dbgon; input pad_yy_gate_clk_en_b; input pad_yy_test_mode; input pmp_ifu_acc_scu; output ibusif_ibuf_no_trans; output ibusif_ifctrl_inst_mad32_high; output ibusif_ifctrl_inst_no_bypass; output ibusif_top_clk_en; output ibusif_xx_16bit_inst; output ibusif_xx_acc_err; output [31:0] ibusif_xx_data; output ibusif_xx_ibus_idle; output ibusif_xx_trans_cmplt; output ibusif_xx_unalign_fetch; output [31:0] ifu_bmu_addr; output ifu_bmu_idle; output [3 :0] ifu_bmu_prot; output ifu_bmu_req; output ifu_bmu_wfd1; output ifu_cp0_lpmd_ack; output ifu_iu_ibus_idle; output ifu_iu_vector_ibus_in_idle; output [31:0] ifu_iu_xx_ibus_data; reg abort_cur_st; reg abort_nxt_st; reg [29:0] addr_cnt; reg [2 :0] cur_st; reg [3 :0] ibus_prot_reg; reg [2 :0] nxt_st; reg unalign_fetch_reg; wire addr_cnt_high_upd_clk; wire addr_cnt_high_upd_en; wire addr_cnt_high_upd_en_local; wire addr_cnt_low_upd_clk; wire addr_cnt_low_upd_en; wire addr_cnt_upd_en; wire bmu_xx_ibus_acc_err; wire [31:0] bmu_xx_ibus_data; wire [31:0] bmu_xx_ibus_data_aft_pol; wire bmu_xx_ibus_grnt; wire bmu_xx_ibus_trans_cmplt; wire change_flow_vld; wire cp0_ifu_in_lpmd; wire cp0_ifu_lpmd_req; wire cp0_yy_clk_en; wire cp0_yy_machine_mode_aft_dbg; wire cpurst_b; wire cru_ifu_acc_ca; wire flop_out_bus; wire forever_cpuclk; wire ibuf_ibusif_inst_fetch; wire ibus_abort_trig; wire ibus_acc_err; wire [30:0] ibus_addr; wire ibus_busy; wire [31:0] ibus_data; wire ibus_inst_fetch_cmplt; wire ibus_inst_mad; wire ibus_inst_mad32_high; wire ibus_inst_no_bypass; wire ibus_inst_req; wire ibus_no_outstanding; wire [30:0] ibus_nonseq_addr; wire [3 :0] ibus_prot; wire ibus_prot_buf; wire ibus_prot_buf_sel; wire ibus_req; wire [30:0] ibus_seq_addr; wire ibus_trans_abort; wire ibusif_ibuf_no_trans; wire ibusif_ifctrl_inst_mad32_high; wire ibusif_ifctrl_inst_no_bypass; wire ibusif_top_clk_en; wire ibusif_xx_16bit_inst; wire ibusif_xx_acc_err; wire [31:0] ibusif_xx_data; wire ibusif_xx_ibus_idle; wire ibusif_xx_trans_cmplt; wire ibusif_xx_unalign_fetch; wire [31:0] ifu_bmu_addr; wire ifu_bmu_idle; wire [3 :0] ifu_bmu_prot; wire ifu_bmu_req; wire ifu_bmu_wfd1; wire ifu_cp0_lpmd_ack; wire ifu_iu_ibus_idle; wire ifu_iu_vector_ibus_in_idle; wire [31:0] ifu_iu_xx_ibus_data; wire ifu_misc_clk; wire [29:0] inc_addr; wire inst_chgflw_for_data; wire internal_inst_fetch; wire internal_inst_fetch_pre; wire [30:0] iu_ifu_addr; wire iu_ifu_data_fetch; wire iu_ifu_data_fetch_for_data; wire iu_ifu_inst_fetch; wire iu_ifu_inst_fetch_for_data; wire iu_ifu_inst_fetch_mask; wire iu_ifu_security_violation; wire iu_yy_xx_dbgon; wire lpmd_mask; wire pad_yy_gate_clk_en_b; wire pad_yy_test_mode; wire pmp_ifu_acc_scu; wire sm_upd_clk; wire sm_upd_en; parameter IDLE = 3'b001, WFG1 = 3'b010, WFD1 = 3'b011, WFD1WFG2 = 3'b000, WFD1WFD2 = 3'b110; parameter ABORT_IDLE = 1'b0, ABORT_VLD = 1'b1; gated_clk_cell x_ibus_addr_cnt_low_clkhdr ( .clk_in (forever_cpuclk ), .clk_out (addr_cnt_low_upd_clk), .external_en (1'b0 ), .global_en (cp0_yy_clk_en ), .local_en (addr_cnt_low_upd_en ), .module_en (1'b0 ), .pad_yy_gate_clk_en_b (pad_yy_gate_clk_en_b), .pad_yy_test_mode (pad_yy_test_mode ) ); gated_clk_cell x_ibus_addr_cnt_high_clkhdr ( .clk_in (forever_cpuclk ), .clk_out (addr_cnt_high_upd_clk), .external_en (1'b0 ), .global_en (cp0_yy_clk_en ), .local_en (addr_cnt_high_upd_en ), .module_en (1'b0 ), .pad_yy_gate_clk_en_b (pad_yy_gate_clk_en_b ), .pad_yy_test_mode (pad_yy_test_mode ) ); gated_clk_cell x_sm_upd_clkhdr ( .clk_in (forever_cpuclk ), .clk_out (sm_upd_clk ), .external_en (1'b0 ), .global_en (cp0_yy_clk_en ), .local_en (sm_upd_en ), .module_en (1'b0 ), .pad_yy_gate_clk_en_b (pad_yy_gate_clk_en_b), .pad_yy_test_mode (pad_yy_test_mode ) ); assign sm_upd_en = ibus_req || iu_ifu_inst_fetch_for_data || bmu_xx_ibus_trans_cmplt || (cur_st != IDLE); assign ibus_seq_addr[30:0] = {addr_cnt[29:0], 1'b0}; assign ibus_nonseq_addr[30:0] = iu_ifu_addr[30:0]; assign ibus_addr[30:0] = (iu_ifu_inst_fetch_for_data || iu_ifu_data_fetch_for_data) ? ibus_nonseq_addr[30:0] : ibus_seq_addr[30:0]; assign change_flow_vld = iu_ifu_inst_fetch; assign addr_cnt_upd_en = change_flow_vld || (!iu_ifu_data_fetch_for_data && bmu_xx_ibus_grnt); assign addr_cnt_high_upd_en = change_flow_vld || bmu_xx_ibus_grnt && (addr_cnt[10] ^ inc_addr[10]); assign addr_cnt_low_upd_en = addr_cnt_upd_en; always @(posedge addr_cnt_low_upd_clk or negedge cpurst_b) begin if(!cpurst_b) addr_cnt[9:0] <= 10'b0; else if(addr_cnt_low_upd_en) addr_cnt[9:0] <= inc_addr[9:0]; end assign addr_cnt_high_upd_en_local = 1'b0; always @(posedge addr_cnt_high_upd_clk or negedge cpurst_b) begin if(!cpurst_b) addr_cnt[29:10] <= 20'b0; else if(addr_cnt_high_upd_en) addr_cnt[29:10] <= inc_addr[29:10]; end assign inc_addr[29:0] = ibus_addr[30:1] + bmu_xx_ibus_grnt; assign bmu_xx_ibus_data_aft_pol[31:0] = bmu_xx_ibus_data[31:0]; assign ibus_data[31:0] = {bmu_xx_ibus_data_aft_pol[31:16], unalign_fetch_reg ? bmu_xx_ibus_data_aft_pol[31:16] : bmu_xx_ibus_data_aft_pol[15:0]}; always @(posedge sm_upd_clk or negedge cpurst_b) begin if(!cpurst_b) unalign_fetch_reg <= 1'b0; else if(change_flow_vld) unalign_fetch_reg <= ibus_addr[0]; else if(ibus_inst_fetch_cmplt) unalign_fetch_reg <= 1'b0; end assign ibus_prot[3:0] = {cru_ifu_acc_ca, pmp_ifu_acc_scu, cp0_yy_machine_mode_aft_dbg, 1'b0}; always @(posedge sm_upd_clk) begin if(ibus_prot_buf) ibus_prot_reg[3:0] <= ibus_prot[3:0]; end assign inst_chgflw_for_data = iu_ifu_inst_fetch_for_data; assign internal_inst_fetch_pre = ibuf_ibusif_inst_fetch && !inst_chgflw_for_data && !addr_cnt_high_upd_en_local || iu_ifu_inst_fetch; assign internal_inst_fetch = internal_inst_fetch_pre && !lpmd_mask && !iu_yy_xx_dbgon && !iu_ifu_inst_fetch_mask && !iu_ifu_security_violation; assign lpmd_mask = cp0_ifu_in_lpmd || cp0_ifu_lpmd_req; assign flop_out_bus = 1'b0; always @(posedge sm_upd_clk or negedge cpurst_b) begin if(!cpurst_b) cur_st[2:0] <= IDLE; else cur_st[2:0] <= nxt_st[2:0]; end always @( internal_inst_fetch or bmu_xx_ibus_trans_cmplt or bmu_xx_ibus_grnt or flop_out_bus or cur_st) begin case(cur_st) IDLE: begin if(internal_inst_fetch) begin if(bmu_xx_ibus_grnt) nxt_st = WFD1; else nxt_st = WFG1; end else nxt_st = IDLE; end WFG1: begin if(bmu_xx_ibus_grnt) nxt_st = WFD1; else nxt_st = WFG1; end WFD1: begin if(bmu_xx_ibus_trans_cmplt) begin if(internal_inst_fetch) begin if(bmu_xx_ibus_grnt) nxt_st = WFD1; else nxt_st = WFG1; end else nxt_st = IDLE; end else if(internal_inst_fetch && flop_out_bus) begin if(bmu_xx_ibus_grnt) nxt_st = WFD1WFD2; else nxt_st = WFD1WFG2; end else if(internal_inst_fetch) nxt_st = WFD1WFG2; else nxt_st = WFD1; end WFD1WFG2: begin if(bmu_xx_ibus_trans_cmplt) begin if(bmu_xx_ibus_grnt) nxt_st = WFD1; else nxt_st = WFG1; end else begin if(bmu_xx_ibus_grnt && flop_out_bus) nxt_st = WFD1WFD2; else nxt_st = WFD1WFG2; end end WFD1WFD2: begin if(bmu_xx_ibus_trans_cmplt) nxt_st = WFD1; else nxt_st = WFD1WFD2; end default: begin nxt_st = IDLE; end endcase end assign ibus_busy = !cur_st[0]; assign ibus_inst_fetch_cmplt = ((cur_st == WFD1) || (cur_st == WFD1WFG2) || (cur_st == WFD1WFD2) ) && bmu_xx_ibus_trans_cmplt && !ibus_trans_abort; assign ibus_acc_err = ((cur_st == WFD1) || (cur_st == WFD1WFG2) || (cur_st == WFD1WFD2) ) && bmu_xx_ibus_acc_err; assign ibus_inst_req = (cur_st == IDLE) && internal_inst_fetch || (cur_st == WFG1) || (cur_st == WFD1) && internal_inst_fetch || (cur_st == WFD1WFG2); assign ibus_abort_trig = (cur_st == WFD1) && !bmu_xx_ibus_trans_cmplt && change_flow_vld; assign ibus_no_outstanding = (cur_st == IDLE) || (cur_st == WFG1) || (cur_st == WFD1) && bmu_xx_ibus_trans_cmplt || (cur_st == WFD1WFG2) && bmu_xx_ibus_trans_cmplt; assign ibus_prot_buf = ((cur_st == IDLE) || (cur_st == WFD1)) && ((nxt_st == WFG1) || (nxt_st == WFD1WFG2)); assign ibus_prot_buf_sel = (cur_st == WFG1) || (cur_st == WFD1WFG2); assign ibus_req = ibus_inst_req || iu_ifu_data_fetch; always @(posedge ifu_misc_clk or negedge cpurst_b) begin if(!cpurst_b) abort_cur_st <= ABORT_IDLE; else abort_cur_st <= abort_nxt_st; end always @( abort_cur_st or bmu_xx_ibus_trans_cmplt or ibus_abort_trig) begin case(abort_cur_st) ABORT_IDLE: begin abort_nxt_st = ABORT_IDLE; if(ibus_abort_trig) abort_nxt_st = ABORT_VLD; end ABORT_VLD: begin abort_nxt_st = ABORT_VLD; if(bmu_xx_ibus_trans_cmplt) abort_nxt_st = ABORT_IDLE; end default: begin abort_nxt_st = ABORT_IDLE; end endcase end assign ibus_trans_abort = (abort_cur_st == ABORT_VLD); assign ibusif_top_clk_en = ibus_abort_trig || ibus_trans_abort; assign ibus_inst_no_bypass = ibus_inst_mad; assign ibus_inst_mad = 1'b0; assign ibus_inst_mad32_high = 1'b0; assign ifu_bmu_req = ibus_req; assign ifu_bmu_idle = ibus_no_outstanding; assign ifu_bmu_wfd1 = (cur_st == WFD1) || (cur_st == IDLE); assign ifu_bmu_addr[31:0] = {ibus_addr[30:1], 2'b0}; assign ifu_bmu_prot[3:0] = ibus_prot_buf_sel ? ibus_prot_reg[3:0] : ibus_prot[3:0]; assign ibusif_ifctrl_inst_no_bypass = ibus_inst_no_bypass; assign ibusif_ifctrl_inst_mad32_high = ibus_inst_mad32_high; assign ibusif_ibuf_no_trans = (cur_st == IDLE); assign ibusif_xx_ibus_idle = !ibus_busy; assign ibusif_xx_data[31:0] = ibus_data[31:0]; assign ibusif_xx_acc_err = ibus_acc_err && !iu_yy_xx_dbgon; assign ibusif_xx_unalign_fetch = unalign_fetch_reg; assign ibusif_xx_trans_cmplt = ibus_inst_fetch_cmplt && !iu_ifu_inst_fetch_mask && !iu_yy_xx_dbgon; assign ibusif_xx_16bit_inst = !(ibus_data[1:0] == 2'b11); assign ifu_iu_ibus_idle = !ibus_busy; assign ifu_iu_vector_ibus_in_idle = (cur_st == IDLE); assign ifu_iu_xx_ibus_data[31:0] = bmu_xx_ibus_data_aft_pol[31:0]; assign ifu_cp0_lpmd_ack = cp0_ifu_lpmd_req && (cur_st == IDLE); endmodule module cr_ifu_ifctrl( cpuclk, cpurst_b, had_ifu_ir_vld, ibuf_ifctrl_inst32_low, ibuf_ifctrl_inst_vld, ibuf_ifctrl_pop0_mad32_low, ibuf_ifdp_inst_dbg_disable, ibuf_xx_empty, ibusif_ifctrl_inst_mad32_high, ibusif_ifctrl_inst_no_bypass, ibusif_xx_16bit_inst, ibusif_xx_trans_cmplt, ibusif_xx_unalign_fetch, ifctrl_ibuf_bypass_vld, ifctrl_ibuf_inst_pipe_down, ifctrl_ibuf_pop_en, ifctrl_xx_ifcancel, ifu_iu_ex_inst_vld, ifu_iu_inst_buf_inst_dbg_disable, ifu_iu_inst_buf_inst_vld, iu_ifu_ex_stall, iu_ifu_inst_fetch, iu_ifu_inst_fetch_without_dbg_disable, iu_ifu_wb_stall, iu_yy_xx_dbgon, iu_yy_xx_flush, split_ifctrl_hs_stall, split_ifctrl_hs_stall_part ); input cpuclk; input cpurst_b; input had_ifu_ir_vld; input ibuf_ifctrl_inst32_low; input ibuf_ifctrl_inst_vld; input ibuf_ifctrl_pop0_mad32_low; input ibuf_ifdp_inst_dbg_disable; input ibuf_xx_empty; input ibusif_ifctrl_inst_mad32_high; input ibusif_ifctrl_inst_no_bypass; input ibusif_xx_16bit_inst; input ibusif_xx_trans_cmplt; input ibusif_xx_unalign_fetch; input iu_ifu_ex_stall; input iu_ifu_inst_fetch; input iu_ifu_inst_fetch_without_dbg_disable; input iu_ifu_wb_stall; input iu_yy_xx_dbgon; input iu_yy_xx_flush; input split_ifctrl_hs_stall; input split_ifctrl_hs_stall_part; output ifctrl_ibuf_bypass_vld; output ifctrl_ibuf_inst_pipe_down; output ifctrl_ibuf_pop_en; output ifctrl_xx_ifcancel; output ifu_iu_ex_inst_vld; output ifu_iu_inst_buf_inst_dbg_disable; output ifu_iu_inst_buf_inst_vld; reg ex_inst_vld; wire cpuclk; wire cpurst_b; wire had_ifu_ir_vld; wire ibuf_bypass_vld; wire ibuf_ifctrl_inst32_low; wire ibuf_ifctrl_inst_vld; wire ibuf_ifctrl_pop0_mad32_low; wire ibuf_ifdp_inst_dbg_disable; wire ibuf_inst_vld; wire ibuf_pop_en; wire ibuf_xx_empty; wire ibus_bypass_inst_vld; wire ibusif_ifctrl_inst_mad32_high; wire ibusif_ifctrl_inst_no_bypass; wire ibusif_xx_16bit_inst; wire ibusif_xx_trans_cmplt; wire ibusif_xx_unalign_fetch; wire if_cancel; wire if_cancel_for_pipeline; wire if_inst_stall; wire if_inst_vld; wire if_inst_vld_for_ex; wire if_inst_vld_for_ex_aft_hs; wire if_pipe_down; wire ifctrl_ibuf_bypass_vld; wire ifctrl_ibuf_inst_pipe_down; wire ifctrl_ibuf_pop_en; wire ifctrl_xx_ifcancel; wire ifu_iu_ex_inst_vld; wire ifu_iu_inst_buf_inst_dbg_disable; wire ifu_iu_inst_buf_inst_vld; wire inst_vld; wire iu_ifu_ex_stall; wire iu_ifu_inst_fetch; wire iu_ifu_inst_fetch_without_dbg_disable; wire iu_ifu_wb_stall; wire iu_yy_xx_dbgon; wire iu_yy_xx_flush; wire random_inst_vld; wire split_ifctrl_hs_inst_vld; wire split_ifctrl_hs_stall; wire split_ifctrl_hs_stall_part; wire split_ifctrl_mad_stall; wire split_ifctrl_push_pop_stall; assign ibuf_inst_vld = ibuf_ifctrl_inst_vld && !split_ifctrl_hs_stall; assign inst_vld = ibuf_inst_vld || ibus_bypass_inst_vld || iu_yy_xx_dbgon && had_ifu_ir_vld; assign ibus_bypass_inst_vld = ibusif_xx_trans_cmplt && !split_ifctrl_hs_stall_part && ( (ibuf_xx_empty && (!ibusif_xx_unalign_fetch || ibusif_xx_16bit_inst ) && !ibusif_ifctrl_inst_no_bypass ) || (ibuf_ifctrl_inst32_low && !(ibuf_ifctrl_pop0_mad32_low && ibusif_ifctrl_inst_mad32_high ) ) ); assign if_inst_vld = inst_vld && !if_cancel; assign if_inst_vld_for_ex = if_inst_vld && !if_inst_stall; assign if_inst_stall = split_ifctrl_push_pop_stall || split_ifctrl_mad_stall; assign if_cancel = iu_ifu_inst_fetch || iu_yy_xx_flush; assign if_cancel_for_pipeline = iu_ifu_inst_fetch_without_dbg_disable && !split_ifctrl_hs_stall_part || iu_yy_xx_flush; assign if_pipe_down = ex_inst_vld && !iu_ifu_ex_stall; assign split_ifctrl_hs_inst_vld = 1'b0; assign split_ifctrl_mad_stall = 1'b0; assign split_ifctrl_push_pop_stall = 1'b0; assign if_inst_vld_for_ex_aft_hs = if_inst_vld_for_ex || split_ifctrl_hs_inst_vld; always @(posedge cpuclk or negedge cpurst_b) begin if(!cpurst_b) ex_inst_vld <= 1'b0; else if(if_cancel_for_pipeline) ex_inst_vld <= 1'b0; else if(!iu_ifu_ex_stall) ex_inst_vld <= if_inst_vld_for_ex_aft_hs; end assign ifu_iu_ex_inst_vld = ex_inst_vld; assign ifu_iu_inst_buf_inst_vld = ibuf_inst_vld; assign ifu_iu_inst_buf_inst_dbg_disable = ibuf_ifdp_inst_dbg_disable; assign ibuf_bypass_vld = if_pipe_down && ibus_bypass_inst_vld && !random_inst_vld; assign ibuf_pop_en = if_pipe_down && !random_inst_vld; assign random_inst_vld = 1'b0; assign ifctrl_xx_ifcancel = iu_yy_xx_flush || iu_ifu_inst_fetch && !iu_ifu_wb_stall; assign ifctrl_ibuf_bypass_vld = ibuf_bypass_vld && 1'b0; assign ifctrl_ibuf_inst_pipe_down = if_pipe_down && !random_inst_vld; assign ifctrl_ibuf_pop_en = ibuf_pop_en; endmodule module cr_ifu_ifdp( had_core_dbg_mode_req, had_ifu_inst_bkpt_dbq_req, had_ifu_inst_bkpt_dbqexp_req, had_yy_xx_dp_index_mbee, ifu_had_inst_dbg_disable, ifu_had_split_first, ifu_iu_ex_inst_bkpt, ifu_iu_ex_inst_dbg_disable, ifu_iu_ex_int_spcu_mask, ifu_iu_ex_int_spcu_vld, ifu_iu_ex_ni, ifu_iu_ex_prvlg_expt_vld, ifu_iu_ex_rand_vld, ifu_iu_ex_sp_oper, ifu_iu_inst_bkpt_dbg_occur_vld, ifu_iu_inst_bkpt_dbgexp_occur_vld, ifu_iu_spcu_retire_mask, iu_ifu_kill_inst ); input had_core_dbg_mode_req; input had_ifu_inst_bkpt_dbq_req; input had_ifu_inst_bkpt_dbqexp_req; input had_yy_xx_dp_index_mbee; input iu_ifu_kill_inst; output ifu_had_inst_dbg_disable; output ifu_had_split_first; output ifu_iu_ex_inst_bkpt; output ifu_iu_ex_inst_dbg_disable; output ifu_iu_ex_int_spcu_mask; output ifu_iu_ex_int_spcu_vld; output ifu_iu_ex_ni; output ifu_iu_ex_prvlg_expt_vld; output ifu_iu_ex_rand_vld; output ifu_iu_ex_sp_oper; output ifu_iu_inst_bkpt_dbg_occur_vld; output ifu_iu_inst_bkpt_dbgexp_occur_vld; output ifu_iu_spcu_retire_mask; wire had_core_dbg_mode_req; wire had_ifu_inst_bkpt_dbq_req; wire had_ifu_inst_bkpt_dbqexp_req; wire had_yy_xx_dp_index_mbee; wire if_bkpt_vld; wire ifu_had_inst_dbg_disable; wire ifu_had_split_first; wire ifu_iu_ex_inst_bkpt; wire ifu_iu_ex_inst_dbg_disable; wire ifu_iu_ex_int_spcu_mask; wire ifu_iu_ex_int_spcu_vld; wire ifu_iu_ex_ni; wire ifu_iu_ex_prvlg_expt_vld; wire ifu_iu_ex_rand_vld; wire ifu_iu_ex_sp_oper; wire ifu_iu_inst_bkpt_dbg_occur_vld; wire ifu_iu_inst_bkpt_dbgexp_occur_vld; wire ifu_iu_spcu_retire_mask; wire inst_bkpt; wire inst_bkpt_aft_hs; wire iu_ifu_kill_inst; parameter EBREAK = 32'h00100073; assign if_bkpt_vld = had_core_dbg_mode_req || had_ifu_inst_bkpt_dbq_req || had_ifu_inst_bkpt_dbqexp_req || iu_ifu_kill_inst && had_yy_xx_dp_index_mbee; assign inst_bkpt = if_bkpt_vld; assign ifu_iu_ex_inst_dbg_disable = 1'b0; assign inst_bkpt_aft_hs = inst_bkpt; assign ifu_iu_ex_inst_bkpt = inst_bkpt_aft_hs; assign ifu_iu_ex_int_spcu_mask = 1'b0; assign ifu_iu_ex_int_spcu_vld = 1'b0; assign ifu_iu_ex_ni = 1'b0; assign ifu_iu_ex_prvlg_expt_vld = 1'b0; assign ifu_iu_ex_rand_vld = 1'b0; assign ifu_iu_ex_sp_oper = 1'b0; assign ifu_iu_spcu_retire_mask = 1'b0; assign ifu_had_split_first = 1'b1; assign ifu_had_inst_dbg_disable = 1'b0; assign ifu_iu_inst_bkpt_dbg_occur_vld = had_ifu_inst_bkpt_dbq_req; assign ifu_iu_inst_bkpt_dbgexp_occur_vld = 1'b0; endmodule module cr_ifu_randclk( randclk_ibuf_entry_data_mod_en_w16, randclk_ibuf_pop_mod_en_w3, randclk_ibuf_push_mod_en_w3 ); output [3:0] randclk_ibuf_entry_data_mod_en_w16; output randclk_ibuf_pop_mod_en_w3; output randclk_ibuf_push_mod_en_w3; wire [3:0] randclk_ibuf_entry_data_mod_en_w16; wire randclk_ibuf_pop_mod_en_w3; wire randclk_ibuf_push_mod_en_w3; assign randclk_ibuf_push_mod_en_w3 = 1'b0; assign randclk_ibuf_pop_mod_en_w3 = 1'b0; assign randclk_ibuf_entry_data_mod_en_w16[3:0] = 4'b0; endmodule module cr_ifu_top( bmu_xx_ibus_acc_err, bmu_xx_ibus_data, bmu_xx_ibus_grnt, bmu_xx_ibus_trans_cmplt, cp0_ifu_in_lpmd, cp0_ifu_lpmd_req, cp0_yy_clk_en, cp0_yy_machine_mode_aft_dbg, cpurst_b, forever_cpuclk, had_core_dbg_mode_req, had_ifu_inst_bkpt_dbq_req, had_ifu_inst_bkpt_dbqexp_req, had_ifu_ir, had_ifu_ir_vld, had_yy_xx_dp_index_mbee, ifu_bmu_addr, ifu_bmu_idle, ifu_bmu_prot, ifu_bmu_req, ifu_bmu_wfd1, ifu_cp0_lpmd_ack, ifu_had_fetch_expt_vld, ifu_had_inst_dbg_disable, ifu_had_split_first, ifu_iu_ex_expt_cur, ifu_iu_ex_expt_vld, ifu_iu_ex_inst, ifu_iu_ex_inst_bkpt, ifu_iu_ex_inst_dbg_disable, ifu_iu_ex_inst_vld, ifu_iu_ex_int_spcu_mask, ifu_iu_ex_int_spcu_vld, ifu_iu_ex_ni, ifu_iu_ex_prvlg_expt_vld, ifu_iu_ex_rand_vld, ifu_iu_ex_sp_oper, ifu_iu_ibus_idle, ifu_iu_inst_bkpt_dbg_occur_vld, ifu_iu_inst_bkpt_dbgexp_occur_vld, ifu_iu_inst_buf_inst_dbg_disable, ifu_iu_inst_buf_inst_vld, ifu_iu_spcu_retire_mask, ifu_iu_vector_ibus_in_idle, ifu_iu_xx_ibus_data, iu_ifu_addr, iu_ifu_data_fetch, iu_ifu_data_fetch_for_data, iu_ifu_ex_stall, iu_ifu_ex_stall_noinput, iu_ifu_ex_vld, iu_ifu_inst_fetch, iu_ifu_inst_fetch_for_data, iu_ifu_inst_fetch_mask, iu_ifu_inst_fetch_without_dbg_disable, iu_ifu_kill_inst, iu_ifu_lsu_inst, iu_ifu_security_violation, iu_ifu_wb_ldst, iu_ifu_wb_stall, iu_yy_xx_dbgon, iu_yy_xx_flush, pad_yy_gate_clk_en_b, pad_yy_test_mode, split_ifctrl_hs_stall, split_ifctrl_hs_stall_part ); input bmu_xx_ibus_acc_err; input [31:0] bmu_xx_ibus_data; input bmu_xx_ibus_grnt; input bmu_xx_ibus_trans_cmplt; input cp0_ifu_in_lpmd; input cp0_ifu_lpmd_req; input cp0_yy_clk_en; input cp0_yy_machine_mode_aft_dbg; input cpurst_b; input forever_cpuclk; input had_core_dbg_mode_req; input had_ifu_inst_bkpt_dbq_req; input had_ifu_inst_bkpt_dbqexp_req; input [31:0] had_ifu_ir; input had_ifu_ir_vld; input had_yy_xx_dp_index_mbee; input [30:0] iu_ifu_addr; input iu_ifu_data_fetch; input iu_ifu_data_fetch_for_data; input iu_ifu_ex_stall; input iu_ifu_ex_stall_noinput; input iu_ifu_ex_vld; input iu_ifu_inst_fetch; input iu_ifu_inst_fetch_for_data; input iu_ifu_inst_fetch_mask; input iu_ifu_inst_fetch_without_dbg_disable; input iu_ifu_kill_inst; input iu_ifu_lsu_inst; input iu_ifu_security_violation; input iu_ifu_wb_ldst; input iu_ifu_wb_stall; input iu_yy_xx_dbgon; input iu_yy_xx_flush; input pad_yy_gate_clk_en_b; input pad_yy_test_mode; input split_ifctrl_hs_stall; input split_ifctrl_hs_stall_part; output [31:0] ifu_bmu_addr; output ifu_bmu_idle; output [3 :0] ifu_bmu_prot; output ifu_bmu_req; output ifu_bmu_wfd1; output ifu_cp0_lpmd_ack; output ifu_had_fetch_expt_vld; output ifu_had_inst_dbg_disable; output ifu_had_split_first; output ifu_iu_ex_expt_cur; output ifu_iu_ex_expt_vld; output [31:0] ifu_iu_ex_inst; output ifu_iu_ex_inst_bkpt; output ifu_iu_ex_inst_dbg_disable; output ifu_iu_ex_inst_vld; output ifu_iu_ex_int_spcu_mask; output ifu_iu_ex_int_spcu_vld; output ifu_iu_ex_ni; output ifu_iu_ex_prvlg_expt_vld; output ifu_iu_ex_rand_vld; output ifu_iu_ex_sp_oper; output ifu_iu_ibus_idle; output ifu_iu_inst_bkpt_dbg_occur_vld; output ifu_iu_inst_bkpt_dbgexp_occur_vld; output ifu_iu_inst_buf_inst_dbg_disable; output ifu_iu_inst_buf_inst_vld; output ifu_iu_spcu_retire_mask; output ifu_iu_vector_ibus_in_idle; output [31:0] ifu_iu_xx_ibus_data; wire bmu_xx_ibus_acc_err; wire [31:0] bmu_xx_ibus_data; wire bmu_xx_ibus_grnt; wire bmu_xx_ibus_trans_cmplt; wire cp0_ifu_in_lpmd; wire cp0_ifu_lpmd_req; wire cp0_yy_clk_en; wire cp0_yy_machine_mode_aft_dbg; wire cpurst_b; wire forever_cpuclk; wire forever_cpuclk_gated_ifu; wire had_core_dbg_mode_req; wire had_ifu_inst_bkpt_dbq_req; wire had_ifu_inst_bkpt_dbqexp_req; wire [31:0] had_ifu_ir; wire had_ifu_ir_vld; wire had_yy_xx_dp_index_mbee; wire ibuf_ibusif_inst_fetch; wire ibuf_ifctrl_inst32_low; wire ibuf_ifctrl_inst_vld; wire ibuf_ifctrl_pop0_mad32_low; wire ibuf_ifdp_inst_dbg_disable; wire ibuf_top_clk_en; wire ibuf_xx_empty; wire ibusif_ibuf_no_trans; wire ibusif_ifctrl_inst_mad32_high; wire ibusif_ifctrl_inst_no_bypass; wire ibusif_top_clk_en; wire ibusif_xx_16bit_inst; wire ibusif_xx_acc_err; wire [31:0] ibusif_xx_data; wire ibusif_xx_ibus_idle; wire ibusif_xx_trans_cmplt; wire ibusif_xx_unalign_fetch; wire ifctrl_ibuf_bypass_vld; wire ifctrl_ibuf_inst_pipe_down; wire ifctrl_ibuf_pop_en; wire ifctrl_xx_ifcancel; wire [31:0] ifu_bmu_addr; wire ifu_bmu_idle; wire [3 :0] ifu_bmu_prot; wire ifu_bmu_req; wire ifu_bmu_wfd1; wire ifu_cp0_lpmd_ack; wire ifu_had_fetch_expt_vld; wire ifu_had_inst_dbg_disable; wire ifu_had_split_first; wire ifu_iu_ex_expt_cur; wire ifu_iu_ex_expt_vld; wire [31:0] ifu_iu_ex_inst; wire ifu_iu_ex_inst_bkpt; wire ifu_iu_ex_inst_dbg_disable; wire ifu_iu_ex_inst_vld; wire ifu_iu_ex_int_spcu_mask; wire ifu_iu_ex_int_spcu_vld; wire ifu_iu_ex_ni; wire ifu_iu_ex_prvlg_expt_vld; wire ifu_iu_ex_rand_vld; wire ifu_iu_ex_sp_oper; wire ifu_iu_ibus_idle; wire ifu_iu_inst_bkpt_dbg_occur_vld; wire ifu_iu_inst_bkpt_dbgexp_occur_vld; wire ifu_iu_inst_buf_inst_dbg_disable; wire ifu_iu_inst_buf_inst_vld; wire ifu_iu_spcu_retire_mask; wire ifu_iu_vector_ibus_in_idle; wire [31:0] ifu_iu_xx_ibus_data; wire ifu_misc_clk; wire ifu_misc_upd_en; wire [30:0] iu_ifu_addr; wire iu_ifu_data_fetch; wire iu_ifu_data_fetch_for_data; wire iu_ifu_ex_stall; wire iu_ifu_ex_stall_noinput; wire iu_ifu_ex_vld; wire iu_ifu_inst_fetch; wire iu_ifu_inst_fetch_for_data; wire iu_ifu_inst_fetch_mask; wire iu_ifu_inst_fetch_without_dbg_disable; wire iu_ifu_kill_inst; wire iu_ifu_lsu_inst; wire iu_ifu_security_violation; wire iu_ifu_wb_ldst; wire iu_ifu_wb_stall; wire iu_yy_xx_dbgon; wire iu_yy_xx_flush; wire pad_yy_gate_clk_en_b; wire pad_yy_test_mode; wire [3 :0] randclk_ibuf_entry_data_mod_en_w16; wire randclk_ibuf_pop_mod_en_w3; wire randclk_ibuf_push_mod_en_w3; wire split_ifctrl_hs_stall; wire split_ifctrl_hs_stall_part; gated_clk_cell x_gated_cpuclk_cell_ifu ( .clk_in (forever_cpuclk ), .clk_out (forever_cpuclk_gated_ifu), .external_en (1'b0 ), .global_en (cp0_yy_clk_en ), .local_en (1'b1 ), .module_en (1'b1 ), .pad_yy_gate_clk_en_b (pad_yy_gate_clk_en_b ), .pad_yy_test_mode (pad_yy_test_mode ) ); gated_clk_cell x_entry_ifu_misc_clkhdr ( .clk_in (forever_cpuclk ), .clk_out (ifu_misc_clk ), .external_en (1'b0 ), .global_en (cp0_yy_clk_en ), .local_en (ifu_misc_upd_en ), .module_en (1'b0 ), .pad_yy_gate_clk_en_b (pad_yy_gate_clk_en_b), .pad_yy_test_mode (pad_yy_test_mode ) ); assign ifu_misc_upd_en = ibuf_top_clk_en || ibusif_top_clk_en; cr_ifu_ibusif x_ibusif ( .bmu_xx_ibus_acc_err (bmu_xx_ibus_acc_err ), .bmu_xx_ibus_data (bmu_xx_ibus_data ), .bmu_xx_ibus_grnt (bmu_xx_ibus_grnt ), .bmu_xx_ibus_trans_cmplt (bmu_xx_ibus_trans_cmplt ), .cp0_ifu_in_lpmd (cp0_ifu_in_lpmd ), .cp0_ifu_lpmd_req (cp0_ifu_lpmd_req ), .cp0_yy_clk_en (cp0_yy_clk_en ), .cp0_yy_machine_mode_aft_dbg (cp0_yy_machine_mode_aft_dbg ), .cpurst_b (cpurst_b ), .cru_ifu_acc_ca (1'b0 ), .forever_cpuclk (forever_cpuclk ), .ibuf_ibusif_inst_fetch (ibuf_ibusif_inst_fetch ), .ibusif_ibuf_no_trans (ibusif_ibuf_no_trans ), .ibusif_ifctrl_inst_mad32_high (ibusif_ifctrl_inst_mad32_high), .ibusif_ifctrl_inst_no_bypass (ibusif_ifctrl_inst_no_bypass ), .ibusif_top_clk_en (ibusif_top_clk_en ), .ibusif_xx_16bit_inst (ibusif_xx_16bit_inst ), .ibusif_xx_acc_err (ibusif_xx_acc_err ), .ibusif_xx_data (ibusif_xx_data ), .ibusif_xx_ibus_idle (ibusif_xx_ibus_idle ), .ibusif_xx_trans_cmplt (ibusif_xx_trans_cmplt ), .ibusif_xx_unalign_fetch (ibusif_xx_unalign_fetch ), .ifu_bmu_addr (ifu_bmu_addr ), .ifu_bmu_idle (ifu_bmu_idle ), .ifu_bmu_prot (ifu_bmu_prot ), .ifu_bmu_req (ifu_bmu_req ), .ifu_bmu_wfd1 (ifu_bmu_wfd1 ), .ifu_cp0_lpmd_ack (ifu_cp0_lpmd_ack ), .ifu_iu_ibus_idle (ifu_iu_ibus_idle ), .ifu_iu_vector_ibus_in_idle (ifu_iu_vector_ibus_in_idle ), .ifu_iu_xx_ibus_data (ifu_iu_xx_ibus_data ), .ifu_misc_clk (ifu_misc_clk ), .iu_ifu_addr (iu_ifu_addr ), .iu_ifu_data_fetch (iu_ifu_data_fetch ), .iu_ifu_data_fetch_for_data (iu_ifu_data_fetch_for_data ), .iu_ifu_inst_fetch (iu_ifu_inst_fetch ), .iu_ifu_inst_fetch_for_data (iu_ifu_inst_fetch_for_data ), .iu_ifu_inst_fetch_mask (iu_ifu_inst_fetch_mask ), .iu_ifu_security_violation (iu_ifu_security_violation ), .iu_yy_xx_dbgon (iu_yy_xx_dbgon ), .pad_yy_gate_clk_en_b (pad_yy_gate_clk_en_b ), .pad_yy_test_mode (pad_yy_test_mode ), .pmp_ifu_acc_scu (1'b0 ) ); cr_ifu_ibuf x_ibuf ( .cp0_yy_clk_en (cp0_yy_clk_en ), .cpuclk (forever_cpuclk_gated_ifu ), .cpurst_b (cpurst_b ), .forever_cpuclk (forever_cpuclk ), .had_ifu_ir (had_ifu_ir ), .had_ifu_ir_vld (had_ifu_ir_vld ), .ibuf_ibusif_inst_fetch (ibuf_ibusif_inst_fetch ), .ibuf_ifctrl_inst32_low (ibuf_ifctrl_inst32_low ), .ibuf_ifctrl_inst_vld (ibuf_ifctrl_inst_vld ), .ibuf_ifctrl_pop0_mad32_low (ibuf_ifctrl_pop0_mad32_low ), .ibuf_ifdp_inst_dbg_disable (ibuf_ifdp_inst_dbg_disable ), .ibuf_top_clk_en (ibuf_top_clk_en ), .ibuf_xx_empty (ibuf_xx_empty ), .ibusif_ibuf_no_trans (ibusif_ibuf_no_trans ), .ibusif_xx_16bit_inst (ibusif_xx_16bit_inst ), .ibusif_xx_acc_err (ibusif_xx_acc_err ), .ibusif_xx_data (ibusif_xx_data ), .ibusif_xx_ibus_idle (ibusif_xx_ibus_idle ), .ibusif_xx_trans_cmplt (ibusif_xx_trans_cmplt ), .ibusif_xx_unalign_fetch (ibusif_xx_unalign_fetch ), .ifctrl_ibuf_bypass_vld (ifctrl_ibuf_bypass_vld ), .ifctrl_ibuf_inst_pipe_down (ifctrl_ibuf_inst_pipe_down ), .ifctrl_ibuf_pop_en (ifctrl_ibuf_pop_en ), .ifctrl_xx_ifcancel (ifctrl_xx_ifcancel ), .ifu_had_fetch_expt_vld (ifu_had_fetch_expt_vld ), .ifu_iu_ex_expt_cur (ifu_iu_ex_expt_cur ), .ifu_iu_ex_expt_vld (ifu_iu_ex_expt_vld ), .ifu_iu_ex_inst (ifu_iu_ex_inst ), .ifu_misc_clk (ifu_misc_clk ), .iu_ifu_ex_stall_noinput (iu_ifu_ex_stall_noinput ), .iu_ifu_ex_vld (iu_ifu_ex_vld ), .iu_ifu_inst_fetch (iu_ifu_inst_fetch ), .iu_ifu_lsu_inst (iu_ifu_lsu_inst ), .iu_ifu_wb_ldst (iu_ifu_wb_ldst ), .iu_ifu_wb_stall (iu_ifu_wb_stall ), .iu_yy_xx_dbgon (iu_yy_xx_dbgon ), .pad_yy_gate_clk_en_b (pad_yy_gate_clk_en_b ), .pad_yy_test_mode (pad_yy_test_mode ), .randclk_ibuf_entry_data_mod_en_w16 (randclk_ibuf_entry_data_mod_en_w16), .randclk_ibuf_pop_mod_en_w3 (randclk_ibuf_pop_mod_en_w3 ), .randclk_ibuf_push_mod_en_w3 (randclk_ibuf_push_mod_en_w3 ) ); cr_ifu_ifdp x_ifdp ( .had_core_dbg_mode_req (had_core_dbg_mode_req ), .had_ifu_inst_bkpt_dbq_req (had_ifu_inst_bkpt_dbq_req ), .had_ifu_inst_bkpt_dbqexp_req (had_ifu_inst_bkpt_dbqexp_req ), .had_yy_xx_dp_index_mbee (had_yy_xx_dp_index_mbee ), .ifu_had_inst_dbg_disable (ifu_had_inst_dbg_disable ), .ifu_had_split_first (ifu_had_split_first ), .ifu_iu_ex_inst_bkpt (ifu_iu_ex_inst_bkpt ), .ifu_iu_ex_inst_dbg_disable (ifu_iu_ex_inst_dbg_disable ), .ifu_iu_ex_int_spcu_mask (ifu_iu_ex_int_spcu_mask ), .ifu_iu_ex_int_spcu_vld (ifu_iu_ex_int_spcu_vld ), .ifu_iu_ex_ni (ifu_iu_ex_ni ), .ifu_iu_ex_prvlg_expt_vld (ifu_iu_ex_prvlg_expt_vld ), .ifu_iu_ex_rand_vld (ifu_iu_ex_rand_vld ), .ifu_iu_ex_sp_oper (ifu_iu_ex_sp_oper ), .ifu_iu_inst_bkpt_dbg_occur_vld (ifu_iu_inst_bkpt_dbg_occur_vld ), .ifu_iu_inst_bkpt_dbgexp_occur_vld (ifu_iu_inst_bkpt_dbgexp_occur_vld), .ifu_iu_spcu_retire_mask (ifu_iu_spcu_retire_mask ), .iu_ifu_kill_inst (iu_ifu_kill_inst ) ); cr_ifu_ifctrl x_ifctrl ( .cpuclk (forever_cpuclk_gated_ifu ), .cpurst_b (cpurst_b ), .had_ifu_ir_vld (had_ifu_ir_vld ), .ibuf_ifctrl_inst32_low (ibuf_ifctrl_inst32_low ), .ibuf_ifctrl_inst_vld (ibuf_ifctrl_inst_vld ), .ibuf_ifctrl_pop0_mad32_low (ibuf_ifctrl_pop0_mad32_low ), .ibuf_ifdp_inst_dbg_disable (ibuf_ifdp_inst_dbg_disable ), .ibuf_xx_empty (ibuf_xx_empty ), .ibusif_ifctrl_inst_mad32_high (ibusif_ifctrl_inst_mad32_high ), .ibusif_ifctrl_inst_no_bypass (ibusif_ifctrl_inst_no_bypass ), .ibusif_xx_16bit_inst (ibusif_xx_16bit_inst ), .ibusif_xx_trans_cmplt (ibusif_xx_trans_cmplt ), .ibusif_xx_unalign_fetch (ibusif_xx_unalign_fetch ), .ifctrl_ibuf_bypass_vld (ifctrl_ibuf_bypass_vld ), .ifctrl_ibuf_inst_pipe_down (ifctrl_ibuf_inst_pipe_down ), .ifctrl_ibuf_pop_en (ifctrl_ibuf_pop_en ), .ifctrl_xx_ifcancel (ifctrl_xx_ifcancel ), .ifu_iu_ex_inst_vld (ifu_iu_ex_inst_vld ), .ifu_iu_inst_buf_inst_dbg_disable (ifu_iu_inst_buf_inst_dbg_disable ), .ifu_iu_inst_buf_inst_vld (ifu_iu_inst_buf_inst_vld ), .iu_ifu_ex_stall (iu_ifu_ex_stall ), .iu_ifu_inst_fetch (iu_ifu_inst_fetch ), .iu_ifu_inst_fetch_without_dbg_disable (iu_ifu_inst_fetch_without_dbg_disable), .iu_ifu_wb_stall (iu_ifu_wb_stall ), .iu_yy_xx_dbgon (iu_yy_xx_dbgon ), .iu_yy_xx_flush (iu_yy_xx_flush ), .split_ifctrl_hs_stall (split_ifctrl_hs_stall ), .split_ifctrl_hs_stall_part (split_ifctrl_hs_stall_part ) ); cr_ifu_randclk x_randclk ( .randclk_ibuf_entry_data_mod_en_w16 (randclk_ibuf_entry_data_mod_en_w16), .randclk_ibuf_pop_mod_en_w3 (randclk_ibuf_pop_mod_en_w3 ), .randclk_ibuf_push_mod_en_w3 (randclk_ibuf_push_mod_en_w3 ) ); endmodule module cr_iu_alu( alu_mad_adder_of, alu_mad_adder_rst, alu_mad_rst_cout, alu_rbus_data, alu_rbus_data_vld, alu_rbus_req, branch_alu_adder_cmp, branch_alu_adder_sel, branch_alu_logic_nz, branch_alu_logic_sel, branch_alu_pc_sel, ctrl_alu_ex_sel, ctrl_alu_mad_oper_mux_en, ctrl_alu_oper_mux_en, ctrl_mad_ex_data_sel, decd_alu_dst_vld, decd_alu_func, decd_alu_rs2_imm_vld, decd_alu_sub_func, ifu_iu_ex_cnt, lsu_iu_alu_sel, lsu_iu_mad_buf, mad_alu_data_vld, mad_alu_div_rs2, mad_alu_div_shift, mad_alu_fst_add, mad_alu_imm_vld, mad_alu_rs1, mad_alu_rs1_cst_0, mad_alu_rs1_vld, mad_alu_rs2_cst_0, mad_alu_rst, mad_alu_rst_vld, oper_alu_rs1_reg, oper_alu_rs2_imm, oper_alu_rs2_reg, pcgen_xx_cur_pc ); input branch_alu_adder_cmp; input branch_alu_adder_sel; input branch_alu_logic_nz; input branch_alu_logic_sel; input branch_alu_pc_sel; input ctrl_alu_ex_sel; input ctrl_alu_mad_oper_mux_en; input ctrl_alu_oper_mux_en; input ctrl_mad_ex_data_sel; input decd_alu_dst_vld; input [2 :0] decd_alu_func; input decd_alu_rs2_imm_vld; input [3 :0] decd_alu_sub_func; input [4 :0] ifu_iu_ex_cnt; input lsu_iu_alu_sel; input [31:0] lsu_iu_mad_buf; input mad_alu_data_vld; input [31:0] mad_alu_div_rs2; input mad_alu_div_shift; input mad_alu_fst_add; input mad_alu_imm_vld; input [31:0] mad_alu_rs1; input mad_alu_rs1_cst_0; input mad_alu_rs1_vld; input mad_alu_rs2_cst_0; input [31:0] mad_alu_rst; input mad_alu_rst_vld; input [31:0] oper_alu_rs1_reg; input [31:0] oper_alu_rs2_imm; input [31:0] oper_alu_rs2_reg; input [30:0] pcgen_xx_cur_pc; output alu_mad_adder_of; output [31:0] alu_mad_adder_rst; output alu_mad_rst_cout; output [31:0] alu_rbus_data; output alu_rbus_data_vld; output alu_rbus_req; reg [31:0] alu_shifter_right_rst; wire [1 :0] alu_adder_c_sel; wire alu_adder_reverse; wire [31:0] alu_adder_rs1; wire [31:0] alu_adder_rs2; wire [31:0] alu_adder_rs2_pre_val; wire alu_adder_rst_cmp_signed_lt; wire alu_adder_rst_cmp_unsigned_lt; wire alu_adder_rst_cout; wire [31:0] alu_adder_rst_out; wire alu_adder_sel; wire [31:0] alu_adder_shared_rst_out; wire alu_dst_vld; wire [2 :0] alu_func; wire [31:0] alu_logic_rs1; wire [31:0] alu_logic_rs2; wire [31:0] alu_logic_rst_out; wire [31:0] alu_logic_rst_out_and; wire [31:0] alu_logic_rst_out_mov; wire [31:0] alu_logic_rst_out_or; wire [31:0] alu_logic_rst_out_xor; wire [3 :0] alu_logic_rst_sel; wire alu_logic_sel; wire alu_mad_adder_of; wire [31:0] alu_mad_adder_rst; wire alu_mad_rst_cout; wire [31:0] alu_mux_rs1; wire [31:0] alu_mux_rs2; wire [31:0] alu_prepare_rs1; wire alu_prepare_rs1_sel; wire [31:0] alu_prepare_rs2; wire alu_prepare_rs2_sel; wire [31:0] alu_rbus_data; wire alu_rbus_data_vld; wire alu_rbus_req; wire [31:0] alu_rs1; wire alu_rs1_pre_cst_0; wire [31:0] alu_rs2; wire alu_rs2_imm_sel; wire alu_rs2_pre_cst_0; wire alu_sel; wire alu_shared_adder_cout; wire [31:0] alu_shared_adder_rs1; wire [31:0] alu_shared_adder_rs2; wire [31:0] alu_shared_adder_rst; wire alu_shared_adder_srcc; wire alu_shifter_right_in; wire [31:0] alu_shifter_right_in_mask; wire [31:0] alu_shifter_rs1; wire [31:0] alu_shifter_rs1_pre; wire [31:0] alu_shifter_rs1_reverse; wire [4 :0] alu_shifter_rs2; wire [31:0] alu_shifter_rst_left_out; wire [31:0] alu_shifter_rst_out; wire [31:0] alu_shifter_rst_right_out; wire alu_shifter_rst_sel; wire alu_shifter_sel; wire alu_shifter_shift_dr; wire alu_shifter_shift_in; wire [3 :0] alu_sub_func; wire branch_alu_adder_cmp; wire branch_alu_adder_sel; wire branch_alu_logic_nz; wire branch_alu_logic_sel; wire branch_alu_pc_sel; wire ctrl_alu_ex_sel; wire ctrl_alu_mad_oper_mux_en; wire ctrl_alu_oper_mux_en; wire ctrl_mad_ex_data_sel; wire decd_alu_dst_vld; wire [2 :0] decd_alu_func; wire decd_alu_rs2_imm_vld; wire [3 :0] decd_alu_sub_func; wire [4 :0] ifu_iu_ex_cnt; wire logic_rs1_sel; wire lsu_iu_alu_sel; wire [31:0] lsu_iu_mad_buf; wire mad_alu_data_vld; wire [31:0] mad_alu_div_rs2; wire mad_alu_div_shift; wire mad_alu_fst_add; wire mad_alu_imm_vld; wire [31:0] mad_alu_rs1; wire mad_alu_rs1_cst_0; wire mad_alu_rs1_vld; wire mad_alu_rs2_cst_0; wire [31:0] mad_alu_rst; wire mad_alu_rst_vld; wire [31:0] oper_alu_rs1_reg; wire [31:0] oper_alu_rs2_imm; wire [31:0] oper_alu_rs2_reg; wire [30:0] pcgen_xx_cur_pc; assign alu_mux_rs1[31:0] = mad_alu_rs1_vld ? mad_alu_rs1[31:0] : branch_alu_pc_sel ?{pcgen_xx_cur_pc[30:0], 1'b0} : oper_alu_rs1_reg[31:0]; assign alu_rs2_imm_sel = decd_alu_rs2_imm_vld || mad_alu_imm_vld || lsu_iu_alu_sel || branch_alu_pc_sel; assign alu_mux_rs2[31:0] = alu_rs2_imm_sel ? mad_alu_imm_vld ? lsu_iu_mad_buf[31:0] : oper_alu_rs2_imm[31:0] : oper_alu_rs2_reg[31:0]; assign alu_prepare_rs1_sel = ctrl_alu_oper_mux_en || ctrl_alu_mad_oper_mux_en || mad_alu_rs1_cst_0 || branch_alu_adder_sel || lsu_iu_alu_sel || branch_alu_logic_sel; assign alu_prepare_rs2_sel = alu_prepare_rs1_sel || branch_alu_adder_sel || lsu_iu_alu_sel || branch_alu_logic_sel; assign alu_prepare_rs1[31:0] = {32{alu_prepare_rs1_sel}} & alu_mux_rs1[31:0]; assign alu_prepare_rs2[31:0] = {32{alu_prepare_rs2_sel}} & alu_mux_rs2[31:0]; assign alu_dst_vld = decd_alu_dst_vld; assign alu_rs1_pre_cst_0 = mad_alu_rs1_cst_0; assign alu_rs1[31:0] = {32{~alu_rs1_pre_cst_0}} & alu_prepare_rs1[31:0]; assign alu_rs2_pre_cst_0 = mad_alu_rs2_cst_0; assign alu_rs2[31:0] = {32{~alu_rs2_pre_cst_0}} & alu_prepare_rs2[31:0]; assign alu_func[2:0] = decd_alu_func[2:0]; assign alu_sub_func[3:0] = decd_alu_sub_func[3:0]; assign alu_sel = ctrl_alu_ex_sel; assign alu_adder_sel = ctrl_alu_oper_mux_en && alu_func[0] || ctrl_alu_mad_oper_mux_en || branch_alu_adder_sel || lsu_iu_alu_sel; assign alu_logic_sel = ctrl_alu_oper_mux_en && alu_func[1] || branch_alu_logic_nz; assign alu_shifter_sel = ctrl_alu_oper_mux_en && alu_func[2] || ctrl_alu_mad_oper_mux_en && mad_alu_div_shift; assign alu_shifter_rst_sel = ctrl_alu_oper_mux_en && alu_func[2]; assign alu_adder_c_sel[1:0] = {2{alu_adder_sel}} & alu_sub_func[2:1]; assign alu_adder_rs1[31:0] = {32{alu_adder_sel}} & alu_rs1[31:0]; assign alu_adder_rs2_pre_val[31:0] = {32{alu_adder_sel}} & (mad_alu_div_shift ? alu_shifter_rst_left_out[31:0]: alu_rs2[31:0]); assign alu_adder_reverse = !alu_sub_func[0] && !mad_alu_fst_add && !lsu_iu_alu_sel || branch_alu_adder_cmp; assign alu_adder_rs2[31:0] = alu_adder_reverse ? ~alu_adder_rs2_pre_val[31:0] : alu_adder_rs2_pre_val[31:0]; assign alu_shared_adder_rs1[31:0] = alu_adder_rs1[31:0]; assign alu_shared_adder_rs2[31:0] = alu_adder_rs2[31:0]; assign alu_shared_adder_srcc = alu_adder_reverse; assign {alu_shared_adder_cout,alu_shared_adder_rst[31:0]} = alu_shared_adder_rs1[31:0] + alu_shared_adder_rs2[31:0] + alu_shared_adder_srcc; assign alu_adder_rst_out[31:0] = alu_shared_adder_rst[31:0]; assign alu_adder_rst_cmp_unsigned_lt = !alu_shared_adder_cout; assign alu_adder_rst_cmp_signed_lt = (alu_adder_rs1[31] & alu_adder_rs2[31]) | ((alu_adder_rs1[31] ^ alu_adder_rs2[31]) & alu_adder_rst_out[31]); assign alu_adder_rst_cout = alu_adder_c_sel[0] && alu_adder_rst_cmp_unsigned_lt || alu_adder_c_sel[1] && alu_adder_rst_cmp_signed_lt; assign alu_logic_rst_sel[3:0] = {4{alu_logic_sel}} & alu_sub_func[3:0]; assign logic_rs1_sel = alu_logic_sel || branch_alu_logic_sel; assign alu_logic_rs1[31:0] = {32{logic_rs1_sel}} & alu_rs1[31:0]; assign alu_logic_rs2[31:0] = {32{alu_logic_sel}} & alu_rs2[31:0]; assign alu_logic_rst_out_mov[31:0] = alu_logic_rs2[31:0]; assign alu_logic_rst_out_and[31:0] = alu_logic_rs1[31:0] & alu_logic_rs2[31:0]; assign alu_logic_rst_out_or[31:0] = alu_logic_rs1[31:0] | alu_logic_rs2[31:0]; assign alu_logic_rst_out_xor[31:0] = alu_logic_rs1[31:0] ^ alu_logic_rs2[31:0]; assign alu_logic_rst_out[31:0] = {32{alu_logic_rst_sel[0]}} & alu_logic_rst_out_mov[31:0] | {32{alu_logic_rst_sel[1]}} & alu_logic_rst_out_and[31:0] | {32{alu_logic_rst_sel[2]}} & alu_logic_rst_out_or[31:0] | {32{alu_logic_rst_sel[3]}} & alu_logic_rst_out_xor[31:0]; assign alu_shifter_shift_dr = alu_shifter_sel && !alu_sub_func[1]; assign alu_shifter_shift_in = alu_shifter_sel && alu_sub_func[0]; assign alu_shifter_rs1_pre[31:0] = {32{alu_shifter_sel}} & (mad_alu_div_shift ? mad_alu_div_rs2[31:0] : alu_rs1[31:0]); assign alu_shifter_rs2[4:0] = {5{alu_shifter_sel}} & (mad_alu_div_shift ? (ifu_iu_ex_cnt[4:0]): alu_rs2[4:0]); assign alu_shifter_rs1_reverse[31:0] = {alu_shifter_rs1_pre[0], alu_shifter_rs1_pre[1], alu_shifter_rs1_pre[2], alu_shifter_rs1_pre[3], alu_shifter_rs1_pre[4], alu_shifter_rs1_pre[5], alu_shifter_rs1_pre[6], alu_shifter_rs1_pre[7], alu_shifter_rs1_pre[8], alu_shifter_rs1_pre[9], alu_shifter_rs1_pre[10], alu_shifter_rs1_pre[11], alu_shifter_rs1_pre[12], alu_shifter_rs1_pre[13], alu_shifter_rs1_pre[14], alu_shifter_rs1_pre[15], alu_shifter_rs1_pre[16], alu_shifter_rs1_pre[17], alu_shifter_rs1_pre[18], alu_shifter_rs1_pre[19], alu_shifter_rs1_pre[20], alu_shifter_rs1_pre[21], alu_shifter_rs1_pre[22], alu_shifter_rs1_pre[23], alu_shifter_rs1_pre[24], alu_shifter_rs1_pre[25], alu_shifter_rs1_pre[26], alu_shifter_rs1_pre[27], alu_shifter_rs1_pre[28], alu_shifter_rs1_pre[29], alu_shifter_rs1_pre[30], alu_shifter_rs1_pre[31] }; assign alu_shifter_rs1[31:0] = alu_shifter_shift_dr ? alu_shifter_rs1_pre[31:0] : alu_shifter_rs1_reverse[31:0]; assign alu_shifter_right_in = alu_shifter_shift_in & alu_shifter_rs1_pre[31]; assign alu_shifter_right_in_mask[31:0] = {32{alu_shifter_right_in}}; always @( alu_shifter_rs2[4:0] or alu_shifter_right_in_mask[30:0] or alu_shifter_rs1[31:0]) begin case(alu_shifter_rs2[4:0]) 5'b00000: alu_shifter_right_rst[31:0] = alu_shifter_rs1[31:0]; 5'b00001: alu_shifter_right_rst[31:0] = {alu_shifter_right_in_mask[0], alu_shifter_rs1[31:1]}; 5'b00010: alu_shifter_right_rst[31:0] = {alu_shifter_right_in_mask[1:0], alu_shifter_rs1[31:2]}; 5'b00011: alu_shifter_right_rst[31:0] = {alu_shifter_right_in_mask[2:0], alu_shifter_rs1[31:3]}; 5'b00100: alu_shifter_right_rst[31:0] = {alu_shifter_right_in_mask[3:0], alu_shifter_rs1[31:4]}; 5'b00101: alu_shifter_right_rst[31:0] = {alu_shifter_right_in_mask[4:0], alu_shifter_rs1[31:5]}; 5'b00110: alu_shifter_right_rst[31:0] = {alu_shifter_right_in_mask[5:0], alu_shifter_rs1[31:6]}; 5'b00111: alu_shifter_right_rst[31:0] = {alu_shifter_right_in_mask[6:0], alu_shifter_rs1[31:7]}; 5'b01000: alu_shifter_right_rst[31:0] = {alu_shifter_right_in_mask[7:0], alu_shifter_rs1[31:8]}; 5'b01001: alu_shifter_right_rst[31:0] = {alu_shifter_right_in_mask[8:0], alu_shifter_rs1[31:9]}; 5'b01010: alu_shifter_right_rst[31:0] = {alu_shifter_right_in_mask[9:0], alu_shifter_rs1[31:10]}; 5'b01011: alu_shifter_right_rst[31:0] = {alu_shifter_right_in_mask[10:0], alu_shifter_rs1[31:11]}; 5'b01100: alu_shifter_right_rst[31:0] = {alu_shifter_right_in_mask[11:0], alu_shifter_rs1[31:12]}; 5'b01101: alu_shifter_right_rst[31:0] = {alu_shifter_right_in_mask[12:0], alu_shifter_rs1[31:13]}; 5'b01110: alu_shifter_right_rst[31:0] = {alu_shifter_right_in_mask[13:0], alu_shifter_rs1[31:14]}; 5'b01111: alu_shifter_right_rst[31:0] = {alu_shifter_right_in_mask[14:0], alu_shifter_rs1[31:15]}; 5'b10000: alu_shifter_right_rst[31:0] = {alu_shifter_right_in_mask[15:0], alu_shifter_rs1[31:16]}; 5'b10001: alu_shifter_right_rst[31:0] = {alu_shifter_right_in_mask[16:0], alu_shifter_rs1[31:17]}; 5'b10010: alu_shifter_right_rst[31:0] = {alu_shifter_right_in_mask[17:0], alu_shifter_rs1[31:18]}; 5'b10011: alu_shifter_right_rst[31:0] = {alu_shifter_right_in_mask[18:0], alu_shifter_rs1[31:19]}; 5'b10100: alu_shifter_right_rst[31:0] = {alu_shifter_right_in_mask[19:0], alu_shifter_rs1[31:20]}; 5'b10101: alu_shifter_right_rst[31:0] = {alu_shifter_right_in_mask[20:0], alu_shifter_rs1[31:21]}; 5'b10110: alu_shifter_right_rst[31:0] = {alu_shifter_right_in_mask[21:0], alu_shifter_rs1[31:22]}; 5'b10111: alu_shifter_right_rst[31:0] = {alu_shifter_right_in_mask[22:0], alu_shifter_rs1[31:23]}; 5'b11000: alu_shifter_right_rst[31:0] = {alu_shifter_right_in_mask[23:0], alu_shifter_rs1[31:24]}; 5'b11001: alu_shifter_right_rst[31:0] = {alu_shifter_right_in_mask[24:0], alu_shifter_rs1[31:25]}; 5'b11010: alu_shifter_right_rst[31:0] = {alu_shifter_right_in_mask[25:0], alu_shifter_rs1[31:26]}; 5'b11011: alu_shifter_right_rst[31:0] = {alu_shifter_right_in_mask[26:0], alu_shifter_rs1[31:27]}; 5'b11100: alu_shifter_right_rst[31:0] = {alu_shifter_right_in_mask[27:0], alu_shifter_rs1[31:28]}; 5'b11101: alu_shifter_right_rst[31:0] = {alu_shifter_right_in_mask[28:0], alu_shifter_rs1[31:29]}; 5'b11110: alu_shifter_right_rst[31:0] = {alu_shifter_right_in_mask[29:0], alu_shifter_rs1[31:30]}; 5'b11111: alu_shifter_right_rst[31:0] = {alu_shifter_right_in_mask[30:0], alu_shifter_rs1[31]}; default: alu_shifter_right_rst[31:0] = 32'bx; endcase end assign alu_shifter_rst_right_out[31:0] = alu_shifter_right_rst[31:0]; assign alu_shifter_rst_left_out[31:0] = {alu_shifter_rst_right_out[0], alu_shifter_rst_right_out[1], alu_shifter_rst_right_out[2], alu_shifter_rst_right_out[3], alu_shifter_rst_right_out[4], alu_shifter_rst_right_out[5], alu_shifter_rst_right_out[6], alu_shifter_rst_right_out[7], alu_shifter_rst_right_out[8], alu_shifter_rst_right_out[9], alu_shifter_rst_right_out[10],alu_shifter_rst_right_out[11], alu_shifter_rst_right_out[12],alu_shifter_rst_right_out[13], alu_shifter_rst_right_out[14],alu_shifter_rst_right_out[15], alu_shifter_rst_right_out[16],alu_shifter_rst_right_out[17], alu_shifter_rst_right_out[18],alu_shifter_rst_right_out[19], alu_shifter_rst_right_out[20],alu_shifter_rst_right_out[21], alu_shifter_rst_right_out[22],alu_shifter_rst_right_out[23], alu_shifter_rst_right_out[24],alu_shifter_rst_right_out[25], alu_shifter_rst_right_out[26],alu_shifter_rst_right_out[27], alu_shifter_rst_right_out[28],alu_shifter_rst_right_out[29], alu_shifter_rst_right_out[30],alu_shifter_rst_right_out[31] }; assign alu_shifter_rst_out[31:0] = alu_shifter_shift_dr ? alu_shifter_rst_right_out[31:0] : alu_shifter_rst_left_out[31:0]; assign alu_adder_shared_rst_out[31:0] = mad_alu_rst_vld ? mad_alu_rst[31:0] : (alu_sub_func[2] || alu_sub_func[1]) ? {31'b0, alu_adder_rst_cout} : alu_adder_rst_out[31:0]; assign alu_mad_adder_rst[31:0] = alu_shared_adder_rst[31:0]; assign alu_mad_rst_cout = alu_adder_rst_cout; assign alu_mad_adder_of = alu_shared_adder_cout; assign alu_rbus_req = alu_sel; assign alu_rbus_data_vld = (ctrl_mad_ex_data_sel) ? mad_alu_data_vld : alu_dst_vld; assign alu_rbus_data[31:0] = {32{alu_adder_sel}} & alu_adder_shared_rst_out[31:0] | {32{alu_logic_sel}} & alu_logic_rst_out[31:0] | {32{alu_shifter_rst_sel}} & alu_shifter_rst_out[31:0]; endmodule module cr_iu_branch( branch_alu_adder_cmp, branch_alu_adder_sel, branch_alu_logic_nz, branch_alu_logic_sel, branch_alu_pc_sel, branch_ctrl_stall, branch_pcgen_add_pc, branch_pcgen_br_chgflw_vld, branch_pcgen_br_chgflw_vld_for_data, branch_pcgen_br_pc_chgflw_vld, branch_pcgen_branch_chgflw_vld_for_data, branch_pcgen_jmp_chgflw_vld_for_data, branch_pcgen_reg_pc, branch_rbus_data, branch_rbus_data_vld, branch_rbus_req, branch_wb_cmp, branch_wb_jmp_reg, ctrl_branch_ex_data_sel, ctrl_branch_ex_sel, decd_branch_auipc, decd_branch_beq, decd_branch_bge, decd_branch_bgeu, decd_branch_blt, decd_branch_bltu, decd_branch_bne, decd_branch_cbeqz, decd_branch_cbnez, decd_branch_cj, decd_branch_cjal, decd_branch_cjalr, decd_branch_cjr, decd_branch_jal, decd_branch_jalr, decd_xx_inst_32bit, iu_had_chgflw_dst_pc, iu_had_chgflw_vld, iu_lsu_cmp, iu_lsu_imm_sel, iu_lsu_pc, iu_lsu_pc_sel, iu_lsu_rs1_sel, lsu_iu_branch_cout, lsu_iu_branch_rst, oper_branch_rs1_reg, oper_branch_rs2_imm, oper_branch_rs2_reg, pcgen_xx_cur_pc, pcgen_xx_ibus_idle, retire_branch_stall, wb_branch_dep_ld, wb_ctrl_stall_without_hready ); input ctrl_branch_ex_data_sel; input ctrl_branch_ex_sel; input decd_branch_auipc; input decd_branch_beq; input decd_branch_bge; input decd_branch_bgeu; input decd_branch_blt; input decd_branch_bltu; input decd_branch_bne; input decd_branch_cbeqz; input decd_branch_cbnez; input decd_branch_cj; input decd_branch_cjal; input decd_branch_cjalr; input decd_branch_cjr; input decd_branch_jal; input decd_branch_jalr; input decd_xx_inst_32bit; input lsu_iu_branch_cout; input [31:0] lsu_iu_branch_rst; input [31:0] oper_branch_rs1_reg; input [31:0] oper_branch_rs2_imm; input [31:0] oper_branch_rs2_reg; input [30:0] pcgen_xx_cur_pc; input pcgen_xx_ibus_idle; input retire_branch_stall; input wb_branch_dep_ld; input wb_ctrl_stall_without_hready; output branch_alu_adder_cmp; output branch_alu_adder_sel; output branch_alu_logic_nz; output branch_alu_logic_sel; output branch_alu_pc_sel; output branch_ctrl_stall; output [30:0] branch_pcgen_add_pc; output branch_pcgen_br_chgflw_vld; output branch_pcgen_br_chgflw_vld_for_data; output branch_pcgen_br_pc_chgflw_vld; output branch_pcgen_branch_chgflw_vld_for_data; output branch_pcgen_jmp_chgflw_vld_for_data; output [30:0] branch_pcgen_reg_pc; output [31:0] branch_rbus_data; output branch_rbus_data_vld; output branch_rbus_req; output branch_wb_cmp; output branch_wb_jmp_reg; output [31:0] iu_had_chgflw_dst_pc; output iu_had_chgflw_vld; output iu_lsu_cmp; output iu_lsu_imm_sel; output [31:0] iu_lsu_pc; output iu_lsu_pc_sel; output iu_lsu_rs1_sel; wire [31:0] adder_pc; wire [31:0] adder_src0; wire [31:0] adder_src1; wire branch_alu_adder_cmp; wire branch_alu_adder_sel; wire branch_alu_logic_nz; wire branch_alu_logic_sel; wire branch_alu_pc_sel; wire branch_br; wire branch_br_chgflw; wire branch_br_cmp; wire branch_br_cmpu; wire branch_br_eql; wire branch_br_xor; wire branch_cmp_result; wire branch_ctrl_stall; wire branch_eql_result; wire [31:0] branch_imm; wire branch_jmp; wire branch_jmp_pc; wire branch_jmp_reg; wire branch_link; wire [30:0] branch_pcgen_add_pc; wire branch_pcgen_br_chgflw_vld; wire branch_pcgen_br_chgflw_vld_for_data; wire branch_pcgen_br_pc_chgflw_vld; wire branch_pcgen_branch_chgflw_vld_for_data; wire branch_pcgen_jmp_chgflw_vld_for_data; wire [30:0] branch_pcgen_reg_pc; wire [31:0] branch_rbus_data; wire branch_rbus_data_vld; wire branch_rbus_req; wire [31:0] branch_rs1; wire [31:0] branch_rs2; wire branch_stall; wire branch_taken; wire branch_wb_cmp; wire branch_wb_jmp_reg; wire cmp_signed_result; wire ctrl_branch_ex_data_sel; wire ctrl_branch_ex_sel; wire decd_branch_auipc; wire decd_branch_beq; wire decd_branch_bge; wire decd_branch_bgeu; wire decd_branch_blt; wire decd_branch_bltu; wire decd_branch_bne; wire decd_branch_cbeqz; wire decd_branch_cbnez; wire decd_branch_cj; wire decd_branch_cjal; wire decd_branch_cjalr; wire decd_branch_cjr; wire decd_branch_jal; wire decd_branch_jalr; wire decd_xx_inst_32bit; wire [31:0] inc_offset; wire inst_auipc; wire inst_beq; wire inst_bge; wire inst_bgeu; wire inst_blt; wire inst_bltu; wire inst_bne; wire inst_cbeqz; wire inst_cbnez; wire inst_cj; wire inst_cjal; wire inst_cjalr; wire inst_cjr; wire inst_jal; wire inst_jalr; wire [31:0] iu_had_chgflw_dst_pc; wire iu_had_chgflw_vld; wire iu_lsu_cmp; wire iu_lsu_imm_sel; wire [31:0] iu_lsu_pc; wire iu_lsu_pc_sel; wire iu_lsu_rs1_sel; wire lsu_iu_branch_cout; wire [31:0] lsu_iu_branch_rst; wire [31:0] oper_branch_rs1_reg; wire [31:0] oper_branch_rs2_imm; wire [31:0] oper_branch_rs2_reg; wire [30:0] pcgen_xx_cur_pc; wire pcgen_xx_ibus_idle; wire retire_branch_stall; wire [31:0] target_pc; wire wb_branch_dep_ld; wire wb_ctrl_stall_without_hready; assign inst_cj = decd_branch_cj; assign inst_cjal = decd_branch_cjal; assign inst_cjr = decd_branch_cjr; assign inst_cjalr = decd_branch_cjalr; assign inst_cbeqz = decd_branch_cbeqz; assign inst_cbnez = decd_branch_cbnez; assign inst_auipc = decd_branch_auipc; assign inst_jal = decd_branch_jal; assign inst_jalr = decd_branch_jalr; assign inst_beq = decd_branch_beq; assign inst_bne = decd_branch_bne; assign inst_blt = decd_branch_blt; assign inst_bge = decd_branch_bge; assign inst_bltu = decd_branch_bltu; assign inst_bgeu = decd_branch_bgeu; assign branch_jmp_pc = inst_cj || inst_cjal || inst_jal; assign branch_jmp_reg = inst_cjr || inst_cjalr || inst_jalr; assign branch_br_cmp = inst_blt || inst_bge; assign branch_br_cmpu = inst_bltu || inst_bgeu; assign branch_br_xor = inst_beq || inst_bne; assign branch_jmp = branch_jmp_pc || inst_jalr; assign branch_link = inst_cjal || inst_cjalr || inst_jal || inst_jalr; assign branch_rs1[31:0] = {32{ctrl_branch_ex_data_sel}} & oper_branch_rs1_reg[31:0]; assign branch_imm[31:0] = oper_branch_rs2_imm[31:0]; assign adder_src0[31:0] = {pcgen_xx_cur_pc[30:0], 1'b0}; assign adder_src1[31:0] = (ctrl_branch_ex_data_sel && branch_taken) ? branch_imm[31:0] : inc_offset[31:0]; assign inc_offset[31:0] = {29'b0, decd_xx_inst_32bit, !decd_xx_inst_32bit, 1'b0}; assign adder_pc[31:0] = adder_src0[31:0] + adder_src1[31:0]; assign branch_taken = (inst_beq || inst_cbeqz) && !branch_eql_result || (inst_bne || inst_cbnez) && branch_eql_result || (inst_bge || inst_bgeu) && !branch_cmp_result || (inst_blt || inst_bltu) && branch_cmp_result; assign branch_br_chgflw = (branch_taken || branch_jmp_pc || branch_jmp_reg) && !(wb_branch_dep_ld && branch_link); assign branch_stall = retire_branch_stall || wb_branch_dep_ld && branch_link || (branch_br_chgflw && !pcgen_xx_ibus_idle); assign branch_ctrl_stall = ctrl_branch_ex_data_sel && branch_stall; assign branch_rbus_req = ctrl_branch_ex_sel && !branch_stall; assign branch_rbus_data_vld = branch_link; assign branch_rbus_data[31:0] = {32{branch_link}} & {adder_pc[31:1], 1'b0} ; assign branch_br_eql = inst_beq || inst_bne || inst_cbeqz || inst_cbnez; assign branch_br = branch_br_cmp || branch_br_cmpu || branch_br_eql; assign branch_wb_cmp = ctrl_branch_ex_data_sel && branch_br; assign branch_wb_jmp_reg = ctrl_branch_ex_data_sel && branch_jmp_reg; assign branch_rs2[31:0] = {32{ctrl_branch_ex_data_sel}} & oper_branch_rs2_reg[31:0]; assign iu_lsu_cmp = ctrl_branch_ex_data_sel && (branch_br_cmp || branch_br_cmpu); assign iu_lsu_pc_sel = ctrl_branch_ex_data_sel && branch_jmp_pc; assign iu_lsu_rs1_sel = ctrl_branch_ex_data_sel && (branch_br_cmp || branch_br_cmpu || inst_jalr); assign iu_lsu_imm_sel = ctrl_branch_ex_data_sel && branch_jmp; assign iu_lsu_pc[31:0] = {pcgen_xx_cur_pc[30:0], 1'b0}; assign target_pc[31:0] = branch_jmp ? lsu_iu_branch_rst[31:0] : {adder_pc[31:1], 1'b0}; assign branch_eql_result = |( branch_rs1[31:0] ^ ({32{branch_br_xor}} & branch_rs2[31:0]) ); assign cmp_signed_result = (branch_rs1[31] & ~branch_rs2[31]) | ((branch_rs1[31] ^ ~branch_rs2[31]) & lsu_iu_branch_rst[31]); assign branch_cmp_result = branch_br_cmp ? cmp_signed_result : !lsu_iu_branch_cout; assign branch_alu_adder_sel = 1'b0; assign branch_alu_adder_cmp = 1'b0; assign branch_alu_pc_sel = inst_auipc; assign branch_alu_logic_sel = 1'b0; assign branch_alu_logic_nz = 1'b0; assign branch_pcgen_br_chgflw_vld = ctrl_branch_ex_data_sel && branch_br_chgflw && !wb_ctrl_stall_without_hready && pcgen_xx_ibus_idle; assign branch_pcgen_br_chgflw_vld_for_data = ctrl_branch_ex_data_sel && branch_br_chgflw && pcgen_xx_ibus_idle; assign branch_pcgen_br_pc_chgflw_vld = ctrl_branch_ex_sel && branch_br_chgflw && !branch_stall; assign branch_pcgen_branch_chgflw_vld_for_data = ctrl_branch_ex_data_sel && (branch_taken || branch_jmp); assign branch_pcgen_jmp_chgflw_vld_for_data = ctrl_branch_ex_data_sel && (inst_cjr || inst_cjalr); assign branch_pcgen_reg_pc[30:0] = branch_rs1[31:1]; assign branch_pcgen_add_pc[30:0] = target_pc[31:1]; assign iu_had_chgflw_vld = branch_pcgen_br_pc_chgflw_vld; assign iu_had_chgflw_dst_pc[31:0] = branch_jmp_reg ? {branch_pcgen_reg_pc[30:0], 1'b0} : {branch_pcgen_add_pc[30:0], 1'b0}; endmodule module cr_iu_ctrl( branch_ctrl_stall, cp0_iu_stall, cp0_yy_priv_mode, ctrl_alu_ex_data_sel, ctrl_alu_ex_sel, ctrl_alu_mad_oper_mux_en, ctrl_alu_oper_mux_en, ctrl_branch_ex_data_sel, ctrl_branch_ex_sel, ctrl_cp0_ex_data_sel, ctrl_lsu_ex_data_sel, ctrl_mad_ex_data_sel, ctrl_mad_ex_sel, ctrl_mad_oper_mux_en, ctrl_oper_lsu_data_sel, ctrl_retire_ni_vld, ctrl_special_ex_data_sel, ctrl_special_ex_sel, ctrl_special_expt_vec, ctrl_special_expt_vld, ctrl_xx_sp_adjust, decd_ctrl_alu_sel, decd_ctrl_branch_sel, decd_ctrl_cp0_sel, decd_ctrl_expt_bkpt, decd_ctrl_expt_ecall, decd_ctrl_expt_inv, decd_ctrl_expt_wsc, decd_ctrl_lsu_sel, decd_ctrl_mad_sel, decd_xx_unit_special_sel, hs_split_iu_ctrl_inst_vld, ifu_iu_ex_expt_vld, ifu_iu_ex_inst_vld, ifu_iu_ex_ni, ifu_iu_ex_prvlg_expt_vld, ifu_iu_ex_rand_vld, iu_cp0_ecall, iu_cp0_ex_data_sel, iu_cp0_ex_sel, iu_cp0_oper_mux_en, iu_hs_split_ex_stall, iu_ifu_ex_stall, iu_ifu_ex_stall_noinput, iu_ifu_ex_vld, iu_ifu_wb_stall, iu_lsu_ex_data_sel, iu_lsu_ex_sel, iu_lsu_oper_mux_en, lsu_iu_stall, lsu_iu_stall_noinput, mad_ctrl_stall, mad_ctrl_stall_noinput, pcgen_ctrl_stall, vector_ctrl_stall, wb_ctrl_stall ); input branch_ctrl_stall; input cp0_iu_stall; input [1:0] cp0_yy_priv_mode; input decd_ctrl_alu_sel; input decd_ctrl_branch_sel; input decd_ctrl_cp0_sel; input decd_ctrl_expt_bkpt; input decd_ctrl_expt_ecall; input decd_ctrl_expt_inv; input decd_ctrl_expt_wsc; input decd_ctrl_lsu_sel; input decd_ctrl_mad_sel; input decd_xx_unit_special_sel; input hs_split_iu_ctrl_inst_vld; input ifu_iu_ex_expt_vld; input ifu_iu_ex_inst_vld; input ifu_iu_ex_ni; input ifu_iu_ex_prvlg_expt_vld; input ifu_iu_ex_rand_vld; input lsu_iu_stall; input lsu_iu_stall_noinput; input mad_ctrl_stall; input mad_ctrl_stall_noinput; input pcgen_ctrl_stall; input vector_ctrl_stall; input wb_ctrl_stall; output ctrl_alu_ex_data_sel; output ctrl_alu_ex_sel; output ctrl_alu_mad_oper_mux_en; output ctrl_alu_oper_mux_en; output ctrl_branch_ex_data_sel; output ctrl_branch_ex_sel; output ctrl_cp0_ex_data_sel; output ctrl_lsu_ex_data_sel; output ctrl_mad_ex_data_sel; output ctrl_mad_ex_sel; output ctrl_mad_oper_mux_en; output ctrl_oper_lsu_data_sel; output ctrl_retire_ni_vld; output ctrl_special_ex_data_sel; output ctrl_special_ex_sel; output [4:0] ctrl_special_expt_vec; output ctrl_special_expt_vld; output ctrl_xx_sp_adjust; output iu_cp0_ecall; output iu_cp0_ex_data_sel; output iu_cp0_ex_sel; output iu_cp0_oper_mux_en; output iu_hs_split_ex_stall; output iu_ifu_ex_stall; output iu_ifu_ex_stall_noinput; output iu_ifu_ex_vld; output iu_ifu_wb_stall; output iu_lsu_ex_data_sel; output iu_lsu_ex_sel; output iu_lsu_oper_mux_en; reg [4:0] ctrl_special_expt_vec; wire bctm_ctrl_stall; wire branch_ctrl_stall; wire cp0_iu_stall; wire [1:0] cp0_yy_priv_mode; wire ctrl_alu_ex_data_sel; wire ctrl_alu_ex_sel; wire ctrl_alu_mad_oper_mux_en; wire ctrl_alu_oper_mux_en; wire ctrl_branch_ex_data_sel; wire ctrl_branch_ex_sel; wire ctrl_cp0_ex_data_sel; wire ctrl_ex_inst_vld; wire ctrl_internal_stall; wire ctrl_lsu_ex_data_sel; wire ctrl_mad_ex_data_sel; wire ctrl_mad_ex_sel; wire ctrl_mad_oper_mux_en; wire ctrl_oper_lsu_data_sel; wire ctrl_retire_ni_vld; wire ctrl_special_ex_data_sel; wire ctrl_special_ex_sel; wire ctrl_special_expt_vld; wire ctrl_xx_sp_adjust; wire decd_ctrl_alu_sel; wire decd_ctrl_branch_sel; wire decd_ctrl_cp0_sel; wire decd_ctrl_expt_bkpt; wire decd_ctrl_expt_ecall; wire decd_ctrl_expt_inv; wire decd_ctrl_expt_wsc; wire decd_ctrl_lsu_sel; wire decd_ctrl_mad_sel; wire decd_xx_unit_special_sel; wire hs_split_iu_ctrl_inst_vld; wire ifu_iu_ex_expt_vld; wire ifu_iu_ex_hs_split_expt_vld; wire ifu_iu_ex_hs_split_inst_vld; wire ifu_iu_ex_inst_vld; wire ifu_iu_ex_ni; wire ifu_iu_ex_prvlg_expt_vld; wire ifu_iu_ex_rand_vld; wire iu_cp0_ecall; wire iu_cp0_ex_data_sel; wire iu_cp0_ex_sel; wire iu_cp0_oper_mux_en; wire iu_hs_split_ex_stall; wire iu_ifu_ex_stall; wire iu_ifu_ex_stall_noinput; wire iu_ifu_ex_vld; wire iu_ifu_wb_stall; wire iu_lsu_ex_data_sel; wire iu_lsu_ex_sel; wire iu_lsu_oper_mux_en; wire lsu_iu_stall; wire lsu_iu_stall_noinput; wire mad_ctrl_stall; wire mad_ctrl_stall_noinput; wire pcgen_ctrl_stall; wire predec_lsu_sel; wire sec_ctrl_stall; wire vector_ctrl_stall; wire wb_ctrl_stall; assign ifu_iu_ex_hs_split_inst_vld = ifu_iu_ex_inst_vld || hs_split_iu_ctrl_inst_vld; assign ctrl_internal_stall = ifu_iu_ex_hs_split_inst_vld && wb_ctrl_stall; assign iu_ifu_wb_stall = ctrl_internal_stall; assign bctm_ctrl_stall = 1'b0; assign sec_ctrl_stall = 1'b0; assign iu_ifu_ex_stall = ctrl_internal_stall || branch_ctrl_stall || pcgen_ctrl_stall || vector_ctrl_stall || cp0_iu_stall || lsu_iu_stall || mad_ctrl_stall || bctm_ctrl_stall || sec_ctrl_stall; assign iu_hs_split_ex_stall = ctrl_internal_stall || lsu_iu_stall; assign iu_ifu_ex_vld = ifu_iu_ex_hs_split_inst_vld; assign iu_ifu_ex_stall_noinput = branch_ctrl_stall || pcgen_ctrl_stall || vector_ctrl_stall || cp0_iu_stall || lsu_iu_stall_noinput || mad_ctrl_stall_noinput || bctm_ctrl_stall || sec_ctrl_stall; assign ctrl_ex_inst_vld = ifu_iu_ex_hs_split_inst_vld && !ifu_iu_ex_rand_vld && !ctrl_internal_stall; assign predec_lsu_sel = decd_ctrl_lsu_sel; assign ctrl_alu_ex_sel = ctrl_ex_inst_vld && !decd_xx_unit_special_sel && decd_ctrl_alu_sel; assign ctrl_mad_ex_sel = ctrl_ex_inst_vld && !decd_xx_unit_special_sel && decd_ctrl_mad_sel; assign iu_lsu_ex_sel = ctrl_ex_inst_vld && !decd_xx_unit_special_sel && predec_lsu_sel; assign ctrl_special_ex_sel = ctrl_ex_inst_vld && decd_xx_unit_special_sel; assign iu_cp0_ex_sel = ctrl_ex_inst_vld && !decd_xx_unit_special_sel && decd_ctrl_cp0_sel; assign ctrl_branch_ex_sel = ctrl_ex_inst_vld && decd_ctrl_branch_sel; assign ctrl_alu_oper_mux_en = decd_ctrl_alu_sel || ifu_iu_ex_rand_vld; assign ctrl_mad_oper_mux_en = decd_ctrl_mad_sel; assign ctrl_alu_mad_oper_mux_en = decd_ctrl_mad_sel; assign iu_cp0_oper_mux_en = decd_ctrl_cp0_sel; assign iu_cp0_ecall = decd_ctrl_expt_ecall; assign iu_lsu_oper_mux_en = predec_lsu_sel; assign ctrl_alu_ex_data_sel = ifu_iu_ex_hs_split_inst_vld && !ifu_iu_ex_rand_vld && decd_ctrl_alu_sel; assign ctrl_mad_ex_data_sel = ifu_iu_ex_hs_split_inst_vld && !ifu_iu_ex_rand_vld && decd_ctrl_mad_sel; assign ctrl_lsu_ex_data_sel = ifu_iu_ex_hs_split_inst_vld && !ifu_iu_ex_rand_vld && predec_lsu_sel; assign ctrl_special_ex_data_sel = ifu_iu_ex_hs_split_inst_vld && !ifu_iu_ex_rand_vld && decd_xx_unit_special_sel; assign ctrl_cp0_ex_data_sel = ifu_iu_ex_hs_split_inst_vld && !ifu_iu_ex_rand_vld && decd_ctrl_cp0_sel; assign ctrl_branch_ex_data_sel = ifu_iu_ex_hs_split_inst_vld && !ifu_iu_ex_rand_vld && decd_ctrl_branch_sel; assign ctrl_oper_lsu_data_sel = ifu_iu_ex_hs_split_inst_vld && !ifu_iu_ex_rand_vld && predec_lsu_sel; assign iu_lsu_ex_data_sel = ifu_iu_ex_hs_split_inst_vld && !ifu_iu_ex_rand_vld && predec_lsu_sel && !decd_xx_unit_special_sel; assign iu_cp0_ex_data_sel = ifu_iu_ex_hs_split_inst_vld && !ifu_iu_ex_rand_vld && decd_ctrl_cp0_sel; assign ctrl_xx_sp_adjust = 1'b0; assign ctrl_retire_ni_vld = ifu_iu_ex_hs_split_inst_vld && ifu_iu_ex_ni; assign ifu_iu_ex_hs_split_expt_vld = ifu_iu_ex_expt_vld && !hs_split_iu_ctrl_inst_vld; assign ctrl_special_expt_vld = ifu_iu_ex_hs_split_expt_vld || ifu_iu_ex_prvlg_expt_vld || decd_ctrl_expt_inv || decd_ctrl_expt_bkpt || decd_ctrl_expt_ecall || decd_ctrl_expt_wsc; always @( cp0_yy_priv_mode[1:0] or decd_ctrl_expt_inv or decd_ctrl_expt_bkpt or ifu_iu_ex_hs_split_expt_vld or decd_ctrl_expt_ecall) begin if(ifu_iu_ex_hs_split_expt_vld) begin ctrl_special_expt_vec[4:0] = 5'b1; end else if(decd_ctrl_expt_inv ) begin ctrl_special_expt_vec[4:0] = 5'b10; end else if(decd_ctrl_expt_bkpt) begin ctrl_special_expt_vec[4:0] = 5'b11; end else if(decd_ctrl_expt_ecall) begin ctrl_special_expt_vec[4:0] = {5{(cp0_yy_priv_mode[1:0] == 2'b11)}} & 5'b1011 | {5{(cp0_yy_priv_mode[1:0] == 2'b00)}} & 5'b1000 | {5{(cp0_yy_priv_mode[1:0] == 2'b01)}} & 5'b1001; end else begin ctrl_special_expt_vec[4:0] = 5'b01010; end end endmodule module cr_iu_decd( branch_pcgen_add_pc, cp0_yy_priv_mode, decd_alu_dst_vld, decd_alu_func, decd_alu_rs2_imm_vld, decd_alu_sub_func, decd_branch_auipc, decd_branch_beq, decd_branch_bge, decd_branch_bgeu, decd_branch_blt, decd_branch_bltu, decd_branch_bne, decd_branch_cbeqz, decd_branch_cbnez, decd_branch_cj, decd_branch_cjal, decd_branch_cjalr, decd_branch_cjr, decd_branch_jal, decd_branch_jalr, decd_ctrl_alu_sel, decd_ctrl_branch_sel, decd_ctrl_cp0_sel, decd_ctrl_expt_bkpt, decd_ctrl_expt_ecall, decd_ctrl_expt_inv, decd_ctrl_expt_wsc, decd_ctrl_lsu_sel, decd_ctrl_mad_sel, decd_mad_inst_div, decd_mad_inst_divu, decd_mad_inst_mul, decd_mad_inst_mulh, decd_mad_inst_mulhsu, decd_mad_inst_mulhu, decd_mad_inst_rem, decd_mad_inst_remu, decd_oper_alu_imm, decd_oper_branch_imm, decd_oper_cp0_imm, decd_oper_lsu_imm, decd_retire_cp0_inst, decd_retire_inst_mret, decd_special_fencei, decd_wb_tval, decd_xx_inst_32bit, decd_xx_unit_special_sel, hs_split_iu_ctrl_inst_vld, hs_split_iu_dp_inst_op, ifu_had_chg_flw_inst, ifu_had_match_pc, ifu_iu_ex_expt_cur, ifu_iu_ex_expt_vld, ifu_iu_ex_inst, ifu_iu_ex_inst_bkpt, ifu_iu_ex_prvlg_expt_vld, ifu_iu_ex_rd_reg, ifu_iu_ex_rs1_reg, ifu_iu_ex_rs2_reg, iu_cp0_ex_csrrc, iu_cp0_ex_csrrci, iu_cp0_ex_csrrs, iu_cp0_ex_csrrsi, iu_cp0_ex_csrrw, iu_cp0_ex_csrrwi, iu_cp0_ex_func3, iu_cp0_ex_mret, iu_cp0_ex_rd_reg, iu_cp0_ex_rs1_reg, iu_cp0_ex_wfi, iu_ifu_lsu_inst, iu_lsu_ex_byte, iu_lsu_ex_half, iu_lsu_ex_store, iu_lsu_ex_uns, lsu_iu_wfd, pcgen_xx_cur_pc ); input [30:0] branch_pcgen_add_pc; input [1 :0] cp0_yy_priv_mode; input hs_split_iu_ctrl_inst_vld; input [31:0] hs_split_iu_dp_inst_op; input ifu_iu_ex_expt_cur; input ifu_iu_ex_expt_vld; input [31:0] ifu_iu_ex_inst; input ifu_iu_ex_inst_bkpt; input ifu_iu_ex_prvlg_expt_vld; input lsu_iu_wfd; input [30:0] pcgen_xx_cur_pc; output decd_alu_dst_vld; output [2 :0] decd_alu_func; output decd_alu_rs2_imm_vld; output [3 :0] decd_alu_sub_func; output decd_branch_auipc; output decd_branch_beq; output decd_branch_bge; output decd_branch_bgeu; output decd_branch_blt; output decd_branch_bltu; output decd_branch_bne; output decd_branch_cbeqz; output decd_branch_cbnez; output decd_branch_cj; output decd_branch_cjal; output decd_branch_cjalr; output decd_branch_cjr; output decd_branch_jal; output decd_branch_jalr; output decd_ctrl_alu_sel; output decd_ctrl_branch_sel; output decd_ctrl_cp0_sel; output decd_ctrl_expt_bkpt; output decd_ctrl_expt_ecall; output decd_ctrl_expt_inv; output decd_ctrl_expt_wsc; output decd_ctrl_lsu_sel; output decd_ctrl_mad_sel; output decd_mad_inst_div; output decd_mad_inst_divu; output decd_mad_inst_mul; output decd_mad_inst_mulh; output decd_mad_inst_mulhsu; output decd_mad_inst_mulhu; output decd_mad_inst_rem; output decd_mad_inst_remu; output [31:0] decd_oper_alu_imm; output [31:0] decd_oper_branch_imm; output [11:0] decd_oper_cp0_imm; output [31:0] decd_oper_lsu_imm; output decd_retire_cp0_inst; output decd_retire_inst_mret; output decd_special_fencei; output [31:0] decd_wb_tval; output decd_xx_inst_32bit; output decd_xx_unit_special_sel; output ifu_had_chg_flw_inst; output [31:0] ifu_had_match_pc; output [4 :0] ifu_iu_ex_rd_reg; output [4 :0] ifu_iu_ex_rs1_reg; output [4 :0] ifu_iu_ex_rs2_reg; output iu_cp0_ex_csrrc; output iu_cp0_ex_csrrci; output iu_cp0_ex_csrrs; output iu_cp0_ex_csrrsi; output iu_cp0_ex_csrrw; output iu_cp0_ex_csrrwi; output [2 :0] iu_cp0_ex_func3; output iu_cp0_ex_mret; output [4 :0] iu_cp0_ex_rd_reg; output [4 :0] iu_cp0_ex_rs1_reg; output iu_cp0_ex_wfi; output iu_ifu_lsu_inst; output iu_lsu_ex_byte; output iu_lsu_ex_half; output iu_lsu_ex_store; output iu_lsu_ex_uns; reg decd_dst_vld; reg [2 :0] decd_func; reg decd_ill_expt16; reg decd_ill_expt32; reg decd_rs2_imm_vld; reg [3 :0] decd_sub_func; reg [4 :0] rd_16; reg [4 :0] rs1_16; reg [4 :0] rs2_16; wire [31:0] alu_imm; wire auipc_imm_vld; wire [31:0] branch_imm; wire [30:0] branch_pcgen_add_pc; wire [31:0] btype_imm; wire btype_imm_vld; wire [31:0] cbtype_imm; wire cbtype_imm_vld; wire [31:0] ciatype_imm; wire ciatype_imm_vld; wire [31:0] ciltype_imm; wire ciltype_imm_vld; wire [31:0] cistype_imm; wire cistype_imm_vld; wire [31:0] citype_imm; wire citype_imm_vld; wire [31:0] ciwtype_imm; wire ciwtype_imm_vld; wire [31:0] cjtype_imm; wire cjtype_imm_vld; wire [31:0] cltype_imm; wire cltype_imm_vld; wire [1 :0] cp0_yy_priv_mode; wire [31:0] csstype_imm; wire csstype_imm_vld; wire decd_alu_dst_vld; wire [2 :0] decd_alu_func; wire decd_alu_rs2_imm_vld; wire decd_alu_sel; wire [3 :0] decd_alu_sub_func; wire decd_branch_auipc; wire decd_branch_beq; wire decd_branch_bge; wire decd_branch_bgeu; wire decd_branch_blt; wire decd_branch_bltu; wire decd_branch_bne; wire decd_branch_cbeqz; wire decd_branch_cbnez; wire decd_branch_cj; wire decd_branch_cjal; wire decd_branch_cjalr; wire decd_branch_cjr; wire decd_branch_inst; wire decd_branch_jal; wire decd_branch_jalr; wire decd_branch_sel; wire decd_ctrl_alu_sel; wire decd_ctrl_branch_sel; wire decd_ctrl_cp0_sel; wire decd_ctrl_expt_bkpt; wire decd_ctrl_expt_ecall; wire decd_ctrl_expt_inv; wire decd_ctrl_expt_wsc; wire decd_ctrl_lsu_sel; wire decd_ctrl_mad_sel; wire [2 :0] decd_func3; wire [1 :0] decd_func7; wire decd_ill_expt; wire decd_ill_reg_32; wire [31:0] decd_imm; wire [31:0] decd_inst; wire decd_inst_32bit; wire decd_inst_auipc; wire decd_inst_beq; wire decd_inst_bge; wire decd_inst_bgeu; wire decd_inst_bkpt; wire decd_inst_blt; wire decd_inst_bltu; wire decd_inst_bne; wire decd_inst_cbeqz; wire decd_inst_cbnez; wire decd_inst_cj; wire decd_inst_cjal; wire decd_inst_cjalr; wire decd_inst_cjr; wire decd_inst_clw; wire decd_inst_clwsp; wire decd_inst_csrrc; wire decd_inst_csrrci; wire decd_inst_csrrs; wire decd_inst_csrrsi; wire decd_inst_csrrw; wire decd_inst_csrrwi; wire decd_inst_csw; wire decd_inst_cswsp; wire decd_inst_ecall; wire decd_inst_expt; wire decd_inst_fence; wire decd_inst_fencei; wire decd_inst_jal; wire decd_inst_jalr; wire decd_inst_lb; wire decd_inst_lbu; wire decd_inst_lh; wire decd_inst_lhu; wire decd_inst_lw; wire decd_inst_mret; wire decd_inst_mret_nor; wire decd_inst_nop; wire decd_inst_sb; wire decd_inst_sh; wire decd_inst_sw; wire decd_inst_wfi; wire decd_lsu_byte; wire decd_lsu_half; wire decd_lsu_sel; wire decd_lsu_store; wire decd_lsu_uns; wire decd_mad_inst_div; wire decd_mad_inst_divu; wire decd_mad_inst_mul; wire decd_mad_inst_mulh; wire decd_mad_inst_mulhsu; wire decd_mad_inst_mulhu; wire decd_mad_inst_rem; wire decd_mad_inst_remu; wire decd_mad_sel; wire [6 :0] decd_op; wire [31:0] decd_oper_alu_imm; wire [31:0] decd_oper_branch_imm; wire [11:0] decd_oper_cp0_imm; wire [31:0] decd_oper_lsu_imm; wire [4 :0] decd_rd; wire decd_retire_cp0_inst; wire decd_retire_inst_mret; wire [4 :0] decd_rs1; wire [4 :0] decd_rs2; wire decd_special_fencei; wire decd_special_sel; wire decd_sys; wire [31:0] decd_wb_tval; wire decd_xx_inst_32bit; wire decd_xx_unit_special_sel; wire hs_split_iu_ctrl_inst_vld; wire [31:0] hs_split_iu_dp_inst_op; wire ifu_had_chg_flw_inst; wire [31:0] ifu_had_match_pc; wire ifu_iu_ex_expt_cur; wire ifu_iu_ex_expt_vld; wire ifu_iu_ex_hs_split_expt_vld; wire [31:0] ifu_iu_ex_inst; wire ifu_iu_ex_inst_bkpt; wire ifu_iu_ex_prvlg_expt_vld; wire [4 :0] ifu_iu_ex_rd_reg; wire [4 :0] ifu_iu_ex_rs1_reg; wire [4 :0] ifu_iu_ex_rs2_reg; wire [31:0] itype_imm; wire itype_imm_vld; wire iu_cp0_ex_csrrc; wire iu_cp0_ex_csrrci; wire iu_cp0_ex_csrrs; wire iu_cp0_ex_csrrsi; wire iu_cp0_ex_csrrw; wire iu_cp0_ex_csrrwi; wire [2 :0] iu_cp0_ex_func3; wire iu_cp0_ex_mret; wire [4 :0] iu_cp0_ex_rd_reg; wire [4 :0] iu_cp0_ex_rs1_reg; wire iu_cp0_ex_wfi; wire iu_ifu_lsu_inst; wire iu_lsu_ex_byte; wire iu_lsu_ex_half; wire iu_lsu_ex_store; wire iu_lsu_ex_uns; wire jalr_imm_vld; wire [31:0] jtype_imm; wire jtype_imm_vld; wire load_imm_vld; wire [31:0] lsu_imm; wire lsu_iu_wfd; wire [30:0] pcgen_xx_cur_pc; wire rd_update_32; wire rs1_update_32; wire rs2_update_32; wire [31:0] stype_imm; wire stype_imm_vld; wire [31:0] tval_pc; wire tval_sel_pc; wire [31:0] utype_imm; wire utype_imm_vld; parameter FUNC_WIDTH = 3; parameter SUB_FUNC_WIDTH = 4; parameter ADDER = 3'b001; parameter LOGIC = 3'b010; parameter SHIFT = 3'b100; parameter ADD = 4'b0001; parameter LTU = 4'b0010; parameter SLT = 4'b0100; parameter SUB = 4'b1000; parameter MOV = 4'b0001; parameter AND = 4'b0010; parameter OR = 4'b0100; parameter XOR = 4'b1000; parameter SRA = 4'bx001; parameter SLL = 4'bx010; parameter SRL = 4'bx100; assign decd_inst[31:0] = hs_split_iu_ctrl_inst_vld ? hs_split_iu_dp_inst_op[31:0] : ifu_iu_ex_inst[31:0]; assign decd_inst_32bit = decd_inst[1] && decd_inst[0]; assign decd_op[6:0] = {decd_inst[6:5], decd_inst_32bit ? decd_inst[4:2] : decd_inst[15:13], decd_inst[1:0]}; assign decd_func3[2:0] = decd_inst_32bit ? decd_inst[14:12] : decd_inst[12:10]; assign decd_func7[1:0] = {decd_inst[30], decd_inst[25]}; always @( decd_inst[15:13] or decd_inst[1:0] or decd_inst[11:7]) begin casez({decd_inst[15:13], decd_inst[1:0]}) 5'b01101, 5'b00000, 5'b?1010: rs1_16[4:0] = 5'b00010; 5'b?1000, 5'b11?01, 5'b10001: rs1_16[4:0] = {2'b01, decd_inst[9:7]}; 5'b00001, 5'b?0010: rs1_16[4:0] = decd_inst[11:7]; default: begin rs1_16[4:0] = {1'b0, decd_inst[10:7]}; end endcase end always @( decd_inst[15:13] or decd_inst[6:0]) begin casez({decd_inst[15:13], decd_inst[1:0]}) 5'b11010, 5'b10010: rs2_16[4:0] = decd_inst[6:2]; 5'b11000: rs2_16[4:0] = {2'b01, decd_inst[4:2]}; 5'b10001: rs2_16[4:0] = {2'b01, decd_inst[4:2]}; default: rs2_16[4:0] = {2'b01, decd_inst[4:2]}; endcase end always @( decd_inst[15:13] or decd_inst[11:0]) begin casez({decd_inst[15:13], decd_inst[1:0]}) 5'b01010, 5'b01001, 5'b01101, 5'b00001, 5'b00010: rd_16[4:0] = decd_inst[11:7]; 5'b10010: rd_16[4:0] = decd_inst[6:2] == 5'b0 ? 5'b1 : decd_inst[11:7]; 5'b00101: rd_16[4:0] = 5'b1; 5'b10001: rd_16[4:0] = {2'b01, decd_inst[9:7]}; 5'b01000, 5'b00000: rd_16[4:0] = {2'b01, decd_inst[4:2]}; default : rd_16[4:0] = {2'b01, decd_inst[9:7]}; endcase end assign decd_rs1[4:0] = decd_inst_32bit ? decd_inst[19:15] : rs1_16[4:0]; assign decd_rs2[4:0] = decd_inst_32bit ? decd_inst[24:20] : rs2_16[4:0]; assign decd_rd[4:0] = decd_inst_32bit ? decd_inst[11:7] : rd_16[4:0]; assign load_imm_vld = decd_inst[6:0] == 7'b0000011; assign itype_imm_vld = decd_inst[6:0] == 7'b0010011 || decd_inst[6:0] == 7'b1110011; assign jalr_imm_vld = decd_inst[6:0] == 7'b1100111; assign itype_imm[31:0] = {{21{decd_inst[31]}}, decd_inst[30:20]}; assign stype_imm_vld = decd_inst[6:0] == 7'b0100011; assign stype_imm[31:0] = {{21{decd_inst[31]}}, decd_inst[30:25], decd_inst[11:7]}; assign btype_imm_vld = decd_inst[6:0] == 7'b1100011; assign btype_imm[31:0] = {{20{decd_inst[31]}}, decd_inst[7], decd_inst[30:25], decd_inst[11:8], 1'b0}; assign utype_imm_vld = decd_inst[6:0] == 7'b0110111; assign auipc_imm_vld = decd_inst[6:0] == 7'b0010111; assign utype_imm[31:0] = {decd_inst[31:12], 12'b0}; assign jtype_imm_vld = decd_inst[6:0] == 7'b1101111; assign jtype_imm[31:0] = {{12{decd_inst[31]}}, decd_inst[19:12], decd_inst[20], decd_inst[30:21], 1'b0}; assign citype_imm_vld = {decd_inst[15:13], decd_inst[1:0]} == 5'b01001 || {decd_inst[15:13], decd_inst[1:0]} == 5'b00001 || {decd_inst[15:13], decd_inst[1:0]} == 5'b00010 || {decd_inst[15:13], decd_inst[1:0]} == 5'b10001 && decd_inst[11:10] != 2'b11; assign citype_imm[31:0] = {{27{decd_inst[12]}}, decd_inst[6:2]}; assign cistype_imm_vld = {decd_inst[15:13], decd_inst[1:0]} == 5'b01010; assign cistype_imm[31:0] = {24'b0, decd_inst[3:2], decd_inst[12], decd_inst[6:4], 2'b0}; assign ciltype_imm_vld = {decd_inst[15:13], decd_inst[1:0]} == 5'b01101 && decd_inst[10:7] != 4'b10; assign ciltype_imm[31:0] = {{15{decd_inst[12]}}, decd_inst[6:2], 12'b0}; assign ciatype_imm_vld = {decd_inst[15:13], decd_inst[1:0]} == 5'b01101 && decd_inst[10:7] == 4'b10; assign ciatype_imm[31:0] = {{23{decd_inst[12]}}, decd_inst[4:3], decd_inst[5], decd_inst[2], decd_inst[6], 4'b0}; assign ciwtype_imm_vld = !decd_inst_32bit && {decd_inst[15:13], decd_inst[1:0]} == 5'b00000; assign ciwtype_imm[31:0] = {22'b0, decd_inst[10:7], decd_inst[12:11], decd_inst[5], decd_inst[6], 2'b0}; assign cltype_imm_vld = {decd_inst[15:13], decd_inst[1:0]} == 5'b01000 || {decd_inst[15:13], decd_inst[1:0]} == 5'b11000; assign cltype_imm[31:0] = {25'b0, decd_inst[5], decd_inst[12:10], decd_inst[6], 2'b0}; assign csstype_imm_vld = {decd_inst[15:13], decd_inst[1:0]} == 5'b11010; assign csstype_imm[31:0] = {24'b0, decd_inst[8:7], decd_inst[12:9], 2'b0}; assign cbtype_imm_vld = {decd_inst[15:13], decd_inst[1:0]} == 5'b11001 || {decd_inst[15:13], decd_inst[1:0]} == 5'b11101; assign cbtype_imm[31:0] = {{24{decd_inst[12]}}, decd_inst[6:5], decd_inst[2], decd_inst[11:10], decd_inst[4:3], 1'b0}; assign cjtype_imm_vld = {decd_inst[14:13], decd_inst[1:0]} == 4'b0101; assign cjtype_imm[31:0] = {{21{decd_inst[12]}}, decd_inst[8], decd_inst[10:9], decd_inst[6], decd_inst[7], decd_inst[2], decd_inst[11], decd_inst[5:3], 1'b0}; assign decd_imm[31:0] = citype_imm[31:0]; assign alu_imm[31:0] = {32{ itype_imm_vld}} & itype_imm[31:0] | {32{ utype_imm_vld}} & utype_imm[31:0] | {32{ auipc_imm_vld}} & utype_imm[31:0] | {32{ citype_imm_vld}} & citype_imm[31:0] | {32{ciltype_imm_vld}} & ciltype_imm[31:0] | {32{ciatype_imm_vld}} & ciatype_imm[31:0] | {32{ciwtype_imm_vld}} & ciwtype_imm[31:0]; assign branch_imm[31:0] = {32{ btype_imm_vld}} & btype_imm[31:0] | {32{ cbtype_imm_vld}} & cbtype_imm[31:0]; assign lsu_imm[31:0] = {32{ load_imm_vld}} & itype_imm[31:0] | {32{ jalr_imm_vld}} & itype_imm[31:0] | {32{ jtype_imm_vld}} & jtype_imm[31:0] | {32{ cjtype_imm_vld}} & cjtype_imm[31:0] | {32{ stype_imm_vld}} & stype_imm[31:0] | {32{cistype_imm_vld}} & cistype_imm[31:0] | {32{ cltype_imm_vld}} & cltype_imm[31:0] | {32{csstype_imm_vld}} & csstype_imm[31:0]; assign decd_oper_alu_imm[31:0] = alu_imm[31:0]; assign decd_oper_lsu_imm[31:0] = lsu_imm[31:0]; assign decd_oper_cp0_imm[11:0] = itype_imm[11:0]; assign decd_oper_branch_imm[31:0] = branch_imm[31:0]; assign ifu_iu_ex_rs1_reg[4:0] = {1'b0,decd_rs1[3:0]}; assign ifu_iu_ex_rs2_reg[4:0] = {1'b0,decd_rs2[3:0]}; assign ifu_iu_ex_rd_reg[4:0] = {1'b0, decd_rd[3:0]}; assign iu_ifu_lsu_inst = (decd_inst_clwsp || decd_inst_cswsp || decd_inst_clw || decd_inst_csw || decd_op[6:0] == 7'b0000011 || decd_op[6:0] == 7'b0100011) && !lsu_iu_wfd; assign decd_xx_inst_32bit = decd_inst_32bit; always @( rs2_16[4] or ciatype_imm[9:4] or citype_imm[6:0] or decd_op[4:0] or decd_func3[2:0] or ciwtype_imm[9:2] or rs1_16[4] or rd_16[4:0] or ciltype_imm[17:12]) begin casez({decd_func3[2:0], decd_op[4:0]}) 8'b???01001: begin decd_ill_expt16 = rd_16[4:0] == 5'b0 || rd_16[4]; end 8'b???00001: decd_ill_expt16 = rd_16[4:0] != 5'b0 && citype_imm[6:0] == 6'b0 || rd_16[4:0] == 5'b0 && citype_imm[6:0] != 6'b0 || rd_16[4]; 8'b?0?10001: begin decd_ill_expt16 = citype_imm[5:0] == 6'b0; end 8'b???00000: begin decd_ill_expt16 = ciwtype_imm[9:2] == 8'b0; end 8'b???01010, 8'b???00010: begin decd_ill_expt16 = rd_16[4:0] == 5'b0 && citype_imm[5:0] == 6'b0 || rd_16[4]; end 8'b???01101: begin decd_ill_expt16 = rd_16[4:0] == 5'b0 || rd_16[4:0] != 5'b10 && ciltype_imm[17:12] == 6'b0 || rd_16[4:0] == 5'b10 && ciatype_imm[9:4] == 6'b0 || rd_16[4]; end 8'b???11010: decd_ill_expt16 = rs2_16[4]; 8'b???10010: decd_ill_expt16 = rs1_16[4]; 8'b???01000, 8'b???11000, 8'b???10101, 8'b???00101, 8'b???11001, 8'b???11101, 8'b?1010001, 8'b?1110001: begin decd_ill_expt16 = 1'b0; end default:begin decd_ill_expt16 = 1'b1; end endcase end always @( decd_inst[31:20] or decd_op[6:2] or cp0_yy_priv_mode[1:0] or decd_func3[2:0]) begin casez({decd_inst[31:25], decd_func3[2:0], decd_op[6:2]}) 15'b010000000001100, 15'b010000010101100, 15'b000000????01100, 15'b????????0?00000, 15'b???????01000000, 15'b000000000100100, 15'b0?0000010100100, 15'b????????1100100, 15'b?????????000100, 15'b???????00011001, 15'b?????????111100, 15'b????????1011100, 15'b???????00?01000, 15'b???????01001000, 15'b???????00?11000, 15'b???????1??11000, 15'b??????????01101, 15'b??????????00101, 15'b??????????11011, 15'b???????00?00011: begin decd_ill_expt32 = 1'b0; end 15'b000000000011100: begin decd_ill_expt32 = decd_inst[24:21] != 4'b0; end 15'b001100000011100: begin decd_ill_expt32 = decd_inst[24:20] != 5'b00010 || !(cp0_yy_priv_mode[1:0] == 2'b11); end 15'b000100000011100: begin decd_ill_expt32 = decd_inst[24:20] != 5'b00101 || !(cp0_yy_priv_mode[1:0] == 2'b11); end default: begin decd_ill_expt32 = 1'b1; end endcase end assign rs1_update_32 = decd_inst_32bit && !(decd_op[6:2] == 5'b11100 && decd_func3[2]) && decd_op[6:2] != 5'b01101 && decd_op[6:2] != 5'b00101 && decd_op[6:2] != 5'b11011; assign rs2_update_32 = decd_inst_32bit && ( decd_op[6:2] == 5'b01100 || decd_op[6:2] == 5'b01000 || decd_op[6:2] == 5'b11000 || decd_op[6:2] == 5'b11100 && decd_func3[2:0] == 3'b0); assign rd_update_32 = decd_inst_32bit && decd_op[6:2] != 5'b01000 && decd_op[6:2] != 5'b11000; assign decd_ill_reg_32 = rs1_update_32 && decd_rs1[4] || rs2_update_32 && decd_rs2[4] && !hs_split_iu_ctrl_inst_vld || rd_update_32 && decd_rd[4] && !hs_split_iu_ctrl_inst_vld; assign decd_ill_expt = decd_inst_32bit ? decd_ill_expt32 || decd_ill_reg_32 : decd_ill_expt16; always @( decd_op[6:0] or decd_rd[4:0] or decd_func3[2:0] or decd_func7[1:0]) begin decd_func[FUNC_WIDTH-1:0] = ADDER; decd_sub_func[SUB_FUNC_WIDTH-1:0] = ADD; decd_rs2_imm_vld = 1'b0; decd_dst_vld = 1'b1; casez({decd_func7[1:0], decd_func3[2:0], decd_op[6:0]}) 12'b???????00001: begin decd_func[FUNC_WIDTH-1:0] = ADDER; decd_sub_func[SUB_FUNC_WIDTH-1:0] = ADD; decd_rs2_imm_vld = 1'b1; decd_dst_vld = 1'b1; end 12'b???????01101: begin decd_func[FUNC_WIDTH-1:0] = decd_rd[4:0] == 5'h2 ? ADDER : LOGIC; decd_sub_func[SUB_FUNC_WIDTH-1:0] = ADD; decd_rs2_imm_vld = 1'b1; decd_dst_vld = 1'b1; end 12'b???????00000: begin decd_func[FUNC_WIDTH-1:0] = ADDER; decd_sub_func[SUB_FUNC_WIDTH-1:0] = ADD; decd_rs2_imm_vld = 1'b1; decd_dst_vld = 1'b1; end 12'b??1????10010: begin decd_func[FUNC_WIDTH-1:0] = ADDER; decd_sub_func[SUB_FUNC_WIDTH-1:0] = ADD; decd_rs2_imm_vld = 1'b0; decd_dst_vld = 1'b1; end 12'b??0110010001: begin decd_func[FUNC_WIDTH-1:0] = ADDER; decd_sub_func[SUB_FUNC_WIDTH-1:0] = SUB; decd_rs2_imm_vld = 1'b0; decd_dst_vld = 1'b1; end 12'b??0000010011: begin decd_func[FUNC_WIDTH-1:0] = ADDER; decd_sub_func[SUB_FUNC_WIDTH-1:0] = ADD; decd_rs2_imm_vld = 1'b1; decd_dst_vld = 1'b1; end 12'b??0100010011: begin decd_func[FUNC_WIDTH-1:0] = ADDER; decd_sub_func[SUB_FUNC_WIDTH-1:0] = SLT; decd_rs2_imm_vld = 1'b1; decd_dst_vld = 1'b1; end 12'b??0110010011: begin decd_func[FUNC_WIDTH-1:0] = ADDER; decd_sub_func[SUB_FUNC_WIDTH-1:0] = LTU; decd_rs2_imm_vld = 1'b1; decd_dst_vld = 1'b1; end 12'b000000110011: begin decd_func[FUNC_WIDTH-1:0] = ADDER; decd_sub_func[SUB_FUNC_WIDTH-1:0] = ADD; decd_rs2_imm_vld = 1'b0; decd_dst_vld = 1'b1; end 12'b010??0110011: begin decd_func[FUNC_WIDTH-1:0] = ADDER; decd_sub_func[SUB_FUNC_WIDTH-1:0] = ADD; decd_rs2_imm_vld = 1'b0; decd_dst_vld = 1'b0; end 12'b011??0110011: begin decd_func[FUNC_WIDTH-1:0] = ADDER; decd_sub_func[SUB_FUNC_WIDTH-1:0] = LTU; decd_rs2_imm_vld = 1'b0; decd_dst_vld = 1'b0; end 12'b1?0000110011: begin decd_func[FUNC_WIDTH-1:0] = ADDER; decd_sub_func[SUB_FUNC_WIDTH-1:0] = SUB; decd_rs2_imm_vld = 1'b0; decd_dst_vld = 1'b1; end 12'b?00100110011: begin decd_func[FUNC_WIDTH-1:0] = ADDER; decd_sub_func[SUB_FUNC_WIDTH-1:0] = SLT; decd_rs2_imm_vld = 1'b0; decd_dst_vld = 1'b1; end 12'b?00110110011: begin decd_func[FUNC_WIDTH-1:0] = ADDER; decd_sub_func[SUB_FUNC_WIDTH-1:0] = LTU; decd_rs2_imm_vld = 1'b0; decd_dst_vld = 1'b1; end 12'b??10?1100011: begin decd_func[FUNC_WIDTH-1:0] = ADDER; decd_sub_func[SUB_FUNC_WIDTH-1:0] = SLT; decd_rs2_imm_vld = 1'b0; decd_dst_vld = 1'b0; end 12'b??11?1100011: begin decd_func[FUNC_WIDTH-1:0] = ADDER; decd_sub_func[SUB_FUNC_WIDTH-1:0] = LTU; decd_rs2_imm_vld = 1'b0; decd_dst_vld = 1'b0; end 12'b?????0010111: begin decd_func[FUNC_WIDTH-1:0] = ADDER; decd_sub_func[SUB_FUNC_WIDTH-1:0] = ADD; decd_rs2_imm_vld = 1'b1; decd_dst_vld = 1'b1; end 12'b?????1100111: begin decd_func[FUNC_WIDTH-1:0] = ADDER; decd_sub_func[SUB_FUNC_WIDTH-1:0] = ADD; decd_rs2_imm_vld = 1'b1; decd_dst_vld = 1'b0; end 12'b???????01001: begin decd_func[FUNC_WIDTH-1:0] = LOGIC; decd_sub_func[SUB_FUNC_WIDTH-1:0] = MOV; decd_rs2_imm_vld = 1'b1; decd_dst_vld = 1'b1; end 12'b??0????10010: begin decd_func[FUNC_WIDTH-1:0] = LOGIC; decd_sub_func[SUB_FUNC_WIDTH-1:0] = MOV; decd_rs2_imm_vld = 1'b0; decd_dst_vld = 1'b1; end 12'b???10??10001: begin decd_func[FUNC_WIDTH-1:0] = LOGIC; decd_sub_func[SUB_FUNC_WIDTH-1:0] = AND; decd_rs2_imm_vld = 1'b1; decd_dst_vld = 1'b1; end 12'b???111110001: begin decd_func[FUNC_WIDTH-1:0] = LOGIC; decd_sub_func[SUB_FUNC_WIDTH-1:0] = AND; decd_rs2_imm_vld = 1'b0; decd_dst_vld = 1'b1; end 12'b???111010001: begin decd_func[FUNC_WIDTH-1:0] = LOGIC; decd_sub_func[SUB_FUNC_WIDTH-1:0] = OR; decd_rs2_imm_vld = 1'b0; decd_dst_vld = 1'b1; end 12'b???110110001: begin decd_func[FUNC_WIDTH-1:0] = LOGIC; decd_sub_func[SUB_FUNC_WIDTH-1:0] = XOR; decd_rs2_imm_vld = 1'b0; decd_dst_vld = 1'b1; end 12'b?????0110111: begin decd_func[FUNC_WIDTH-1:0] = LOGIC; decd_sub_func[SUB_FUNC_WIDTH-1:0] = MOV; decd_rs2_imm_vld = 1'b1; decd_dst_vld = 1'b1; end 12'b??1110010011: begin decd_func[FUNC_WIDTH-1:0] = LOGIC; decd_sub_func[SUB_FUNC_WIDTH-1:0] = AND; decd_rs2_imm_vld = 1'b1; decd_dst_vld = 1'b1; end 12'b??1100010011: begin decd_func[FUNC_WIDTH-1:0] = LOGIC; decd_sub_func[SUB_FUNC_WIDTH-1:0] = OR; decd_rs2_imm_vld = 1'b1; decd_dst_vld = 1'b1; end 12'b??1000010011: begin decd_func[FUNC_WIDTH-1:0] = LOGIC; decd_sub_func[SUB_FUNC_WIDTH-1:0] = XOR; decd_rs2_imm_vld = 1'b1; decd_dst_vld = 1'b1; end 12'b?01110110011: begin decd_func[FUNC_WIDTH-1:0] = LOGIC; decd_sub_func[SUB_FUNC_WIDTH-1:0] = AND; decd_rs2_imm_vld = 1'b0; decd_dst_vld = 1'b1; end 12'b?01100110011: begin decd_func[FUNC_WIDTH-1:0] = LOGIC; decd_sub_func[SUB_FUNC_WIDTH-1:0] = OR; decd_rs2_imm_vld = 1'b0; decd_dst_vld = 1'b1; end 12'b?01000110011: begin decd_func[FUNC_WIDTH-1:0] = LOGIC; decd_sub_func[SUB_FUNC_WIDTH-1:0] = XOR; decd_rs2_imm_vld = 1'b0; decd_dst_vld = 1'b1; end 12'b???????00010: begin decd_func[FUNC_WIDTH-1:0] = SHIFT; decd_sub_func[SUB_FUNC_WIDTH-1:0] = SLL; decd_rs2_imm_vld = 1'b1; decd_dst_vld = 1'b1; end 12'b???00??10001: begin decd_func[FUNC_WIDTH-1:0] = SHIFT; decd_sub_func[SUB_FUNC_WIDTH-1:0] = SRL; decd_rs2_imm_vld = 1'b1; decd_dst_vld = 1'b1; end 12'b???01??10001: begin decd_func[FUNC_WIDTH-1:0] = SHIFT; decd_sub_func[SUB_FUNC_WIDTH-1:0] = SRA; decd_rs2_imm_vld = 1'b1; decd_dst_vld = 1'b1; end 12'b??0010010011: begin decd_func[FUNC_WIDTH-1:0] = SHIFT; decd_sub_func[SUB_FUNC_WIDTH-1:0] = SLL; decd_rs2_imm_vld = 1'b1; decd_dst_vld = 1'b1; end 12'b0?1010010011: begin decd_func[FUNC_WIDTH-1:0] = SHIFT; decd_sub_func[SUB_FUNC_WIDTH-1:0] = SRL; decd_rs2_imm_vld = 1'b1; decd_dst_vld = 1'b1; end 12'b1?1010010011: begin decd_func[FUNC_WIDTH-1:0] = SHIFT; decd_sub_func[SUB_FUNC_WIDTH-1:0] = SRA; decd_rs2_imm_vld = 1'b1; decd_dst_vld = 1'b1; end 12'b?00010110011: begin decd_func[FUNC_WIDTH-1:0] = SHIFT; decd_sub_func[SUB_FUNC_WIDTH-1:0] = SLL; decd_rs2_imm_vld = 1'b0; decd_dst_vld = 1'b1; end 12'b001010110011: begin decd_func[FUNC_WIDTH-1:0] = SHIFT; decd_sub_func[SUB_FUNC_WIDTH-1:0] = SRL; decd_rs2_imm_vld = 1'b0; decd_dst_vld = 1'b1; end 12'b1?1010110011: begin decd_func[FUNC_WIDTH-1:0] = SHIFT; decd_sub_func[SUB_FUNC_WIDTH-1:0] = SRA; decd_rs2_imm_vld = 1'b0; decd_dst_vld = 1'b1; end endcase end assign decd_mad_sel = decd_op[6:0] == 7'b0110011 && decd_func7[0] && !decd_inst_expt; assign decd_mad_inst_mul = decd_mad_sel && decd_func3[2:0] == 3'b000; assign decd_mad_inst_mulh = decd_mad_sel && decd_func3[2:0] == 3'b001; assign decd_mad_inst_mulhsu = decd_mad_sel && decd_func3[2:0] == 3'b010; assign decd_mad_inst_mulhu = decd_mad_sel && decd_func3[2:0] == 3'b011; assign decd_mad_inst_div = decd_mad_sel && decd_func3[2:0] == 3'b100; assign decd_mad_inst_divu = decd_mad_sel && decd_func3[2:0] == 3'b101; assign decd_mad_inst_rem = decd_mad_sel && decd_func3[2:0] == 3'b110; assign decd_mad_inst_remu = decd_mad_sel && decd_func3[2:0] == 3'b111; assign decd_lsu_sel = (decd_inst_clwsp || decd_inst_cswsp || decd_inst_clw || decd_inst_csw || decd_inst_lb || decd_inst_lh || decd_inst_lbu || decd_inst_lhu || decd_inst_lw || decd_inst_sb || decd_inst_sh || decd_inst_sw || decd_inst_fence || decd_inst_fencei) && !decd_inst_expt; assign decd_inst_clwsp = decd_op[4:0] == 5'b01010; assign decd_inst_cswsp = decd_op[4:0] == 5'b11010; assign decd_inst_clw = decd_op[4:0] == 5'b01000; assign decd_inst_csw = decd_op[4:0] == 5'b11000; assign decd_inst_lb = decd_op[6:0] == 7'b0000011 && decd_func3[2:0] == 3'b000; assign decd_inst_lh = decd_op[6:0] == 7'b0000011 && decd_func3[2:0] == 3'b001; assign decd_inst_lw = decd_op[6:0] == 7'b0000011 && decd_func3[2:0] == 3'b010; assign decd_inst_lbu = decd_op[6:0] == 7'b0000011 && decd_func3[2:0] == 3'b100; assign decd_inst_lhu = decd_op[6:0] == 7'b0000011 && decd_func3[2:0] == 3'b101; assign decd_inst_sb = decd_op[6:0] == 7'b0100011 && decd_func3[2:0] == 3'b000; assign decd_inst_sh = decd_op[6:0] == 7'b0100011 && decd_func3[2:0] == 3'b001; assign decd_inst_sw = decd_op[6:0] == 7'b0100011 && decd_func3[2:0] == 3'b010; assign decd_lsu_store = decd_inst_cswsp || decd_inst_csw || decd_inst_sb || decd_inst_sh || decd_inst_sw; assign decd_lsu_byte = decd_inst_lb || decd_inst_lbu || decd_inst_sb; assign decd_lsu_half = decd_inst_lh || decd_inst_lhu || decd_inst_sh; assign decd_lsu_uns = decd_inst_lbu || decd_inst_lhu; assign decd_inst_fence = decd_op[6:0] == 7'b0001111 && !decd_func3[0]; assign decd_inst_fencei = decd_op[6:0] == 7'b0001111 && decd_func3[0]; assign decd_sys = decd_op[6:0] == 7'b1110011 && !decd_inst_expt; assign decd_inst_ecall = decd_sys && decd_func3[2:0] == 3'b000 && decd_rs2[1:0] == 2'b0; assign decd_inst_mret = decd_sys && decd_func3[2:0] == 3'b000 && decd_rs2[1]; assign decd_inst_mret_nor= decd_inst_mret && (cp0_yy_priv_mode[1:0] == 2'b11); assign decd_inst_wfi = decd_sys && decd_func3[2:0] == 3'b000 && decd_rs2[2]; assign decd_inst_csrrw = decd_sys && decd_func3[2:0] == 3'b001; assign decd_inst_csrrs = decd_sys && decd_func3[2:0] == 3'b010; assign decd_inst_csrrc = decd_sys && decd_func3[2:0] == 3'b011; assign decd_inst_csrrwi = decd_sys && decd_func3[2:0] == 3'b101; assign decd_inst_csrrsi = decd_sys && decd_func3[2:0] == 3'b110; assign decd_inst_csrrci = decd_sys && decd_func3[2:0] == 3'b111; assign decd_retire_inst_mret = 1'b0; assign decd_ctrl_expt_wsc = 1'b0; assign decd_branch_inst = decd_inst_cj || decd_inst_cjal || decd_inst_cjr || decd_inst_cjalr || decd_inst_cbeqz || decd_inst_cbnez || decd_inst_jal || decd_inst_jalr || decd_inst_beq || decd_inst_bne || decd_inst_blt || decd_inst_bge || decd_inst_bltu || decd_inst_bgeu; assign decd_branch_sel = decd_branch_inst && !decd_inst_expt; assign decd_inst_cj = decd_op[4:0] == 5'b10101; assign decd_inst_cjal = decd_op[4:0] == 5'b00101; assign decd_inst_cjr = decd_op[4:0] == 5'b10010 && !decd_func3[2] && decd_rs2[4:0] == 5'b0; assign decd_inst_cjalr = decd_op[4:0] == 5'b10010 && decd_func3[2] && decd_rs2[4:0] == 5'b0; assign decd_inst_cbeqz = decd_op[4:0] == 5'b11001; assign decd_inst_cbnez = decd_op[4:0] == 5'b11101; assign decd_inst_auipc = decd_op[6:0] == 7'b0010111; assign decd_inst_jal = decd_op[6:0] == 7'b1101111; assign decd_inst_jalr = decd_op[6:0] == 7'b1100111; assign decd_inst_beq = decd_op[6:0] == 7'b1100011 && decd_func3[2:0] == 3'b000; assign decd_inst_bne = decd_op[6:0] == 7'b1100011 && decd_func3[2:0] == 3'b001; assign decd_inst_blt = decd_op[6:0] == 7'b1100011 && decd_func3[2:0] == 3'b100; assign decd_inst_bge = decd_op[6:0] == 7'b1100011 && decd_func3[2:0] == 3'b101; assign decd_inst_bltu = decd_op[6:0] == 7'b1100011 && decd_func3[2:0] == 3'b110; assign decd_inst_bgeu = decd_op[6:0] == 7'b1100011 && decd_func3[2:0] == 3'b111; assign decd_inst_nop = decd_op[4:0] == 5'b1 && decd_rd[4:0] == 5'b0 && decd_imm[5:0] == 1'b0; assign decd_inst_bkpt = decd_inst[15:0] == 16'h9002 || decd_inst[31:0] == 32'h0010_0073 || (ifu_iu_ex_inst_bkpt && !hs_split_iu_ctrl_inst_vld); assign decd_inst_expt = decd_ill_expt || decd_inst_bkpt; assign decd_special_fencei = decd_inst_fencei; assign ifu_iu_ex_hs_split_expt_vld = ifu_iu_ex_expt_vld && !hs_split_iu_ctrl_inst_vld || decd_inst_bkpt; assign decd_special_sel = decd_ill_expt || ifu_iu_ex_hs_split_expt_vld || ifu_iu_ex_prvlg_expt_vld || decd_inst_ecall || decd_inst_nop || decd_inst_fence || decd_inst_fencei || decd_ctrl_expt_wsc; assign tval_sel_pc = (ifu_iu_ex_inst_bkpt || ifu_iu_ex_expt_vld) && !hs_split_iu_ctrl_inst_vld; assign tval_pc[31:0] = ifu_iu_ex_expt_cur ? {pcgen_xx_cur_pc[30:0], 1'b0}: {branch_pcgen_add_pc[30:1], 2'b0}; assign decd_wb_tval[31:0] = {32{tval_sel_pc}} & tval_pc[31:0] | {32{decd_ill_expt}} & decd_inst[31:0] & {{16{decd_inst_32bit}},16'hffff}; assign decd_retire_cp0_inst = decd_sys; assign decd_alu_sel = !(decd_mad_sel || decd_lsu_sel || decd_sys || decd_branch_sel || decd_special_sel); assign decd_alu_func[FUNC_WIDTH-1:0] = decd_func[FUNC_WIDTH-1:0]; assign decd_alu_sub_func[SUB_FUNC_WIDTH-1:0] = decd_sub_func[SUB_FUNC_WIDTH-1:0]; assign decd_alu_dst_vld = decd_dst_vld; assign decd_alu_rs2_imm_vld = decd_rs2_imm_vld; assign decd_branch_cj = decd_inst_cj; assign decd_branch_cjal = decd_inst_cjal; assign decd_branch_cjr = decd_inst_cjr; assign decd_branch_cjalr = decd_inst_cjalr; assign decd_branch_cbeqz = decd_inst_cbeqz; assign decd_branch_cbnez = decd_inst_cbnez; assign decd_branch_auipc = decd_inst_auipc; assign decd_branch_jal = decd_inst_jal; assign decd_branch_jalr = decd_inst_jalr; assign decd_branch_beq = decd_inst_beq; assign decd_branch_bne = decd_inst_bne; assign decd_branch_blt = decd_inst_blt; assign decd_branch_bge = decd_inst_bge; assign decd_branch_bltu = decd_inst_bltu; assign decd_branch_bgeu = decd_inst_bgeu; assign decd_xx_unit_special_sel = decd_special_sel; assign decd_ctrl_alu_sel = decd_alu_sel; assign decd_ctrl_branch_sel = decd_branch_sel; assign decd_ctrl_mad_sel = decd_mad_sel; assign decd_ctrl_lsu_sel = decd_lsu_sel; assign decd_ctrl_cp0_sel = decd_sys; assign decd_ctrl_expt_inv = decd_ill_expt; assign decd_ctrl_expt_bkpt = decd_inst_bkpt; assign decd_ctrl_expt_ecall = decd_inst_ecall; assign iu_lsu_ex_store = decd_lsu_store; assign iu_lsu_ex_byte = decd_lsu_byte; assign iu_lsu_ex_half = decd_lsu_half; assign iu_lsu_ex_uns = decd_lsu_uns; assign iu_cp0_ex_mret = decd_inst_mret_nor; assign iu_cp0_ex_wfi = decd_inst_wfi; assign iu_cp0_ex_csrrw = decd_inst_csrrw; assign iu_cp0_ex_csrrs = decd_inst_csrrs; assign iu_cp0_ex_csrrc = decd_inst_csrrc; assign iu_cp0_ex_csrrwi = decd_inst_csrrwi; assign iu_cp0_ex_csrrsi = decd_inst_csrrsi; assign iu_cp0_ex_csrrci = decd_inst_csrrci; assign iu_cp0_ex_rs1_reg[4:0] = decd_rs1[4:0]; assign iu_cp0_ex_rd_reg[4:0] = decd_rd[4:0]; assign iu_cp0_ex_func3[2:0] = decd_func3[2:0]; assign ifu_had_chg_flw_inst = decd_branch_inst; assign ifu_had_match_pc[31:0] = {pcgen_xx_cur_pc[30:0], 1'b0}; endmodule module cr_iu_gated_clk_reg( cp0_yy_clk_en, forever_cpuclk, pad_yy_gate_clk_en_b, pad_yy_test_mode, write_data, x_randclk_reg_mod_en_w32, x_reg_dout, x_write_en ); input cp0_yy_clk_en; input forever_cpuclk; input pad_yy_gate_clk_en_b; input pad_yy_test_mode; input [31:0] write_data; input x_randclk_reg_mod_en_w32; input x_write_en; output [31:0] x_reg_dout; reg [31:0] x_reg_dout; wire cp0_yy_clk_en; wire forever_cpuclk; wire pad_yy_gate_clk_en_b; wire pad_yy_test_mode; wire reg_clk_en; wire reg_cpuclk; wire [31:0] write_data; wire [31:0] write_in_data; wire write_in_en; wire x_randclk_reg_mod_en_w32; wire x_write_en; assign reg_clk_en = write_in_en; gated_clk_cell x_reg_gated_clk ( .clk_in (forever_cpuclk ), .clk_out (reg_cpuclk ), .external_en (1'b0 ), .global_en (cp0_yy_clk_en ), .local_en (reg_clk_en ), .module_en (x_randclk_reg_mod_en_w32), .pad_yy_gate_clk_en_b (pad_yy_gate_clk_en_b ), .pad_yy_test_mode (pad_yy_test_mode ) ); assign write_in_en = x_write_en; assign write_in_data[31:0] = write_data[31:0]; always @(posedge reg_cpuclk) begin if(write_in_en) x_reg_dout[31:0] <= write_in_data[31:0]; else x_reg_dout[31:0] <= x_reg_dout[31:0]; end endmodule module cr_iu_gated_clk_reg_timing( cp0_yy_clk_en, forever_cpuclk, pad_yy_gate_clk_en_b, pad_yy_test_mode, write_data, x_randclk_reg_mod_en_w32, x_reg_dout, x_write_en ); input cp0_yy_clk_en; input forever_cpuclk; input pad_yy_gate_clk_en_b; input pad_yy_test_mode; input [31:0] write_data; input x_randclk_reg_mod_en_w32; input x_write_en; output [31:0] x_reg_dout; reg [31:0] x_reg_dout; wire cp0_yy_clk_en; wire forever_cpuclk; wire pad_yy_gate_clk_en_b; wire pad_yy_test_mode; wire reg_clk_en; wire reg_cpuclk; wire [31:0] write_data; wire [31:0] write_in_data; wire write_in_en; wire x_randclk_reg_mod_en_w32; wire x_write_en; assign reg_clk_en = write_in_en; gated_clk_cell x_reg_gated_clk ( .clk_in (forever_cpuclk ), .clk_out (reg_cpuclk ), .external_en (1'b0 ), .global_en (cp0_yy_clk_en ), .local_en (reg_clk_en ), .module_en (x_randclk_reg_mod_en_w32), .pad_yy_gate_clk_en_b (pad_yy_gate_clk_en_b ), .pad_yy_test_mode (pad_yy_test_mode ) ); assign write_in_en = x_write_en; assign write_in_data[31:0] = write_data[31:0]; always @(posedge reg_cpuclk) begin if(write_in_en) x_reg_dout[31:0] <= write_in_data[31:0]; else x_reg_dout[31:0] <= x_reg_dout[31:0]; end endmodule module cr_iu_hs_split( hs_split_iu_ctrl_inst_vld, hs_split_iu_dp_inst_op, hs_split_iu_hs_retire_mask, hs_split_iu_hs_switch_se, hs_split_iu_nsinst_gpr_rst_b, hs_split_iu_unstack_chgflw, iu_hs_split_ex_stall, iu_ifu_spcu_int_en, split_ifctrl_hs_stall, split_ifctrl_hs_stall_part ); input iu_hs_split_ex_stall; input iu_ifu_spcu_int_en; output hs_split_iu_ctrl_inst_vld; output [31:0] hs_split_iu_dp_inst_op; output hs_split_iu_hs_retire_mask; output hs_split_iu_hs_switch_se; output hs_split_iu_nsinst_gpr_rst_b; output hs_split_iu_unstack_chgflw; output split_ifctrl_hs_stall; output split_ifctrl_hs_stall_part; wire hs_split_iu_ctrl_inst_vld; wire [31:0] hs_split_iu_dp_inst_op; wire hs_split_iu_hs_retire_mask; wire hs_split_iu_hs_switch_se; wire hs_split_iu_nsinst_gpr_rst_b; wire hs_split_iu_unstack_chgflw; wire split_ifctrl_hs_stall; wire split_ifctrl_hs_stall_part; assign hs_split_iu_nsinst_gpr_rst_b = 1'b1; assign hs_split_iu_hs_retire_mask = 1'b0; assign hs_split_iu_unstack_chgflw = 1'b0; assign hs_split_iu_hs_switch_se = 1'b0; assign split_ifctrl_hs_stall_part = 1'b0; assign split_ifctrl_hs_stall = 1'b0; assign hs_split_iu_ctrl_inst_vld = 1'b0; assign hs_split_iu_dp_inst_op[31:0] = 32'b0; endmodule module cr_iu_mad( alu_mad_adder_of, alu_mad_adder_rst, alu_mad_rst_cout, cp0_yy_clk_en, cpurst_b, ctrl_mad_ex_data_sel, ctrl_mad_ex_sel, ctrl_mad_oper_mux_en, decd_mad_inst_div, decd_mad_inst_divu, decd_mad_inst_mul, decd_mad_inst_mulh, decd_mad_inst_mulhsu, decd_mad_inst_mulhu, decd_mad_inst_rem, decd_mad_inst_remu, forever_cpuclk, ifu_iu_ex_cnt, ifu_iu_ex_split_on, iu_lsu_imm_data, iu_lsu_imm_write_en, iu_yy_xx_flush, lsu_iu_mad_buf, mad_alu_data_vld, mad_alu_div_rs2, mad_alu_div_shift, mad_alu_fst_add, mad_alu_imm_vld, mad_alu_rs1, mad_alu_rs1_cst_0, mad_alu_rs1_vld, mad_alu_rs2_cst_0, mad_alu_rst, mad_alu_rst_vld, mad_ctrl_stall, mad_ctrl_stall_noinput, mad_rbus_req, oper_mad_rs1, oper_mad_rs2, pad_yy_gate_clk_en_b, pad_yy_test_mode, randclk_mad_mod_en_w2, retire_mad_ex_cancel, wb_ctrl_stall ); input alu_mad_adder_of; input [31:0 ] alu_mad_adder_rst; input alu_mad_rst_cout; input cp0_yy_clk_en; input cpurst_b; input ctrl_mad_ex_data_sel; input ctrl_mad_ex_sel; input ctrl_mad_oper_mux_en; input decd_mad_inst_div; input decd_mad_inst_divu; input decd_mad_inst_mul; input decd_mad_inst_mulh; input decd_mad_inst_mulhsu; input decd_mad_inst_mulhu; input decd_mad_inst_rem; input decd_mad_inst_remu; input forever_cpuclk; input iu_yy_xx_flush; input [31:0 ] lsu_iu_mad_buf; input [31:0 ] oper_mad_rs1; input [31:0 ] oper_mad_rs2; input pad_yy_gate_clk_en_b; input pad_yy_test_mode; input randclk_mad_mod_en_w2; input retire_mad_ex_cancel; input wb_ctrl_stall; output [4 :0 ] ifu_iu_ex_cnt; output ifu_iu_ex_split_on; output [31:0 ] iu_lsu_imm_data; output iu_lsu_imm_write_en; output mad_alu_data_vld; output [31:0 ] mad_alu_div_rs2; output mad_alu_div_shift; output mad_alu_fst_add; output mad_alu_imm_vld; output [31:0 ] mad_alu_rs1; output mad_alu_rs1_cst_0; output mad_alu_rs1_vld; output mad_alu_rs2_cst_0; output [31:0 ] mad_alu_rst; output mad_alu_rst_vld; output mad_ctrl_stall; output mad_ctrl_stall_noinput; output mad_rbus_req; reg [2 :0 ] cur_st; reg [31:0 ] mad_internal; reg mad_neg; reg mad_rs1_cst_0; reg [2 :0 ] nxt_st; reg [4 :0 ] rst_ff1; reg [4 :0 ] split_cnt; wire alu_mad_adder_of; wire [31:0 ] alu_mad_adder_rst; wire alu_mad_rst_cout; wire cnt_en; wire cp0_yy_clk_en; wire cpurst_b; wire ctrl_mad_ex_data_sel; wire ctrl_mad_ex_sel; wire ctrl_mad_oper_mux_en; wire decd_mad_inst_div; wire decd_mad_inst_divu; wire decd_mad_inst_mul; wire decd_mad_inst_mulh; wire decd_mad_inst_mulhsu; wire decd_mad_inst_mulhu; wire decd_mad_inst_rem; wire decd_mad_inst_remu; wire [4 :0 ] div_cnt; wire [31:0 ] div_ifu_imm; wire [31:0 ] div_ifu_imm_pre; wire div_neg; wire [31:0 ] div_quotient; wire [31:0 ] div_remainder; wire div_rs2_shift; wire [31:0 ] div_rst; wire div_rst_neg; wire [31:0 ] div_rst_rev; wire [31:0 ] div_rst_sel; wire div_single_quotient; wire div_unsigned; wire div_vld; wire div_zero; wire [4 :0 ] ff1_disp; wire forever_cpuclk; wire [4 :0 ] ifu_iu_ex_cnt; wire ifu_iu_ex_split_on; wire ifu_iu_mad_idle; wire ifu_iu_mad_pair; wire ifu_iu_mad_split; wire ifu_iu_mad_wfi2; wire ifu_iu_mult_sign; wire [4 :0 ] iu_ifu_cnt; wire iu_ifu_cnt_write_en; wire iu_ifu_ex_stall; wire iu_ifu_mad_cmplt; wire [31:0 ] iu_lsu_imm_data; wire iu_lsu_imm_write_en; wire iu_yy_xx_flush; wire [31:0 ] lsu_iu_mad_buf; wire mad_alu_data_vld; wire [31:0 ] mad_alu_div_rs2; wire mad_alu_div_shift; wire mad_alu_fst_add; wire mad_alu_imm_vld; wire [31:0 ] mad_alu_rs1; wire mad_alu_rs1_cst_0; wire mad_alu_rs1_vld; wire mad_alu_rs2_cst_0; wire [31:0 ] mad_alu_rst; wire mad_alu_rst_vld; wire mad_clk; wire mad_clk_en; wire mad_cmplt; wire [4 :0 ] mad_cnt; wire mad_ctrl_stall; wire mad_ctrl_stall_noinput; wire [31:0 ] mad_ff1_src; wire mad_pair; wire mad_pair_mult_sign; wire mad_pair_vld; wire mad_rbus_req; wire [31:0 ] mad_rs1; wire [31:0 ] mad_rs1_abs; wire mad_rs1_abs_sel; wire [31:0 ] mad_rs1_fin; wire [31:0 ] mad_rs2; wire [31:0 ] mad_rs2_abs; wire mad_rs2_abs_sel; wire [31:00] mad_rs2_fin; wire mad_vld_no_cancel; wire mls_cmplt; wire mls_vld_no_cancel; wire mulh_vld; wire mult_add_one; wire mult_fst_vld; wire [31:0 ] mult_high_data; wire [31:0 ] mult_high_rst; wire [31:0 ] mult_ifu_imm; wire [31:0 ] mult_low_rst; wire mult_neg; wire [31:0 ] mult_reverse; wire [31:0 ] mult_rst; wire [31:0 ] mult_rst_fin; wire [31:0 ] mult_rst_pre; wire mult_vld; wire mult_zero; wire [31:0 ] oper_mad_rs1; wire [31:0 ] oper_mad_rs2; wire pad_yy_gate_clk_en_b; wire pad_yy_test_mode; wire quot_zero; wire randclk_mad_mod_en_w2; wire rem_vld; wire retire_mad_ex_cancel; wire rs1_eqlz; wire [4 :0 ] rs1_ff1_rst; wire rs2_eqlz; wire [4 :0 ] rs2_ff1_rst; wire sm_upd_clk; wire sm_upd_en; wire [4 :0 ] split_cnt_dec; wire split_cnt_en; wire [4 :0 ] split_cnt_inc; wire split_cnt_offset; wire split_cnt_rst; wire split_cnt_upd_clk; wire split_cnt_upd_en; wire split_cnt_write_en; wire split_last; wire split_last_noinput; wire split_mad_cmplt; wire split_on; wire split_xx_stall; wire wb_ctrl_stall; assign mad_rs1_abs_sel = !(decd_mad_inst_mulhu || div_unsigned) && mad_rs1[31]; assign mad_cnt[4:0] = {5{ctrl_mad_oper_mux_en}} & split_cnt[4:0]; always @( mad_rs2_fin[01:00] or mad_rs2_fin[20:16] or mad_cnt[4:0] or mad_rs2_fin[31:21] or mad_rs2_fin[12:00] or mad_rs2_fin[16:09]) begin case(mad_cnt[4:0]) 5'd31 : mad_rs1_cst_0 = mad_rs2_fin[31]; 5'd30 : mad_rs1_cst_0 = mad_rs2_fin[30]; 5'd29 : mad_rs1_cst_0 = mad_rs2_fin[29]; 5'd28 : mad_rs1_cst_0 = mad_rs2_fin[28]; 5'd27 : mad_rs1_cst_0 = mad_rs2_fin[27]; 5'd26 : mad_rs1_cst_0 = mad_rs2_fin[26]; 5'd25 : mad_rs1_cst_0 = mad_rs2_fin[25]; 5'd24 : mad_rs1_cst_0 = mad_rs2_fin[24]; 5'd23 : mad_rs1_cst_0 = mad_rs2_fin[23]; 5'd22 : mad_rs1_cst_0 = mad_rs2_fin[22]; 5'd21 : mad_rs1_cst_0 = mad_rs2_fin[21]; 5'd20 : mad_rs1_cst_0 = mad_rs2_fin[20]; 5'd19 : mad_rs1_cst_0 = mad_rs2_fin[19]; 5'd18 : mad_rs1_cst_0 = mad_rs2_fin[18]; 5'd17 : mad_rs1_cst_0 = mad_rs2_fin[17]; 5'd16 : mad_rs1_cst_0 = mad_rs2_fin[16]; 5'd15 : mad_rs1_cst_0 = mad_rs2_fin[15]; 5'd14 : mad_rs1_cst_0 = mad_rs2_fin[14]; 5'd13 : mad_rs1_cst_0 = mad_rs2_fin[13]; 5'd12 : mad_rs1_cst_0 = mad_rs2_fin[12]; 5'd11 : mad_rs1_cst_0 = mad_rs2_fin[11]; 5'd10 : mad_rs1_cst_0 = mad_rs2_fin[10]; 5'd9 : mad_rs1_cst_0 = mad_rs2_fin[09]; 5'd8 : mad_rs1_cst_0 = mad_rs2_fin[08]; 5'd7 : mad_rs1_cst_0 = mad_rs2_fin[07]; 5'd6 : mad_rs1_cst_0 = mad_rs2_fin[06]; 5'd5 : mad_rs1_cst_0 = mad_rs2_fin[05]; 5'd4 : mad_rs1_cst_0 = mad_rs2_fin[04]; 5'd3 : mad_rs1_cst_0 = mad_rs2_fin[03]; 5'd2 : mad_rs1_cst_0 = mad_rs2_fin[02]; 5'd1 : mad_rs1_cst_0 = mad_rs2_fin[01]; 5'd0 : mad_rs1_cst_0 = mad_rs2_fin[00]; default:mad_rs1_cst_0 = 1'bx; endcase end assign mult_fst_vld = ifu_iu_mad_wfi2; assign mad_alu_rs2_cst_0 = ctrl_mad_ex_data_sel && mult_fst_vld && mult_vld; assign mad_alu_rs1_cst_0 = ctrl_mad_ex_data_sel && mult_vld && (!mad_rs1_cst_0 || mult_fst_vld); assign mad_alu_imm_vld = ctrl_mad_ex_data_sel && mult_vld && !mult_fst_vld; assign mult_low_rst[31:0] = mad_pair ? lsu_iu_mad_buf[31:0] : (mult_vld && rst_ff1[4:0] == 5'b0) ? mad_rs1_fin[31:0] : alu_mad_adder_rst[31:0]; assign mult_high_rst[31:0] = rst_ff1[4:0] == 5'b0 ? 32'b0 : (mad_internal[31:0] + alu_mad_adder_of); assign mult_high_data[31:0] = {mult_high_rst[30:0], alu_mad_adder_rst[31]}; assign mult_ifu_imm[31:0] = (mult_fst_vld && mult_vld && rst_ff1[4:0] == 5'b0) ? mad_rs1_fin[31:0] : split_on ? {alu_mad_adder_rst[30:0], 1'b0} : alu_mad_adder_rst[31:0]; assign mult_zero = rs1_eqlz || rs2_eqlz; assign mult_neg = mad_pair ? mad_neg : (decd_mad_inst_mulh || decd_mad_inst_mul) && (mad_rs1[31] ^ mad_rs2[31]) || decd_mad_inst_mulhsu && mad_rs1[31]; assign mult_rst_pre[31:0] = mulh_vld ? mult_high_rst[31:0] : mult_low_rst[31:0]; assign mult_reverse[31:0] = {32{mult_neg}} ^ mult_rst_pre[31:0]; assign mult_add_one = mulh_vld ? mult_neg && alu_mad_adder_rst[31:0] == 32'b0 : mult_neg; assign mult_rst_fin[31:0] = mult_reverse[31:0] + mult_add_one; assign mult_rst[31:0] = {32{!mult_zero}} & mult_rst_fin[31:0]; assign iu_lsu_imm_write_en = ctrl_mad_ex_sel && (split_on || mulh_vld) && !ifu_iu_mad_pair; assign mad_clk_en = ctrl_mad_ex_sel; gated_clk_cell x_mad_gated_clk ( .clk_in (forever_cpuclk ), .clk_out (mad_clk ), .external_en (1'b0 ), .global_en (cp0_yy_clk_en ), .local_en (mad_clk_en ), .module_en (randclk_mad_mod_en_w2), .pad_yy_gate_clk_en_b (pad_yy_gate_clk_en_b ), .pad_yy_test_mode (pad_yy_test_mode ) ); parameter IDLE = 3'b000, WFI1 = 3'b001, SPLIT = 3'b010, WFI2 = 3'b011, PAIR = 3'b110, PAIRS = 3'b111; assign mad_rs1[31:0] = {32{ctrl_mad_oper_mux_en}} & oper_mad_rs1[31:0]; assign mad_rs2[31:0] = {32{ctrl_mad_oper_mux_en}} & oper_mad_rs2[31:0]; assign mult_vld = decd_mad_inst_mul || decd_mad_inst_mulhu || decd_mad_inst_mulh || decd_mad_inst_mulhsu; assign div_vld = decd_mad_inst_div || decd_mad_inst_divu || decd_mad_inst_rem || decd_mad_inst_remu; assign div_unsigned = decd_mad_inst_divu || decd_mad_inst_remu; assign rem_vld = decd_mad_inst_rem || decd_mad_inst_remu; assign mulh_vld = decd_mad_inst_mulhu || decd_mad_inst_mulh || decd_mad_inst_mulhsu; assign mad_rs1_abs[31:0] = ~mad_rs1[31:0] + 1'b1; assign mad_rs2_abs[31:0] = ~mad_rs2[31:0] + 1'b1; assign mad_rs1_fin[31:0] = mad_rs1_abs_sel ? mad_rs1_abs[31:0] : mad_rs1[31:0]; assign mad_rs2_abs_sel = !(decd_mad_inst_mulhu || decd_mad_inst_mulhsu || div_unsigned) && mad_rs2[31]; assign mad_rs2_fin[31:0] = mad_rs2_abs_sel ? mad_rs2_abs[31:0] : mad_rs2[31:0]; assign rs1_eqlz = mad_rs1[31:0] == 32'b0; assign rs2_eqlz = mad_rs2[31:0] == 32'b0; assign iu_ifu_cnt_write_en = ctrl_mad_ex_sel && (div_vld ? ifu_iu_mad_wfi2 : ifu_iu_mad_wfi2); assign iu_ifu_cnt[4:0] = mult_vld ? rst_ff1[4:0] : div_cnt[4:0]; assign mad_ff1_src[31:0] = ifu_iu_mad_idle && div_vld ? mad_rs1_fin[31:0] : mad_rs2_fin[31:0]; always @( mad_ff1_src[31:0]) begin rst_ff1[4:0] = 5'd0; casez(mad_ff1_src[31:0]) 32'b1???????????????????????????????: rst_ff1[4:0] = 5'd31; 32'b01??????????????????????????????: rst_ff1[4:0] = 5'd30; 32'b001?????????????????????????????: rst_ff1[4:0] = 5'd29; 32'b0001????????????????????????????: rst_ff1[4:0] = 5'd28; 32'b00001???????????????????????????: rst_ff1[4:0] = 5'd27; 32'b000001??????????????????????????: rst_ff1[4:0] = 5'd26; 32'b0000001?????????????????????????: rst_ff1[4:0] = 5'd25; 32'b00000001????????????????????????: rst_ff1[4:0] = 5'd24; 32'b000000001???????????????????????: rst_ff1[4:0] = 5'd23; 32'b0000000001??????????????????????: rst_ff1[4:0] = 5'd22; 32'b00000000001?????????????????????: rst_ff1[4:0] = 5'd21; 32'b000000000001????????????????????: rst_ff1[4:0] = 5'd20; 32'b0000000000001???????????????????: rst_ff1[4:0] = 5'd19; 32'b00000000000001??????????????????: rst_ff1[4:0] = 5'd18; 32'b000000000000001?????????????????: rst_ff1[4:0] = 5'd17; 32'b0000000000000001????????????????: rst_ff1[4:0] = 5'd16; 32'b00000000000000001???????????????: rst_ff1[4:0] = 5'd15; 32'b000000000000000001??????????????: rst_ff1[4:0] = 5'd14; 32'b0000000000000000001?????????????: rst_ff1[4:0] = 5'd13; 32'b00000000000000000001????????????: rst_ff1[4:0] = 5'd12; 32'b000000000000000000001???????????: rst_ff1[4:0] = 5'd11; 32'b0000000000000000000001??????????: rst_ff1[4:0] = 5'd10; 32'b00000000000000000000001?????????: rst_ff1[4:0] = 5'd9; 32'b000000000000000000000001????????: rst_ff1[4:0] = 5'd8; 32'b0000000000000000000000001???????: rst_ff1[4:0] = 5'd7; 32'b00000000000000000000000001??????: rst_ff1[4:0] = 5'd6; 32'b000000000000000000000000001?????: rst_ff1[4:0] = 5'd5; 32'b0000000000000000000000000001????: rst_ff1[4:0] = 5'd4; 32'b00000000000000000000000000001???: rst_ff1[4:0] = 5'd3; 32'b000000000000000000000000000001??: rst_ff1[4:0] = 5'd2; 32'b0000000000000000000000000000001?: rst_ff1[4:0] = 5'd1; 32'b00000000000000000000000000000001: rst_ff1[4:0] = 5'd0; endcase end always @ (posedge mad_clk or negedge cpurst_b) begin if(!cpurst_b) mad_internal[31:0] <= 32'b0; else if (ctrl_mad_ex_sel && mulh_vld && ifu_iu_mad_wfi2) mad_internal[31:0] <= 32'b0; else if (ctrl_mad_ex_sel && mulh_vld) mad_internal[31:0] <= mult_high_data[31:0]; else if (ctrl_mad_ex_sel && div_vld && ifu_iu_mad_idle && (quot_zero || div_zero)) mad_internal[31:0] <= mad_rs1_fin[31:0]; else if (ctrl_mad_ex_sel && div_vld && ifu_iu_mad_idle) mad_internal[31:0] <= {27'b0, rst_ff1[4:0]}; else if (ctrl_mad_ex_sel && div_vld && ifu_iu_mad_wfi2) mad_internal[31:0] <= mad_rs1_fin[31:0]; else if (ctrl_mad_ex_sel && div_vld && split_on && div_single_quotient && !ifu_iu_mad_pair) mad_internal[31:0] <= alu_mad_adder_rst[31:0]; else mad_internal[31:0] <= mad_internal[31:0]; end assign mad_pair = 1'b0; always @ (posedge mad_clk or negedge cpurst_b) begin if(!cpurst_b) mad_neg <= 1'b0; else if(ifu_iu_mult_sign) mad_neg <= 1'b1; else if(!split_on) mad_neg <= 1'b0; else mad_neg <= mad_neg; end assign div_neg = !div_unsigned && (mad_rs1[31] ^ mad_rs2[31]) && !rs1_eqlz; assign quot_zero = ifu_iu_mad_idle && alu_mad_rst_cout && !rs2_eqlz && alu_mad_adder_rst[31:0] != 32'b0; assign div_zero = rs2_eqlz; assign rs1_ff1_rst[4:0] = {5{ifu_iu_mad_wfi2}} & mad_internal[4:0]; assign rs2_ff1_rst[4:0] = rst_ff1[4:0]; assign ff1_disp[4:0] = rs1_ff1_rst[4:0] - rs2_ff1_rst[4:0]; assign div_cnt[4:0] = ff1_disp[4:0]; assign div_rs2_shift = div_vld && ifu_iu_mad_split; assign div_single_quotient = !alu_mad_rst_cout; assign div_ifu_imm_pre[31:0] = {32{!ifu_iu_mad_wfi2}} & {lsu_iu_mad_buf[30:0], div_single_quotient}; assign div_ifu_imm[31:0] = {32{!quot_zero}} & div_ifu_imm_pre[31:0] | {32{div_zero}}; assign div_quotient[31:0] = div_ifu_imm[31:0]; assign div_remainder[31:0] = (quot_zero || div_zero) ? mad_rs1[31:0] : div_single_quotient ? alu_mad_adder_rst[31:0] : mad_internal[31:0]; assign div_rst_sel[31:0] = rem_vld ? div_remainder[31:0] : div_quotient[31:0]; assign div_rst_neg = rem_vld ? !div_unsigned && mad_rs1[31] && !(quot_zero || div_zero) : div_neg && !rs2_eqlz; assign div_rst_rev[31:0] = {32{div_rst_neg}} ^ div_rst_sel[31:0]; assign div_rst[31:0] = div_rst_rev[31:0] + div_rst_neg; assign mad_alu_rs1_vld = div_vld || mult_vld; assign mad_alu_rs1[31:0] = div_rs2_shift ? mad_internal[31:0] : mad_rs1_fin[31:0]; assign mad_alu_div_shift = div_rs2_shift; assign mad_alu_fst_add = ifu_iu_mad_idle && mad_rs2_abs_sel; assign mad_alu_div_rs2[31:0] = mad_rs2_fin[31:0]; assign iu_ifu_mad_cmplt = div_vld && ifu_iu_mad_idle && (quot_zero || div_zero) && ctrl_mad_ex_sel; assign iu_lsu_imm_data[31:0] = div_vld ? div_ifu_imm[31:0] : mult_ifu_imm[31:0]; assign mad_rbus_req = ctrl_mad_ex_sel && split_mad_cmplt; assign mad_alu_data_vld = split_mad_cmplt; assign mad_alu_rst_vld = mult_vld || div_vld; assign mad_alu_rst[31:0] = div_vld ? div_rst[31:0] : mult_rst[31:0]; assign iu_ifu_ex_stall = wb_ctrl_stall; assign ifu_iu_ex_split_on = split_on; assign mad_ctrl_stall = split_xx_stall; assign mad_ctrl_stall_noinput = split_on && !split_last_noinput; assign split_last_noinput = (cur_st == IDLE) && (mls_vld_no_cancel && mls_cmplt || mad_vld_no_cancel && iu_ifu_mad_cmplt) || (cur_st == SPLIT) && ((mls_vld_no_cancel && mls_cmplt) || (mad_vld_no_cancel && mad_cmplt) ) || cur_st[2] || (cur_st == WFI1) && iu_ifu_mad_cmplt || (cur_st == WFI2) && iu_ifu_mad_cmplt; gated_clk_cell x_split_cnt_upd_clkhdr ( .clk_in (forever_cpuclk ), .clk_out (split_cnt_upd_clk ), .external_en (1'b0 ), .global_en (cp0_yy_clk_en ), .local_en (split_cnt_upd_en ), .module_en (1'b0 ), .pad_yy_gate_clk_en_b (pad_yy_gate_clk_en_b), .pad_yy_test_mode (pad_yy_test_mode ) ); assign split_cnt_upd_en = split_cnt_rst || split_cnt_en || split_cnt_write_en; gated_clk_cell x_sm_upd_clkhdr ( .clk_in (forever_cpuclk ), .clk_out (sm_upd_clk ), .external_en (1'b0 ), .global_en (cp0_yy_clk_en ), .local_en (sm_upd_en ), .module_en (1'b0 ), .pad_yy_gate_clk_en_b (pad_yy_gate_clk_en_b), .pad_yy_test_mode (pad_yy_test_mode ) ); assign sm_upd_en = retire_mad_ex_cancel || mad_vld_no_cancel || iu_ifu_cnt_write_en; assign split_cnt_write_en = iu_ifu_cnt_write_en; always @(posedge split_cnt_upd_clk or negedge cpurst_b) begin if(!cpurst_b) split_cnt[4:0] <= 5'b0; else if(split_cnt_rst) split_cnt[4:0] <= 5'b0; else if(split_cnt_write_en) split_cnt[4:0] <= iu_ifu_cnt[4:0]; else if(split_cnt_en) split_cnt[4:0] <= cnt_en ? split_cnt_dec[4:0]: split_cnt_inc[4:0]; end assign split_cnt_inc[4:0] = split_cnt[4:0] + split_cnt_offset; assign split_cnt_dec[4:0] = split_cnt[4:0] - split_cnt_offset; assign split_cnt_offset = 1'b1; assign ifu_iu_ex_cnt[4:0] = split_cnt[4:0]; assign mls_vld_no_cancel = 1'b0; assign mls_cmplt = 1'b0; assign mad_vld_no_cancel = ctrl_mad_ex_sel; assign split_mad_cmplt = split_last; assign mad_pair_vld = 1'b0; assign mad_pair_mult_sign = 1'b0; assign mad_cmplt = split_cnt[4:0] == 5'b0; always @(posedge sm_upd_clk or negedge cpurst_b) begin if(!cpurst_b) cur_st[2:0] <= IDLE; else if(retire_mad_ex_cancel) cur_st[2:0] <= IDLE; else cur_st[2:0] <= nxt_st[2:0]; end always @( iu_ifu_mad_cmplt or mad_cmplt or mls_cmplt or mls_vld_no_cancel or iu_ifu_cnt_write_en or mad_pair_mult_sign or mad_vld_no_cancel or iu_ifu_ex_stall or mad_pair_vld or cur_st) begin case(cur_st) IDLE: begin nxt_st = IDLE; if(iu_ifu_ex_stall) nxt_st = IDLE; else begin case({mls_vld_no_cancel, mad_vld_no_cancel}) 2'b10: begin if(!mls_cmplt) nxt_st = SPLIT; end 2'b01: begin if(mad_pair_vld) if(mad_pair_mult_sign) nxt_st = PAIRS; else nxt_st = PAIR; else if(iu_ifu_mad_cmplt) nxt_st = IDLE; else nxt_st = WFI2; end default; endcase end end WFI1: begin nxt_st = WFI1; if(iu_ifu_mad_cmplt) nxt_st = IDLE; else if(!iu_ifu_ex_stall) nxt_st = WFI2; end WFI2: begin nxt_st = WFI2; if(iu_ifu_mad_cmplt) nxt_st = IDLE; else if(iu_ifu_cnt_write_en) begin nxt_st = SPLIT; end end SPLIT: begin nxt_st = SPLIT; case({mls_vld_no_cancel, mad_vld_no_cancel}) 2'b10: begin if(mls_cmplt) nxt_st = IDLE; end 2'b01: begin if(mad_cmplt) nxt_st = IDLE; end default; endcase end PAIR: begin nxt_st = IDLE; end PAIRS: begin nxt_st = IDLE; end default: nxt_st = IDLE; endcase end assign split_on = (cur_st != IDLE) || mls_vld_no_cancel || mad_vld_no_cancel; assign cnt_en = (cur_st == IDLE) && !iu_ifu_ex_stall && ((mls_vld_no_cancel && !mls_cmplt) || mad_vld_no_cancel) || (cur_st == SPLIT) && !iu_ifu_ex_stall && ((mls_vld_no_cancel && !mls_cmplt) || (mad_vld_no_cancel && !mad_cmplt) ); assign split_last = (cur_st == IDLE) && !iu_ifu_ex_stall && (mls_vld_no_cancel && mls_cmplt || mad_vld_no_cancel && iu_ifu_mad_cmplt) || (cur_st == SPLIT) && !iu_ifu_ex_stall && ((mls_vld_no_cancel && mls_cmplt) || (mad_vld_no_cancel && mad_cmplt) ) || cur_st[2] || (cur_st == WFI1) && iu_ifu_mad_cmplt || (cur_st == WFI2) && iu_ifu_mad_cmplt; assign ifu_iu_mad_idle = (cur_st == IDLE); assign ifu_iu_mad_wfi2 = (cur_st == WFI2); assign ifu_iu_mad_split = (cur_st == SPLIT); assign ifu_iu_mad_pair = 1'b0; assign ifu_iu_mult_sign = 1'b0; assign split_cnt_rst = split_last || iu_yy_xx_flush; assign split_cnt_en = cnt_en; assign split_xx_stall = (split_on && !split_last) ; endmodule module cr_iu_oper( cp0_yy_clk_en, ctrl_oper_lsu_data_sel, decd_oper_alu_imm, decd_oper_branch_imm, decd_oper_cp0_imm, decd_oper_lsu_imm, forever_cpuclk, had_idu_wbbr_data, had_idu_wbbr_vld, hs_split_iu_nsinst_gpr_rst_b, ifu_iu_ex_rs1_reg, ifu_iu_ex_rs2_reg, iu_cp0_imm, iu_cp0_rs1, iu_lsu_base, iu_lsu_data, iu_lsu_offset, iu_lsu_rs2, iu_yy_xx_reg_rst_b, oper_alu_rs1_reg, oper_alu_rs2_imm, oper_alu_rs2_reg, oper_branch_rs1_reg, oper_branch_rs2_imm, oper_branch_rs2_reg, oper_mad_rs1, oper_mad_rs2, oper_wb_rs1_equal_to_dst, oper_wb_rs2_equal_to_dst, pad_yy_gate_clk_en_b, pad_yy_test_mode, randclk_oper_gpr_mod_en_w32, wb_oper_fwd_data_no_load, wb_oper_fwd_en, wb_oper_write_data, wb_oper_write_en, wb_oper_write_idx, wb_oper_write_idx_for_dep ); input cp0_yy_clk_en; input ctrl_oper_lsu_data_sel; input [31:0] decd_oper_alu_imm; input [31:0] decd_oper_branch_imm; input [11:0] decd_oper_cp0_imm; input [31:0] decd_oper_lsu_imm; input forever_cpuclk; input [31:0] had_idu_wbbr_data; input had_idu_wbbr_vld; input hs_split_iu_nsinst_gpr_rst_b; input [4 :0] ifu_iu_ex_rs1_reg; input [4 :0] ifu_iu_ex_rs2_reg; input iu_yy_xx_reg_rst_b; input pad_yy_gate_clk_en_b; input pad_yy_test_mode; input [20:0] randclk_oper_gpr_mod_en_w32; input [31:0] wb_oper_fwd_data_no_load; input wb_oper_fwd_en; input [31:0] wb_oper_write_data; input wb_oper_write_en; input [4 :0] wb_oper_write_idx; input [4 :0] wb_oper_write_idx_for_dep; output [11:0] iu_cp0_imm; output [31:0] iu_cp0_rs1; output [31:0] iu_lsu_base; output [31:0] iu_lsu_data; output [31:0] iu_lsu_offset; output [31:0] iu_lsu_rs2; output [31:0] oper_alu_rs1_reg; output [31:0] oper_alu_rs2_imm; output [31:0] oper_alu_rs2_reg; output [31:0] oper_branch_rs1_reg; output [31:0] oper_branch_rs2_imm; output [31:0] oper_branch_rs2_reg; output [31:0] oper_mad_rs1; output [31:0] oper_mad_rs2; output oper_wb_rs1_equal_to_dst; output oper_wb_rs2_equal_to_dst; wire cp0_yy_clk_en; wire ctrl_oper_lsu_data_sel; wire [31:0] decd_oper_alu_imm; wire [31:0] decd_oper_branch_imm; wire [11:0] decd_oper_cp0_imm; wire [31:0] decd_oper_lsu_imm; wire forever_cpuclk; wire [31:0] had_idu_wbbr_data; wire had_idu_wbbr_vld; wire hs_split_iu_nsinst_gpr_rst_b; wire [4 :0] ifu_iu_ex_rs1_reg; wire [4 :0] ifu_iu_ex_rs2_reg; wire [11:0] iu_cp0_imm; wire [31:0] iu_cp0_rs1; wire [31:0] iu_lsu_base; wire [31:0] iu_lsu_data; wire [31:0] iu_lsu_offset; wire [31:0] iu_lsu_rs2; wire iu_yy_xx_reg_rst_b; wire [31:0] oper_alu_rs1_reg; wire [31:0] oper_alu_rs2_imm; wire [31:0] oper_alu_rs2_reg; wire [31:0] oper_branch_rs1_reg; wire [31:0] oper_branch_rs2_imm; wire [31:0] oper_branch_rs2_reg; wire [31:0] oper_imm_for_alu; wire [31:0] oper_imm_for_branch; wire [11:0] oper_imm_for_cp0; wire [31:0] oper_imm_for_lsu; wire [31:0] oper_mad_rs1; wire [31:0] oper_mad_rs2; wire oper_rs1_bsp_dep_vld; wire oper_rs1_dep_vld; wire oper_rs1_dep_vld_aft_bsp; wire oper_rs1_equal_to_dst; wire [31:0] oper_rs1_gpr_data; wire [31:0] oper_rs1_gpr_reg; wire [31:0] oper_rs1_reg; wire [31:0] oper_rs1_reg_before_pol; wire [31:0] oper_rs1_reg_no_load; wire [31:0] oper_rs1_reg_no_load_before_pol; wire oper_rs2_dep_vld; wire oper_rs2_equal_to_dst; wire [31:0] oper_rs2_gpr_data; wire [31:0] oper_rs2_gpr_reg; wire [31:0] oper_rs2_reg; wire [31:0] oper_rs2_reg_before_pol; wire [31:0] oper_rs2_reg_no_load; wire [31:0] oper_rs2_reg_no_load_before_pol; wire oper_wb_rs1_equal_to_dst; wire oper_wb_rs2_equal_to_dst; wire pad_yy_gate_clk_en_b; wire pad_yy_test_mode; wire [20:0] randclk_oper_gpr_mod_en_w32; wire [31:0] wb_data_no_load_aft_bsp_fwd; wire [31:0] wb_oper_fwd_data_no_load; wire wb_oper_fwd_en; wire [31:0] wb_oper_write_data; wire wb_oper_write_en; wire [4 :0] wb_oper_write_idx; wire [4 :0] wb_oper_write_idx_for_dep; cr_iu_oper_gpr x_cr_iu_oper_gpr ( .cp0_yy_clk_en (cp0_yy_clk_en ), .forever_cpuclk (forever_cpuclk ), .hs_split_iu_nsinst_gpr_rst_b (hs_split_iu_nsinst_gpr_rst_b ), .inst_read_data0 (oper_rs1_gpr_data[31:0] ), .inst_read_data1 (oper_rs2_gpr_data[31:0] ), .inst_read_index0 (ifu_iu_ex_rs1_reg[4:0] ), .inst_read_index1 (ifu_iu_ex_rs2_reg[4:0] ), .inst_wen (wb_oper_write_en ), .inst_write_data (wb_oper_write_data[31:0] ), .inst_write_index (wb_oper_write_idx[4:0] ), .iu_yy_xx_reg_rst_b (iu_yy_xx_reg_rst_b ), .pad_yy_gate_clk_en_b (pad_yy_gate_clk_en_b ), .pad_yy_test_mode (pad_yy_test_mode ), .randclk_oper_gpr_mod_en_w32 (randclk_oper_gpr_mod_en_w32 ) ); assign oper_rs1_gpr_reg[31:0] = (had_idu_wbbr_vld && !ctrl_oper_lsu_data_sel) ? had_idu_wbbr_data[31:0] : oper_rs1_gpr_data[31:0]; assign oper_rs2_gpr_reg[31:0] = had_idu_wbbr_vld ? had_idu_wbbr_data[31:0] : oper_rs2_gpr_data[31:0]; assign oper_rs1_equal_to_dst = (ifu_iu_ex_rs1_reg[4:0] == wb_oper_write_idx_for_dep[4:0]) && ifu_iu_ex_rs1_reg[4:0] != 5'b0; assign oper_rs2_equal_to_dst = (ifu_iu_ex_rs2_reg[4:0] == wb_oper_write_idx_for_dep[4:0]) && ifu_iu_ex_rs2_reg[4:0] != 5'b0; assign oper_wb_rs1_equal_to_dst = oper_rs1_equal_to_dst; assign oper_wb_rs2_equal_to_dst = oper_rs2_equal_to_dst; assign oper_rs1_dep_vld = wb_oper_fwd_en && oper_rs1_equal_to_dst; assign oper_rs2_dep_vld = wb_oper_fwd_en && oper_rs2_equal_to_dst; assign oper_rs1_bsp_dep_vld = 1'b0; assign wb_data_no_load_aft_bsp_fwd[31:0] = wb_oper_fwd_data_no_load[31:0]; assign oper_rs1_reg_before_pol[31:0] = (oper_rs1_dep_vld && !had_idu_wbbr_vld) ? wb_oper_write_data[31:0] : oper_rs1_gpr_reg[31:0]; assign oper_rs2_reg_before_pol[31:0] = (oper_rs2_dep_vld) ? wb_oper_write_data[31:0] : oper_rs2_gpr_reg[31:0]; assign oper_rs1_dep_vld_aft_bsp = oper_rs1_dep_vld || oper_rs1_bsp_dep_vld; assign oper_rs1_reg_no_load_before_pol[31:0] = (oper_rs1_dep_vld_aft_bsp && !had_idu_wbbr_vld) ? wb_data_no_load_aft_bsp_fwd[31:0] : oper_rs1_gpr_reg[31:0]; assign oper_rs2_reg_no_load_before_pol[31:0] = oper_rs2_dep_vld ? wb_oper_fwd_data_no_load[31:0] : oper_rs2_gpr_reg[31:0]; assign oper_rs1_reg[31:0] = oper_rs1_reg_before_pol[31:0]; assign oper_rs2_reg[31:0] = oper_rs2_reg_before_pol[31:0]; assign oper_rs1_reg_no_load[31:0] = oper_rs1_reg_no_load_before_pol[31:0]; assign oper_rs2_reg_no_load[31:0] = oper_rs2_reg_no_load_before_pol[31:0]; assign oper_imm_for_alu[31:0] = decd_oper_alu_imm[31:0]; assign oper_imm_for_lsu[31:0] = decd_oper_lsu_imm[31:0]; assign oper_imm_for_cp0[11:0] = decd_oper_cp0_imm[11:0]; assign oper_imm_for_branch[31:0] = decd_oper_branch_imm[31:0]; assign oper_alu_rs1_reg[31:0] = oper_rs1_reg[31:0]; assign oper_alu_rs2_reg[31:0] = oper_rs2_reg[31:0]; assign oper_alu_rs2_imm[31:0] = oper_imm_for_alu[31:0]; assign oper_mad_rs1[31:0] = oper_rs1_reg[31:0]; assign oper_mad_rs2[31:0] = oper_rs2_reg[31:0]; assign oper_branch_rs1_reg[31:0] = oper_rs1_reg_no_load[31:0]; assign oper_branch_rs2_reg[31:0] = oper_rs2_reg_no_load[31:0]; assign oper_branch_rs2_imm[31:0] = oper_imm_for_branch[31:0]; assign iu_lsu_offset[31:0] = oper_imm_for_lsu[31:0]; assign iu_lsu_data[31:0] = oper_rs2_reg_before_pol[31:0]; assign iu_lsu_base[31:0] = oper_rs1_reg_no_load[31:0]; assign iu_lsu_rs2[31:0] = oper_rs2_reg_no_load[31:0]; assign iu_cp0_rs1[31:0] = oper_rs1_reg_no_load[31:0]; assign iu_cp0_imm[11:0] = oper_imm_for_cp0[11:0]; endmodule module cr_iu_oper_gpr( cp0_yy_clk_en, forever_cpuclk, hs_split_iu_nsinst_gpr_rst_b, inst_read_data0, inst_read_data1, inst_read_index0, inst_read_index1, inst_wen, inst_write_data, inst_write_index, iu_yy_xx_reg_rst_b, pad_yy_gate_clk_en_b, pad_yy_test_mode, randclk_oper_gpr_mod_en_w32 ); input cp0_yy_clk_en; input forever_cpuclk; input hs_split_iu_nsinst_gpr_rst_b; input [4 :0] inst_read_index0; input [4 :0] inst_read_index1; input inst_wen; input [31:0] inst_write_data; input [4 :0] inst_write_index; input iu_yy_xx_reg_rst_b; input pad_yy_gate_clk_en_b; input pad_yy_test_mode; input [20:0] randclk_oper_gpr_mod_en_w32; output [31:0] inst_read_data0; output [31:0] inst_read_data1; reg [31:0] gpr_read_data0; reg [31:0] gpr_read_data1; reg [31:0] reg_sel; reg [31:0] sp_read_data0; reg [31:0] sp_read_data1; wire [31:0] alter_0_reg_dout; wire [31:0] alter_10_reg_dout; wire [31:0] alter_11_reg_dout; wire [31:0] alter_12_reg_dout; wire [31:0] alter_13_reg_dout; wire [31:0] alter_14_reg_dout; wire [31:0] alter_15_reg_dout; wire [31:0] alter_1_reg_dout; wire [31:0] alter_2_reg_dout; wire [31:0] alter_3_reg_dout; wire [31:0] alter_4_reg_dout; wire [31:0] alter_5_reg_dout; wire [31:0] alter_6_reg_dout; wire [31:0] alter_7_reg_dout; wire [31:0] alter_8_reg_dout; wire [31:0] alter_9_reg_dout; wire alter_mode; wire cp0_yy_clk_en; wire forever_cpuclk; wire gpr_sync_rst_b; wire gpr_sync_rst_for_sp_b; wire hs_split_iu_nsinst_gpr_rst_b; wire [31:0] inst_read_data0; wire [31:0] inst_read_data1; wire [4 :0] inst_read_index0; wire [4 :0] inst_read_index1; wire inst_wen; wire [31:0] inst_write_data; wire [4 :0] inst_write_index; wire iu_yy_xx_reg_rst_b; wire machine_2_randclk_reg_mod_en_w32; wire [31:0] machine_2_reg_dout; wire machine_2_write_en; wire machine_write_en_2; wire pad_cpu_gpr_rst_b; wire pad_yy_gate_clk_en_b; wire pad_yy_test_mode; wire [20:0] randclk_oper_gpr_mod_en_w32; wire user_10_randclk_reg_mod_en_w32; wire [31:0] user_10_reg_dout; wire user_10_write_en; wire user_11_randclk_reg_mod_en_w32; wire [31:0] user_11_reg_dout; wire user_11_write_en; wire user_12_randclk_reg_mod_en_w32; wire [31:0] user_12_reg_dout; wire user_12_write_en; wire user_13_randclk_reg_mod_en_w32; wire [31:0] user_13_reg_dout; wire user_13_write_en; wire user_14_randclk_reg_mod_en_w32; wire [31:0] user_14_reg_dout; wire user_14_write_en; wire user_15_randclk_reg_mod_en_w32; wire [31:0] user_15_reg_dout; wire user_15_write_en; wire user_1_randclk_reg_mod_en_w32; wire [31:0] user_1_reg_dout; wire user_1_write_en; wire user_3_randclk_reg_mod_en_w32; wire [31:0] user_3_reg_dout; wire user_3_write_en; wire user_4_randclk_reg_mod_en_w32; wire [31:0] user_4_reg_dout; wire user_4_write_en; wire user_5_randclk_reg_mod_en_w32; wire [31:0] user_5_reg_dout; wire user_5_write_en; wire user_6_randclk_reg_mod_en_w32; wire [31:0] user_6_reg_dout; wire user_6_write_en; wire user_7_randclk_reg_mod_en_w32; wire [31:0] user_7_reg_dout; wire user_7_write_en; wire user_8_randclk_reg_mod_en_w32; wire [31:0] user_8_reg_dout; wire user_8_write_en; wire user_9_randclk_reg_mod_en_w32; wire [31:0] user_9_reg_dout; wire user_9_write_en; wire [31:0] user_write_en; wire ussp_explicit_we; wire [31:0] write_data; wire [31:0] write_data_for_sp; wire [31:0] write_port_data; cr_iu_gated_clk_reg x_cr_iu_gated_clk_reg_user_1 ( .cp0_yy_clk_en (cp0_yy_clk_en ), .forever_cpuclk (forever_cpuclk ), .pad_yy_gate_clk_en_b (pad_yy_gate_clk_en_b ), .pad_yy_test_mode (pad_yy_test_mode ), .write_data (write_data ), .x_randclk_reg_mod_en_w32 (user_1_randclk_reg_mod_en_w32), .x_reg_dout (user_1_reg_dout ), .x_write_en (user_1_write_en ) ); cr_iu_gated_clk_reg x_cr_iu_gated_clk_reg_user_3 ( .cp0_yy_clk_en (cp0_yy_clk_en ), .forever_cpuclk (forever_cpuclk ), .pad_yy_gate_clk_en_b (pad_yy_gate_clk_en_b ), .pad_yy_test_mode (pad_yy_test_mode ), .write_data (write_data ), .x_randclk_reg_mod_en_w32 (user_3_randclk_reg_mod_en_w32), .x_reg_dout (user_3_reg_dout ), .x_write_en (user_3_write_en ) ); cr_iu_gated_clk_reg x_cr_iu_gated_clk_reg_user_4 ( .cp0_yy_clk_en (cp0_yy_clk_en ), .forever_cpuclk (forever_cpuclk ), .pad_yy_gate_clk_en_b (pad_yy_gate_clk_en_b ), .pad_yy_test_mode (pad_yy_test_mode ), .write_data (write_data ), .x_randclk_reg_mod_en_w32 (user_4_randclk_reg_mod_en_w32), .x_reg_dout (user_4_reg_dout ), .x_write_en (user_4_write_en ) ); cr_iu_gated_clk_reg x_cr_iu_gated_clk_reg_user_5 ( .cp0_yy_clk_en (cp0_yy_clk_en ), .forever_cpuclk (forever_cpuclk ), .pad_yy_gate_clk_en_b (pad_yy_gate_clk_en_b ), .pad_yy_test_mode (pad_yy_test_mode ), .write_data (write_data ), .x_randclk_reg_mod_en_w32 (user_5_randclk_reg_mod_en_w32), .x_reg_dout (user_5_reg_dout ), .x_write_en (user_5_write_en ) ); cr_iu_gated_clk_reg x_cr_iu_gated_clk_reg_user_6 ( .cp0_yy_clk_en (cp0_yy_clk_en ), .forever_cpuclk (forever_cpuclk ), .pad_yy_gate_clk_en_b (pad_yy_gate_clk_en_b ), .pad_yy_test_mode (pad_yy_test_mode ), .write_data (write_data ), .x_randclk_reg_mod_en_w32 (user_6_randclk_reg_mod_en_w32), .x_reg_dout (user_6_reg_dout ), .x_write_en (user_6_write_en ) ); cr_iu_gated_clk_reg x_cr_iu_gated_clk_reg_user_7 ( .cp0_yy_clk_en (cp0_yy_clk_en ), .forever_cpuclk (forever_cpuclk ), .pad_yy_gate_clk_en_b (pad_yy_gate_clk_en_b ), .pad_yy_test_mode (pad_yy_test_mode ), .write_data (write_data ), .x_randclk_reg_mod_en_w32 (user_7_randclk_reg_mod_en_w32), .x_reg_dout (user_7_reg_dout ), .x_write_en (user_7_write_en ) ); cr_iu_gated_clk_reg x_cr_iu_gated_clk_reg_user_8 ( .cp0_yy_clk_en (cp0_yy_clk_en ), .forever_cpuclk (forever_cpuclk ), .pad_yy_gate_clk_en_b (pad_yy_gate_clk_en_b ), .pad_yy_test_mode (pad_yy_test_mode ), .write_data (write_data ), .x_randclk_reg_mod_en_w32 (user_8_randclk_reg_mod_en_w32), .x_reg_dout (user_8_reg_dout ), .x_write_en (user_8_write_en ) ); cr_iu_gated_clk_reg x_cr_iu_gated_clk_reg_user_9 ( .cp0_yy_clk_en (cp0_yy_clk_en ), .forever_cpuclk (forever_cpuclk ), .pad_yy_gate_clk_en_b (pad_yy_gate_clk_en_b ), .pad_yy_test_mode (pad_yy_test_mode ), .write_data (write_data ), .x_randclk_reg_mod_en_w32 (user_9_randclk_reg_mod_en_w32), .x_reg_dout (user_9_reg_dout ), .x_write_en (user_9_write_en ) ); cr_iu_gated_clk_reg x_cr_iu_gated_clk_reg_user_10 ( .cp0_yy_clk_en (cp0_yy_clk_en ), .forever_cpuclk (forever_cpuclk ), .pad_yy_gate_clk_en_b (pad_yy_gate_clk_en_b ), .pad_yy_test_mode (pad_yy_test_mode ), .write_data (write_data ), .x_randclk_reg_mod_en_w32 (user_10_randclk_reg_mod_en_w32), .x_reg_dout (user_10_reg_dout ), .x_write_en (user_10_write_en ) ); cr_iu_gated_clk_reg x_cr_iu_gated_clk_reg_user_11 ( .cp0_yy_clk_en (cp0_yy_clk_en ), .forever_cpuclk (forever_cpuclk ), .pad_yy_gate_clk_en_b (pad_yy_gate_clk_en_b ), .pad_yy_test_mode (pad_yy_test_mode ), .write_data (write_data ), .x_randclk_reg_mod_en_w32 (user_11_randclk_reg_mod_en_w32), .x_reg_dout (user_11_reg_dout ), .x_write_en (user_11_write_en ) ); cr_iu_gated_clk_reg x_cr_iu_gated_clk_reg_user_12 ( .cp0_yy_clk_en (cp0_yy_clk_en ), .forever_cpuclk (forever_cpuclk ), .pad_yy_gate_clk_en_b (pad_yy_gate_clk_en_b ), .pad_yy_test_mode (pad_yy_test_mode ), .write_data (write_data ), .x_randclk_reg_mod_en_w32 (user_12_randclk_reg_mod_en_w32), .x_reg_dout (user_12_reg_dout ), .x_write_en (user_12_write_en ) ); cr_iu_gated_clk_reg x_cr_iu_gated_clk_reg_user_13 ( .cp0_yy_clk_en (cp0_yy_clk_en ), .forever_cpuclk (forever_cpuclk ), .pad_yy_gate_clk_en_b (pad_yy_gate_clk_en_b ), .pad_yy_test_mode (pad_yy_test_mode ), .write_data (write_data ), .x_randclk_reg_mod_en_w32 (user_13_randclk_reg_mod_en_w32), .x_reg_dout (user_13_reg_dout ), .x_write_en (user_13_write_en ) ); cr_iu_gated_clk_reg x_cr_iu_gated_clk_reg_user_14 ( .cp0_yy_clk_en (cp0_yy_clk_en ), .forever_cpuclk (forever_cpuclk ), .pad_yy_gate_clk_en_b (pad_yy_gate_clk_en_b ), .pad_yy_test_mode (pad_yy_test_mode ), .write_data (write_data ), .x_randclk_reg_mod_en_w32 (user_14_randclk_reg_mod_en_w32), .x_reg_dout (user_14_reg_dout ), .x_write_en (user_14_write_en ) ); cr_iu_gated_clk_reg x_cr_iu_gated_clk_reg_user_15 ( .cp0_yy_clk_en (cp0_yy_clk_en ), .forever_cpuclk (forever_cpuclk ), .pad_yy_gate_clk_en_b (pad_yy_gate_clk_en_b ), .pad_yy_test_mode (pad_yy_test_mode ), .write_data (write_data ), .x_randclk_reg_mod_en_w32 (user_15_randclk_reg_mod_en_w32), .x_reg_dout (user_15_reg_dout ), .x_write_en (user_15_write_en ) ); cr_iu_gated_clk_reg_timing x_cr_iu_gated_clk_reg_machine_2 ( .cp0_yy_clk_en (cp0_yy_clk_en ), .forever_cpuclk (forever_cpuclk ), .pad_yy_gate_clk_en_b (pad_yy_gate_clk_en_b ), .pad_yy_test_mode (pad_yy_test_mode ), .write_data (write_data_for_sp[31:0] ), .x_randclk_reg_mod_en_w32 (machine_2_randclk_reg_mod_en_w32), .x_reg_dout (machine_2_reg_dout ), .x_write_en (machine_2_write_en ) ); assign user_1_randclk_reg_mod_en_w32 = randclk_oper_gpr_mod_en_w32[1]; assign user_3_randclk_reg_mod_en_w32 = randclk_oper_gpr_mod_en_w32[3]; assign user_4_randclk_reg_mod_en_w32 = randclk_oper_gpr_mod_en_w32[4]; assign user_5_randclk_reg_mod_en_w32 = randclk_oper_gpr_mod_en_w32[5]; assign user_6_randclk_reg_mod_en_w32 = randclk_oper_gpr_mod_en_w32[6]; assign user_7_randclk_reg_mod_en_w32 = randclk_oper_gpr_mod_en_w32[7]; assign user_8_randclk_reg_mod_en_w32 = randclk_oper_gpr_mod_en_w32[8]; assign user_9_randclk_reg_mod_en_w32 = randclk_oper_gpr_mod_en_w32[9]; assign user_10_randclk_reg_mod_en_w32 = randclk_oper_gpr_mod_en_w32[10]; assign user_11_randclk_reg_mod_en_w32 = randclk_oper_gpr_mod_en_w32[11]; assign user_12_randclk_reg_mod_en_w32 = randclk_oper_gpr_mod_en_w32[12]; assign user_13_randclk_reg_mod_en_w32 = randclk_oper_gpr_mod_en_w32[13]; assign user_14_randclk_reg_mod_en_w32 = randclk_oper_gpr_mod_en_w32[14]; assign user_15_randclk_reg_mod_en_w32 = randclk_oper_gpr_mod_en_w32[15]; assign machine_2_randclk_reg_mod_en_w32 = randclk_oper_gpr_mod_en_w32[16]; assign pad_cpu_gpr_rst_b = 1'b1; assign gpr_sync_rst_b = pad_cpu_gpr_rst_b && iu_yy_xx_reg_rst_b && hs_split_iu_nsinst_gpr_rst_b; assign gpr_sync_rst_for_sp_b = pad_cpu_gpr_rst_b && iu_yy_xx_reg_rst_b; assign write_port_data[31:0] = {32{gpr_sync_rst_b}} & inst_write_data[31:0]; assign write_data[31:0] = write_port_data[31:0]; assign write_data_for_sp[31:0] = write_port_data[31:0]; always @( inst_write_index[4:0]) begin reg_sel[31:0] = 32'b0; case(inst_write_index[4:0]) 5'h0 : reg_sel[0] = 1'b1; 5'h1 : reg_sel[1] = 1'b1; 5'h2 : reg_sel[2] = 1'b1; 5'h3 : reg_sel[3] = 1'b1; 5'h4 : reg_sel[4] = 1'b1; 5'h5 : reg_sel[5] = 1'b1; 5'h6 : reg_sel[6] = 1'b1; 5'h7 : reg_sel[7] = 1'b1; 5'h8 : reg_sel[8] = 1'b1; 5'h9 : reg_sel[9] = 1'b1; 5'ha : reg_sel[10] = 1'b1; 5'hb : reg_sel[11] = 1'b1; 5'hc : reg_sel[12] = 1'b1; 5'hd : reg_sel[13] = 1'b1; 5'he : reg_sel[14] = 1'b1; 5'hf : reg_sel[15] = 1'b1; endcase end assign user_write_en[31:3] = reg_sel[31:3] & {29{inst_wen}}; assign user_write_en[1:0] = reg_sel[1:0] & {2{inst_wen}}; assign user_write_en[2] = 1'b0; assign ussp_explicit_we = reg_sel[2] && inst_wen || !gpr_sync_rst_for_sp_b; assign machine_write_en_2 = ussp_explicit_we; assign user_1_write_en = !gpr_sync_rst_b | user_write_en[1]; assign user_3_write_en = !gpr_sync_rst_b | user_write_en[3]; assign user_4_write_en = !gpr_sync_rst_b | user_write_en[4]; assign user_5_write_en = !gpr_sync_rst_b | user_write_en[5]; assign user_6_write_en = !gpr_sync_rst_b | user_write_en[6]; assign user_7_write_en = !gpr_sync_rst_b | user_write_en[7]; assign user_8_write_en = !gpr_sync_rst_b | user_write_en[8]; assign user_9_write_en = !gpr_sync_rst_b | user_write_en[9]; assign user_10_write_en = !gpr_sync_rst_b | user_write_en[10]; assign user_11_write_en = !gpr_sync_rst_b | user_write_en[11]; assign user_12_write_en = !gpr_sync_rst_b | user_write_en[12]; assign user_13_write_en = !gpr_sync_rst_b | user_write_en[13]; assign user_14_write_en = !gpr_sync_rst_b | user_write_en[14]; assign user_15_write_en = !gpr_sync_rst_b | user_write_en[15]; assign machine_2_write_en = machine_write_en_2; assign alter_mode = 1'b0; assign alter_0_reg_dout[31:0] = 32'b0; assign alter_1_reg_dout[31:0] = 32'b0; assign alter_2_reg_dout[31:0] = 32'b0; assign alter_3_reg_dout[31:0] = 32'b0; assign alter_4_reg_dout[31:0] = 32'b0; assign alter_5_reg_dout[31:0] = 32'b0; assign alter_6_reg_dout[31:0] = 32'b0; assign alter_7_reg_dout[31:0] = 32'b0; assign alter_8_reg_dout[31:0] = 32'b0; assign alter_9_reg_dout[31:0] = 32'b0; assign alter_10_reg_dout[31:0] = 32'b0; assign alter_11_reg_dout[31:0] = 32'b0; assign alter_12_reg_dout[31:0] = 32'b0; assign alter_13_reg_dout[31:0] = 32'b0; assign alter_14_reg_dout[31:0] = 32'b0; assign alter_15_reg_dout[31:0] = 32'b0; always @( user_8_reg_dout[31:0] or alter_3_reg_dout[31:0] or alter_7_reg_dout[31:0] or alter_13_reg_dout[31:0] or inst_read_index0[4:0] or user_11_reg_dout[31:0] or user_10_reg_dout[31:0] or user_3_reg_dout[31:0] or user_9_reg_dout[31:0] or alter_15_reg_dout[31:0] or alter_1_reg_dout[31:0] or alter_6_reg_dout[31:0] or user_1_reg_dout[31:0] or sp_read_data0[31:0] or user_13_reg_dout[31:0] or alter_5_reg_dout[31:0] or alter_4_reg_dout[31:0] or alter_mode or user_4_reg_dout[31:0] or user_5_reg_dout[31:0] or user_15_reg_dout[31:0] or user_6_reg_dout[31:0] or alter_10_reg_dout[31:0] or alter_12_reg_dout[31:0] or alter_9_reg_dout[31:0] or alter_11_reg_dout[31:0] or alter_0_reg_dout[31:0] or user_14_reg_dout[31:0] or user_12_reg_dout[31:0] or user_7_reg_dout[31:0] or alter_8_reg_dout[31:0] or alter_14_reg_dout[31:0]) begin case(inst_read_index0[4:0]) 5'h0: if(alter_mode) gpr_read_data0[31:0] = alter_0_reg_dout[31:0]; else gpr_read_data0[31:0] = 32'b0; 5'h1: if(alter_mode) gpr_read_data0[31:0] = alter_1_reg_dout[31:0]; else gpr_read_data0[31:0] = user_1_reg_dout[31:0]; 5'h2: gpr_read_data0[31:0] = sp_read_data0[31:0]; 5'h3: if(alter_mode) gpr_read_data0[31:0] = alter_3_reg_dout[31:0]; else gpr_read_data0[31:0] = user_3_reg_dout[31:0]; 5'h4: if(alter_mode) gpr_read_data0[31:0] = alter_4_reg_dout[31:0]; else gpr_read_data0[31:0] = user_4_reg_dout[31:0]; 5'h5: if(alter_mode) gpr_read_data0[31:0] = alter_5_reg_dout[31:0]; else gpr_read_data0[31:0] = user_5_reg_dout[31:0]; 5'h6: if(alter_mode) gpr_read_data0[31:0] = alter_6_reg_dout[31:0]; else gpr_read_data0[31:0] = user_6_reg_dout[31:0]; 5'h7: if(alter_mode) gpr_read_data0[31:0] = alter_7_reg_dout[31:0]; else gpr_read_data0[31:0] = user_7_reg_dout[31:0]; 5'h8: if(alter_mode) gpr_read_data0[31:0] = alter_8_reg_dout[31:0]; else gpr_read_data0[31:0] = user_8_reg_dout[31:0]; 5'h9: if(alter_mode) gpr_read_data0[31:0] = alter_9_reg_dout[31:0]; else gpr_read_data0[31:0] = user_9_reg_dout[31:0]; 5'ha: if(alter_mode) gpr_read_data0[31:0] = alter_10_reg_dout[31:0]; else gpr_read_data0[31:0] = user_10_reg_dout[31:0]; 5'hb: if(alter_mode) gpr_read_data0[31:0] = alter_11_reg_dout[31:0]; else gpr_read_data0[31:0] = user_11_reg_dout[31:0]; 5'hc: if(alter_mode) gpr_read_data0[31:0] = alter_12_reg_dout[31:0]; else gpr_read_data0[31:0] = user_12_reg_dout[31:0]; 5'hd: if(alter_mode) gpr_read_data0[31:0] = alter_13_reg_dout[31:0]; else gpr_read_data0[31:0] = user_13_reg_dout[31:0]; 5'he: if(alter_mode) gpr_read_data0[31:0] = alter_14_reg_dout[31:0]; else gpr_read_data0[31:0] = user_14_reg_dout[31:0]; 5'hf: if(alter_mode) gpr_read_data0[31:0] = alter_15_reg_dout[31:0]; else gpr_read_data0[31:0] = user_15_reg_dout[31:0]; default: gpr_read_data0[31:0] = 32'b0; endcase end always @( alter_2_reg_dout[31:0] or alter_mode or machine_2_reg_dout[31:0]) begin if(alter_mode) sp_read_data0[31:0] = alter_2_reg_dout[31:0]; else sp_read_data0[31:0] = machine_2_reg_dout[31:0]; end assign inst_read_data0[31:0] = gpr_read_data0[31:0]; always @( user_8_reg_dout[31:0] or alter_3_reg_dout[31:0] or sp_read_data1[31:0] or alter_7_reg_dout[31:0] or alter_13_reg_dout[31:0] or user_11_reg_dout[31:0] or user_10_reg_dout[31:0] or user_3_reg_dout[31:0] or user_9_reg_dout[31:0] or alter_15_reg_dout[31:0] or inst_read_index1[4:0] or alter_1_reg_dout[31:0] or alter_6_reg_dout[31:0] or user_1_reg_dout[31:0] or user_13_reg_dout[31:0] or alter_5_reg_dout[31:0] or alter_4_reg_dout[31:0] or alter_mode or user_4_reg_dout[31:0] or user_5_reg_dout[31:0] or user_15_reg_dout[31:0] or user_6_reg_dout[31:0] or alter_12_reg_dout[31:0] or alter_10_reg_dout[31:0] or alter_9_reg_dout[31:0] or alter_11_reg_dout[31:0] or user_14_reg_dout[31:0] or alter_0_reg_dout[31:0] or user_12_reg_dout[31:0] or user_7_reg_dout[31:0] or alter_8_reg_dout[31:0] or alter_14_reg_dout[31:0]) begin case(inst_read_index1[4:0]) 5'h0: if(alter_mode) gpr_read_data1[31:0] = alter_0_reg_dout[31:0]; else gpr_read_data1[31:0] = 32'b0; 5'h1: if(alter_mode) gpr_read_data1[31:0] = alter_1_reg_dout[31:0]; else gpr_read_data1[31:0] = user_1_reg_dout[31:0]; 5'h2: gpr_read_data1[31:0] = sp_read_data1[31:0]; 5'h3: if(alter_mode) gpr_read_data1[31:0] = alter_3_reg_dout[31:0]; else gpr_read_data1[31:0] = user_3_reg_dout[31:0]; 5'h4: if(alter_mode) gpr_read_data1[31:0] = alter_4_reg_dout[31:0]; else gpr_read_data1[31:0] = user_4_reg_dout[31:0]; 5'h5: if(alter_mode) gpr_read_data1[31:0] = alter_5_reg_dout[31:0]; else gpr_read_data1[31:0] = user_5_reg_dout[31:0]; 5'h6: if(alter_mode) gpr_read_data1[31:0] = alter_6_reg_dout[31:0]; else gpr_read_data1[31:0] = user_6_reg_dout[31:0]; 5'h7: if(alter_mode) gpr_read_data1[31:0] = alter_7_reg_dout[31:0]; else gpr_read_data1[31:0] = user_7_reg_dout[31:0]; 5'h8: if(alter_mode) gpr_read_data1[31:0] = alter_8_reg_dout[31:0]; else gpr_read_data1[31:0] = user_8_reg_dout[31:0]; 5'h9: if(alter_mode) gpr_read_data1[31:0] = alter_9_reg_dout[31:0]; else gpr_read_data1[31:0] = user_9_reg_dout[31:0]; 5'ha: if(alter_mode) gpr_read_data1[31:0] = alter_10_reg_dout[31:0]; else gpr_read_data1[31:0] = user_10_reg_dout[31:0]; 5'hb: if(alter_mode) gpr_read_data1[31:0] = alter_11_reg_dout[31:0]; else gpr_read_data1[31:0] = user_11_reg_dout[31:0]; 5'hc: if(alter_mode) gpr_read_data1[31:0] = alter_12_reg_dout[31:0]; else gpr_read_data1[31:0] = user_12_reg_dout[31:0]; 5'hd: if(alter_mode) gpr_read_data1[31:0] = alter_13_reg_dout[31:0]; else gpr_read_data1[31:0] = user_13_reg_dout[31:0]; 5'he: if(alter_mode) gpr_read_data1[31:0] = alter_14_reg_dout[31:0]; else gpr_read_data1[31:0] = user_14_reg_dout[31:0]; 5'hf: if(alter_mode) gpr_read_data1[31:0] = alter_15_reg_dout[31:0]; else gpr_read_data1[31:0] = user_15_reg_dout[31:0]; default: gpr_read_data1[31:0] = 32'b0; endcase end always @( alter_2_reg_dout[31:0] or alter_mode or machine_2_reg_dout[31:0]) begin if(alter_mode) sp_read_data1[31:0] = alter_2_reg_dout[31:0]; else sp_read_data1[31:0] = machine_2_reg_dout[31:0]; end assign inst_read_data1[31:0] = gpr_read_data1[31:0]; endmodule module cr_iu_pcgen( branch_pcgen_add_pc, branch_pcgen_br_chgflw_vld, branch_pcgen_br_chgflw_vld_for_data, branch_pcgen_br_pc_chgflw_vld, branch_pcgen_branch_chgflw_vld_for_data, branch_pcgen_jmp_chgflw_vld_for_data, branch_pcgen_reg_pc, cp0_iu_epc_for_chgflw, cp0_iu_flush_chgflw_vld, cp0_iu_rte_chgflw_vld, cp0_iu_rte_chgflw_vld_for_data, cp0_yy_clk_en, cpurst_b, forever_cpuclk, had_iu_pc, had_iu_rte_pc_sel, had_yy_xx_exit_dbg, hs_split_iu_unstack_chgflw, ifu_iu_ibus_idle, ifu_iu_spcu_retire_mask, ifu_iu_xx_ibus_data, iu_ifu_addr, iu_ifu_data_fetch, iu_ifu_data_fetch_for_data, iu_ifu_inst_fetch, iu_ifu_inst_fetch_for_data, iu_ifu_inst_fetch_without_dbg_disable, iu_yy_xx_flush, iu_yy_xx_retire, misc_clk, nie_flush_chgflw, pad_yy_gate_clk_en_b, pad_yy_test_mode, pcgen_ctrl_stall, pcgen_retire_updt_pc, pcgen_top_abort_clk_en, pcgen_vector_expt_taken, pcgen_xx_cur_pc, pcgen_xx_ibus_idle, randclk_pcgen_mod_en_w32, retire_branch_stall, retire_pcgen_curpc_update, retire_xx_normal_retire, special_pcgen_chgflw_vld, vector_pcgen_buf_vbr, vector_pcgen_chgflw_vld, vector_pcgen_cur_pc_vld, vector_pcgen_enter_addr, vector_pcgen_ibus_req, wb_pcgen_ldst_stall, wb_pcgen_pc_updt_val, wb_pcgen_switch_ld_pc, wb_retire_fast_retire_load_pc ); input [30:0] branch_pcgen_add_pc; input branch_pcgen_br_chgflw_vld; input branch_pcgen_br_chgflw_vld_for_data; input branch_pcgen_br_pc_chgflw_vld; input branch_pcgen_branch_chgflw_vld_for_data; input branch_pcgen_jmp_chgflw_vld_for_data; input [30:0] branch_pcgen_reg_pc; input [30:0] cp0_iu_epc_for_chgflw; input cp0_iu_flush_chgflw_vld; input cp0_iu_rte_chgflw_vld; input cp0_iu_rte_chgflw_vld_for_data; input cp0_yy_clk_en; input cpurst_b; input forever_cpuclk; input [30:0] had_iu_pc; input had_iu_rte_pc_sel; input had_yy_xx_exit_dbg; input hs_split_iu_unstack_chgflw; input ifu_iu_ibus_idle; input ifu_iu_spcu_retire_mask; input [31:0] ifu_iu_xx_ibus_data; input iu_yy_xx_flush; input iu_yy_xx_retire; input misc_clk; input nie_flush_chgflw; input pad_yy_gate_clk_en_b; input pad_yy_test_mode; input randclk_pcgen_mod_en_w32; input retire_branch_stall; input retire_pcgen_curpc_update; input retire_xx_normal_retire; input special_pcgen_chgflw_vld; input vector_pcgen_buf_vbr; input vector_pcgen_chgflw_vld; input vector_pcgen_cur_pc_vld; input [30:0] vector_pcgen_enter_addr; input vector_pcgen_ibus_req; input wb_pcgen_ldst_stall; input [30:0] wb_pcgen_pc_updt_val; input wb_pcgen_switch_ld_pc; input [30:0] wb_retire_fast_retire_load_pc; output [30:0] iu_ifu_addr; output iu_ifu_data_fetch; output iu_ifu_data_fetch_for_data; output iu_ifu_inst_fetch; output iu_ifu_inst_fetch_for_data; output iu_ifu_inst_fetch_without_dbg_disable; output pcgen_ctrl_stall; output [30:0] pcgen_retire_updt_pc; output pcgen_top_abort_clk_en; output pcgen_vector_expt_taken; output [30:0] pcgen_xx_cur_pc; output pcgen_xx_ibus_idle; reg cur_state; reg fetch_cur_state; reg fetch_next_state; reg next_state; reg [30:0] pcgen_cur_pc; wire [30:0] bctm_pcgen_chgflw_pc; wire bctm_pcgen_chk_chgflw_vld; wire bctm_pcgen_chk_fail_pc_vld; wire bctm_pcgen_jmp_chgflw_vld; wire bctm_pcgen_jmp_chgflw_vld_for_data; wire [30:0] branch_pcgen_add_pc; wire branch_pcgen_br_chgflw_vld; wire branch_pcgen_br_chgflw_vld_for_data; wire branch_pcgen_br_pc_chgflw_vld; wire branch_pcgen_branch_chgflw_vld_for_data; wire branch_pcgen_jmp_chgflw_vld_for_data; wire [30:0] branch_pcgen_reg_pc; wire [30:0] cp0_iu_epc_for_chgflw; wire cp0_iu_flush_chgflw_vld; wire cp0_iu_rte_chgflw_vld; wire cp0_iu_rte_chgflw_vld_for_data; wire cp0_yy_clk_en; wire cpurst_b; wire curpc_10_0_clk; wire curpc_10_0_clk_en; wire curpc_30_11_clk; wire curpc_30_11_clk_en; wire curpc_sel_from_wb; wire curpc_sel_not_hs; wire forever_cpuclk; wire [30:0] had_iu_pc; wire had_iu_rte_pc_sel; wire had_yy_xx_exit_dbg; wire hs_split_iu_unstack_chgflw; wire ifu_iu_ibus_idle; wire ifu_iu_spcu_retire_mask; wire [31:0] ifu_iu_xx_ibus_data; wire inst_fetch_mask; wire [30:0] iu_ifu_addr; wire iu_ifu_data_fetch; wire iu_ifu_data_fetch_for_data; wire iu_ifu_inst_fetch; wire iu_ifu_inst_fetch_for_data; wire iu_ifu_inst_fetch_without_dbg_disable; wire iu_yy_xx_flush; wire iu_yy_xx_retire; wire misc_clk; wire nie_flush_chgflw; wire pad_yy_gate_clk_en_b; wire pad_yy_test_mode; wire pcgen_abort_chgflw_vld; wire pcgen_abort_chgflw_vld_for_data; wire [30:0] pcgen_addr_after_bctm; wire [30:0] pcgen_addr_chgflw_asap; wire [30:0] pcgen_addr_chgflw_delay; wire [30:0] pcgen_addr_except_chgflw_delay; wire pcgen_address_add; wire pcgen_address_cur; wire pcgen_address_epc; wire pcgen_address_had; wire pcgen_address_ibus; wire pcgen_address_inc; wire pcgen_address_reg; wire pcgen_address_svbr; wire pcgen_address_vec; wire pcgen_chfglw_asap_vld_for_data; wire pcgen_chgflw_asap_vld; wire pcgen_chgflw_delay_sel; wire pcgen_ctrl_stall; wire [30:0] pcgen_cur_pc_next_val; wire [30:0] pcgen_cur_pc_next_val_before_hs; wire pcgen_cur_pc_updt_vld; wire pcgen_cur_pc_updt_vld_by_inst; wire pcgen_cur_pc_updt_vld_chgflw; wire pcgen_cur_pc_updt_vld_normal; wire pcgen_cur_pc_updt_vld_not_by_inst; wire pcgen_fetch_mask_trig; wire pcgen_idle_chgflw_vld; wire pcgen_idle_chgflw_vld_for_data; wire [30:0] pcgen_increase_pc; wire pcgen_inst_fetch; wire [30:0] pcgen_retire_updt_pc; wire pcgen_top_abort_clk_en; wire pcgen_vector_expt_taken; wire pcgen_wait_idle_trig; wire [30:0] pcgen_xx_cur_pc; wire pcgen_xx_ibus_idle; wire randclk_pcgen_mod_en_w32; wire retire_branch_stall; wire retire_pcgen_curpc_update; wire retire_xx_normal_retire; wire special_pcgen_chgflw_vld; wire vector_pcgen_buf_vbr; wire vector_pcgen_chgflw_vld; wire vector_pcgen_cur_pc_vld; wire [30:0] vector_pcgen_enter_addr; wire vector_pcgen_ibus_req; wire wb_pcgen_ldst_stall; wire [30:0] wb_pcgen_pc_updt_val; wire wb_pcgen_switch_ld_pc; wire [30:0] wb_retire_fast_retire_load_pc; parameter IDLE = 1'b0; parameter WAIT_IDLE = 1'b1; parameter FETCH_IDLE = 1'b0; parameter FETCH_MASK = 1'b1; parameter EMMU_IDLE = 1'b0; parameter EMMU_WAIT_IDLE = 1'b1; assign pcgen_top_abort_clk_en = pcgen_wait_idle_trig || pcgen_fetch_mask_trig || (cur_state != IDLE) || (fetch_cur_state != FETCH_IDLE); assign curpc_10_0_clk_en = pcgen_cur_pc_updt_vld; gated_clk_cell x_curpc_gated_clk ( .clk_in (forever_cpuclk ), .clk_out (curpc_10_0_clk ), .external_en (1'b0 ), .global_en (cp0_yy_clk_en ), .local_en (curpc_10_0_clk_en ), .module_en (randclk_pcgen_mod_en_w32), .pad_yy_gate_clk_en_b (pad_yy_gate_clk_en_b ), .pad_yy_test_mode (pad_yy_test_mode ) ); assign curpc_30_11_clk_en = pcgen_cur_pc_updt_vld_chgflw || pcgen_cur_pc_updt_vld_normal && (pcgen_cur_pc[11] ^ pcgen_cur_pc_next_val[11]); gated_clk_cell x_curpc_30_11_gated_clk ( .clk_in (forever_cpuclk ), .clk_out (curpc_30_11_clk ), .external_en (1'b0 ), .global_en (cp0_yy_clk_en ), .local_en (curpc_30_11_clk_en ), .module_en (randclk_pcgen_mod_en_w32), .pad_yy_gate_clk_en_b (pad_yy_gate_clk_en_b ), .pad_yy_test_mode (pad_yy_test_mode ) ); assign bctm_pcgen_jmp_chgflw_vld = 1'b0; assign bctm_pcgen_jmp_chgflw_vld_for_data = 1'b0; assign bctm_pcgen_chgflw_pc[30:0] = 31'b0; assign bctm_pcgen_chk_fail_pc_vld = 1'b0; assign bctm_pcgen_chk_chgflw_vld = 1'b0; assign pcgen_inst_fetch = branch_pcgen_br_chgflw_vld || cp0_iu_rte_chgflw_vld || cp0_iu_flush_chgflw_vld || had_yy_xx_exit_dbg || vector_pcgen_chgflw_vld || special_pcgen_chgflw_vld || bctm_pcgen_jmp_chgflw_vld || bctm_pcgen_chk_chgflw_vld || hs_split_iu_unstack_chgflw || nie_flush_chgflw; always @(posedge misc_clk or negedge cpurst_b) begin if(!cpurst_b) cur_state <= IDLE; else cur_state <= next_state; end assign pcgen_chgflw_asap_vld = branch_pcgen_br_chgflw_vld; assign pcgen_chfglw_asap_vld_for_data = branch_pcgen_br_chgflw_vld_for_data; assign pcgen_wait_idle_trig = pcgen_inst_fetch && !pcgen_chgflw_asap_vld; always @( cur_state or pcgen_wait_idle_trig or ifu_iu_ibus_idle) begin case(cur_state) IDLE : if(pcgen_wait_idle_trig) next_state = WAIT_IDLE; else next_state = IDLE; WAIT_IDLE : if(ifu_iu_ibus_idle) next_state = IDLE; else next_state = WAIT_IDLE; default : next_state = IDLE; endcase end always @(posedge misc_clk or negedge cpurst_b) begin if(!cpurst_b) fetch_cur_state <= FETCH_IDLE; else if(iu_yy_xx_flush) fetch_cur_state <= FETCH_IDLE; else fetch_cur_state <= fetch_next_state; end assign pcgen_fetch_mask_trig = pcgen_chgflw_asap_vld && !iu_yy_xx_retire; always @( pcgen_fetch_mask_trig or iu_yy_xx_retire or fetch_cur_state) begin case(fetch_cur_state) FETCH_IDLE : if(pcgen_fetch_mask_trig) fetch_next_state = FETCH_MASK; else fetch_next_state = FETCH_IDLE; FETCH_MASK : if(iu_yy_xx_retire) fetch_next_state = FETCH_IDLE; else fetch_next_state = FETCH_MASK; default : fetch_next_state = FETCH_IDLE; endcase end assign inst_fetch_mask = (fetch_cur_state == FETCH_MASK); assign pcgen_xx_ibus_idle = ifu_iu_ibus_idle || inst_fetch_mask; assign pcgen_idle_chgflw_vld = pcgen_chgflw_asap_vld && !inst_fetch_mask; assign pcgen_abort_chgflw_vld = (cur_state == WAIT_IDLE) && ifu_iu_ibus_idle; assign iu_ifu_inst_fetch = pcgen_abort_chgflw_vld || pcgen_idle_chgflw_vld; assign pcgen_idle_chgflw_vld_for_data = pcgen_chfglw_asap_vld_for_data && !inst_fetch_mask; assign pcgen_abort_chgflw_vld_for_data = (cur_state == WAIT_IDLE) && ifu_iu_ibus_idle; assign iu_ifu_inst_fetch_for_data = pcgen_abort_chgflw_vld_for_data || pcgen_idle_chgflw_vld_for_data; assign iu_ifu_inst_fetch_without_dbg_disable = iu_ifu_inst_fetch && !retire_branch_stall && !wb_pcgen_ldst_stall; assign iu_ifu_data_fetch = vector_pcgen_ibus_req; assign iu_ifu_data_fetch_for_data = vector_pcgen_ibus_req; assign pcgen_ctrl_stall = (cur_state == WAIT_IDLE) && !ifu_iu_spcu_retire_mask; assign pcgen_address_had = had_yy_xx_exit_dbg || cp0_iu_rte_chgflw_vld_for_data && had_iu_rte_pc_sel; assign pcgen_address_vec = vector_pcgen_buf_vbr; assign pcgen_address_ibus = vector_pcgen_cur_pc_vld; assign pcgen_address_epc = cp0_iu_rte_chgflw_vld_for_data && !had_iu_rte_pc_sel && !pcgen_address_svbr; assign pcgen_address_add = branch_pcgen_branch_chgflw_vld_for_data && !pcgen_address_svbr; assign pcgen_address_reg = branch_pcgen_jmp_chgflw_vld_for_data && !pcgen_address_svbr; assign pcgen_address_svbr = bctm_pcgen_jmp_chgflw_vld_for_data || bctm_pcgen_chk_fail_pc_vld; assign pcgen_address_inc = !(pcgen_address_add || pcgen_address_reg || pcgen_address_svbr || pcgen_address_cur); assign pcgen_address_cur = (cur_state == WAIT_IDLE) || vector_pcgen_ibus_req; assign pcgen_addr_chgflw_delay[30:0] = {31{pcgen_address_had}} & had_iu_pc[30:0] | {31{pcgen_address_vec}} & vector_pcgen_enter_addr[30:0] | {31{pcgen_address_ibus}} & ifu_iu_xx_ibus_data[31:1] | {31{pcgen_address_epc}} & cp0_iu_epc_for_chgflw[30:0]; assign pcgen_addr_chgflw_asap[30:0] = {31{pcgen_address_add}} & branch_pcgen_add_pc[30:0] | {31{pcgen_address_reg}} & branch_pcgen_reg_pc[30:0] | {31{pcgen_address_inc}} & pcgen_increase_pc[30:0] | {31{pcgen_address_cur}} & pcgen_cur_pc[30:0]; assign pcgen_addr_after_bctm[30:0] = {31{pcgen_address_svbr}} & bctm_pcgen_chgflw_pc[30:0] | {31{!pcgen_address_svbr}} & pcgen_addr_chgflw_asap[30:0]; assign pcgen_addr_except_chgflw_delay[30:0] = pcgen_cur_pc_updt_vld ? pcgen_addr_after_bctm[30:0] : pcgen_cur_pc[30:0]; assign pcgen_retire_updt_pc[30:0] = pcgen_addr_except_chgflw_delay[30:0]; assign pcgen_chgflw_delay_sel = pcgen_cur_pc_updt_vld && (pcgen_address_had || pcgen_address_vec || pcgen_address_ibus || pcgen_address_epc); assign pcgen_cur_pc_next_val_before_hs[30:0] = pcgen_chgflw_delay_sel ? pcgen_addr_chgflw_delay[30:0] : pcgen_addr_except_chgflw_delay[30:0]; assign curpc_sel_from_wb = retire_pcgen_curpc_update && !bctm_pcgen_chk_fail_pc_vld; assign curpc_sel_not_hs = !curpc_sel_from_wb && !wb_pcgen_switch_ld_pc; assign pcgen_cur_pc_next_val[30:0] = {31{curpc_sel_from_wb}} & wb_retire_fast_retire_load_pc[30:0] | {31{wb_pcgen_switch_ld_pc}} & wb_pcgen_pc_updt_val[30:0] | {31{curpc_sel_not_hs}} & pcgen_cur_pc_next_val_before_hs[30:0]; assign iu_ifu_addr[30:0] = pcgen_addr_chgflw_asap[30:0]; assign pcgen_cur_pc_updt_vld_not_by_inst = had_yy_xx_exit_dbg || vector_pcgen_cur_pc_vld || vector_pcgen_buf_vbr || bctm_pcgen_chk_fail_pc_vld || retire_pcgen_curpc_update || wb_pcgen_switch_ld_pc; assign pcgen_cur_pc_updt_vld_by_inst = branch_pcgen_br_pc_chgflw_vld || cp0_iu_rte_chgflw_vld || bctm_pcgen_jmp_chgflw_vld; assign pcgen_cur_pc_updt_vld_normal = retire_xx_normal_retire; assign pcgen_cur_pc_updt_vld_chgflw = pcgen_cur_pc_updt_vld_not_by_inst || pcgen_cur_pc_updt_vld_by_inst; assign pcgen_cur_pc_updt_vld = pcgen_cur_pc_updt_vld_not_by_inst || pcgen_cur_pc_updt_vld_normal; always @(posedge curpc_10_0_clk or negedge cpurst_b) begin if(!cpurst_b) pcgen_cur_pc[10:0] <= 11'b0; else pcgen_cur_pc[10:0] <= pcgen_cur_pc_next_val[10:0]; end always @(posedge curpc_30_11_clk or negedge cpurst_b) begin if(!cpurst_b) pcgen_cur_pc[30:11] <= 20'b0; else pcgen_cur_pc[30:11] <= pcgen_cur_pc_next_val[30:11]; end assign pcgen_xx_cur_pc[30:0] = pcgen_cur_pc[30:0]; assign pcgen_increase_pc[30:0] = branch_pcgen_add_pc[30:0]; assign pcgen_vector_expt_taken = (cur_state==IDLE); endmodule module cr_iu_randclk( randclk_mad_mod_en_w2, randclk_oper_gpr_mod_en_w32, randclk_pcgen_mod_en_w32, randclk_retire_mod_en_w2, randclk_wb_buf_mod_en_w32, randclk_wb_ctrl_mod_en_w2, randclk_wb_idx_mod_en_w5 ); output randclk_mad_mod_en_w2; output [20:0] randclk_oper_gpr_mod_en_w32; output randclk_pcgen_mod_en_w32; output randclk_retire_mod_en_w2; output randclk_wb_buf_mod_en_w32; output randclk_wb_ctrl_mod_en_w2; output randclk_wb_idx_mod_en_w5; wire randclk_mad_mod_en_w2; wire [20:0] randclk_oper_gpr_mod_en_w32; wire randclk_pcgen_mod_en_w32; wire randclk_retire_mod_en_w2; wire randclk_wb_buf_mod_en_w32; wire randclk_wb_ctrl_mod_en_w2; wire randclk_wb_idx_mod_en_w5; assign randclk_mad_mod_en_w2 = 1'b0; assign randclk_oper_gpr_mod_en_w32[20:0] = 21'b0; assign randclk_pcgen_mod_en_w32 = 1'b0; assign randclk_retire_mod_en_w2 = 1'b0; assign randclk_wb_buf_mod_en_w32 = 1'b0; assign randclk_wb_ctrl_mod_en_w2 = 1'b0; assign randclk_wb_idx_mod_en_w5 = 1'b0; endmodule module cr_iu_rbus( alu_rbus_data, alu_rbus_data_vld, alu_rbus_req, branch_rbus_data, branch_rbus_data_vld, branch_rbus_req, cp0_iu_data, cp0_iu_data_vld, cp0_iu_expt_vec, cp0_iu_expt_vld, cp0_iu_flush, cp0_iu_req, ctrl_alu_ex_data_sel, ctrl_branch_ex_data_sel, ctrl_cp0_ex_data_sel, ctrl_lsu_ex_data_sel, ctrl_mad_ex_data_sel, ctrl_special_ex_data_sel, ctrl_xx_sp_adjust, decd_xx_unit_special_sel, hs_split_iu_hs_retire_mask, ifu_iu_ex_int_spcu_mask, ifu_iu_ex_rd_reg, lsu_iu_data, lsu_iu_data_vld, lsu_iu_expt_vec, lsu_iu_expt_vld, lsu_iu_fast_retire, lsu_iu_req, lsu_iu_store, mad_alu_data_vld, mad_ctrl_stall, mad_rbus_req, rbus_retire_cmplt, rbus_retire_expt_vec, rbus_retire_expt_vld, rbus_retire_flush, rbus_retire_split_inst, rbus_wb_cmplt, rbus_wb_data, rbus_wb_dst_reg, rbus_wb_inst_cmplt, rbus_wb_load, rbus_wb_store, special_rbus_expt_vec, special_rbus_expt_vld, special_rbus_flush, special_rbus_req, wb_rbus_lsu_vec, wb_rbus_st_aft_load, wb_xx_acc_err_after_retire ); input [31:0] alu_rbus_data; input alu_rbus_data_vld; input alu_rbus_req; input [31:0] branch_rbus_data; input branch_rbus_data_vld; input branch_rbus_req; input [31:0] cp0_iu_data; input cp0_iu_data_vld; input [4 :0] cp0_iu_expt_vec; input cp0_iu_expt_vld; input cp0_iu_flush; input cp0_iu_req; input ctrl_alu_ex_data_sel; input ctrl_branch_ex_data_sel; input ctrl_cp0_ex_data_sel; input ctrl_lsu_ex_data_sel; input ctrl_mad_ex_data_sel; input ctrl_special_ex_data_sel; input ctrl_xx_sp_adjust; input decd_xx_unit_special_sel; input hs_split_iu_hs_retire_mask; input ifu_iu_ex_int_spcu_mask; input [4 :0] ifu_iu_ex_rd_reg; input [31:0] lsu_iu_data; input lsu_iu_data_vld; input [4 :0] lsu_iu_expt_vec; input lsu_iu_expt_vld; input lsu_iu_fast_retire; input lsu_iu_req; input lsu_iu_store; input mad_alu_data_vld; input mad_ctrl_stall; input mad_rbus_req; input [4 :0] special_rbus_expt_vec; input special_rbus_expt_vld; input special_rbus_flush; input special_rbus_req; input [4 :0] wb_rbus_lsu_vec; input wb_rbus_st_aft_load; input wb_xx_acc_err_after_retire; output rbus_retire_cmplt; output [4 :0] rbus_retire_expt_vec; output rbus_retire_expt_vld; output rbus_retire_flush; output rbus_retire_split_inst; output rbus_wb_cmplt; output [31:0] rbus_wb_data; output [4 :0] rbus_wb_dst_reg; output rbus_wb_inst_cmplt; output rbus_wb_load; output rbus_wb_store; wire alu_data_sel; wire [31:0] alu_rbus_data; wire alu_rbus_data_vld; wire alu_rbus_req; wire alu_sel; wire bctm_rbus_flush; wire bctm_rbus_req; wire [31:0] bctm_rbus_wb_data; wire [4 :0] bctm_rbus_wb_reg; wire bctm_rbus_wb_vld; wire [31:0] branch_rbus_data; wire branch_rbus_data_vld; wire branch_rbus_req; wire branch_sel; wire [31:0] cp0_iu_data; wire cp0_iu_data_vld; wire [4 :0] cp0_iu_expt_vec; wire cp0_iu_expt_vld; wire cp0_iu_flush; wire cp0_iu_req; wire cp0_sel; wire ctrl_alu_ex_data_sel; wire ctrl_branch_ex_data_sel; wire ctrl_cp0_ex_data_sel; wire ctrl_lsu_ex_data_sel; wire ctrl_mad_ex_data_sel; wire ctrl_special_ex_data_sel; wire ctrl_xx_sp_adjust; wire decd_xx_unit_special_sel; wire hs_split_iu_hs_retire_mask; wire ifu_iu_ex_int_spcu_mask; wire [4 :0] ifu_iu_ex_rd_reg; wire [31:0] lsu_iu_data; wire lsu_iu_data_vld; wire [4 :0] lsu_iu_expt_vec; wire lsu_iu_expt_vld; wire lsu_iu_fast_retire; wire lsu_iu_flush; wire lsu_iu_req; wire lsu_iu_store; wire lsu_sel; wire mad_alu_data_vld; wire [31:0] mad_alu_rbus_data; wire mad_ctrl_stall; wire mad_data_sel; wire mad_rbus_req; wire mad_sel; wire prgsign_rbus_req; wire prgsign_rbus_secure_violation; wire rbus_cmplt; wire [31:0] rbus_data; wire [31:0] rbus_data_expt_lsu; wire [31:0] rbus_data_expt_lsu_without_pol; wire rbus_data_sel_alu; wire rbus_data_sel_branch; wire rbus_data_sel_cp0; wire rbus_data_sel_lsu; wire rbus_data_sel_mad; wire rbus_retire_cmplt; wire rbus_retire_data_vld; wire [4 :0] rbus_retire_expt_vec; wire [4 :0] rbus_retire_expt_vec_aft_prgsign; wire [4 :0] rbus_retire_expt_vec_pre; wire rbus_retire_expt_vld; wire rbus_retire_expt_vld_pre; wire rbus_retire_flush; wire rbus_retire_split_inst; wire rbus_wb_cmplt; wire [31:0] rbus_wb_data; wire [4 :0] rbus_wb_dst_reg; wire rbus_wb_inst_cmplt; wire rbus_wb_load; wire rbus_wb_store; wire rbus_write_back_cmplt; wire [4 :0] special_rbus_expt_vec; wire special_rbus_expt_vld; wire special_rbus_flush; wire special_rbus_req; wire special_sel; wire [4 :0] wb_rbus_lsu_vec; wire wb_rbus_st_aft_load; wire wb_xx_acc_err_after_retire; assign bctm_rbus_req = 1'b0; assign bctm_rbus_flush = 1'b0; assign bctm_rbus_wb_vld = 1'b0; assign bctm_rbus_wb_data[31:0] = 32'b0; assign bctm_rbus_wb_reg[4:0] = 5'b0; assign lsu_iu_flush = 1'b0; assign branch_sel = ctrl_branch_ex_data_sel; assign cp0_sel = ctrl_cp0_ex_data_sel && !decd_xx_unit_special_sel; assign special_sel = ctrl_special_ex_data_sel || decd_xx_unit_special_sel; assign lsu_sel = ctrl_lsu_ex_data_sel && !decd_xx_unit_special_sel; assign alu_sel = (ctrl_alu_ex_data_sel || ctrl_mad_ex_data_sel) && !decd_xx_unit_special_sel; assign alu_data_sel= ctrl_alu_ex_data_sel || ctrl_mad_ex_data_sel; assign mad_sel = ctrl_mad_ex_data_sel; assign mad_data_sel= 1'b0; assign mad_alu_rbus_data[31:0] = 32'b0; assign prgsign_rbus_req = 1'b0; assign prgsign_rbus_secure_violation = 1'b0; assign rbus_cmplt = alu_rbus_req || mad_rbus_req || lsu_iu_req || special_rbus_req || cp0_iu_req || branch_rbus_req || bctm_rbus_req || prgsign_rbus_req; assign rbus_retire_cmplt = rbus_cmplt && !hs_split_iu_hs_retire_mask && !ifu_iu_ex_int_spcu_mask; assign rbus_retire_flush = cp0_iu_req && cp0_iu_flush || bctm_rbus_req && bctm_rbus_flush || special_rbus_req && special_rbus_flush || lsu_iu_req && lsu_iu_flush; assign rbus_data_sel_branch = ctrl_branch_ex_data_sel && branch_rbus_data_vld && !bctm_rbus_wb_vld; assign rbus_data_sel_cp0 = ctrl_cp0_ex_data_sel && !bctm_rbus_wb_vld; assign rbus_data_sel_mad = mad_data_sel && !bctm_rbus_wb_vld; assign rbus_data_sel_alu = alu_data_sel && !bctm_rbus_wb_vld; assign rbus_data_expt_lsu_without_pol[31:0] = {32{bctm_rbus_wb_vld}} & bctm_rbus_wb_data[31:0] | {32{rbus_data_sel_branch}} & branch_rbus_data[31:0] | {32{rbus_data_sel_cp0}} & cp0_iu_data[31:0] | {32{rbus_data_sel_mad}} & mad_alu_rbus_data[31:0] | {32{rbus_data_sel_alu}} & alu_rbus_data[31:0]; assign rbus_data[31:0] = {32{!rbus_data_sel_lsu}} & rbus_data_expt_lsu[31:0] | {32{rbus_data_sel_lsu}} & lsu_iu_data[31:0]; assign rbus_data_expt_lsu[31:0] = rbus_data_expt_lsu_without_pol[31:0]; assign rbus_data_sel_lsu = (ctrl_lsu_ex_data_sel || wb_rbus_st_aft_load) && !bctm_rbus_wb_vld && !ctrl_xx_sp_adjust; assign rbus_retire_data_vld = alu_sel && alu_rbus_data_vld || mad_sel && mad_alu_data_vld || lsu_sel && lsu_iu_data_vld || cp0_sel && cp0_iu_data_vld || branch_sel && branch_rbus_data_vld; assign rbus_retire_expt_vld_pre = lsu_sel && lsu_iu_expt_vld || special_sel && special_rbus_expt_vld || cp0_sel && cp0_iu_expt_vld; assign rbus_retire_expt_vec_pre[4:0] = {5{lsu_sel}} & lsu_iu_expt_vec[4:0] | {5{special_sel}} & special_rbus_expt_vec[4:0] | {5{cp0_sel}} & cp0_iu_expt_vec[4:0]; assign rbus_retire_expt_vld = rbus_retire_expt_vld_pre || wb_xx_acc_err_after_retire || prgsign_rbus_secure_violation; assign rbus_retire_expt_vec_aft_prgsign[4:0] = prgsign_rbus_secure_violation ? 5'b01000 : rbus_retire_expt_vec_pre[4:0]; assign rbus_retire_expt_vec[4:0] = wb_xx_acc_err_after_retire ? wb_rbus_lsu_vec[4:0] : rbus_retire_expt_vec_aft_prgsign[4:0]; assign rbus_retire_split_inst = mad_ctrl_stall; assign rbus_wb_dst_reg[4:0] = (bctm_rbus_wb_vld) ? bctm_rbus_wb_reg[4:0] : ifu_iu_ex_rd_reg[4:0]; assign rbus_wb_data[31:0] = rbus_data[31:0]; assign rbus_write_back_cmplt = rbus_cmplt && rbus_retire_data_vld; assign rbus_wb_load = !lsu_iu_store && lsu_iu_fast_retire; assign rbus_wb_store = lsu_iu_store && lsu_iu_fast_retire; assign rbus_wb_cmplt = rbus_write_back_cmplt || bctm_rbus_wb_vld; assign rbus_wb_inst_cmplt = rbus_cmplt; endmodule module cr_iu_retire( clic_cpu_int_hv, clic_cpu_int_id, clic_cpu_int_il, clic_cpu_int_priv, clk_en, cp0_iu_dbg_disable_for_tee, cp0_iu_il, cp0_iu_meie, cp0_iu_mie_for_int, cp0_iu_vec_mode, cp0_yy_clk_en, cpurst_b, ctrl_branch_ex_sel, ctrl_retire_ni_vld, decd_retire_cp0_inst, decd_retire_inst_mret, forever_cpuclk, had_core_dbg_mode_req, had_iu_bkpt_trace_en, had_iu_dr_set_req, had_iu_force_dbg_en, had_iu_int_vld, had_iu_mbkpt_fsm_index_mbee, had_iu_mem_bkpt_exp_req, had_iu_mem_bkpt_mask, had_iu_mem_bkpt_req, had_iu_rte_pc_sel, had_iu_trace_req, had_iu_trace_req_for_dbg_disable, had_iu_xx_fdb, had_iu_xx_jdbreq, had_yy_xx_exit_dbg, hs_split_iu_hs_retire_mask, hs_split_iu_hs_switch_se, ifu_iu_ex_inst_dbg_disable, ifu_iu_ex_sp_oper, ifu_iu_ex_split_on, ifu_iu_ibus_idle, ifu_iu_inst_bkpt_dbg_occur_vld, ifu_iu_inst_bkpt_dbgexp_occur_vld, ifu_iu_inst_buf_inst_dbg_disable, ifu_iu_inst_buf_inst_vld, iu_cp0_epc, iu_cp0_epc_update, iu_cp0_expt_vld, iu_cp0_int_vld, iu_cp0_lp_wk_int, iu_cp0_mtval_updt_vld, iu_cp0_nt_int_pending_vld, iu_had_adr_dbg_ack, iu_had_data_bkpt_occur_vld, iu_had_dbg_disable_for_tee, iu_had_dr_dbg_ack, iu_had_expt_vld, iu_had_fast_retire_acc_err_pc_update, iu_had_fast_retire_acc_err_pc_val, iu_had_inst_bkpt_occur_vld, iu_had_int_ack, iu_had_retire_with_had_int, iu_had_trace_occur_vld, iu_had_xx_bkpt_inst, iu_had_xx_dbg_ack, iu_had_xx_mldst, iu_had_xx_retire, iu_had_xx_retire_normal, iu_had_xx_retire_pc, iu_ifu_kill_inst, iu_ifu_spcu_int_en, iu_pad_inst_retire, iu_pad_inst_split, iu_pad_retire_pc, iu_sys_lp_wk_int, iu_yy_xx_dbgon, iu_yy_xx_expt_vec, iu_yy_xx_flush, iu_yy_xx_int_hv, iu_yy_xx_int_il, iu_yy_xx_int_pending_hv, iu_yy_xx_int_pending_id, iu_yy_xx_int_pending_il, iu_yy_xx_int_pending_priv, iu_yy_xx_reg_rst_b, iu_yy_xx_retire, lsu_iu_wb_acc_err, lsu_iu_wb_cmplt, nie_flush_chgflw, pad_cpu_ext_int_b, pad_yy_gate_clk_en_b, pad_yy_test_mode, pcgen_retire_updt_pc, pcgen_xx_cur_pc, randclk_retire_mod_en_w2, rbus_retire_cmplt, rbus_retire_expt_vec, rbus_retire_expt_vld, rbus_retire_flush, rbus_retire_split_inst, rbus_wb_load, rbus_wb_store, retire_branch_stall, retire_mad_ex_cancel, retire_pcgen_curpc_update, retire_vector_expt_int_hv, retire_vector_expt_vld, retire_wb_dbg_in_ack, retire_wb_hs_err_epc_sel, retire_wb_mem_bkpt_fast_retire, retire_xx_normal_retire, special_retire_inst_wsc, wb_retire_fast_retire_load_pc, wb_xx_acc_err_after_retire, wb_xx_lsu_check_fail_after_retire ); input clic_cpu_int_hv; input [9 :0] clic_cpu_int_id; input [7 :0] clic_cpu_int_il; input [1 :0] clic_cpu_int_priv; input clk_en; input cp0_iu_dbg_disable_for_tee; input [7 :0] cp0_iu_il; input cp0_iu_meie; input cp0_iu_mie_for_int; input [1 :0] cp0_iu_vec_mode; input cp0_yy_clk_en; input cpurst_b; input ctrl_branch_ex_sel; input ctrl_retire_ni_vld; input decd_retire_cp0_inst; input decd_retire_inst_mret; input forever_cpuclk; input had_core_dbg_mode_req; input had_iu_bkpt_trace_en; input had_iu_dr_set_req; input had_iu_force_dbg_en; input had_iu_int_vld; input had_iu_mbkpt_fsm_index_mbee; input had_iu_mem_bkpt_exp_req; input had_iu_mem_bkpt_mask; input had_iu_mem_bkpt_req; input had_iu_rte_pc_sel; input had_iu_trace_req; input had_iu_trace_req_for_dbg_disable; input had_iu_xx_fdb; input had_iu_xx_jdbreq; input had_yy_xx_exit_dbg; input hs_split_iu_hs_retire_mask; input hs_split_iu_hs_switch_se; input ifu_iu_ex_inst_dbg_disable; input ifu_iu_ex_sp_oper; input ifu_iu_ex_split_on; input ifu_iu_ibus_idle; input ifu_iu_inst_bkpt_dbg_occur_vld; input ifu_iu_inst_bkpt_dbgexp_occur_vld; input ifu_iu_inst_buf_inst_dbg_disable; input ifu_iu_inst_buf_inst_vld; input iu_yy_xx_reg_rst_b; input lsu_iu_wb_acc_err; input lsu_iu_wb_cmplt; input pad_cpu_ext_int_b; input pad_yy_gate_clk_en_b; input pad_yy_test_mode; input [30:0] pcgen_retire_updt_pc; input [30:0] pcgen_xx_cur_pc; input randclk_retire_mod_en_w2; input rbus_retire_cmplt; input [4 :0] rbus_retire_expt_vec; input rbus_retire_expt_vld; input rbus_retire_flush; input rbus_retire_split_inst; input rbus_wb_load; input rbus_wb_store; input special_retire_inst_wsc; input [30:0] wb_retire_fast_retire_load_pc; input wb_xx_acc_err_after_retire; input wb_xx_lsu_check_fail_after_retire; output [30:0] iu_cp0_epc; output iu_cp0_epc_update; output iu_cp0_expt_vld; output iu_cp0_int_vld; output iu_cp0_lp_wk_int; output iu_cp0_mtval_updt_vld; output iu_cp0_nt_int_pending_vld; output iu_had_adr_dbg_ack; output iu_had_data_bkpt_occur_vld; output iu_had_dbg_disable_for_tee; output iu_had_dr_dbg_ack; output iu_had_expt_vld; output iu_had_fast_retire_acc_err_pc_update; output [30:0] iu_had_fast_retire_acc_err_pc_val; output iu_had_inst_bkpt_occur_vld; output iu_had_int_ack; output iu_had_retire_with_had_int; output iu_had_trace_occur_vld; output iu_had_xx_bkpt_inst; output iu_had_xx_dbg_ack; output iu_had_xx_mldst; output iu_had_xx_retire; output iu_had_xx_retire_normal; output [31:0] iu_had_xx_retire_pc; output iu_ifu_kill_inst; output iu_ifu_spcu_int_en; output iu_pad_inst_retire; output iu_pad_inst_split; output [31:0] iu_pad_retire_pc; output iu_sys_lp_wk_int; output iu_yy_xx_dbgon; output [9 :0] iu_yy_xx_expt_vec; output iu_yy_xx_flush; output iu_yy_xx_int_hv; output [7 :0] iu_yy_xx_int_il; output iu_yy_xx_int_pending_hv; output [9 :0] iu_yy_xx_int_pending_id; output [7 :0] iu_yy_xx_int_pending_il; output [1 :0] iu_yy_xx_int_pending_priv; output iu_yy_xx_retire; output nie_flush_chgflw; output retire_branch_stall; output retire_mad_ex_cancel; output retire_pcgen_curpc_update; output retire_vector_expt_int_hv; output retire_vector_expt_vld; output retire_wb_dbg_in_ack; output retire_wb_hs_err_epc_sel; output retire_wb_mem_bkpt_fast_retire; output retire_xx_normal_retire; reg bkpt_cur_state; reg bkpt_next_state; reg [1 :0] br_cur_state; reg [1 :0] br_next_state; reg cpu_ext_int_b; reg dbg_mode_on; reg dbgreq_ack_ff; reg [9 :0] expt_vec; reg retire_ack_expt; reg retire_ack_int; reg retire_with_ack_dbg; reg retire_with_ack_int; reg trace_cur_state; reg trace_next_state; reg wb_split_inst; wire bctm_retire_epc_updt_vld; wire bctm_retire_had_pc_updt_vld; wire bkpt_fsm_trigger; wire clic_cpu_int_hv; wire [9 :0] clic_cpu_int_id; wire [7 :0] clic_cpu_int_il; wire [1 :0] clic_cpu_int_priv; wire clic_int_pending_vld; wire clic_lp_wk_int; wire clic_pending_int_need_ack; wire clint_lp_wk_int; wire clk_en; wire cp0_iu_dbg_disable_for_tee; wire cp0_iu_ee; wire cp0_iu_ic; wire [7 :0] cp0_iu_il; wire cp0_iu_int_spcu_en; wire cp0_iu_meie; wire cp0_iu_mie_for_int; wire [1 :0] cp0_iu_vec_mode; wire cp0_yy_clk_en; wire cpu_int_vld; wire cpurst_b; wire ctrl_branch_ex_sel; wire ctrl_retire_ni_vld; wire dbg_clk; wire dbg_clk_en; wire dbgreq_ack; wire dbgreq_ack_aft_force; wire decd_retire_cp0_inst; wire decd_retire_inst_mret; wire epc_update_after_retire; wire ex_inst_dbg_disable; wire [30:0] fast_retire_acc_err_epc; wire forever_cpuclk; wire had_core_dbg_mode_req; wire had_iu_bkpt_trace_en; wire had_iu_dr_set_req; wire had_iu_force_dbg_en; wire had_iu_int_vld; wire had_iu_mbkpt_fsm_index_mbee; wire had_iu_mem_bkpt_exp_req; wire had_iu_mem_bkpt_mask; wire had_iu_mem_bkpt_req; wire had_iu_rte_pc_sel; wire had_iu_trace_req; wire had_iu_trace_req_for_dbg_disable; wire had_iu_xx_fdb; wire had_iu_xx_jdbreq; wire had_yy_xx_exit_dbg; wire hadpc_update_after_retire; wire hs_split_iu_hs_retire_mask; wire hs_split_iu_hs_switch_se; wire ifu_iu_ex_inst_dbg_disable; wire ifu_iu_ex_sp_oper; wire ifu_iu_ex_split_on; wire ifu_iu_ibus_idle; wire ifu_iu_inst_bkpt_dbg_occur_vld; wire ifu_iu_inst_bkpt_dbgexp_occur_vld; wire ifu_iu_inst_buf_inst_dbg_disable; wire ifu_iu_inst_buf_inst_vld; wire inst_dbg_disable; wire int_cpuclk; wire int_enable_with_ee_ie; wire int_ic_aft_sec_sel; wire int_wakeup_vld; wire intc_cpu_int_vld; wire [30:0] iu_cp0_epc; wire iu_cp0_epc_update; wire iu_cp0_expt_vld; wire iu_cp0_int_vld; wire iu_cp0_lp_wk_int; wire iu_cp0_mtval_updt_vld; wire iu_cp0_nt_int_pending_vld; wire iu_had_adr_dbg_ack; wire iu_had_data_bkpt_occur_vld; wire iu_had_dbg_disable_for_tee; wire iu_had_dr_dbg_ack; wire iu_had_expt_vld; wire iu_had_fast_retire_acc_err_pc_update; wire [30:0] iu_had_fast_retire_acc_err_pc_val; wire iu_had_inst_bkpt_occur_vld; wire iu_had_int_ack; wire iu_had_retire_with_had_int; wire iu_had_trace_occur_vld; wire iu_had_xx_bkpt_inst; wire iu_had_xx_dbg_ack; wire iu_had_xx_mldst; wire iu_had_xx_retire; wire iu_had_xx_retire_normal; wire [31:0] iu_had_xx_retire_pc; wire iu_ifu_kill_inst; wire iu_ifu_spcu_int_en; wire iu_pad_inst_retire; wire iu_pad_inst_split; wire [31:0] iu_pad_retire_pc; wire iu_sys_lp_wk_int; wire iu_yy_xx_dbgon; wire [9 :0] iu_yy_xx_expt_vec; wire iu_yy_xx_flush; wire iu_yy_xx_int_hv; wire [7 :0] iu_yy_xx_int_il; wire iu_yy_xx_int_pending_hv; wire [9 :0] iu_yy_xx_int_pending_id; wire [7 :0] iu_yy_xx_int_pending_il; wire [1 :0] iu_yy_xx_int_pending_priv; wire iu_yy_xx_reg_rst_b; wire iu_yy_xx_retire; wire load_store_fast_retire; wire lsu_iu_wb_acc_err; wire lsu_iu_wb_cmplt; wire nie_flush; wire nie_flush_chgflw; wire pad_cpu_ext_int_b; wire pad_yy_gate_clk_en_b; wire pad_yy_test_mode; wire [30:0] pcgen_retire_updt_pc; wire [30:0] pcgen_xx_cur_pc; wire randclk_retire_mod_en_w2; wire rbus_flush; wire rbus_retire_cmplt; wire [4 :0] rbus_retire_expt_vec; wire rbus_retire_expt_vld; wire rbus_retire_flush; wire rbus_retire_split_inst; wire rbus_wb_load; wire rbus_wb_store; wire retire_ack_bkpt; wire retire_ack_dr_set_req; wire retire_ack_expt_vld; wire retire_ack_int_vld; wire retire_ack_jdbreq; wire retire_ack_mem_bkpt_fast_retire; wire retire_ack_mem_bkpt_req; wire retire_ack_mem_bkpt_vld; wire retire_ack_mem_bkpt_vld_idle; wire retire_ack_trace_fast_retire; wire retire_ack_trace_req; wire retire_ack_trace_vld; wire retire_ack_trace_vld_idle; wire retire_branch_dbg_idle; wire retire_branch_stall; wire retire_dbg_disable; wire retire_dbg_disable_pre; wire retire_dbg_expt; wire retire_dbg_mask; wire [30:0] retire_epc_or_hadpc; wire retire_expt_int_vld; wire retire_expt_vld; wire retire_hs_acc_err; wire retire_hs_err_epc_sel; wire retire_inst_expt; wire retire_int; wire retire_int_mask_from_had; wire retire_int_vld; wire retire_mad_ex_cancel; wire retire_pc_expt_vld; wire retire_pcgen_curpc_update; wire retire_split_inst_no_dbg; wire retire_split_inst_no_dbg_for_pad; wire retire_split_inst_with_dbg_ack; wire retire_vector_expt_int_hv; wire retire_vector_expt_vld; wire retire_wb_dbg_in_ack; wire retire_wb_hs_err_epc_sel; wire retire_wb_mem_bkpt_fast_retire; wire retire_with_ack_had_int; wire retire_with_ack_vic_int; wire retire_xx_normal_retire; wire sec_retire_flush; wire soft_reset_vld; wire special_retire_inst_wsc; wire wb_dbg_exp_after_retire; wire [30:0] wb_retire_fast_retire_load_pc; wire wb_split_inst_clk_en; wire wb_xx_acc_err_after_retire; wire wb_xx_lsu_check_fail_after_retire; assign cp0_iu_ee = 1'b1; assign cp0_iu_int_spcu_en = 1'b0; assign dbg_clk_en = dbgreq_ack_aft_force || dbg_mode_on || dbgreq_ack_ff || retire_int_vld || retire_with_ack_int || retire_with_ack_dbg || wb_split_inst_clk_en || had_iu_mem_bkpt_req || had_iu_trace_req || had_iu_trace_req_for_dbg_disable || retire_wb_dbg_in_ack || had_iu_mem_bkpt_exp_req; gated_clk_cell x_dbg_gated_clk ( .clk_in (forever_cpuclk ), .clk_out (dbg_clk ), .external_en (1'b0 ), .global_en (cp0_yy_clk_en ), .local_en (dbg_clk_en ), .module_en (randclk_retire_mod_en_w2), .pad_yy_gate_clk_en_b (pad_yy_gate_clk_en_b ), .pad_yy_test_mode (pad_yy_test_mode ) ); assign iu_yy_xx_retire = rbus_retire_cmplt; gated_clk_cell x_ext_int_gated_cell ( .clk_in (forever_cpuclk ), .clk_out (int_cpuclk ), .external_en (1'b0 ), .global_en (1'b1 ), .local_en (1'b0 ), .module_en (int_wakeup_vld ), .pad_yy_gate_clk_en_b (pad_yy_gate_clk_en_b), .pad_yy_test_mode (pad_yy_test_mode ) ); assign int_wakeup_vld = clk_en && (!(pad_cpu_ext_int_b && cpu_ext_int_b)); always@ (posedge int_cpuclk or negedge cpurst_b) begin if(!cpurst_b) begin cpu_ext_int_b <= 1'b1; end else if(clk_en) begin cpu_ext_int_b <= pad_cpu_ext_int_b; end end assign cpu_int_vld = cp0_iu_vec_mode[1] ? clic_pending_int_need_ack : intc_cpu_int_vld && (int_enable_with_ee_ie); assign clic_pending_int_need_ack = clic_int_pending_vld && ( (int_enable_with_ee_ie && (clic_cpu_int_il[7:0] > cp0_iu_il[7:0]))); assign clic_int_pending_vld = |clic_cpu_int_il[7:0]; assign clint_lp_wk_int = !cpu_ext_int_b && cp0_iu_meie; assign iu_cp0_nt_int_pending_vld = !cpu_ext_int_b; assign iu_yy_xx_int_pending_priv[1:0] = clic_cpu_int_priv[1:0]; assign iu_yy_xx_int_pending_hv = clic_cpu_int_hv; assign iu_yy_xx_int_pending_il[7:0] = clic_cpu_int_il[7:0]; assign iu_yy_xx_int_pending_id[9:0] = clic_cpu_int_id[9:0]; assign iu_yy_xx_int_il[7:0] = clic_cpu_int_il[7:0]; assign iu_yy_xx_int_hv = clic_cpu_int_hv; assign iu_cp0_lp_wk_int = cp0_iu_vec_mode[1] ? clic_lp_wk_int : clint_lp_wk_int; assign iu_sys_lp_wk_int = iu_cp0_lp_wk_int; assign clic_lp_wk_int = clic_int_pending_vld ; assign int_enable_with_ee_ie = cp0_iu_mie_for_int; assign intc_cpu_int_vld = !cpu_ext_int_b && cp0_iu_meie; assign int_ic_aft_sec_sel = cp0_iu_ic; assign cp0_iu_ic = 1'b0; assign retire_int = (cpu_int_vld && !had_iu_int_vld || had_iu_int_vld && !decd_retire_cp0_inst ) && !special_retire_inst_wsc && !decd_retire_inst_mret && !had_iu_rte_pc_sel && !(ctrl_retire_ni_vld || wb_xx_acc_err_after_retire) && ( !int_ic_aft_sec_sel && !rbus_retire_split_inst || int_ic_aft_sec_sel); assign retire_inst_expt = rbus_retire_expt_vld; assign retire_dbg_expt = 1'b0; assign iu_ifu_kill_inst = 1'b0; always @( rbus_retire_expt_vec[4:0] or retire_dbg_expt or retire_int or retire_inst_expt or had_iu_int_vld or cp0_iu_vec_mode[1] or clic_cpu_int_id[9:0]) begin expt_vec[9:0] = 10'b0; retire_ack_expt = 1'b0; retire_ack_int = 1'b0; if(retire_dbg_expt) begin retire_ack_expt = 1'b1; expt_vec[9:0] = {7'b0,3'b11}; end else if(retire_int) begin retire_ack_int = 1'b1; expt_vec[9:0] = had_iu_int_vld ? {6'b0,4'b1101} : cp0_iu_vec_mode[1] ? clic_cpu_int_id[9:0] : {6'b0,4'b1011}; end else if(retire_inst_expt) begin retire_ack_expt = 1'b1; expt_vec[9:0] = {5'b0,rbus_retire_expt_vec[4:0]}; end end assign retire_hs_acc_err = 1'b0; assign retire_ack_expt_vld = (retire_ack_expt && iu_yy_xx_retire) || (wb_xx_acc_err_after_retire && !retire_with_ack_int) || wb_dbg_exp_after_retire && cp0_iu_ee; assign retire_ack_int_vld = retire_ack_int && iu_yy_xx_retire; assign retire_expt_vld = retire_ack_expt_vld && (!dbg_mode_on || soft_reset_vld) && !dbgreq_ack_aft_force; assign retire_int_mask_from_had = had_iu_mem_bkpt_mask || had_iu_trace_req; assign retire_int_vld = retire_ack_int_vld && !dbg_mode_on && !dbgreq_ack_aft_force && !retire_int_mask_from_had; assign iu_yy_xx_expt_vec[9:0] = retire_hs_acc_err ? {5'b0,rbus_retire_expt_vec[4:0]}: expt_vec[9:0]; assign retire_expt_int_vld = retire_expt_vld || retire_int_vld; assign retire_split_inst_no_dbg = rbus_retire_split_inst && !(iu_yy_xx_retire && retire_int); assign retire_split_inst_no_dbg_for_pad = rbus_retire_split_inst && !(retire_ack_expt_vld || retire_ack_int_vld); assign retire_split_inst_with_dbg_ack = retire_split_inst_no_dbg_for_pad && !dbgreq_ack_aft_force; assign retire_pc_expt_vld = retire_inst_expt && !dbg_mode_on; assign iu_cp0_expt_vld = retire_expt_int_vld; assign iu_cp0_mtval_updt_vld = retire_expt_int_vld && !special_retire_inst_wsc || retire_hs_acc_err ||(iu_yy_xx_retire && ifu_iu_inst_bkpt_dbg_occur_vld) || retire_ack_mem_bkpt_req || retire_ack_mem_bkpt_fast_retire; assign retire_wb_mem_bkpt_fast_retire = retire_ack_mem_bkpt_fast_retire; assign iu_cp0_int_vld = retire_int_vld; assign iu_ifu_spcu_int_en = retire_int_vld && !had_iu_bkpt_trace_en && cp0_iu_int_spcu_en; assign retire_vector_expt_vld = retire_expt_int_vld; assign retire_vector_expt_int_hv = retire_ack_int ? cp0_iu_vec_mode[1] && (clic_cpu_int_hv || (cp0_iu_vec_mode[1:0] == 2'b11)) : 1'b0; assign soft_reset_vld = 1'b0; always @(posedge dbg_clk or negedge cpurst_b) begin if(!cpurst_b) retire_with_ack_int <= 1'b0; else if(retire_int_vld) retire_with_ack_int <= 1'b1; else if(iu_yy_xx_retire) retire_with_ack_int <= 1'b0; end always @(posedge dbg_clk or negedge cpurst_b) begin if(!cpurst_b) retire_with_ack_dbg <= 1'b0; else if(dbgreq_ack_aft_force) retire_with_ack_dbg <= 1'b1; else if(iu_yy_xx_retire) retire_with_ack_dbg <= 1'b0; end assign retire_with_ack_vic_int = retire_with_ack_int && !had_iu_rte_pc_sel; assign retire_with_ack_had_int = retire_with_ack_int && had_iu_rte_pc_sel; assign bctm_retire_epc_updt_vld = 1'b0; assign bctm_retire_had_pc_updt_vld = 1'b0; assign fast_retire_acc_err_epc[30:0] = wb_retire_fast_retire_load_pc[30:0]; assign retire_hs_err_epc_sel = retire_hs_acc_err && !retire_with_ack_int; assign retire_wb_hs_err_epc_sel = retire_hs_err_epc_sel; assign retire_epc_or_hadpc[30:0] = (wb_xx_acc_err_after_retire && !retire_hs_acc_err || retire_hs_err_epc_sel) ? fast_retire_acc_err_epc[30:0] : pcgen_retire_updt_pc[30:0]; assign iu_cp0_epc[30:0] = retire_epc_or_hadpc[30:0]; assign epc_update_after_retire = wb_xx_acc_err_after_retire && retire_with_ack_vic_int || bctm_retire_epc_updt_vld; assign iu_cp0_epc_update = epc_update_after_retire && !hs_split_iu_hs_retire_mask; assign retire_pcgen_curpc_update = (epc_update_after_retire || hadpc_update_after_retire) && hs_split_iu_hs_retire_mask && !retire_hs_acc_err; assign inst_dbg_disable = 1'b0; assign retire_ack_jdbreq = had_iu_xx_jdbreq && !hs_split_iu_hs_switch_se && !inst_dbg_disable && !retire_dbg_disable; assign retire_dbg_mask = ifu_iu_ex_sp_oper && ifu_iu_ex_split_on; assign retire_ack_dr_set_req = iu_yy_xx_retire && had_iu_dr_set_req && !retire_dbg_mask && !inst_dbg_disable && !had_iu_rte_pc_sel && !retire_dbg_disable; assign retire_ack_bkpt = iu_yy_xx_retire && rbus_retire_expt_vld && (rbus_retire_expt_vec[4:0] == 5'b00011) && (had_iu_xx_fdb || had_core_dbg_mode_req || ifu_iu_inst_bkpt_dbg_occur_vld) && !dbg_mode_on && !inst_dbg_disable && !had_iu_rte_pc_sel && !retire_dbg_disable && !(ifu_iu_inst_bkpt_dbgexp_occur_vld && !ifu_iu_inst_bkpt_dbg_occur_vld); assign retire_ack_mem_bkpt_req = retire_ack_mem_bkpt_vld_idle && had_iu_mem_bkpt_req && !inst_dbg_disable && !had_iu_rte_pc_sel && !retire_dbg_disable; assign retire_ack_mem_bkpt_fast_retire = retire_ack_mem_bkpt_vld && !had_iu_mbkpt_fsm_index_mbee; assign retire_ack_trace_req = retire_ack_trace_vld_idle && had_iu_trace_req && !inst_dbg_disable && !had_iu_rte_pc_sel && !retire_dbg_disable; assign retire_ack_trace_fast_retire = retire_ack_trace_vld; assign dbgreq_ack = retire_ack_jdbreq || retire_ack_bkpt || retire_ack_dr_set_req || retire_ack_mem_bkpt_req || retire_ack_trace_req || retire_ack_mem_bkpt_fast_retire || retire_ack_trace_fast_retire; assign dbgreq_ack_aft_force = dbgreq_ack || had_iu_force_dbg_en; always @(posedge dbg_clk or negedge cpurst_b) begin if(!cpurst_b) dbgreq_ack_ff <= 1'b0; else dbgreq_ack_ff <= dbgreq_ack_aft_force; end assign iu_had_xx_dbg_ack = dbgreq_ack_ff; always @(posedge dbg_clk or negedge cpurst_b) begin if(!cpurst_b) dbg_mode_on <= 1'b0; else if(had_yy_xx_exit_dbg || !iu_yy_xx_reg_rst_b) dbg_mode_on <= 1'b0; else if(dbgreq_ack_aft_force) dbg_mode_on <= 1'b1; else dbg_mode_on <= dbg_mode_on; end assign iu_yy_xx_dbgon = dbg_mode_on; assign iu_had_xx_retire = iu_yy_xx_retire; assign iu_had_xx_retire_pc[31:0] = {pcgen_xx_cur_pc[30:0],1'b0}; assign iu_had_xx_mldst = retire_split_inst_no_dbg; assign iu_had_xx_retire_normal = !rbus_retire_expt_vld; assign iu_had_int_ack = 1'b0; assign iu_had_retire_with_had_int = 1'b0; assign iu_had_dbg_disable_for_tee = cp0_iu_dbg_disable_for_tee; assign iu_had_adr_dbg_ack = retire_ack_jdbreq; assign iu_had_dr_dbg_ack = retire_ack_dr_set_req; assign iu_had_inst_bkpt_occur_vld = retire_ack_bkpt && ifu_iu_inst_bkpt_dbg_occur_vld; assign iu_had_data_bkpt_occur_vld = retire_ack_mem_bkpt_req || retire_ack_mem_bkpt_fast_retire; assign iu_had_xx_bkpt_inst = retire_ack_bkpt && !ifu_iu_inst_bkpt_dbg_occur_vld && !had_core_dbg_mode_req; assign iu_had_trace_occur_vld = retire_ack_trace_req || retire_ack_trace_fast_retire; assign iu_had_expt_vld = retire_expt_int_vld; assign wb_split_inst_clk_en = wb_split_inst ^ retire_split_inst_no_dbg; always @(posedge dbg_clk or negedge cpurst_b) begin if(!cpurst_b) wb_split_inst <= 1'b0; else if(iu_yy_xx_retire) wb_split_inst <= retire_split_inst_no_dbg; end assign hadpc_update_after_retire = wb_xx_acc_err_after_retire && (retire_with_ack_dbg || retire_with_ack_had_int) || bctm_retire_had_pc_updt_vld; assign iu_had_fast_retire_acc_err_pc_update = hadpc_update_after_retire && !retire_hs_acc_err; assign iu_had_fast_retire_acc_err_pc_val[30:0] = retire_epc_or_hadpc[30:0]; assign load_store_fast_retire = rbus_wb_load || rbus_wb_store; parameter BKPT_IDLE = 1'b0; parameter BKPT_ACK = 1'b1; always @(posedge dbg_clk or negedge cpurst_b) begin if(!cpurst_b) bkpt_cur_state <= BKPT_IDLE; else bkpt_cur_state <= bkpt_next_state; end assign bkpt_fsm_trigger = (had_iu_mem_bkpt_req || had_iu_mem_bkpt_exp_req) && load_store_fast_retire && !ex_inst_dbg_disable && !had_iu_rte_pc_sel; always @( bkpt_cur_state or bkpt_fsm_trigger or lsu_iu_wb_cmplt) begin case(bkpt_cur_state) BKPT_IDLE : if(bkpt_fsm_trigger) bkpt_next_state = BKPT_ACK; else bkpt_next_state = BKPT_IDLE; BKPT_ACK : if(lsu_iu_wb_cmplt) bkpt_next_state = BKPT_IDLE; else bkpt_next_state = BKPT_ACK; default : bkpt_next_state = BKPT_IDLE; endcase end assign retire_ack_mem_bkpt_vld_idle = (bkpt_cur_state == BKPT_IDLE) && !load_store_fast_retire; assign retire_ack_mem_bkpt_vld = (bkpt_cur_state == BKPT_ACK) && lsu_iu_wb_cmplt && !lsu_iu_wb_acc_err; assign wb_dbg_exp_after_retire = (bkpt_cur_state == BKPT_ACK) && lsu_iu_wb_cmplt && !lsu_iu_wb_acc_err && had_iu_mbkpt_fsm_index_mbee; parameter TRACE_IDLE = 1'b0; parameter TRACE_ACK = 1'b1; always @(posedge dbg_clk or negedge cpurst_b) begin if(!cpurst_b) trace_cur_state <= TRACE_IDLE; else trace_cur_state <= trace_next_state; end always @( trace_cur_state or ex_inst_dbg_disable or load_store_fast_retire or had_iu_rte_pc_sel or had_iu_trace_req or lsu_iu_wb_cmplt) begin case(trace_cur_state) TRACE_IDLE : if(had_iu_trace_req && load_store_fast_retire && !ex_inst_dbg_disable && !had_iu_rte_pc_sel) trace_next_state = TRACE_ACK; else trace_next_state = TRACE_IDLE; TRACE_ACK : if(lsu_iu_wb_cmplt) trace_next_state = TRACE_IDLE; else trace_next_state = TRACE_ACK; default : trace_next_state = TRACE_IDLE; endcase end assign retire_ack_trace_vld_idle = (trace_cur_state == TRACE_IDLE) && !load_store_fast_retire; assign retire_ack_trace_vld = (trace_cur_state == TRACE_ACK) && lsu_iu_wb_cmplt && !lsu_iu_wb_acc_err; assign retire_wb_dbg_in_ack = (bkpt_cur_state == BKPT_ACK) || (trace_cur_state == TRACE_ACK); parameter BR_DBG_IDLE = 2'b00; parameter BR_DBG_ACK = 2'b10; always @(posedge dbg_clk or negedge cpurst_b) begin if(!cpurst_b) br_cur_state[1:0] <= BR_DBG_IDLE; else br_cur_state[1:0] <= br_next_state[1:0]; end always @( ctrl_branch_ex_sel or br_cur_state or ifu_iu_ibus_idle or had_iu_trace_req_for_dbg_disable or ifu_iu_inst_buf_inst_vld) begin case(br_cur_state) BR_DBG_IDLE : if(ctrl_branch_ex_sel && ifu_iu_ibus_idle && had_iu_trace_req_for_dbg_disable) br_next_state = BR_DBG_ACK; else br_next_state = BR_DBG_IDLE; BR_DBG_ACK : if(ifu_iu_inst_buf_inst_vld) br_next_state = BR_DBG_IDLE; else br_next_state = BR_DBG_ACK; default : br_next_state = BR_DBG_IDLE; endcase end assign retire_branch_stall = (br_cur_state == BR_DBG_IDLE) && had_iu_trace_req_for_dbg_disable || (br_cur_state == BR_DBG_ACK) && !ifu_iu_inst_buf_inst_vld; assign retire_branch_dbg_idle = (br_cur_state == BR_DBG_IDLE); assign retire_dbg_disable = retire_dbg_disable_pre || cp0_iu_dbg_disable_for_tee; assign retire_dbg_disable_pre = retire_branch_dbg_idle ? ex_inst_dbg_disable : ifu_iu_inst_buf_inst_dbg_disable; assign ex_inst_dbg_disable = ifu_iu_ex_inst_dbg_disable || cp0_iu_dbg_disable_for_tee; assign retire_xx_normal_retire = iu_yy_xx_retire && !rbus_retire_split_inst && !(retire_pc_expt_vld && !special_retire_inst_wsc); assign sec_retire_flush = 1'b0; assign rbus_flush = iu_yy_xx_retire && rbus_retire_flush; assign nie_flush = 1'b0; assign nie_flush_chgflw = 1'b0; assign retire_mad_ex_cancel = dbgreq_ack_aft_force; assign iu_yy_xx_flush = rbus_flush || iu_cp0_expt_vld || dbgreq_ack_aft_force || wb_xx_lsu_check_fail_after_retire || retire_hs_acc_err || sec_retire_flush || nie_flush; assign iu_pad_inst_retire = iu_yy_xx_retire && !retire_split_inst_with_dbg_ack; assign iu_pad_inst_split = retire_split_inst_with_dbg_ack; assign iu_pad_retire_pc[31:0] = {pcgen_xx_cur_pc[30:0],1'b0}; endmodule module cr_iu_special( ctrl_special_ex_sel, ctrl_special_expt_vec, ctrl_special_expt_vld, decd_special_fencei, special_pcgen_chgflw_vld, special_rbus_expt_vec, special_rbus_expt_vld, special_rbus_flush, special_rbus_req, special_retire_inst_wsc, wb_special_st_uncmplt, wb_special_store ); input ctrl_special_ex_sel; input [4:0] ctrl_special_expt_vec; input ctrl_special_expt_vld; input decd_special_fencei; input wb_special_st_uncmplt; input wb_special_store; output special_pcgen_chgflw_vld; output [4:0] special_rbus_expt_vec; output special_rbus_expt_vld; output special_rbus_flush; output special_rbus_req; output special_retire_inst_wsc; wire ctrl_special_ex_sel; wire [4:0] ctrl_special_expt_vec; wire ctrl_special_expt_vld; wire decd_special_fencei; wire fencei_cmplt; wire special_pcgen_chgflw_vld; wire [4:0] special_rbus_expt_vec; wire special_rbus_expt_vld; wire special_rbus_flush; wire special_rbus_req; wire special_retire_inst_wsc; wire special_stall; wire wb_special_st_uncmplt; wire wb_special_store; assign special_stall = decd_special_fencei && wb_special_st_uncmplt; assign fencei_cmplt = decd_special_fencei && !wb_special_st_uncmplt; assign special_rbus_req = ctrl_special_ex_sel && !special_stall; assign special_rbus_flush = wb_special_store && fencei_cmplt; assign special_pcgen_chgflw_vld = wb_special_store && fencei_cmplt; assign special_rbus_expt_vld = ctrl_special_expt_vld; assign special_rbus_expt_vec[4:0] = ctrl_special_expt_vec[4:0]; assign special_retire_inst_wsc = 1'b0; endmodule module cr_iu_top( bmu_xx_ibus_acc_err, bmu_xx_ibus_data_vld, bmu_xx_ibus_grnt, clic_cpu_int_hv, clic_cpu_int_id, clic_cpu_int_il, clic_cpu_int_priv, clk_en, cp0_iu_data, cp0_iu_data_vld, cp0_iu_dbg_disable_for_tee, cp0_iu_epc_for_chgflw, cp0_iu_expt_vec, cp0_iu_expt_vld, cp0_iu_flush, cp0_iu_flush_chgflw_vld, cp0_iu_il, cp0_iu_meie, cp0_iu_mie_for_int, cp0_iu_req, cp0_iu_rte_chgflw_vld, cp0_iu_rte_chgflw_vld_for_data, cp0_iu_stall, cp0_iu_vbr, cp0_iu_vec_mode, cp0_vector_vec_err_vbr, cp0_yy_clk_en, cp0_yy_priv_mode, cpurst_b, forever_cpuclk, had_core_dbg_mode_req, had_idu_wbbr_data, had_idu_wbbr_vld, had_iu_bkpt_trace_en, had_iu_dr_set_req, had_iu_force_dbg_en, had_iu_int_vld, had_iu_mbkpt_fsm_index_mbee, had_iu_mem_bkpt_exp_req, had_iu_mem_bkpt_mask, had_iu_mem_bkpt_req, had_iu_pc, had_iu_rte_pc_sel, had_iu_trace_req, had_iu_trace_req_for_dbg_disable, had_iu_xx_fdb, had_iu_xx_jdbreq, had_yy_xx_exit_dbg, ifu_had_chg_flw_inst, ifu_had_match_pc, ifu_iu_ex_expt_cur, ifu_iu_ex_expt_vld, ifu_iu_ex_inst, ifu_iu_ex_inst_bkpt, ifu_iu_ex_inst_dbg_disable, ifu_iu_ex_inst_vld, ifu_iu_ex_int_spcu_mask, ifu_iu_ex_int_spcu_vld, ifu_iu_ex_ni, ifu_iu_ex_prvlg_expt_vld, ifu_iu_ex_rand_vld, ifu_iu_ex_sp_oper, ifu_iu_ibus_idle, ifu_iu_inst_bkpt_dbg_occur_vld, ifu_iu_inst_bkpt_dbgexp_occur_vld, ifu_iu_inst_buf_inst_dbg_disable, ifu_iu_inst_buf_inst_vld, ifu_iu_spcu_retire_mask, ifu_iu_vector_ibus_in_idle, ifu_iu_xx_ibus_data, iu_bmu_vec_redirect, iu_cp0_ecall, iu_cp0_epc, iu_cp0_epc_update, iu_cp0_ex_csrrc, iu_cp0_ex_csrrci, iu_cp0_ex_csrrs, iu_cp0_ex_csrrsi, iu_cp0_ex_csrrw, iu_cp0_ex_csrrwi, iu_cp0_ex_data_sel, iu_cp0_ex_func3, iu_cp0_ex_mret, iu_cp0_ex_rd_reg, iu_cp0_ex_rs1_reg, iu_cp0_ex_sel, iu_cp0_ex_wfi, iu_cp0_expt_tval, iu_cp0_expt_vld, iu_cp0_imm, iu_cp0_int_vld, iu_cp0_lp_wk_int, iu_cp0_mtval_updt_vld, iu_cp0_nt_int_pending_vld, iu_cp0_oper_mux_en, iu_cp0_rs1, iu_cp0_syc_rst_b, iu_had_adr_dbg_ack, iu_had_chgflw_dst_pc, iu_had_chgflw_vld, iu_had_data_bkpt_occur_vld, iu_had_dbg_disable_for_tee, iu_had_dr_dbg_ack, iu_had_expt_vld, iu_had_fast_retire_acc_err_pc_update, iu_had_fast_retire_acc_err_pc_val, iu_had_flush, iu_had_inst_bkpt_occur_vld, iu_had_int_ack, iu_had_retire_with_had_int, iu_had_trace_occur_vld, iu_had_xx_bkpt_inst, iu_had_xx_data, iu_had_xx_data_vld, iu_had_xx_dbg_ack, iu_had_xx_mldst, iu_had_xx_retire, iu_had_xx_retire_normal, iu_had_xx_retire_pc, iu_ifu_addr, iu_ifu_data_fetch, iu_ifu_data_fetch_for_data, iu_ifu_ex_stall, iu_ifu_ex_stall_noinput, iu_ifu_ex_vld, iu_ifu_inst_fetch, iu_ifu_inst_fetch_for_data, iu_ifu_inst_fetch_mask, iu_ifu_inst_fetch_without_dbg_disable, iu_ifu_kill_inst, iu_ifu_lsu_inst, iu_ifu_security_violation, iu_ifu_wb_ldst, iu_ifu_wb_stall, iu_lsu_base, iu_lsu_cmp, iu_lsu_data, iu_lsu_ex_byte, iu_lsu_ex_data_sel, iu_lsu_ex_half, iu_lsu_ex_sel, iu_lsu_ex_store, iu_lsu_ex_uns, iu_lsu_imm_data, iu_lsu_imm_sel, iu_lsu_imm_write_en, iu_lsu_offset, iu_lsu_oper_mux_en, iu_lsu_pc, iu_lsu_pc_sel, iu_lsu_rs1_sel, iu_lsu_rs2, iu_lsu_stall_without_hready, iu_lsu_wb_ldst, iu_lsu_wb_load, iu_lsu_wb_store, iu_pad_gpr_data, iu_pad_gpr_index, iu_pad_gpr_we, iu_pad_inst_retire, iu_pad_inst_split, iu_pad_retire_pc, iu_sys_lp_wk_int, iu_sysyio_soft_rst, iu_yy_xx_dbgon, iu_yy_xx_expt_vec, iu_yy_xx_flush, iu_yy_xx_int_hv, iu_yy_xx_int_il, iu_yy_xx_int_pending_hv, iu_yy_xx_int_pending_id, iu_yy_xx_int_pending_il, iu_yy_xx_int_pending_priv, lsu_iu_addr, lsu_iu_addr_vld, lsu_iu_alu_sel, lsu_iu_branch_cout, lsu_iu_branch_rst, lsu_iu_data, lsu_iu_data_vld, lsu_iu_expt_vec, lsu_iu_expt_vld, lsu_iu_fast_retire, lsu_iu_mad_buf, lsu_iu_req, lsu_iu_stall, lsu_iu_stall_noinput, lsu_iu_store, lsu_iu_wb_acc_err, lsu_iu_wb_bstack_chk_fail, lsu_iu_wb_cmplt, lsu_iu_wb_data_vld, lsu_iu_wb_load_data, lsu_iu_wfd, pad_cpu_ext_int_b, pad_yy_gate_clk_en_b, pad_yy_test_mode, split_ifctrl_hs_stall, split_ifctrl_hs_stall_part, vector_cp0_vec_err, vector_cp0_vec_err_epc, vector_cp0_vec_succeed ); input bmu_xx_ibus_acc_err; input bmu_xx_ibus_data_vld; input bmu_xx_ibus_grnt; input clic_cpu_int_hv; input [9 :0] clic_cpu_int_id; input [7 :0] clic_cpu_int_il; input [1 :0] clic_cpu_int_priv; input clk_en; input [31:0] cp0_iu_data; input cp0_iu_data_vld; input cp0_iu_dbg_disable_for_tee; input [30:0] cp0_iu_epc_for_chgflw; input [4 :0] cp0_iu_expt_vec; input cp0_iu_expt_vld; input cp0_iu_flush; input cp0_iu_flush_chgflw_vld; input [7 :0] cp0_iu_il; input cp0_iu_meie; input cp0_iu_mie_for_int; input cp0_iu_req; input cp0_iu_rte_chgflw_vld; input cp0_iu_rte_chgflw_vld_for_data; input cp0_iu_stall; input [29:0] cp0_iu_vbr; input [1 :0] cp0_iu_vec_mode; input [29:0] cp0_vector_vec_err_vbr; input cp0_yy_clk_en; input [1 :0] cp0_yy_priv_mode; input cpurst_b; input forever_cpuclk; input had_core_dbg_mode_req; input [31:0] had_idu_wbbr_data; input had_idu_wbbr_vld; input had_iu_bkpt_trace_en; input had_iu_dr_set_req; input had_iu_force_dbg_en; input had_iu_int_vld; input had_iu_mbkpt_fsm_index_mbee; input had_iu_mem_bkpt_exp_req; input had_iu_mem_bkpt_mask; input had_iu_mem_bkpt_req; input [30:0] had_iu_pc; input had_iu_rte_pc_sel; input had_iu_trace_req; input had_iu_trace_req_for_dbg_disable; input had_iu_xx_fdb; input had_iu_xx_jdbreq; input had_yy_xx_exit_dbg; input ifu_iu_ex_expt_cur; input ifu_iu_ex_expt_vld; input [31:0] ifu_iu_ex_inst; input ifu_iu_ex_inst_bkpt; input ifu_iu_ex_inst_dbg_disable; input ifu_iu_ex_inst_vld; input ifu_iu_ex_int_spcu_mask; input ifu_iu_ex_int_spcu_vld; input ifu_iu_ex_ni; input ifu_iu_ex_prvlg_expt_vld; input ifu_iu_ex_rand_vld; input ifu_iu_ex_sp_oper; input ifu_iu_ibus_idle; input ifu_iu_inst_bkpt_dbg_occur_vld; input ifu_iu_inst_bkpt_dbgexp_occur_vld; input ifu_iu_inst_buf_inst_dbg_disable; input ifu_iu_inst_buf_inst_vld; input ifu_iu_spcu_retire_mask; input ifu_iu_vector_ibus_in_idle; input [31:0] ifu_iu_xx_ibus_data; input [31:0] lsu_iu_addr; input lsu_iu_addr_vld; input lsu_iu_alu_sel; input lsu_iu_branch_cout; input [31:0] lsu_iu_branch_rst; input [31:0] lsu_iu_data; input lsu_iu_data_vld; input [4 :0] lsu_iu_expt_vec; input lsu_iu_expt_vld; input lsu_iu_fast_retire; input [31:0] lsu_iu_mad_buf; input lsu_iu_req; input lsu_iu_stall; input lsu_iu_stall_noinput; input lsu_iu_store; input lsu_iu_wb_acc_err; input lsu_iu_wb_bstack_chk_fail; input lsu_iu_wb_cmplt; input lsu_iu_wb_data_vld; input [31:0] lsu_iu_wb_load_data; input lsu_iu_wfd; input pad_cpu_ext_int_b; input pad_yy_gate_clk_en_b; input pad_yy_test_mode; output ifu_had_chg_flw_inst; output [31:0] ifu_had_match_pc; output iu_bmu_vec_redirect; output iu_cp0_ecall; output [30:0] iu_cp0_epc; output iu_cp0_epc_update; output iu_cp0_ex_csrrc; output iu_cp0_ex_csrrci; output iu_cp0_ex_csrrs; output iu_cp0_ex_csrrsi; output iu_cp0_ex_csrrw; output iu_cp0_ex_csrrwi; output iu_cp0_ex_data_sel; output [2 :0] iu_cp0_ex_func3; output iu_cp0_ex_mret; output [4 :0] iu_cp0_ex_rd_reg; output [4 :0] iu_cp0_ex_rs1_reg; output iu_cp0_ex_sel; output iu_cp0_ex_wfi; output [31:0] iu_cp0_expt_tval; output iu_cp0_expt_vld; output [11:0] iu_cp0_imm; output iu_cp0_int_vld; output iu_cp0_lp_wk_int; output iu_cp0_mtval_updt_vld; output iu_cp0_nt_int_pending_vld; output iu_cp0_oper_mux_en; output [31:0] iu_cp0_rs1; output iu_cp0_syc_rst_b; output iu_had_adr_dbg_ack; output [31:0] iu_had_chgflw_dst_pc; output iu_had_chgflw_vld; output iu_had_data_bkpt_occur_vld; output iu_had_dbg_disable_for_tee; output iu_had_dr_dbg_ack; output iu_had_expt_vld; output iu_had_fast_retire_acc_err_pc_update; output [30:0] iu_had_fast_retire_acc_err_pc_val; output iu_had_flush; output iu_had_inst_bkpt_occur_vld; output iu_had_int_ack; output iu_had_retire_with_had_int; output iu_had_trace_occur_vld; output iu_had_xx_bkpt_inst; output [31:0] iu_had_xx_data; output iu_had_xx_data_vld; output iu_had_xx_dbg_ack; output iu_had_xx_mldst; output iu_had_xx_retire; output iu_had_xx_retire_normal; output [31:0] iu_had_xx_retire_pc; output [30:0] iu_ifu_addr; output iu_ifu_data_fetch; output iu_ifu_data_fetch_for_data; output iu_ifu_ex_stall; output iu_ifu_ex_stall_noinput; output iu_ifu_ex_vld; output iu_ifu_inst_fetch; output iu_ifu_inst_fetch_for_data; output iu_ifu_inst_fetch_mask; output iu_ifu_inst_fetch_without_dbg_disable; output iu_ifu_kill_inst; output iu_ifu_lsu_inst; output iu_ifu_security_violation; output iu_ifu_wb_ldst; output iu_ifu_wb_stall; output [31:0] iu_lsu_base; output iu_lsu_cmp; output [31:0] iu_lsu_data; output iu_lsu_ex_byte; output iu_lsu_ex_data_sel; output iu_lsu_ex_half; output iu_lsu_ex_sel; output iu_lsu_ex_store; output iu_lsu_ex_uns; output [31:0] iu_lsu_imm_data; output iu_lsu_imm_sel; output iu_lsu_imm_write_en; output [31:0] iu_lsu_offset; output iu_lsu_oper_mux_en; output [31:0] iu_lsu_pc; output iu_lsu_pc_sel; output iu_lsu_rs1_sel; output [31:0] iu_lsu_rs2; output iu_lsu_stall_without_hready; output iu_lsu_wb_ldst; output iu_lsu_wb_load; output iu_lsu_wb_store; output [31:0] iu_pad_gpr_data; output [4 :0] iu_pad_gpr_index; output iu_pad_gpr_we; output iu_pad_inst_retire; output iu_pad_inst_split; output [31:0] iu_pad_retire_pc; output iu_sys_lp_wk_int; output iu_sysyio_soft_rst; output iu_yy_xx_dbgon; output [9 :0] iu_yy_xx_expt_vec; output iu_yy_xx_flush; output iu_yy_xx_int_hv; output [7 :0] iu_yy_xx_int_il; output iu_yy_xx_int_pending_hv; output [9 :0] iu_yy_xx_int_pending_id; output [7 :0] iu_yy_xx_int_pending_il; output [1 :0] iu_yy_xx_int_pending_priv; output split_ifctrl_hs_stall; output split_ifctrl_hs_stall_part; output vector_cp0_vec_err; output [29:0] vector_cp0_vec_err_epc; output vector_cp0_vec_succeed; wire alu_mad_adder_of; wire [31:0] alu_mad_adder_rst; wire alu_mad_rst_cout; wire [31:0] alu_rbus_data; wire alu_rbus_data_vld; wire alu_rbus_req; wire bctm_top_clk_en; wire bmu_xx_ibus_acc_err; wire bmu_xx_ibus_data_vld; wire bmu_xx_ibus_grnt; wire branch_alu_adder_cmp; wire branch_alu_adder_sel; wire branch_alu_logic_nz; wire branch_alu_logic_sel; wire branch_alu_pc_sel; wire branch_ctrl_stall; wire [30:0] branch_pcgen_add_pc; wire branch_pcgen_br_chgflw_vld; wire branch_pcgen_br_chgflw_vld_for_data; wire branch_pcgen_br_pc_chgflw_vld; wire branch_pcgen_branch_chgflw_vld_for_data; wire branch_pcgen_jmp_chgflw_vld_for_data; wire [30:0] branch_pcgen_reg_pc; wire [31:0] branch_rbus_data; wire branch_rbus_data_vld; wire branch_rbus_req; wire branch_wb_cmp; wire branch_wb_jmp_reg; wire clic_cpu_int_hv; wire [9 :0] clic_cpu_int_id; wire [7 :0] clic_cpu_int_il; wire [1 :0] clic_cpu_int_priv; wire clk_en; wire [31:0] cp0_iu_data; wire cp0_iu_data_vld; wire cp0_iu_dbg_disable_for_tee; wire [30:0] cp0_iu_epc_for_chgflw; wire [4 :0] cp0_iu_expt_vec; wire cp0_iu_expt_vld; wire cp0_iu_flush; wire cp0_iu_flush_chgflw_vld; wire [7 :0] cp0_iu_il; wire cp0_iu_meie; wire cp0_iu_mie_for_int; wire cp0_iu_req; wire cp0_iu_rte_chgflw_vld; wire cp0_iu_rte_chgflw_vld_for_data; wire cp0_iu_stall; wire [29:0] cp0_iu_vbr; wire [1 :0] cp0_iu_vec_mode; wire [29:0] cp0_vector_vec_err_vbr; wire cp0_yy_clk_en; wire [1 :0] cp0_yy_priv_mode; wire cpurst_b; wire ctrl_alu_ex_data_sel; wire ctrl_alu_ex_sel; wire ctrl_alu_mad_oper_mux_en; wire ctrl_alu_oper_mux_en; wire ctrl_branch_ex_data_sel; wire ctrl_branch_ex_sel; wire ctrl_cp0_ex_data_sel; wire ctrl_lsu_ex_data_sel; wire ctrl_mad_ex_data_sel; wire ctrl_mad_ex_sel; wire ctrl_mad_oper_mux_en; wire ctrl_oper_lsu_data_sel; wire ctrl_retire_ni_vld; wire ctrl_special_ex_data_sel; wire ctrl_special_ex_sel; wire [4 :0] ctrl_special_expt_vec; wire ctrl_special_expt_vld; wire ctrl_xx_sp_adjust; wire decd_alu_dst_vld; wire [2 :0] decd_alu_func; wire decd_alu_rs2_imm_vld; wire [3 :0] decd_alu_sub_func; wire decd_branch_auipc; wire decd_branch_beq; wire decd_branch_bge; wire decd_branch_bgeu; wire decd_branch_blt; wire decd_branch_bltu; wire decd_branch_bne; wire decd_branch_cbeqz; wire decd_branch_cbnez; wire decd_branch_cj; wire decd_branch_cjal; wire decd_branch_cjalr; wire decd_branch_cjr; wire decd_branch_jal; wire decd_branch_jalr; wire decd_ctrl_alu_sel; wire decd_ctrl_branch_sel; wire decd_ctrl_cp0_sel; wire decd_ctrl_expt_bkpt; wire decd_ctrl_expt_ecall; wire decd_ctrl_expt_inv; wire decd_ctrl_expt_wsc; wire decd_ctrl_lsu_sel; wire decd_ctrl_mad_sel; wire decd_mad_inst_div; wire decd_mad_inst_divu; wire decd_mad_inst_mul; wire decd_mad_inst_mulh; wire decd_mad_inst_mulhsu; wire decd_mad_inst_mulhu; wire decd_mad_inst_rem; wire decd_mad_inst_remu; wire [31:0] decd_oper_alu_imm; wire [31:0] decd_oper_branch_imm; wire [11:0] decd_oper_cp0_imm; wire [31:0] decd_oper_lsu_imm; wire decd_retire_cp0_inst; wire decd_retire_inst_mret; wire decd_special_fencei; wire [31:0] decd_wb_tval; wire decd_xx_inst_32bit; wire decd_xx_unit_special_sel; wire forever_cpuclk; wire had_core_dbg_mode_req; wire [31:0] had_idu_wbbr_data; wire had_idu_wbbr_vld; wire had_iu_bkpt_trace_en; wire had_iu_dr_set_req; wire had_iu_force_dbg_en; wire had_iu_int_vld; wire had_iu_mbkpt_fsm_index_mbee; wire had_iu_mem_bkpt_exp_req; wire had_iu_mem_bkpt_mask; wire had_iu_mem_bkpt_req; wire [30:0] had_iu_pc; wire had_iu_rte_pc_sel; wire had_iu_trace_req; wire had_iu_trace_req_for_dbg_disable; wire had_iu_xx_fdb; wire had_iu_xx_jdbreq; wire had_yy_xx_exit_dbg; wire hs_split_iu_ctrl_inst_vld; wire [31:0] hs_split_iu_dp_inst_op; wire hs_split_iu_hs_retire_mask; wire hs_split_iu_hs_switch_se; wire hs_split_iu_nsinst_gpr_rst_b; wire hs_split_iu_unstack_chgflw; wire ifu_had_chg_flw_inst; wire [31:0] ifu_had_match_pc; wire [4 :0] ifu_iu_ex_cnt; wire ifu_iu_ex_expt_cur; wire ifu_iu_ex_expt_vld; wire [31:0] ifu_iu_ex_inst; wire ifu_iu_ex_inst_bkpt; wire ifu_iu_ex_inst_dbg_disable; wire ifu_iu_ex_inst_vld; wire ifu_iu_ex_int_spcu_mask; wire ifu_iu_ex_int_spcu_vld; wire ifu_iu_ex_ni; wire ifu_iu_ex_prvlg_expt_vld; wire ifu_iu_ex_rand_vld; wire [4 :0] ifu_iu_ex_rd_reg; wire [4 :0] ifu_iu_ex_rs1_reg; wire [4 :0] ifu_iu_ex_rs2_reg; wire ifu_iu_ex_sp_oper; wire ifu_iu_ex_split_on; wire ifu_iu_ibus_idle; wire ifu_iu_inst_bkpt_dbg_occur_vld; wire ifu_iu_inst_bkpt_dbgexp_occur_vld; wire ifu_iu_inst_buf_inst_dbg_disable; wire ifu_iu_inst_buf_inst_vld; wire ifu_iu_spcu_retire_mask; wire ifu_iu_vector_ibus_in_idle; wire [31:0] ifu_iu_xx_ibus_data; wire iu_bmu_vec_redirect; wire iu_cp0_ecall; wire [30:0] iu_cp0_epc; wire iu_cp0_epc_update; wire iu_cp0_ex_csrrc; wire iu_cp0_ex_csrrci; wire iu_cp0_ex_csrrs; wire iu_cp0_ex_csrrsi; wire iu_cp0_ex_csrrw; wire iu_cp0_ex_csrrwi; wire iu_cp0_ex_data_sel; wire [2 :0] iu_cp0_ex_func3; wire iu_cp0_ex_mret; wire [4 :0] iu_cp0_ex_rd_reg; wire [4 :0] iu_cp0_ex_rs1_reg; wire iu_cp0_ex_sel; wire iu_cp0_ex_wfi; wire [31:0] iu_cp0_expt_tval; wire iu_cp0_expt_vld; wire [11:0] iu_cp0_imm; wire iu_cp0_int_vld; wire iu_cp0_lp_wk_int; wire iu_cp0_mtval_updt_vld; wire iu_cp0_nt_int_pending_vld; wire iu_cp0_oper_mux_en; wire [31:0] iu_cp0_rs1; wire iu_cp0_syc_rst_b; wire iu_had_adr_dbg_ack; wire [31:0] iu_had_chgflw_dst_pc; wire iu_had_chgflw_vld; wire iu_had_data_bkpt_occur_vld; wire iu_had_dbg_disable_for_tee; wire iu_had_dr_dbg_ack; wire iu_had_expt_vld; wire iu_had_fast_retire_acc_err_pc_update; wire [30:0] iu_had_fast_retire_acc_err_pc_val; wire iu_had_flush; wire iu_had_inst_bkpt_occur_vld; wire iu_had_int_ack; wire iu_had_retire_with_had_int; wire iu_had_trace_occur_vld; wire iu_had_xx_bkpt_inst; wire [31:0] iu_had_xx_data; wire iu_had_xx_data_vld; wire iu_had_xx_dbg_ack; wire iu_had_xx_mldst; wire iu_had_xx_retire; wire iu_had_xx_retire_normal; wire [31:0] iu_had_xx_retire_pc; wire iu_hs_split_ex_stall; wire [30:0] iu_ifu_addr; wire iu_ifu_data_fetch; wire iu_ifu_data_fetch_for_data; wire iu_ifu_ex_stall; wire iu_ifu_ex_stall_noinput; wire iu_ifu_ex_vld; wire iu_ifu_inst_fetch; wire iu_ifu_inst_fetch_for_data; wire iu_ifu_inst_fetch_mask; wire iu_ifu_inst_fetch_without_dbg_disable; wire iu_ifu_kill_inst; wire iu_ifu_lsu_inst; wire iu_ifu_security_violation; wire iu_ifu_spcu_int_en; wire iu_ifu_wb_ldst; wire iu_ifu_wb_stall; wire [31:0] iu_lsu_base; wire iu_lsu_cmp; wire [31:0] iu_lsu_data; wire iu_lsu_ex_byte; wire iu_lsu_ex_data_sel; wire iu_lsu_ex_half; wire iu_lsu_ex_sel; wire iu_lsu_ex_store; wire iu_lsu_ex_uns; wire [31:0] iu_lsu_imm_data; wire iu_lsu_imm_sel; wire iu_lsu_imm_write_en; wire [31:0] iu_lsu_offset; wire iu_lsu_oper_mux_en; wire [31:0] iu_lsu_pc; wire iu_lsu_pc_sel; wire iu_lsu_rs1_sel; wire [31:0] iu_lsu_rs2; wire iu_lsu_stall_without_hready; wire iu_lsu_wb_ldst; wire iu_lsu_wb_load; wire iu_lsu_wb_store; wire [31:0] iu_pad_gpr_data; wire [4 :0] iu_pad_gpr_index; wire iu_pad_gpr_we; wire iu_pad_inst_retire; wire iu_pad_inst_split; wire [31:0] iu_pad_retire_pc; wire iu_sys_lp_wk_int; wire iu_sysyio_soft_rst; wire iu_yy_xx_dbgon; wire [9 :0] iu_yy_xx_expt_vec; wire iu_yy_xx_flush; wire iu_yy_xx_int_hv; wire [7 :0] iu_yy_xx_int_il; wire iu_yy_xx_int_pending_hv; wire [9 :0] iu_yy_xx_int_pending_id; wire [7 :0] iu_yy_xx_int_pending_il; wire [1 :0] iu_yy_xx_int_pending_priv; wire iu_yy_xx_reg_rst_b; wire iu_yy_xx_retire; wire [31:0] lsu_iu_addr; wire lsu_iu_addr_vld; wire lsu_iu_alu_sel; wire lsu_iu_branch_cout; wire [31:0] lsu_iu_branch_rst; wire [31:0] lsu_iu_data; wire lsu_iu_data_vld; wire [4 :0] lsu_iu_expt_vec; wire lsu_iu_expt_vld; wire lsu_iu_fast_retire; wire [31:0] lsu_iu_mad_buf; wire lsu_iu_req; wire lsu_iu_stall; wire lsu_iu_stall_noinput; wire lsu_iu_store; wire lsu_iu_wb_acc_err; wire lsu_iu_wb_bstack_chk_fail; wire lsu_iu_wb_cmplt; wire lsu_iu_wb_data_vld; wire [31:0] lsu_iu_wb_load_data; wire lsu_iu_wfd; wire mad_alu_data_vld; wire [31:0] mad_alu_div_rs2; wire mad_alu_div_shift; wire mad_alu_fst_add; wire mad_alu_imm_vld; wire [31:0] mad_alu_rs1; wire mad_alu_rs1_cst_0; wire mad_alu_rs1_vld; wire mad_alu_rs2_cst_0; wire [31:0] mad_alu_rst; wire mad_alu_rst_vld; wire mad_ctrl_stall; wire mad_ctrl_stall_noinput; wire mad_rbus_req; wire misc_clk; wire misc_clk_en; wire nie_flush_chgflw; wire [31:0] oper_alu_rs1_reg; wire [31:0] oper_alu_rs2_imm; wire [31:0] oper_alu_rs2_reg; wire [31:0] oper_branch_rs1_reg; wire [31:0] oper_branch_rs2_imm; wire [31:0] oper_branch_rs2_reg; wire [31:0] oper_mad_rs1; wire [31:0] oper_mad_rs2; wire oper_wb_rs1_equal_to_dst; wire oper_wb_rs2_equal_to_dst; wire pad_cpu_ext_int_b; wire pad_yy_gate_clk_en_b; wire pad_yy_test_mode; wire pcgen_ctrl_stall; wire [30:0] pcgen_retire_updt_pc; wire pcgen_top_abort_clk_en; wire pcgen_vector_expt_taken; wire [30:0] pcgen_xx_cur_pc; wire pcgen_xx_ibus_idle; wire randclk_mad_mod_en_w2; wire [20:0] randclk_oper_gpr_mod_en_w32; wire randclk_pcgen_mod_en_w32; wire randclk_retire_mod_en_w2; wire randclk_wb_buf_mod_en_w32; wire randclk_wb_ctrl_mod_en_w2; wire randclk_wb_idx_mod_en_w5; wire rbus_retire_cmplt; wire [4 :0] rbus_retire_expt_vec; wire rbus_retire_expt_vld; wire rbus_retire_flush; wire rbus_retire_split_inst; wire rbus_wb_cmplt; wire [31:0] rbus_wb_data; wire [4 :0] rbus_wb_dst_reg; wire rbus_wb_inst_cmplt; wire rbus_wb_load; wire rbus_wb_store; wire retire_branch_stall; wire retire_mad_ex_cancel; wire retire_pcgen_curpc_update; wire retire_vector_expt_int_hv; wire retire_vector_expt_vld; wire retire_wb_dbg_in_ack; wire retire_wb_hs_err_epc_sel; wire retire_wb_mem_bkpt_fast_retire; wire retire_xx_normal_retire; wire sec_top_clk_en; wire special_pcgen_chgflw_vld; wire [4 :0] special_rbus_expt_vec; wire special_rbus_expt_vld; wire special_rbus_flush; wire special_rbus_req; wire special_retire_inst_wsc; wire split_ifctrl_hs_stall; wire split_ifctrl_hs_stall_part; wire vec_top_clk_en; wire vector_cp0_vec_err; wire [29:0] vector_cp0_vec_err_epc; wire vector_cp0_vec_succeed; wire vector_ctrl_stall; wire vector_pcgen_buf_vbr; wire vector_pcgen_chgflw_vld; wire vector_pcgen_cur_pc_vld; wire [30:0] vector_pcgen_enter_addr; wire vector_pcgen_ibus_req; wire wb_branch_dep_ld; wire wb_ctrl_stall; wire wb_ctrl_stall_without_hready; wire [31:0] wb_oper_fwd_data_no_load; wire wb_oper_fwd_en; wire [31:0] wb_oper_write_data; wire wb_oper_write_en; wire [4 :0] wb_oper_write_idx; wire [4 :0] wb_oper_write_idx_for_dep; wire wb_pcgen_ldst_stall; wire [30:0] wb_pcgen_pc_updt_val; wire wb_pcgen_switch_ld_pc; wire [4 :0] wb_rbus_lsu_vec; wire wb_rbus_st_aft_load; wire [30:0] wb_retire_fast_retire_load_pc; wire wb_special_st_uncmplt; wire wb_special_store; wire wb_top_machine_mode_clk_en; wire wb_top_machine_sp_en_clk_en; wire wb_top_secu_mode_clk_en; wire wb_top_sp_adjust_clk_en; wire wb_vector_ldst_wait_cmplt; wire wb_xx_acc_err_after_retire; wire wb_xx_lsu_check_fail_after_retire; gated_clk_cell x_misc_gated_clk ( .clk_in (forever_cpuclk ), .clk_out (misc_clk ), .external_en (1'b0 ), .global_en (cp0_yy_clk_en ), .local_en (misc_clk_en ), .module_en (1'b0 ), .pad_yy_gate_clk_en_b (pad_yy_gate_clk_en_b), .pad_yy_test_mode (pad_yy_test_mode ) ); assign bctm_top_clk_en = 1'b0; assign sec_top_clk_en = 1'b0; assign misc_clk_en = bctm_top_clk_en || pcgen_top_abort_clk_en || sec_top_clk_en || wb_top_secu_mode_clk_en || wb_top_machine_mode_clk_en || wb_top_sp_adjust_clk_en || vec_top_clk_en || wb_top_machine_sp_en_clk_en; cr_iu_decd x_cr_iu_decd ( .branch_pcgen_add_pc (branch_pcgen_add_pc ), .cp0_yy_priv_mode (cp0_yy_priv_mode ), .decd_alu_dst_vld (decd_alu_dst_vld ), .decd_alu_func (decd_alu_func ), .decd_alu_rs2_imm_vld (decd_alu_rs2_imm_vld ), .decd_alu_sub_func (decd_alu_sub_func ), .decd_branch_auipc (decd_branch_auipc ), .decd_branch_beq (decd_branch_beq ), .decd_branch_bge (decd_branch_bge ), .decd_branch_bgeu (decd_branch_bgeu ), .decd_branch_blt (decd_branch_blt ), .decd_branch_bltu (decd_branch_bltu ), .decd_branch_bne (decd_branch_bne ), .decd_branch_cbeqz (decd_branch_cbeqz ), .decd_branch_cbnez (decd_branch_cbnez ), .decd_branch_cj (decd_branch_cj ), .decd_branch_cjal (decd_branch_cjal ), .decd_branch_cjalr (decd_branch_cjalr ), .decd_branch_cjr (decd_branch_cjr ), .decd_branch_jal (decd_branch_jal ), .decd_branch_jalr (decd_branch_jalr ), .decd_ctrl_alu_sel (decd_ctrl_alu_sel ), .decd_ctrl_branch_sel (decd_ctrl_branch_sel ), .decd_ctrl_cp0_sel (decd_ctrl_cp0_sel ), .decd_ctrl_expt_bkpt (decd_ctrl_expt_bkpt ), .decd_ctrl_expt_ecall (decd_ctrl_expt_ecall ), .decd_ctrl_expt_inv (decd_ctrl_expt_inv ), .decd_ctrl_expt_wsc (decd_ctrl_expt_wsc ), .decd_ctrl_lsu_sel (decd_ctrl_lsu_sel ), .decd_ctrl_mad_sel (decd_ctrl_mad_sel ), .decd_mad_inst_div (decd_mad_inst_div ), .decd_mad_inst_divu (decd_mad_inst_divu ), .decd_mad_inst_mul (decd_mad_inst_mul ), .decd_mad_inst_mulh (decd_mad_inst_mulh ), .decd_mad_inst_mulhsu (decd_mad_inst_mulhsu ), .decd_mad_inst_mulhu (decd_mad_inst_mulhu ), .decd_mad_inst_rem (decd_mad_inst_rem ), .decd_mad_inst_remu (decd_mad_inst_remu ), .decd_oper_alu_imm (decd_oper_alu_imm ), .decd_oper_branch_imm (decd_oper_branch_imm ), .decd_oper_cp0_imm (decd_oper_cp0_imm ), .decd_oper_lsu_imm (decd_oper_lsu_imm ), .decd_retire_cp0_inst (decd_retire_cp0_inst ), .decd_retire_inst_mret (decd_retire_inst_mret ), .decd_special_fencei (decd_special_fencei ), .decd_wb_tval (decd_wb_tval ), .decd_xx_inst_32bit (decd_xx_inst_32bit ), .decd_xx_unit_special_sel (decd_xx_unit_special_sel ), .hs_split_iu_ctrl_inst_vld (hs_split_iu_ctrl_inst_vld), .hs_split_iu_dp_inst_op (hs_split_iu_dp_inst_op ), .ifu_had_chg_flw_inst (ifu_had_chg_flw_inst ), .ifu_had_match_pc (ifu_had_match_pc ), .ifu_iu_ex_expt_cur (ifu_iu_ex_expt_cur ), .ifu_iu_ex_expt_vld (ifu_iu_ex_expt_vld ), .ifu_iu_ex_inst (ifu_iu_ex_inst ), .ifu_iu_ex_inst_bkpt (ifu_iu_ex_inst_bkpt ), .ifu_iu_ex_prvlg_expt_vld (ifu_iu_ex_prvlg_expt_vld ), .ifu_iu_ex_rd_reg (ifu_iu_ex_rd_reg ), .ifu_iu_ex_rs1_reg (ifu_iu_ex_rs1_reg ), .ifu_iu_ex_rs2_reg (ifu_iu_ex_rs2_reg ), .iu_cp0_ex_csrrc (iu_cp0_ex_csrrc ), .iu_cp0_ex_csrrci (iu_cp0_ex_csrrci ), .iu_cp0_ex_csrrs (iu_cp0_ex_csrrs ), .iu_cp0_ex_csrrsi (iu_cp0_ex_csrrsi ), .iu_cp0_ex_csrrw (iu_cp0_ex_csrrw ), .iu_cp0_ex_csrrwi (iu_cp0_ex_csrrwi ), .iu_cp0_ex_func3 (iu_cp0_ex_func3 ), .iu_cp0_ex_mret (iu_cp0_ex_mret ), .iu_cp0_ex_rd_reg (iu_cp0_ex_rd_reg ), .iu_cp0_ex_rs1_reg (iu_cp0_ex_rs1_reg ), .iu_cp0_ex_wfi (iu_cp0_ex_wfi ), .iu_ifu_lsu_inst (iu_ifu_lsu_inst ), .iu_lsu_ex_byte (iu_lsu_ex_byte ), .iu_lsu_ex_half (iu_lsu_ex_half ), .iu_lsu_ex_store (iu_lsu_ex_store ), .iu_lsu_ex_uns (iu_lsu_ex_uns ), .lsu_iu_wfd (lsu_iu_wfd ), .pcgen_xx_cur_pc (pcgen_xx_cur_pc ) ); cr_iu_oper x_cr_iu_oper ( .cp0_yy_clk_en (cp0_yy_clk_en ), .ctrl_oper_lsu_data_sel (ctrl_oper_lsu_data_sel ), .decd_oper_alu_imm (decd_oper_alu_imm ), .decd_oper_branch_imm (decd_oper_branch_imm ), .decd_oper_cp0_imm (decd_oper_cp0_imm ), .decd_oper_lsu_imm (decd_oper_lsu_imm ), .forever_cpuclk (forever_cpuclk ), .had_idu_wbbr_data (had_idu_wbbr_data ), .had_idu_wbbr_vld (had_idu_wbbr_vld ), .hs_split_iu_nsinst_gpr_rst_b (hs_split_iu_nsinst_gpr_rst_b), .ifu_iu_ex_rs1_reg (ifu_iu_ex_rs1_reg ), .ifu_iu_ex_rs2_reg (ifu_iu_ex_rs2_reg ), .iu_cp0_imm (iu_cp0_imm ), .iu_cp0_rs1 (iu_cp0_rs1 ), .iu_lsu_base (iu_lsu_base ), .iu_lsu_data (iu_lsu_data ), .iu_lsu_offset (iu_lsu_offset ), .iu_lsu_rs2 (iu_lsu_rs2 ), .iu_yy_xx_reg_rst_b (iu_yy_xx_reg_rst_b ), .oper_alu_rs1_reg (oper_alu_rs1_reg ), .oper_alu_rs2_imm (oper_alu_rs2_imm ), .oper_alu_rs2_reg (oper_alu_rs2_reg ), .oper_branch_rs1_reg (oper_branch_rs1_reg ), .oper_branch_rs2_imm (oper_branch_rs2_imm ), .oper_branch_rs2_reg (oper_branch_rs2_reg ), .oper_mad_rs1 (oper_mad_rs1 ), .oper_mad_rs2 (oper_mad_rs2 ), .oper_wb_rs1_equal_to_dst (oper_wb_rs1_equal_to_dst ), .oper_wb_rs2_equal_to_dst (oper_wb_rs2_equal_to_dst ), .pad_yy_gate_clk_en_b (pad_yy_gate_clk_en_b ), .pad_yy_test_mode (pad_yy_test_mode ), .randclk_oper_gpr_mod_en_w32 (randclk_oper_gpr_mod_en_w32 ), .wb_oper_fwd_data_no_load (wb_oper_fwd_data_no_load ), .wb_oper_fwd_en (wb_oper_fwd_en ), .wb_oper_write_data (wb_oper_write_data ), .wb_oper_write_en (wb_oper_write_en ), .wb_oper_write_idx (wb_oper_write_idx ), .wb_oper_write_idx_for_dep (wb_oper_write_idx_for_dep ) ); cr_iu_alu x_cr_iu_alu ( .alu_mad_adder_of (alu_mad_adder_of ), .alu_mad_adder_rst (alu_mad_adder_rst ), .alu_mad_rst_cout (alu_mad_rst_cout ), .alu_rbus_data (alu_rbus_data ), .alu_rbus_data_vld (alu_rbus_data_vld ), .alu_rbus_req (alu_rbus_req ), .branch_alu_adder_cmp (branch_alu_adder_cmp ), .branch_alu_adder_sel (branch_alu_adder_sel ), .branch_alu_logic_nz (branch_alu_logic_nz ), .branch_alu_logic_sel (branch_alu_logic_sel ), .branch_alu_pc_sel (branch_alu_pc_sel ), .ctrl_alu_ex_sel (ctrl_alu_ex_sel ), .ctrl_alu_mad_oper_mux_en (ctrl_alu_mad_oper_mux_en), .ctrl_alu_oper_mux_en (ctrl_alu_oper_mux_en ), .ctrl_mad_ex_data_sel (ctrl_mad_ex_data_sel ), .decd_alu_dst_vld (decd_alu_dst_vld ), .decd_alu_func (decd_alu_func ), .decd_alu_rs2_imm_vld (decd_alu_rs2_imm_vld ), .decd_alu_sub_func (decd_alu_sub_func ), .ifu_iu_ex_cnt (ifu_iu_ex_cnt ), .lsu_iu_alu_sel (lsu_iu_alu_sel ), .lsu_iu_mad_buf (lsu_iu_mad_buf ), .mad_alu_data_vld (mad_alu_data_vld ), .mad_alu_div_rs2 (mad_alu_div_rs2 ), .mad_alu_div_shift (mad_alu_div_shift ), .mad_alu_fst_add (mad_alu_fst_add ), .mad_alu_imm_vld (mad_alu_imm_vld ), .mad_alu_rs1 (mad_alu_rs1 ), .mad_alu_rs1_cst_0 (mad_alu_rs1_cst_0 ), .mad_alu_rs1_vld (mad_alu_rs1_vld ), .mad_alu_rs2_cst_0 (mad_alu_rs2_cst_0 ), .mad_alu_rst (mad_alu_rst ), .mad_alu_rst_vld (mad_alu_rst_vld ), .oper_alu_rs1_reg (oper_alu_rs1_reg ), .oper_alu_rs2_imm (oper_alu_rs2_imm ), .oper_alu_rs2_reg (oper_alu_rs2_reg ), .pcgen_xx_cur_pc (pcgen_xx_cur_pc ) ); cr_iu_mad x_cr_iu_mad ( .alu_mad_adder_of (alu_mad_adder_of ), .alu_mad_adder_rst (alu_mad_adder_rst ), .alu_mad_rst_cout (alu_mad_rst_cout ), .cp0_yy_clk_en (cp0_yy_clk_en ), .cpurst_b (cpurst_b ), .ctrl_mad_ex_data_sel (ctrl_mad_ex_data_sel ), .ctrl_mad_ex_sel (ctrl_mad_ex_sel ), .ctrl_mad_oper_mux_en (ctrl_mad_oper_mux_en ), .decd_mad_inst_div (decd_mad_inst_div ), .decd_mad_inst_divu (decd_mad_inst_divu ), .decd_mad_inst_mul (decd_mad_inst_mul ), .decd_mad_inst_mulh (decd_mad_inst_mulh ), .decd_mad_inst_mulhsu (decd_mad_inst_mulhsu ), .decd_mad_inst_mulhu (decd_mad_inst_mulhu ), .decd_mad_inst_rem (decd_mad_inst_rem ), .decd_mad_inst_remu (decd_mad_inst_remu ), .forever_cpuclk (forever_cpuclk ), .ifu_iu_ex_cnt (ifu_iu_ex_cnt ), .ifu_iu_ex_split_on (ifu_iu_ex_split_on ), .iu_lsu_imm_data (iu_lsu_imm_data ), .iu_lsu_imm_write_en (iu_lsu_imm_write_en ), .iu_yy_xx_flush (iu_yy_xx_flush ), .lsu_iu_mad_buf (lsu_iu_mad_buf ), .mad_alu_data_vld (mad_alu_data_vld ), .mad_alu_div_rs2 (mad_alu_div_rs2 ), .mad_alu_div_shift (mad_alu_div_shift ), .mad_alu_fst_add (mad_alu_fst_add ), .mad_alu_imm_vld (mad_alu_imm_vld ), .mad_alu_rs1 (mad_alu_rs1 ), .mad_alu_rs1_cst_0 (mad_alu_rs1_cst_0 ), .mad_alu_rs1_vld (mad_alu_rs1_vld ), .mad_alu_rs2_cst_0 (mad_alu_rs2_cst_0 ), .mad_alu_rst (mad_alu_rst ), .mad_alu_rst_vld (mad_alu_rst_vld ), .mad_ctrl_stall (mad_ctrl_stall ), .mad_ctrl_stall_noinput (mad_ctrl_stall_noinput), .mad_rbus_req (mad_rbus_req ), .oper_mad_rs1 (oper_mad_rs1 ), .oper_mad_rs2 (oper_mad_rs2 ), .pad_yy_gate_clk_en_b (pad_yy_gate_clk_en_b ), .pad_yy_test_mode (pad_yy_test_mode ), .randclk_mad_mod_en_w2 (randclk_mad_mod_en_w2 ), .retire_mad_ex_cancel (retire_mad_ex_cancel ), .wb_ctrl_stall (wb_ctrl_stall ) ); cr_iu_branch x_cr_iu_branch ( .branch_alu_adder_cmp (branch_alu_adder_cmp ), .branch_alu_adder_sel (branch_alu_adder_sel ), .branch_alu_logic_nz (branch_alu_logic_nz ), .branch_alu_logic_sel (branch_alu_logic_sel ), .branch_alu_pc_sel (branch_alu_pc_sel ), .branch_ctrl_stall (branch_ctrl_stall ), .branch_pcgen_add_pc (branch_pcgen_add_pc ), .branch_pcgen_br_chgflw_vld (branch_pcgen_br_chgflw_vld ), .branch_pcgen_br_chgflw_vld_for_data (branch_pcgen_br_chgflw_vld_for_data ), .branch_pcgen_br_pc_chgflw_vld (branch_pcgen_br_pc_chgflw_vld ), .branch_pcgen_branch_chgflw_vld_for_data (branch_pcgen_branch_chgflw_vld_for_data), .branch_pcgen_jmp_chgflw_vld_for_data (branch_pcgen_jmp_chgflw_vld_for_data ), .branch_pcgen_reg_pc (branch_pcgen_reg_pc ), .branch_rbus_data (branch_rbus_data ), .branch_rbus_data_vld (branch_rbus_data_vld ), .branch_rbus_req (branch_rbus_req ), .branch_wb_cmp (branch_wb_cmp ), .branch_wb_jmp_reg (branch_wb_jmp_reg ), .ctrl_branch_ex_data_sel (ctrl_branch_ex_data_sel ), .ctrl_branch_ex_sel (ctrl_branch_ex_sel ), .decd_branch_auipc (decd_branch_auipc ), .decd_branch_beq (decd_branch_beq ), .decd_branch_bge (decd_branch_bge ), .decd_branch_bgeu (decd_branch_bgeu ), .decd_branch_blt (decd_branch_blt ), .decd_branch_bltu (decd_branch_bltu ), .decd_branch_bne (decd_branch_bne ), .decd_branch_cbeqz (decd_branch_cbeqz ), .decd_branch_cbnez (decd_branch_cbnez ), .decd_branch_cj (decd_branch_cj ), .decd_branch_cjal (decd_branch_cjal ), .decd_branch_cjalr (decd_branch_cjalr ), .decd_branch_cjr (decd_branch_cjr ), .decd_branch_jal (decd_branch_jal ), .decd_branch_jalr (decd_branch_jalr ), .decd_xx_inst_32bit (decd_xx_inst_32bit ), .iu_had_chgflw_dst_pc (iu_had_chgflw_dst_pc ), .iu_had_chgflw_vld (iu_had_chgflw_vld ), .iu_lsu_cmp (iu_lsu_cmp ), .iu_lsu_imm_sel (iu_lsu_imm_sel ), .iu_lsu_pc (iu_lsu_pc ), .iu_lsu_pc_sel (iu_lsu_pc_sel ), .iu_lsu_rs1_sel (iu_lsu_rs1_sel ), .lsu_iu_branch_cout (lsu_iu_branch_cout ), .lsu_iu_branch_rst (lsu_iu_branch_rst ), .oper_branch_rs1_reg (oper_branch_rs1_reg ), .oper_branch_rs2_imm (oper_branch_rs2_imm ), .oper_branch_rs2_reg (oper_branch_rs2_reg ), .pcgen_xx_cur_pc (pcgen_xx_cur_pc ), .pcgen_xx_ibus_idle (pcgen_xx_ibus_idle ), .retire_branch_stall (retire_branch_stall ), .wb_branch_dep_ld (wb_branch_dep_ld ), .wb_ctrl_stall_without_hready (wb_ctrl_stall_without_hready ) ); cr_iu_special x_cr_iu_special ( .ctrl_special_ex_sel (ctrl_special_ex_sel ), .ctrl_special_expt_vec (ctrl_special_expt_vec ), .ctrl_special_expt_vld (ctrl_special_expt_vld ), .decd_special_fencei (decd_special_fencei ), .special_pcgen_chgflw_vld (special_pcgen_chgflw_vld), .special_rbus_expt_vec (special_rbus_expt_vec ), .special_rbus_expt_vld (special_rbus_expt_vld ), .special_rbus_flush (special_rbus_flush ), .special_rbus_req (special_rbus_req ), .special_retire_inst_wsc (special_retire_inst_wsc ), .wb_special_st_uncmplt (wb_special_st_uncmplt ), .wb_special_store (wb_special_store ) ); cr_iu_rbus x_cr_iu_rbus ( .alu_rbus_data (alu_rbus_data ), .alu_rbus_data_vld (alu_rbus_data_vld ), .alu_rbus_req (alu_rbus_req ), .branch_rbus_data (branch_rbus_data ), .branch_rbus_data_vld (branch_rbus_data_vld ), .branch_rbus_req (branch_rbus_req ), .cp0_iu_data (cp0_iu_data ), .cp0_iu_data_vld (cp0_iu_data_vld ), .cp0_iu_expt_vec (cp0_iu_expt_vec ), .cp0_iu_expt_vld (cp0_iu_expt_vld ), .cp0_iu_flush (cp0_iu_flush ), .cp0_iu_req (cp0_iu_req ), .ctrl_alu_ex_data_sel (ctrl_alu_ex_data_sel ), .ctrl_branch_ex_data_sel (ctrl_branch_ex_data_sel ), .ctrl_cp0_ex_data_sel (ctrl_cp0_ex_data_sel ), .ctrl_lsu_ex_data_sel (ctrl_lsu_ex_data_sel ), .ctrl_mad_ex_data_sel (ctrl_mad_ex_data_sel ), .ctrl_special_ex_data_sel (ctrl_special_ex_data_sel ), .ctrl_xx_sp_adjust (ctrl_xx_sp_adjust ), .decd_xx_unit_special_sel (decd_xx_unit_special_sel ), .hs_split_iu_hs_retire_mask (hs_split_iu_hs_retire_mask), .ifu_iu_ex_int_spcu_mask (ifu_iu_ex_int_spcu_mask ), .ifu_iu_ex_rd_reg (ifu_iu_ex_rd_reg ), .lsu_iu_data (lsu_iu_data ), .lsu_iu_data_vld (lsu_iu_data_vld ), .lsu_iu_expt_vec (lsu_iu_expt_vec ), .lsu_iu_expt_vld (lsu_iu_expt_vld ), .lsu_iu_fast_retire (lsu_iu_fast_retire ), .lsu_iu_req (lsu_iu_req ), .lsu_iu_store (lsu_iu_store ), .mad_alu_data_vld (mad_alu_data_vld ), .mad_ctrl_stall (mad_ctrl_stall ), .mad_rbus_req (mad_rbus_req ), .rbus_retire_cmplt (rbus_retire_cmplt ), .rbus_retire_expt_vec (rbus_retire_expt_vec ), .rbus_retire_expt_vld (rbus_retire_expt_vld ), .rbus_retire_flush (rbus_retire_flush ), .rbus_retire_split_inst (rbus_retire_split_inst ), .rbus_wb_cmplt (rbus_wb_cmplt ), .rbus_wb_data (rbus_wb_data ), .rbus_wb_dst_reg (rbus_wb_dst_reg ), .rbus_wb_inst_cmplt (rbus_wb_inst_cmplt ), .rbus_wb_load (rbus_wb_load ), .rbus_wb_store (rbus_wb_store ), .special_rbus_expt_vec (special_rbus_expt_vec ), .special_rbus_expt_vld (special_rbus_expt_vld ), .special_rbus_flush (special_rbus_flush ), .special_rbus_req (special_rbus_req ), .wb_rbus_lsu_vec (wb_rbus_lsu_vec ), .wb_rbus_st_aft_load (wb_rbus_st_aft_load ), .wb_xx_acc_err_after_retire (wb_xx_acc_err_after_retire) ); cr_iu_retire x_cr_iu_retire ( .clic_cpu_int_hv (clic_cpu_int_hv ), .clic_cpu_int_id (clic_cpu_int_id ), .clic_cpu_int_il (clic_cpu_int_il ), .clic_cpu_int_priv (clic_cpu_int_priv ), .clk_en (clk_en ), .cp0_iu_dbg_disable_for_tee (cp0_iu_dbg_disable_for_tee ), .cp0_iu_il (cp0_iu_il ), .cp0_iu_meie (cp0_iu_meie ), .cp0_iu_mie_for_int (cp0_iu_mie_for_int ), .cp0_iu_vec_mode (cp0_iu_vec_mode ), .cp0_yy_clk_en (cp0_yy_clk_en ), .cpurst_b (cpurst_b ), .ctrl_branch_ex_sel (ctrl_branch_ex_sel ), .ctrl_retire_ni_vld (ctrl_retire_ni_vld ), .decd_retire_cp0_inst (decd_retire_cp0_inst ), .decd_retire_inst_mret (decd_retire_inst_mret ), .forever_cpuclk (forever_cpuclk ), .had_core_dbg_mode_req (had_core_dbg_mode_req ), .had_iu_bkpt_trace_en (had_iu_bkpt_trace_en ), .had_iu_dr_set_req (had_iu_dr_set_req ), .had_iu_force_dbg_en (had_iu_force_dbg_en ), .had_iu_int_vld (had_iu_int_vld ), .had_iu_mbkpt_fsm_index_mbee (had_iu_mbkpt_fsm_index_mbee ), .had_iu_mem_bkpt_exp_req (had_iu_mem_bkpt_exp_req ), .had_iu_mem_bkpt_mask (had_iu_mem_bkpt_mask ), .had_iu_mem_bkpt_req (had_iu_mem_bkpt_req ), .had_iu_rte_pc_sel (had_iu_rte_pc_sel ), .had_iu_trace_req (had_iu_trace_req ), .had_iu_trace_req_for_dbg_disable (had_iu_trace_req_for_dbg_disable ), .had_iu_xx_fdb (had_iu_xx_fdb ), .had_iu_xx_jdbreq (had_iu_xx_jdbreq ), .had_yy_xx_exit_dbg (had_yy_xx_exit_dbg ), .hs_split_iu_hs_retire_mask (hs_split_iu_hs_retire_mask ), .hs_split_iu_hs_switch_se (hs_split_iu_hs_switch_se ), .ifu_iu_ex_inst_dbg_disable (ifu_iu_ex_inst_dbg_disable ), .ifu_iu_ex_sp_oper (ifu_iu_ex_sp_oper ), .ifu_iu_ex_split_on (ifu_iu_ex_split_on ), .ifu_iu_ibus_idle (ifu_iu_ibus_idle ), .ifu_iu_inst_bkpt_dbg_occur_vld (ifu_iu_inst_bkpt_dbg_occur_vld ), .ifu_iu_inst_bkpt_dbgexp_occur_vld (ifu_iu_inst_bkpt_dbgexp_occur_vld ), .ifu_iu_inst_buf_inst_dbg_disable (ifu_iu_inst_buf_inst_dbg_disable ), .ifu_iu_inst_buf_inst_vld (ifu_iu_inst_buf_inst_vld ), .iu_cp0_epc (iu_cp0_epc ), .iu_cp0_epc_update (iu_cp0_epc_update ), .iu_cp0_expt_vld (iu_cp0_expt_vld ), .iu_cp0_int_vld (iu_cp0_int_vld ), .iu_cp0_lp_wk_int (iu_cp0_lp_wk_int ), .iu_cp0_mtval_updt_vld (iu_cp0_mtval_updt_vld ), .iu_cp0_nt_int_pending_vld (iu_cp0_nt_int_pending_vld ), .iu_had_adr_dbg_ack (iu_had_adr_dbg_ack ), .iu_had_data_bkpt_occur_vld (iu_had_data_bkpt_occur_vld ), .iu_had_dbg_disable_for_tee (iu_had_dbg_disable_for_tee ), .iu_had_dr_dbg_ack (iu_had_dr_dbg_ack ), .iu_had_expt_vld (iu_had_expt_vld ), .iu_had_fast_retire_acc_err_pc_update (iu_had_fast_retire_acc_err_pc_update), .iu_had_fast_retire_acc_err_pc_val (iu_had_fast_retire_acc_err_pc_val ), .iu_had_inst_bkpt_occur_vld (iu_had_inst_bkpt_occur_vld ), .iu_had_int_ack (iu_had_int_ack ), .iu_had_retire_with_had_int (iu_had_retire_with_had_int ), .iu_had_trace_occur_vld (iu_had_trace_occur_vld ), .iu_had_xx_bkpt_inst (iu_had_xx_bkpt_inst ), .iu_had_xx_dbg_ack (iu_had_xx_dbg_ack ), .iu_had_xx_mldst (iu_had_xx_mldst ), .iu_had_xx_retire (iu_had_xx_retire ), .iu_had_xx_retire_normal (iu_had_xx_retire_normal ), .iu_had_xx_retire_pc (iu_had_xx_retire_pc ), .iu_ifu_kill_inst (iu_ifu_kill_inst ), .iu_ifu_spcu_int_en (iu_ifu_spcu_int_en ), .iu_pad_inst_retire (iu_pad_inst_retire ), .iu_pad_inst_split (iu_pad_inst_split ), .iu_pad_retire_pc (iu_pad_retire_pc ), .iu_sys_lp_wk_int (iu_sys_lp_wk_int ), .iu_yy_xx_dbgon (iu_yy_xx_dbgon ), .iu_yy_xx_expt_vec (iu_yy_xx_expt_vec ), .iu_yy_xx_flush (iu_yy_xx_flush ), .iu_yy_xx_int_hv (iu_yy_xx_int_hv ), .iu_yy_xx_int_il (iu_yy_xx_int_il ), .iu_yy_xx_int_pending_hv (iu_yy_xx_int_pending_hv ), .iu_yy_xx_int_pending_id (iu_yy_xx_int_pending_id ), .iu_yy_xx_int_pending_il (iu_yy_xx_int_pending_il ), .iu_yy_xx_int_pending_priv (iu_yy_xx_int_pending_priv ), .iu_yy_xx_reg_rst_b (iu_yy_xx_reg_rst_b ), .iu_yy_xx_retire (iu_yy_xx_retire ), .lsu_iu_wb_acc_err (lsu_iu_wb_acc_err ), .lsu_iu_wb_cmplt (lsu_iu_wb_cmplt ), .nie_flush_chgflw (nie_flush_chgflw ), .pad_cpu_ext_int_b (pad_cpu_ext_int_b ), .pad_yy_gate_clk_en_b (pad_yy_gate_clk_en_b ), .pad_yy_test_mode (pad_yy_test_mode ), .pcgen_retire_updt_pc (pcgen_retire_updt_pc ), .pcgen_xx_cur_pc (pcgen_xx_cur_pc ), .randclk_retire_mod_en_w2 (randclk_retire_mod_en_w2 ), .rbus_retire_cmplt (rbus_retire_cmplt ), .rbus_retire_expt_vec (rbus_retire_expt_vec ), .rbus_retire_expt_vld (rbus_retire_expt_vld ), .rbus_retire_flush (rbus_retire_flush ), .rbus_retire_split_inst (rbus_retire_split_inst ), .rbus_wb_load (rbus_wb_load ), .rbus_wb_store (rbus_wb_store ), .retire_branch_stall (retire_branch_stall ), .retire_mad_ex_cancel (retire_mad_ex_cancel ), .retire_pcgen_curpc_update (retire_pcgen_curpc_update ), .retire_vector_expt_int_hv (retire_vector_expt_int_hv ), .retire_vector_expt_vld (retire_vector_expt_vld ), .retire_wb_dbg_in_ack (retire_wb_dbg_in_ack ), .retire_wb_hs_err_epc_sel (retire_wb_hs_err_epc_sel ), .retire_wb_mem_bkpt_fast_retire (retire_wb_mem_bkpt_fast_retire ), .retire_xx_normal_retire (retire_xx_normal_retire ), .special_retire_inst_wsc (special_retire_inst_wsc ), .wb_retire_fast_retire_load_pc (wb_retire_fast_retire_load_pc ), .wb_xx_acc_err_after_retire (wb_xx_acc_err_after_retire ), .wb_xx_lsu_check_fail_after_retire (wb_xx_lsu_check_fail_after_retire ) ); cr_iu_wb x_cr_iu_wb ( .branch_wb_cmp (branch_wb_cmp ), .branch_wb_jmp_reg (branch_wb_jmp_reg ), .cp0_yy_clk_en (cp0_yy_clk_en ), .cp0_yy_priv_mode (cp0_yy_priv_mode ), .cpurst_b (cpurst_b ), .ctrl_cp0_ex_data_sel (ctrl_cp0_ex_data_sel ), .ctrl_lsu_ex_data_sel (ctrl_lsu_ex_data_sel ), .decd_wb_tval (decd_wb_tval ), .decd_xx_inst_32bit (decd_xx_inst_32bit ), .decd_xx_unit_special_sel (decd_xx_unit_special_sel ), .forever_cpuclk (forever_cpuclk ), .ifu_iu_ex_int_spcu_mask (ifu_iu_ex_int_spcu_mask ), .ifu_iu_ex_int_spcu_vld (ifu_iu_ex_int_spcu_vld ), .ifu_iu_ex_split_on (ifu_iu_ex_split_on ), .iu_cp0_expt_tval (iu_cp0_expt_tval ), .iu_had_flush (iu_had_flush ), .iu_had_xx_data (iu_had_xx_data ), .iu_had_xx_data_vld (iu_had_xx_data_vld ), .iu_ifu_wb_ldst (iu_ifu_wb_ldst ), .iu_lsu_stall_without_hready (iu_lsu_stall_without_hready ), .iu_lsu_wb_ldst (iu_lsu_wb_ldst ), .iu_lsu_wb_load (iu_lsu_wb_load ), .iu_lsu_wb_store (iu_lsu_wb_store ), .iu_pad_gpr_data (iu_pad_gpr_data ), .iu_pad_gpr_index (iu_pad_gpr_index ), .iu_pad_gpr_we (iu_pad_gpr_we ), .iu_yy_xx_dbgon (iu_yy_xx_dbgon ), .iu_yy_xx_flush (iu_yy_xx_flush ), .lsu_iu_addr (lsu_iu_addr ), .lsu_iu_addr_vld (lsu_iu_addr_vld ), .lsu_iu_fast_retire (lsu_iu_fast_retire ), .lsu_iu_wb_acc_err (lsu_iu_wb_acc_err ), .lsu_iu_wb_bstack_chk_fail (lsu_iu_wb_bstack_chk_fail ), .lsu_iu_wb_cmplt (lsu_iu_wb_cmplt ), .lsu_iu_wb_data_vld (lsu_iu_wb_data_vld ), .lsu_iu_wb_load_data (lsu_iu_wb_load_data ), .misc_clk (misc_clk ), .oper_wb_rs1_equal_to_dst (oper_wb_rs1_equal_to_dst ), .oper_wb_rs2_equal_to_dst (oper_wb_rs2_equal_to_dst ), .pad_yy_gate_clk_en_b (pad_yy_gate_clk_en_b ), .pad_yy_test_mode (pad_yy_test_mode ), .pcgen_xx_cur_pc (pcgen_xx_cur_pc ), .randclk_wb_buf_mod_en_w32 (randclk_wb_buf_mod_en_w32 ), .randclk_wb_ctrl_mod_en_w2 (randclk_wb_ctrl_mod_en_w2 ), .randclk_wb_idx_mod_en_w5 (randclk_wb_idx_mod_en_w5 ), .rbus_wb_cmplt (rbus_wb_cmplt ), .rbus_wb_data (rbus_wb_data ), .rbus_wb_dst_reg (rbus_wb_dst_reg ), .rbus_wb_inst_cmplt (rbus_wb_inst_cmplt ), .rbus_wb_load (rbus_wb_load ), .rbus_wb_store (rbus_wb_store ), .retire_wb_dbg_in_ack (retire_wb_dbg_in_ack ), .retire_wb_hs_err_epc_sel (retire_wb_hs_err_epc_sel ), .retire_wb_mem_bkpt_fast_retire (retire_wb_mem_bkpt_fast_retire ), .wb_branch_dep_ld (wb_branch_dep_ld ), .wb_ctrl_stall (wb_ctrl_stall ), .wb_ctrl_stall_without_hready (wb_ctrl_stall_without_hready ), .wb_oper_fwd_data_no_load (wb_oper_fwd_data_no_load ), .wb_oper_fwd_en (wb_oper_fwd_en ), .wb_oper_write_data (wb_oper_write_data ), .wb_oper_write_en (wb_oper_write_en ), .wb_oper_write_idx (wb_oper_write_idx ), .wb_oper_write_idx_for_dep (wb_oper_write_idx_for_dep ), .wb_pcgen_ldst_stall (wb_pcgen_ldst_stall ), .wb_pcgen_pc_updt_val (wb_pcgen_pc_updt_val ), .wb_pcgen_switch_ld_pc (wb_pcgen_switch_ld_pc ), .wb_rbus_lsu_vec (wb_rbus_lsu_vec ), .wb_rbus_st_aft_load (wb_rbus_st_aft_load ), .wb_retire_fast_retire_load_pc (wb_retire_fast_retire_load_pc ), .wb_special_st_uncmplt (wb_special_st_uncmplt ), .wb_special_store (wb_special_store ), .wb_top_machine_mode_clk_en (wb_top_machine_mode_clk_en ), .wb_top_machine_sp_en_clk_en (wb_top_machine_sp_en_clk_en ), .wb_top_secu_mode_clk_en (wb_top_secu_mode_clk_en ), .wb_top_sp_adjust_clk_en (wb_top_sp_adjust_clk_en ), .wb_vector_ldst_wait_cmplt (wb_vector_ldst_wait_cmplt ), .wb_xx_acc_err_after_retire (wb_xx_acc_err_after_retire ), .wb_xx_lsu_check_fail_after_retire (wb_xx_lsu_check_fail_after_retire) ); cr_iu_pcgen x_cr_iu_pcgen ( .branch_pcgen_add_pc (branch_pcgen_add_pc ), .branch_pcgen_br_chgflw_vld (branch_pcgen_br_chgflw_vld ), .branch_pcgen_br_chgflw_vld_for_data (branch_pcgen_br_chgflw_vld_for_data ), .branch_pcgen_br_pc_chgflw_vld (branch_pcgen_br_pc_chgflw_vld ), .branch_pcgen_branch_chgflw_vld_for_data (branch_pcgen_branch_chgflw_vld_for_data), .branch_pcgen_jmp_chgflw_vld_for_data (branch_pcgen_jmp_chgflw_vld_for_data ), .branch_pcgen_reg_pc (branch_pcgen_reg_pc ), .cp0_iu_epc_for_chgflw (cp0_iu_epc_for_chgflw ), .cp0_iu_flush_chgflw_vld (cp0_iu_flush_chgflw_vld ), .cp0_iu_rte_chgflw_vld (cp0_iu_rte_chgflw_vld ), .cp0_iu_rte_chgflw_vld_for_data (cp0_iu_rte_chgflw_vld_for_data ), .cp0_yy_clk_en (cp0_yy_clk_en ), .cpurst_b (cpurst_b ), .forever_cpuclk (forever_cpuclk ), .had_iu_pc (had_iu_pc ), .had_iu_rte_pc_sel (had_iu_rte_pc_sel ), .had_yy_xx_exit_dbg (had_yy_xx_exit_dbg ), .hs_split_iu_unstack_chgflw (hs_split_iu_unstack_chgflw ), .ifu_iu_ibus_idle (ifu_iu_ibus_idle ), .ifu_iu_spcu_retire_mask (ifu_iu_spcu_retire_mask ), .ifu_iu_xx_ibus_data (ifu_iu_xx_ibus_data ), .iu_ifu_addr (iu_ifu_addr ), .iu_ifu_data_fetch (iu_ifu_data_fetch ), .iu_ifu_data_fetch_for_data (iu_ifu_data_fetch_for_data ), .iu_ifu_inst_fetch (iu_ifu_inst_fetch ), .iu_ifu_inst_fetch_for_data (iu_ifu_inst_fetch_for_data ), .iu_ifu_inst_fetch_without_dbg_disable (iu_ifu_inst_fetch_without_dbg_disable ), .iu_yy_xx_flush (iu_yy_xx_flush ), .iu_yy_xx_retire (iu_yy_xx_retire ), .misc_clk (misc_clk ), .nie_flush_chgflw (nie_flush_chgflw ), .pad_yy_gate_clk_en_b (pad_yy_gate_clk_en_b ), .pad_yy_test_mode (pad_yy_test_mode ), .pcgen_ctrl_stall (pcgen_ctrl_stall ), .pcgen_retire_updt_pc (pcgen_retire_updt_pc ), .pcgen_top_abort_clk_en (pcgen_top_abort_clk_en ), .pcgen_vector_expt_taken (pcgen_vector_expt_taken ), .pcgen_xx_cur_pc (pcgen_xx_cur_pc ), .pcgen_xx_ibus_idle (pcgen_xx_ibus_idle ), .randclk_pcgen_mod_en_w32 (randclk_pcgen_mod_en_w32 ), .retire_branch_stall (retire_branch_stall ), .retire_pcgen_curpc_update (retire_pcgen_curpc_update ), .retire_xx_normal_retire (retire_xx_normal_retire ), .special_pcgen_chgflw_vld (special_pcgen_chgflw_vld ), .vector_pcgen_buf_vbr (vector_pcgen_buf_vbr ), .vector_pcgen_chgflw_vld (vector_pcgen_chgflw_vld ), .vector_pcgen_cur_pc_vld (vector_pcgen_cur_pc_vld ), .vector_pcgen_enter_addr (vector_pcgen_enter_addr ), .vector_pcgen_ibus_req (vector_pcgen_ibus_req ), .wb_pcgen_ldst_stall (wb_pcgen_ldst_stall ), .wb_pcgen_pc_updt_val (wb_pcgen_pc_updt_val ), .wb_pcgen_switch_ld_pc (wb_pcgen_switch_ld_pc ), .wb_retire_fast_retire_load_pc (wb_retire_fast_retire_load_pc ) ); cr_iu_vector x_cr_iu_vector ( .bmu_xx_ibus_acc_err (bmu_xx_ibus_acc_err ), .bmu_xx_ibus_data_vld (bmu_xx_ibus_data_vld ), .bmu_xx_ibus_grnt (bmu_xx_ibus_grnt ), .cp0_iu_vbr (cp0_iu_vbr ), .cp0_vector_vec_err_vbr (cp0_vector_vec_err_vbr ), .cpurst_b (cpurst_b ), .ifu_iu_vector_ibus_in_idle (ifu_iu_vector_ibus_in_idle), .iu_bmu_vec_redirect (iu_bmu_vec_redirect ), .iu_cp0_syc_rst_b (iu_cp0_syc_rst_b ), .iu_ifu_inst_fetch_mask (iu_ifu_inst_fetch_mask ), .iu_sysyio_soft_rst (iu_sysyio_soft_rst ), .iu_yy_xx_reg_rst_b (iu_yy_xx_reg_rst_b ), .misc_clk (misc_clk ), .pcgen_vector_expt_taken (pcgen_vector_expt_taken ), .retire_vector_expt_int_hv (retire_vector_expt_int_hv ), .retire_vector_expt_vld (retire_vector_expt_vld ), .vec_top_clk_en (vec_top_clk_en ), .vector_cp0_vec_err (vector_cp0_vec_err ), .vector_cp0_vec_err_epc (vector_cp0_vec_err_epc ), .vector_cp0_vec_succeed (vector_cp0_vec_succeed ), .vector_ctrl_stall (vector_ctrl_stall ), .vector_pcgen_buf_vbr (vector_pcgen_buf_vbr ), .vector_pcgen_chgflw_vld (vector_pcgen_chgflw_vld ), .vector_pcgen_cur_pc_vld (vector_pcgen_cur_pc_vld ), .vector_pcgen_enter_addr (vector_pcgen_enter_addr ), .vector_pcgen_ibus_req (vector_pcgen_ibus_req ), .wb_vector_ldst_wait_cmplt (wb_vector_ldst_wait_cmplt ) ); cr_iu_ctrl x_cr_iu_ctrl ( .branch_ctrl_stall (branch_ctrl_stall ), .cp0_iu_stall (cp0_iu_stall ), .cp0_yy_priv_mode (cp0_yy_priv_mode ), .ctrl_alu_ex_data_sel (ctrl_alu_ex_data_sel ), .ctrl_alu_ex_sel (ctrl_alu_ex_sel ), .ctrl_alu_mad_oper_mux_en (ctrl_alu_mad_oper_mux_en ), .ctrl_alu_oper_mux_en (ctrl_alu_oper_mux_en ), .ctrl_branch_ex_data_sel (ctrl_branch_ex_data_sel ), .ctrl_branch_ex_sel (ctrl_branch_ex_sel ), .ctrl_cp0_ex_data_sel (ctrl_cp0_ex_data_sel ), .ctrl_lsu_ex_data_sel (ctrl_lsu_ex_data_sel ), .ctrl_mad_ex_data_sel (ctrl_mad_ex_data_sel ), .ctrl_mad_ex_sel (ctrl_mad_ex_sel ), .ctrl_mad_oper_mux_en (ctrl_mad_oper_mux_en ), .ctrl_oper_lsu_data_sel (ctrl_oper_lsu_data_sel ), .ctrl_retire_ni_vld (ctrl_retire_ni_vld ), .ctrl_special_ex_data_sel (ctrl_special_ex_data_sel ), .ctrl_special_ex_sel (ctrl_special_ex_sel ), .ctrl_special_expt_vec (ctrl_special_expt_vec ), .ctrl_special_expt_vld (ctrl_special_expt_vld ), .ctrl_xx_sp_adjust (ctrl_xx_sp_adjust ), .decd_ctrl_alu_sel (decd_ctrl_alu_sel ), .decd_ctrl_branch_sel (decd_ctrl_branch_sel ), .decd_ctrl_cp0_sel (decd_ctrl_cp0_sel ), .decd_ctrl_expt_bkpt (decd_ctrl_expt_bkpt ), .decd_ctrl_expt_ecall (decd_ctrl_expt_ecall ), .decd_ctrl_expt_inv (decd_ctrl_expt_inv ), .decd_ctrl_expt_wsc (decd_ctrl_expt_wsc ), .decd_ctrl_lsu_sel (decd_ctrl_lsu_sel ), .decd_ctrl_mad_sel (decd_ctrl_mad_sel ), .decd_xx_unit_special_sel (decd_xx_unit_special_sel ), .hs_split_iu_ctrl_inst_vld (hs_split_iu_ctrl_inst_vld), .ifu_iu_ex_expt_vld (ifu_iu_ex_expt_vld ), .ifu_iu_ex_inst_vld (ifu_iu_ex_inst_vld ), .ifu_iu_ex_ni (ifu_iu_ex_ni ), .ifu_iu_ex_prvlg_expt_vld (ifu_iu_ex_prvlg_expt_vld ), .ifu_iu_ex_rand_vld (ifu_iu_ex_rand_vld ), .iu_cp0_ecall (iu_cp0_ecall ), .iu_cp0_ex_data_sel (iu_cp0_ex_data_sel ), .iu_cp0_ex_sel (iu_cp0_ex_sel ), .iu_cp0_oper_mux_en (iu_cp0_oper_mux_en ), .iu_hs_split_ex_stall (iu_hs_split_ex_stall ), .iu_ifu_ex_stall (iu_ifu_ex_stall ), .iu_ifu_ex_stall_noinput (iu_ifu_ex_stall_noinput ), .iu_ifu_ex_vld (iu_ifu_ex_vld ), .iu_ifu_wb_stall (iu_ifu_wb_stall ), .iu_lsu_ex_data_sel (iu_lsu_ex_data_sel ), .iu_lsu_ex_sel (iu_lsu_ex_sel ), .iu_lsu_oper_mux_en (iu_lsu_oper_mux_en ), .lsu_iu_stall (lsu_iu_stall ), .lsu_iu_stall_noinput (lsu_iu_stall_noinput ), .mad_ctrl_stall (mad_ctrl_stall ), .mad_ctrl_stall_noinput (mad_ctrl_stall_noinput ), .pcgen_ctrl_stall (pcgen_ctrl_stall ), .vector_ctrl_stall (vector_ctrl_stall ), .wb_ctrl_stall (wb_ctrl_stall ) ); cr_iu_randclk x_cr_iu_randclk ( .randclk_mad_mod_en_w2 (randclk_mad_mod_en_w2 ), .randclk_oper_gpr_mod_en_w32 (randclk_oper_gpr_mod_en_w32), .randclk_pcgen_mod_en_w32 (randclk_pcgen_mod_en_w32 ), .randclk_retire_mod_en_w2 (randclk_retire_mod_en_w2 ), .randclk_wb_buf_mod_en_w32 (randclk_wb_buf_mod_en_w32 ), .randclk_wb_ctrl_mod_en_w2 (randclk_wb_ctrl_mod_en_w2 ), .randclk_wb_idx_mod_en_w5 (randclk_wb_idx_mod_en_w5 ) ); cr_iu_hs_split x_cr_iu_hs_split ( .hs_split_iu_ctrl_inst_vld (hs_split_iu_ctrl_inst_vld ), .hs_split_iu_dp_inst_op (hs_split_iu_dp_inst_op ), .hs_split_iu_hs_retire_mask (hs_split_iu_hs_retire_mask ), .hs_split_iu_hs_switch_se (hs_split_iu_hs_switch_se ), .hs_split_iu_nsinst_gpr_rst_b (hs_split_iu_nsinst_gpr_rst_b), .hs_split_iu_unstack_chgflw (hs_split_iu_unstack_chgflw ), .iu_hs_split_ex_stall (iu_hs_split_ex_stall ), .iu_ifu_spcu_int_en (iu_ifu_spcu_int_en ), .split_ifctrl_hs_stall (split_ifctrl_hs_stall ), .split_ifctrl_hs_stall_part (split_ifctrl_hs_stall_part ) ); assign iu_ifu_security_violation = 1'b0; endmodule module cr_iu_vector( bmu_xx_ibus_acc_err, bmu_xx_ibus_data_vld, bmu_xx_ibus_grnt, cp0_iu_vbr, cp0_vector_vec_err_vbr, cpurst_b, ifu_iu_vector_ibus_in_idle, iu_bmu_vec_redirect, iu_cp0_syc_rst_b, iu_ifu_inst_fetch_mask, iu_sysyio_soft_rst, iu_yy_xx_reg_rst_b, misc_clk, pcgen_vector_expt_taken, retire_vector_expt_int_hv, retire_vector_expt_vld, vec_top_clk_en, vector_cp0_vec_err, vector_cp0_vec_err_epc, vector_cp0_vec_succeed, vector_ctrl_stall, vector_pcgen_buf_vbr, vector_pcgen_chgflw_vld, vector_pcgen_cur_pc_vld, vector_pcgen_enter_addr, vector_pcgen_ibus_req, wb_vector_ldst_wait_cmplt ); input bmu_xx_ibus_acc_err; input bmu_xx_ibus_data_vld; input bmu_xx_ibus_grnt; input [29:0] cp0_iu_vbr; input [29:0] cp0_vector_vec_err_vbr; input cpurst_b; input ifu_iu_vector_ibus_in_idle; input misc_clk; input pcgen_vector_expt_taken; input retire_vector_expt_int_hv; input retire_vector_expt_vld; input wb_vector_ldst_wait_cmplt; output iu_bmu_vec_redirect; output iu_cp0_syc_rst_b; output iu_ifu_inst_fetch_mask; output iu_sysyio_soft_rst; output iu_yy_xx_reg_rst_b; output vec_top_clk_en; output vector_cp0_vec_err; output [29:0] vector_cp0_vec_err_epc; output vector_cp0_vec_succeed; output vector_ctrl_stall; output vector_pcgen_buf_vbr; output vector_pcgen_chgflw_vld; output vector_pcgen_cur_pc_vld; output [30:0] vector_pcgen_enter_addr; output vector_pcgen_ibus_req; reg [3 :0] cur_state; reg [3 :0] next_state; wire bmu_xx_ibus_acc_err; wire bmu_xx_ibus_data_vld; wire bmu_xx_ibus_grnt; wire [29:0] cp0_iu_vbr; wire [29:0] cp0_vector_vec_err_vbr; wire cpurst_b; wire expt_non_vec; wire hs_split_iu_hs_stall_vector; wire ifu_iu_vector_ibus_in_idle; wire iu_bmu_vec_redirect; wire iu_cp0_syc_rst_b; wire iu_ifu_inst_fetch_mask; wire iu_sysyio_soft_rst; wire iu_yy_xx_hs_acc_err; wire iu_yy_xx_reg_rst_b; wire misc_clk; wire pcgen_vector_expt_taken; wire reg_rst_b; wire retire_vector_expt_int_hv; wire retire_vector_expt_vld; wire vec_top_clk_en; wire vector_cp0_vec_err; wire [29:0] vector_cp0_vec_err_epc; wire vector_cp0_vec_succeed; wire vector_ctrl_stall; wire vector_cur_pc_vld; wire vector_pcgen_buf_vbr; wire vector_pcgen_chgflw_vld; wire vector_pcgen_cur_pc_vld; wire [30:0] vector_pcgen_enter_addr; wire vector_pcgen_ibus_req; wire wb_vector_ldst_wait_cmplt; parameter IDLE = 4'b0000; parameter BUF_VBR = 4'b0001; parameter WAIT_IDLE = 4'b0010; parameter WAIT_GRANT = 4'b0011; parameter WAIT_DATA = 4'b0100; parameter NONVEC_WAIT = 4'b0101; parameter NONVEC_WAIT_IDLE = 4'b0110; parameter VEC_ERR = 4'b0111; assign vector_pcgen_enter_addr[30:1] = (cur_state == VEC_ERR) ? cp0_vector_vec_err_vbr[29:0] : cp0_iu_vbr[29:0]; assign vector_pcgen_enter_addr[0] = 1'b0; assign iu_ifu_inst_fetch_mask = !(cur_state == IDLE); assign vec_top_clk_en = (cur_state == IDLE) && retire_vector_expt_vld || (cur_state != IDLE) || iu_yy_xx_hs_acc_err; assign reg_rst_b =1'b1; assign iu_yy_xx_reg_rst_b = reg_rst_b; assign iu_cp0_syc_rst_b = reg_rst_b; assign iu_sysyio_soft_rst = 1'b1; assign iu_bmu_vec_redirect = 1'b0; assign iu_yy_xx_hs_acc_err =1'b0; assign hs_split_iu_hs_stall_vector = 1'b0; always @(posedge misc_clk or negedge cpurst_b) begin if(!cpurst_b) cur_state[3:0] <= IDLE; else cur_state[3:0] <= next_state[3:0]; end assign expt_non_vec = !retire_vector_expt_int_hv ; always @( cur_state or iu_yy_xx_hs_acc_err or ifu_iu_vector_ibus_in_idle or bmu_xx_ibus_data_vld or pcgen_vector_expt_taken or bmu_xx_ibus_acc_err or expt_non_vec or hs_split_iu_hs_stall_vector or retire_vector_expt_vld or wb_vector_ldst_wait_cmplt or bmu_xx_ibus_grnt) begin case(cur_state) IDLE : if((retire_vector_expt_vld)) next_state = expt_non_vec ? NONVEC_WAIT : BUF_VBR; else if(iu_yy_xx_hs_acc_err) next_state = NONVEC_WAIT; else next_state = IDLE; NONVEC_WAIT: if(wb_vector_ldst_wait_cmplt) next_state = NONVEC_WAIT; else if(iu_yy_xx_hs_acc_err) next_state = NONVEC_WAIT; else if(hs_split_iu_hs_stall_vector) next_state = NONVEC_WAIT; else next_state = NONVEC_WAIT_IDLE; NONVEC_WAIT_IDLE: if(pcgen_vector_expt_taken) next_state = IDLE; else next_state = NONVEC_WAIT_IDLE; BUF_VBR : if(wb_vector_ldst_wait_cmplt) next_state = BUF_VBR; else if(iu_yy_xx_hs_acc_err) next_state = NONVEC_WAIT; else if(hs_split_iu_hs_stall_vector) next_state = BUF_VBR; else next_state = WAIT_IDLE; WAIT_IDLE : if(ifu_iu_vector_ibus_in_idle && !bmu_xx_ibus_grnt) next_state = WAIT_GRANT; else if(ifu_iu_vector_ibus_in_idle) next_state = WAIT_DATA; else next_state = WAIT_IDLE; WAIT_GRANT : if(bmu_xx_ibus_grnt) next_state = WAIT_DATA; else next_state = WAIT_GRANT; WAIT_DATA : if(bmu_xx_ibus_data_vld) next_state = IDLE; else if(bmu_xx_ibus_acc_err) next_state = VEC_ERR; else next_state = WAIT_DATA; VEC_ERR : next_state = IDLE; default : next_state = IDLE; endcase end assign vector_pcgen_buf_vbr = ((cur_state == BUF_VBR) && (next_state == WAIT_IDLE)) || ((cur_state == NONVEC_WAIT_IDLE) && (next_state == IDLE)) || (cur_state == VEC_ERR); assign vector_pcgen_ibus_req = (cur_state == WAIT_IDLE) && ifu_iu_vector_ibus_in_idle || (cur_state == WAIT_GRANT); assign vector_cur_pc_vld = (cur_state == VEC_ERR) || (cur_state == WAIT_DATA) && bmu_xx_ibus_data_vld || ((cur_state == NONVEC_WAIT_IDLE) && (next_state == IDLE)) ; assign vector_pcgen_cur_pc_vld = (cur_state == WAIT_DATA) && bmu_xx_ibus_data_vld; assign vector_pcgen_chgflw_vld = vector_cur_pc_vld; assign vector_ctrl_stall = (cur_state!=IDLE); assign vector_cp0_vec_err = (cur_state == VEC_ERR); assign vector_cp0_vec_err_epc[29:0] = cp0_iu_vbr[29:0]; assign vector_cp0_vec_succeed = (cur_state == WAIT_DATA) && bmu_xx_ibus_data_vld; endmodule module cr_iu_wb( branch_wb_cmp, branch_wb_jmp_reg, cp0_yy_clk_en, cp0_yy_priv_mode, cpurst_b, ctrl_cp0_ex_data_sel, ctrl_lsu_ex_data_sel, decd_wb_tval, decd_xx_inst_32bit, decd_xx_unit_special_sel, forever_cpuclk, ifu_iu_ex_int_spcu_mask, ifu_iu_ex_int_spcu_vld, ifu_iu_ex_split_on, iu_cp0_expt_tval, iu_had_flush, iu_had_xx_data, iu_had_xx_data_vld, iu_ifu_wb_ldst, iu_lsu_stall_without_hready, iu_lsu_wb_ldst, iu_lsu_wb_load, iu_lsu_wb_store, iu_pad_gpr_data, iu_pad_gpr_index, iu_pad_gpr_we, iu_yy_xx_dbgon, iu_yy_xx_flush, lsu_iu_addr, lsu_iu_addr_vld, lsu_iu_fast_retire, lsu_iu_wb_acc_err, lsu_iu_wb_bstack_chk_fail, lsu_iu_wb_cmplt, lsu_iu_wb_data_vld, lsu_iu_wb_load_data, misc_clk, oper_wb_rs1_equal_to_dst, oper_wb_rs2_equal_to_dst, pad_yy_gate_clk_en_b, pad_yy_test_mode, pcgen_xx_cur_pc, randclk_wb_buf_mod_en_w32, randclk_wb_ctrl_mod_en_w2, randclk_wb_idx_mod_en_w5, rbus_wb_cmplt, rbus_wb_data, rbus_wb_dst_reg, rbus_wb_inst_cmplt, rbus_wb_load, rbus_wb_store, retire_wb_dbg_in_ack, retire_wb_hs_err_epc_sel, retire_wb_mem_bkpt_fast_retire, wb_branch_dep_ld, wb_ctrl_stall, wb_ctrl_stall_without_hready, wb_oper_fwd_data_no_load, wb_oper_fwd_en, wb_oper_write_data, wb_oper_write_en, wb_oper_write_idx, wb_oper_write_idx_for_dep, wb_pcgen_ldst_stall, wb_pcgen_pc_updt_val, wb_pcgen_switch_ld_pc, wb_rbus_lsu_vec, wb_rbus_st_aft_load, wb_retire_fast_retire_load_pc, wb_special_st_uncmplt, wb_special_store, wb_top_machine_mode_clk_en, wb_top_machine_sp_en_clk_en, wb_top_secu_mode_clk_en, wb_top_sp_adjust_clk_en, wb_vector_ldst_wait_cmplt, wb_xx_acc_err_after_retire, wb_xx_lsu_check_fail_after_retire ); input branch_wb_cmp; input branch_wb_jmp_reg; input cp0_yy_clk_en; input [1 :0] cp0_yy_priv_mode; input cpurst_b; input ctrl_cp0_ex_data_sel; input ctrl_lsu_ex_data_sel; input [31:0] decd_wb_tval; input decd_xx_inst_32bit; input decd_xx_unit_special_sel; input forever_cpuclk; input ifu_iu_ex_int_spcu_mask; input ifu_iu_ex_int_spcu_vld; input ifu_iu_ex_split_on; input iu_yy_xx_dbgon; input iu_yy_xx_flush; input [31:0] lsu_iu_addr; input lsu_iu_addr_vld; input lsu_iu_fast_retire; input lsu_iu_wb_acc_err; input lsu_iu_wb_bstack_chk_fail; input lsu_iu_wb_cmplt; input lsu_iu_wb_data_vld; input [31:0] lsu_iu_wb_load_data; input misc_clk; input oper_wb_rs1_equal_to_dst; input oper_wb_rs2_equal_to_dst; input pad_yy_gate_clk_en_b; input pad_yy_test_mode; input [30:0] pcgen_xx_cur_pc; input randclk_wb_buf_mod_en_w32; input randclk_wb_ctrl_mod_en_w2; input randclk_wb_idx_mod_en_w5; input rbus_wb_cmplt; input [31:0] rbus_wb_data; input [4 :0] rbus_wb_dst_reg; input rbus_wb_inst_cmplt; input rbus_wb_load; input rbus_wb_store; input retire_wb_dbg_in_ack; input retire_wb_hs_err_epc_sel; input retire_wb_mem_bkpt_fast_retire; output [31:0] iu_cp0_expt_tval; output iu_had_flush; output [31:0] iu_had_xx_data; output iu_had_xx_data_vld; output iu_ifu_wb_ldst; output iu_lsu_stall_without_hready; output iu_lsu_wb_ldst; output iu_lsu_wb_load; output iu_lsu_wb_store; output [31:0] iu_pad_gpr_data; output [4 :0] iu_pad_gpr_index; output iu_pad_gpr_we; output wb_branch_dep_ld; output wb_ctrl_stall; output wb_ctrl_stall_without_hready; output [31:0] wb_oper_fwd_data_no_load; output wb_oper_fwd_en; output [31:0] wb_oper_write_data; output wb_oper_write_en; output [4 :0] wb_oper_write_idx; output [4 :0] wb_oper_write_idx_for_dep; output wb_pcgen_ldst_stall; output [30:0] wb_pcgen_pc_updt_val; output wb_pcgen_switch_ld_pc; output [4 :0] wb_rbus_lsu_vec; output wb_rbus_st_aft_load; output [30:0] wb_retire_fast_retire_load_pc; output wb_special_st_uncmplt; output wb_special_store; output wb_top_machine_mode_clk_en; output wb_top_machine_sp_en_clk_en; output wb_top_secu_mode_clk_en; output wb_top_sp_adjust_clk_en; output wb_vector_ldst_wait_cmplt; output wb_xx_acc_err_after_retire; output wb_xx_lsu_check_fail_after_retire; reg [1 :0] cur_state; reg ex_wb_split_on; reg [1 :0] next_state; reg [31:0] wb_data_buffer; reg [4 :0] wb_idx_buffer; reg wb_inst_32; reg wb_int_spcu_inst; reg wb_int_spcu_mask; wire branch_wb_cmp; wire branch_wb_jmp_reg; wire cp0_yy_clk_en; wire cp0_yy_machine_mode; wire cp0_yy_machine_mode_post; wire [1 :0] cp0_yy_priv_mode; wire cpurst_b; wire ctrl_cp0_ex_data_sel; wire ctrl_lsu_ex_data_sel; wire [31:0] decd_wb_tval; wire decd_xx_inst_32bit; wire decd_xx_unit_special_sel; wire forever_cpuclk; wire ifu_iu_ex_int_spcu_mask; wire ifu_iu_ex_int_spcu_vld; wire ifu_iu_ex_split_on; wire [31:0] iu_cp0_expt_tval; wire iu_had_flush; wire [31:0] iu_had_xx_data; wire iu_had_xx_data_vld; wire iu_ifu_wb_ldst; wire iu_lsu_stall_without_hready; wire iu_lsu_wb_ldst; wire iu_lsu_wb_load; wire iu_lsu_wb_store; wire [31:0] iu_pad_gpr_data; wire [4 :0] iu_pad_gpr_index; wire iu_pad_gpr_we; wire iu_yy_xx_dbgon; wire iu_yy_xx_flush; wire ldst_stall; wire [31:0] lsu_iu_addr; wire lsu_iu_addr_vld; wire lsu_iu_fast_retire; wire lsu_iu_wb_acc_err; wire lsu_iu_wb_bstack_chk_fail; wire lsu_iu_wb_cmplt; wire lsu_iu_wb_data_vld; wire [31:0] lsu_iu_wb_load_data; wire misc_clk; wire [1 :0] next_cmplt_state; wire oper_wb_rs1_equal_to_dst; wire oper_wb_rs2_equal_to_dst; wire pad_yy_gate_clk_en_b; wire pad_yy_test_mode; wire [30:0] pcgen_xx_cur_pc; wire [30:0] pcgen_xx_cur_pc_mask; wire randclk_wb_buf_mod_en_w32; wire randclk_wb_ctrl_mod_en_w2; wire randclk_wb_idx_mod_en_w5; wire rbus_wb_cmplt; wire [31:0] rbus_wb_data; wire [4 :0] rbus_wb_dst_reg; wire rbus_wb_inst_cmplt; wire rbus_wb_load; wire rbus_wb_store; wire retire_wb_dbg_in_ack; wire retire_wb_hs_err_epc_sel; wire retire_wb_mem_bkpt_fast_retire; wire wb_acc_err_after_retire; wire wb_alu_or_load_wen; wire wb_branch_dep_ld; wire wb_buf_stall; wire wb_buf_stall_without_hready; wire wb_check_fail_after_retire; wire wb_clk; wire wb_clk_en; wire wb_cmplt_write_back; wire wb_ctrl_load_fwd_non_alu; wire wb_ctrl_stall; wire wb_ctrl_stall_without_bctm; wire wb_ctrl_stall_without_bctm_without_hready; wire wb_ctrl_stall_without_hready; wire wb_data_buf_0_16_update; wire wb_data_buf_16_0_clk; wire wb_data_buf_16_0_clk_en; wire [31:0] wb_data_buffer_post; wire wb_data_buffer_update; wire wb_dst_reg_22; wire wb_dst_reg_23; wire wb_dst_reg_24; wire wb_dst_reg_25; wire wb_dst_reg_30; wire wb_dst_reg_high_16; wire wb_dst_reg_valid; wire wb_ex_cmplt; wire wb_fast_retire_pc_mask; wire [1 :0] wb_fast_retire_pc_offset; wire wb_idx_buf_3_0_clk; wire wb_idx_buf_3_0_clk_en; wire wb_idx_buf_3_0_update; wire wb_idx_buf_update; wire [4 :0] wb_idx_for_dep; wire wb_int_spcu_epc_mask; wire wb_int_spcu_expt_mask; wire wb_ldst; wire wb_load_fwd_mad; wire [31:0] wb_oper_fwd_data_no_load; wire wb_oper_fwd_en; wire wb_oper_machine_mode; wire [31:0] wb_oper_write_data; wire wb_oper_write_en; wire [4 :0] wb_oper_write_idx; wire [4 :0] wb_oper_write_idx_for_dep; wire wb_pcgen_ldst_stall; wire [30:0] wb_pcgen_pc_updt_val; wire wb_pcgen_switch_ld_pc; wire [4 :0] wb_rbus_lsu_vec; wire wb_rbus_st_aft_load; wire [30:0] wb_retire_fast_retire_load_pc; wire wb_sp_wen_stall; wire wb_special_st_uncmplt; wire wb_special_store; wire wb_store_aft_load; wire wb_top_machine_mode_clk_en; wire wb_top_machine_sp_en_clk_en; wire wb_top_secu_mode_clk_en; wire wb_top_sp_adjust_clk_en; wire wb_uncmplt_load; wire wb_uncmplt_store; wire wb_vector_ldst_wait_cmplt; wire wb_write_back; wire [31:0] wb_write_back_data; wire [31:0] wb_write_back_data_without_pol; wire wb_write_back_en; wire wb_xx_acc_err_after_retire; wire wb_xx_lsu_check_fail_after_retire; parameter IDLE = 2'b00; parameter LOAD = 2'b11; parameter STORE = 2'b10; parameter ALU = 2'b01; assign wb_clk_en = (cur_state != IDLE) || wb_ex_cmplt; gated_clk_cell x_wb_gated_clk ( .clk_in (forever_cpuclk ), .clk_out (wb_clk ), .external_en (1'b0 ), .global_en (cp0_yy_clk_en ), .local_en (wb_clk_en ), .module_en (randclk_wb_ctrl_mod_en_w2), .pad_yy_gate_clk_en_b (pad_yy_gate_clk_en_b ), .pad_yy_test_mode (pad_yy_test_mode ) ); assign wb_data_buf_16_0_clk_en = wb_data_buf_0_16_update; gated_clk_cell x_wb_data_buf_16_0_gated_clk ( .clk_in (forever_cpuclk ), .clk_out (wb_data_buf_16_0_clk ), .external_en (1'b0 ), .global_en (cp0_yy_clk_en ), .local_en (wb_data_buf_16_0_clk_en ), .module_en (randclk_wb_buf_mod_en_w32), .pad_yy_gate_clk_en_b (pad_yy_gate_clk_en_b ), .pad_yy_test_mode (pad_yy_test_mode ) ); assign wb_idx_buf_update = wb_cmplt_write_back || wb_uncmplt_load; assign wb_idx_buf_3_0_update = wb_idx_buf_update; assign wb_idx_buf_3_0_clk_en = wb_idx_buf_3_0_update; gated_clk_cell x_idx_buf_3_0_gated_clk ( .clk_in (forever_cpuclk ), .clk_out (wb_idx_buf_3_0_clk ), .external_en (1'b0 ), .global_en (cp0_yy_clk_en ), .local_en (wb_idx_buf_3_0_clk_en ), .module_en (randclk_wb_idx_mod_en_w5), .pad_yy_gate_clk_en_b (pad_yy_gate_clk_en_b ), .pad_yy_test_mode (pad_yy_test_mode ) ); always @(posedge wb_clk or negedge cpurst_b) begin if(!cpurst_b) cur_state[1:0] <= IDLE; else cur_state[1:0] <= next_state[1:0]; end assign wb_uncmplt_load = rbus_wb_load; assign wb_uncmplt_store = rbus_wb_store; assign wb_cmplt_write_back = rbus_wb_cmplt; assign wb_ex_cmplt = wb_uncmplt_load || wb_uncmplt_store || wb_cmplt_write_back; assign next_cmplt_state[1:0] = {2{wb_uncmplt_load}} & LOAD | {2{wb_uncmplt_store}} & STORE | {2{wb_cmplt_write_back}} & ALU; always @( cur_state or wb_ex_cmplt or next_cmplt_state or lsu_iu_wb_cmplt) begin case(cur_state) IDLE : if(wb_ex_cmplt) next_state = next_cmplt_state; else next_state = IDLE; LOAD : if(lsu_iu_wb_cmplt && wb_ex_cmplt) next_state = next_cmplt_state; else if(lsu_iu_wb_cmplt && !wb_ex_cmplt) next_state = IDLE; else next_state = LOAD; STORE : if(lsu_iu_wb_cmplt && wb_ex_cmplt) next_state = next_cmplt_state; else if(lsu_iu_wb_cmplt && !wb_ex_cmplt) next_state = IDLE; else next_state = STORE; ALU : if(wb_ex_cmplt) next_state = next_cmplt_state; else next_state = IDLE; default : next_state = IDLE; endcase end assign wb_alu_or_load_wen = ((cur_state == LOAD) && lsu_iu_wb_cmplt && lsu_iu_wb_data_vld || (cur_state == ALU)); assign wb_write_back_en = wb_alu_or_load_wen && wb_dst_reg_valid; assign wb_write_back = ((cur_state == ALU) || (cur_state == LOAD)) && wb_dst_reg_valid; assign wb_acc_err_after_retire = ((cur_state == LOAD) || (cur_state == STORE)) && lsu_iu_wb_cmplt && lsu_iu_wb_acc_err && !wb_int_spcu_expt_mask; assign wb_xx_acc_err_after_retire = wb_acc_err_after_retire; assign wb_ldst = ((cur_state == LOAD) || (cur_state == STORE)); assign iu_lsu_wb_ldst = wb_ldst; assign iu_ifu_wb_ldst = wb_ldst; assign iu_lsu_wb_load = cur_state == LOAD; assign iu_lsu_wb_store = cur_state == STORE; assign wb_special_store = cur_state == STORE; assign wb_special_st_uncmplt = cur_state == STORE && !lsu_iu_wb_cmplt; assign wb_oper_machine_mode = 1'b0; assign cp0_yy_machine_mode_post = cp0_yy_machine_mode; assign wb_top_machine_mode_clk_en = cp0_yy_machine_mode_post ^ wb_oper_machine_mode; assign cp0_yy_machine_mode = cp0_yy_priv_mode[1:0] == 2'b11; assign wb_top_secu_mode_clk_en = 1'b0; assign wb_top_machine_sp_en_clk_en = 1'b0; always @(posedge misc_clk or negedge cpurst_b) begin if(!cpurst_b) wb_int_spcu_inst <= 1'b0; else if(rbus_wb_inst_cmplt) wb_int_spcu_inst <= ifu_iu_ex_int_spcu_vld; end always @(posedge misc_clk or negedge cpurst_b) begin if(!cpurst_b) wb_int_spcu_mask <= 1'b0; else if(rbus_wb_inst_cmplt) wb_int_spcu_mask <= ifu_iu_ex_int_spcu_mask; end assign wb_int_spcu_epc_mask = wb_int_spcu_inst; assign wb_int_spcu_expt_mask = wb_int_spcu_mask; assign wb_top_sp_adjust_clk_en = (ifu_iu_ex_int_spcu_vld ^ wb_int_spcu_inst) || (ifu_iu_ex_int_spcu_mask ^ wb_int_spcu_mask); always @(posedge wb_clk or negedge cpurst_b) begin if(!cpurst_b) wb_inst_32 <= 1'b0; else if(lsu_iu_fast_retire) wb_inst_32 <= decd_xx_inst_32bit; end always @(posedge wb_clk or negedge cpurst_b) begin if(!cpurst_b) ex_wb_split_on <= 1'b0; else if(lsu_iu_fast_retire) ex_wb_split_on <= ifu_iu_ex_split_on; end assign wb_check_fail_after_retire = ((cur_state == LOAD) || (cur_state == STORE)) && lsu_iu_wb_bstack_chk_fail; assign wb_xx_lsu_check_fail_after_retire = wb_check_fail_after_retire; assign wb_buf_stall = ((cur_state == LOAD) || (cur_state == STORE)) && !(lsu_iu_wb_cmplt && !lsu_iu_wb_acc_err && !lsu_iu_wb_bstack_chk_fail) || retire_wb_dbg_in_ack; assign wb_buf_stall_without_hready = ((cur_state == LOAD) || (cur_state == STORE)) && (lsu_iu_wb_acc_err || lsu_iu_wb_bstack_chk_fail) || retire_wb_dbg_in_ack; assign ldst_stall = ((cur_state == LOAD) || (cur_state == STORE)) && !lsu_iu_wb_cmplt; assign wb_pcgen_ldst_stall = ldst_stall; assign wb_data_buffer_post[31:0] = lsu_iu_addr_vld ? lsu_iu_addr[31:0] : rbus_wb_data[31:0]; assign wb_data_buffer_update = wb_cmplt_write_back || rbus_wb_inst_cmplt || lsu_iu_addr_vld && !ldst_stall; assign wb_store_aft_load = (cur_state == LOAD) && (wb_uncmplt_store || (next_state == IDLE)); assign wb_rbus_st_aft_load = wb_store_aft_load; assign wb_rbus_lsu_vec[4:0] = cur_state == LOAD ? 5'b00101 : 5'b00111; assign wb_data_buf_0_16_update = wb_data_buffer_update || wb_store_aft_load; always @(posedge wb_data_buf_16_0_clk or negedge cpurst_b) begin if(!cpurst_b) wb_data_buffer[31:0] <= 32'b0; else if(wb_data_buf_0_16_update) wb_data_buffer[31:0] <= wb_data_buffer_post[31:0]; else wb_data_buffer[31:0] <= wb_data_buffer[31:0]; end assign wb_fast_retire_pc_mask = !ex_wb_split_on && lsu_iu_wb_acc_err && !wb_int_spcu_epc_mask; assign wb_fast_retire_pc_offset[1:0] = {2{wb_fast_retire_pc_mask}} & {wb_inst_32,!wb_inst_32} | {retire_wb_hs_err_epc_sel,1'b0}; assign pcgen_xx_cur_pc_mask[30:8] = pcgen_xx_cur_pc[30:8]; assign pcgen_xx_cur_pc_mask[7:0] = pcgen_xx_cur_pc[7:0] & {8{lsu_iu_wb_acc_err || retire_wb_hs_err_epc_sel}}; assign wb_retire_fast_retire_load_pc[30:0] = pcgen_xx_cur_pc_mask[30:0] - wb_fast_retire_pc_offset[1:0]; assign wb_vector_ldst_wait_cmplt = ((cur_state == LOAD) || (cur_state == STORE)) && !lsu_iu_wb_cmplt; always @(posedge wb_idx_buf_3_0_clk or negedge cpurst_b) begin if(!cpurst_b) wb_idx_buffer[4:0] <= 5'b0; else if(wb_idx_buf_3_0_update) wb_idx_buffer[4:0] <= rbus_wb_dst_reg[4:0]; else wb_idx_buffer[4:0] <= wb_idx_buffer[4:0]; end assign wb_dst_reg_30 = 1'b0; assign wb_dst_reg_25 = 1'b0; assign wb_dst_reg_24 = 1'b0; assign wb_dst_reg_23 = 1'b0; assign wb_dst_reg_22 = 1'b0; assign wb_dst_reg_high_16 = wb_idx_buffer[4] && !wb_dst_reg_30 && !wb_dst_reg_25 && !wb_dst_reg_24 && !wb_dst_reg_23 && !wb_dst_reg_22; assign wb_dst_reg_valid = !wb_dst_reg_high_16 && wb_idx_buffer[4:0] != 5'd0; assign wb_write_back_data[31:0] = (cur_state == LOAD) ? lsu_iu_wb_load_data[31:0] : wb_data_buffer[31:0]; assign wb_write_back_data_without_pol[31:0] = wb_write_back_data[31:0]; assign wb_oper_write_en = wb_write_back_en; assign wb_pcgen_switch_ld_pc = 1'b0; assign wb_pcgen_pc_updt_val[30:0] = 31'b0; assign wb_oper_write_idx[4:0] = wb_idx_buffer[4:0]; assign wb_idx_for_dep[4:0] = wb_idx_buffer[4:0]; assign wb_oper_write_idx_for_dep[4:0] = wb_idx_for_dep[4:0]; assign wb_oper_write_data[31:0] = wb_write_back_data[31:0]; assign wb_oper_fwd_en = wb_write_back; assign wb_oper_fwd_data_no_load[31:0] = wb_data_buffer[31:0]; assign iu_pad_gpr_we = wb_write_back_en; assign iu_pad_gpr_index[4:0] = wb_idx_buffer[4:0]; assign iu_pad_gpr_data[31:0] = wb_write_back_data_without_pol[31:0]; assign iu_had_xx_data_vld = wb_write_back_en && iu_yy_xx_dbgon; assign iu_had_xx_data[31:0] = wb_write_back_data_without_pol[31:0]; assign iu_had_flush = iu_yy_xx_flush; assign wb_ctrl_load_fwd_non_alu = (cur_state == LOAD) &&(oper_wb_rs1_equal_to_dst && (branch_wb_jmp_reg || ctrl_lsu_ex_data_sel || ctrl_cp0_ex_data_sel) || branch_wb_cmp && (oper_wb_rs2_equal_to_dst || oper_wb_rs1_equal_to_dst)); assign wb_branch_dep_ld = wb_ctrl_load_fwd_non_alu || (cur_state == LOAD) || (cur_state == STORE); assign wb_load_fwd_mad = 1'b0; assign wb_sp_wen_stall = 1'b0; assign wb_ctrl_stall_without_bctm = wb_buf_stall || wb_ctrl_load_fwd_non_alu || wb_load_fwd_mad || wb_sp_wen_stall; assign wb_ctrl_stall_without_bctm_without_hready = wb_buf_stall_without_hready || wb_ctrl_load_fwd_non_alu || wb_load_fwd_mad || wb_sp_wen_stall; assign wb_ctrl_stall = wb_ctrl_stall_without_bctm; assign wb_ctrl_stall_without_hready = wb_ctrl_stall_without_bctm_without_hready; assign iu_lsu_stall_without_hready = wb_ctrl_stall_without_hready; assign iu_cp0_expt_tval[31:0] = wb_acc_err_after_retire ? wb_data_buffer[31:0]: decd_xx_unit_special_sel ? decd_wb_tval[31:0]: retire_wb_mem_bkpt_fast_retire ? wb_data_buffer[31:0]: lsu_iu_addr[31:0]; endmodule module cr_lsu_ctrl( bmu_lsu_acc_err, bmu_lsu_bstack_chk_fail, bmu_lsu_data_vld, bmu_lsu_grnt, bmu_lsu_trans_cmplt, cpurst_b, ctrl_dp_ldst_info_buf_reuse, ctrl_dp_ldst_req_grnt, ctrl_dp_store_buffer_updt, ctrl_top_req_en, dp_ctrl_misalign, iu_lsu_ex_data_sel, iu_lsu_ex_sel, iu_lsu_ex_store, iu_lsu_oper_mux_en, iu_lsu_stall_without_hready, iu_lsu_wb_ldst, iu_lsu_wb_load, iu_lsu_wb_store, iu_yy_xx_flush, lsu_bmu_addr_check_fail, lsu_bmu_idle, lsu_bmu_req, lsu_bmu_req_without_cmplt, lsu_bmu_sg_chk_fail, lsu_bmu_wfd1, lsu_had_addr_vld, lsu_had_ex_cmplt, lsu_inst_store, lsu_iu_data_vld, lsu_iu_expt_vec, lsu_iu_expt_vld, lsu_iu_fast_retire, lsu_iu_req, lsu_iu_stall, lsu_iu_stall_noinput, lsu_iu_wb_acc_err, lsu_iu_wb_bstack_chk_fail, lsu_iu_wb_cmplt, lsu_iu_wb_data_vld, lsu_iu_wfd, sm_clk, unalign_ctrl_not_last_beat, unalign_ctrl_stall, unalign_xx_split_on ); input bmu_lsu_acc_err; input bmu_lsu_bstack_chk_fail; input bmu_lsu_data_vld; input bmu_lsu_grnt; input bmu_lsu_trans_cmplt; input cpurst_b; input dp_ctrl_misalign; input iu_lsu_ex_data_sel; input iu_lsu_ex_sel; input iu_lsu_ex_store; input iu_lsu_oper_mux_en; input iu_lsu_stall_without_hready; input iu_lsu_wb_ldst; input iu_lsu_wb_load; input iu_lsu_wb_store; input iu_yy_xx_flush; input sm_clk; input unalign_ctrl_not_last_beat; input unalign_ctrl_stall; input unalign_xx_split_on; output ctrl_dp_ldst_info_buf_reuse; output ctrl_dp_ldst_req_grnt; output ctrl_dp_store_buffer_updt; output ctrl_top_req_en; output lsu_bmu_addr_check_fail; output lsu_bmu_idle; output lsu_bmu_req; output lsu_bmu_req_without_cmplt; output lsu_bmu_sg_chk_fail; output lsu_bmu_wfd1; output lsu_had_addr_vld; output lsu_had_ex_cmplt; output lsu_inst_store; output lsu_iu_data_vld; output [4:0] lsu_iu_expt_vec; output lsu_iu_expt_vld; output lsu_iu_fast_retire; output lsu_iu_req; output lsu_iu_stall; output lsu_iu_stall_noinput; output lsu_iu_wb_acc_err; output lsu_iu_wb_bstack_chk_fail; output lsu_iu_wb_cmplt; output lsu_iu_wb_data_vld; output lsu_iu_wfd; reg cur_state; reg next_state; wire bmu_lsu_acc_err; wire bmu_lsu_bstack_chk_fail; wire bmu_lsu_data_vld; wire bmu_lsu_grnt; wire bmu_lsu_trans_cmplt; wire cpurst_b; wire ctrl_dp_ldst_info_buf_reuse; wire ctrl_dp_ldst_req_grnt; wire ctrl_dp_store_buffer_updt; wire ctrl_top_req_en; wire dp_ctrl_misalign; wire fast_retire_grnt; wire idle_retire; wire iu_lsu_ex_data_sel; wire iu_lsu_ex_sel; wire iu_lsu_ex_store; wire iu_lsu_oper_mux_en; wire iu_lsu_stall_without_hready; wire iu_lsu_wb_ldst; wire iu_lsu_wb_load; wire iu_lsu_wb_store; wire iu_yy_xx_flush; wire lsu_addr_chk_fail; wire lsu_bmu_addr_check_fail; wire lsu_bmu_idle; wire lsu_bmu_req; wire lsu_bmu_req_without_cmplt; wire lsu_bmu_sg_chk_fail; wire lsu_bmu_wfd1; wire lsu_dbus_req; wire lsu_fast_retire; wire lsu_had_addr_vld; wire lsu_had_ex_cmplt; wire lsu_inst_store; wire lsu_iu_data_vld; wire [4:0] lsu_iu_expt_vec; wire lsu_iu_expt_vld; wire lsu_iu_fast_retire; wire lsu_iu_req; wire lsu_iu_req_wait_data; wire lsu_iu_stall; wire lsu_iu_stall_noinput; wire lsu_iu_wb_acc_err; wire lsu_iu_wb_bstack_chk_fail; wire lsu_iu_wb_cmplt; wire lsu_iu_wb_data_vld; wire lsu_iu_wfd; wire lsu_sel_without_cmplt; wire lsu_sel_without_hready; wire lsu_trans_cmplt; wire lsu_wb_acc_err; wire sm_clk; wire unalign_ctrl_not_last_beat; wire unalign_ctrl_stall; wire unalign_xx_split_on; parameter IDLE = 1'b0; parameter WAIT_DATA = 1'b1; assign ctrl_top_req_en = (cur_state == IDLE) && (next_state == WAIT_DATA) || (cur_state != IDLE); parameter MISL_VEC=5'b00100, MISS_VEC=5'b00110, ACCL_VEC=5'b00101, ACCS_VEC=5'b00111; assign lsu_addr_chk_fail = 1'b0; assign lsu_sel_without_hready = iu_lsu_ex_data_sel && !dp_ctrl_misalign && !iu_lsu_stall_without_hready; assign lsu_bmu_addr_check_fail = lsu_addr_chk_fail; assign lsu_sel_without_cmplt = iu_lsu_ex_data_sel && !dp_ctrl_misalign; assign lsu_inst_store = iu_lsu_oper_mux_en && iu_lsu_ex_store; assign lsu_fast_retire = !unalign_xx_split_on; assign fast_retire_grnt = lsu_fast_retire && bmu_lsu_grnt; always @(posedge sm_clk or negedge cpurst_b) begin if(!cpurst_b) cur_state <= IDLE; else if(iu_yy_xx_flush) cur_state <= IDLE; else cur_state <= next_state; end always @( cur_state or bmu_lsu_grnt or lsu_sel_without_hready or iu_lsu_ex_sel or lsu_fast_retire or iu_lsu_wb_ldst or lsu_trans_cmplt) begin case(cur_state) IDLE : if(lsu_sel_without_hready) begin if(bmu_lsu_grnt) begin if(!iu_lsu_ex_sel || !lsu_fast_retire) next_state = WAIT_DATA; else next_state = IDLE; end else next_state = IDLE; end else next_state = IDLE; WAIT_DATA : if(lsu_trans_cmplt) begin if(!iu_lsu_wb_ldst || lsu_fast_retire) next_state = IDLE; else next_state = WAIT_DATA; end else next_state = WAIT_DATA; default : next_state = IDLE; endcase end assign lsu_trans_cmplt = bmu_lsu_trans_cmplt; assign lsu_dbus_req = (cur_state == IDLE) && lsu_sel_without_hready; assign lsu_bmu_req = lsu_dbus_req; assign lsu_bmu_req_without_cmplt = (cur_state == IDLE) && lsu_sel_without_cmplt; assign lsu_bmu_idle = !iu_lsu_wb_ldst || (cur_state == IDLE) && lsu_trans_cmplt; assign lsu_bmu_wfd1 = iu_lsu_wb_ldst ^ (cur_state == WAIT_DATA); assign idle_retire = fast_retire_grnt || dp_ctrl_misalign; assign lsu_iu_req = (cur_state == IDLE) && iu_lsu_ex_sel && idle_retire || lsu_iu_req_wait_data; assign lsu_wb_acc_err = iu_lsu_wb_ldst && bmu_lsu_acc_err; assign lsu_iu_req_wait_data = (cur_state == WAIT_DATA) && lsu_trans_cmplt && !lsu_wb_acc_err && (lsu_fast_retire || !iu_lsu_wb_ldst && (!unalign_ctrl_not_last_beat || bmu_lsu_acc_err || bmu_lsu_bstack_chk_fail) ); assign lsu_iu_fast_retire = (cur_state == IDLE) && iu_lsu_ex_sel && fast_retire_grnt && !dp_ctrl_misalign || (cur_state == WAIT_DATA) && lsu_trans_cmplt && !lsu_wb_acc_err && lsu_fast_retire; assign ctrl_dp_store_buffer_updt = lsu_dbus_req && lsu_inst_store && bmu_lsu_grnt; assign ctrl_dp_ldst_info_buf_reuse = lsu_dbus_req && bmu_lsu_grnt && lsu_bmu_idle || (cur_state == WAIT_DATA) && iu_lsu_wb_ldst && lsu_trans_cmplt && !bmu_lsu_acc_err; assign ctrl_dp_ldst_req_grnt = 1'b0; assign lsu_iu_stall = (cur_state == IDLE) && iu_lsu_ex_sel && !idle_retire || (cur_state == WAIT_DATA) && (!lsu_trans_cmplt || iu_lsu_wb_ldst && !lsu_fast_retire) || unalign_ctrl_stall; assign lsu_iu_stall_noinput = (cur_state == IDLE) && iu_lsu_ex_data_sel || unalign_ctrl_stall; assign lsu_iu_data_vld = (cur_state == WAIT_DATA) && bmu_lsu_data_vld && !iu_lsu_wb_ldst && !lsu_fast_retire; assign lsu_iu_expt_vld = (cur_state == WAIT_DATA) && bmu_lsu_acc_err && !iu_lsu_wb_ldst && !lsu_fast_retire || dp_ctrl_misalign; assign lsu_iu_expt_vec[4:0] = {5{dp_ctrl_misalign && !lsu_inst_store}} & MISL_VEC | {5{dp_ctrl_misalign && lsu_inst_store}} & MISS_VEC | {5{cur_state && iu_lsu_wb_load}} & ACCL_VEC | {5{cur_state && iu_lsu_wb_store}} & ACCS_VEC; assign lsu_iu_wfd = (cur_state == WAIT_DATA); assign lsu_had_addr_vld = lsu_dbus_req && bmu_lsu_grnt; assign lsu_had_ex_cmplt = lsu_iu_req; assign lsu_iu_wb_cmplt = bmu_lsu_trans_cmplt; assign lsu_iu_wb_data_vld = bmu_lsu_data_vld; assign lsu_iu_wb_acc_err = bmu_lsu_acc_err; assign lsu_iu_wb_bstack_chk_fail = bmu_lsu_bstack_chk_fail; assign lsu_bmu_sg_chk_fail = 1'b0; endmodule module cr_lsu_dp( bmu_lsu_data, cp0_yy_be_v1, cp0_yy_be_v2, cp0_yy_clk_en, cp0_yy_machine_mode_aft_dbg, cpurst_b, cru_lsu_acc_ca, ctrl_dp_ldst_info_buf_reuse, ctrl_dp_ldst_req_grnt, ctrl_dp_store_buffer_updt, dp_ctrl_misalign, forever_cpuclk, iu_lsu_base, iu_lsu_cmp, iu_lsu_data, iu_lsu_ex_byte, iu_lsu_ex_data_sel, iu_lsu_ex_half, iu_lsu_ex_uns, iu_lsu_imm_data, iu_lsu_imm_sel, iu_lsu_imm_write_en, iu_lsu_offset, iu_lsu_oper_mux_en, iu_lsu_pc, iu_lsu_pc_sel, iu_lsu_rs1_sel, iu_lsu_rs2, lsu_bmu_addr, lsu_bmu_prot, lsu_bmu_size, lsu_bmu_store_error, lsu_bmu_wdata, lsu_bmu_write, lsu_had_addr, lsu_had_st, lsu_inst_store, lsu_iu_addr, lsu_iu_addr_vld, lsu_iu_alu_sel, lsu_iu_branch_cout, lsu_iu_branch_rst, lsu_iu_data, lsu_iu_mad_buf, lsu_iu_store, lsu_iu_wb_load_data, pad_yy_gate_clk_en_b, pad_yy_test_mode, pmp_lsu_acc_scu, randclk_dp_size_buf_mod_en_w5, unalign_dp_first_req, unalign_dp_load_data_byte1_to_byte1, unalign_dp_load_data_byte1_to_byte2, unalign_dp_load_data_byte1_to_byte3, unalign_dp_load_data_byte1_to_byte4, unalign_dp_load_data_byte2_to_byte1, unalign_dp_load_data_byte2_to_byte2, unalign_dp_load_data_byte2_to_byte3, unalign_dp_load_data_byte2_to_byte4, unalign_dp_load_data_byte3_to_byte1, unalign_dp_load_data_byte3_to_byte2, unalign_dp_load_data_byte3_to_byte3, unalign_dp_load_data_byte3_to_byte4, unalign_dp_load_data_byte4_to_byte1, unalign_dp_load_data_byte4_to_byte2, unalign_dp_load_data_byte4_to_byte3, unalign_dp_load_data_byte4_to_byte4, unalign_dp_store_data_byte1_to_byte1, unalign_dp_store_data_byte1_to_byte2, unalign_dp_store_data_byte1_to_byte3, unalign_dp_store_data_byte1_to_byte4, unalign_dp_store_data_byte2_to_byte1, unalign_dp_store_data_byte2_to_byte2, unalign_dp_store_data_byte2_to_byte3, unalign_dp_store_data_byte2_to_byte4, unalign_dp_store_data_byte3_to_byte1, unalign_dp_store_data_byte3_to_byte2, unalign_dp_store_data_byte3_to_byte3, unalign_dp_store_data_byte3_to_byte4, unalign_dp_store_data_byte4_to_byte1, unalign_dp_store_data_byte4_to_byte2, unalign_dp_store_data_byte4_to_byte3, unalign_dp_store_data_byte4_to_byte4 ); input [31:0] bmu_lsu_data; input cp0_yy_be_v1; input cp0_yy_be_v2; input cp0_yy_clk_en; input cp0_yy_machine_mode_aft_dbg; input cpurst_b; input cru_lsu_acc_ca; input ctrl_dp_ldst_info_buf_reuse; input ctrl_dp_ldst_req_grnt; input ctrl_dp_store_buffer_updt; input forever_cpuclk; input [31:0] iu_lsu_base; input iu_lsu_cmp; input [31:0] iu_lsu_data; input iu_lsu_ex_byte; input iu_lsu_ex_data_sel; input iu_lsu_ex_half; input iu_lsu_ex_uns; input [31:0] iu_lsu_imm_data; input iu_lsu_imm_sel; input iu_lsu_imm_write_en; input [31:0] iu_lsu_offset; input iu_lsu_oper_mux_en; input [31:0] iu_lsu_pc; input iu_lsu_pc_sel; input iu_lsu_rs1_sel; input [31:0] iu_lsu_rs2; input lsu_inst_store; input pad_yy_gate_clk_en_b; input pad_yy_test_mode; input pmp_lsu_acc_scu; input randclk_dp_size_buf_mod_en_w5; input unalign_dp_first_req; input unalign_dp_load_data_byte1_to_byte1; input unalign_dp_load_data_byte1_to_byte2; input unalign_dp_load_data_byte1_to_byte3; input unalign_dp_load_data_byte1_to_byte4; input unalign_dp_load_data_byte2_to_byte1; input unalign_dp_load_data_byte2_to_byte2; input unalign_dp_load_data_byte2_to_byte3; input unalign_dp_load_data_byte2_to_byte4; input unalign_dp_load_data_byte3_to_byte1; input unalign_dp_load_data_byte3_to_byte2; input unalign_dp_load_data_byte3_to_byte3; input unalign_dp_load_data_byte3_to_byte4; input unalign_dp_load_data_byte4_to_byte1; input unalign_dp_load_data_byte4_to_byte2; input unalign_dp_load_data_byte4_to_byte3; input unalign_dp_load_data_byte4_to_byte4; input unalign_dp_store_data_byte1_to_byte1; input unalign_dp_store_data_byte1_to_byte2; input unalign_dp_store_data_byte1_to_byte3; input unalign_dp_store_data_byte1_to_byte4; input unalign_dp_store_data_byte2_to_byte1; input unalign_dp_store_data_byte2_to_byte2; input unalign_dp_store_data_byte2_to_byte3; input unalign_dp_store_data_byte2_to_byte4; input unalign_dp_store_data_byte3_to_byte1; input unalign_dp_store_data_byte3_to_byte2; input unalign_dp_store_data_byte3_to_byte3; input unalign_dp_store_data_byte3_to_byte4; input unalign_dp_store_data_byte4_to_byte1; input unalign_dp_store_data_byte4_to_byte2; input unalign_dp_store_data_byte4_to_byte3; input unalign_dp_store_data_byte4_to_byte4; output dp_ctrl_misalign; output [31:0] lsu_bmu_addr; output [3 :0] lsu_bmu_prot; output [1 :0] lsu_bmu_size; output lsu_bmu_store_error; output [31:0] lsu_bmu_wdata; output lsu_bmu_write; output [31:0] lsu_had_addr; output lsu_had_st; output [31:0] lsu_iu_addr; output lsu_iu_addr_vld; output lsu_iu_alu_sel; output lsu_iu_branch_cout; output [31:0] lsu_iu_branch_rst; output [31:0] lsu_iu_data; output [31:0] lsu_iu_mad_buf; output lsu_iu_store; output [31:0] lsu_iu_wb_load_data; reg [4 :0] ldst_size_buffer; reg [1 :0] lsu_addr_mask; reg [31:0] lsu_data_sign_extd; reg lsu_misalign; reg [31:0] lsu_sized_data; reg [31:0] lsu_store_wdata; reg [31:0] store_data_buffer; reg [31:0] store_data_buffer_updt_val; wire adder_cout; wire [31:0] bmu_lsu_data; wire [4 :0] buffer_ldst_info; wire cp0_yy_be_v1; wire cp0_yy_be_v2; wire cp0_yy_clk_en; wire cp0_yy_machine_mode_aft_dbg; wire cpurst_b; wire cru_lsu_acc_ca; wire ctrl_dp_ldst_info_buf_reuse; wire ctrl_dp_ldst_req_grnt; wire ctrl_dp_store_buffer_updt; wire dp_ctrl_misalign; wire forever_cpuclk; wire [31:0] iu_lsu_base; wire iu_lsu_cmp; wire [31:0] iu_lsu_data; wire iu_lsu_ex_byte; wire iu_lsu_ex_data_sel; wire iu_lsu_ex_half; wire iu_lsu_ex_uns; wire [31:0] iu_lsu_imm_data; wire iu_lsu_imm_sel; wire iu_lsu_imm_write_en; wire [31:0] iu_lsu_offset; wire iu_lsu_oper_mux_en; wire [31:0] iu_lsu_pc; wire iu_lsu_pc_sel; wire iu_lsu_rs1_sel; wire [31:0] iu_lsu_rs2; wire [1 :0] iu_lsu_size; wire [31:0] lsu_addr; wire [1 :0] lsu_addr_1_0; wire [1 :0] lsu_addr_1_0_pre_mux; wire [31:0] lsu_addr_post; wire [31:0] lsu_base; wire [31:0] lsu_bmu_addr; wire [3 :0] lsu_bmu_prot; wire [1 :0] lsu_bmu_size; wire lsu_bmu_store_error; wire [31:0] lsu_bmu_wdata; wire lsu_bmu_write; wire [31:0] lsu_data; wire [31:0] lsu_had_addr; wire lsu_had_st; wire lsu_inst_store; wire [31:0] lsu_iu_adder_src0; wire [31:0] lsu_iu_adder_src1; wire [31:0] lsu_iu_addr; wire lsu_iu_addr_vld; wire lsu_iu_alu_sel; wire lsu_iu_branch_cout; wire [31:0] lsu_iu_branch_rst; wire [31:0] lsu_iu_data; wire [31:0] lsu_iu_mad_buf; wire lsu_iu_store; wire [31:0] lsu_iu_wb_load_data; wire [31:0] lsu_offset; wire lsu_sign_exten; wire [1 :0] lsu_size; wire [1 :0] lsu_size_post; wire [7 :0] lsu_sized_data_default; wire [7 :0] lsu_store_wdata_default; wire [1 :0] lsu_wb_addr_1_0; wire lsu_wb_sign_exten; wire [1 :0] lsu_wb_size; wire [31:0] lsu_wdata; wire pad_yy_gate_clk_en_b; wire pad_yy_test_mode; wire pmp_lsu_acc_scu; wire randclk_dp_size_buf_mod_en_w5; wire size_buf_clk; wire size_buf_clk_en; wire size_buf_en; wire size_buf_vld; wire store_buffer_clk; wire store_buffer_clk_en; wire store_buffer_updt; wire [31:0] store_buffer_updt_data; wire unalign_dp_first_req; wire unalign_dp_load_data_byte1_to_byte1; wire unalign_dp_load_data_byte1_to_byte2; wire unalign_dp_load_data_byte1_to_byte3; wire unalign_dp_load_data_byte1_to_byte4; wire unalign_dp_load_data_byte2_to_byte1; wire unalign_dp_load_data_byte2_to_byte2; wire unalign_dp_load_data_byte2_to_byte3; wire unalign_dp_load_data_byte2_to_byte4; wire unalign_dp_load_data_byte3_to_byte1; wire unalign_dp_load_data_byte3_to_byte2; wire unalign_dp_load_data_byte3_to_byte3; wire unalign_dp_load_data_byte3_to_byte4; wire unalign_dp_load_data_byte4_to_byte1; wire unalign_dp_load_data_byte4_to_byte2; wire unalign_dp_load_data_byte4_to_byte3; wire unalign_dp_load_data_byte4_to_byte4; wire unalign_dp_store_data_byte1_to_byte1; wire unalign_dp_store_data_byte1_to_byte2; wire unalign_dp_store_data_byte1_to_byte3; wire unalign_dp_store_data_byte1_to_byte4; wire unalign_dp_store_data_byte2_to_byte1; wire unalign_dp_store_data_byte2_to_byte2; wire unalign_dp_store_data_byte2_to_byte3; wire unalign_dp_store_data_byte2_to_byte4; wire unalign_dp_store_data_byte3_to_byte1; wire unalign_dp_store_data_byte3_to_byte2; wire unalign_dp_store_data_byte3_to_byte3; wire unalign_dp_store_data_byte3_to_byte4; wire unalign_dp_store_data_byte4_to_byte1; wire unalign_dp_store_data_byte4_to_byte2; wire unalign_dp_store_data_byte4_to_byte3; wire unalign_dp_store_data_byte4_to_byte4; wire [3 :0] unalign_ld_byte1_sel; wire [3 :0] unalign_ld_byte2_sel; wire [3 :0] unalign_ld_byte3_sel; wire [3 :0] unalign_ld_byte4_sel; wire [3 :0] unalign_st_byte1_sel; wire [3 :0] unalign_st_byte2_sel; wire [3 :0] unalign_st_byte3_sel; wire [3 :0] unalign_st_byte4_sel; assign size_buf_vld = !lsu_inst_store; assign size_buf_en = ctrl_dp_ldst_info_buf_reuse && unalign_dp_first_req && size_buf_vld; assign size_buf_clk_en = (ctrl_dp_ldst_info_buf_reuse || ctrl_dp_ldst_req_grnt) && unalign_dp_first_req && size_buf_vld; gated_clk_cell x_size_buf_gated_clk ( .clk_in (forever_cpuclk ), .clk_out (size_buf_clk ), .external_en (1'b0 ), .global_en (cp0_yy_clk_en ), .local_en (size_buf_clk_en ), .module_en (randclk_dp_size_buf_mod_en_w5), .pad_yy_gate_clk_en_b (pad_yy_gate_clk_en_b ), .pad_yy_test_mode (pad_yy_test_mode ) ); assign iu_lsu_size[1:0] = iu_lsu_ex_byte ? 2'b00 : iu_lsu_ex_half ? 2'b01 : 2'b10; assign lsu_wdata[31:0] = {32{iu_lsu_oper_mux_en}} & iu_lsu_data[31:0]; assign lsu_size[1:0] = iu_lsu_size[1:0]; assign lsu_addr_1_0[1:0] = lsu_addr_1_0_pre_mux[1:0]; assign lsu_sign_exten = !iu_lsu_ex_uns; assign lsu_data[31:0] = bmu_lsu_data[31:0]; parameter BYTE = 2'b00, HALF = 2'b01, WORD = 2'b10; parameter LE = 2'b00; parameter BE_V1 = 2'b10, BE_V2 = 2'b01; assign lsu_base[31:0] = {32{iu_lsu_oper_mux_en}} & iu_lsu_base[31:0] | {32{iu_lsu_rs1_sel}} & iu_lsu_base[31:0] | {32{iu_lsu_pc_sel}} & iu_lsu_pc[31:0]; assign lsu_offset[31:0] = {32{iu_lsu_oper_mux_en}} & iu_lsu_offset[31:0] | {32{iu_lsu_imm_sel}} & iu_lsu_offset[31:0] | {32{iu_lsu_cmp}} & iu_lsu_rs2[31:0]; assign lsu_iu_adder_src0[31:0] = lsu_base[31:0]; assign lsu_iu_adder_src1[31:0] = {32{iu_lsu_cmp}} ^ lsu_offset[31:0]; assign {adder_cout, lsu_addr[31:0]} = lsu_iu_adder_src0[31:0] + lsu_iu_adder_src1[31:0] + iu_lsu_cmp; assign lsu_iu_branch_rst[31:0] = lsu_addr[31:0]; assign lsu_iu_branch_cout = adder_cout; assign lsu_iu_alu_sel = 1'b0; assign lsu_bmu_store_error = 1'b0; assign lsu_bmu_addr[31:0] = lsu_addr_post[31:0]; assign lsu_bmu_size[1:0] = lsu_size_post[1:0]; assign lsu_bmu_prot[3:0] = {cru_lsu_acc_ca, pmp_lsu_acc_scu, cp0_yy_machine_mode_aft_dbg, 1'b1}; always @( lsu_size[1:0]) begin case(lsu_size[1:0]) WORD : lsu_addr_mask[1:0] = 2'b00; HALF : lsu_addr_mask[1:0] = 2'b10; default : lsu_addr_mask[1:0] = 2'b11; endcase end assign lsu_addr_1_0_pre_mux[1:0] = lsu_addr_mask[1:0] & lsu_addr[1:0]; always @( lsu_addr[1:0] or lsu_size[1:0]) begin case(lsu_size[1:0]) WORD : lsu_misalign = | lsu_addr[1:0]; HALF : lsu_misalign = lsu_addr[0]; default : lsu_misalign = 1'b0; endcase end assign dp_ctrl_misalign = lsu_misalign; assign lsu_size_post[1:0] = lsu_size[1:0]; assign lsu_addr_post[31:0] = {lsu_addr[31:2], lsu_addr_1_0[1:0]}; assign lsu_bmu_write = lsu_inst_store && iu_lsu_ex_data_sel; assign lsu_iu_store = lsu_inst_store; assign unalign_st_byte1_sel[3:0] = {unalign_dp_store_data_byte1_to_byte1, unalign_dp_store_data_byte2_to_byte1, unalign_dp_store_data_byte3_to_byte1, unalign_dp_store_data_byte4_to_byte1}; assign lsu_store_wdata_default[7:0] = 8'b0; always @( lsu_addr_1_0[1:0] or unalign_st_byte1_sel[3:0] or cp0_yy_be_v2 or lsu_size[1:0] or lsu_wdata[7:0] or lsu_wdata[31:8] or lsu_store_wdata_default[7:0] or cp0_yy_be_v1) begin lsu_store_wdata[7:0] = lsu_store_wdata_default[7:0]; casez({unalign_st_byte1_sel[3:0],cp0_yy_be_v1,cp0_yy_be_v2,lsu_size[1:0],lsu_addr_1_0[1:0]}) {4'b1000,2'b??,2'b??,2'b??} : lsu_store_wdata[7:0] = lsu_wdata[7:0]; {4'b0100,2'b??,2'b??,2'b??} : lsu_store_wdata[7:0] = lsu_wdata[15:8]; {4'b0010,2'b??,2'b??,2'b??} : lsu_store_wdata[7:0] = lsu_wdata[23:16]; {4'b0001,2'b??,2'b??,2'b??} : lsu_store_wdata[7:0] = lsu_wdata[31:24]; {4'b0000,BE_V1,BYTE, 2'b11} : lsu_store_wdata[7:0] = lsu_wdata[7:0]; {4'b0000,BE_V1,HALF, 2'b1?} : lsu_store_wdata[7:0] = lsu_wdata[7:0]; {4'b0000,BE_V1,WORD, 2'b??} : lsu_store_wdata[7:0] = lsu_wdata[7:0]; {4'b0000,BE_V2,BYTE, 2'b00} : lsu_store_wdata[7:0] = lsu_wdata[7:0]; {4'b0000,BE_V2,HALF, 2'b0?} : lsu_store_wdata[7:0] = lsu_wdata[15:8]; {4'b0000,BE_V2,WORD, 2'b??} : lsu_store_wdata[7:0] = lsu_wdata[31:24]; {4'b0000,LE ,BYTE, 2'b00} : lsu_store_wdata[7:0] = lsu_wdata[7:0]; {4'b0000,LE ,HALF, 2'b0?} : lsu_store_wdata[7:0] = lsu_wdata[7:0]; {4'b0000,LE ,WORD, 2'b??} : lsu_store_wdata[7:0] = lsu_wdata[7:0]; endcase end assign unalign_st_byte2_sel[3:0] = {unalign_dp_store_data_byte1_to_byte2, unalign_dp_store_data_byte2_to_byte2, unalign_dp_store_data_byte3_to_byte2, unalign_dp_store_data_byte4_to_byte2}; always @( lsu_addr_1_0[1:0] or cp0_yy_be_v2 or lsu_size[1:0] or lsu_wdata[7:0] or lsu_wdata[31:8] or lsu_store_wdata_default[7:0] or cp0_yy_be_v1 or unalign_st_byte2_sel[3:0]) begin lsu_store_wdata[15:8] = lsu_store_wdata_default[7:0]; casez({unalign_st_byte2_sel[3:0],cp0_yy_be_v1,cp0_yy_be_v2,lsu_size[1:0],lsu_addr_1_0[1:0]}) {4'b1000,2'b??,2'b??,2'b??} : lsu_store_wdata[15:8] = lsu_wdata[7:0]; {4'b0100,2'b??,2'b??,2'b??} : lsu_store_wdata[15:8] = lsu_wdata[15:8]; {4'b0010,2'b??,2'b??,2'b??} : lsu_store_wdata[15:8] = lsu_wdata[23:16]; {4'b0001,2'b??,2'b??,2'b??} : lsu_store_wdata[15:8] = lsu_wdata[31:24]; {4'b0000,BE_V1,BYTE, 2'b10} : lsu_store_wdata[15:8] = lsu_wdata[7:0]; {4'b0000,BE_V1,HALF, 2'b1?} : lsu_store_wdata[15:8] = lsu_wdata[15:8]; {4'b0000,BE_V1,WORD, 2'b??} : lsu_store_wdata[15:8] = lsu_wdata[15:8]; {4'b0000,BE_V2,BYTE, 2'b01} : lsu_store_wdata[15:8] = lsu_wdata[7:0]; {4'b0000,BE_V2,HALF, 2'b0?} : lsu_store_wdata[15:8] = lsu_wdata[7:0]; {4'b0000,BE_V2,WORD, 2'b??} : lsu_store_wdata[15:8] = lsu_wdata[23:16]; {4'b0000,LE ,BYTE, 2'b01} : lsu_store_wdata[15:8] = lsu_wdata[7:0]; {4'b0000,LE ,HALF, 2'b0?} : lsu_store_wdata[15:8] = lsu_wdata[15:8]; {4'b0000,LE ,WORD, 2'b??} : lsu_store_wdata[15:8] = lsu_wdata[15:8]; endcase end assign unalign_st_byte3_sel[3:0] = {unalign_dp_store_data_byte1_to_byte3, unalign_dp_store_data_byte2_to_byte3, unalign_dp_store_data_byte3_to_byte3, unalign_dp_store_data_byte4_to_byte3}; always @( lsu_addr_1_0[1:0] or cp0_yy_be_v2 or unalign_st_byte3_sel[3:0] or lsu_size[1:0] or lsu_wdata[7:0] or lsu_wdata[31:8] or lsu_store_wdata_default[7:0] or cp0_yy_be_v1) begin lsu_store_wdata[23:16] = lsu_store_wdata_default[7:0]; casez({unalign_st_byte3_sel[3:0],cp0_yy_be_v1,cp0_yy_be_v2,lsu_size[1:0],lsu_addr_1_0[1:0]}) {4'b1000,2'b??,2'b??,2'b??} : lsu_store_wdata[23:16] = lsu_wdata[7:0]; {4'b0100,2'b??,2'b??,2'b??} : lsu_store_wdata[23:16] = lsu_wdata[15:8]; {4'b0010,2'b??,2'b??,2'b??} : lsu_store_wdata[23:16] = lsu_wdata[23:16]; {4'b0001,2'b??,2'b??,2'b??} : lsu_store_wdata[23:16] = lsu_wdata[31:24]; {4'b0000,BE_V1,BYTE, 2'b01} : lsu_store_wdata[23:16] = lsu_wdata[7:0]; {4'b0000,BE_V1,HALF, 2'b0?} : lsu_store_wdata[23:16] = lsu_wdata[7:0]; {4'b0000,BE_V1,WORD, 2'b??} : lsu_store_wdata[23:16] = lsu_wdata[23:16]; {4'b0000,BE_V2,BYTE, 2'b10} : lsu_store_wdata[23:16] = lsu_wdata[7:0]; {4'b0000,BE_V2,HALF, 2'b1?} : lsu_store_wdata[23:16] = lsu_wdata[15:8]; {4'b0000,BE_V2,WORD, 2'b??} : lsu_store_wdata[23:16] = lsu_wdata[15:8]; {4'b0000,LE ,BYTE, 2'b10} : lsu_store_wdata[23:16] = lsu_wdata[7:0]; {4'b0000,LE ,HALF, 2'b1?} : lsu_store_wdata[23:16] = lsu_wdata[7:0]; {4'b0000,LE ,WORD, 2'b??} : lsu_store_wdata[23:16] = lsu_wdata[23:16]; endcase end assign unalign_st_byte4_sel[3:0] = {unalign_dp_store_data_byte1_to_byte4, unalign_dp_store_data_byte2_to_byte4, unalign_dp_store_data_byte3_to_byte4, unalign_dp_store_data_byte4_to_byte4}; always @( lsu_addr_1_0[1:0] or cp0_yy_be_v2 or lsu_size[1:0] or lsu_wdata[7:0] or lsu_wdata[31:8] or lsu_store_wdata_default[7:0] or cp0_yy_be_v1 or unalign_st_byte4_sel[3:0]) begin lsu_store_wdata[31:24] = lsu_store_wdata_default[7:0]; casez({unalign_st_byte4_sel[3:0],cp0_yy_be_v1,cp0_yy_be_v2,lsu_size[1:0],lsu_addr_1_0[1:0]}) {4'b1000,2'b??,2'b??,2'b??} : lsu_store_wdata[31:24] = lsu_wdata[7:0]; {4'b0100,2'b??,2'b??,2'b??} : lsu_store_wdata[31:24] = lsu_wdata[15:8]; {4'b0010,2'b??,2'b??,2'b??} : lsu_store_wdata[31:24] = lsu_wdata[23:16]; {4'b0001,2'b??,2'b??,2'b??} : lsu_store_wdata[31:24] = lsu_wdata[31:24]; {4'b0000,BE_V1,BYTE, 2'b00} : lsu_store_wdata[31:24] = lsu_wdata[7:0]; {4'b0000,BE_V1,HALF, 2'b0?} : lsu_store_wdata[31:24] = lsu_wdata[15:8]; {4'b0000,BE_V1,WORD, 2'b??} : lsu_store_wdata[31:24] = lsu_wdata[31:24]; {4'b0000,BE_V2,BYTE, 2'b11} : lsu_store_wdata[31:24] = lsu_wdata[7:0]; {4'b0000,BE_V2,HALF, 2'b1?} : lsu_store_wdata[31:24] = lsu_wdata[7:0]; {4'b0000,BE_V2,WORD, 2'b??} : lsu_store_wdata[31:24] = lsu_wdata[7:0]; {4'b0000,LE ,BYTE, 2'b11} : lsu_store_wdata[31:24] = lsu_wdata[7:0]; {4'b0000,LE ,HALF, 2'b1?} : lsu_store_wdata[31:24] = lsu_wdata[15:8]; {4'b0000,LE ,WORD, 2'b??} : lsu_store_wdata[31:24] = lsu_wdata[31:24]; endcase end assign store_buffer_clk_en = store_buffer_updt; gated_clk_cell x_store_buffer_clk ( .clk_in (forever_cpuclk ), .clk_out (store_buffer_clk ), .external_en (1'b0 ), .global_en (cp0_yy_clk_en ), .local_en (store_buffer_clk_en ), .module_en (1'b0 ), .pad_yy_gate_clk_en_b (pad_yy_gate_clk_en_b), .pad_yy_test_mode (pad_yy_test_mode ) ); assign store_buffer_updt = ctrl_dp_store_buffer_updt || iu_lsu_imm_write_en; assign store_buffer_updt_data[31:0] = {32{ctrl_dp_store_buffer_updt}} & lsu_store_wdata[31:0] | {32{iu_lsu_imm_write_en}} & iu_lsu_imm_data[31:0]; always @( store_buffer_updt_data[31:0] or store_buffer_updt or store_data_buffer[31:0]) begin if(store_buffer_updt) store_data_buffer_updt_val[31:0] = store_buffer_updt_data[31:0]; else store_data_buffer_updt_val[31:0] = store_data_buffer[31:0]; end always @(posedge store_buffer_clk or negedge cpurst_b) begin if(!cpurst_b) store_data_buffer[31:0] <= 32'b0; else store_data_buffer[31:0] <= store_data_buffer_updt_val[31:0]; end assign lsu_bmu_wdata[31:0] = store_data_buffer[31:0]; assign lsu_iu_mad_buf[31:0] = store_data_buffer[31:0]; assign buffer_ldst_info[4:0] = {lsu_sign_exten, lsu_size[1:0], lsu_addr_1_0[1:0]}; always @(posedge size_buf_clk) begin if(size_buf_en) ldst_size_buffer[4:0] <= buffer_ldst_info[4:0]; end assign lsu_wb_addr_1_0[1:0] = ldst_size_buffer[1:0]; assign lsu_wb_size[1:0] = ldst_size_buffer[3:2]; assign lsu_wb_sign_exten = ldst_size_buffer[4]; assign unalign_ld_byte1_sel[3:0] = {unalign_dp_load_data_byte1_to_byte1, unalign_dp_load_data_byte2_to_byte1, unalign_dp_load_data_byte3_to_byte1, unalign_dp_load_data_byte4_to_byte1}; assign lsu_sized_data_default[7:0] = 8'b0; always @( lsu_wb_size[1:0] or unalign_ld_byte1_sel[3:0] or lsu_wb_addr_1_0[1:0] or cp0_yy_be_v2 or lsu_data[31:16] or cp0_yy_be_v1 or lsu_sized_data_default[7:0] or lsu_data[15:0]) begin lsu_sized_data[7:0] = lsu_sized_data_default[7:0]; casez({unalign_ld_byte1_sel[3:0],cp0_yy_be_v1,cp0_yy_be_v2,lsu_wb_size[1:0],lsu_wb_addr_1_0[1:0]}) {4'b1000,2'b??,2'b??,2'b??} : lsu_sized_data[7:0] = lsu_data[7:0]; {4'b0100,2'b??,2'b??,2'b??} : lsu_sized_data[7:0] = lsu_data[15:8]; {4'b0010,2'b??,2'b??,2'b??} : lsu_sized_data[7:0] = lsu_data[23:16]; {4'b0001,2'b??,2'b??,2'b??} : lsu_sized_data[7:0] = lsu_data[31:24]; {4'b0000,BE_V1,BYTE, 2'b00} : lsu_sized_data[7:0] = lsu_data[31:24]; {4'b0000,BE_V1,BYTE, 2'b01} : lsu_sized_data[7:0] = lsu_data[23:16]; {4'b0000,BE_V1,BYTE, 2'b10} : lsu_sized_data[7:0] = lsu_data[15:8]; {4'b0000,BE_V1,BYTE, 2'b11} : lsu_sized_data[7:0] = lsu_data[7:0]; {4'b0000,BE_V1,HALF, 2'b0?} : lsu_sized_data[7:0] = lsu_data[23:16]; {4'b0000,BE_V1,HALF, 2'b1?} : lsu_sized_data[7:0] = lsu_data[7:0]; {4'b0000,BE_V1,WORD, 2'b??} : lsu_sized_data[7:0] = lsu_data[7:0]; {4'b0000,BE_V2,BYTE, 2'b00} : lsu_sized_data[7:0] = lsu_data[7:0]; {4'b0000,BE_V2,BYTE, 2'b01} : lsu_sized_data[7:0] = lsu_data[15:8]; {4'b0000,BE_V2,BYTE, 2'b10} : lsu_sized_data[7:0] = lsu_data[23:16]; {4'b0000,BE_V2,BYTE, 2'b11} : lsu_sized_data[7:0] = lsu_data[31:24]; {4'b0000,BE_V2,HALF, 2'b0?} : lsu_sized_data[7:0] = lsu_data[15:8]; {4'b0000,BE_V2,HALF, 2'b1?} : lsu_sized_data[7:0] = lsu_data[31:24]; {4'b0000,BE_V2,WORD, 2'b??} : lsu_sized_data[7:0] = lsu_data[31:24]; {4'b0000,LE ,BYTE, 2'b00} : lsu_sized_data[7:0] = lsu_data[7:0]; {4'b0000,LE ,BYTE, 2'b01} : lsu_sized_data[7:0] = lsu_data[15:8]; {4'b0000,LE ,BYTE, 2'b10} : lsu_sized_data[7:0] = lsu_data[23:16]; {4'b0000,LE ,BYTE, 2'b11} : lsu_sized_data[7:0] = lsu_data[31:24]; {4'b0000,LE ,HALF, 2'b0?} : lsu_sized_data[7:0] = lsu_data[7:0]; {4'b0000,LE ,HALF, 2'b1?} : lsu_sized_data[7:0] = lsu_data[23:16]; {4'b0000,LE ,WORD, 2'b??} : lsu_sized_data[7:0] = lsu_data[7:0]; endcase end assign unalign_ld_byte2_sel[3:0] = {unalign_dp_load_data_byte1_to_byte2, unalign_dp_load_data_byte2_to_byte2, unalign_dp_load_data_byte3_to_byte2, unalign_dp_load_data_byte4_to_byte2}; always @( lsu_wb_size[1:0] or lsu_wb_addr_1_0[1:0] or cp0_yy_be_v2 or lsu_data[31:16] or cp0_yy_be_v1 or lsu_sized_data_default[7:0] or lsu_data[15:0] or unalign_ld_byte2_sel[3:0]) begin lsu_sized_data[15:8] = lsu_sized_data_default[7:0]; casez({unalign_ld_byte2_sel[3:0],cp0_yy_be_v1,cp0_yy_be_v2,lsu_wb_size[1:0],lsu_wb_addr_1_0[1:0]}) {4'b1000,2'b??,2'b??,2'b??} : lsu_sized_data[15:8] = lsu_data[7:0]; {4'b0100,2'b??,2'b??,2'b??} : lsu_sized_data[15:8] = lsu_data[15:8]; {4'b0010,2'b??,2'b??,2'b??} : lsu_sized_data[15:8] = lsu_data[23:16]; {4'b0001,2'b??,2'b??,2'b??} : lsu_sized_data[15:8] = lsu_data[31:24]; {4'b0000,BE_V1,HALF, 2'b0?} : lsu_sized_data[15:8] = lsu_data[31:24]; {4'b0000,BE_V1,HALF, 2'b1?} : lsu_sized_data[15:8] = lsu_data[15:8]; {4'b0000,BE_V1,WORD, 2'b??} : lsu_sized_data[15:8] = lsu_data[15:8]; {4'b0000,BE_V2,HALF, 2'b0?} : lsu_sized_data[15:8] = lsu_data[7:0]; {4'b0000,BE_V2,HALF, 2'b1?} : lsu_sized_data[15:8] = lsu_data[23:16]; {4'b0000,BE_V2,WORD, 2'b??} : lsu_sized_data[15:8] = lsu_data[23:16]; {4'b0000,LE ,HALF, 2'b0?} : lsu_sized_data[15:8] = lsu_data[15:8]; {4'b0000,LE ,HALF, 2'b1?} : lsu_sized_data[15:8] = lsu_data[31:24]; {4'b0000,LE ,WORD, 2'b??} : lsu_sized_data[15:8] = lsu_data[15:8]; endcase end assign unalign_ld_byte3_sel[3:0] = {unalign_dp_load_data_byte1_to_byte3, unalign_dp_load_data_byte2_to_byte3, unalign_dp_load_data_byte3_to_byte3, unalign_dp_load_data_byte4_to_byte3}; always @( lsu_wb_size[1:0] or lsu_wb_addr_1_0[1:0] or cp0_yy_be_v2 or lsu_data[31:16] or cp0_yy_be_v1 or lsu_sized_data_default[7:0] or unalign_ld_byte3_sel[3:0] or lsu_data[15:0]) begin lsu_sized_data[23:16] = lsu_sized_data_default[7:0]; casez({unalign_ld_byte3_sel[3:0],cp0_yy_be_v1,cp0_yy_be_v2,lsu_wb_size[1:0],lsu_wb_addr_1_0[1:0]}) {4'b1000,2'b??,2'b??,2'b??} : lsu_sized_data[23:16] = lsu_data[7:0]; {4'b0100,2'b??,2'b??,2'b??} : lsu_sized_data[23:16] = lsu_data[15:8]; {4'b0010,2'b??,2'b??,2'b??} : lsu_sized_data[23:16] = lsu_data[23:16]; {4'b0001,2'b??,2'b??,2'b??} : lsu_sized_data[23:16] = lsu_data[31:24]; {4'b0000,BE_V1,WORD ,2'b??} : lsu_sized_data[23:16] = lsu_data[23:16]; {4'b0000,BE_V2,WORD ,2'b??} : lsu_sized_data[23:16] = lsu_data[15:8]; {4'b0000,LE ,WORD ,2'b??} : lsu_sized_data[23:16] = lsu_data[23:16]; endcase end assign unalign_ld_byte4_sel[3:0] = {unalign_dp_load_data_byte1_to_byte4, unalign_dp_load_data_byte2_to_byte4, unalign_dp_load_data_byte3_to_byte4, unalign_dp_load_data_byte4_to_byte4}; always @( lsu_wb_size[1:0] or lsu_wb_addr_1_0[1:0] or cp0_yy_be_v2 or lsu_data[31:16] or cp0_yy_be_v1 or lsu_sized_data_default[7:0] or unalign_ld_byte4_sel[3:0] or lsu_data[15:0]) begin lsu_sized_data[31:24] = lsu_sized_data_default[7:0]; casez({unalign_ld_byte4_sel[3:0],cp0_yy_be_v1,cp0_yy_be_v2,lsu_wb_size[1:0],lsu_wb_addr_1_0[1:0]}) {4'b1000,2'b??,2'b??,2'b??} : lsu_sized_data[31:24] = lsu_data[7:0]; {4'b0100,2'b??,2'b??,2'b??} : lsu_sized_data[31:24] = lsu_data[15:8]; {4'b0010,2'b??,2'b??,2'b??} : lsu_sized_data[31:24] = lsu_data[23:16]; {4'b0001,2'b??,2'b??,2'b??} : lsu_sized_data[31:24] = lsu_data[31:24]; {4'b0000,BE_V1,WORD ,2'b??} : lsu_sized_data[31:24] = lsu_data[31:24]; {4'b0000,BE_V2,WORD ,2'b??} : lsu_sized_data[31:24] = lsu_data[7:0]; {4'b0000,LE ,WORD ,2'b??} : lsu_sized_data[31:24] = lsu_data[31:24]; endcase end always @( lsu_wb_size[1:0] or lsu_sized_data[31:0] or lsu_wb_sign_exten) begin case({lsu_wb_sign_exten,lsu_wb_size[1:0]}) {1'b1,BYTE} : lsu_data_sign_extd[31:0] = {{24{lsu_sized_data[7]}},lsu_sized_data[7:0]}; {1'b1,HALF} : lsu_data_sign_extd[31:0] = {{16{lsu_sized_data[15]}},lsu_sized_data[15:0]}; default : lsu_data_sign_extd[31:0] = lsu_sized_data[31:0]; endcase end assign lsu_iu_data[31:0] = lsu_data_sign_extd[31:0]; assign lsu_iu_wb_load_data[31:0] = lsu_data_sign_extd[31:0]; assign lsu_iu_addr_vld = iu_lsu_ex_data_sel; assign lsu_iu_addr[31:0] = lsu_addr[31:0]; assign lsu_had_st = lsu_inst_store; assign lsu_had_addr[31:0] = lsu_bmu_addr[31:0]; endmodule module cr_lsu_randclk( randclk_dp_size_buf_mod_en_w5 ); output randclk_dp_size_buf_mod_en_w5; wire randclk_dp_size_buf_mod_en_w5; assign randclk_dp_size_buf_mod_en_w5 = 1'b0; endmodule module cr_lsu_top( bmu_lsu_acc_err, bmu_lsu_bstack_chk_fail, bmu_lsu_data, bmu_lsu_data_vld, bmu_lsu_grnt, bmu_lsu_trans_cmplt, cp0_yy_be_v1, cp0_yy_be_v2, cp0_yy_clk_en, cp0_yy_machine_mode_aft_dbg, cpurst_b, forever_cpuclk, iu_lsu_base, iu_lsu_cmp, iu_lsu_data, iu_lsu_ex_byte, iu_lsu_ex_data_sel, iu_lsu_ex_half, iu_lsu_ex_sel, iu_lsu_ex_store, iu_lsu_ex_uns, iu_lsu_imm_data, iu_lsu_imm_sel, iu_lsu_imm_write_en, iu_lsu_offset, iu_lsu_oper_mux_en, iu_lsu_pc, iu_lsu_pc_sel, iu_lsu_rs1_sel, iu_lsu_rs2, iu_lsu_stall_without_hready, iu_lsu_wb_ldst, iu_lsu_wb_load, iu_lsu_wb_store, iu_yy_xx_flush, lsu_bmu_addr, lsu_bmu_addr_check_fail, lsu_bmu_idle, lsu_bmu_prot, lsu_bmu_req, lsu_bmu_req_without_cmplt, lsu_bmu_sg_chk_fail, lsu_bmu_size, lsu_bmu_store_error, lsu_bmu_wdata, lsu_bmu_wfd1, lsu_bmu_write, lsu_had_addr, lsu_had_addr_vld, lsu_had_ex_cmplt, lsu_had_st, lsu_iu_addr, lsu_iu_addr_vld, lsu_iu_alu_sel, lsu_iu_branch_cout, lsu_iu_branch_rst, lsu_iu_data, lsu_iu_data_vld, lsu_iu_expt_vec, lsu_iu_expt_vld, lsu_iu_fast_retire, lsu_iu_mad_buf, lsu_iu_req, lsu_iu_stall, lsu_iu_stall_noinput, lsu_iu_store, lsu_iu_wb_acc_err, lsu_iu_wb_bstack_chk_fail, lsu_iu_wb_cmplt, lsu_iu_wb_data_vld, lsu_iu_wb_load_data, lsu_iu_wfd, pad_yy_gate_clk_en_b, pad_yy_test_mode ); input bmu_lsu_acc_err; input bmu_lsu_bstack_chk_fail; input [31:0] bmu_lsu_data; input bmu_lsu_data_vld; input bmu_lsu_grnt; input bmu_lsu_trans_cmplt; input cp0_yy_be_v1; input cp0_yy_be_v2; input cp0_yy_clk_en; input cp0_yy_machine_mode_aft_dbg; input cpurst_b; input forever_cpuclk; input [31:0] iu_lsu_base; input iu_lsu_cmp; input [31:0] iu_lsu_data; input iu_lsu_ex_byte; input iu_lsu_ex_data_sel; input iu_lsu_ex_half; input iu_lsu_ex_sel; input iu_lsu_ex_store; input iu_lsu_ex_uns; input [31:0] iu_lsu_imm_data; input iu_lsu_imm_sel; input iu_lsu_imm_write_en; input [31:0] iu_lsu_offset; input iu_lsu_oper_mux_en; input [31:0] iu_lsu_pc; input iu_lsu_pc_sel; input iu_lsu_rs1_sel; input [31:0] iu_lsu_rs2; input iu_lsu_stall_without_hready; input iu_lsu_wb_ldst; input iu_lsu_wb_load; input iu_lsu_wb_store; input iu_yy_xx_flush; input pad_yy_gate_clk_en_b; input pad_yy_test_mode; output [31:0] lsu_bmu_addr; output lsu_bmu_addr_check_fail; output lsu_bmu_idle; output [3 :0] lsu_bmu_prot; output lsu_bmu_req; output lsu_bmu_req_without_cmplt; output lsu_bmu_sg_chk_fail; output [1 :0] lsu_bmu_size; output lsu_bmu_store_error; output [31:0] lsu_bmu_wdata; output lsu_bmu_wfd1; output lsu_bmu_write; output [31:0] lsu_had_addr; output lsu_had_addr_vld; output lsu_had_ex_cmplt; output lsu_had_st; output [31:0] lsu_iu_addr; output lsu_iu_addr_vld; output lsu_iu_alu_sel; output lsu_iu_branch_cout; output [31:0] lsu_iu_branch_rst; output [31:0] lsu_iu_data; output lsu_iu_data_vld; output [4 :0] lsu_iu_expt_vec; output lsu_iu_expt_vld; output lsu_iu_fast_retire; output [31:0] lsu_iu_mad_buf; output lsu_iu_req; output lsu_iu_stall; output lsu_iu_stall_noinput; output lsu_iu_store; output lsu_iu_wb_acc_err; output lsu_iu_wb_bstack_chk_fail; output lsu_iu_wb_cmplt; output lsu_iu_wb_data_vld; output [31:0] lsu_iu_wb_load_data; output lsu_iu_wfd; wire bmu_lsu_acc_err; wire bmu_lsu_bstack_chk_fail; wire [31:0] bmu_lsu_data; wire bmu_lsu_data_vld; wire bmu_lsu_grnt; wire bmu_lsu_trans_cmplt; wire cp0_yy_be_v1; wire cp0_yy_be_v2; wire cp0_yy_clk_en; wire cp0_yy_machine_mode_aft_dbg; wire cpurst_b; wire ctrl_dp_ldst_info_buf_reuse; wire ctrl_dp_ldst_req_grnt; wire ctrl_dp_store_buffer_updt; wire ctrl_top_req_en; wire dp_ctrl_misalign; wire forever_cpuclk; wire [31:0] iu_lsu_base; wire iu_lsu_cmp; wire [31:0] iu_lsu_data; wire iu_lsu_ex_byte; wire iu_lsu_ex_data_sel; wire iu_lsu_ex_half; wire iu_lsu_ex_sel; wire iu_lsu_ex_store; wire iu_lsu_ex_uns; wire [31:0] iu_lsu_imm_data; wire iu_lsu_imm_sel; wire iu_lsu_imm_write_en; wire [31:0] iu_lsu_offset; wire iu_lsu_oper_mux_en; wire [31:0] iu_lsu_pc; wire iu_lsu_pc_sel; wire iu_lsu_rs1_sel; wire [31:0] iu_lsu_rs2; wire iu_lsu_stall_without_hready; wire iu_lsu_wb_ldst; wire iu_lsu_wb_load; wire iu_lsu_wb_store; wire iu_yy_xx_flush; wire [31:0] lsu_bmu_addr; wire lsu_bmu_addr_check_fail; wire lsu_bmu_idle; wire [3 :0] lsu_bmu_prot; wire lsu_bmu_req; wire lsu_bmu_req_without_cmplt; wire lsu_bmu_sg_chk_fail; wire [1 :0] lsu_bmu_size; wire lsu_bmu_store_error; wire [31:0] lsu_bmu_wdata; wire lsu_bmu_wfd1; wire lsu_bmu_write; wire [31:0] lsu_had_addr; wire lsu_had_addr_vld; wire lsu_had_ex_cmplt; wire lsu_had_st; wire lsu_inst_store; wire [31:0] lsu_iu_addr; wire lsu_iu_addr_vld; wire lsu_iu_alu_sel; wire lsu_iu_branch_cout; wire [31:0] lsu_iu_branch_rst; wire [31:0] lsu_iu_data; wire lsu_iu_data_vld; wire [4 :0] lsu_iu_expt_vec; wire lsu_iu_expt_vld; wire lsu_iu_fast_retire; wire [31:0] lsu_iu_mad_buf; wire lsu_iu_req; wire lsu_iu_stall; wire lsu_iu_stall_noinput; wire lsu_iu_store; wire lsu_iu_wb_acc_err; wire lsu_iu_wb_bstack_chk_fail; wire lsu_iu_wb_cmplt; wire lsu_iu_wb_data_vld; wire [31:0] lsu_iu_wb_load_data; wire lsu_iu_wfd; wire pad_yy_gate_clk_en_b; wire pad_yy_test_mode; wire randclk_dp_size_buf_mod_en_w5; wire top_sm_clk_en; wire unalign_ctrl_not_last_beat; wire unalign_ctrl_stall; wire unalign_dp_first_req; wire unalign_dp_load_data_byte1_to_byte1; wire unalign_dp_load_data_byte1_to_byte2; wire unalign_dp_load_data_byte1_to_byte3; wire unalign_dp_load_data_byte1_to_byte4; wire unalign_dp_load_data_byte2_to_byte1; wire unalign_dp_load_data_byte2_to_byte2; wire unalign_dp_load_data_byte2_to_byte3; wire unalign_dp_load_data_byte2_to_byte4; wire unalign_dp_load_data_byte3_to_byte1; wire unalign_dp_load_data_byte3_to_byte2; wire unalign_dp_load_data_byte3_to_byte3; wire unalign_dp_load_data_byte3_to_byte4; wire unalign_dp_load_data_byte4_to_byte1; wire unalign_dp_load_data_byte4_to_byte2; wire unalign_dp_load_data_byte4_to_byte3; wire unalign_dp_load_data_byte4_to_byte4; wire unalign_dp_store_data_byte1_to_byte1; wire unalign_dp_store_data_byte1_to_byte2; wire unalign_dp_store_data_byte1_to_byte3; wire unalign_dp_store_data_byte1_to_byte4; wire unalign_dp_store_data_byte2_to_byte1; wire unalign_dp_store_data_byte2_to_byte2; wire unalign_dp_store_data_byte2_to_byte3; wire unalign_dp_store_data_byte2_to_byte4; wire unalign_dp_store_data_byte3_to_byte1; wire unalign_dp_store_data_byte3_to_byte2; wire unalign_dp_store_data_byte3_to_byte3; wire unalign_dp_store_data_byte3_to_byte4; wire unalign_dp_store_data_byte4_to_byte1; wire unalign_dp_store_data_byte4_to_byte2; wire unalign_dp_store_data_byte4_to_byte3; wire unalign_dp_store_data_byte4_to_byte4; wire unalign_top_clk_en; wire unalign_xx_split_on; assign top_sm_clk_en = ctrl_top_req_en || unalign_top_clk_en; cr_lsu_dp x_cr_lsu_dp ( .bmu_lsu_data (bmu_lsu_data ), .cp0_yy_be_v1 (cp0_yy_be_v1 ), .cp0_yy_be_v2 (cp0_yy_be_v2 ), .cp0_yy_clk_en (cp0_yy_clk_en ), .cp0_yy_machine_mode_aft_dbg (cp0_yy_machine_mode_aft_dbg ), .cpurst_b (cpurst_b ), .cru_lsu_acc_ca (1'b0 ), .ctrl_dp_ldst_info_buf_reuse (ctrl_dp_ldst_info_buf_reuse ), .ctrl_dp_ldst_req_grnt (ctrl_dp_ldst_req_grnt ), .ctrl_dp_store_buffer_updt (ctrl_dp_store_buffer_updt ), .dp_ctrl_misalign (dp_ctrl_misalign ), .forever_cpuclk (forever_cpuclk ), .iu_lsu_base (iu_lsu_base ), .iu_lsu_cmp (iu_lsu_cmp ), .iu_lsu_data (iu_lsu_data ), .iu_lsu_ex_byte (iu_lsu_ex_byte ), .iu_lsu_ex_data_sel (iu_lsu_ex_data_sel ), .iu_lsu_ex_half (iu_lsu_ex_half ), .iu_lsu_ex_uns (iu_lsu_ex_uns ), .iu_lsu_imm_data (iu_lsu_imm_data ), .iu_lsu_imm_sel (iu_lsu_imm_sel ), .iu_lsu_imm_write_en (iu_lsu_imm_write_en ), .iu_lsu_offset (iu_lsu_offset ), .iu_lsu_oper_mux_en (iu_lsu_oper_mux_en ), .iu_lsu_pc (iu_lsu_pc ), .iu_lsu_pc_sel (iu_lsu_pc_sel ), .iu_lsu_rs1_sel (iu_lsu_rs1_sel ), .iu_lsu_rs2 (iu_lsu_rs2 ), .lsu_bmu_addr (lsu_bmu_addr ), .lsu_bmu_prot (lsu_bmu_prot ), .lsu_bmu_size (lsu_bmu_size ), .lsu_bmu_store_error (lsu_bmu_store_error ), .lsu_bmu_wdata (lsu_bmu_wdata ), .lsu_bmu_write (lsu_bmu_write ), .lsu_had_addr (lsu_had_addr ), .lsu_had_st (lsu_had_st ), .lsu_inst_store (lsu_inst_store ), .lsu_iu_addr (lsu_iu_addr ), .lsu_iu_addr_vld (lsu_iu_addr_vld ), .lsu_iu_alu_sel (lsu_iu_alu_sel ), .lsu_iu_branch_cout (lsu_iu_branch_cout ), .lsu_iu_branch_rst (lsu_iu_branch_rst ), .lsu_iu_data (lsu_iu_data ), .lsu_iu_mad_buf (lsu_iu_mad_buf ), .lsu_iu_store (lsu_iu_store ), .lsu_iu_wb_load_data (lsu_iu_wb_load_data ), .pad_yy_gate_clk_en_b (pad_yy_gate_clk_en_b ), .pad_yy_test_mode (pad_yy_test_mode ), .pmp_lsu_acc_scu (1'b0 ), .randclk_dp_size_buf_mod_en_w5 (randclk_dp_size_buf_mod_en_w5 ), .unalign_dp_first_req (unalign_dp_first_req ), .unalign_dp_load_data_byte1_to_byte1 (unalign_dp_load_data_byte1_to_byte1 ), .unalign_dp_load_data_byte1_to_byte2 (unalign_dp_load_data_byte1_to_byte2 ), .unalign_dp_load_data_byte1_to_byte3 (unalign_dp_load_data_byte1_to_byte3 ), .unalign_dp_load_data_byte1_to_byte4 (unalign_dp_load_data_byte1_to_byte4 ), .unalign_dp_load_data_byte2_to_byte1 (unalign_dp_load_data_byte2_to_byte1 ), .unalign_dp_load_data_byte2_to_byte2 (unalign_dp_load_data_byte2_to_byte2 ), .unalign_dp_load_data_byte2_to_byte3 (unalign_dp_load_data_byte2_to_byte3 ), .unalign_dp_load_data_byte2_to_byte4 (unalign_dp_load_data_byte2_to_byte4 ), .unalign_dp_load_data_byte3_to_byte1 (unalign_dp_load_data_byte3_to_byte1 ), .unalign_dp_load_data_byte3_to_byte2 (unalign_dp_load_data_byte3_to_byte2 ), .unalign_dp_load_data_byte3_to_byte3 (unalign_dp_load_data_byte3_to_byte3 ), .unalign_dp_load_data_byte3_to_byte4 (unalign_dp_load_data_byte3_to_byte4 ), .unalign_dp_load_data_byte4_to_byte1 (unalign_dp_load_data_byte4_to_byte1 ), .unalign_dp_load_data_byte4_to_byte2 (unalign_dp_load_data_byte4_to_byte2 ), .unalign_dp_load_data_byte4_to_byte3 (unalign_dp_load_data_byte4_to_byte3 ), .unalign_dp_load_data_byte4_to_byte4 (unalign_dp_load_data_byte4_to_byte4 ), .unalign_dp_store_data_byte1_to_byte1 (unalign_dp_store_data_byte1_to_byte1), .unalign_dp_store_data_byte1_to_byte2 (unalign_dp_store_data_byte1_to_byte2), .unalign_dp_store_data_byte1_to_byte3 (unalign_dp_store_data_byte1_to_byte3), .unalign_dp_store_data_byte1_to_byte4 (unalign_dp_store_data_byte1_to_byte4), .unalign_dp_store_data_byte2_to_byte1 (unalign_dp_store_data_byte2_to_byte1), .unalign_dp_store_data_byte2_to_byte2 (unalign_dp_store_data_byte2_to_byte2), .unalign_dp_store_data_byte2_to_byte3 (unalign_dp_store_data_byte2_to_byte3), .unalign_dp_store_data_byte2_to_byte4 (unalign_dp_store_data_byte2_to_byte4), .unalign_dp_store_data_byte3_to_byte1 (unalign_dp_store_data_byte3_to_byte1), .unalign_dp_store_data_byte3_to_byte2 (unalign_dp_store_data_byte3_to_byte2), .unalign_dp_store_data_byte3_to_byte3 (unalign_dp_store_data_byte3_to_byte3), .unalign_dp_store_data_byte3_to_byte4 (unalign_dp_store_data_byte3_to_byte4), .unalign_dp_store_data_byte4_to_byte1 (unalign_dp_store_data_byte4_to_byte1), .unalign_dp_store_data_byte4_to_byte2 (unalign_dp_store_data_byte4_to_byte2), .unalign_dp_store_data_byte4_to_byte3 (unalign_dp_store_data_byte4_to_byte3), .unalign_dp_store_data_byte4_to_byte4 (unalign_dp_store_data_byte4_to_byte4) ); cr_lsu_ctrl x_cr_lsu_ctrl ( .bmu_lsu_acc_err (bmu_lsu_acc_err ), .bmu_lsu_bstack_chk_fail (bmu_lsu_bstack_chk_fail ), .bmu_lsu_data_vld (bmu_lsu_data_vld ), .bmu_lsu_grnt (bmu_lsu_grnt ), .bmu_lsu_trans_cmplt (bmu_lsu_trans_cmplt ), .cpurst_b (cpurst_b ), .ctrl_dp_ldst_info_buf_reuse (ctrl_dp_ldst_info_buf_reuse), .ctrl_dp_ldst_req_grnt (ctrl_dp_ldst_req_grnt ), .ctrl_dp_store_buffer_updt (ctrl_dp_store_buffer_updt ), .ctrl_top_req_en (ctrl_top_req_en ), .dp_ctrl_misalign (dp_ctrl_misalign ), .iu_lsu_ex_data_sel (iu_lsu_ex_data_sel ), .iu_lsu_ex_sel (iu_lsu_ex_sel ), .iu_lsu_ex_store (iu_lsu_ex_store ), .iu_lsu_oper_mux_en (iu_lsu_oper_mux_en ), .iu_lsu_stall_without_hready (iu_lsu_stall_without_hready), .iu_lsu_wb_ldst (iu_lsu_wb_ldst ), .iu_lsu_wb_load (iu_lsu_wb_load ), .iu_lsu_wb_store (iu_lsu_wb_store ), .iu_yy_xx_flush (iu_yy_xx_flush ), .lsu_bmu_addr_check_fail (lsu_bmu_addr_check_fail ), .lsu_bmu_idle (lsu_bmu_idle ), .lsu_bmu_req (lsu_bmu_req ), .lsu_bmu_req_without_cmplt (lsu_bmu_req_without_cmplt ), .lsu_bmu_sg_chk_fail (lsu_bmu_sg_chk_fail ), .lsu_bmu_wfd1 (lsu_bmu_wfd1 ), .lsu_had_addr_vld (lsu_had_addr_vld ), .lsu_had_ex_cmplt (lsu_had_ex_cmplt ), .lsu_inst_store (lsu_inst_store ), .lsu_iu_data_vld (lsu_iu_data_vld ), .lsu_iu_expt_vec (lsu_iu_expt_vec ), .lsu_iu_expt_vld (lsu_iu_expt_vld ), .lsu_iu_fast_retire (lsu_iu_fast_retire ), .lsu_iu_req (lsu_iu_req ), .lsu_iu_stall (lsu_iu_stall ), .lsu_iu_stall_noinput (lsu_iu_stall_noinput ), .lsu_iu_wb_acc_err (lsu_iu_wb_acc_err ), .lsu_iu_wb_bstack_chk_fail (lsu_iu_wb_bstack_chk_fail ), .lsu_iu_wb_cmplt (lsu_iu_wb_cmplt ), .lsu_iu_wb_data_vld (lsu_iu_wb_data_vld ), .lsu_iu_wfd (lsu_iu_wfd ), .sm_clk (forever_cpuclk ), .unalign_ctrl_not_last_beat (unalign_ctrl_not_last_beat ), .unalign_ctrl_stall (unalign_ctrl_stall ), .unalign_xx_split_on (unalign_xx_split_on ) ); cr_lsu_randclk x_randclk ( .randclk_dp_size_buf_mod_en_w5 (randclk_dp_size_buf_mod_en_w5) ); cr_lsu_unalign x_cr_lsu_unalign ( .unalign_ctrl_not_last_beat (unalign_ctrl_not_last_beat ), .unalign_ctrl_stall (unalign_ctrl_stall ), .unalign_dp_first_req (unalign_dp_first_req ), .unalign_dp_load_data_byte1_to_byte1 (unalign_dp_load_data_byte1_to_byte1 ), .unalign_dp_load_data_byte1_to_byte2 (unalign_dp_load_data_byte1_to_byte2 ), .unalign_dp_load_data_byte1_to_byte3 (unalign_dp_load_data_byte1_to_byte3 ), .unalign_dp_load_data_byte1_to_byte4 (unalign_dp_load_data_byte1_to_byte4 ), .unalign_dp_load_data_byte2_to_byte1 (unalign_dp_load_data_byte2_to_byte1 ), .unalign_dp_load_data_byte2_to_byte2 (unalign_dp_load_data_byte2_to_byte2 ), .unalign_dp_load_data_byte2_to_byte3 (unalign_dp_load_data_byte2_to_byte3 ), .unalign_dp_load_data_byte2_to_byte4 (unalign_dp_load_data_byte2_to_byte4 ), .unalign_dp_load_data_byte3_to_byte1 (unalign_dp_load_data_byte3_to_byte1 ), .unalign_dp_load_data_byte3_to_byte2 (unalign_dp_load_data_byte3_to_byte2 ), .unalign_dp_load_data_byte3_to_byte3 (unalign_dp_load_data_byte3_to_byte3 ), .unalign_dp_load_data_byte3_to_byte4 (unalign_dp_load_data_byte3_to_byte4 ), .unalign_dp_load_data_byte4_to_byte1 (unalign_dp_load_data_byte4_to_byte1 ), .unalign_dp_load_data_byte4_to_byte2 (unalign_dp_load_data_byte4_to_byte2 ), .unalign_dp_load_data_byte4_to_byte3 (unalign_dp_load_data_byte4_to_byte3 ), .unalign_dp_load_data_byte4_to_byte4 (unalign_dp_load_data_byte4_to_byte4 ), .unalign_dp_store_data_byte1_to_byte1 (unalign_dp_store_data_byte1_to_byte1), .unalign_dp_store_data_byte1_to_byte2 (unalign_dp_store_data_byte1_to_byte2), .unalign_dp_store_data_byte1_to_byte3 (unalign_dp_store_data_byte1_to_byte3), .unalign_dp_store_data_byte1_to_byte4 (unalign_dp_store_data_byte1_to_byte4), .unalign_dp_store_data_byte2_to_byte1 (unalign_dp_store_data_byte2_to_byte1), .unalign_dp_store_data_byte2_to_byte2 (unalign_dp_store_data_byte2_to_byte2), .unalign_dp_store_data_byte2_to_byte3 (unalign_dp_store_data_byte2_to_byte3), .unalign_dp_store_data_byte2_to_byte4 (unalign_dp_store_data_byte2_to_byte4), .unalign_dp_store_data_byte3_to_byte1 (unalign_dp_store_data_byte3_to_byte1), .unalign_dp_store_data_byte3_to_byte2 (unalign_dp_store_data_byte3_to_byte2), .unalign_dp_store_data_byte3_to_byte3 (unalign_dp_store_data_byte3_to_byte3), .unalign_dp_store_data_byte3_to_byte4 (unalign_dp_store_data_byte3_to_byte4), .unalign_dp_store_data_byte4_to_byte1 (unalign_dp_store_data_byte4_to_byte1), .unalign_dp_store_data_byte4_to_byte2 (unalign_dp_store_data_byte4_to_byte2), .unalign_dp_store_data_byte4_to_byte3 (unalign_dp_store_data_byte4_to_byte3), .unalign_dp_store_data_byte4_to_byte4 (unalign_dp_store_data_byte4_to_byte4), .unalign_top_clk_en (unalign_top_clk_en ), .unalign_xx_split_on (unalign_xx_split_on ) ); endmodule module cr_lsu_unalign( unalign_ctrl_not_last_beat, unalign_ctrl_stall, unalign_dp_first_req, unalign_dp_load_data_byte1_to_byte1, unalign_dp_load_data_byte1_to_byte2, unalign_dp_load_data_byte1_to_byte3, unalign_dp_load_data_byte1_to_byte4, unalign_dp_load_data_byte2_to_byte1, unalign_dp_load_data_byte2_to_byte2, unalign_dp_load_data_byte2_to_byte3, unalign_dp_load_data_byte2_to_byte4, unalign_dp_load_data_byte3_to_byte1, unalign_dp_load_data_byte3_to_byte2, unalign_dp_load_data_byte3_to_byte3, unalign_dp_load_data_byte3_to_byte4, unalign_dp_load_data_byte4_to_byte1, unalign_dp_load_data_byte4_to_byte2, unalign_dp_load_data_byte4_to_byte3, unalign_dp_load_data_byte4_to_byte4, unalign_dp_store_data_byte1_to_byte1, unalign_dp_store_data_byte1_to_byte2, unalign_dp_store_data_byte1_to_byte3, unalign_dp_store_data_byte1_to_byte4, unalign_dp_store_data_byte2_to_byte1, unalign_dp_store_data_byte2_to_byte2, unalign_dp_store_data_byte2_to_byte3, unalign_dp_store_data_byte2_to_byte4, unalign_dp_store_data_byte3_to_byte1, unalign_dp_store_data_byte3_to_byte2, unalign_dp_store_data_byte3_to_byte3, unalign_dp_store_data_byte3_to_byte4, unalign_dp_store_data_byte4_to_byte1, unalign_dp_store_data_byte4_to_byte2, unalign_dp_store_data_byte4_to_byte3, unalign_dp_store_data_byte4_to_byte4, unalign_top_clk_en, unalign_xx_split_on ); output unalign_ctrl_not_last_beat; output unalign_ctrl_stall; output unalign_dp_first_req; output unalign_dp_load_data_byte1_to_byte1; output unalign_dp_load_data_byte1_to_byte2; output unalign_dp_load_data_byte1_to_byte3; output unalign_dp_load_data_byte1_to_byte4; output unalign_dp_load_data_byte2_to_byte1; output unalign_dp_load_data_byte2_to_byte2; output unalign_dp_load_data_byte2_to_byte3; output unalign_dp_load_data_byte2_to_byte4; output unalign_dp_load_data_byte3_to_byte1; output unalign_dp_load_data_byte3_to_byte2; output unalign_dp_load_data_byte3_to_byte3; output unalign_dp_load_data_byte3_to_byte4; output unalign_dp_load_data_byte4_to_byte1; output unalign_dp_load_data_byte4_to_byte2; output unalign_dp_load_data_byte4_to_byte3; output unalign_dp_load_data_byte4_to_byte4; output unalign_dp_store_data_byte1_to_byte1; output unalign_dp_store_data_byte1_to_byte2; output unalign_dp_store_data_byte1_to_byte3; output unalign_dp_store_data_byte1_to_byte4; output unalign_dp_store_data_byte2_to_byte1; output unalign_dp_store_data_byte2_to_byte2; output unalign_dp_store_data_byte2_to_byte3; output unalign_dp_store_data_byte2_to_byte4; output unalign_dp_store_data_byte3_to_byte1; output unalign_dp_store_data_byte3_to_byte2; output unalign_dp_store_data_byte3_to_byte3; output unalign_dp_store_data_byte3_to_byte4; output unalign_dp_store_data_byte4_to_byte1; output unalign_dp_store_data_byte4_to_byte2; output unalign_dp_store_data_byte4_to_byte3; output unalign_dp_store_data_byte4_to_byte4; output unalign_top_clk_en; output unalign_xx_split_on; wire unalign_ctrl_not_last_beat; wire unalign_ctrl_stall; wire unalign_dp_first_req; wire unalign_dp_load_data_byte1_to_byte1; wire unalign_dp_load_data_byte1_to_byte2; wire unalign_dp_load_data_byte1_to_byte3; wire unalign_dp_load_data_byte1_to_byte4; wire unalign_dp_load_data_byte2_to_byte1; wire unalign_dp_load_data_byte2_to_byte2; wire unalign_dp_load_data_byte2_to_byte3; wire unalign_dp_load_data_byte2_to_byte4; wire unalign_dp_load_data_byte3_to_byte1; wire unalign_dp_load_data_byte3_to_byte2; wire unalign_dp_load_data_byte3_to_byte3; wire unalign_dp_load_data_byte3_to_byte4; wire unalign_dp_load_data_byte4_to_byte1; wire unalign_dp_load_data_byte4_to_byte2; wire unalign_dp_load_data_byte4_to_byte3; wire unalign_dp_load_data_byte4_to_byte4; wire unalign_dp_store_data_byte1_to_byte1; wire unalign_dp_store_data_byte1_to_byte2; wire unalign_dp_store_data_byte1_to_byte3; wire unalign_dp_store_data_byte1_to_byte4; wire unalign_dp_store_data_byte2_to_byte1; wire unalign_dp_store_data_byte2_to_byte2; wire unalign_dp_store_data_byte2_to_byte3; wire unalign_dp_store_data_byte2_to_byte4; wire unalign_dp_store_data_byte3_to_byte1; wire unalign_dp_store_data_byte3_to_byte2; wire unalign_dp_store_data_byte3_to_byte3; wire unalign_dp_store_data_byte3_to_byte4; wire unalign_dp_store_data_byte4_to_byte1; wire unalign_dp_store_data_byte4_to_byte2; wire unalign_dp_store_data_byte4_to_byte3; wire unalign_dp_store_data_byte4_to_byte4; wire unalign_top_clk_en; wire unalign_xx_split_on; assign unalign_top_clk_en = 1'b0; assign unalign_ctrl_not_last_beat = 1'b0; assign unalign_ctrl_stall = 1'b0; assign unalign_dp_first_req = 1'b1; assign unalign_xx_split_on = 1'b0; assign unalign_dp_load_data_byte1_to_byte1 = 1'b0; assign unalign_dp_load_data_byte1_to_byte2 = 1'b0; assign unalign_dp_load_data_byte1_to_byte3 = 1'b0; assign unalign_dp_load_data_byte1_to_byte4 = 1'b0; assign unalign_dp_load_data_byte2_to_byte1 = 1'b0; assign unalign_dp_load_data_byte2_to_byte2 = 1'b0; assign unalign_dp_load_data_byte2_to_byte3 = 1'b0; assign unalign_dp_load_data_byte2_to_byte4 = 1'b0; assign unalign_dp_load_data_byte3_to_byte1 = 1'b0; assign unalign_dp_load_data_byte3_to_byte2 = 1'b0; assign unalign_dp_load_data_byte3_to_byte3 = 1'b0; assign unalign_dp_load_data_byte3_to_byte4 = 1'b0; assign unalign_dp_load_data_byte4_to_byte1 = 1'b0; assign unalign_dp_load_data_byte4_to_byte2 = 1'b0; assign unalign_dp_load_data_byte4_to_byte3 = 1'b0; assign unalign_dp_load_data_byte4_to_byte4 = 1'b0; assign unalign_dp_store_data_byte1_to_byte1 = 1'b0; assign unalign_dp_store_data_byte1_to_byte2 = 1'b0; assign unalign_dp_store_data_byte1_to_byte3 = 1'b0; assign unalign_dp_store_data_byte1_to_byte4 = 1'b0; assign unalign_dp_store_data_byte2_to_byte1 = 1'b0; assign unalign_dp_store_data_byte2_to_byte2 = 1'b0; assign unalign_dp_store_data_byte2_to_byte3 = 1'b0; assign unalign_dp_store_data_byte2_to_byte4 = 1'b0; assign unalign_dp_store_data_byte3_to_byte1 = 1'b0; assign unalign_dp_store_data_byte3_to_byte2 = 1'b0; assign unalign_dp_store_data_byte3_to_byte3 = 1'b0; assign unalign_dp_store_data_byte3_to_byte4 = 1'b0; assign unalign_dp_store_data_byte4_to_byte1 = 1'b0; assign unalign_dp_store_data_byte4_to_byte2 = 1'b0; assign unalign_dp_store_data_byte4_to_byte3 = 1'b0; assign unalign_dp_store_data_byte4_to_byte4 = 1'b0; endmodule module cr_pwrm_top_dummy( pwrm_cpu_bus_peak_power_limit_en ); output pwrm_cpu_bus_peak_power_limit_en; wire pwrm_cpu_bus_peak_power_limit_en; assign pwrm_cpu_bus_peak_power_limit_en = 1'b0; endmodule module cr_rst_top( cpurst_b, hadrst_b, pad_cpu_rst_b, pad_had_jtg_trst_b, pad_had_rst_b, pad_yy_test_mode, trst_b ); input pad_cpu_rst_b; input pad_had_jtg_trst_b; input pad_had_rst_b; input pad_yy_test_mode; output cpurst_b; output hadrst_b; output trst_b; wire cpurst_b; wire hadrst_b; wire pad_cpu_rst_b; wire pad_had_jtg_trst_b; wire pad_had_rst_b; wire pad_yy_test_mode; wire trst_b; assign cpurst_b = pad_yy_test_mode ? pad_had_jtg_trst_b : pad_cpu_rst_b; assign hadrst_b = pad_yy_test_mode ? pad_had_jtg_trst_b : pad_had_rst_b; assign trst_b = pad_had_jtg_trst_b; endmodule module cr_sahbl_top( ahblif_idle, biu_bmu_dbus_acc_err, biu_bmu_dbus_data, biu_bmu_dbus_data_vld, biu_bmu_dbus_grnt, biu_bmu_dbus_trans_cmplt, biu_bmu_ibus_acc_err, biu_bmu_ibus_data, biu_bmu_ibus_data_vld, biu_bmu_ibus_grnt, biu_bmu_ibus_trans_cmplt, biu_pad_haddr, biu_pad_hburst, biu_pad_hprot, biu_pad_hsize, biu_pad_htrans, biu_pad_hwdata, biu_pad_hwrite, biu_pad_vec_redrct, bmu_biu_dbus_acc_deny, bmu_biu_dbus_addr, bmu_biu_dbus_chk_fail, bmu_biu_dbus_prot, bmu_biu_dbus_req, bmu_biu_dbus_req_without_cmplt, bmu_biu_dbus_size, bmu_biu_dbus_wdata, bmu_biu_dbus_write, bmu_biu_ibus_acc_deny, bmu_biu_ibus_addr, bmu_biu_ibus_hit, bmu_biu_ibus_prot, bmu_biu_ibus_req, bmu_biu_ibus_req_no_hit, bmu_biu_ibus_size, bmu_biu_ibus_vec_redirect, cpurst_b, dahblif_other_mask, forever_cpuclk, iahblif_other_mask, pad_biu_hrdata, pad_biu_hready, pad_biu_hresp, pad_cpu_halt_ff2, pad_yy_gate_clk_en_b, pad_yy_test_mode, pwrm_cpu_bus_peak_power_limit_en, sahblif_iahblif_mask ); input bmu_biu_dbus_acc_deny; input [31:0] bmu_biu_dbus_addr; input bmu_biu_dbus_chk_fail; input [3 :0] bmu_biu_dbus_prot; input bmu_biu_dbus_req; input bmu_biu_dbus_req_without_cmplt; input [1 :0] bmu_biu_dbus_size; input [31:0] bmu_biu_dbus_wdata; input bmu_biu_dbus_write; input bmu_biu_ibus_acc_deny; input [31:0] bmu_biu_ibus_addr; input bmu_biu_ibus_hit; input [3 :0] bmu_biu_ibus_prot; input bmu_biu_ibus_req; input bmu_biu_ibus_req_no_hit; input [1 :0] bmu_biu_ibus_size; input bmu_biu_ibus_vec_redirect; input cpurst_b; input dahblif_other_mask; input forever_cpuclk; input iahblif_other_mask; input [31:0] pad_biu_hrdata; input pad_biu_hready; input pad_biu_hresp; input pad_cpu_halt_ff2; input pad_yy_gate_clk_en_b; input pad_yy_test_mode; input pwrm_cpu_bus_peak_power_limit_en; output ahblif_idle; output biu_bmu_dbus_acc_err; output [31:0] biu_bmu_dbus_data; output biu_bmu_dbus_data_vld; output biu_bmu_dbus_grnt; output biu_bmu_dbus_trans_cmplt; output biu_bmu_ibus_acc_err; output [31:0] biu_bmu_ibus_data; output biu_bmu_ibus_data_vld; output biu_bmu_ibus_grnt; output biu_bmu_ibus_trans_cmplt; output [31:0] biu_pad_haddr; output [2 :0] biu_pad_hburst; output [3 :0] biu_pad_hprot; output [2 :0] biu_pad_hsize; output [1 :0] biu_pad_htrans; output [31:0] biu_pad_hwdata; output biu_pad_hwrite; output biu_pad_vec_redrct; output sahblif_iahblif_mask; wire ahbl_clk_en; wire ahbl_gated_clk; wire ahblif_busy; wire ahblif_idle; wire ahblif_power_mask; wire biu_bmu_dbus_acc_err; wire [31:0] biu_bmu_dbus_data; wire biu_bmu_dbus_data_vld; wire biu_bmu_dbus_grnt; wire biu_bmu_dbus_trans_cmplt; wire biu_bmu_ibus_acc_err; wire [31:0] biu_bmu_ibus_data; wire biu_bmu_ibus_data_vld; wire biu_bmu_ibus_grnt; wire biu_bmu_ibus_trans_cmplt; wire [31:0] biu_pad_haddr; wire [2 :0] biu_pad_hburst; wire [3 :0] biu_pad_hprot; wire [2 :0] biu_pad_hsize; wire [1 :0] biu_pad_htrans; wire [31:0] biu_pad_hwdata; wire biu_pad_hwrite; wire biu_pad_vec_redrct; wire bmu_biu_dbus_acc_deny; wire [31:0] bmu_biu_dbus_addr; wire bmu_biu_dbus_chk_fail; wire [3 :0] bmu_biu_dbus_prot; wire bmu_biu_dbus_req; wire bmu_biu_dbus_req_without_cmplt; wire [1 :0] bmu_biu_dbus_size; wire [31:0] bmu_biu_dbus_wdata; wire bmu_biu_dbus_write; wire bmu_biu_ibus_acc_deny; wire [31:0] bmu_biu_ibus_addr; wire bmu_biu_ibus_hit; wire [3 :0] bmu_biu_ibus_prot; wire bmu_biu_ibus_req; wire bmu_biu_ibus_req_no_hit; wire [1 :0] bmu_biu_ibus_size; wire bmu_biu_ibus_vec_redirect; wire cpu_acc_err; wire [31:0] cpu_addr; wire cpu_data_vld; wire [3 :0] cpu_prot; wire [31:0] cpu_rdata; wire cpu_req; wire cpu_req_for_grnt; wire cpu_req_for_peak_power; wire cpu_req_grnt; wire cpu_req_power_masked; wire cpu_sec; wire [1 :0] cpu_size; wire cpu_trans_cmplt; wire cpu_vec_redirect; wire [31:0] cpu_wdata; wire cpu_wdata_sel; wire cpu_write; wire cpurst_b; wire dahblif_other_mask; wire dbus_mask; wire forever_cpuclk; wire iahblif_other_mask; wire ibus_not_granted; wire [31:0] pad_biu_hrdata; wire pad_biu_hready; wire pad_biu_hresp; wire pad_cpu_halt_ff2; wire pad_yy_gate_clk_en_b; wire pad_yy_test_mode; wire pwrm_cpu_bus_peak_power_limit_en; wire sahblif_iahblif_mask; gated_clk_cell x_gated_ahbl_cpuclk_cell ( .clk_in (forever_cpuclk ), .clk_out (ahbl_gated_clk ), .external_en (1'b0 ), .global_en (1'b1 ), .local_en (dbus_mask ), .module_en (ahbl_clk_en ), .pad_yy_gate_clk_en_b (pad_yy_gate_clk_en_b), .pad_yy_test_mode (pad_yy_test_mode ) ); cr_ahbl_req_arb x_cr_ahbl_req_arb ( .ahbl_bmu_dbus_acc_err (biu_bmu_dbus_acc_err ), .ahbl_bmu_dbus_data (biu_bmu_dbus_data ), .ahbl_bmu_dbus_data_vld (biu_bmu_dbus_data_vld ), .ahbl_bmu_dbus_grnt (biu_bmu_dbus_grnt ), .ahbl_bmu_dbus_trans_cmplt (biu_bmu_dbus_trans_cmplt ), .ahbl_bmu_ibus_acc_err (biu_bmu_ibus_acc_err ), .ahbl_bmu_ibus_data (biu_bmu_ibus_data ), .ahbl_bmu_ibus_data_vld (biu_bmu_ibus_data_vld ), .ahbl_bmu_ibus_grnt (biu_bmu_ibus_grnt ), .ahbl_bmu_ibus_trans_cmplt (biu_bmu_ibus_trans_cmplt ), .ahbl_gated_clk (ahbl_gated_clk ), .bmu_ahbl_dbus_acc_deny (bmu_biu_dbus_acc_deny ), .bmu_ahbl_dbus_addr (bmu_biu_dbus_addr ), .bmu_ahbl_dbus_chk_fail (bmu_biu_dbus_chk_fail ), .bmu_ahbl_dbus_prot (bmu_biu_dbus_prot ), .bmu_ahbl_dbus_req (bmu_biu_dbus_req ), .bmu_ahbl_dbus_req_without_cmplt (bmu_biu_dbus_req_without_cmplt ), .bmu_ahbl_dbus_req_without_deny_chk_fail (bmu_biu_dbus_req ), .bmu_ahbl_dbus_size (bmu_biu_dbus_size ), .bmu_ahbl_dbus_write (bmu_biu_dbus_write ), .bmu_ahbl_ibus_acc_deny (bmu_biu_ibus_acc_deny ), .bmu_ahbl_ibus_addr (bmu_biu_ibus_addr ), .bmu_ahbl_ibus_hit (bmu_biu_ibus_hit ), .bmu_ahbl_ibus_prot (bmu_biu_ibus_prot ), .bmu_ahbl_ibus_req (bmu_biu_ibus_req ), .bmu_ahbl_ibus_req_no_hit (bmu_biu_ibus_req_no_hit ), .bmu_ahbl_ibus_size (bmu_biu_ibus_size ), .bmu_ahbl_ibus_vec_redirect (bmu_biu_ibus_vec_redirect ), .bmu_ahbl_ibus_write (1'b0 ), .bmu_ahbl_wdata (bmu_biu_dbus_wdata ), .cpu_acc_err (cpu_acc_err ), .cpu_addr (cpu_addr ), .cpu_data_vld (cpu_data_vld ), .cpu_prot (cpu_prot ), .cpu_rdata (cpu_rdata ), .cpu_req (cpu_req ), .cpu_req_for_grnt (cpu_req_for_grnt ), .cpu_req_for_peak_power (cpu_req_for_peak_power ), .cpu_req_grnt (cpu_req_grnt ), .cpu_sec (cpu_sec ), .cpu_size (cpu_size ), .cpu_trans_cmplt (cpu_trans_cmplt ), .cpu_vec_redirect (cpu_vec_redirect ), .cpu_wdata (cpu_wdata ), .cpu_write (cpu_write ), .cpurst_b (cpurst_b ), .ibus_not_granted (ibus_not_granted ) ); assign dbus_mask = ibus_not_granted; cr_ahbl_if x_cr_ahbl_if ( .ahbLif_ahbl_haddr (biu_pad_haddr ), .ahbLif_ahbl_hburst (biu_pad_hburst ), .ahbLif_ahbl_hprot (biu_pad_hprot ), .ahbLif_ahbl_hsize (biu_pad_hsize ), .ahbLif_ahbl_htrans (biu_pad_htrans ), .ahbLif_ahbl_hwdata (biu_pad_hwdata ), .ahbLif_ahbl_hwrite (biu_pad_hwrite ), .ahbLif_ahbl_vec_redrct (biu_pad_vec_redrct ), .ahbl_ahbLif_hrdata (pad_biu_hrdata ), .ahbl_ahbLif_hready (pad_biu_hready ), .ahbl_ahbLif_hresp (pad_biu_hresp ), .ahbl_clk_en (ahbl_clk_en ), .ahbl_gated_clk (ahbl_gated_clk ), .ahblif_busy (ahblif_busy ), .ahblif_idle (ahblif_idle ), .ahblif_power_mask (ahblif_power_mask ), .cpu_acc_err (cpu_acc_err ), .cpu_addr (cpu_addr ), .cpu_data_vld (cpu_data_vld ), .cpu_prot (cpu_prot ), .cpu_rdata (cpu_rdata ), .cpu_req (cpu_req ), .cpu_req_grnt (cpu_req_grnt ), .cpu_req_power_masked (cpu_req_power_masked ), .cpu_sec (cpu_sec ), .cpu_size (cpu_size ), .cpu_trans_cmplt (cpu_trans_cmplt ), .cpu_vec_redirect (cpu_vec_redirect ), .cpu_wdata_sel (cpu_wdata_sel ), .cpu_wr_data (cpu_wdata ), .cpu_write (cpu_write ), .cpurst_b (cpurst_b ), .pad_cpu_halt_ff2 (pad_cpu_halt_ff2 ) ); assign sahblif_iahblif_mask = (ahblif_busy || cpu_req_for_peak_power) && pwrm_cpu_bus_peak_power_limit_en; assign ahblif_power_mask = iahblif_other_mask || dahblif_other_mask; assign cpu_req_power_masked = cpu_req && !ahblif_power_mask; endmodule module cr_sys_io( clk_en, cp0_sysio_ipend_b, cp0_sysio_lpmd_b, cpurst_b, forever_cpuclk, had_yy_xx_dbg, iu_sys_lp_wk_int, iu_sysyio_soft_rst, iu_yy_xx_dbgon, pad_sysio_bigend_b, pad_sysio_clkratio, pad_sysio_endian_v2, pad_yy_gate_clk_en_b, pad_yy_test_mode, sysio_cp0_bigend, sysio_cp0_clkratio, sysio_cp0_endian_v2, sysio_cp0_sys_view_lpmd_b, sysio_pad_dbg_b, sysio_pad_ipend_b, sysio_pad_lpmd_b, sysio_pad_srst, sysio_pad_wakeup_b ); input clk_en; input cp0_sysio_ipend_b; input [1:0] cp0_sysio_lpmd_b; input cpurst_b; input forever_cpuclk; input had_yy_xx_dbg; input iu_sys_lp_wk_int; input iu_sysyio_soft_rst; input iu_yy_xx_dbgon; input pad_sysio_bigend_b; input [2:0] pad_sysio_clkratio; input pad_sysio_endian_v2; input pad_yy_gate_clk_en_b; input pad_yy_test_mode; output sysio_cp0_bigend; output [2:0] sysio_cp0_clkratio; output sysio_cp0_endian_v2; output [1:0] sysio_cp0_sys_view_lpmd_b; output sysio_pad_dbg_b; output sysio_pad_ipend_b; output [1:0] sysio_pad_lpmd_b; output sysio_pad_srst; output sysio_pad_wakeup_b; reg sysio_pad_dbg_b; reg sysio_pad_ipend_b; reg [1:0] sysio_pad_lpmd_b; reg sysio_pad_wakeup_b; wire clk_en; wire cp0_sysio_ipend_b; wire [1:0] cp0_sysio_lpmd_b; wire cpu_wake_up_b; wire cpurst_b; wire forever_cpuclk; wire had_yy_xx_dbg; wire iu_sys_lp_wk_int; wire iu_sysyio_soft_rst; wire iu_yy_xx_dbgon; wire pad_sysio_bigend_b; wire [2:0] pad_sysio_clkratio; wire pad_sysio_endian_v2; wire pad_yy_gate_clk_en_b; wire pad_yy_test_mode; wire sysio_cp0_bigend; wire [2:0] sysio_cp0_clkratio; wire sysio_cp0_endian_v2; wire [1:0] sysio_cp0_sys_view_lpmd_b; wire sysio_lpmd_gated_clk; wire sysio_lpmd_gated_en; wire sysio_pad_srst; gated_clk_cell x_gated_sysio_lpmd_cpuclk_cell ( .clk_in (forever_cpuclk ), .clk_out (sysio_lpmd_gated_clk), .external_en (1'b0 ), .global_en (1'b1 ), .local_en (sysio_lpmd_gated_en ), .module_en (1'b0 ), .pad_yy_gate_clk_en_b (pad_yy_gate_clk_en_b), .pad_yy_test_mode (pad_yy_test_mode ) ); assign sysio_lpmd_gated_en = ((sysio_pad_dbg_b ^ (~iu_yy_xx_dbgon)) || (sysio_pad_lpmd_b[1] ^ cp0_sysio_lpmd_b[1]) || (sysio_pad_lpmd_b[0] ^ cp0_sysio_lpmd_b[0]) || (sysio_pad_ipend_b ^ cp0_sysio_ipend_b) || (sysio_pad_wakeup_b ^ cpu_wake_up_b)) && clk_en; assign sysio_cp0_bigend =!pad_sysio_bigend_b; assign sysio_cp0_endian_v2 = pad_sysio_endian_v2; assign sysio_cp0_clkratio[2:0] = pad_sysio_clkratio[2:0]; assign cpu_wake_up_b = iu_sys_lp_wk_int && !had_yy_xx_dbg; always @(posedge sysio_lpmd_gated_clk or negedge cpurst_b) begin if(!cpurst_b) begin sysio_pad_dbg_b <= 1'b1; sysio_pad_lpmd_b[1:0] <= 2'b11; sysio_pad_ipend_b <= 1'b0; sysio_pad_wakeup_b <= 1'b0; end else if(clk_en) begin sysio_pad_dbg_b <= ~iu_yy_xx_dbgon; sysio_pad_lpmd_b[1:0] <= cp0_sysio_lpmd_b[1:0]; sysio_pad_ipend_b <= cp0_sysio_ipend_b; sysio_pad_wakeup_b <= cpu_wake_up_b; end end assign sysio_cp0_sys_view_lpmd_b[1:0] = sysio_pad_lpmd_b[1:0]; assign sysio_pad_srst = iu_sysyio_soft_rst; endmodule module cr_tcipif_behavior_bus( bmu_tcipif_dbus_acc_deny, bmu_tcipif_dbus_addr, bmu_tcipif_dbus_chk_fail, bmu_tcipif_dbus_req, bmu_tcipif_dbus_size, bmu_tcipif_dbus_supv_mode, bmu_tcipif_dbus_wdata, bmu_tcipif_dbus_write, coretim_tcipif_cmplt, coretim_tcipif_rdata, cp0_yy_be_v2, cpurst_b, forever_cpuclk, had_img_tcipif_cmplt, had_img_tcipif_rdata, iu_yy_xx_dbgon, pad_yy_gate_clk_en_b, pad_yy_test_mode, tcipif_bmu_dbus_acc_err, tcipif_bmu_dbus_data, tcipif_bmu_dbus_data_vld, tcipif_bmu_dbus_grnt, tcipif_bmu_dbus_trans_cmplt, tcipif_coretim_sel, tcipif_had_img_sel, tcipif_vic_sel, tcipif_vic_size, tcipif_xx_dbus_addr, tcipif_xx_dbus_wdata, tcipif_xx_dbus_write, vic_tcipif_cmplt, vic_tcipif_rdata ); input bmu_tcipif_dbus_acc_deny; input [31:0] bmu_tcipif_dbus_addr; input bmu_tcipif_dbus_chk_fail; input bmu_tcipif_dbus_req; input [1 :0] bmu_tcipif_dbus_size; input bmu_tcipif_dbus_supv_mode; input [31:0] bmu_tcipif_dbus_wdata; input bmu_tcipif_dbus_write; input coretim_tcipif_cmplt; input [31:0] coretim_tcipif_rdata; input cp0_yy_be_v2; input cpurst_b; input forever_cpuclk; input had_img_tcipif_cmplt; input [31:0] had_img_tcipif_rdata; input iu_yy_xx_dbgon; input pad_yy_gate_clk_en_b; input pad_yy_test_mode; input vic_tcipif_cmplt; input [31:0] vic_tcipif_rdata; output tcipif_bmu_dbus_acc_err; output [31:0] tcipif_bmu_dbus_data; output tcipif_bmu_dbus_data_vld; output tcipif_bmu_dbus_grnt; output tcipif_bmu_dbus_trans_cmplt; output tcipif_coretim_sel; output tcipif_had_img_sel; output tcipif_vic_sel; output [1 :0] tcipif_vic_size; output [15:0] tcipif_xx_dbus_addr; output [31:0] tcipif_xx_dbus_wdata; output tcipif_xx_dbus_write; reg coretim_sel_ff; reg dummy_addr_cmplt; reg had_img_sel_ff; reg tcipif_acc_err; reg [15:0] tcipif_xx_dbus_addr; reg vic_sel_ff; reg [1 :0] vic_size_ff; reg xx_dbus_write; reg xx_tcip_grant; wire bmu_tcipif_dbus_acc_deny; wire [31:0] bmu_tcipif_dbus_addr; wire bmu_tcipif_dbus_chk_fail; wire bmu_tcipif_dbus_req; wire [1 :0] bmu_tcipif_dbus_size; wire bmu_tcipif_dbus_supv_mode; wire [31:0] bmu_tcipif_dbus_wdata; wire bmu_tcipif_dbus_write; wire [31:0] bmu_tcipif_had_addr; wire bmu_tcipif_had_req; wire [1 :0] bmu_tcipif_had_size; wire bmu_tcipif_had_supv_mode; wire [31:0] bmu_tcipif_had_wdata; wire bmu_tcipif_had_write; wire cmmu_req_mask; wire cmmu_sel; wire cmmu_tcipif_cmplt; wire [31:0] cmmu_tcipif_rdata; wire coretim_req_mask; wire coretim_tcipif_cmplt; wire [31:0] coretim_tcipif_rdata; wire cp0_yy_be_v2; wire cpurst_b; wire cru_req_mask; wire cru_sel; wire cru_tcipif_cmplt; wire [31:0] cru_tcipif_rdata; wire ctim_sel; wire ctrl_cpuclk; wire dbus_err; wire dbus_req; wire dbus_req_pre; wire dbus_sel; wire dummy_addr_sel; wire forever_cpuclk; wire had_err; wire had_img_req_mask; wire had_img_sel; wire had_img_tcipif_cmplt; wire [31:0] had_img_tcipif_rdata; wire had_req; wire had_req_pre; wire had_sel; wire iu_yy_xx_dbgon; wire pad_yy_gate_clk_en_b; wire pad_yy_test_mode; wire pwrm_req_mask; wire pwrm_sel; wire pwrm_tcipif_cmplt; wire [31:0] pwrm_tcipif_rdata; wire scram_req_mask; wire scram_sel; wire scram_tcipif_cmplt; wire [31:0] scram_tcipif_rdata; wire sel_clk_en; wire sel_cpuclk; wire seu_bist_req_mask; wire seu_bist_sel; wire seu_bist_tcipif_cmplt; wire [31:0] seu_bist_tcipif_rdata; wire seu_req_mask; wire seu_sel; wire seu_tcipif_cmplt; wire [31:0] seu_tcipif_rdata; wire tcip_err; wire tcip_req; wire [31:0] tcip_req_addr; wire tcip_req_mask; wire tcip_req_pre; wire tcipif_bmu_dbus_acc_err; wire [31:0] tcipif_bmu_dbus_data; wire tcipif_bmu_dbus_data_vld; wire tcipif_bmu_dbus_grnt; wire tcipif_bmu_dbus_trans_cmplt; wire tcipif_coretim_sel; wire tcipif_data_vld; wire tcipif_dbus_req; wire [31:0] tcipif_dbus_wdata; wire tcipif_had_img_sel; wire tcipif_had_req; wire [31:0] tcipif_rd_data; wire [31:0] tcipif_rdata; wire tcipif_req_write; wire tcipif_trans_cmplt; wire tcipif_vic_sel; wire [1 :0] tcipif_vic_size; wire [31:0] tcipif_wdata; wire [31:0] tcipif_xx_dbus_wdata; wire tcipif_xx_dbus_write; wire vic_req_mask; wire vic_sel; wire [1 :0] vic_size; wire vic_tcipif_cmplt; wire [31:0] vic_tcipif_rdata; wire xx_tcipif_cmplt; parameter CORETIM_IN = 24'hE000E0; parameter CORETIM_EX = 28'hE000E00; parameter VIC_IN = 20'hE000E; parameter VIC_EX1 = 24'hE000E0; parameter VIC_EX2 = 24'hE000ED; parameter VIC_EX3 = 24'hE000EE; parameter VIC_EX4 = 24'hE000EF; parameter POWER_IN = 28'hE000EF9; parameter SEU_IN = 28'hE000EFA; parameter SCRMB_IN1 = 28'hE000EFB; parameter SCRMB_IN2 = 28'hE000EFC; parameter CRU_IN = 20'hE000F; parameter SEU_BIST_IN = 20'hE0010; parameter HAD_IMG_IN = 20'hE0011; parameter CMMU_IN1 = 24'hE01000; parameter CMMU_IN2 = 24'hE01001; assign bmu_tcipif_had_req = 1'b0; assign bmu_tcipif_had_addr[31:0] = 32'b0; assign bmu_tcipif_had_write = 1'b0; assign bmu_tcipif_had_wdata[31:0] = 32'b0; assign bmu_tcipif_had_supv_mode = 1'b0; assign bmu_tcipif_had_size[1:0] = 2'b0; assign tcipif_dbus_req = bmu_tcipif_dbus_req && !tcip_req_mask && !bmu_tcipif_had_req; assign tcipif_had_req = bmu_tcipif_had_req && !tcip_req_mask; assign dbus_sel = tcipif_dbus_req; assign had_sel = tcipif_had_req; assign dbus_req_pre = tcipif_dbus_req && !bmu_tcipif_dbus_acc_deny && !bmu_tcipif_dbus_chk_fail; assign had_req_pre = tcipif_had_req; assign tcip_req_pre = dbus_req_pre || had_req_pre; assign dbus_req = dbus_req_pre && !dbus_err; assign had_req = had_req_pre && !had_err; assign tcip_req = dbus_req || had_req; assign dbus_err = !bmu_tcipif_dbus_supv_mode && !iu_yy_xx_dbgon; assign had_err = !bmu_tcipif_had_supv_mode; assign tcip_err = dbus_sel && dbus_err || had_sel && had_err; assign tcip_req_addr[31:0] = {32{dbus_sel}} & bmu_tcipif_dbus_addr[31:0] | {32{had_sel}} & bmu_tcipif_had_addr[31:0]; assign tcipif_req_write = dbus_sel && bmu_tcipif_dbus_write || had_sel && bmu_tcipif_had_write; assign ctim_sel = (tcip_req_addr[31:8] == CORETIM_IN) && !(tcip_req_addr[31:4] == CORETIM_EX); assign vic_sel = (tcip_req_addr[31:12] == VIC_IN) && !(tcip_req_addr[31:8] == VIC_EX1) && !(tcip_req_addr[31:8] == VIC_EX2) && !(tcip_req_addr[31:8] == VIC_EX3) && !(tcip_req_addr[31:8] == VIC_EX4); assign pwrm_sel = 1'b0; assign seu_sel = 1'b0; assign scram_sel = 1'b0; assign cru_sel = 1'b0; assign cmmu_sel = 1'b0; assign seu_bist_sel = 1'b0; assign had_img_sel = (tcip_req_addr[31:12] == HAD_IMG_IN); assign dummy_addr_sel = !(ctim_sel || vic_sel || pwrm_sel || seu_sel || scram_sel || cru_sel || seu_bist_sel || had_img_sel || cmmu_sel); assign sel_clk_en = xx_tcipif_cmplt || tcipif_acc_err || dummy_addr_cmplt; gated_clk_cell x_tcipif_dbus_sel_clk ( .clk_in (forever_cpuclk ), .clk_out (sel_cpuclk ), .external_en (1'b0 ), .global_en (1'b1 ), .local_en (tcip_req_pre ), .module_en (sel_clk_en ), .pad_yy_gate_clk_en_b (pad_yy_gate_clk_en_b), .pad_yy_test_mode (pad_yy_test_mode ) ); always @(posedge sel_cpuclk or negedge cpurst_b) begin if(!cpurst_b) tcipif_acc_err <= 1'b0; else if(tcip_req_pre) tcipif_acc_err <= tcip_err; else if(tcipif_acc_err) tcipif_acc_err <= 1'b0; end always @(posedge sel_cpuclk or negedge cpurst_b) begin if(!cpurst_b) coretim_sel_ff <= 1'b0; else if(tcip_req) coretim_sel_ff <= ctim_sel; else if(coretim_tcipif_cmplt) coretim_sel_ff <= 1'b0; end assign tcipif_coretim_sel = coretim_sel_ff; assign coretim_req_mask = coretim_sel_ff && !coretim_tcipif_cmplt; always @(posedge sel_cpuclk or negedge cpurst_b) begin if(!cpurst_b) vic_sel_ff <= 1'b0; else if(tcip_req) vic_sel_ff <= vic_sel; else if(vic_tcipif_cmplt) vic_sel_ff <= 1'b0; end always @(posedge sel_cpuclk or negedge cpurst_b) begin if(!cpurst_b) vic_size_ff[1:0] <= 1'b0; else if(tcip_req) vic_size_ff[1:0] <= vic_size[1:0]; end assign tcipif_vic_sel = vic_sel_ff; assign vic_req_mask = vic_sel_ff && !vic_tcipif_cmplt; assign vic_size[1:0] = {2{dbus_sel}} & bmu_tcipif_dbus_size[1:0] |{2{had_sel}} & bmu_tcipif_had_size[1:0]; assign tcipif_vic_size[1:0] = vic_size_ff[1:0]; assign pwrm_req_mask = 1'b0; assign pwrm_tcipif_cmplt = 1'b0; assign pwrm_tcipif_rdata[31:0] = 32'b0; assign seu_req_mask = 1'b0; assign seu_tcipif_cmplt = 1'b0; assign seu_tcipif_rdata[31:0] = 32'b0; assign scram_req_mask = 1'b0; assign scram_tcipif_cmplt = 1'b0; assign scram_tcipif_rdata[31:0] = 32'b0; assign cru_req_mask = 1'b0; assign cru_tcipif_cmplt = 1'b0; assign cru_tcipif_rdata[31:0] = 32'b0; assign cmmu_req_mask = 1'b0; assign cmmu_tcipif_cmplt = 1'b0; assign cmmu_tcipif_rdata[31:0] = 32'b0; assign seu_bist_req_mask = 1'b0; assign seu_bist_tcipif_cmplt = 1'b0; assign seu_bist_tcipif_rdata[31:0] = 32'b0; always @(posedge sel_cpuclk or negedge cpurst_b) begin if(!cpurst_b) had_img_sel_ff <= 1'b0; else if(tcip_req) had_img_sel_ff <= had_img_sel; else if(had_img_tcipif_cmplt) had_img_sel_ff <= 1'b0; end assign tcipif_had_img_sel = had_img_sel_ff; assign had_img_req_mask = had_img_sel_ff && !had_img_tcipif_cmplt; always @(posedge sel_cpuclk or negedge cpurst_b) begin if(!cpurst_b) dummy_addr_cmplt <= 1'b0; else if(tcip_req) dummy_addr_cmplt <= dummy_addr_sel; else if(dummy_addr_cmplt) dummy_addr_cmplt <= 1'b0; end assign tcip_req_mask = (coretim_req_mask || vic_req_mask || pwrm_req_mask || seu_req_mask || scram_req_mask || cru_req_mask || seu_bist_req_mask || had_img_req_mask || cmmu_req_mask); gated_clk_cell x_tcipif_dbus_ctrl_clk ( .clk_in (forever_cpuclk ), .clk_out (ctrl_cpuclk ), .external_en (1'b0 ), .global_en (1'b1 ), .local_en (tcip_req_pre ), .module_en (1'b0 ), .pad_yy_gate_clk_en_b (pad_yy_gate_clk_en_b), .pad_yy_test_mode (pad_yy_test_mode ) ); always @(posedge ctrl_cpuclk) begin if(!cpurst_b) xx_tcip_grant <= 1'b0; else if(tcip_req_pre) xx_tcip_grant <= had_req_pre; end always @(posedge ctrl_cpuclk) begin if(tcip_req) begin tcipif_xx_dbus_addr[15:0] <= tcip_req_addr[15:0]; xx_dbus_write <= tcipif_req_write; end end assign tcipif_xx_dbus_write = xx_dbus_write; assign tcipif_wdata[31:0] = xx_tcip_grant ? bmu_tcipif_had_wdata[31:0] : bmu_tcipif_dbus_wdata[31:0]; assign tcipif_dbus_wdata[31:0] = tcipif_wdata[31:0]; assign tcipif_xx_dbus_wdata[31:0] = cp0_yy_be_v2 ? {tcipif_dbus_wdata[7:0], tcipif_dbus_wdata[15:8], tcipif_dbus_wdata[23:16],tcipif_dbus_wdata[31:24]} : tcipif_dbus_wdata[31:0]; assign tcipif_bmu_dbus_grnt = tcipif_dbus_req ; assign xx_tcipif_cmplt = coretim_tcipif_cmplt || vic_tcipif_cmplt || pwrm_tcipif_cmplt || seu_tcipif_cmplt || scram_tcipif_cmplt || cru_tcipif_cmplt || seu_bist_tcipif_cmplt || had_img_tcipif_cmplt || cmmu_tcipif_cmplt; assign tcipif_trans_cmplt = xx_tcipif_cmplt || dummy_addr_cmplt || tcipif_acc_err; assign tcipif_bmu_dbus_trans_cmplt = !xx_tcip_grant && tcipif_trans_cmplt; assign tcipif_data_vld = (xx_tcipif_cmplt || dummy_addr_cmplt) && !xx_dbus_write; assign tcipif_bmu_dbus_data_vld = !xx_tcip_grant && tcipif_data_vld; assign tcipif_bmu_dbus_acc_err = !xx_tcip_grant && tcipif_acc_err; assign tcipif_rd_data[31:0] = {32{coretim_tcipif_cmplt}} & coretim_tcipif_rdata[31:0] | {32{vic_tcipif_cmplt}} & vic_tcipif_rdata[31:0] | {32{pwrm_tcipif_cmplt}} & pwrm_tcipif_rdata[31:0] | {32{seu_tcipif_cmplt}} & seu_tcipif_rdata[31:0] | {32{scram_tcipif_cmplt}} & scram_tcipif_rdata[31:0] | {32{cru_tcipif_cmplt}} & cru_tcipif_rdata[31:0] | {32{seu_bist_tcipif_cmplt}} & seu_bist_tcipif_rdata[31:0] | {32{had_img_tcipif_cmplt}} & had_img_tcipif_rdata[31:0] | {32{cmmu_tcipif_cmplt}} & cmmu_tcipif_rdata[31:0]; assign tcipif_rdata[31:0] = cp0_yy_be_v2 ? {tcipif_rd_data[7:0], tcipif_rd_data[15:8], tcipif_rd_data[23:16],tcipif_rd_data[31:24]} : tcipif_rd_data[31:0]; assign tcipif_bmu_dbus_data[31:0] = tcipif_rdata[31:0]; endmodule module cr_tcipif_dummy_bus( bmu_tcipif_ibus_acc_deny, bmu_tcipif_ibus_addr, bmu_tcipif_ibus_req, bmu_tcipif_ibus_write, cpurst_b, forever_cpuclk, pad_yy_gate_clk_en_b, pad_yy_test_mode, tcipif_bmu_ibus_acc_err, tcipif_bmu_ibus_data, tcipif_bmu_ibus_data_vld, tcipif_bmu_ibus_grnt, tcipif_bmu_ibus_trans_cmplt ); input bmu_tcipif_ibus_acc_deny; input [31:0] bmu_tcipif_ibus_addr; input bmu_tcipif_ibus_req; input bmu_tcipif_ibus_write; input cpurst_b; input forever_cpuclk; input pad_yy_gate_clk_en_b; input pad_yy_test_mode; output tcipif_bmu_ibus_acc_err; output [31:0] tcipif_bmu_ibus_data; output tcipif_bmu_ibus_data_vld; output tcipif_bmu_ibus_grnt; output tcipif_bmu_ibus_trans_cmplt; reg bus_next_state; reg bus_state; wire bmu_tcipif_ibus_acc_deny; wire bmu_tcipif_ibus_req; wire cpurst_b; wire forever_cpuclk; wire ibus_acc_err; wire ibus_busy; wire ibus_req; wire pad_yy_gate_clk_en_b; wire pad_yy_test_mode; wire sel_cpuclk; wire tcipif_bmu_ibus_acc_err; wire [31:0] tcipif_bmu_ibus_data; wire tcipif_bmu_ibus_data_vld; wire tcipif_bmu_ibus_grnt; wire tcipif_bmu_ibus_trans_cmplt; assign tcipif_bmu_ibus_grnt = bmu_tcipif_ibus_req; assign ibus_req = bmu_tcipif_ibus_req && !bmu_tcipif_ibus_acc_deny; parameter IDLE = 1'b0, ERROR = 1'b1; gated_clk_cell x_tcipif_ibus_sel_clk ( .clk_in (forever_cpuclk ), .clk_out (sel_cpuclk ), .external_en (1'b0 ), .global_en (1'b1 ), .local_en (bmu_tcipif_ibus_req ), .module_en (ibus_busy ), .pad_yy_gate_clk_en_b (pad_yy_gate_clk_en_b), .pad_yy_test_mode (pad_yy_test_mode ) ); assign ibus_busy = (bus_state != IDLE); always@(posedge sel_cpuclk or negedge cpurst_b) begin if(!cpurst_b) bus_state <= IDLE; else bus_state <= bus_next_state; end always @( bus_state or ibus_req) begin case(bus_state) IDLE: if(ibus_req) bus_next_state = ERROR; else bus_next_state = IDLE; ERROR: if(ibus_req) bus_next_state = ERROR; else bus_next_state = IDLE; default: bus_next_state = IDLE; endcase end assign ibus_acc_err = (bus_state == ERROR); assign tcipif_bmu_ibus_trans_cmplt = ibus_acc_err; assign tcipif_bmu_ibus_acc_err = ibus_acc_err; assign tcipif_bmu_ibus_data_vld = 1'b0; assign tcipif_bmu_ibus_data[31:0] = 32'b0; endmodule module cr_tcipif_top( bmu_tcipif_dbus_acc_deny, bmu_tcipif_dbus_addr, bmu_tcipif_dbus_chk_fail, bmu_tcipif_dbus_req, bmu_tcipif_dbus_size, bmu_tcipif_dbus_supv_mode, bmu_tcipif_dbus_wdata, bmu_tcipif_dbus_write, bmu_tcipif_ibus_acc_deny, bmu_tcipif_ibus_addr, bmu_tcipif_ibus_req, bmu_tcipif_ibus_write, clic_cpu_int_hv, clic_cpu_int_id, clic_cpu_int_il, clic_cpu_int_priv, cp0_yy_be_v2, cpu_clic_curid, cpu_clic_int_exit, cpurst_b, ctim_pad_int_vld, forever_cpuclk, forever_cpuclk_nogated, had_tcipif_cmplt, had_tcipif_rdata, iu_yy_xx_dbgon, pad_clic_int_cfg, pad_clic_int_vld, pad_ctim_calib, pad_ctim_refclk, pad_yy_gate_clk_en_b, pad_yy_test_mode, pwrm_cpu_bus_peak_power_limit_en, tcipif_bmu_dbus_acc_err, tcipif_bmu_dbus_data, tcipif_bmu_dbus_data_vld, tcipif_bmu_dbus_grnt, tcipif_bmu_dbus_trans_cmplt, tcipif_bmu_ibus_acc_err, tcipif_bmu_ibus_data, tcipif_bmu_ibus_data_vld, tcipif_bmu_ibus_grnt, tcipif_bmu_ibus_trans_cmplt, tcipif_had_addr, tcipif_had_sel, tcipif_had_wdata, tcipif_had_write ); input bmu_tcipif_dbus_acc_deny; input [31:0] bmu_tcipif_dbus_addr; input bmu_tcipif_dbus_chk_fail; input bmu_tcipif_dbus_req; input [1 :0] bmu_tcipif_dbus_size; input bmu_tcipif_dbus_supv_mode; input [31:0] bmu_tcipif_dbus_wdata; input bmu_tcipif_dbus_write; input bmu_tcipif_ibus_acc_deny; input [31:0] bmu_tcipif_ibus_addr; input bmu_tcipif_ibus_req; input bmu_tcipif_ibus_write; input cp0_yy_be_v2; input [9 :0] cpu_clic_curid; input cpu_clic_int_exit; input cpurst_b; input forever_cpuclk; input forever_cpuclk_nogated; input had_tcipif_cmplt; input [31:0] had_tcipif_rdata; input iu_yy_xx_dbgon; input [63:0] pad_clic_int_cfg; input [63:0] pad_clic_int_vld; input [25:0] pad_ctim_calib; input pad_ctim_refclk; input pad_yy_gate_clk_en_b; input pad_yy_test_mode; output clic_cpu_int_hv; output [9 :0] clic_cpu_int_id; output [7 :0] clic_cpu_int_il; output [1 :0] clic_cpu_int_priv; output ctim_pad_int_vld; output pwrm_cpu_bus_peak_power_limit_en; output tcipif_bmu_dbus_acc_err; output [31:0] tcipif_bmu_dbus_data; output tcipif_bmu_dbus_data_vld; output tcipif_bmu_dbus_grnt; output tcipif_bmu_dbus_trans_cmplt; output tcipif_bmu_ibus_acc_err; output [31:0] tcipif_bmu_ibus_data; output tcipif_bmu_ibus_data_vld; output tcipif_bmu_ibus_grnt; output tcipif_bmu_ibus_trans_cmplt; output [15:0] tcipif_had_addr; output tcipif_had_sel; output [31:0] tcipif_had_wdata; output tcipif_had_write; wire bmu_tcipif_dbus_acc_deny; wire [31:0] bmu_tcipif_dbus_addr; wire bmu_tcipif_dbus_chk_fail; wire bmu_tcipif_dbus_req; wire [1 :0] bmu_tcipif_dbus_size; wire bmu_tcipif_dbus_supv_mode; wire [31:0] bmu_tcipif_dbus_wdata; wire bmu_tcipif_dbus_write; wire bmu_tcipif_ibus_acc_deny; wire [31:0] bmu_tcipif_ibus_addr; wire bmu_tcipif_ibus_req; wire bmu_tcipif_ibus_write; wire clic_cpu_int_hv; wire [9 :0] clic_cpu_int_id; wire [7 :0] clic_cpu_int_il; wire [1 :0] clic_cpu_int_priv; wire coretim_tcipif_cmplt; wire [31:0] coretim_tcipif_rdata; wire cp0_yy_be_v2; wire [9 :0] cpu_clic_curid; wire cpu_clic_int_exit; wire cpurst_b; wire ctim_pad_int_vld; wire forever_cpuclk; wire forever_cpuclk_nogated; wire had_img_tcipif_cmplt; wire [31:0] had_img_tcipif_rdata; wire had_tcipif_cmplt; wire [31:0] had_tcipif_rdata; wire iu_yy_xx_dbgon; wire [63:0] pad_clic_int_cfg; wire [63:0] pad_clic_int_vld; wire [25:0] pad_ctim_calib; wire pad_ctim_refclk; wire pad_yy_gate_clk_en_b; wire pad_yy_test_mode; wire pwrm_cpu_bus_peak_power_limit_en; wire tcipif_bmu_dbus_acc_err; wire [31:0] tcipif_bmu_dbus_data; wire tcipif_bmu_dbus_data_vld; wire tcipif_bmu_dbus_grnt; wire tcipif_bmu_dbus_trans_cmplt; wire tcipif_bmu_ibus_acc_err; wire [31:0] tcipif_bmu_ibus_data; wire tcipif_bmu_ibus_data_vld; wire tcipif_bmu_ibus_grnt; wire tcipif_bmu_ibus_trans_cmplt; wire tcipif_coretim_sel; wire [15:0] tcipif_had_addr; wire tcipif_had_img_sel; wire tcipif_had_sel; wire [31:0] tcipif_had_wdata; wire tcipif_had_write; wire tcipif_vic_sel; wire [1 :0] tcipif_vic_size; wire [15:0] tcipif_xx_dbus_addr; wire [31:0] tcipif_xx_dbus_wdata; wire tcipif_xx_dbus_write; wire vic_tcipif_cmplt; wire [31:0] vic_tcipif_rdata; cr_tcipif_behavior_bus x_cr_tcipif_dbus ( .bmu_tcipif_dbus_acc_deny (bmu_tcipif_dbus_acc_deny ), .bmu_tcipif_dbus_addr (bmu_tcipif_dbus_addr ), .bmu_tcipif_dbus_chk_fail (bmu_tcipif_dbus_chk_fail ), .bmu_tcipif_dbus_req (bmu_tcipif_dbus_req ), .bmu_tcipif_dbus_size (bmu_tcipif_dbus_size ), .bmu_tcipif_dbus_supv_mode (bmu_tcipif_dbus_supv_mode ), .bmu_tcipif_dbus_wdata (bmu_tcipif_dbus_wdata ), .bmu_tcipif_dbus_write (bmu_tcipif_dbus_write ), .coretim_tcipif_cmplt (coretim_tcipif_cmplt ), .coretim_tcipif_rdata (coretim_tcipif_rdata ), .cp0_yy_be_v2 (cp0_yy_be_v2 ), .cpurst_b (cpurst_b ), .forever_cpuclk (forever_cpuclk ), .had_img_tcipif_cmplt (had_img_tcipif_cmplt ), .had_img_tcipif_rdata (had_img_tcipif_rdata ), .iu_yy_xx_dbgon (iu_yy_xx_dbgon ), .pad_yy_gate_clk_en_b (pad_yy_gate_clk_en_b ), .pad_yy_test_mode (pad_yy_test_mode ), .tcipif_bmu_dbus_acc_err (tcipif_bmu_dbus_acc_err ), .tcipif_bmu_dbus_data (tcipif_bmu_dbus_data ), .tcipif_bmu_dbus_data_vld (tcipif_bmu_dbus_data_vld ), .tcipif_bmu_dbus_grnt (tcipif_bmu_dbus_grnt ), .tcipif_bmu_dbus_trans_cmplt (tcipif_bmu_dbus_trans_cmplt), .tcipif_coretim_sel (tcipif_coretim_sel ), .tcipif_had_img_sel (tcipif_had_img_sel ), .tcipif_vic_sel (tcipif_vic_sel ), .tcipif_vic_size (tcipif_vic_size ), .tcipif_xx_dbus_addr (tcipif_xx_dbus_addr ), .tcipif_xx_dbus_wdata (tcipif_xx_dbus_wdata ), .tcipif_xx_dbus_write (tcipif_xx_dbus_write ), .vic_tcipif_cmplt (vic_tcipif_cmplt ), .vic_tcipif_rdata (vic_tcipif_rdata ) ); cr_tcipif_dummy_bus x_cr_tcipif_ibus ( .bmu_tcipif_ibus_acc_deny (bmu_tcipif_ibus_acc_deny ), .bmu_tcipif_ibus_addr (bmu_tcipif_ibus_addr ), .bmu_tcipif_ibus_req (bmu_tcipif_ibus_req ), .bmu_tcipif_ibus_write (bmu_tcipif_ibus_write ), .cpurst_b (cpurst_b ), .forever_cpuclk (forever_cpuclk ), .pad_yy_gate_clk_en_b (pad_yy_gate_clk_en_b ), .pad_yy_test_mode (pad_yy_test_mode ), .tcipif_bmu_ibus_acc_err (tcipif_bmu_ibus_acc_err ), .tcipif_bmu_ibus_data (tcipif_bmu_ibus_data ), .tcipif_bmu_ibus_data_vld (tcipif_bmu_ibus_data_vld ), .tcipif_bmu_ibus_grnt (tcipif_bmu_ibus_grnt ), .tcipif_bmu_ibus_trans_cmplt (tcipif_bmu_ibus_trans_cmplt) ); cr_clic_top x_cr_clic_top ( .clic_pad_int_hv (clic_cpu_int_hv ), .clic_pad_int_id (clic_cpu_int_id ), .clic_pad_int_il (clic_cpu_int_il ), .clic_pad_int_priv (clic_cpu_int_priv ), .clic_tcipif_cmplt (vic_tcipif_cmplt ), .clic_tcipif_rdata (vic_tcipif_rdata ), .cpu_clic_curid (cpu_clic_curid ), .cpu_clic_int_exit (cpu_clic_int_exit ), .cpurst_b (cpurst_b ), .forever_cpuclk (forever_cpuclk ), .forever_cpuclk_nogated (forever_cpuclk_nogated), .pad_clic_int_cfg (pad_clic_int_cfg ), .pad_clic_int_vld (pad_clic_int_vld ), .pad_yy_gate_clk_en_b (pad_yy_gate_clk_en_b ), .pad_yy_test_mode (pad_yy_test_mode ), .tcipif_clic_addr (tcipif_xx_dbus_addr ), .tcipif_clic_sel (tcipif_vic_sel ), .tcipif_clic_size (tcipif_vic_size ), .tcipif_clic_wdata (tcipif_xx_dbus_wdata ), .tcipif_clic_write (tcipif_xx_dbus_write ) ); cr_pwrm_top_dummy x_cr_pwrm_top_dummy ( .pwrm_cpu_bus_peak_power_limit_en (pwrm_cpu_bus_peak_power_limit_en) ); cr_coretim_top x_cr_coretim_top ( .core_dbgon (iu_yy_xx_dbgon ), .coretim_tcipif_cmplt (coretim_tcipif_cmplt ), .coretim_tcipif_rdata (coretim_tcipif_rdata ), .cpurst_b (cpurst_b ), .ctim_pad_int_vld (ctim_pad_int_vld ), .forever_cpuclk (forever_cpuclk ), .forever_cpuclk_nogated (forever_cpuclk_nogated), .pad_ctim_calib (pad_ctim_calib ), .pad_ctim_refclk (pad_ctim_refclk ), .pad_yy_gate_clk_en_b (pad_yy_gate_clk_en_b ), .pad_yy_test_mode (pad_yy_test_mode ), .tcipif_coretim_addr (tcipif_xx_dbus_addr ), .tcipif_coretim_sel (tcipif_coretim_sel ), .tcipif_coretim_wdata (tcipif_xx_dbus_wdata ), .tcipif_coretim_write (tcipif_xx_dbus_write ) ); assign tcipif_had_sel = tcipif_had_img_sel; assign tcipif_had_addr[15:0] = tcipif_xx_dbus_addr[15:0]; assign tcipif_had_write = tcipif_xx_dbus_write; assign tcipif_had_wdata[31:0] = tcipif_xx_dbus_wdata[31:0]; assign had_img_tcipif_cmplt = had_tcipif_cmplt; assign had_img_tcipif_rdata[31:0] = had_tcipif_rdata[31:0]; endmodule module A186a0( A1868b, A17, A117, had_core_dbg_mode_req, hadrst_b, ifu_had_chg_flw_inst, ifu_had_fetch_expt_vld, ifu_had_inst_dbg_disable, ifu_had_match_pc, ifu_had_split_first, iu_had_expt_vld, iu_had_flush, iu_had_xx_mldst, iu_had_xx_retire, iu_had_xx_retire_normal, iu_yy_xx_dbgon, lsu_had_addr, lsu_had_addr_vld, lsu_had_ex_cmplt, lsu_had_st, A1867c, A14, A1868d ); input A117; input had_core_dbg_mode_req; input hadrst_b; input ifu_had_chg_flw_inst; input ifu_had_fetch_expt_vld; input ifu_had_inst_dbg_disable; input [31:0] ifu_had_match_pc; input ifu_had_split_first; input iu_had_expt_vld; input iu_had_flush; input iu_had_xx_mldst; input iu_had_xx_retire; input iu_had_xx_retire_normal; input iu_yy_xx_dbgon; input [31:0] lsu_had_addr; input lsu_had_addr_vld; input lsu_had_ex_cmplt; input lsu_had_st; input [31:0] A1867c; input [2 :0] A14; input [7 :0] A1868d; output A1868b; output A17; reg A1868c; reg A1869f; reg A3; reg A16; wire A1868b; wire A17; wire A1868a; wire A18; wire A18689; wire A117; wire A18688; wire A1a; wire A18687; wire A1b; wire A18686; wire A1c; wire had_core_dbg_mode_req; wire hadrst_b; wire ifu_had_chg_flw_inst; wire ifu_had_fetch_expt_vld; wire ifu_had_inst_dbg_disable; wire [31:0] ifu_had_match_pc; wire ifu_had_split_first; wire A18694; wire Ae; wire iu_had_expt_vld; wire iu_had_flush; wire iu_had_xx_mldst; wire iu_had_xx_retire; wire iu_had_xx_retire_normal; wire iu_yy_xx_dbgon; wire [31:0] lsu_had_addr; wire lsu_had_addr_vld; wire lsu_had_ex_cmplt; wire lsu_had_st; wire [31:0] A1867c; wire [2 :0] A14; wire [7 :0] A1868d; assign A1868a = |A14[2:0]; assign A18688 = ((lsu_had_addr[31:0] & {24'hFF_FFFF,A1868d[7:0]}) == A1867c[31:0]); assign A18687 = A18688; assign A1b = A18687 && lsu_had_addr_vld; assign A18686 = (A1b || A16) && iu_had_xx_retire; always @(posedge A117 or negedge hadrst_b) begin if (!hadrst_b) A16 <= 1'b0; else if (lsu_had_ex_cmplt || iu_had_flush) A16 <= 1'b0; else if (A1b) A16 <= 1'b1; else A16 <= A16; end assign A18694 = ((ifu_had_match_pc[31:0] & {24'hFF_FFFF, A1868d[7:0]} ) == A1867c[31:0] ); assign Ae = A18694 && A1868a && ifu_had_split_first && !had_core_dbg_mode_req; always @( A14[2:0] or ifu_had_chg_flw_inst or Ae or A18686 or lsu_had_st) begin A3 = 1'b0; A1869f = 1'b0; case (A14[2:0]) 3'b001: begin A3 = Ae; A1869f = A18686; end 3'b010: A3 = Ae; 3'b011: A1869f = A18686; 3'b100: A3 = Ae && ifu_had_chg_flw_inst; 3'b101: A1869f = A18686 && lsu_had_st; 3'b110: A1869f = A18686 && !lsu_had_st; default: begin A3 = 1'b0; A1869f = 1'b0; end endcase end assign A1c = A1868a && A1869f; assign A1868b = A3 && !ifu_had_fetch_expt_vld && !ifu_had_inst_dbg_disable && !iu_yy_xx_dbgon; assign A18 = iu_had_expt_vld; always @(posedge A117 or negedge hadrst_b) begin if(!hadrst_b) A1868c <= 1'b0; else if (A17 || A18) A1868c <= 1'b0; else if (!A1868c && A1c && iu_had_xx_mldst) A1868c <= 1'b1; else A1868c <= A1868c; end assign A1a = !A1868c && A1c && !iu_had_xx_mldst; assign A18689 = A1868c && !iu_had_xx_mldst && iu_had_xx_retire; assign A17 = (A1a || A18689) && !iu_yy_xx_dbgon && A1868a && iu_had_xx_retire_normal; endmodule module A15( A1868b, A17, A117, had_core_dbg_mode_req, hadrst_b, ifu_had_fetch_expt_vld, ifu_had_inst_dbg_disable, ifu_had_match_pc, ifu_had_split_first, iu_had_expt_vld, iu_had_flush, iu_had_xx_mldst, iu_had_xx_retire, iu_had_xx_retire_normal, iu_yy_xx_dbgon, lsu_had_addr, lsu_had_addr_vld, lsu_had_ex_cmplt, A1867c, A26 ); input A117; input had_core_dbg_mode_req; input hadrst_b; input ifu_had_fetch_expt_vld; input ifu_had_inst_dbg_disable; input [31:0] ifu_had_match_pc; input ifu_had_split_first; input iu_had_expt_vld; input iu_had_flush; input iu_had_xx_mldst; input iu_had_xx_retire; input iu_had_xx_retire_normal; input iu_yy_xx_dbgon; input [31:0] lsu_had_addr; input lsu_had_addr_vld; input lsu_had_ex_cmplt; input [31:0] A1867c; input A26; output A1868b; output A17; reg A1868c; reg A16; wire A1868b; wire A17; wire A1868a; wire A18; wire A18689; wire A117; wire A18688; wire A1a; wire A18687; wire A1b; wire A18686; wire A1c; wire had_core_dbg_mode_req; wire hadrst_b; wire ifu_had_fetch_expt_vld; wire ifu_had_inst_dbg_disable; wire [31:0] ifu_had_match_pc; wire ifu_had_split_first; wire A18682; wire A20; wire A18681; wire iu_had_expt_vld; wire iu_had_flush; wire iu_had_xx_mldst; wire iu_had_xx_retire; wire iu_had_xx_retire_normal; wire iu_yy_xx_dbgon; wire [31:0] lsu_had_addr; wire lsu_had_addr_vld; wire lsu_had_ex_cmplt; wire [31:0] A1867c; wire A26; assign A1868a = A26; assign A18688 = (lsu_had_addr[31:0] == A1867c[31:0]); assign A18687 = A18688; assign A1b = A18687 && lsu_had_addr_vld; assign A18686 = (A1b || A16) && iu_had_xx_retire; always @(posedge A117 or negedge hadrst_b) begin if (!hadrst_b) A16 <= 1'b0; else if (lsu_had_ex_cmplt || iu_had_flush) A16 <= 1'b0; else if (A1b) A16 <= 1'b1; else A16 <= A16; end assign A18682 = (ifu_had_match_pc[31:0] == A1867c[31:0]); assign A20 = A18682 && !ifu_had_fetch_expt_vld && !ifu_had_inst_dbg_disable && ifu_had_split_first && !iu_yy_xx_dbgon && !had_core_dbg_mode_req; assign A18681 = A1868a ? A20 : 1'b0; assign A1c = A1868a ? A18686 : 1'b0; assign A1868b = A18681; assign A18 = iu_had_expt_vld; always @(posedge A117 or negedge hadrst_b) begin if(!hadrst_b) A1868c <= 1'b0; else if (A17 || A18) A1868c <= 1'b0; else if (!A1868c && A1c && iu_had_xx_mldst) A1868c <= 1'b1; else A1868c <= A1868c; end assign A1a = !A1868c && A1c && !iu_had_xx_mldst; assign A18689 = A1868c && !iu_had_xx_mldst && iu_had_xx_retire; assign A17 = (A1a || A18689) && !iu_yy_xx_dbgon && iu_had_xx_retire_normal && A1868a; endmodule module A1867b( A110, A18591, A111, A18590, A112, A1858f, A113, A1858e, A114, A1858d, A117, A1858a, A118, A18589, A119, A18588, A11a, had_ifu_inst_bkpt_dbq_req, had_ifu_inst_bkpt_dbqexp_req, had_iu_bkpt_trace_en, had_iu_dr_set_req, had_iu_mbkpt_fsm_index_mbee, had_iu_mem_bkpt_exp_req, had_iu_mem_bkpt_mask, had_iu_mem_bkpt_req, had_iu_trace_req, had_iu_trace_req_for_dbg_disable, had_iu_xx_jdbreq, had_yy_xx_dbg, had_yy_xx_dp_index_mbee, had_yy_xx_exit_dbg, hadrst_b, iu_had_adr_dbg_ack, iu_had_chgflw_dst_pc, iu_had_chgflw_vld, iu_had_data_bkpt_occur_vld, iu_had_dbg_disable_for_tee, iu_had_dr_dbg_ack, iu_had_inst_bkpt_occur_vld, iu_had_trace_occur_vld, iu_had_xx_bkpt_inst, iu_yy_xx_dbgon, A18563, A1855e, A1855c, A18556, A14c, A18555, A14d, A18554, A14e, A18553, A161, A162, A1853f ); input A110; input A18591; input A111; input A18590; input A112; input A1858f; input A113; input A1858e; input A114; input A1858d; input A117; input hadrst_b; input iu_had_adr_dbg_ack; input [31:0] iu_had_chgflw_dst_pc; input iu_had_chgflw_vld; input iu_had_data_bkpt_occur_vld; input iu_had_dbg_disable_for_tee; input iu_had_dr_dbg_ack; input iu_had_inst_bkpt_occur_vld; input iu_had_trace_occur_vld; input iu_had_xx_bkpt_inst; input iu_yy_xx_dbgon; input A18563; input A1855e; input A1855c; input A18556; input A14c; input A18555; input A14d; input A18554; input A14e; input [8 :0] A18553; input A161; input A162; input A1853f; output A1858a; output A118; output A18589; output A119; output A18588; output A11a; output had_ifu_inst_bkpt_dbq_req; output had_ifu_inst_bkpt_dbqexp_req; output had_iu_bkpt_trace_en; output had_iu_dr_set_req; output had_iu_mbkpt_fsm_index_mbee; output had_iu_mem_bkpt_exp_req; output had_iu_mem_bkpt_mask; output had_iu_mem_bkpt_req; output had_iu_trace_req; output had_iu_trace_req_for_dbg_disable; output had_iu_xx_jdbreq; output had_yy_xx_dbg; output had_yy_xx_dp_index_mbee; output had_yy_xx_exit_dbg; reg A27; wire A1867a; wire A110; wire A18591; wire A111; wire A18590; wire A112; wire A1858f; wire A113; wire A1858e; wire A114; wire A1858d; wire A117; wire A1858a; wire A118; wire A18589; wire A119; wire A18588; wire A11a; wire A18671; wire A31; wire had_ifu_inst_bkpt_dbq_req; wire had_ifu_inst_bkpt_dbqexp_req; wire had_iu_bkpt_trace_en; wire had_iu_dr_set_req; wire had_iu_mbkpt_fsm_index_mbee; wire had_iu_mem_bkpt_exp_req; wire had_iu_mem_bkpt_mask; wire had_iu_mem_bkpt_req; wire had_iu_trace_req; wire had_iu_trace_req_for_dbg_disable; wire had_iu_xx_jdbreq; wire had_yy_xx_dbg; wire had_yy_xx_dp_index_mbee; wire had_yy_xx_exit_dbg; wire hadrst_b; wire iu_had_adr_dbg_ack; wire iu_had_data_bkpt_occur_vld; wire iu_had_dbg_disable_for_tee; wire iu_had_dr_dbg_ack; wire iu_had_inst_bkpt_occur_vld; wire iu_had_trace_occur_vld; wire iu_had_xx_bkpt_inst; wire iu_yy_xx_dbgon; wire A18563; wire A18664; wire A3e; wire A1855e; wire A1855c; wire A18556; wire A14c; wire A18555; wire A14d; wire A18554; wire A14e; wire [8 :0] A18553; wire A161; wire A162; wire A1853f; wire A1865d; assign A1865d = A162; assign A18664 = (A18591 && !A18553[0]) || (A18590 && !A18553[1]) || (A1858f && !A18553[2]) || (A1858e && !A18553[3]) || (A1858d && !A18553[4]); assign A3e = (A18591 && A18553[0]) || (A18590 && A18553[1]) || (A1858f && A18553[2]) || (A1858e && A18553[3]) || (A1858d && A18553[4]); assign had_ifu_inst_bkpt_dbq_req = ((A110 && !A18553[0]) || (A111 && !A18553[1]) || (A112 && !A18553[2]) || (A113 && !A18553[3]) || (A114 && !A18553[4]) ) && !A14e && !iu_had_dbg_disable_for_tee; assign had_ifu_inst_bkpt_dbqexp_req = ((A110 && A18553[0]) || (A111 && A18553[1]) || (A112 && A18553[2]) || (A113 && A18553[3]) || (A114 && A18553[4]) ) && !A14e && !iu_had_dbg_disable_for_tee; assign A18671 = A14c; assign A1867a = A18556; assign had_iu_dr_set_req = A18671 && !iu_yy_xx_dbgon; assign had_iu_trace_req = A1865d && !iu_yy_xx_dbgon; assign had_iu_mem_bkpt_req = A18664 && !iu_yy_xx_dbgon; assign had_iu_mem_bkpt_mask = (A18664 || A3e) && !iu_yy_xx_dbgon; assign had_iu_mem_bkpt_exp_req = 1'b0; assign had_iu_xx_jdbreq = (A1855e || A1867a) && !iu_yy_xx_dbgon; assign had_iu_trace_req_for_dbg_disable = A1853f && !iu_yy_xx_dbgon; assign had_iu_bkpt_trace_en = A1855c || A161; assign had_yy_xx_dbg = A18671 || A1855e || A1867a; assign A118 = iu_had_adr_dbg_ack; assign A18589 = iu_had_dr_dbg_ack; assign A119 = iu_had_data_bkpt_occur_vld || iu_had_inst_bkpt_occur_vld; assign A18588 = iu_had_xx_bkpt_inst; assign A11a = iu_had_trace_occur_vld; assign A31 = (A14d && A18554) && A18563 && A18555 && iu_yy_xx_dbgon; always @(posedge A117 or negedge hadrst_b) begin if (!hadrst_b) A27 <= 1'b0; else A27 <= A31; end assign A1858a = A27; assign had_yy_xx_exit_dbg = A27; assign had_iu_mbkpt_fsm_index_mbee = 1'b0; assign had_yy_xx_dp_index_mbee = 1'b0; endmodule module A45( A117, A18587, A11b, A18586, A11c, hadrst_b, iu_had_xx_retire, A18563, A14f, A18552, A153 ); input A117; input hadrst_b; input iu_had_xx_retire; input A18563; input A14f; input A18552; input A153; output A18587; output [31:0] A11b; output A18586; output A11c; reg [3 :0] A1865c; reg [3 :0] A46; wire A1865b; wire A47; wire A1865a; wire A117; wire A18659; wire A49; wire A18658; wire A18587; wire [31:0] A11b; wire A18586; wire A11c; wire hadrst_b; wire iu_had_xx_retire; wire A18563; wire A14f; wire A18552; wire A153; wire A4f; wire A18652; parameter A50 = 4'h0; parameter A18651 = 4'h1; parameter A51 = 4'h2; parameter A18650 = 4'h3; parameter A52 = 4'h4; parameter A1864f = 4'h5; parameter A53 = 4'h6; parameter A1864e = 4'h7; parameter A54 = 4'h8; always @(posedge A117 or negedge hadrst_b) begin if (!hadrst_b) A1865c[3:0] <= A50; else A1865c[3:0] <= A46[3:0]; end always @( * ) begin case(A1865c[3:0]) A50 : begin if (A153) A46[3:0] = A18651; else A46[3:0] = A50; end A18651 : begin if (A47) A46[3:0] = A51; else A46[3:0] = A18651; end A51 : begin A46[3:0] = A18650; end A18650 : begin if (A49) A46[3:0] = A52; else if (A47) A46[3:0] = A51; else if (!A153) A46[3:0] = A50; else A46[3:0] = A18650; end A52 : begin A46[3:0] = A1864f; end A1864f : begin if (A18659) A46[3:0] = A53; else A46[3:0] = A1864f; end A53 : begin A46[3:0] = A1864e; end A1864e : begin if (A4f) A46[3:0] = A54; else A46[3:0] = A1864e; end A54 : begin A46[3:0] = A18650; end default : begin A46[3:0] = A50; end endcase end assign A18659 = iu_had_xx_retire; assign A4f = iu_had_xx_retire; assign A47 = A18563 && A14f; assign A49 = A18563 && A18552; assign A1865a = A1865c[3:0] == A51; assign A18658 = A1865c[3:0] == A52; assign A18652 = A1865c[3:0] == A53; assign A1865b = A1865c[3:0] == A54; assign A11c = A1865a || A18658 || A18652 || A1865b; assign A11b[31:0] = A1865a ? 32'h00008093 : A18658 ? 32'h00010113 : A18652 ? 32'h0020a023 : 32'h00408093; assign A18586 = A1865a || A18658 || A18652 || A1865b; assign A18587 = (A1865a || A18658) ? 1'b1 : 1'b0; endmodule module A1864d( A117, forever_cpuclk_nogated, had_pad_wakeup_req_b, hadrst_b, A13c, A18565, A13d, A18564, A13e, A18563, A144, A1855d, A150, A18551, A151, A18550, A1854e, tclk, trst_b ); input A117; input forever_cpuclk_nogated; input hadrst_b; input A144; input A1855d; input [31:0] A150; input A18551; input A151; input A18550; input tclk; input trst_b; output had_pad_wakeup_req_b; output A13c; output A18565; output A13d; output A18564; output [31:0] A13e; output A18563; output A1854e; reg A55; reg [31:0] A1864c; reg [31:0] A56; reg [3 :0] A1864b; reg [4 :0] A57; reg [3 :0] A1864a; reg A58; reg A18649; reg [1 :0] A59; reg A18648; reg [6 :0] A5a; reg A1854e; reg A5b; reg A18646; wire A117; wire forever_cpuclk_nogated; wire had_pad_wakeup_req_b; wire hadrst_b; wire A13c; wire A18565; wire A13d; wire A18564; wire [31:0] A13e; wire A18563; wire A144; wire A1855d; wire [31:0] A150; wire A1863f; wire A63; wire A1863e; wire A64; wire A1863d; wire A65; wire A1863c; wire A66; wire A1863b; wire A67; wire A1863a; wire A68; wire A18639; wire A69; wire A18638; wire A6a; wire A18637; wire A6b; wire A18636; wire A6c; wire A18635; wire A6d; wire tclk; wire A6e; wire A18633; wire trst_b; parameter A18632 = 4'b0000; parameter A70 = 4'b0001; parameter A18631 = 4'b0011; parameter A71 = 4'b0010; parameter A18630 = 4'b0110; parameter A72 = 4'b0111; parameter A1862f = 4'b0101; parameter A73 = 4'b0100; parameter A1862e = 4'b1100; always @(posedge tclk or negedge trst_b) begin if (!trst_b) A1864b[3:0] <= A18632; else if (A1863c && A18633) A1864b[3:0] <= A18632; else A1864b[3:0] <= A1864a[3:0]; end always @(posedge tclk or negedge trst_b) begin if (!trst_b) A5a[6:0] <= 7'd80; else begin if (!A18633) A5a[6:0] <= 7'd80; else if (A5a[6:0] != 7'd0) A5a[6:0] <= A5a[6:0] - 7'd1; else A5a[6:0] <= 7'd80; end end assign A1863c = (A5a[6:0] == 7'd00); A10a A74 ( .A18595 (A117 ), .A10d (tclk ), .A18594 (hadrst_b ), .A10e (trst_b ), .A18593 (A1863c ), .A10f (A66) ); assign A13d = A66; always @( * ) begin case (A1864b[3:0]) A18632 : begin if (A144) begin if (!A18633) A1864a[3:0] = A18631; else A1864a[3:0] = A70; end else A1864a[3:0] = A18632; end A70 : begin if (!A18633) A1864a[3:0] = A18631; else A1864a[3:0] = A70; end A18631 : begin A1864a[3:0] = A71; end A71 : begin if (A18648 == 1'b0) A1864a[3:0] = A18630; else A1864a[3:0] = A71; end A18630 : begin if (A18649) A1864a[3:0] = A1862f; else A1864a[3:0] = A72; end A1862f : begin A1864a[3:0] = A72; end A72 : begin if (A57[4:0] == 5'b0) A1864a[3:0] = A73; else A1864a[3:0] = A72; end A73 : begin A1864a[3:0] = A1862e; end A1862e : begin A1864a[3:0] = A70; end default : begin A1864a[3:0] = A18632; end endcase end assign A63 = A1864b[3:0] == A18631; assign A6a = A1864b[3:0] == A18630; assign A18637 = A1864b[3:0] == A1862e; assign A69 = A1864b[3:0] == A18631; assign A18639 = A1864b[3:0] == A72; assign A1863e = A1864b[3:0] == A73; assign A18638 = A1864b[3:0] == A1862f; assign A1863a = A1863e; assign A68 = A18638; assign A67 = A65 && A18639; assign A1863b = A1863d && A18639; assign A6c = A65 && A18637 && (!A58); assign A6b = A1863d && !A18649 && A18637 && (!A58); assign A1863f = A1863d && A18649 && A6a; A10a A1862d ( .A18595 (A117 ), .A10d (tclk ), .A18594 (hadrst_b ), .A10e (trst_b ), .A18593 (A6c ), .A10f (A18635) ); A10a A75 ( .A18595 (A117 ), .A10d (tclk ), .A18594 (hadrst_b ), .A10e (trst_b ), .A18593 (A6b ), .A10f (A18636) ); assign A18564 = A18635; assign A18563 = A18636; assign had_pad_wakeup_req_b = (A1864b[3:0] == A18632) || (A1864b[3:0] == A70); always @(posedge tclk) begin if (A63) A18649 <= A1855d; end always @(posedge tclk) begin if (A69) A18648 <= 1'b1; else if (A1864b[3:0] == A71) A18648 <= 1'b0; else A18648 <= A18648; end always @(posedge tclk) begin if (A1864b[3:0] == A71) A59[1:0] <= {A1855d, A59[1]}; else A59[1:0] <= A59[1:0]; end assign A64 = A59[1:0] == 2'b01; assign A65 = A59[1:0] == 2'b10; assign A1863d = A59[1:0] == 2'b11; always @(posedge tclk) begin if (A1864b[3:0] == A18630) begin if (A1863d || A64) A57[4:0] <= 5'b11111; else A57[4:0] <= 5'b00111; end else if (A18639) A57[4:0] <= A57[4:0] - 5'b1; end always @(posedge tclk or negedge trst_b) begin if (!trst_b) A18646 <= 1'b0; else if (A1863c) A18646 <= 1'b0; else if (A6a && A18649) A18646 <= 1'b1; else if (A18637) A18646 <= 1'b0; else A18646 <= A18646; end always @(posedge tclk) begin if (A69) A58 <= 1'b1; else if ((A1863d || A65) && A18639) A58 <= A58 ^ A1855d; else if (A1863e) A58 <= A58 ^ A1855d; else A58 <= A58; end assign A6d = !(A1864b[3:0] == A18632); always @(posedge forever_cpuclk_nogated or negedge hadrst_b) begin if (!hadrst_b) A1854e <= 1'b0; else if (A6d) A1854e <= 1'b1; else A1854e <= A1854e; end always @( * ) begin A56[31:0] = 32'b0; if (A67) A56[7:0] = {A6e, A1864c[7:1]}; else if (A1863f) A56[31:0] = A150[31:0]; else if (A1863b) A56[31:0] = {A6e, A1864c[31:1]}; else A56[31:0] = A1864c[31:0]; end assign A13e[31:0] = A1864c[31:0]; always @(posedge tclk) begin A1864c[31:0] <= A56[31:0]; end always @(negedge tclk or negedge trst_b) begin if (!trst_b) A5b <= 1'b1; else if (A68) A5b <= 1'b0; else if (A1863b && A18649) A5b <= A1864c[0]; else if (A1863a && A18649) A5b <= A55; else A5b <= 1'b1; end always @(posedge tclk) begin if (A1863f) A55 <= 1'b1; else if (A1863b && A18649) A55 <= A55 ^ A1864c[0]; else A55 <= A55; end assign A18565 = A18646; assign A13c = A5b; assign A18633 = A1855d; assign A6e = A1855d; endmodule module A1862c( had_pad_jdb_ack_b, had_pad_jdb_pm, had_pad_jtg_tap_on, had_pad_jtg_tms_o, had_pad_jtg_tms_oe, iu_yy_xx_dbgon, A13c, A18565, pad_had_jdb_req_b, pad_had_jtg_tap_en, pad_had_jtg_tms_i, A1855e, A144, A1855d, A152, tclk, trst_b ); input iu_yy_xx_dbgon; input A13c; input A18565; input pad_had_jdb_req_b; input pad_had_jtg_tap_en; input pad_had_jtg_tms_i; input [1:0] A152; input tclk; input trst_b; output had_pad_jdb_ack_b; output [1:0] had_pad_jdb_pm; output had_pad_jtg_tap_on; output had_pad_jtg_tms_o; output had_pad_jtg_tms_oe; output A1855e; output A144; output A1855d; reg had_pad_jdb_ack_b; reg A1862b; wire [1:0] had_pad_jdb_pm; wire had_pad_jtg_tap_on; wire had_pad_jtg_tms_o; wire had_pad_jtg_tms_oe; wire iu_yy_xx_dbgon; wire A18628; wire A13c; wire A18565; wire pad_had_jtg_tap_en; wire pad_had_jtg_tms_i; wire A1855e; wire A144; wire A1855d; wire [1:0] A152; wire tclk; wire trst_b; assign A18628 = 1'b0; assign A1855e = 1'b0; assign A144 = A18628 || pad_had_jtg_tap_en; assign had_pad_jdb_pm[1:0] = A152[1:0]; always @(posedge tclk or negedge trst_b) begin if (!trst_b) had_pad_jdb_ack_b <= 1'b1; else if (A1862b) had_pad_jdb_ack_b <= 1'b1; else if (iu_yy_xx_dbgon) had_pad_jdb_ack_b <= 1'b0; else had_pad_jdb_ack_b <= had_pad_jdb_ack_b; end always @(posedge tclk or negedge trst_b) begin if (!trst_b) A1862b <= 1'b0; else if (!had_pad_jdb_ack_b) A1862b <= 1'b1; else if (!iu_yy_xx_dbgon) A1862b <= 1'b0; else A1862b <= A1862b; end assign had_pad_jtg_tap_on = A144; assign A1855d = pad_had_jtg_tms_i; assign had_pad_jtg_tms_o = A13c; assign had_pad_jtg_tms_oe = A18565; endmodule module A7f( cp0_had_cpuid_idx0, cp0_had_int_exit, cp0_had_lpmd_b, cp0_had_mcause_data, A117, A1858a, A118, A18589, A119, A18588, A11a, A18587, A11b, A18586, A11c, had_core_dbg_mode_req, had_idu_wbbr_data, had_idu_wbbr_vld, had_ifu_ir, had_ifu_ir_vld, had_iu_force_dbg_en, had_iu_int_vld, had_iu_pc, had_iu_rte_pc_sel, had_iu_xx_fdb, had_tcipif_cmplt, had_tcipif_rdata, hadrst_b, iu_had_fast_retire_acc_err_pc_update, iu_had_fast_retire_acc_err_pc_val, iu_had_int_ack, iu_had_retire_with_had_int, iu_had_xx_data, iu_had_xx_data_vld, iu_had_xx_dbg_ack, iu_had_xx_retire_pc, iu_yy_xx_dbgon, A13d, A18564, A13e, A18563, A145, A1855c, A146, A1855b, A147, A1855a, A148, A18559, A149, A18558, A14a, A18557, A14b, A18556, A14c, A18555, A14d, A18554, A14e, A18553, A14f, A18552, A150, A18551, A151, A18550, A152, A161, A153, tcipif_had_addr, tcipif_had_sel, tcipif_had_wdata, tcipif_had_write ); input [31:0] cp0_had_cpuid_idx0; input cp0_had_int_exit; input [1 :0] cp0_had_lpmd_b; input [31:0] cp0_had_mcause_data; input A117; input A1858a; input A118; input A18589; input A119; input A18588; input A11a; input A18587; input [31:0] A11b; input A18586; input A11c; input hadrst_b; input iu_had_fast_retire_acc_err_pc_update; input [30:0] iu_had_fast_retire_acc_err_pc_val; input iu_had_int_ack; input iu_had_retire_with_had_int; input [31:0] iu_had_xx_data; input iu_had_xx_data_vld; input iu_had_xx_dbg_ack; input [31:0] iu_had_xx_retire_pc; input iu_yy_xx_dbgon; input A13d; input A18564; input [31:0] A13e; input A18563; input [15:0] tcipif_had_addr; input tcipif_had_sel; input [31:0] tcipif_had_wdata; input tcipif_had_write; output had_core_dbg_mode_req; output [31:0] had_idu_wbbr_data; output had_idu_wbbr_vld; output [31:0] had_ifu_ir; output had_ifu_ir_vld; output had_iu_force_dbg_en; output had_iu_int_vld; output [30:0] had_iu_pc; output had_iu_rte_pc_sel; output had_iu_xx_fdb; output had_tcipif_cmplt; output [31:0] had_tcipif_rdata; output [31:0] A145; output A1855c; output [2 :0] A146; output [7 :0] A1855b; output [31:0] A147; output [2 :0] A1855a; output [7 :0] A148; output [31:0] A18559; output A149; output [31:0] A18558; output A14a; output [31:0] A18557; output A14b; output A18556; output A14c; output A18555; output A14d; output A18554; output A14e; output [8 :0] A18553; output A14f; output A18552; output [31:0] A150; output A18551; output A151; output A18550; output [1 :0] A152; output A161; output A153; reg A18622; reg [31:0] A80; reg [31:0] A18621; reg [31:0] A81; reg [31:0] A18620; reg [31:0] A82; reg [7 :0] A1861f; reg [7 :0] A83; reg [1 :0] A1861e; reg A84; reg A1861d; reg A85; reg [7 :0] A1861c; reg [7 :0] A86; reg A1861b; reg [1 :0] A87; reg A1861a; reg A88; reg [2 :0] A18619; reg [2 :0] A89; reg A18618; reg A8a; reg A18617; reg A8b; reg A18616; reg A8c; reg A18615; reg [30:0] A8d; reg A18614; reg [31:0] A8e; reg A18613; reg A8f; reg [31:0] A18612; wire A90; wire A18611; wire A91; wire A18610; wire A92; wire [31:0] A1860f; wire [31:0] A93; wire [31:0] A1860e; wire [31:0] A94; wire A1860d; wire A95; wire [7 :0] A1860c; wire [7 :0] A96; wire [7 :0] A1860b; wire [7 :0] A97; wire [7 :0] A1860a; wire [7 :0] A98; wire [7 :0] A18609; wire A99; wire A18608; wire A9a; wire A18607; wire A9b; wire A18606; wire [1 :0] A9c; wire A18605; wire [31:0] cp0_had_cpuid_idx0; wire [1 :0] cp0_had_lpmd_b; wire [31:0] cp0_had_mcause_data; wire A18603; wire A117; wire [15:0] A18602; wire Aa0; wire A1858a; wire A118; wire A18589; wire A119; wire A18588; wire A11a; wire [31:0] A185fe; wire [31:0] Aa4; wire [31:0] A185fd; wire [31:0] Aa5; wire [31:0] A185fc; wire Aa6; wire A18587; wire [31:0] A11b; wire A18586; wire A11c; wire [31:0] A185f9; wire [31:0] Aa9; wire A185f8; wire [31:0] Aaa; wire A185f7; wire [31:0] Aab; wire A185f6; wire Aac; wire A185f5; wire Aad; wire A185f4; wire Aae; wire A185f3; wire Aaf; wire A185f2; wire Ab0; wire A185f1; wire Ab1; wire A185f0; wire Ab2; wire A185ef; wire Ab3; wire A185ee; wire Ab4; wire A185ed; wire Ab5; wire A185ec; wire Ab6; wire A185eb; wire Ab7; wire A185ea; wire Ab8; wire A185e9; wire Ab9; wire A185e8; wire Aba; wire A185e7; wire Abb; wire A185e6; wire Abc; wire A185e5; wire Abd; wire A185e4; wire Abe; wire A185e3; wire Abf; wire A185e2; wire Ac0; wire A185e1; wire Ac1; wire A185e0; wire Ac2; wire A185df; wire Ac3; wire A185de; wire Ac4; wire A185dd; wire Ac5; wire A185dc; wire Ac6; wire A185db; wire Ac7; wire A185da; wire Ac8; wire A185d9; wire Ac9; wire A185d8; wire Aca; wire A185d7; wire Acb; wire A185d6; wire Acc; wire A185d5; wire Acd; wire A185d4; wire Ace; wire A185d3; wire Acf; wire A185d2; wire Ad0; wire A185d1; wire Ad1; wire A185d0; wire Ad2; wire A185cf; wire Ad3; wire A185ce; wire Ad4; wire A185cd; wire [4 :0] Ad5; wire A185cc; wire Ad6; wire A185cb; wire Ad7; wire A185ca; wire Ad8; wire A185c9; wire had_core_dbg_mode_req; wire [31:0] had_idu_wbbr_data; wire had_idu_wbbr_vld; wire [31:0] had_ifu_ir; wire had_ifu_ir_vld; wire had_iu_force_dbg_en; wire had_iu_int_vld; wire [30:0] had_iu_pc; wire had_iu_rte_pc_sel; wire had_iu_xx_fdb; wire had_tcipif_cmplt; wire [31:0] had_tcipif_rdata; wire hadrst_b; wire A185c2; wire Ae0; wire [6 :0] A185c1; wire [2 :0] Ae1; wire [3 :0] A185c0; wire Ae2; wire A185bf; wire Ae3; wire A185be; wire Ae4; wire A185bd; wire [31:0] Ae5; wire A185bc; wire [31:0] Ae6; wire A185bb; wire [15:0] Ae7; wire [31:0] A185ba; wire iu_had_fast_retire_acc_err_pc_update; wire [30:0] iu_had_fast_retire_acc_err_pc_val; wire iu_had_int_ack; wire iu_had_retire_with_had_int; wire [31:0] iu_had_xx_data; wire iu_had_xx_data_vld; wire iu_had_xx_dbg_ack; wire [31:0] iu_had_xx_retire_pc; wire iu_yy_xx_dbgon; wire A185b5; wire Aed; wire A13d; wire A18564; wire [31:0] A13e; wire A18563; wire A185b2; wire [31:0] Af0; wire [3 :0] A185b1; wire [31:0] Af1; wire [31:0] A185b0; wire Af2; wire [1 :0] A185af; wire Af3; wire A185ae; wire [31:0] Af4; wire [31:0] A185ad; wire Af5; wire [31:0] A145; wire A1855c; wire [2 :0] A146; wire [7 :0] A1855b; wire [31:0] A147; wire [2 :0] A1855a; wire [7 :0] A148; wire [31:0] A18559; wire A149; wire [31:0] A18558; wire A14a; wire [31:0] A18557; wire A14b; wire A18556; wire A14c; wire A18555; wire A14d; wire A18554; wire A14e; wire [8 :0] A18553; wire A14f; wire A18552; wire [31:0] A150; wire A18551; wire A151; wire A18550; wire [1 :0] A152; wire A161; wire A153; wire [31:0] A104; wire A1859d; wire A105; wire A1859c; wire A106; wire A1859b; wire [15:0] tcipif_had_addr; wire tcipif_had_sel; wire [31:0] tcipif_had_wdata; wire A18599; wire A109; wire A18598; always @(posedge A117 or negedge hadrst_b) begin if (!hadrst_b) A1861c[7:0] <= 8'h82; else if (A13d) A1861c[7:0] <= 8'h82; else if (A18564) A1861c[7:0] <= A13e[7:0]; else A1861c[7:0] <= A1861c[7:0]; end assign A185c9 = A1861c[7]; assign Aac = A1861c[6]; assign A185f6 = A1861c[5]; assign A109 = 1'b0; assign Ad5[4:0] = A109 ? tcipif_had_addr[6:2] : A1861c[4:0]; assign A18605 = A18563 && A185e3; always @(posedge A117 or negedge hadrst_b) begin if (!hadrst_b) A1861e[1:0] <= 2'b0; else if (A13d) A1861e[1:0] <= 2'b0; else if (A18605) A1861e[1:0] <= A13e[1:0]; else A1861e[1:0] <= A1861e[1:0]; end assign A9c[1:0] = {1'b0, A1861e[0]}; assign A18608 = A9c[1:0] == 2'b0; assign A9a = tcipif_had_addr[11:7] == 5'b0; assign A99 = A109 ? A9a : A18608; assign A9b = A9c[1:0] == 2'b1; assign A18606 = tcipif_had_addr[11:7] == 5'b1; assign A18607 = A109 ? A18606 : A9b; assign A185e3 = (Ad5[4:0] == 5'b11110); assign A185d6 = (Ad5[4:0] == 5'b00010) && A99; assign A185cb = 1'b0; assign A185e2 = (Ad5[4:0] == 5'b01100) && A99; assign A185d7 = (Ad5[4:0] == 5'b01110) && A99; assign A185ca = (Ad5[4:0] == 5'b10001) && A99; assign A185d5 = (Ad5[4:0] == 5'b10100) && A99; assign Ac0 = (Ad5[4:0] == 5'b10101) && A99; assign Ac2 = (Ad5[4:0] == 5'b11000) && A99; assign Ac6 = (Ad5[4:0] == 5'b11001) && A99; assign A185cc = (Ad5[4:0] == 5'b11111) && A99; assign Ad4 = (Ad5[4:0] == 5'b10010) && A99; assign Ad2 = (Ad5[4:0] == 5'b10011) && A99; assign A185d9 = (Ad5[4:0] == 5'b01101) && A99; assign A185d8 = 1'b0; assign Acd = 1'b0; assign Ace = 1'b0; assign A185f5 = (Ad5[4:0] == 5'b00111) && A99; assign A185ec = (Ad5[4:0] == 5'b01001) && A99; assign A185f4 = (Ad5[4:0] == 5'b01000) && A99; assign A185eb = (Ad5[4:0] == 5'b01010) && A99; assign A185f3 = (Ad5[4:0] == 5'b00000) && A18607; assign A185f2 = (Ad5[4:0] == 5'b00010) && A18607; assign A185f1 = (Ad5[4:0] == 5'b00100) && A18607; assign A185ea = 1'b0; assign A185e9 = 1'b0; assign A185e8 = 1'b0; assign A185f0 = 1'b0; assign A185ef = 1'b0; assign A185ee = 1'b0; assign A185ed = 1'b0; assign A185e7 = 1'b0; assign A185e6 = 1'b0; assign A185e5 = 1'b0; assign A185e4 = 1'b0; assign Ac1 = 1'b0; assign Ac4 = 1'b0; assign Ac3 = 1'b0; assign Ad0 = 1'b0; assign Acf = 1'b0; assign Ad1 = 1'b0; assign Ac5 = 1'b0; assign Ad3 = 1'b0; assign A185da = 1'b0; assign A1859b = 1'b0; assign Aa6 = A18563; assign A104[31:0] = A109 ? tcipif_had_wdata[31:0] : A13e[31:0]; assign A185ba[31:28] = 4'b0001; assign A185ba[27:26] = cp0_had_cpuid_idx0[27:26]; assign A185ba[25:18] = 8'b0; assign A185ba[17] = 1'b0; assign A185ba[16] = 1'b0; assign A185ba[15:12] = 4'd5; assign A185ba[11:8] = 4'd11; assign A185ba[7:4] = 4'b0011; assign A185ba[3:0] = 4'b0001; assign A90 = Aa6 && A185f5; always @(posedge A117) begin if (A90) A80[31:0] <= A104[31:0]; else A80[31:0] <= A80[31:0]; end assign A1860d = Aa6 && A185ec; always @(posedge A117 or negedge hadrst_b) begin if (!hadrst_b) A1861f[7:0] <= 8'b0; else if (A1860d) A1861f[7:0] <= A104[7:0]; else A1861f[7:0] <= A1861f[7:0]; end assign A18611 = Aa6 && A185f4; always @(posedge A117) begin if (A18611) A18621[31:0] <= A104[31:0]; else A18621[31:0] <= A18621[31:0]; end assign A95 = Aa6 && A185eb; always @(posedge A117 or negedge hadrst_b) begin if (!hadrst_b) A83[7:0] <= 8'b0; else if (A95) A83[7:0] <= A104[7:0]; else A83[7:0] <= A83[7:0]; end assign A18598 = A18563 && (A185ca || Ac2 || Ac6); always @(posedge A117) begin if (A18598) A18612[31:0] <= A13e[31:0]; else if (iu_had_xx_data_vld) A18612[31:0] <= iu_had_xx_data[31:0]; else A18612[31:0] <= A18612[31:0]; end assign Aed = A18563 && iu_yy_xx_dbgon; assign A18599 = A1859b && !iu_had_retire_with_had_int; assign Af5 = ((Aed && A18603) || A18599) && Ad4; always @(posedge A117) begin if (iu_had_int_ack) begin A87[1:0] <= cp0_had_mcause_data[29:28]; A86[7:0] <= cp0_had_mcause_data[23:16]; A1861b <= cp0_had_mcause_data[27]; A1861a <= cp0_had_mcause_data[26]; end else if (Af5) begin A87[1:0] <= A104[29:28]; A86[7:0] <= A104[23:16]; A1861b <= A104[27]; A1861a <= A104[26]; end end assign A185ad[31:0] = {1'b0,1'b0,A87[1:0],A1861b,A1861a,2'b0,A86[7:0],16'b0}; assign Af2 = (Aed || A18599) && Ad2; always @(posedge A117) begin if (iu_had_fast_retire_acc_err_pc_update || iu_had_int_ack) A8d[30:0] <= iu_had_fast_retire_acc_err_pc_val[30:0]; else if (iu_had_xx_dbg_ack) A8d[30:0] <= iu_had_xx_retire_pc[31:1]; else if (Af2) A8d[30:0] <= A104[31:1]; else A8d[30:0] <= A8d[30:0]; end assign A185b0[31:0] = {A8d[30:0], 1'b0}; assign Aa0 = A18563 && Ac0; always @(posedge A117 or negedge hadrst_b) begin if (!hadrst_b) begin A85 <= 1'b0; A1861d <= 1'b0; end else if (Aa0) begin A85 <= A13e[8]; A1861d <= A13e[7]; end else if (A18586) begin A85 <= A18587; A1861d <= 1'b0; end else begin A85 <= A85; A1861d <= A1861d; end end assign A18602[15:0] = {7'b0, A85, A1861d, 7'b0}; assign A185bc = A18563 && A185d9; always @(posedge A117 or negedge hadrst_b) begin if (!hadrst_b) begin A88 <= 1'b0; A8b <= 1'b0; A18616 <= 1'b0; A8c <= 1'b0; end else if (A185bc) begin A88 <= A13e[21]; A8b <= A13e[20]; A18616 <= A13e[15]; A8c <= A13e[13]; end else begin A88 <= A88; A8b <= A8b; A18616 <= A18616; A8c <= A8c; end end assign A185c2 = Aa6 && A185d9; always @(posedge A117 or negedge hadrst_b) begin if (!hadrst_b) begin A18619[2:0] <= 3'b0; end else if (A185c2) begin A18619[2:0] <= A104[2:0]; end else begin A18619[2:0] <= A18619[2:0]; end end assign Ae0 = Aa6 && A185d9; always @(posedge A117 or negedge hadrst_b) begin if (!hadrst_b) begin A89[2:0] <= 3'b0; end else if (Ae0) begin A89[2:0] <= A104[8:6]; end else begin A89[2:0] <= A89[2:0]; end end assign Ae2 = Aa6 && A185d9; always @(posedge A117 or negedge hadrst_b) begin if (!hadrst_b) A18618 <= 1'b0; else if (Ae2) A18618 <= A104[22]; else A18618 <= A18618; end assign A185bf = Aa6 && A185d9; always @(posedge A117 or negedge hadrst_b) begin if (!hadrst_b) A8a <= 1'b0; else if (A185bf) A8a <= A104[23]; else A8a <= A8a; end assign Ae3 = Aa6 && A185d9; always @(posedge A117 or negedge hadrst_b) begin if (!hadrst_b) A18617 <= 1'b0; else if (Ae3) A18617 <= A104[24]; else A18617 <= A18617; end assign Ae1[2:0] = {A18617, A8a, A18618}; assign A185c0[3:0] = 4'b0; assign A185c1[6:0] = {A185c0[3:0], Ae1[2:0]}; assign A185be = 1'b0; assign Ae4 = 1'b0; assign A185bd = 1'b0; assign Ae5[31:0] = {2'b0, A185be, A185c1[6:0], A88, A8b, Ae4, A185bd, 2'b0, A18616, 1'b0, A8c, 4'b0, A89[2:0], 3'b0, A18619[2:0]}; assign A1855c = (A185c1[6:0] != 7'b0) || (A89[2:0] != 3'b0) || (A18619[2:0] != 3'b0); always @(posedge A117 or negedge hadrst_b) begin if (!hadrst_b) A18622 <= 1'b0; else if (A118) A18622 <= 1'b1; else if (A1858a) A18622 <= 1'b0; else A18622 <= A18622; end always @(posedge A117 or negedge hadrst_b) begin if (!hadrst_b) A84 <= 1'b0; else if (A18589) A84 <= 1'b1; else if (A1858a) A84 <= 1'b0; else A84 <= A84; end always @(posedge A117 or negedge hadrst_b) begin if (!hadrst_b) A18615 <= 1'b0; else if (A119) A18615 <= 1'b1; else if (A1858a) A18615 <= 1'b0; else A18615 <= A18615; end always @(posedge A117 or negedge hadrst_b) begin if (!hadrst_b) A18613 <= 1'b0; else if (A18588) A18613 <= 1'b1; else if (A1858a) A18613 <= 1'b0; else A18613 <= A18613; end always @(posedge A117 or negedge hadrst_b) begin if (!hadrst_b) A8f <= 1'b0; else if (A11a) A8f <= 1'b1; else if (A1858a) A8f <= 1'b0; else A8f <= A8f; end assign Af3 = !cp0_had_lpmd_b[1] || !cp0_had_lpmd_b[0]; always @(posedge A117 or negedge hadrst_b) begin if (!hadrst_b) begin A18614 <= 1'b0; end else begin if (A1858a) A18614 <= 1'b0; else if (iu_yy_xx_dbgon) A18614 <= 1'b1; else A18614 <= A18614; end end assign A185af[1:0] = {A18614, Af3}; assign had_core_dbg_mode_req = A18614 && !iu_yy_xx_dbgon; assign Ae7[15:0] = {6'b0, A18622, A84, A18615, A18613, A8f, 3'b0, A185af[1:0]}; assign A185bb = 1'b0; assign A185f8 = 1'b0; assign A185f7 = 1'b0; assign A185b2 = 1'b0; assign A185b5 = 1'b0; assign A1859d = 1'b0; assign A14e = 1'b0; assign had_iu_rte_pc_sel = 1'b0; assign had_iu_int_vld = 1'b0; assign Ae6[31:0] = {26'b0, A1859d, A185b5, A185b2, A185f7, A185f8, A185bb}; assign Aa9[31:0] = 32'b0; assign Aaa[31:0] = 32'b0; assign Aa4[31:0] = 32'b0; assign A185fd[31:0] = 32'b0; assign Aa5[31:0] = 32'b0; assign A1859c = 1'b0; assign A18603 = 1'b1; assign A106 = A18603 || ~(A18603 || A1859c); assign A105 = A18603? Aa4[10] : 1'b0; assign A91 = Aa6 && A185f3; always @(posedge A117) begin if (A91) A81[31:0] <= A104[31:0]; else A81[31:0] <= A81[31:0]; end assign A18610 = Aa6 && A185f2; always @(posedge A117) begin if (A18610) A18620[31:0] <= A104[31:0]; else A18620[31:0] <= A18620[31:0]; end assign A92 = Aa6 && A185f1; always @(posedge A117) begin if (A92) A82[31:0] <= A104[31:0]; else A82[31:0] <= A82[31:0]; end assign A1860f[31:0] = 32'b0; assign A93[31:0] = 32'b0; assign A1860e[31:0] = 32'b0; assign A94[31:0] = 32'b0; assign A1860c[7:0] = 8'b0; assign A96[7:0] = 8'b0; assign A1860b[7:0] = 8'b0; assign A97[7:0] = 8'b0; assign A1860a[7:0] = 8'b0; assign A98[7:0] = 8'b0; assign A18609[7:0] = 8'b0; assign A185b1[3:0] = 4'b0; assign Af0[31:0] = 32'b0; assign Af1[31:0] = 32'b0; assign A185ae = 1'b0; assign Af4[31:0] = 32'b0; assign A185fc[31:0] = {31'b0, A185ae}; assign had_iu_force_dbg_en = 1'b0; assign Aab[31:0] = 32'b0; assign Abf = A185e3 && !A109; assign Acc = A185d6 && !A109; assign Ad7 = 1'b0; assign Acb = A185d7 && !A109; assign Ad8 = A185ca && !A109; assign A185e1 = Ac0 && !A109; assign A185df = Ac2 && !A109; assign A185db = Ac6 && !A109; assign Ad6 = A185cc && !A109; assign A185cd = Ad4 && !A109; assign A185cf = Ad2 && !A109; assign Aca = A185d8 && !A109; assign Ac7 = 1'b0; assign Ac9 = A185d9 && !A109; assign A185d4 = 1'b0; assign A185d3 = 1'b0; assign Ab8 = 1'b0; assign Ab9 = 1'b0; assign Aba = 1'b0; assign Abb = 1'b0; assign Abc = 1'b0; assign Abd = 1'b0; assign Abe = 1'b0; assign Aad = A185f5 && !A109; assign Ab6 = A185ec && !A109; assign Aae = A185f4 && !A109; assign Ab7 = A185eb && !A109; assign Aaf = A185f3 && !A109; assign Ab0 = A185f2 && !A109; assign Ab1 = A185f1 && !A109; assign Ab2 = A185f0 && !A109; assign Ab3 = A185ef && !A109; assign Ab4 = A185ee && !A109; assign Ab5 = A185ed && !A109; assign A185e0 = Ac1 && !A109; assign A185dd = Ac4 && !A109; assign A185de = Ac3 && !A109 && A106; assign A185d1 = Ad0; assign A185d2 = Acf; assign A185d0 = Ad1; assign A185dc = Ac5 && !A109; assign A185ce = Ad3 && !A109; assign Ac8 = A185da && !A109; assign A185f9[31:0] = A109 ? Aa9[31:0] : Aaa[31:0]; assign A185fe[31:0] = {Aa4[31:11], A105, Aa4[9:0]}; always @( * ) begin case (1'b1) Abf : A8e[31:0] = {30'b0, A9c[1:0]}; Acc : A8e[31:0] = A185ba[31:0]; Ad7 : A8e[31:0] = 32'b0; A185d4 : A8e[31:0] = 32'b0; Aad : A8e[31:0] = A80[31:0]; Ab6 : A8e[31:0] = {24'b0, A1861f[7:0]}; Ac9 : A8e[31:0] = Ae5[31:0]; Acb : A8e[31:0] = {16'b0, Ae7[15:0]}; Aca : A8e[31:0] = Ae6[31:0]; Ad8 : A8e[31:0] = A18612[31:0]; A185cd : A8e[31:0] = {32{A18603}} & A185ad[31:0]; A185cf : A8e[31:0] = A185b0[31:0]; A185e1 : A8e[31:0] = {16'b0, A18602[15:0]}; Ac7 : A8e[31:0] = A185f9[31:0]; A185df : A8e[31:0] = A18612[31:0]; A185db : A8e[31:0] = A18612[31:0]; Ad6 : A8e[31:0] = A185ba[31:0]; A185d3 : A8e[31:0] = 32'b0; Aae: A8e[31:0] = A18621[31:0]; Ab7: A8e[31:0] = {24'b0, A83[7:0]}; Aaf : A8e[31:0] = A81[31:0]; Ab8 : A8e[31:0] = {24'b0, A1860c[7:0]}; Ab0 : A8e[31:0] = A18620[31:0]; Ab9 : A8e[31:0] = {24'b0, A96[7:0]}; Ab1 : A8e[31:0] = A82[31:0]; Aba : A8e[31:0] = {24'b0, A1860b[7:0]}; Ab2 : A8e[31:0] = A1860f[31:0]; Abb : A8e[31:0] = {24'b0, A97[7:0]}; Ab3 : A8e[31:0] = A93[31:0]; Abc : A8e[31:0] = {24'b0, A1860a[7:0]}; Ab4 : A8e[31:0] = A1860e[31:0]; Abd : A8e[31:0] = {24'b0, A98[7:0]}; Ab5 : A8e[31:0] = A94[31:0]; Abe : A8e[31:0] = {24'b0, A18609[7:0]}; A185e0 : A8e[31:0] = A185fe[31:0]; A185dd : A8e[31:0] = Aa5[31:0]; A185de : A8e[31:0] = A185fd[31:0]; A185d1 : A8e[31:0] = {28'b0, A185b1[3:0]}; A185d2 : A8e[31:0] = Af0[31:0]; A185d0 : A8e[31:0] = Af1[31:0]; A185dc : A8e[31:0] = A185fc[31:0]; A185ce : A8e[31:0] = Af4[31:0]; Ac8 : A8e[31:0] = Aab[31:0]; default : A8e[31:0] = 32'b0; endcase end assign had_ifu_ir[31:0] = A11c ? A11b[31:0] : A13e[31:0]; assign had_ifu_ir_vld = ((A18563 && A185d5 && Aac && !A185f6) || (A11c && A8b)) && iu_yy_xx_dbgon; assign had_iu_pc[30:0] = A185b0[31:1]; assign had_iu_xx_fdb = A1861d; assign had_idu_wbbr_data[31:0] = A18612[31:0]; assign had_idu_wbbr_vld = A85 && iu_yy_xx_dbgon; assign had_tcipif_cmplt = tcipif_had_sel; assign had_tcipif_rdata[31:0] = 32'b0; assign A150[31:0] = A8e[31:0]; assign A18551 = A185c9; assign A18550 = Acd || Ace || A185ec || A185eb || A185cb || A185ea || A185e9 || A185e8 || A185e7 || A185e6 || A185e5 || A185e4; assign A151 = A185d7 || Ac0; assign A18554 = Aac; assign A14d = A185f6; assign A14c = A18616; assign A18556 = A88; assign A18555 = Ad2 || A185d5 || A185ca || Ad4 || Ac0 || A185e2; assign A14f = Ac2; assign A18552 = Ac6; assign A153 = A8b; assign A161 = A8c; assign A152[1:0] = A185af[1:0]; assign A145[31:0] = A80[31:0]; assign A1855b[7:0] = A1861f[7:0]; assign A146[2:0] = A18619[2:0]; assign A147[31:0] = A18621[31:0]; assign A148[7:0] = A83[7:0]; assign A1855a[2:0] = A89[2:0]; assign A18559[31:0] = A81[31:0]; assign A149 = A185c1[0]; assign A18558[31:0] = A18620[31:0]; assign A14a = A185c1[1]; assign A18557[31:0] = A82[31:0]; assign A14b = A185c1[2]; assign A18553[8:0] = Af0[8:0]; endmodule module A10a( A18595, A10d, A18594, A10e, A18593, A10f ); input A18595; input A10d; input A18594; input A10e; input A18593; output A10f; reg A18597; reg A10b; reg A18596; reg A10c; wire A18595; wire A10d; wire A18594; wire A10e; wire A18593; wire A10f; always @(posedge A10d or negedge A10e) begin if (!A10e) A10c <= 1'b0; else A10c <= A18593; end always @(posedge A18595 or negedge A18594) begin if (!A18594) begin A18597 <= 1'b0; A10b <= 1'b0; end else begin A18597 <= A10c; A10b <= A18597; end end always @(posedge A18595 or negedge A18594) begin if (!A18594) A18596 <= 1'b0; else A18596 <= A10b; end assign A10f = !A18596 && A10b; endmodule module cr_had_top( cp0_had_cpuid_idx0, cp0_had_int_exit, cp0_had_lpmd_b, cp0_had_mcause_data, forever_cpuclk_nogated, had_core_dbg_mode_req, had_idu_wbbr_data, had_idu_wbbr_vld, had_ifu_inst_bkpt_dbq_req, had_ifu_inst_bkpt_dbqexp_req, had_ifu_ir, had_ifu_ir_vld, had_iu_bkpt_trace_en, had_iu_dr_set_req, had_iu_force_dbg_en, had_iu_int_vld, had_iu_mbkpt_fsm_index_mbee, had_iu_mem_bkpt_exp_req, had_iu_mem_bkpt_mask, had_iu_mem_bkpt_req, had_iu_pc, had_iu_rte_pc_sel, had_iu_trace_req, had_iu_trace_req_for_dbg_disable, had_iu_xx_fdb, had_iu_xx_jdbreq, had_pad_jdb_ack_b, had_pad_jdb_pm, had_pad_jtg_tap_on, had_pad_jtg_tms_o, had_pad_jtg_tms_oe, had_pad_wakeup_req_b, had_tcipif_cmplt, had_tcipif_rdata, had_yy_xx_dbg, had_yy_xx_dp_index_mbee, had_yy_xx_exit_dbg, hadrst_b, ifu_had_chg_flw_inst, ifu_had_fetch_expt_vld, ifu_had_inst_dbg_disable, ifu_had_match_pc, ifu_had_split_first, iu_had_adr_dbg_ack, iu_had_chgflw_dst_pc, iu_had_chgflw_vld, iu_had_data_bkpt_occur_vld, iu_had_dbg_disable_for_tee, iu_had_dr_dbg_ack, iu_had_expt_vld, iu_had_fast_retire_acc_err_pc_update, iu_had_fast_retire_acc_err_pc_val, iu_had_flush, iu_had_inst_bkpt_occur_vld, iu_had_int_ack, iu_had_retire_with_had_int, iu_had_trace_occur_vld, iu_had_xx_bkpt_inst, iu_had_xx_data, iu_had_xx_data_vld, iu_had_xx_dbg_ack, iu_had_xx_mldst, iu_had_xx_retire, iu_had_xx_retire_normal, iu_had_xx_retire_pc, iu_yy_xx_dbgon, lsu_had_addr, lsu_had_addr_vld, lsu_had_ex_cmplt, lsu_had_st, pad_had_jdb_req_b, pad_had_jtg_tap_en, pad_had_jtg_tms_i, pad_yy_gate_clk_en_b, pad_yy_test_mode, tcipif_had_addr, tcipif_had_sel, tcipif_had_wdata, tcipif_had_write, tclk, trst_b ); input [31:0] cp0_had_cpuid_idx0; input cp0_had_int_exit; input [1 :0] cp0_had_lpmd_b; input [31:0] cp0_had_mcause_data; input forever_cpuclk_nogated; input hadrst_b; input ifu_had_chg_flw_inst; input ifu_had_fetch_expt_vld; input ifu_had_inst_dbg_disable; input [31:0] ifu_had_match_pc; input ifu_had_split_first; input iu_had_adr_dbg_ack; input [31:0] iu_had_chgflw_dst_pc; input iu_had_chgflw_vld; input iu_had_data_bkpt_occur_vld; input iu_had_dbg_disable_for_tee; input iu_had_dr_dbg_ack; input iu_had_expt_vld; input iu_had_fast_retire_acc_err_pc_update; input [30:0] iu_had_fast_retire_acc_err_pc_val; input iu_had_flush; input iu_had_inst_bkpt_occur_vld; input iu_had_int_ack; input iu_had_retire_with_had_int; input iu_had_trace_occur_vld; input iu_had_xx_bkpt_inst; input [31:0] iu_had_xx_data; input iu_had_xx_data_vld; input iu_had_xx_dbg_ack; input iu_had_xx_mldst; input iu_had_xx_retire; input iu_had_xx_retire_normal; input [31:0] iu_had_xx_retire_pc; input iu_yy_xx_dbgon; input [31:0] lsu_had_addr; input lsu_had_addr_vld; input lsu_had_ex_cmplt; input lsu_had_st; input pad_had_jdb_req_b; input pad_had_jtg_tap_en; input pad_had_jtg_tms_i; input pad_yy_gate_clk_en_b; input pad_yy_test_mode; input [15:0] tcipif_had_addr; input tcipif_had_sel; input [31:0] tcipif_had_wdata; input tcipif_had_write; input tclk; input trst_b; output had_core_dbg_mode_req; output [31:0] had_idu_wbbr_data; output had_idu_wbbr_vld; output had_ifu_inst_bkpt_dbq_req; output had_ifu_inst_bkpt_dbqexp_req; output [31:0] had_ifu_ir; output had_ifu_ir_vld; output had_iu_bkpt_trace_en; output had_iu_dr_set_req; output had_iu_force_dbg_en; output had_iu_int_vld; output had_iu_mbkpt_fsm_index_mbee; output had_iu_mem_bkpt_exp_req; output had_iu_mem_bkpt_mask; output had_iu_mem_bkpt_req; output [30:0] had_iu_pc; output had_iu_rte_pc_sel; output had_iu_trace_req; output had_iu_trace_req_for_dbg_disable; output had_iu_xx_fdb; output had_iu_xx_jdbreq; output had_pad_jdb_ack_b; output [1 :0] had_pad_jdb_pm; output had_pad_jtg_tap_on; output had_pad_jtg_tms_o; output had_pad_jtg_tms_oe; output had_pad_wakeup_req_b; output had_tcipif_cmplt; output [31:0] had_tcipif_rdata; output had_yy_xx_dbg; output had_yy_xx_dp_index_mbee; output had_yy_xx_exit_dbg; wire A110; wire A18591; wire A111; wire A18590; wire A112; wire A1858f; wire A113; wire A1858e; wire A114; wire A1858d; wire [31:0] cp0_had_cpuid_idx0; wire cp0_had_int_exit; wire [1 :0] cp0_had_lpmd_b; wire [31:0] cp0_had_mcause_data; wire A117; wire A1858a; wire A118; wire A18589; wire A119; wire A18588; wire A11a; wire A18587; wire [31:0] A11b; wire A18586; wire A11c; wire forever_cpuclk_nogated; wire A11d; wire had_core_dbg_mode_req; wire [31:0] had_idu_wbbr_data; wire had_idu_wbbr_vld; wire had_ifu_inst_bkpt_dbq_req; wire had_ifu_inst_bkpt_dbqexp_req; wire [31:0] had_ifu_ir; wire had_ifu_ir_vld; wire had_iu_bkpt_trace_en; wire had_iu_dr_set_req; wire had_iu_force_dbg_en; wire had_iu_int_vld; wire had_iu_mbkpt_fsm_index_mbee; wire had_iu_mem_bkpt_exp_req; wire had_iu_mem_bkpt_mask; wire had_iu_mem_bkpt_req; wire [30:0] had_iu_pc; wire had_iu_rte_pc_sel; wire had_iu_trace_req; wire had_iu_trace_req_for_dbg_disable; wire had_iu_xx_fdb; wire had_iu_xx_jdbreq; wire had_pad_jdb_ack_b; wire [1 :0] had_pad_jdb_pm; wire had_pad_jtg_tap_on; wire had_pad_jtg_tms_o; wire had_pad_jtg_tms_oe; wire had_pad_wakeup_req_b; wire had_tcipif_cmplt; wire [31:0] had_tcipif_rdata; wire had_yy_xx_dbg; wire had_yy_xx_dp_index_mbee; wire had_yy_xx_exit_dbg; wire hadrst_b; wire ifu_had_chg_flw_inst; wire ifu_had_fetch_expt_vld; wire ifu_had_inst_dbg_disable; wire [31:0] ifu_had_match_pc; wire ifu_had_split_first; wire iu_had_adr_dbg_ack; wire [31:0] iu_had_chgflw_dst_pc; wire iu_had_chgflw_vld; wire iu_had_data_bkpt_occur_vld; wire iu_had_dbg_disable_for_tee; wire iu_had_dr_dbg_ack; wire iu_had_expt_vld; wire iu_had_fast_retire_acc_err_pc_update; wire [30:0] iu_had_fast_retire_acc_err_pc_val; wire iu_had_flush; wire iu_had_inst_bkpt_occur_vld; wire iu_had_int_ack; wire iu_had_retire_with_had_int; wire iu_had_trace_occur_vld; wire iu_had_xx_bkpt_inst; wire [31:0] iu_had_xx_data; wire iu_had_xx_data_vld; wire iu_had_xx_dbg_ack; wire iu_had_xx_mldst; wire iu_had_xx_retire; wire iu_had_xx_retire_normal; wire [31:0] iu_had_xx_retire_pc; wire iu_yy_xx_dbgon; wire A13c; wire A18565; wire A13d; wire A18564; wire [31:0] A13e; wire A18563; wire [31:0] lsu_had_addr; wire lsu_had_addr_vld; wire lsu_had_ex_cmplt; wire lsu_had_st; wire pad_had_jdb_req_b; wire pad_had_jtg_tap_en; wire pad_had_jtg_tms_i; wire pad_yy_gate_clk_en_b; wire pad_yy_test_mode; wire A1855e; wire A144; wire A1855d; wire [31:0] A145; wire A1855c; wire [2 :0] A146; wire [7 :0] A1855b; wire [31:0] A147; wire [2 :0] A1855a; wire [7 :0] A148; wire [31:0] A18559; wire A149; wire [31:0] A18558; wire A14a; wire [31:0] A18557; wire A14b; wire A18556; wire A14c; wire A18555; wire A14d; wire A18554; wire A14e; wire [8 :0] A18553; wire A14f; wire A18552; wire [31:0] A150; wire A18551; wire A151; wire A18550; wire [1 :0] A152; wire A161; wire A153; wire A1854e; wire [15:0] tcipif_had_addr; wire tcipif_had_sel; wire [31:0] tcipif_had_wdata; wire tcipif_had_write; wire tclk; wire A162; wire A1853f; wire trst_b; gated_clk_cell A158 ( .clk_in (forever_cpuclk_nogated), .clk_out (A117 ), .external_en (1'b0 ), .global_en (1'b1 ), .local_en (1'b0 ), .module_en (A11d ), .pad_yy_gate_clk_en_b (pad_yy_gate_clk_en_b ), .pad_yy_test_mode (pad_yy_test_mode ) ); assign A11d = A1854e || tcipif_had_sel; A186a0 A18549 ( .A1868b (A110), .A17 (A18591 ), .A117 (A117 ), .had_core_dbg_mode_req (had_core_dbg_mode_req ), .hadrst_b (hadrst_b ), .ifu_had_chg_flw_inst (ifu_had_chg_flw_inst ), .ifu_had_fetch_expt_vld (ifu_had_fetch_expt_vld ), .ifu_had_inst_dbg_disable (ifu_had_inst_dbg_disable ), .ifu_had_match_pc (ifu_had_match_pc ), .ifu_had_split_first (ifu_had_split_first ), .iu_had_expt_vld (iu_had_expt_vld ), .iu_had_flush (iu_had_flush ), .iu_had_xx_mldst (iu_had_xx_mldst ), .iu_had_xx_retire (iu_had_xx_retire ), .iu_had_xx_retire_normal (iu_had_xx_retire_normal ), .iu_yy_xx_dbgon (iu_yy_xx_dbgon ), .lsu_had_addr (lsu_had_addr ), .lsu_had_addr_vld (lsu_had_addr_vld ), .lsu_had_ex_cmplt (lsu_had_ex_cmplt ), .lsu_had_st (lsu_had_st ), .A1867c (A145 ), .A14 (A146 ), .A1868d (A1855b ) ); A186a0 A159 ( .A1868b (A111), .A17 (A18590 ), .A117 (A117 ), .had_core_dbg_mode_req (had_core_dbg_mode_req ), .hadrst_b (hadrst_b ), .ifu_had_chg_flw_inst (ifu_had_chg_flw_inst ), .ifu_had_fetch_expt_vld (ifu_had_fetch_expt_vld ), .ifu_had_inst_dbg_disable (ifu_had_inst_dbg_disable ), .ifu_had_match_pc (ifu_had_match_pc ), .ifu_had_split_first (ifu_had_split_first ), .iu_had_expt_vld (iu_had_expt_vld ), .iu_had_flush (iu_had_flush ), .iu_had_xx_mldst (iu_had_xx_mldst ), .iu_had_xx_retire (iu_had_xx_retire ), .iu_had_xx_retire_normal (iu_had_xx_retire_normal ), .iu_yy_xx_dbgon (iu_yy_xx_dbgon ), .lsu_had_addr (lsu_had_addr ), .lsu_had_addr_vld (lsu_had_addr_vld ), .lsu_had_ex_cmplt (lsu_had_ex_cmplt ), .lsu_had_st (lsu_had_st ), .A1867c (A147 ), .A14 (A1855a ), .A1868d (A148 ) ); A15 A18548 ( .A1868b (A112), .A17 (A1858f ), .A117 (A117 ), .had_core_dbg_mode_req (had_core_dbg_mode_req ), .hadrst_b (hadrst_b ), .ifu_had_fetch_expt_vld (ifu_had_fetch_expt_vld ), .ifu_had_inst_dbg_disable (ifu_had_inst_dbg_disable ), .ifu_had_match_pc (ifu_had_match_pc ), .ifu_had_split_first (ifu_had_split_first ), .iu_had_expt_vld (iu_had_expt_vld ), .iu_had_flush (iu_had_flush ), .iu_had_xx_mldst (iu_had_xx_mldst ), .iu_had_xx_retire (iu_had_xx_retire ), .iu_had_xx_retire_normal (iu_had_xx_retire_normal ), .iu_yy_xx_dbgon (iu_yy_xx_dbgon ), .lsu_had_addr (lsu_had_addr ), .lsu_had_addr_vld (lsu_had_addr_vld ), .lsu_had_ex_cmplt (lsu_had_ex_cmplt ), .A1867c (A18559 ), .A26 (A149 ) ); A15 A15a ( .A1868b (A113), .A17 (A1858e ), .A117 (A117 ), .had_core_dbg_mode_req (had_core_dbg_mode_req ), .hadrst_b (hadrst_b ), .ifu_had_fetch_expt_vld (ifu_had_fetch_expt_vld ), .ifu_had_inst_dbg_disable (ifu_had_inst_dbg_disable ), .ifu_had_match_pc (ifu_had_match_pc ), .ifu_had_split_first (ifu_had_split_first ), .iu_had_expt_vld (iu_had_expt_vld ), .iu_had_flush (iu_had_flush ), .iu_had_xx_mldst (iu_had_xx_mldst ), .iu_had_xx_retire (iu_had_xx_retire ), .iu_had_xx_retire_normal (iu_had_xx_retire_normal ), .iu_yy_xx_dbgon (iu_yy_xx_dbgon ), .lsu_had_addr (lsu_had_addr ), .lsu_had_addr_vld (lsu_had_addr_vld ), .lsu_had_ex_cmplt (lsu_had_ex_cmplt ), .A1867c (A18558 ), .A26 (A14a ) ); A15 A18547 ( .A1868b (A114), .A17 (A1858d ), .A117 (A117 ), .had_core_dbg_mode_req (had_core_dbg_mode_req ), .hadrst_b (hadrst_b ), .ifu_had_fetch_expt_vld (ifu_had_fetch_expt_vld ), .ifu_had_inst_dbg_disable (ifu_had_inst_dbg_disable ), .ifu_had_match_pc (ifu_had_match_pc ), .ifu_had_split_first (ifu_had_split_first ), .iu_had_expt_vld (iu_had_expt_vld ), .iu_had_flush (iu_had_flush ), .iu_had_xx_mldst (iu_had_xx_mldst ), .iu_had_xx_retire (iu_had_xx_retire ), .iu_had_xx_retire_normal (iu_had_xx_retire_normal ), .iu_yy_xx_dbgon (iu_yy_xx_dbgon ), .lsu_had_addr (lsu_had_addr ), .lsu_had_addr_vld (lsu_had_addr_vld ), .lsu_had_ex_cmplt (lsu_had_ex_cmplt ), .A1867c (A18557 ), .A26 (A14b ) ); A1867b A15b ( .A110 (A110 ), .A18591 (A18591 ), .A111 (A111 ), .A18590 (A18590 ), .A112 (A112 ), .A1858f (A1858f ), .A113 (A113 ), .A1858e (A1858e ), .A114 (A114 ), .A1858d (A1858d ), .A117 (A117 ), .A1858a (A1858a ), .A118 (A118 ), .A18589 (A18589 ), .A119 (A119 ), .A18588 (A18588 ), .A11a (A11a ), .had_ifu_inst_bkpt_dbq_req (had_ifu_inst_bkpt_dbq_req ), .had_ifu_inst_bkpt_dbqexp_req (had_ifu_inst_bkpt_dbqexp_req ), .had_iu_bkpt_trace_en (had_iu_bkpt_trace_en ), .had_iu_dr_set_req (had_iu_dr_set_req ), .had_iu_mbkpt_fsm_index_mbee (had_iu_mbkpt_fsm_index_mbee ), .had_iu_mem_bkpt_exp_req (had_iu_mem_bkpt_exp_req ), .had_iu_mem_bkpt_mask (had_iu_mem_bkpt_mask ), .had_iu_mem_bkpt_req (had_iu_mem_bkpt_req ), .had_iu_trace_req (had_iu_trace_req ), .had_iu_trace_req_for_dbg_disable (had_iu_trace_req_for_dbg_disable), .had_iu_xx_jdbreq (had_iu_xx_jdbreq ), .had_yy_xx_dbg (had_yy_xx_dbg ), .had_yy_xx_dp_index_mbee (had_yy_xx_dp_index_mbee ), .had_yy_xx_exit_dbg (had_yy_xx_exit_dbg ), .hadrst_b (hadrst_b ), .iu_had_adr_dbg_ack (iu_had_adr_dbg_ack ), .iu_had_chgflw_dst_pc (iu_had_chgflw_dst_pc ), .iu_had_chgflw_vld (iu_had_chgflw_vld ), .iu_had_data_bkpt_occur_vld (iu_had_data_bkpt_occur_vld ), .iu_had_dbg_disable_for_tee (iu_had_dbg_disable_for_tee ), .iu_had_dr_dbg_ack (iu_had_dr_dbg_ack ), .iu_had_inst_bkpt_occur_vld (iu_had_inst_bkpt_occur_vld ), .iu_had_trace_occur_vld (iu_had_trace_occur_vld ), .iu_had_xx_bkpt_inst (iu_had_xx_bkpt_inst ), .iu_yy_xx_dbgon (iu_yy_xx_dbgon ), .A18563 (A18563 ), .A1855e (A1855e ), .A1855c (A1855c ), .A18556 (A18556 ), .A14c (A14c ), .A18555 (A18555 ), .A14d (A14d ), .A18554 (A18554 ), .A14e (A14e ), .A18553 (A18553 ), .A161 (A161 ), .A162 (A162 ), .A1853f (A1853f ) ); A45 A18546 ( .A117 (A117 ), .A18587 (A18587 ), .A11b (A11b ), .A18586 (A18586), .A11c (A11c ), .hadrst_b (hadrst_b ), .iu_had_xx_retire (iu_had_xx_retire ), .A18563 (A18563 ), .A14f (A14f ), .A18552 (A18552 ), .A153 (A153 ) ); A1862c A15c ( .had_pad_jdb_ack_b (had_pad_jdb_ack_b ), .had_pad_jdb_pm (had_pad_jdb_pm ), .had_pad_jtg_tap_on (had_pad_jtg_tap_on), .had_pad_jtg_tms_o (had_pad_jtg_tms_o ), .had_pad_jtg_tms_oe (had_pad_jtg_tms_oe), .iu_yy_xx_dbgon (iu_yy_xx_dbgon ), .A13c (A13c ), .A18565 (A18565 ), .pad_had_jdb_req_b (pad_had_jdb_req_b ), .pad_had_jtg_tap_en (pad_had_jtg_tap_en), .pad_had_jtg_tms_i (pad_had_jtg_tms_i ), .A1855e (A1855e ), .A144 (A144 ), .A1855d (A1855d ), .A152 (A152 ), .tclk (tclk ), .trst_b (trst_b ) ); A7f A18545 ( .cp0_had_cpuid_idx0 (cp0_had_cpuid_idx0 ), .cp0_had_int_exit (cp0_had_int_exit ), .cp0_had_lpmd_b (cp0_had_lpmd_b ), .cp0_had_mcause_data (cp0_had_mcause_data ), .A117 (A117 ), .A1858a (A1858a ), .A118 (A118 ), .A18589 (A18589 ), .A119 (A119 ), .A18588 (A18588 ), .A11a (A11a ), .A18587 (A18587 ), .A11b (A11b ), .A18586 (A18586 ), .A11c (A11c ), .had_core_dbg_mode_req (had_core_dbg_mode_req ), .had_idu_wbbr_data (had_idu_wbbr_data ), .had_idu_wbbr_vld (had_idu_wbbr_vld ), .had_ifu_ir (had_ifu_ir ), .had_ifu_ir_vld (had_ifu_ir_vld ), .had_iu_force_dbg_en (had_iu_force_dbg_en ), .had_iu_int_vld (had_iu_int_vld ), .had_iu_pc (had_iu_pc ), .had_iu_rte_pc_sel (had_iu_rte_pc_sel ), .had_iu_xx_fdb (had_iu_xx_fdb ), .had_tcipif_cmplt (had_tcipif_cmplt ), .had_tcipif_rdata (had_tcipif_rdata ), .hadrst_b (hadrst_b ), .iu_had_fast_retire_acc_err_pc_update (iu_had_fast_retire_acc_err_pc_update), .iu_had_fast_retire_acc_err_pc_val (iu_had_fast_retire_acc_err_pc_val ), .iu_had_int_ack (iu_had_int_ack ), .iu_had_retire_with_had_int (iu_had_retire_with_had_int ), .iu_had_xx_data (iu_had_xx_data ), .iu_had_xx_data_vld (iu_had_xx_data_vld ), .iu_had_xx_dbg_ack (iu_had_xx_dbg_ack ), .iu_had_xx_retire_pc (iu_had_xx_retire_pc ), .iu_yy_xx_dbgon (iu_yy_xx_dbgon ), .A13d (A13d ), .A18564 (A18564 ), .A13e (A13e ), .A18563 (A18563 ), .A145 (A145 ), .A1855c (A1855c ), .A146 (A146 ), .A1855b (A1855b ), .A147 (A147 ), .A1855a (A1855a ), .A148 (A148 ), .A18559 (A18559 ), .A149 (A149 ), .A18558 (A18558 ), .A14a (A14a ), .A18557 (A18557 ), .A14b (A14b ), .A18556 (A18556 ), .A14c (A14c ), .A18555 (A18555 ), .A14d (A14d ), .A18554 (A18554 ), .A14e (A14e ), .A18553 (A18553 ), .A14f (A14f ), .A18552 (A18552 ), .A150 (A150 ), .A18551 (A18551 ), .A151 (A151 ), .A18550 (A18550 ), .A152 (A152 ), .A161 (A161 ), .A153 (A153 ), .tcipif_had_addr (tcipif_had_addr ), .tcipif_had_sel (tcipif_had_sel ), .tcipif_had_wdata (tcipif_had_wdata ), .tcipif_had_write (tcipif_had_write ) ); A1864d A15d ( .A117 (A117 ), .forever_cpuclk_nogated (forever_cpuclk_nogated), .had_pad_wakeup_req_b (had_pad_wakeup_req_b ), .hadrst_b (hadrst_b ), .A13c (A13c ), .A18565 (A18565 ), .A13d (A13d ), .A18564 (A18564 ), .A13e (A13e ), .A18563 (A18563 ), .A144 (A144 ), .A1855d (A1855d ), .A150 (A150 ), .A18551 (A18551 ), .A151 (A151 ), .A18550 (A18550 ), .A1854e (A1854e ), .tclk (tclk ), .trst_b (trst_b ) ); A15e A18544 ( .had_core_dbg_mode_req (had_core_dbg_mode_req ), .iu_had_xx_mldst (iu_had_xx_mldst ), .iu_had_xx_retire (iu_had_xx_retire ), .iu_had_xx_retire_normal (iu_had_xx_retire_normal ), .iu_yy_xx_dbgon (iu_yy_xx_dbgon ), .A161 (A161 ), .A162 (A162 ), .A1853f (A1853f) ); endmodule module A15e( had_core_dbg_mode_req, iu_had_xx_mldst, iu_had_xx_retire, iu_had_xx_retire_normal, iu_yy_xx_dbgon, A161, A162, A1853f ); input had_core_dbg_mode_req; input iu_had_xx_mldst; input iu_had_xx_retire; input iu_had_xx_retire_normal; input iu_yy_xx_dbgon; input A161; output A162; output A1853f; wire had_core_dbg_mode_req; wire iu_had_xx_mldst; wire iu_had_xx_retire; wire iu_had_xx_retire_normal; wire iu_yy_xx_dbgon; wire A161; wire A18540; wire A162; wire A1853f; wire A163; wire A1853e; assign A163 = !iu_yy_xx_dbgon && A161 && !had_core_dbg_mode_req; assign A1853e = iu_had_xx_retire && !iu_had_xx_mldst && A163; assign A18540 = 1'b1; assign A162 = A1853e && A18540 && iu_had_xx_retire_normal; assign A1853f = 1'b0; endmodule