From 03429c91d1db134e1deda4c8e58bc0939d5fedf9 Mon Sep 17 00:00:00 2001 From: Mahesh Bodapati Date: Thu, 12 Jan 2017 16:52:56 +0530 Subject: [PATCH 11/54] [Patch, microblaze]: Added ashrsi3_with_size_opt Added ashrsi3_with_size_opt pattern to optimize the sra instructions when the -Os optimization is used. lshrsi3_with_size_opt is being removed as it has conflicts with unsigned int variables Signed-off-by:Nagaraju Mekala --- gcc/config/microblaze/microblaze.md | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md index eba2776ae56..187ad522dcc 100644 --- a/gcc/config/microblaze/microblaze.md +++ b/gcc/config/microblaze/microblaze.md @@ -1508,6 +1508,27 @@ (set_attr "length" "4,4")] ) +(define_insn "*ashrsi3_with_size_opt" + [(set (match_operand:SI 0 "register_operand" "=&d") + (ashiftrt:SI (match_operand:SI 1 "register_operand" "d") + (match_operand:SI 2 "immediate_operand" "I")))] + "(INTVAL (operands[2]) > 5 && optimize_size)" + { + operands[3] = gen_rtx_REG (SImode, MB_ABI_ASM_TEMP_REGNUM); + + output_asm_insn ("ori\t%3,r0,%2", operands); + if (REGNO (operands[0]) != REGNO (operands[1])) + output_asm_insn ("addk\t%0,%1,r0", operands); + + output_asm_insn ("addik\t%3,%3,-1", operands); + output_asm_insn ("bneid\t%3,.-4", operands); + return "sra\t%0,%0"; + } + [(set_attr "type" "arith") + (set_attr "mode" "SI") + (set_attr "length" "20")] +) + (define_insn "*ashrsi_inline" [(set (match_operand:SI 0 "register_operand" "=&d") (ashiftrt:SI (match_operand:SI 1 "register_operand" "d") -- 2.17.1