*** Running vivado with args -log encoder83.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source encoder83.tcl -notrace ****** Vivado v2018.1 (64-bit) **** SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 **** IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 ** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. source encoder83.tcl -notrace Command: link_design -top encoder83 -part xc7a100tcsg324-1 Design is defaulting to srcset: sources_1 Design is defaulting to constrset: constrs_1 INFO: [Project 1-479] Netlist was created with Vivado 2018.1 INFO: [Device 21-403] Loading part xc7a100tcsg324-1 INFO: [Project 1-570] Preparing netlist for logic optimization Parsing XDC File [C:/Users/lenovo/Desktop/T2Task4/encoder83/encoder83.srcs/constrs_1/new/encoder83_constrains.xdc] Finished Parsing XDC File [C:/Users/lenovo/Desktop/T2Task4/encoder83/encoder83.srcs/constrs_1/new/encoder83_constrains.xdc] INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 5 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. link_design completed successfully link_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 579.945 ; gain = 329.113 Command: opt_design Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' Running DRC as a precondition to command opt_design Starting DRC Task INFO: [DRC 23-27] Running DRC with 2 threads INFO: [Project 1-461] DRC finished with 0 Errors INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.416 . Memory (MB): peak = 579.945 ; gain = 0.000 INFO: [Timing 38-35] Done setting XDC timing constraints. Starting Logic Optimization Task Phase 1 Retarget INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Opt 31-49] Retargeted 0 cell(s). Phase 1 Retarget | Checksum: 1adb5c766 Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.036 . Memory (MB): peak = 1071.098 ; gain = 0.000 INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells Phase 2 Constant propagation INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Phase 2 Constant propagation | Checksum: 1adb5c766 Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.039 . Memory (MB): peak = 1071.098 ; gain = 0.000 INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells Phase 3 Sweep Phase 3 Sweep | Checksum: 1adb5c766 Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.048 . Memory (MB): peak = 1071.098 ; gain = 0.000 INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells Phase 4 BUFG optimization Phase 4 BUFG optimization | Checksum: 1adb5c766 Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.055 . Memory (MB): peak = 1071.098 ; gain = 0.000 INFO: [Opt 31-389] Phase BUFG optimization created 0 cells and removed 0 cells Phase 5 Shift Register Optimization Phase 5 Shift Register Optimization | Checksum: 1adb5c766 Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.059 . Memory (MB): peak = 1071.098 ; gain = 0.000 INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells Phase 6 Post Processing Netlist Phase 6 Post Processing Netlist | Checksum: 1adb5c766 Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.061 . Memory (MB): peak = 1071.098 ; gain = 0.000 INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells Starting Connectivity Check Task Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1071.098 ; gain = 0.000 Ending Logic Optimization Task | Checksum: 1adb5c766 Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.066 . Memory (MB): peak = 1071.098 ; gain = 0.000 Starting Power Optimization Task INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. Ending Power Optimization Task | Checksum: 1adb5c766 Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.032 . Memory (MB): peak = 1071.098 ; gain = 0.000 INFO: [Common 17-83] Releasing license: Implementation 21 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. opt_design completed successfully opt_design: Time (s): cpu = 00:00:35 ; elapsed = 00:00:42 . Memory (MB): peak = 1071.098 ; gain = 491.152 INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.137 . Memory (MB): peak = 1071.098 ; gain = 0.000 INFO: [Common 17-1381] The checkpoint 'C:/Users/lenovo/Desktop/T2Task4/encoder83/encoder83.runs/impl_1/encoder83_opt.dcp' has been generated. INFO: [runtcl-4] Executing : report_drc -file encoder83_drc_opted.rpt -pb encoder83_drc_opted.pb -rpx encoder83_drc_opted.rpx Command: report_drc -file encoder83_drc_opted.rpt -pb encoder83_drc_opted.pb -rpx encoder83_drc_opted.rpx INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2018.1/data/ip'. INFO: [DRC 23-27] Running DRC with 2 threads INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/lenovo/Desktop/T2Task4/encoder83/encoder83.runs/impl_1/encoder83_drc_opted.rpt. report_drc completed successfully report_drc: Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1104.590 ; gain = 33.492 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' INFO: [DRC 23-27] Running DRC with 2 threads INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design INFO: [DRC 23-27] Running DRC with 2 threads INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1104.590 ; gain = 0.000 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 163777304 Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.024 . Memory (MB): peak = 1104.590 ; gain = 0.000 Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1104.590 ; gain = 0.000 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 163777304 Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1115.883 ; gain = 11.293 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1f62c04f2 Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1115.883 ; gain = 11.293 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1f62c04f2 Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1115.883 ; gain = 11.293 Phase 1 Placer Initialization | Checksum: 1f62c04f2 Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1115.883 ; gain = 11.293 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1f62c04f2 Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1115.883 ; gain = 11.293 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: 163777304 Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1115.883 ; gain = 11.293 INFO: [Common 17-83] Releasing license: Implementation 40 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.109 . Memory (MB): peak = 1120.285 ; gain = 4.375 INFO: [Common 17-1381] The checkpoint 'C:/Users/lenovo/Desktop/T2Task4/encoder83/encoder83.runs/impl_1/encoder83_placed.dcp' has been generated. INFO: [runtcl-4] Executing : report_io -file encoder83_io_placed.rpt report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.126 . Memory (MB): peak = 1129.996 ; gain = 0.000 INFO: [runtcl-4] Executing : report_utilization -file encoder83_utilization_placed.rpt -pb encoder83_utilization_placed.pb report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.107 . Memory (MB): peak = 1129.996 ; gain = 0.000 INFO: [runtcl-4] Executing : report_control_sets -verbose -file encoder83_control_sets_placed.rpt report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 1129.996 ; gain = 0.000 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' Running DRC as a precondition to command route_design INFO: [DRC 23-27] Running DRC with 2 threads INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs Checksum: PlaceDB: 8a2781f4 ConstDB: 0 ShapeSum: d94ff110 RouteDB: 0 Phase 1 Build RT Design Phase 1 Build RT Design | Checksum: e21d7a74 Time (s): cpu = 00:01:09 ; elapsed = 00:01:08 . Memory (MB): peak = 1289.859 ; gain = 159.863 Post Restoration Checksum: NetGraph: a6f2c5c4 NumContArr: 3b2ab4b0 Constraints: 0 Timing: 0 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: e21d7a74 Time (s): cpu = 00:01:09 ; elapsed = 00:01:09 . Memory (MB): peak = 1296.094 ; gain = 166.098 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: e21d7a74 Time (s): cpu = 00:01:09 ; elapsed = 00:01:09 . Memory (MB): peak = 1296.094 ; gain = 166.098 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 14d4ff571 Time (s): cpu = 00:01:10 ; elapsed = 00:01:09 . Memory (MB): peak = 1300.703 ; gain = 170.707 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 14d4ff571 Time (s): cpu = 00:01:10 ; elapsed = 00:01:09 . Memory (MB): peak = 1300.703 ; gain = 170.707 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 14d4ff571 Time (s): cpu = 00:01:10 ; elapsed = 00:01:09 . Memory (MB): peak = 1300.703 ; gain = 170.707 Phase 4 Rip-up And Reroute | Checksum: 14d4ff571 Time (s): cpu = 00:01:10 ; elapsed = 00:01:09 . Memory (MB): peak = 1300.703 ; gain = 170.707 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 14d4ff571 Time (s): cpu = 00:01:10 ; elapsed = 00:01:09 . Memory (MB): peak = 1300.703 ; gain = 170.707 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 14d4ff571 Time (s): cpu = 00:01:10 ; elapsed = 00:01:09 . Memory (MB): peak = 1300.703 ; gain = 170.707 Phase 6 Post Hold Fix | Checksum: 14d4ff571 Time (s): cpu = 00:01:10 ; elapsed = 00:01:09 . Memory (MB): peak = 1300.703 ; gain = 170.707 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. ------------------------------ Reporting congestion hotspots ------------------------------ Direction: North ---------------- Congested clusters found at Level 0 Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 Direction: South ---------------- Congested clusters found at Level 0 Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 Direction: East ---------------- Congested clusters found at Level 0 Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 Direction: West ---------------- Congested clusters found at Level 0 Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 Phase 7 Route finalize | Checksum: 14d4ff571 Time (s): cpu = 00:01:10 ; elapsed = 00:01:09 . Memory (MB): peak = 1300.703 ; gain = 170.707 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 14d4ff571 Time (s): cpu = 00:01:10 ; elapsed = 00:01:09 . Memory (MB): peak = 1303.020 ; gain = 173.023 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 14d4ff571 Time (s): cpu = 00:01:10 ; elapsed = 00:01:09 . Memory (MB): peak = 1303.020 ; gain = 173.023 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:01:10 ; elapsed = 00:01:09 . Memory (MB): peak = 1303.020 ; gain = 173.023 Routing Is Done. INFO: [Common 17-83] Releasing license: Implementation 53 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:01:11 ; elapsed = 00:01:10 . Memory (MB): peak = 1303.020 ; gain = 173.023 INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.067 . Memory (MB): peak = 1303.020 ; gain = 0.000 INFO: [Common 17-1381] The checkpoint 'C:/Users/lenovo/Desktop/T2Task4/encoder83/encoder83.runs/impl_1/encoder83_routed.dcp' has been generated. INFO: [runtcl-4] Executing : report_drc -file encoder83_drc_routed.rpt -pb encoder83_drc_routed.pb -rpx encoder83_drc_routed.rpx Command: report_drc -file encoder83_drc_routed.rpt -pb encoder83_drc_routed.pb -rpx encoder83_drc_routed.rpx INFO: [DRC 23-27] Running DRC with 2 threads INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/lenovo/Desktop/T2Task4/encoder83/encoder83.runs/impl_1/encoder83_drc_routed.rpt. report_drc completed successfully INFO: [runtcl-4] Executing : report_methodology -file encoder83_methodology_drc_routed.rpt -pb encoder83_methodology_drc_routed.pb -rpx encoder83_methodology_drc_routed.rpx Command: report_methodology -file encoder83_methodology_drc_routed.rpt -pb encoder83_methodology_drc_routed.pb -rpx encoder83_methodology_drc_routed.rpx INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [DRC 23-133] Running Methodology with 2 threads INFO: [Coretcl 2-1520] The results of Report Methodology are in file C:/Users/lenovo/Desktop/T2Task4/encoder83/encoder83.runs/impl_1/encoder83_methodology_drc_routed.rpt. report_methodology completed successfully INFO: [runtcl-4] Executing : report_power -file encoder83_power_routed.rpt -pb encoder83_power_summary_routed.pb -rpx encoder83_power_routed.rpx Command: report_power -file encoder83_power_routed.rpt -pb encoder83_power_summary_routed.pb -rpx encoder83_power_routed.rpx WARNING: [Power 33-232] No user defined clocks were found in the design! Resolution: Please specify clocks using create_clock/create_generated_clock for sequential elements. For pure combinatorial circuits, please specify a virtual clock, otherwise the vectorless estimation might be inaccurate INFO: [Timing 38-35] Done setting XDC timing constraints. Running Vector-less Activity Propagation... Finished Running Vector-less Activity Propagation 65 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. report_power completed successfully INFO: [runtcl-4] Executing : report_route_status -file encoder83_route_status.rpt -pb encoder83_route_status.pb INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file encoder83_timing_summary_routed.rpt -pb encoder83_timing_summary_routed.pb -rpx encoder83_timing_summary_routed.rpx -warn_on_violation INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max, Timing Stage: Requireds. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis. INFO: [runtcl-4] Executing : report_incremental_reuse -file encoder83_incremental_reuse_routed.rpt INFO: [Vivado_Tcl 4-545] No incremental reuse to report, no incremental placement and routing data was found. INFO: [runtcl-4] Executing : report_clock_utilization -file encoder83_clock_utilization_routed.rpt INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file route_report_bus_skew_0.rpt -rpx route_report_bus_skew_0.rpx INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max, Timing Stage: Requireds. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs INFO: [Common 17-206] Exiting Vivado at Wed Sep 9 19:52:55 2020... *** Running vivado with args -log encoder83.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source encoder83.tcl -notrace ****** Vivado v2018.1 (64-bit) **** SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 **** IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 ** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. source encoder83.tcl -notrace Command: open_checkpoint encoder83_routed.dcp Starting open_checkpoint Task Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.090 . Memory (MB): peak = 233.242 ; gain = 0.000 INFO: [Project 1-479] Netlist was created with Vivado 2018.1 INFO: [Device 21-403] Loading part xc7a100tcsg324-1 INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Timing 38-478] Restoring timing data from binary archive. INFO: [Timing 38-479] Binary timing data restore complete. INFO: [Project 1-856] Restoring constraints from binary archive. INFO: [Project 1-853] Binary constraint restore complete. Reading XDEF placement. Reading placer database... Reading XDEF routing. Read XDEF File: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.437 . Memory (MB): peak = 1080.637 ; gain = 0.000 Restored from archive | CPU: 0.000000 secs | Memory: 0.000000 MB | Finished XDEF File Restore: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.440 . Memory (MB): peak = 1080.637 ; gain = 0.000 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. INFO: [Project 1-604] Checkpoint was created with Vivado v2018.1 (64-bit) build 2188600 open_checkpoint: Time (s): cpu = 00:00:43 ; elapsed = 00:00:55 . Memory (MB): peak = 1080.637 ; gain = 850.379 Command: write_bitstream -force encoder83.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' Running DRC as a precondition to command write_bitstream INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2018.1/data/ip'. INFO: [DRC 23-27] Running DRC with 2 threads WARNING: [DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: set_property CFGBVS value1 [current_design] #where value1 is either VCCO or GND set_property CONFIG_VOLTAGE value2 [current_design] #where value2 is the voltage provided to configuration bank 0 Refer to the device configuration user guide for more information. INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Designutils 20-2272] Running write_bitstream with 2 threads. Loading data files... Loading site data... Loading route data... Processing options... Creating bitmap... Creating bitstream... Writing bitstream ./encoder83.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Common 17-83] Releasing license: Implementation 20 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:47 ; elapsed = 00:00:54 . Memory (MB): peak = 1567.039 ; gain = 486.402 INFO: [Common 17-206] Exiting Vivado at Wed Sep 9 19:55:19 2020...