Device Usage Statistics Report

Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
To see the actual file transmitted to Xilinx, please click here.

software_version_and_target_device
beta	FALSE	build_version	2188600
date_generated	Wed Sep 9 19:55:16 2020	os_platform	WIN64
product_version	Vivado v2018.1 (64-bit)	project_id	872ee29657ef43efa5c8348537e96987
project_iteration	2	random_id	2fb59037-c7d4-4fac-bd5e-c45ffaec0ee3
registration_id	2fb59037-c7d4-4fac-bd5e-c45ffaec0ee3	route_design	TRUE
target_device	xc7a100t	target_family	artix7
target_package	csg324	target_speed	-1
tool_flow	Vivado

user_environment
cpu_name	Intel(R) Core(TM) i5-7200U CPU @ 2.50GHz	cpu_speed	2712 MHz
os_name	Microsoft Windows 8 or later , 64-bit	os_release	major release (build 9200)
system_ram	8.000 GB	total_processors	1

vivado_usage

gui_handlers
addsrcwizard_specify_or_create_constraint_files=1	addsrcwizard_specify_simulation_specific_hdl_files=1	basedialog_cancel=3	basedialog_close=2
basedialog_ok=15	basedialog_yes=2	boardchooser_board_table=1	cmdmsgdialog_ok=1
constraintschooserpanel_create_file=1	createconstraintsfilepanel_file_name=1	createsrcfiledialog_file_name=2	definemodulesdialog_define_modules_and_specify_io_ports=14
filesetpanel_file_set_panel_tree=21	flownavigatortreepanel_flow_navigator_tree=18	gettingstartedview_create_new_project=1	hardwaretreepanel_hardware_tree_table=4
hcodeeditor_search_text_combo_box=2	languagetemplatesdialog_templates_tree=29	numjobschooser_number_of_jobs=3	pacommandnames_add_sources=2
pacommandnames_auto_connect_target=2	pacommandnames_language_templates=4	pacommandnames_run_bitgen=2	pacommandnames_simulation_run_behavioral=5
programdebugtab_program_device=4	programdebugtab_refresh_device=3	programfpgadialog_program=3	projectnamechooser_choose_project_location=1
projectnamechooser_project_name=1	rdicommands_line_comment=1	rdicommands_save_file=2	rdiviews_waveform_viewer=25
saveprojectutils_save=2	simulationobjectspanel_simulation_objects_tree_table=5	srcchooserpanel_create_file=2	stalemoreaction_out_of_date_details=1
syntheticastatemonitor_cancel=1	taskbanner_close=3	tclconsoleview_tcl_console_code_editor=16	waveformnametree_waveform_name_tree=7

java_command_handlers
addsources=2	autoconnecttarget=2	launchprogramfpga=4	newproject=1
openhardwaremanager=3	openrecenttarget=5	refreshdevice=2	runbitgen=3
runimplementation=4	savefileproxyhandler=1	simulationrun=5	toolstemplates=4

other_data
guimode=1

project_data
constraintsetcount=1	core_container=false	currentimplrun=impl_1	currentsynthesisrun=synth_1
default_library=xil_defaultlib	designmode=RTL	export_simulation_activehdl=0	export_simulation_ies=0
export_simulation_modelsim=0	export_simulation_questa=0	export_simulation_riviera=0	export_simulation_vcs=0
export_simulation_xsim=0	implstrategy=Vivado Implementation Defaults	launch_simulation_activehdl=0	launch_simulation_ies=0
launch_simulation_modelsim=0	launch_simulation_questa=0	launch_simulation_riviera=0	launch_simulation_vcs=0
launch_simulation_xsim=4	simulator_language=Mixed	srcsetcount=1	synthesisstrategy=Vivado Synthesis Defaults
target_language=Verilog	target_simulator=XSim	totalimplruns=1	totalsynthesisruns=1

unisim_transformation

post_unisim_transformation
gnd=1	obuf=3

pre_unisim_transformation
gnd=1	obuf=3

report_drc

command_line_options
-append=default::[not_specified]	-checks=default::[not_specified]	-fail_on=default::[not_specified]	-force=default::[not_specified]
-format=default::[not_specified]	-internal=default::[not_specified]	-internal_only=default::[not_specified]	-messages=default::[not_specified]
-name=default::[not_specified]	-no_waivers=default::[not_specified]	-return_string=default::[not_specified]	-ruledecks=default::[not_specified]
-upgrade_cw=default::[not_specified]	-waived=default::[not_specified]

results
cfgbvs-1=1

report_utilization

clocking
bufgctrl_available=32	bufgctrl_fixed=0	bufgctrl_used=0	bufgctrl_util_percentage=0.00
bufhce_available=96	bufhce_fixed=0	bufhce_used=0	bufhce_util_percentage=0.00
bufio_available=24	bufio_fixed=0	bufio_used=0	bufio_util_percentage=0.00
bufmrce_available=12	bufmrce_fixed=0	bufmrce_used=0	bufmrce_util_percentage=0.00
bufr_available=24	bufr_fixed=0	bufr_used=0	bufr_util_percentage=0.00
mmcme2_adv_available=6	mmcme2_adv_fixed=0	mmcme2_adv_used=0	mmcme2_adv_util_percentage=0.00
plle2_adv_available=6	plle2_adv_fixed=0	plle2_adv_used=0	plle2_adv_util_percentage=0.00

dsp
dsps_available=240	dsps_fixed=0	dsps_used=0	dsps_util_percentage=0.00

io_standard
blvds_25=0	diff_hstl_i=0	diff_hstl_i_18=0	diff_hstl_ii=0
diff_hstl_ii_18=0	diff_hsul_12=0	diff_mobile_ddr=0	diff_sstl135=0
diff_sstl135_r=0	diff_sstl15=0	diff_sstl15_r=0	diff_sstl18_i=0
diff_sstl18_ii=0	hstl_i=0	hstl_i_18=0	hstl_ii=0
hstl_ii_18=0	hsul_12=0	lvcmos12=0	lvcmos15=0
lvcmos18=0	lvcmos25=0	lvcmos33=1	lvds_25=0
lvttl=0	mini_lvds_25=0	mobile_ddr=0	pci33_3=0
ppds_25=0	rsds_25=0	sstl135=0	sstl135_r=0
sstl15=0	sstl15_r=0	sstl18_i=0	sstl18_ii=0
tmds_33=0

memory
block_ram_tile_available=135	block_ram_tile_fixed=0	block_ram_tile_used=0	block_ram_tile_util_percentage=0.00
ramb18_available=270	ramb18_fixed=0	ramb18_used=0	ramb18_util_percentage=0.00
ramb36_fifo_available=135	ramb36_fifo_fixed=0	ramb36_fifo_used=0	ramb36_fifo_util_percentage=0.00

primitives
obuf_functional_category=IO	obuf_used=3

slice_logic
f7_muxes_available=31700	f7_muxes_fixed=0	f7_muxes_used=0	f7_muxes_util_percentage=0.00
f8_muxes_available=15850	f8_muxes_fixed=0	f8_muxes_used=0	f8_muxes_util_percentage=0.00
lut_as_logic_available=63400	lut_as_logic_fixed=0	lut_as_logic_used=0	lut_as_logic_util_percentage=0.00
lut_as_memory_available=19000	lut_as_memory_fixed=0	lut_as_memory_used=0	lut_as_memory_util_percentage=0.00
register_as_flip_flop_available=126800	register_as_flip_flop_fixed=0	register_as_flip_flop_used=0	register_as_flip_flop_util_percentage=0.00
register_as_latch_available=126800	register_as_latch_fixed=0	register_as_latch_used=0	register_as_latch_util_percentage=0.00
slice_luts_available=63400	slice_luts_fixed=0	slice_luts_used=0	slice_luts_util_percentage=0.00
slice_registers_available=126800	slice_registers_fixed=0	slice_registers_used=0	slice_registers_util_percentage=0.00
lut_as_distributed_ram_fixed=0	lut_as_distributed_ram_used=0	lut_as_logic_available=63400	lut_as_logic_fixed=0
lut_as_logic_used=0	lut_as_logic_util_percentage=0.00	lut_as_memory_available=19000	lut_as_memory_fixed=0
lut_as_memory_used=0	lut_as_memory_util_percentage=0.00	lut_as_shift_register_fixed=0	lut_as_shift_register_used=0
lut_flip_flop_pairs_available=63400	lut_flip_flop_pairs_fixed=0	lut_flip_flop_pairs_used=0	lut_flip_flop_pairs_util_percentage=0.00
slice_available=15850	slice_fixed=0	slice_used=0	slice_util_percentage=0.00
slicel_fixed=0	slicel_used=0	slicem_fixed=0	slicem_used=0
unique_control_sets_used=0

specific_feature
bscane2_available=4	bscane2_fixed=0	bscane2_used=0	bscane2_util_percentage=0.00
capturee2_available=1	capturee2_fixed=0	capturee2_used=0	capturee2_util_percentage=0.00
dna_port_available=1	dna_port_fixed=0	dna_port_used=0	dna_port_util_percentage=0.00
efuse_usr_available=1	efuse_usr_fixed=0	efuse_usr_used=0	efuse_usr_util_percentage=0.00
frame_ecce2_available=1	frame_ecce2_fixed=0	frame_ecce2_used=0	frame_ecce2_util_percentage=0.00
icape2_available=2	icape2_fixed=0	icape2_used=0	icape2_util_percentage=0.00
pcie_2_1_available=1	pcie_2_1_fixed=0	pcie_2_1_used=0	pcie_2_1_util_percentage=0.00
startupe2_available=1	startupe2_fixed=0	startupe2_used=0	startupe2_util_percentage=0.00
xadc_available=1	xadc_fixed=0	xadc_used=0	xadc_util_percentage=0.00

router

usage
actual_expansions=27	bogomips=0	bram18=0	bram36=0
bufg=0	bufr=0	ctrls=0	dsp=0
effort=2	estimated_expansions=0	ff=0	global_clocks=0
high_fanout_nets=0	iob=3	lut=0	movable_instances=4
nets=4	pins=7	pll=0	router_runtime=1.000000
router_timing_driven=1	threads=2	timing_constraints_exist=1

synthesis

command_line_options
-assert=default::[not_specified]	-bufg=default::12	-cascade_dsp=default::auto	-constrset=default::[not_specified]
-control_set_opt_threshold=default::auto	-directive=default::default	-fanout_limit=default::10000	-flatten_hierarchy=default::rebuilt
-fsm_extraction=default::auto	-gated_clock_conversion=default::off	-generic=default::[not_specified]	-include_dirs=default::[not_specified]
-keep_equivalent_registers=default::[not_specified]	-max_bram=default::-1	-max_bram_cascade_height=default::-1	-max_dsp=default::-1
-max_uram=default::-1	-max_uram_cascade_height=default::-1	-mode=default::default	-name=default::[not_specified]
-no_lc=default::[not_specified]	-no_srlextract=default::[not_specified]	-no_timing_driven=default::[not_specified]	-part=xc7a100tcsg324-1
-resource_sharing=default::auto	-retiming=default::[not_specified]	-rtl=default::[not_specified]	-rtl_skip_constraints=default::[not_specified]
-rtl_skip_ip=default::[not_specified]	-seu_protect=default::none	-sfcu=default::[not_specified]	-shreg_min_size=default::3
-top=encoder83	-verilog_define=default::[not_specified]

usage
elapsed=00:01:43s	hls_ip=0	memory_gain=480.535MB	memory_peak=727.625MB

xsim

command_line_options
-sim_mode=default::behavioral	-sim_type=default::