{
  "$schema": "https://agent-plugins.org/schemas/1.0.0/plugin.schema.json",
  "name": "hdl-rtl",
  "version": "0.1.0",
  "description": "ASIC HDL skills: Verilog/SystemVerilog format, synthesizable DUT constraints, TESTBED/PATTERN generation, flow environment setup, preflight check before VCS/DC, and opt-in RTL timing local rewrites.",
  "author": {
    "name": "Marco",
    "email": "harry2963753@gmail.com"
  },
  "license": "MIT",
  "keywords": ["verilog", "systemverilog", "rtl", "asic", "dv", "testbench"]
}