#!/usr/bin/env python3
import sys
import struct
import xml.etree.ElementTree as ET

import sys
import binascii
 
class SigmadDSPFirmwareGen(object):

	CHUNK_TYPE_DATA = 0
	CHUNK_TYPE_CONTROL = 1
	CHUNK_TYPE_SAMPLERATES = 2

	CHUNK_HEADER_SIZE = 12
	CHUNK_DATA_HEADER_SIZE = CHUNK_HEADER_SIZE + 2
	CHUNK_CONTROL_HEADER_SIZE = CHUNK_HEADER_SIZE + 6

	def __init__(self, in_files, out_file):
		self.crcsum = 0xffffffff
		self.size = 12

		self.data_chunks = []
		self.control_chunks = []
		self.controls = {}

		samplerates = []
		samplerate_mask = 1

		for samplerate, in_file in in_files:
			samplerates.append(samplerate)
			self.parse_input_file(in_file, samplerate_mask, samplerate)
			samplerate_mask <<= 1

		ok = True
		for chunk in self.control_chunks:
			ok = ok & self.validate_control_chunk(chunk)
		ok |= self.merge_control_chunks()

		if not ok:
			return

		self.out = open(out_file, "wb")

		self.out.write(b"ADISIGM")
		self.out.write(struct.pack("<BI", 2, 0x0000)) # checksum, will be overwritten latter

		self.write_samplerates_chunk(samplerates)
		for chunk in self.data_chunks:
			self.write_data_chunk(chunk)
		for chunk in self.control_chunks:
			self.write_control_chunk(chunk)

		self.out.seek(8)
		# binascii.crc32() inverts the bits interally here we intert it back
		self.crcsum ^= 0xffffffff
		self.out.write(struct.pack('<I', self.crcsum))
		self.out.close()

	def parse_input_file(self, filename, samplerate_mask, samplerate):
		tree = ET.parse(filename)
	
		for child in tree.getroot().iter("Program"):
			name = child.find("Name").text
			if name != "Program Data":
				continue
			self.add_data_chunk(child, samplerate_mask)

		for child in tree.getroot().iter("Register"):
			name = child.find("Name").text
			if name == "Non Modulo RAM":
				print("WARNING: Non modulo RAM currently not supported. Design might not work correctly.")
				continue
			if name != "Param":
				continue
			self.add_data_chunk(child, samplerate_mask)

		for child in tree.getroot().iter("Module"):
			name = child.find("CellName").text
			for para in child.iter("ModuleParameter"):
				self.add_control_chunk(para, name, samplerate_mask)

	def write(self, data):
		self.out.write(data)
		self.crcsum = binascii.crc32(data, self.crcsum)
		self.size += len(data)

	def write_chunk_header(self, size, type, samplerate_mask):
		# The start of a chunk is 4bytes aligned
		padding = ((self.size + 3) & ~3) - self.size
		for i in range(0, padding):
			self.write(b"\xaa")
		self.write(struct.pack("<III", size, type, samplerate_mask))

	def add_data_chunk(self, node, samplerate_mask):
		addr = int(node.find("Address").text, 0)
		size = int(node.find("Size").text)

		data = node.find("Data").text
		data = bytes([int(x.strip(), 16) for x in data.split(",") if x.strip()])

		self.data_chunks.append((addr, size, data, samplerate_mask))

	def write_data_chunk(self, data_chunk):
		addr, size, data, samplerate_mask = data_chunk

		size += self.CHUNK_DATA_HEADER_SIZE

		self.write_chunk_header(size, self.CHUNK_TYPE_DATA, samplerate_mask)
		self.write(struct.pack("<H", addr))
		self.write(data)	

	def add_control_chunk(self, node, name, samplerate_mask):
		pname = node.find("Name").text
		addr = int(node.find("Address").text, 0)
		length = int(node.find("Size").text)

		self.control_chunks.append((name, pname, addr, length, samplerate_mask))

	def validate_control_chunk(self, control_chunk):
		name, pname, addr, length, samplerate_mask = control_chunk
		ok = True

		full_name = "%s %s" % (name, pname)
		if len(full_name) > 43:
			print("ERROR: Control name '%s' is to long. Maximum length is 43 characters" % full_name)
			ok = False

		key = (full_name, samplerate_mask)

		if key in self.controls:
			# SigmaStudio sometimes generates multiple controls that are 100%
			# identical, only generate an error if there are multiple controls
			# with the same name, but having different addresses or lengths
			if self.controls[key] != control_chunk:
				print("ERROR: Duplicated control name '%s'" % full_name)
				ok = False
		else:
			self.controls[key] = control_chunk

		return ok

	def merge_control_chunks(self):
		new_chunks = {}
		ok = True

		for chunk in self.control_chunks:
			name, pname, addr, length, samplerate_mask = chunk
			full_name = "%s %s" % (name, pname)
			if full_name in new_chunks.keys():
				other_addr, other_length, other_samplerate_mask = new_chunks[full_name][2:5]
				if (other_addr != addr or other_length != length) and \
				   (samplerate_mask & other_samplerate_mask) == 0:
					print("ERROR: Controls with the same name for different samplerates need the same address and length. Mismatch for control {} ({}, {}) != ({}, {})".format(
						full_name, other_addr, other_length, addr, length))
					ok = False

				new_chunks[full_name][4] |= samplerate_mask
			else:
				new_chunks[full_name] = [name, pname, addr, length, samplerate_mask]

		self.control_chunks = [tuple(x) for x in new_chunks.values()]

		return ok

	def write_control_chunk(self, control_chunk):
		name, pname, addr, length, samplerate_mask = control_chunk

		name_len = len("%s %s" % (name, pname))
		size = self.CHUNK_CONTROL_HEADER_SIZE + name_len

		self.write_chunk_header(size, self.CHUNK_TYPE_CONTROL, samplerate_mask)
		self.write(struct.pack("<HHH", 0, addr, length))
		self.write(bytearray("%s %s" % (name, pname), "ascii"))

	def write_samplerates_chunk(self, samplerates):
		size = self.CHUNK_HEADER_SIZE + len(samplerates) * 4
		self.write_chunk_header(size, self.CHUNK_TYPE_SAMPLERATES, 0)
		for samplerate in samplerates:
			self.write(struct.pack("<I", samplerate))

if __name__ == "__main__":
	if len(sys.argv) % 2 != 0 or len(sys.argv) < 4:
		print("Usage {0}: <xml file> <samplerate> [<xml file> <samplerate>] <output file>".format(sys.argv[0]))
		sys.exit(1)

	in_files = {}
	for i in range(1, len(sys.argv) - 2, 2):
		rate = int(sys.argv[i+1])
		if rate in in_files.keys():
			print("ERROR: Duplicated samplerate {}".format(rate))
			sys.exit(1)
		in_files[rate] = sys.argv[i]

	SigmadDSPFirmwareGen(in_files.items(), sys.argv[-1])