Atmel Corporation ATMEL ATSAMD21G18A SAMD21 A Atmel ATSAMD21G18A device: Cortex-M0+ Microcontroller with 256KB Flash, 32KB SRAM, 48-pin package (refer to http://www.atmel.com/devices/SAMD21G18A.aspx for more) ============================================================================\n Atmel Microcontroller Software Support\n ============================================================================\n Copyright (c) 2014, Atmel Corporation\n \n All rights reserved.\n \n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following condition is met:\n \n - Redistributions of source code must retain the above copyright notice,\n this list of conditions and the disclaimer below.\n \n Atmel's name may not be used to endorse or promote products derived from\n this software without specific prior written permission.\n \n DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\n IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\n MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\n DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\n INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\n OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\n LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\n NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\n EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n ============================================================================ CM0+ r0p1 little false false true 2 false system_samd21 8 32 32 read-write 0x00000000 0xFFFFFFFF AC 1.1.1 Analog Comparators AC AC_ 0x42004400 0 0x40 registers AC 24 2 0x4 COMPCTRL%s Comparator Control n 0x10 32 ENABLE Enable 0 1 SINGLE Single-Shot Mode 1 1 SPEED Speed Selection 2 2 SPEEDSelect LOW Low speed 0x0 HIGH High speed 0x1 INTSEL Interrupt Selection 5 2 INTSELSelect TOGGLE Interrupt on comparator output toggle 0x0 RISING Interrupt on comparator output rising 0x1 FALLING Interrupt on comparator output falling 0x2 EOC Interrupt on end of comparison (single-shot mode only) 0x3 MUXNEG Negative Input Mux Selection 8 3 MUXNEGSelect PIN0 I/O pin 0 0x0 PIN1 I/O pin 1 0x1 PIN2 I/O pin 2 0x2 PIN3 I/O pin 3 0x3 GND Ground 0x4 VSCALE VDD scaler 0x5 BANDGAP Internal bandgap voltage 0x6 DAC DAC output 0x7 MUXPOS Positive Input Mux Selection 12 2 MUXPOSSelect PIN0 I/O pin 0 0x0 PIN1 I/O pin 1 0x1 PIN2 I/O pin 2 0x2 PIN3 I/O pin 3 0x3 SWAP Swap Inputs and Invert 15 1 OUT Output 16 2 OUTSelect OFF The output of COMPn is not routed to the COMPn I/O port 0x0 ASYNC The asynchronous output of COMPn is routed to the COMPn I/O port 0x1 SYNC The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port 0x2 HYST Hysteresis Enable 19 1 FLEN Filter Length 24 3 FLENSelect OFF No filtering 0x0 MAJ3 3-bit majority function (2 of 3) 0x1 MAJ5 5-bit majority function (3 of 5) 0x2 CTRLA Control A 0x00 8 SWRST Software Reset 0 1 write-only ENABLE Enable 1 1 RUNSTDBY Run in Standby 2 1 LPMUX Low-Power Mux 7 1 CTRLB Control B 0x01 8 write-only START0 Comparator 0 Start Comparison 0 1 START1 Comparator 1 Start Comparison 1 1 EVCTRL Event Control 0x02 16 COMPEO0 Comparator 0 Event Output Enable 0 1 COMPEO1 Comparator 1 Event Output Enable 1 1 WINEO0 Window 0 Event Output Enable 4 1 COMPEI0 Comparator 0 Event Input 8 1 COMPEI1 Comparator 1 Event Input 9 1 INTENCLR Interrupt Enable Clear 0x04 8 COMP0 Comparator 0 Interrupt Enable 0 1 COMP1 Comparator 1 Interrupt Enable 1 1 WIN0 Window 0 Interrupt Enable 4 1 INTENSET Interrupt Enable Set 0x05 8 COMP0 Comparator 0 Interrupt Enable 0 1 COMP1 Comparator 1 Interrupt Enable 1 1 WIN0 Window 0 Interrupt Enable 4 1 INTFLAG Interrupt Flag Status and Clear 0x06 8 COMP0 Comparator 0 0 1 COMP1 Comparator 1 1 1 WIN0 Window 0 4 1 2 0x1 SCALER%s Scaler n 0x20 8 VALUE Scaler Value 0 6 STATUSA Status A 0x08 8 read-only STATE0 Comparator 0 Current State 0 1 STATE1 Comparator 1 Current State 1 1 WSTATE0 Window 0 Current State 4 2 WSTATE0Select ABOVE Signal is above window 0x0 INSIDE Signal is inside window 0x1 BELOW Signal is below window 0x2 STATUSB Status B 0x09 8 read-only READY0 Comparator 0 Ready 0 1 read-only READY1 Comparator 1 Ready 1 1 read-only SYNCBUSY Synchronization Busy 7 1 STATUSC Status C 0x0A 8 read-only STATE0 Comparator 0 Current State 0 1 STATE1 Comparator 1 Current State 1 1 WSTATE0 Window 0 Current State 4 2 WSTATE0Select ABOVE Signal is above window 0x0 INSIDE Signal is inside window 0x1 BELOW Signal is below window 0x2 WINCTRL Window Control 0x0C 8 WEN0 Window 0 Mode Enable 0 1 WINTSEL0 Window 0 Interrupt Selection 1 2 WINTSEL0Select ABOVE Interrupt on signal above window 0x0 INSIDE Interrupt on signal inside window 0x1 BELOW Interrupt on signal below window 0x2 OUTSIDE Interrupt on signal outside window 0x3 ADC 1.2.0 Analog Digital Converter ADC ADC_ 0x42004000 0 0x80 registers ADC 23 AVGCTRL Average Control 0x02 8 SAMPLENUM Number of Samples to be Collected 0 4 SAMPLENUMSelect 1 1 sample 0x0 2 2 samples 0x1 4 4 samples 0x2 8 8 samples 0x3 16 16 samples 0x4 32 32 samples 0x5 64 64 samples 0x6 128 128 samples 0x7 256 256 samples 0x8 512 512 samples 0x9 1024 1024 samples 0xa ADJRES Adjusting Result / Division Coefficient 4 3 CALIB Calibration 0x28 16 LINEARITY_CAL Linearity Calibration Value 0 8 BIAS_CAL Bias Calibration Value 8 3 CTRLA Control A 0x00 8 SWRST Software Reset 0 1 ENABLE Enable 1 1 RUNSTDBY Run in Standby 2 1 CTRLB Control B 0x04 16 DIFFMODE Differential Mode 0 1 LEFTADJ Left-Adjusted Result 1 1 FREERUN Free Running Mode 2 1 CORREN Digital Correction Logic Enabled 3 1 RESSEL Conversion Result Resolution 4 2 RESSELSelect 12BIT 12-bit result 0x0 16BIT For averaging mode output 0x1 10BIT 10-bit result 0x2 8BIT 8-bit result 0x3 PRESCALER Prescaler Configuration 8 3 PRESCALERSelect DIV4 Peripheral clock divided by 4 0x0 DIV8 Peripheral clock divided by 8 0x1 DIV16 Peripheral clock divided by 16 0x2 DIV32 Peripheral clock divided by 32 0x3 DIV64 Peripheral clock divided by 64 0x4 DIV128 Peripheral clock divided by 128 0x5 DIV256 Peripheral clock divided by 256 0x6 DIV512 Peripheral clock divided by 512 0x7 DBGCTRL Debug Control 0x2A 8 DBGRUN Debug Run 0 1 EVCTRL Event Control 0x14 8 STARTEI Start Conversion Event In 0 1 SYNCEI Synchronization Event In 1 1 RESRDYEO Result Ready Event Out 4 1 WINMONEO Window Monitor Event Out 5 1 GAINCORR Gain Correction 0x24 16 GAINCORR Gain Correction Value 0 12 INPUTCTRL Input Control 0x10 32 MUXPOS Positive Mux Input Selection 0 5 MUXPOSSelect PIN0 ADC AIN0 Pin 0x0 PIN1 ADC AIN1 Pin 0x1 PIN2 ADC AIN2 Pin 0x2 PIN3 ADC AIN3 Pin 0x3 PIN4 ADC AIN4 Pin 0x4 PIN5 ADC AIN5 Pin 0x5 PIN6 ADC AIN6 Pin 0x6 PIN7 ADC AIN7 Pin 0x7 PIN8 ADC AIN8 Pin 0x8 PIN9 ADC AIN9 Pin 0x9 PIN10 ADC AIN10 Pin 0xa PIN11 ADC AIN11 Pin 0xb PIN12 ADC AIN12 Pin 0xc PIN13 ADC AIN13 Pin 0xd PIN14 ADC AIN14 Pin 0xe PIN15 ADC AIN15 Pin 0xf PIN16 ADC AIN16 Pin 0x10 PIN17 ADC AIN17 Pin 0x11 PIN18 ADC AIN18 Pin 0x12 PIN19 ADC AIN19 Pin 0x13 TEMP Temperature Reference 0x18 BANDGAP Bandgap Voltage 0x19 SCALEDCOREVCC 1/4 Scaled Core Supply 0x1a SCALEDIOVCC 1/4 Scaled I/O Supply 0x1b DAC DAC Output 0x1c MUXNEG Negative Mux Input Selection 8 5 MUXNEGSelect PIN0 ADC AIN0 Pin 0x0 PIN1 ADC AIN1 Pin 0x1 PIN2 ADC AIN2 Pin 0x2 PIN3 ADC AIN3 Pin 0x3 PIN4 ADC AIN4 Pin 0x4 PIN5 ADC AIN5 Pin 0x5 PIN6 ADC AIN6 Pin 0x6 PIN7 ADC AIN7 Pin 0x7 GND Internal Ground 0x18 IOGND I/O Ground 0x19 INPUTSCAN Number of Input Channels Included in Scan 16 4 INPUTOFFSET Positive Mux Setting Offset 20 4 GAIN Gain Factor Selection 24 4 GAINSelect 1X 1x 0x0 2X 2x 0x1 4X 4x 0x2 8X 8x 0x3 16X 16x 0x4 DIV2 1/2x 0xf INTENCLR Interrupt Enable Clear 0x16 8 RESRDY Result Ready Interrupt Enable 0 1 OVERRUN Overrun Interrupt Enable 1 1 WINMON Window Monitor Interrupt Enable 2 1 SYNCRDY Synchronization Ready Interrupt Enable 3 1 INTENSET Interrupt Enable Set 0x17 8 RESRDY Result Ready Interrupt Enable 0 1 OVERRUN Overrun Interrupt Enable 1 1 WINMON Window Monitor Interrupt Enable 2 1 SYNCRDY Synchronization Ready Interrupt Enable 3 1 INTFLAG Interrupt Flag Status and Clear 0x18 8 RESRDY Result Ready 0 1 OVERRUN Overrun 1 1 WINMON Window Monitor 2 1 SYNCRDY Synchronization Ready 3 1 OFFSETCORR Offset Correction 0x26 16 OFFSETCORR Offset Correction Value 0 12 REFCTRL Reference Control 0x01 8 REFSEL Reference Selection 0 4 REFSELSelect INT1V 1.0V voltage reference 0x0 INTVCC0 1/1.48 VDDANA 0x1 INTVCC1 1/2 VDDANA (only for VDDANA > 2.0V) 0x2 AREFA External reference 0x3 AREFB External reference 0x4 REFCOMP Reference Buffer Offset Compensation Enable 7 1 RESULT Result 0x1A 16 read-only RESULT Result Conversion Value 0 16 read-only SAMPCTRL Sampling Time Control 0x03 8 SAMPLEN Sampling Time Length 0 6 STATUS Status 0x19 8 read-only SYNCBUSY Synchronization Busy 7 1 read-only SWTRIG Software Trigger 0x0C 8 FLUSH ADC Conversion Flush 0 1 START ADC Start Conversion 1 1 WINCTRL Window Monitor Control 0x08 8 WINMODE Window Monitor Mode 0 3 WINMODESelect DISABLE No window mode (default) 0x0 MODE1 Mode 1: RESULT > WINLT 0x1 MODE2 Mode 2: RESULT < WINUT 0x2 MODE3 Mode 3: WINLT < RESULT < WINUT 0x3 MODE4 Mode 4: !(WINLT < RESULT < WINUT) 0x4 WINLT Window Monitor Lower Threshold 0x1C 16 WINLT Window Lower Threshold 0 16 WINUT Window Monitor Upper Threshold 0x20 16 WINUT Window Upper Threshold 0 16 DAC 1.1.0 Digital Analog Converter DAC DAC_ 0x42004800 0 0x10 registers DAC 25 CTRLA Control A 0x0 8 SWRST Software Reset 0 1 ENABLE Enable 1 1 RUNSTDBY Run in Standby 2 1 CTRLB Control B 0x1 8 EOEN External Output Enable 0 1 IOEN Internal Output Enable 1 1 LEFTADJ Left Adjusted Data 2 1 VPD Voltage Pump Disable 3 1 BDWP Bypass DATABUF Write Protection 4 1 REFSEL Reference Selection 6 2 REFSELSelect INT1V Internal 1.0V reference 0x0 AVCC AVCC 0x1 VREFP External reference 0x2 DATA Data 0x8 16 DATA Data value to be converted 0 16 DATABUF Data Buffer 0xC 16 DATABUF Data Buffer 0 16 EVCTRL Event Control 0x2 8 STARTEI Start Conversion Event Input 0 1 EMPTYEO Data Buffer Empty Event Output 1 1 INTENCLR Interrupt Enable Clear 0x4 8 UNDERRUN Underrun Interrupt Enable 0 1 EMPTY Data Buffer Empty Interrupt Enable 1 1 SYNCRDY Synchronization Ready Interrupt Enable 2 1 INTENSET Interrupt Enable Set 0x5 8 UNDERRUN Underrun Interrupt Enable 0 1 EMPTY Data Buffer Empty Interrupt Enable 1 1 SYNCRDY Synchronization Ready Interrupt Enable 2 1 INTFLAG Interrupt Flag Status and Clear 0x6 8 UNDERRUN Underrun 0 1 EMPTY Data Buffer Empty 1 1 SYNCRDY Synchronization Ready 2 1 STATUS Status 0x7 8 read-only SYNCBUSY Synchronization Busy Status 7 1 read-only DMAC 1.0.0 Direct Memory Access Controller DMAC DMAC_ 0x41004800 0 0x80 registers DMAC 6 ACTIVE Active Channel and Levels 0x30 32 read-only LVLEX0 Level 0 Channel Trigger Request Executing 0 1 read-only LVLEX1 Level 1 Channel Trigger Request Executing 1 1 read-only LVLEX2 Level 2 Channel Trigger Request Executing 2 1 read-only LVLEX3 Level 3 Channel Trigger Request Executing 3 1 read-only ID Active Channel ID 8 5 read-only ABUSY Active Channel Busy 15 1 read-only BTCNT Active Channel Block Transfer Count 16 16 read-only BASEADDR Descriptor Memory Section Base Address 0x34 32 BASEADDR Descriptor Memory Base Address 0 32 BUSYCH Busy Channels 0x28 32 read-only BUSYCH0 Busy Channel 0 0 1 read-only BUSYCH1 Busy Channel 1 1 1 read-only BUSYCH2 Busy Channel 2 2 1 read-only BUSYCH3 Busy Channel 3 3 1 read-only BUSYCH4 Busy Channel 4 4 1 read-only BUSYCH5 Busy Channel 5 5 1 read-only BUSYCH6 Busy Channel 6 6 1 read-only BUSYCH7 Busy Channel 7 7 1 read-only BUSYCH8 Busy Channel 8 8 1 read-only BUSYCH9 Busy Channel 9 9 1 read-only BUSYCH10 Busy Channel 10 10 1 read-only BUSYCH11 Busy Channel 11 11 1 read-only CHCTRLA Channel Control A 0x40 8 SWRST Channel Software Reset 0 1 ENABLE Channel Enable 1 1 CHCTRLB Channel Control B 0x44 32 EVACT Event Input Action 0 3 EVACTSelect NOACT No action 0x0 TRIG Transfer and periodic transfer trigger 0x1 CTRIG Conditional transfer trigger 0x2 CBLOCK Conditional block transfer 0x3 SUSPEND Channel suspend operation 0x4 RESUME Channel resume operation 0x5 SSKIP Skip next block suspend action 0x6 EVIE Channel Event Input Enable 3 1 EVOE Channel Event Output Enable 4 1 LVL Channel Arbitration Level 5 2 TRIGSRC Peripheral Trigger Source 8 6 TRIGSRCSelect DISABLE Only software/event triggers 0x0 TRIGACT Trigger Action 22 2 TRIGACTSelect BLOCK One trigger required for each block transfer 0x0 BEAT One trigger required for each beat transfer 0x2 TRANSACTION One trigger required for each transaction 0x3 CMD Software Command 24 2 CMDSelect NOACT No action 0x0 SUSPEND Channel suspend operation 0x1 RESUME Channel resume operation 0x2 CHID Channel ID 0x3F 8 ID Channel ID 0 4 CHINTENCLR Channel Interrupt Enable Clear 0x4C 8 TERR Transfer Error Interrupt Enable 0 1 TCMPL Transfer Complete Interrupt Enable 1 1 SUSP Channel Suspend Interrupt Enable 2 1 CHINTENSET Channel Interrupt Enable Set 0x4D 8 TERR Transfer Error Interrupt Enable 0 1 TCMPL Transfer Complete Interrupt Enable 1 1 SUSP Channel Suspend Interrupt Enable 2 1 CHINTFLAG Channel Interrupt Flag Status and Clear 0x4E 8 TERR Transfer Error 0 1 TCMPL Transfer Complete 1 1 SUSP Channel Suspend 2 1 CHSTATUS Channel Status 0x4F 8 read-only PEND Channel Pending 0 1 read-only BUSY Channel Busy 1 1 read-only FERR Fetch Error 2 1 read-only CRCCHKSUM CRC Checksum 0x08 32 CRCCHKSUM CRC Checksum 0 32 CRCCTRL CRC Control 0x02 16 CRCBEATSIZE CRC Beat Size 0 2 CRCBEATSIZESelect BYTE Byte bus access 0x0 HWORD Half-word bus access 0x1 WORD Word bus access 0x2 CRCPOLY CRC Polynomial Type 2 2 CRCPOLYSelect CRC16 CRC-16 (CRC-CCITT) 0x0 CRC32 CRC32 (IEEE 802.3) 0x1 CRCSRC CRC Input Source 8 6 CRCSRCSelect NOACT No action 0x0 IO I/O interface 0x1 CRCDATAIN CRC Data Input 0x04 32 CRCDATAIN CRC Data Input 0 32 CRCSTATUS CRC Status 0x0C 8 CRCBUSY CRC Module Busy 0 1 CRCZERO CRC Zero 1 1 read-only CTRL Control 0x00 16 SWRST Software Reset 0 1 DMAENABLE DMA Enable 1 1 CRCENABLE CRC Enable 2 1 LVLEN0 Priority Level 0 Enable 8 1 LVLEN1 Priority Level 1 Enable 9 1 LVLEN2 Priority Level 2 Enable 10 1 LVLEN3 Priority Level 3 Enable 11 1 DBGCTRL Debug Control 0x0D 8 DBGRUN Debug Run 0 1 INTPEND Interrupt Pending 0x20 16 ID Channel ID 0 4 TERR Transfer Error 8 1 TCMPL Transfer Complete 9 1 SUSP Channel Suspend 10 1 FERR Fetch Error 13 1 read-only BUSY Busy 14 1 read-only PEND Pending 15 1 read-only INTSTATUS Interrupt Status 0x24 32 read-only CHINT0 Channel 0 Pending Interrupt 0 1 read-only CHINT1 Channel 1 Pending Interrupt 1 1 read-only CHINT2 Channel 2 Pending Interrupt 2 1 read-only CHINT3 Channel 3 Pending Interrupt 3 1 read-only CHINT4 Channel 4 Pending Interrupt 4 1 read-only CHINT5 Channel 5 Pending Interrupt 5 1 read-only CHINT6 Channel 6 Pending Interrupt 6 1 read-only CHINT7 Channel 7 Pending Interrupt 7 1 read-only CHINT8 Channel 8 Pending Interrupt 8 1 read-only CHINT9 Channel 9 Pending Interrupt 9 1 read-only CHINT10 Channel 10 Pending Interrupt 10 1 read-only CHINT11 Channel 11 Pending Interrupt 11 1 read-only PENDCH Pending Channels 0x2C 32 read-only PENDCH0 Pending Channel 0 0 1 read-only PENDCH1 Pending Channel 1 1 1 read-only PENDCH2 Pending Channel 2 2 1 read-only PENDCH3 Pending Channel 3 3 1 read-only PENDCH4 Pending Channel 4 4 1 read-only PENDCH5 Pending Channel 5 5 1 read-only PENDCH6 Pending Channel 6 6 1 read-only PENDCH7 Pending Channel 7 7 1 read-only PENDCH8 Pending Channel 8 8 1 read-only PENDCH9 Pending Channel 9 9 1 read-only PENDCH10 Pending Channel 10 10 1 read-only PENDCH11 Pending Channel 11 11 1 read-only PRICTRL0 Priority Control 0 0x14 32 LVLPRI0 Level 0 Channel Priority Number 0 4 RRLVLEN0 Level 0 Round-Robin Scheduling Enable 7 1 LVLPRI1 Level 1 Channel Priority Number 8 4 RRLVLEN1 Level 1 Round-Robin Scheduling Enable 15 1 LVLPRI2 Level 2 Channel Priority Number 16 4 RRLVLEN2 Level 2 Round-Robin Scheduling Enable 23 1 LVLPRI3 Level 3 Channel Priority Number 24 4 RRLVLEN3 Level 3 Round-Robin Scheduling Enable 31 1 SWTRIGCTRL Software Trigger Control 0x10 32 SWTRIG0 Channel 0 Software Trigger 0 1 SWTRIG1 Channel 1 Software Trigger 1 1 SWTRIG2 Channel 2 Software Trigger 2 1 SWTRIG3 Channel 3 Software Trigger 3 1 SWTRIG4 Channel 4 Software Trigger 4 1 SWTRIG5 Channel 5 Software Trigger 5 1 SWTRIG6 Channel 6 Software Trigger 6 1 SWTRIG7 Channel 7 Software Trigger 7 1 SWTRIG8 Channel 8 Software Trigger 8 1 SWTRIG9 Channel 9 Software Trigger 9 1 SWTRIG10 Channel 10 Software Trigger 10 1 SWTRIG11 Channel 11 Software Trigger 11 1 WRBADDR Write-Back Memory Section Base Address 0x38 32 WRBADDR Write-Back Memory Base Address 0 32 DSU 2.0.0 Device Service Unit DSU DSU_ 0x41002000 0 0x2000 registers ADDR Address 0x0004 32 ADDR Address 2 30 CID0 Component Identification 0 0x1FF0 32 read-only 0x0000000D PREAMBLEB0 Preamble Byte 0 0 8 read-only CID1 Component Identification 1 0x1FF4 32 read-only 0x00000010 PREAMBLE Preamble 0 4 read-only CCLASS Component Class 4 4 read-only CID2 Component Identification 2 0x1FF8 32 read-only 0x00000005 PREAMBLEB2 Preamble Byte 2 0 8 read-only CID3 Component Identification 3 0x1FFC 32 read-only 0x000000B1 PREAMBLEB3 Preamble Byte 3 0 8 CTRL Control 0x0000 8 write-only SWRST Software Reset 0 1 write-only CRC 32-bit Cyclic Redundancy Check 2 1 write-only MBIST Memory Built-In Self-Test 3 1 write-only CE Chip Erase 4 1 write-only DATA Data 0x000C 32 DATA Data 0 32 2 0x4 DCC%s Debug Communication Channel n 0x0010 32 DATA Data 0 32 DID Device Identification 0x0018 32 read-only DEVSEL Device Select 0 8 read-only REVISION Revision 8 4 read-only DIE Die Identification 12 4 read-only SERIES Product Series 16 6 read-only FAMILY Product Family 23 5 read-only PROCESSOR Processor 28 4 read-only END Coresight ROM Table End 0x1008 32 read-only END End Marker 0 32 2 0x4 ENTRY%s Coresight ROM Table Entry n 0x1000 32 read-only 0x00000002 EPRES Entry Present 0 1 FMT Format 1 1 read-only ADDOFF Address Offset 12 20 read-only LENGTH Length 0x0008 32 LENGTH Length 2 30 MEMTYPE Coresight ROM Table Memory Type 0x1FCC 32 read-only SMEMP System Memory Present 0 1 PID0 Peripheral Identification 0 0x1FE0 32 read-only 0x000000D0 PARTNBL Part Number Low 0 8 PID1 Peripheral Identification 1 0x1FE4 32 read-only 0x000000FC PARTNBH Part Number High 0 4 JEPIDCL Low part of the JEP-106 Identity Code 4 4 read-only PID2 Peripheral Identification 2 0x1FE8 32 read-only 0x00000009 JEPIDCH JEP-106 Identity Code High 0 3 JEPU JEP-106 Identity Code is used 3 1 read-only REVISION Revision Number 4 4 read-only PID3 Peripheral Identification 3 0x1FEC 32 read-only CUSMOD ARM CUSMOD 0 4 REVAND Revision Number 4 4 read-only PID4 Peripheral Identification 4 0x1FD0 32 read-only JEPCC JEP-106 Continuation Code 0 4 FKBC 4KB Count 4 4 read-only STATUSA Status A 0x0001 8 DONE Done 0 1 CRSTEXT CPU Reset Phase Extension 1 1 BERR Bus Error 2 1 FAIL Failure 3 1 PERR Protection Error 4 1 STATUSB Status B 0x0002 8 read-only 0x10 PROT Protected 0 1 DBGPRES Debugger Present 1 1 DCCD0 Debug Communication Channel 0 Dirty 2 1 DCCD1 Debug Communication Channel 1 Dirty 3 1 HPE Hot-Plugging Enable 4 1 EIC 1.0.1 External Interrupt Controller EIC EIC_ 0x40001800 0 0x40 registers EIC 4 2 0x4 CONFIG%s Configuration n 0x18 32 SENSE0 Input Sense n Configuration 0 3 SENSE0Select NONE No detection 0x0 RISE Rising-edge detection 0x1 FALL Falling-edge detection 0x2 BOTH Both-edges detection 0x3 HIGH High-level detection 0x4 LOW Low-level detection 0x5 FILTEN0 Filter n Enable 3 1 SENSE1 Input Sense 1 Configuration 4 3 SENSE1Select NONE No detection 0x0 RISE Rising edge detection 0x1 FALL Falling edge detection 0x2 BOTH Both edges detection 0x3 HIGH High level detection 0x4 LOW Low level detection 0x5 FILTEN1 Filter 1 Enable 7 1 SENSE2 Input Sense 2 Configuration 8 3 SENSE2Select NONE No detection 0x0 RISE Rising edge detection 0x1 FALL Falling edge detection 0x2 BOTH Both edges detection 0x3 HIGH High level detection 0x4 LOW Low level detection 0x5 FILTEN2 Filter 2 Enable 11 1 SENSE3 Input Sense 3 Configuration 12 3 SENSE3Select NONE No detection 0x0 RISE Rising edge detection 0x1 FALL Falling edge detection 0x2 BOTH Both edges detection 0x3 HIGH High level detection 0x4 LOW Low level detection 0x5 FILTEN3 Filter 3 Enable 15 1 SENSE4 Input Sense 4 Configuration 16 3 SENSE4Select NONE No detection 0x0 RISE Rising edge detection 0x1 FALL Falling edge detection 0x2 BOTH Both edges detection 0x3 HIGH High level detection 0x4 LOW Low level detection 0x5 FILTEN4 Filter 4 Enable 19 1 SENSE5 Input Sense 5 Configuration 20 3 SENSE5Select NONE No detection 0x0 RISE Rising edge detection 0x1 FALL Falling edge detection 0x2 BOTH Both edges detection 0x3 HIGH High level detection 0x4 LOW Low level detection 0x5 FILTEN5 Filter 5 Enable 23 1 SENSE6 Input Sense 6 Configuration 24 3 SENSE6Select NONE No detection 0x0 RISE Rising edge detection 0x1 FALL Falling edge detection 0x2 BOTH Both edges detection 0x3 HIGH High level detection 0x4 LOW Low level detection 0x5 FILTEN6 Filter 6 Enable 27 1 SENSE7 Input Sense 7 Configuration 28 3 SENSE7Select NONE No detection 0x0 RISE Rising edge detection 0x1 FALL Falling edge detection 0x2 BOTH Both edges detection 0x3 HIGH High level detection 0x4 LOW Low level detection 0x5 FILTEN7 Filter 7 Enable 31 1 CTRL Control 0x00 8 SWRST Software Reset 0 1 ENABLE Enable 1 1 EVCTRL Event Control 0x04 32 EXTINTEO0 External Interrupt 0 Event Output Enable 0 1 EXTINTEO1 External Interrupt 1 Event Output Enable 1 1 EXTINTEO2 External Interrupt 2 Event Output Enable 2 1 EXTINTEO3 External Interrupt 3 Event Output Enable 3 1 EXTINTEO4 External Interrupt 4 Event Output Enable 4 1 EXTINTEO5 External Interrupt 5 Event Output Enable 5 1 EXTINTEO6 External Interrupt 6 Event Output Enable 6 1 EXTINTEO7 External Interrupt 7 Event Output Enable 7 1 EXTINTEO8 External Interrupt 8 Event Output Enable 8 1 EXTINTEO9 External Interrupt 9 Event Output Enable 9 1 EXTINTEO10 External Interrupt 10 Event Output Enable 10 1 EXTINTEO11 External Interrupt 11 Event Output Enable 11 1 EXTINTEO12 External Interrupt 12 Event Output Enable 12 1 EXTINTEO13 External Interrupt 13 Event Output Enable 13 1 EXTINTEO14 External Interrupt 14 Event Output Enable 14 1 EXTINTEO15 External Interrupt 15 Event Output Enable 15 1 INTENCLR Interrupt Enable Clear 0x08 32 EXTINT0 External Interrupt 0 Enable 0 1 EXTINT1 External Interrupt 1 Enable 1 1 EXTINT2 External Interrupt 2 Enable 2 1 EXTINT3 External Interrupt 3 Enable 3 1 EXTINT4 External Interrupt 4 Enable 4 1 EXTINT5 External Interrupt 5 Enable 5 1 EXTINT6 External Interrupt 6 Enable 6 1 EXTINT7 External Interrupt 7 Enable 7 1 EXTINT8 External Interrupt 8 Enable 8 1 EXTINT9 External Interrupt 9 Enable 9 1 EXTINT10 External Interrupt 10 Enable 10 1 EXTINT11 External Interrupt 11 Enable 11 1 EXTINT12 External Interrupt 12 Enable 12 1 EXTINT13 External Interrupt 13 Enable 13 1 EXTINT14 External Interrupt 14 Enable 14 1 EXTINT15 External Interrupt 15 Enable 15 1 INTENSET Interrupt Enable Set 0x0C 32 EXTINT0 External Interrupt 0 Enable 0 1 EXTINT1 External Interrupt 1 Enable 1 1 EXTINT2 External Interrupt 2 Enable 2 1 EXTINT3 External Interrupt 3 Enable 3 1 EXTINT4 External Interrupt 4 Enable 4 1 EXTINT5 External Interrupt 5 Enable 5 1 EXTINT6 External Interrupt 6 Enable 6 1 EXTINT7 External Interrupt 7 Enable 7 1 EXTINT8 External Interrupt 8 Enable 8 1 EXTINT9 External Interrupt 9 Enable 9 1 EXTINT10 External Interrupt 10 Enable 10 1 EXTINT11 External Interrupt 11 Enable 11 1 EXTINT12 External Interrupt 12 Enable 12 1 EXTINT13 External Interrupt 13 Enable 13 1 EXTINT14 External Interrupt 14 Enable 14 1 EXTINT15 External Interrupt 15 Enable 15 1 INTFLAG Interrupt Flag Status and Clear 0x10 32 EXTINT0 External Interrupt 0 0 1 EXTINT1 External Interrupt 1 1 1 EXTINT2 External Interrupt 2 2 1 EXTINT3 External Interrupt 3 3 1 EXTINT4 External Interrupt 4 4 1 EXTINT5 External Interrupt 5 5 1 EXTINT6 External Interrupt 6 6 1 EXTINT7 External Interrupt 7 7 1 EXTINT8 External Interrupt 8 8 1 EXTINT9 External Interrupt 9 9 1 EXTINT10 External Interrupt 10 10 1 EXTINT11 External Interrupt 11 11 1 EXTINT12 External Interrupt 12 12 1 EXTINT13 External Interrupt 13 13 1 EXTINT14 External Interrupt 14 14 1 EXTINT15 External Interrupt 15 15 1 NMICTRL Non-Maskable Interrupt Control 0x02 8 NMISENSE Non-Maskable Interrupt Sense 0 3 NMISENSESelect NONE No detection 0x0 RISE Rising-edge detection 0x1 FALL Falling-edge detection 0x2 BOTH Both-edges detection 0x3 HIGH High-level detection 0x4 LOW Low-level detection 0x5 NMIFILTEN Non-Maskable Interrupt Filter Enable 3 1 NMIFLAG Non-Maskable Interrupt Flag Status and Clear 0x03 8 NMI Non-Maskable Interrupt 0 1 STATUS Status 0x01 8 read-only SYNCBUSY Synchronization Busy 7 1 read-only WAKEUP Wake-Up Enable 0x14 32 WAKEUPEN0 External Interrupt 0 Wake-up Enable 0 1 WAKEUPEN1 External Interrupt 1 Wake-up Enable 1 1 WAKEUPEN2 External Interrupt 2 Wake-up Enable 2 1 WAKEUPEN3 External Interrupt 3 Wake-up Enable 3 1 WAKEUPEN4 External Interrupt 4 Wake-up Enable 4 1 WAKEUPEN5 External Interrupt 5 Wake-up Enable 5 1 WAKEUPEN6 External Interrupt 6 Wake-up Enable 6 1 WAKEUPEN7 External Interrupt 7 Wake-up Enable 7 1 WAKEUPEN8 External Interrupt 8 Wake-up Enable 8 1 WAKEUPEN9 External Interrupt 9 Wake-up Enable 9 1 WAKEUPEN10 External Interrupt 10 Wake-up Enable 10 1 WAKEUPEN11 External Interrupt 11 Wake-up Enable 11 1 WAKEUPEN12 External Interrupt 12 Wake-up Enable 12 1 WAKEUPEN13 External Interrupt 13 Wake-up Enable 13 1 WAKEUPEN14 External Interrupt 14 Wake-up Enable 14 1 WAKEUPEN15 External Interrupt 15 Wake-up Enable 15 1 EVSYS 1.0.1 Event System Interface EVSYS EVSYS_ 0x42000400 0 0x80 registers EVSYS 8 CHANNEL Channel 0x04 32 CHANNEL Channel Selection 0 4 SWEVT Software Event 8 1 EVGEN Event Generator Selection 16 7 PATH Path Selection 24 2 PATHSelect SYNCHRONOUS Synchronous path 0x0 RESYNCHRONIZED Resynchronized path 0x1 ASYNCHRONOUS Asynchronous path 0x2 EDGSEL Edge Detection Selection 26 2 EDGSELSelect NO_EVT_OUTPUT No event output when using the resynchronized or synchronous path 0x0 RISING_EDGE Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path 0x1 FALLING_EDGE Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path 0x2 BOTH_EDGES Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path 0x3 CHSTATUS Channel Status 0x0C 32 read-only 0x000F00FF USRRDY0 Channel 0 User Ready 0 1 read-only USRRDY1 Channel 1 User Ready 1 1 read-only USRRDY2 Channel 2 User Ready 2 1 read-only USRRDY3 Channel 3 User Ready 3 1 read-only USRRDY4 Channel 4 User Ready 4 1 read-only USRRDY5 Channel 5 User Ready 5 1 read-only USRRDY6 Channel 6 User Ready 6 1 read-only USRRDY7 Channel 7 User Ready 7 1 read-only CHBUSY0 Channel 0 Busy 8 1 read-only CHBUSY1 Channel 1 Busy 9 1 read-only CHBUSY2 Channel 2 Busy 10 1 read-only CHBUSY3 Channel 3 Busy 11 1 read-only CHBUSY4 Channel 4 Busy 12 1 read-only CHBUSY5 Channel 5 Busy 13 1 read-only CHBUSY6 Channel 6 Busy 14 1 read-only CHBUSY7 Channel 7 Busy 15 1 read-only USRRDY8 Channel 8 User Ready 16 1 read-only USRRDY9 Channel 9 User Ready 17 1 read-only USRRDY10 Channel 10 User Ready 18 1 read-only USRRDY11 Channel 11 User Ready 19 1 read-only CHBUSY8 Channel 8 Busy 24 1 read-only CHBUSY9 Channel 9 Busy 25 1 read-only CHBUSY10 Channel 10 Busy 26 1 read-only CHBUSY11 Channel 11 Busy 27 1 read-only CTRL Control 0x00 8 write-only SWRST Software Reset 0 1 write-only GCLKREQ Generic Clock Requests 4 1 INTENCLR Interrupt Enable Clear 0x10 32 OVR0 Channel 0 Overrun Interrupt Enable 0 1 OVR1 Channel 1 Overrun Interrupt Enable 1 1 OVR2 Channel 2 Overrun Interrupt Enable 2 1 OVR3 Channel 3 Overrun Interrupt Enable 3 1 OVR4 Channel 4 Overrun Interrupt Enable 4 1 OVR5 Channel 5 Overrun Interrupt Enable 5 1 OVR6 Channel 6 Overrun Interrupt Enable 6 1 OVR7 Channel 7 Overrun Interrupt Enable 7 1 EVD0 Channel 0 Event Detection Interrupt Enable 8 1 EVD1 Channel 1 Event Detection Interrupt Enable 9 1 EVD2 Channel 2 Event Detection Interrupt Enable 10 1 EVD3 Channel 3 Event Detection Interrupt Enable 11 1 EVD4 Channel 4 Event Detection Interrupt Enable 12 1 EVD5 Channel 5 Event Detection Interrupt Enable 13 1 EVD6 Channel 6 Event Detection Interrupt Enable 14 1 EVD7 Channel 7 Event Detection Interrupt Enable 15 1 OVR8 Channel 8 Overrun Interrupt Enable 16 1 OVR9 Channel 9 Overrun Interrupt Enable 17 1 OVR10 Channel 10 Overrun Interrupt Enable 18 1 OVR11 Channel 11 Overrun Interrupt Enable 19 1 EVD8 Channel 8 Event Detection Interrupt Enable 24 1 EVD9 Channel 9 Event Detection Interrupt Enable 25 1 EVD10 Channel 10 Event Detection Interrupt Enable 26 1 EVD11 Channel 11 Event Detection Interrupt Enable 27 1 INTENSET Interrupt Enable Set 0x14 32 OVR0 Channel 0 Overrun Interrupt Enable 0 1 OVR1 Channel 1 Overrun Interrupt Enable 1 1 OVR2 Channel 2 Overrun Interrupt Enable 2 1 OVR3 Channel 3 Overrun Interrupt Enable 3 1 OVR4 Channel 4 Overrun Interrupt Enable 4 1 OVR5 Channel 5 Overrun Interrupt Enable 5 1 OVR6 Channel 6 Overrun Interrupt Enable 6 1 OVR7 Channel 7 Overrun Interrupt Enable 7 1 EVD0 Channel 0 Event Detection Interrupt Enable 8 1 EVD1 Channel 1 Event Detection Interrupt Enable 9 1 EVD2 Channel 2 Event Detection Interrupt Enable 10 1 EVD3 Channel 3 Event Detection Interrupt Enable 11 1 EVD4 Channel 4 Event Detection Interrupt Enable 12 1 EVD5 Channel 5 Event Detection Interrupt Enable 13 1 EVD6 Channel 6 Event Detection Interrupt Enable 14 1 EVD7 Channel 7 Event Detection Interrupt Enable 15 1 OVR8 Channel 8 Overrun Interrupt Enable 16 1 OVR9 Channel 9 Overrun Interrupt Enable 17 1 OVR10 Channel 10 Overrun Interrupt Enable 18 1 OVR11 Channel 11 Overrun Interrupt Enable 19 1 EVD8 Channel 8 Event Detection Interrupt Enable 24 1 EVD9 Channel 9 Event Detection Interrupt Enable 25 1 EVD10 Channel 10 Event Detection Interrupt Enable 26 1 EVD11 Channel 11 Event Detection Interrupt Enable 27 1 INTFLAG Interrupt Flag Status and Clear 0x18 32 OVR0 Channel 0 Overrun 0 1 OVR1 Channel 1 Overrun 1 1 OVR2 Channel 2 Overrun 2 1 OVR3 Channel 3 Overrun 3 1 OVR4 Channel 4 Overrun 4 1 OVR5 Channel 5 Overrun 5 1 OVR6 Channel 6 Overrun 6 1 OVR7 Channel 7 Overrun 7 1 EVD0 Channel 0 Event Detection 8 1 EVD1 Channel 1 Event Detection 9 1 EVD2 Channel 2 Event Detection 10 1 EVD3 Channel 3 Event Detection 11 1 EVD4 Channel 4 Event Detection 12 1 EVD5 Channel 5 Event Detection 13 1 EVD6 Channel 6 Event Detection 14 1 EVD7 Channel 7 Event Detection 15 1 OVR8 Channel 8 Overrun 16 1 OVR9 Channel 9 Overrun 17 1 OVR10 Channel 10 Overrun 18 1 OVR11 Channel 11 Overrun 19 1 EVD8 Channel 8 Event Detection 24 1 EVD9 Channel 9 Event Detection 25 1 EVD10 Channel 10 Event Detection 26 1 EVD11 Channel 11 Event Detection 27 1 USER User Multiplexer 0x08 16 USER User Multiplexer Selection 0 5 CHANNEL Channel Event Selection 8 5 CHANNELSelect 0 No Channel Output Selected 0x0 GCLK 2.1.0 Generic Clock Generator GCLK GCLK_ 0x40000C00 0 0x10 registers CLKCTRL Generic Clock Control 0x2 16 ID Generic Clock Selection ID 0 6 GEN Generic Clock Generator 8 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 CLKEN Clock Enable 14 1 WRTLOCK Write Lock 15 1 CTRL Control 0x0 8 SWRST Software Reset 0 1 GENCTRL Generic Clock Generator Control 0x4 32 ID Generic Clock Generator Selection 0 4 SRC Source Select 8 5 SRCSelect XOSC XOSC oscillator output 0x0 GCLKIN Generator input pad 0x1 GCLKGEN1 Generic clock generator 1 output 0x2 OSCULP32K OSCULP32K oscillator output 0x3 OSC32K OSC32K oscillator output 0x4 XOSC32K XOSC32K oscillator output 0x5 OSC8M OSC8M oscillator output 0x6 DFLL48M DFLL48M output 0x7 GENEN Generic Clock Generator Enable 16 1 IDC Improve Duty Cycle 17 1 OOV Output Off Value 18 1 OE Output Enable 19 1 DIVSEL Divide Selection 20 1 RUNSTDBY Run in Standby 21 1 GENDIV Generic Clock Generator Division 0x8 32 ID Generic Clock Generator Selection 0 4 DIV Division Factor 8 16 STATUS Status 0x1 8 read-only SYNCBUSY Synchronization Busy Status 7 1 read-only I2S 1.0.1 Inter-IC Sound Interface I2S I2S_ 0x42005000 0 0x40 registers I2S 27 2 0x4 CLKCTRL%s Clock Unit n Control 0x04 32 SLOTSIZE Slot Size 0 2 SLOTSIZESelect 8 8-bit Slot for Clock Unit n 0x0 16 16-bit Slot for Clock Unit n 0x1 24 24-bit Slot for Clock Unit n 0x2 32 32-bit Slot for Clock Unit n 0x3 NBSLOTS Number of Slots in Frame 2 3 FSWIDTH Frame Sync Width 5 2 FSWIDTHSelect SLOT Frame Sync Pulse is 1 Slot wide (default for I2S protocol) 0x0 HALF Frame Sync Pulse is half a Frame wide 0x1 BIT Frame Sync Pulse is 1 Bit wide 0x2 BURST Clock Unit n operates in Burst mode, with a 1-bit wide Frame Sync pulse per Data sample, only when Data transfer is requested 0x3 BITDELAY Data Delay from Frame Sync 7 1 BITDELAYSelect LJ Left Justified (0 Bit Delay) 0x0 I2S I2S (1 Bit Delay) 0x1 FSSEL Frame Sync Select 8 1 FSSELSelect SCKDIV Divided Serial Clock n is used as Frame Sync n source 0x0 FSPIN FSn input pin is used as Frame Sync n source 0x1 FSINV Frame Sync Invert 11 1 SCKSEL Serial Clock Select 12 1 SCKSELSelect MCKDIV Divided Master Clock n is used as Serial Clock n source 0x0 SCKPIN SCKn input pin is used as Serial Clock n source 0x1 MCKSEL Master Clock Select 16 1 MCKSELSelect GCLK clk_gen_n is used as Master Clock n source 0x0 MCKPIN MCKn input pin is used as Master Clock n source 0x1 MCKEN Master Clock Enable 18 1 MCKDIV Master Clock Division Factor 19 5 MCKOUTDIV Master Clock Output Division Factor 24 5 FSOUTINV Frame Sync Output Invert 29 1 SCKOUTINV Serial Clock Output Invert 30 1 MCKOUTINV Master Clock Output Invert 31 1 CTRLA Control A 0x00 8 SWRST Software Reset 0 1 ENABLE Enable 1 1 CKEN0 Clock Unit 0 Enable 2 1 CKEN1 Clock Unit 1 Enable 3 1 SEREN0 Serializer 0 Enable 4 1 SEREN1 Serializer 1 Enable 5 1 2 0x4 DATA%s Data n 0x30 32 DATA Sample Data 0 32 INTENCLR Interrupt Enable Clear 0x0C 16 RXRDY0 Receive Ready 0 Interrupt Enable 0 1 RXRDY1 Receive Ready 1 Interrupt Enable 1 1 RXOR0 Receive Overrun 0 Interrupt Enable 4 1 RXOR1 Receive Overrun 1 Interrupt Enable 5 1 TXRDY0 Transmit Ready 0 Interrupt Enable 8 1 TXRDY1 Transmit Ready 1 Interrupt Enable 9 1 TXUR0 Transmit Underrun 0 Interrupt Enable 12 1 TXUR1 Transmit Underrun 1 Interrupt Enable 13 1 INTENSET Interrupt Enable Set 0x10 16 RXRDY0 Receive Ready 0 Interrupt Enable 0 1 RXRDY1 Receive Ready 1 Interrupt Enable 1 1 RXOR0 Receive Overrun 0 Interrupt Enable 4 1 RXOR1 Receive Overrun 1 Interrupt Enable 5 1 TXRDY0 Transmit Ready 0 Interrupt Enable 8 1 TXRDY1 Transmit Ready 1 Interrupt Enable 9 1 TXUR0 Transmit Underrun 0 Interrupt Enable 12 1 TXUR1 Transmit Underrun 1 Interrupt Enable 13 1 INTFLAG Interrupt Flag Status and Clear 0x14 16 RXRDY0 Receive Ready 0 0 1 RXRDY1 Receive Ready 1 1 1 RXOR0 Receive Overrun 0 4 1 RXOR1 Receive Overrun 1 5 1 TXRDY0 Transmit Ready 0 8 1 TXRDY1 Transmit Ready 1 9 1 TXUR0 Transmit Underrun 0 12 1 TXUR1 Transmit Underrun 1 13 1 2 0x4 SERCTRL%s Serializer n Control 0x20 32 SERMODE Serializer Mode 0 2 SERMODESelect RX Receive 0x0 TX Transmit 0x1 PDM2 Receive 1 PDM data on each clock edge 0x2 TXDEFAULT Line Default Line when Slot Disabled 2 2 TXDEFAULTSelect ZERO Output Default Value is 0 0x0 ONE Output Default Value is 1 0x1 HIZ Output Default Value is high impedance 0x3 TXSAME Transmit Data when Underrun 4 1 TXSAMESelect ZERO Zero data transmitted in case of underrun 0x0 SAME Last data transmitted in case of underrun 0x1 CLKSEL Clock Unit Selection 5 1 CLKSELSelect CLK0 Use Clock Unit 0 0x0 CLK1 Use Clock Unit 1 0x1 SLOTADJ Data Slot Formatting Adjust 7 1 SLOTADJSelect RIGHT Data is right adjusted in slot 0x0 LEFT Data is left adjusted in slot 0x1 DATASIZE Data Word Size 8 3 DATASIZESelect 32 32 bits 0x0 24 24 bits 0x1 20 20 bits 0x2 18 18 bits 0x3 16 16 bits 0x4 16C 16 bits compact stereo 0x5 8 8 bits 0x6 8C 8 bits compact stereo 0x7 WORDADJ Data Word Formatting Adjust 12 1 WORDADJSelect RIGHT Data is right adjusted in word 0x0 LEFT Data is left adjusted in word 0x1 EXTEND Data Formatting Bit Extension 13 2 EXTENDSelect ZERO Extend with zeroes 0x0 ONE Extend with ones 0x1 MSBIT Extend with Most Significant Bit 0x2 LSBIT Extend with Least Significant Bit 0x3 BITREV Data Formatting Bit Reverse 15 1 BITREVSelect MSBIT Transfer Data Most Significant Bit (MSB) first (default for I2S protocol) 0x0 LSBIT Transfer Data Least Significant Bit (LSB) first 0x1 SLOTDIS0 Slot 0 Disabled for this Serializer 16 1 SLOTDIS1 Slot 1 Disabled for this Serializer 17 1 SLOTDIS2 Slot 2 Disabled for this Serializer 18 1 SLOTDIS3 Slot 3 Disabled for this Serializer 19 1 SLOTDIS4 Slot 4 Disabled for this Serializer 20 1 SLOTDIS5 Slot 5 Disabled for this Serializer 21 1 SLOTDIS6 Slot 6 Disabled for this Serializer 22 1 SLOTDIS7 Slot 7 Disabled for this Serializer 23 1 MONO Mono Mode 24 1 MONOSelect STEREO Normal mode 0x0 MONO Left channel data is duplicated to right channel 0x1 DMA Single or Multiple DMA Channels 25 1 DMASelect SINGLE Single DMA channel 0x0 MULTIPLE One DMA channel per data channel 0x1 RXLOOP Loop-back Test Mode 26 1 SYNCBUSY Synchronization Status 0x18 16 read-only SWRST Software Reset Synchronization Status 0 1 ENABLE Enable Synchronization Status 1 1 CKEN0 Clock Unit 0 Enable Synchronization Status 2 1 CKEN1 Clock Unit 1 Enable Synchronization Status 3 1 SEREN0 Serializer 0 Enable Synchronization Status 4 1 SEREN1 Serializer 1 Enable Synchronization Status 5 1 DATA0 Data 0 Synchronization Status 8 1 DATA1 Data 1 Synchronization Status 9 1 MTB 1.0.0 Cortex-M0+ Micro-Trace Buffer MTB MTB_ 0x41006000 0 0x1000 registers AUTHSTATUS MTB Authentication Status 0xFB8 32 read-only BASE MTB Base 0x00C 32 read-only CID0 CoreSight 0xFF0 32 read-only CID1 CoreSight 0xFF4 32 read-only CID2 CoreSight 0xFF8 32 read-only CID3 CoreSight 0xFFC 32 read-only CLAIMCLR MTB Claim Clear 0xFA4 32 CLAIMSET MTB Claim Set 0xFA0 32 DEVARCH MTB Device Architecture 0xFBC 32 read-only DEVID MTB Device Configuration 0xFC8 32 read-only DEVTYPE MTB Device Type 0xFCC 32 read-only FLOW MTB Flow 0x008 32 AUTOSTOP Auto Stop Tracing 0 1 AUTOHALT Auto Halt Request 1 1 WATERMARK Watermark value 3 29 ITCTRL MTB Integration Mode Control 0xF00 32 LOCKACCESS MTB Lock Access 0xFB0 32 LOCKSTATUS MTB Lock Status 0xFB4 32 read-only MASTER MTB Master 0x004 32 MASK Maximum Value of the Trace Buffer in SRAM 0 5 TSTARTEN Trace Start Input Enable 5 1 TSTOPEN Trace Stop Input Enable 6 1 SFRWPRIV Special Function Register Write Privilege 7 1 RAMPRIV SRAM Privilege 8 1 HALTREQ Halt Request 9 1 EN Main Trace Enable 31 1 PID0 CoreSight 0xFE0 32 read-only PID1 CoreSight 0xFE4 32 read-only PID2 CoreSight 0xFE8 32 read-only PID3 CoreSight 0xFEC 32 read-only PID4 CoreSight 0xFD0 32 read-only PID5 CoreSight 0xFD4 32 read-only PID6 CoreSight 0xFD8 32 read-only PID7 CoreSight 0xFDC 32 read-only POSITION MTB Position 0x000 32 WRAP Pointer Value Wraps 2 1 POINTER Trace Packet Location Pointer 3 29 NVMCTRL 1.0.6 Non-Volatile Memory Controller NVMCTRL NVMCTRL_ 0x41004000 0 0x80 registers NVMCTRL 5 ADDR Address 0x1C 32 ADDR NVM Address 0 22 CTRLA Control A 0x00 16 CMD Command 0 7 CMDSelect ER Erase Row - Erases the row addressed by the ADDR register. 0x2 WP Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register. 0x4 EAR Erase Auxiliary Row - Erases the auxiliary row addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row. 0x5 WAP Write Auxiliary Page - Writes the contents of the page buffer to the page addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row. 0x6 SF Security Flow Command 0xa WL Write lockbits 0xf LR Lock Region - Locks the region containing the address location in the ADDR register. 0x40 UR Unlock Region - Unlocks the region containing the address location in the ADDR register. 0x41 SPRM Sets the power reduction mode. 0x42 CPRM Clears the power reduction mode. 0x43 PBC Page Buffer Clear - Clears the page buffer. 0x44 SSB Set Security Bit - Sets the security bit by writing 0x00 to the first byte in the lockbit row. 0x45 INVALL Invalidates all cache lines. 0x46 CMDEX Command Execution 8 8 CMDEXSelect KEY Execution Key 0xa5 CTRLB Control B 0x04 32 RWS NVM Read Wait States 1 4 RWSSelect SINGLE Single Auto Wait State 0x0 HALF Half Auto Wait State 0x1 DUAL Dual Auto Wait State 0x2 MANW Manual Write 7 1 SLEEPPRM Power Reduction Mode during Sleep 8 2 SLEEPPRMSelect WAKEONACCESS NVM block enters low-power mode when entering sleep.NVM block exits low-power mode upon first access. 0x0 WAKEUPINSTANT NVM block enters low-power mode when entering sleep.NVM block exits low-power mode when exiting sleep. 0x1 DISABLED Auto power reduction disabled. 0x3 READMODE NVMCTRL Read Mode 16 2 READMODESelect NO_MISS_PENALTY The NVM Controller (cache system) does not insert wait states on a cache miss. Gives the best system performance. 0x0 LOW_POWER Reduces power consumption of the cache system, but inserts a wait state each time there is a cache miss. This mode may not be relevant if CPU performance is required, as the application will be stalled and may lead to increase run time. 0x1 DETERMINISTIC The cache system ensures that a cache hit or miss takes the same amount of time, determined by the number of programmed flash wait states. This mode can be used for real-time applications that require deterministic execution timings. 0x2 CACHEDIS Cache Disable 18 1 INTENCLR Interrupt Enable Clear 0x0C 8 READY NVM Ready Interrupt Enable 0 1 ERROR Error Interrupt Enable 1 1 INTENSET Interrupt Enable Set 0x10 8 READY NVM Ready Interrupt Enable 0 1 ERROR Error Interrupt Enable 1 1 INTFLAG Interrupt Flag Status and Clear 0x14 8 READY NVM Ready 0 1 read-only ERROR Error 1 1 LOCK Lock Section 0x20 16 LOCK Region Lock Bits 0 16 read-only PARAM NVM Parameter 0x08 32 NVMP NVM Pages 0 16 read-only PSZ Page Size 16 3 read-only PSZSelect 8 8 bytes 0x0 16 16 bytes 0x1 32 32 bytes 0x2 64 64 bytes 0x3 128 128 bytes 0x4 256 256 bytes 0x5 512 512 bytes 0x6 1024 1024 bytes 0x7 STATUS Status 0x18 16 PRM Power Reduction Mode 0 1 read-only LOAD NVM Page Buffer Active Loading 1 1 PROGE Programming Error Status 2 1 LOCKE Lock Error Status 3 1 NVME NVM Error 4 1 SB Security Bit Status 8 1 read-only PAC0 1.0.1 Peripheral Access Controller 0 PAC PAC_ 0x40000000 0 0x08 registers WPCLR Write Protection Clear 0x0 32 WP Write Protection Clear 1 31 WPSET Write Protection Set 0x4 32 WP Write Protection Set 1 31 PAC1 Peripheral Access Controller 1 0x41000000 PAC2 Peripheral Access Controller 2 0x42000000 PM 2.0.1 Power Manager PM PM_ 0x40000400 0 0x80 registers PM 0 AHBMASK AHB Mask 0x14 32 0x0000007F HPB0 HPB0 AHB Clock Enable 0 1 HPB1 HPB1 AHB Clock Enable 1 1 HPB2 HPB2 AHB Clock Enable 2 1 DSU DSU AHB Clock Enable 3 1 NVMCTRL NVMCTRL AHB Clock Enable 4 1 DMAC DMAC AHB Clock Enable 5 1 USB USB AHB Clock Enable 6 1 APBAMASK APBA Mask 0x18 32 0x0000007F PAC0 PAC0 APB Clock Enable 0 1 PM PM APB Clock Enable 1 1 SYSCTRL SYSCTRL APB Clock Enable 2 1 GCLK GCLK APB Clock Enable 3 1 WDT WDT APB Clock Enable 4 1 RTC RTC APB Clock Enable 5 1 EIC EIC APB Clock Enable 6 1 APBASEL APBA Clock Select 0x09 8 APBADIV APBA Prescaler Selection 0 3 APBADIVSelect DIV1 Divide by 1 0x0 DIV2 Divide by 2 0x1 DIV4 Divide by 4 0x2 DIV8 Divide by 8 0x3 DIV16 Divide by 16 0x4 DIV32 Divide by 32 0x5 DIV64 Divide by 64 0x6 DIV128 Divide by 128 0x7 APBBMASK APBB Mask 0x1C 32 0x0000007F PAC1 PAC1 APB Clock Enable 0 1 DSU DSU APB Clock Enable 1 1 NVMCTRL NVMCTRL APB Clock Enable 2 1 PORT PORT APB Clock Enable 3 1 DMAC DMAC APB Clock Enable 4 1 USB USB APB Clock Enable 5 1 APBBSEL APBB Clock Select 0x0A 8 APBBDIV APBB Prescaler Selection 0 3 APBBDIVSelect DIV1 Divide by 1 0x0 DIV2 Divide by 2 0x1 DIV4 Divide by 4 0x2 DIV8 Divide by 8 0x3 DIV16 Divide by 16 0x4 DIV32 Divide by 32 0x5 DIV64 Divide by 64 0x6 DIV128 Divide by 128 0x7 APBCMASK APBC Mask 0x20 32 0x00010000 PAC2 PAC2 APB Clock Enable 0 1 EVSYS EVSYS APB Clock Enable 1 1 SERCOM0 SERCOM0 APB Clock Enable 2 1 SERCOM1 SERCOM1 APB Clock Enable 3 1 SERCOM2 SERCOM2 APB Clock Enable 4 1 SERCOM3 SERCOM3 APB Clock Enable 5 1 SERCOM4 SERCOM4 APB Clock Enable 6 1 SERCOM5 SERCOM5 APB Clock Enable 7 1 TCC0 TCC0 APB Clock Enable 8 1 TCC1 TCC1 APB Clock Enable 9 1 TCC2 TCC2 APB Clock Enable 10 1 TC3 TC3 APB Clock Enable 11 1 TC4 TC4 APB Clock Enable 12 1 TC5 TC5 APB Clock Enable 13 1 ADC ADC APB Clock Enable 16 1 AC AC APB Clock Enable 17 1 DAC DAC APB Clock Enable 18 1 I2S I2S APB Clock Enable 20 1 ATW ATW APB Clock Enable 23 1 APBCSEL APBC Clock Select 0x0B 8 APBCDIV APBC Prescaler Selection 0 3 APBCDIVSelect DIV1 Divide by 1 0x0 DIV2 Divide by 2 0x1 DIV4 Divide by 4 0x2 DIV8 Divide by 8 0x3 DIV16 Divide by 16 0x4 DIV32 Divide by 32 0x5 DIV64 Divide by 64 0x6 DIV128 Divide by 128 0x7 CPUSEL CPU Clock Select 0x08 8 CPUDIV CPU Prescaler Selection 0 3 CPUDIVSelect DIV1 Divide by 1 0x0 DIV2 Divide by 2 0x1 DIV4 Divide by 4 0x2 DIV8 Divide by 8 0x3 DIV16 Divide by 16 0x4 DIV32 Divide by 32 0x5 DIV64 Divide by 64 0x6 DIV128 Divide by 128 0x7 CTRL Control 0x00 8 CFDEN Clock Failure Detector Enable 2 1 BKUPCLK Backup Clock Select 4 1 INTENCLR Interrupt Enable Clear 0x34 8 CKRDY Clock Ready Interrupt Enable 0 1 CFD Clock Failure Detector Interrupt Enable 1 1 INTENSET Interrupt Enable Set 0x35 8 CKRDY Clock Ready Interrupt Enable 0 1 CFD Clock Failure Detector Interrupt Enable 1 1 INTFLAG Interrupt Flag Status and Clear 0x36 8 CKRDY Clock Ready 0 1 CFD Clock Failure Detector 1 1 RCAUSE Reset Cause 0x38 8 read-only 0x01 POR Power On Reset 0 1 BOD12 Brown Out 12 Detector Reset 1 1 BOD33 Brown Out 33 Detector Reset 2 1 EXT External Reset 4 1 WDT Watchdog Reset 5 1 SYST System Reset Request 6 1 SLEEP Sleep Mode 0x01 8 IDLE Idle Mode Configuration 0 2 IDLESelect CPU The CPU clock domain is stopped 0x0 AHB The CPU and AHB clock domains are stopped 0x1 APB The CPU, AHB and APB clock domains are stopped 0x2 PORT 1.0.0 Port Module PORT PORT_ 0x41004400 0 0x200 registers 3 0x80 CTRL%s Control 0x24 32 SAMPLING Input Sampling Mode 0 32 write-only 3 0x80 DIR%s Data Direction 0x00 32 DIR Port Data Direction 0 32 3 0x80 DIRCLR%s Data Direction Clear 0x04 32 DIRCLR Port Data Direction Clear 0 32 3 0x80 DIRSET%s Data Direction Set 0x08 32 DIRSET Port Data Direction Set 0 32 3 0x80 DIRTGL%s Data Direction Toggle 0x0C 32 DIRTGL Port Data Direction Toggle 0 32 3 0x80 IN%s Data Input Value 0x20 32 read-only IN Port Data Input Value 0 32 3 0x80 OUT%s Data Output Value 0x10 32 OUT Port Data Output Value 0 32 3 0x80 OUTCLR%s Data Output Value Clear 0x14 32 OUTCLR Port Data Output Value Clear 0 32 3 0x80 OUTSET%s Data Output Value Set 0x18 32 OUTSET Port Data Output Value Set 0 32 3 0x80 OUTTGL%s Data Output Value Toggle 0x1C 32 OUTTGL Port Data Output Value Toggle 0 32 32 0x1 PINCFG0_%s Pin Configuration n - Group 0 0x40 8 PMUXEN Peripheral Multiplexer Enable 0 1 INEN Input Enable 1 1 PULLEN Pull Enable 2 1 DRVSTR Output Driver Strength Selection 6 1 write-only 32 0x1 PINCFG1_%s Pin Configuration n - Group 1 0xc0 32 0x1 PINCFG2_%s Pin Configuration n - Group 2 0x140 16 0x1 PMUX0_%s Peripheral Multiplexing n - Group 0 0x30 8 PMUXE Peripheral Multiplexing Even 0 4 PMUXESelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 PMUXO Peripheral Multiplexing Odd 4 4 PMUXOSelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 16 0x1 PMUX1_%s Peripheral Multiplexing n - Group 1 0xb0 16 0x1 PMUX2_%s Peripheral Multiplexing n - Group 2 0x130 3 0x80 WRCONFIG%s Write Configuration 0x28 32 write-only PINMASK Pin Mask for Multiple Pin Configuration 0 16 PMUXEN Peripheral Multiplexer Enable 16 1 INEN Input Enable 17 1 PULLEN Pull Enable 18 1 DRVSTR Output Driver Strength Selection 22 1 PMUX Peripheral Multiplexing 24 4 WRPMUX Write PMUX 28 1 WRPINCFG Write PINCFG 30 1 HWSEL Half-Word Select 31 1 RTC 1.0.1 Real-Time Counter RTC RTC_ 0x40001400 0 0x40 registers RTC 3 MODE0 32-bit Counter with Single 32-bit Compare RtcMode0 0x0 DBGCTRL Debug Control 0x0B 8 DBGRUN Run During Debug 0 1 FREQCORR Frequency Correction 0x0C 8 VALUE Correction Value 0 7 SIGN Correction Sign 7 1 1 0x4 COMP%s MODE0 Compare n Value 0x18 32 COMP Compare Value 0 32 COUNT MODE0 Counter Value 0x10 32 COUNT Counter Value 0 32 CTRL MODE0 Control 0x00 16 SWRST Software Reset 0 1 write-only ENABLE Enable 1 1 MODE Operating Mode 2 2 MODESelect COUNT32 Mode 0: 32-bit Counter 0x0 COUNT16 Mode 1: 16-bit Counter 0x1 CLOCK Mode 2: Clock/Calendar 0x2 MATCHCLR Clear on Match 7 1 PRESCALER Prescaler 8 4 PRESCALERSelect DIV1 CLK_RTC_CNT = GCLK_RTC/1 0x0 DIV2 CLK_RTC_CNT = GCLK_RTC/2 0x1 DIV4 CLK_RTC_CNT = GCLK_RTC/4 0x2 DIV8 CLK_RTC_CNT = GCLK_RTC/8 0x3 DIV16 CLK_RTC_CNT = GCLK_RTC/16 0x4 DIV32 CLK_RTC_CNT = GCLK_RTC/32 0x5 DIV64 CLK_RTC_CNT = GCLK_RTC/64 0x6 DIV128 CLK_RTC_CNT = GCLK_RTC/128 0x7 DIV256 CLK_RTC_CNT = GCLK_RTC/256 0x8 DIV512 CLK_RTC_CNT = GCLK_RTC/512 0x9 DIV1024 CLK_RTC_CNT = GCLK_RTC/1024 0xa EVCTRL MODE0 Event Control 0x04 16 PEREO0 Periodic Interval 0 Event Output Enable 0 1 PEREO1 Periodic Interval 1 Event Output Enable 1 1 PEREO2 Periodic Interval 2 Event Output Enable 2 1 PEREO3 Periodic Interval 3 Event Output Enable 3 1 PEREO4 Periodic Interval 4 Event Output Enable 4 1 PEREO5 Periodic Interval 5 Event Output Enable 5 1 PEREO6 Periodic Interval 6 Event Output Enable 6 1 PEREO7 Periodic Interval 7 Event Output Enable 7 1 CMPEO0 Compare 0 Event Output Enable 8 1 OVFEO Overflow Event Output Enable 15 1 INTENCLR MODE0 Interrupt Enable Clear 0x06 8 CMP0 Compare 0 Interrupt Enable 0 1 SYNCRDY Synchronization Ready Interrupt Enable 6 1 OVF Overflow Interrupt Enable 7 1 INTENSET MODE0 Interrupt Enable Set 0x07 8 CMP0 Compare 0 Interrupt Enable 0 1 SYNCRDY Synchronization Ready Interrupt Enable 6 1 OVF Overflow Interrupt Enable 7 1 INTFLAG MODE0 Interrupt Flag Status and Clear 0x08 8 CMP0 Compare 0 0 1 SYNCRDY Synchronization Ready 6 1 OVF Overflow 7 1 READREQ Read Request 0x02 16 0x0010 ADDR Address 0 6 read-only RCONT Read Continuously 14 1 RREQ Read Request 15 1 write-only STATUS Status 0x0A 8 SYNCBUSY Synchronization Busy 7 1 read-only MODE1 16-bit Counter with Two 16-bit Compares MODE0 RtcMode1 0x0 DBGCTRL Debug Control 0x0B 8 DBGRUN Run During Debug 0 1 FREQCORR Frequency Correction 0x0C 8 VALUE Correction Value 0 7 SIGN Correction Sign 7 1 2 0x2 COMP%s MODE1 Compare n Value 0x18 16 COMP Compare Value 0 16 COUNT MODE1 Counter Value 0x10 16 COUNT Counter Value 0 16 CTRL MODE1 Control 0x00 16 SWRST Software Reset 0 1 write-only ENABLE Enable 1 1 MODE Operating Mode 2 2 MODESelect COUNT32 Mode 0: 32-bit Counter 0x0 COUNT16 Mode 1: 16-bit Counter 0x1 CLOCK Mode 2: Clock/Calendar 0x2 PRESCALER Prescaler 8 4 PRESCALERSelect DIV1 CLK_RTC_CNT = GCLK_RTC/1 0x0 DIV2 CLK_RTC_CNT = GCLK_RTC/2 0x1 DIV4 CLK_RTC_CNT = GCLK_RTC/4 0x2 DIV8 CLK_RTC_CNT = GCLK_RTC/8 0x3 DIV16 CLK_RTC_CNT = GCLK_RTC/16 0x4 DIV32 CLK_RTC_CNT = GCLK_RTC/32 0x5 DIV64 CLK_RTC_CNT = GCLK_RTC/64 0x6 DIV128 CLK_RTC_CNT = GCLK_RTC/128 0x7 DIV256 CLK_RTC_CNT = GCLK_RTC/256 0x8 DIV512 CLK_RTC_CNT = GCLK_RTC/512 0x9 DIV1024 CLK_RTC_CNT = GCLK_RTC/1024 0xa EVCTRL MODE1 Event Control 0x04 16 PEREO0 Periodic Interval 0 Event Output Enable 0 1 PEREO1 Periodic Interval 1 Event Output Enable 1 1 PEREO2 Periodic Interval 2 Event Output Enable 2 1 PEREO3 Periodic Interval 3 Event Output Enable 3 1 PEREO4 Periodic Interval 4 Event Output Enable 4 1 PEREO5 Periodic Interval 5 Event Output Enable 5 1 PEREO6 Periodic Interval 6 Event Output Enable 6 1 PEREO7 Periodic Interval 7 Event Output Enable 7 1 CMPEO0 Compare 0 Event Output Enable 8 1 CMPEO1 Compare 1 Event Output Enable 9 1 OVFEO Overflow Event Output Enable 15 1 INTENCLR MODE1 Interrupt Enable Clear 0x06 8 CMP0 Compare 0 Interrupt Enable 0 1 CMP1 Compare 1 Interrupt Enable 1 1 SYNCRDY Synchronization Ready Interrupt Enable 6 1 OVF Overflow Interrupt Enable 7 1 INTENSET MODE1 Interrupt Enable Set 0x07 8 CMP0 Compare 0 Interrupt Enable 0 1 CMP1 Compare 1 Interrupt Enable 1 1 SYNCRDY Synchronization Ready Interrupt Enable 6 1 OVF Overflow Interrupt Enable 7 1 INTFLAG MODE1 Interrupt Flag Status and Clear 0x08 8 CMP0 Compare 0 0 1 CMP1 Compare 1 1 1 SYNCRDY Synchronization Ready 6 1 OVF Overflow 7 1 PER MODE1 Counter Period 0x14 16 PER Counter Period 0 16 READREQ Read Request 0x02 16 0x0010 ADDR Address 0 6 read-only RCONT Read Continuously 14 1 RREQ Read Request 15 1 write-only STATUS Status 0x0A 8 SYNCBUSY Synchronization Busy 7 1 read-only MODE2 Clock/Calendar with Alarm MODE0 RtcMode2 0x0 DBGCTRL Debug Control 0x0B 8 DBGRUN Run During Debug 0 1 FREQCORR Frequency Correction 0x0C 8 VALUE Correction Value 0 7 SIGN Correction Sign 7 1 CLOCK MODE2 Clock Value 0x10 32 SECOND Second 0 6 MINUTE Minute 6 6 HOUR Hour 12 5 HOURSelect PM Afternoon Hour 0x10 DAY Day 17 5 MONTH Month 22 4 YEAR Year 26 6 CTRL MODE2 Control 0x00 16 SWRST Software Reset 0 1 write-only ENABLE Enable 1 1 MODE Operating Mode 2 2 MODESelect COUNT32 Mode 0: 32-bit Counter 0x0 COUNT16 Mode 1: 16-bit Counter 0x1 CLOCK Mode 2: Clock/Calendar 0x2 CLKREP Clock Representation 6 1 MATCHCLR Clear on Match 7 1 PRESCALER Prescaler 8 4 PRESCALERSelect DIV1 CLK_RTC_CNT = GCLK_RTC/1 0x0 DIV2 CLK_RTC_CNT = GCLK_RTC/2 0x1 DIV4 CLK_RTC_CNT = GCLK_RTC/4 0x2 DIV8 CLK_RTC_CNT = GCLK_RTC/8 0x3 DIV16 CLK_RTC_CNT = GCLK_RTC/16 0x4 DIV32 CLK_RTC_CNT = GCLK_RTC/32 0x5 DIV64 CLK_RTC_CNT = GCLK_RTC/64 0x6 DIV128 CLK_RTC_CNT = GCLK_RTC/128 0x7 DIV256 CLK_RTC_CNT = GCLK_RTC/256 0x8 DIV512 CLK_RTC_CNT = GCLK_RTC/512 0x9 DIV1024 CLK_RTC_CNT = GCLK_RTC/1024 0xa EVCTRL MODE2 Event Control 0x04 16 PEREO0 Periodic Interval 0 Event Output Enable 0 1 PEREO1 Periodic Interval 1 Event Output Enable 1 1 PEREO2 Periodic Interval 2 Event Output Enable 2 1 PEREO3 Periodic Interval 3 Event Output Enable 3 1 PEREO4 Periodic Interval 4 Event Output Enable 4 1 PEREO5 Periodic Interval 5 Event Output Enable 5 1 PEREO6 Periodic Interval 6 Event Output Enable 6 1 PEREO7 Periodic Interval 7 Event Output Enable 7 1 ALARMEO0 Alarm 0 Event Output Enable 8 1 OVFEO Overflow Event Output Enable 15 1 INTENCLR MODE2 Interrupt Enable Clear 0x06 8 ALARM0 Alarm 0 Interrupt Enable 0 1 SYNCRDY Synchronization Ready Interrupt Enable 6 1 OVF Overflow Interrupt Enable 7 1 INTENSET MODE2 Interrupt Enable Set 0x07 8 ALARM0 Alarm 0 Interrupt Enable 0 1 SYNCRDY Synchronization Ready Interrupt Enable 6 1 OVF Overflow Interrupt Enable 7 1 INTFLAG MODE2 Interrupt Flag Status and Clear 0x08 8 ALARM0 Alarm 0 0 1 SYNCRDY Synchronization Ready 6 1 OVF Overflow 7 1 1 0x8 ALARM%s MODE2 Alarm n Value 0x18 32 SECOND Second 0 6 MINUTE Minute 6 6 HOUR Hour 12 5 DAY Day 17 5 MONTH Month 22 4 YEAR Year 26 6 1 0x8 MASK%s MODE2 Alarm n Mask 0x1C 8 SEL Alarm Mask Selection 0 3 SELSelect OFF Alarm Disabled 0x0 SS Match seconds only 0x1 MMSS Match seconds and minutes only 0x2 HHMMSS Match seconds, minutes, and hours only 0x3 DDHHMMSS Match seconds, minutes, hours, and days only 0x4 MMDDHHMMSS Match seconds, minutes, hours, days, and months only 0x5 YYMMDDHHMMSS Match seconds, minutes, hours, days, months, and years 0x6 READREQ Read Request 0x02 16 0x0010 ADDR Address 0 6 read-only RCONT Read Continuously 14 1 RREQ Read Request 15 1 write-only STATUS Status 0x0A 8 SYNCBUSY Synchronization Busy 7 1 read-only SERCOM0 2.0.0 Serial Communication Interface 0 SERCOM SERCOM_ 0x42000800 0 0x40 registers SERCOM0 9 I2CM I2C Master Mode SercomI2cm 0x0 ADDR I2CM Address 0x24 32 ADDR Address Value 0 11 LENEN Length Enable 13 1 HS High Speed Mode 14 1 TENBITEN Ten Bit Addressing Enable 15 1 LEN Length 16 8 BAUD I2CM Baud Rate 0x0C 32 BAUD Baud Rate Value 0 8 BAUDLOW Baud Rate Value Low 8 8 HSBAUD High Speed Baud Rate Value 16 8 HSBAUDLOW High Speed Baud Rate Value Low 24 8 CTRLA I2CM Control A 0x00 32 SWRST Software Reset 0 1 ENABLE Enable 1 1 MODE Operating Mode 2 3 MODESelect USART_EXT_CLK USART mode with external clock 0x0 USART_INT_CLK USART mode with internal clock 0x1 SPI_SLAVE SPI mode with external clock 0x2 SPI_MASTER SPI mode with internal clock 0x3 I2C_SLAVE I2C mode with external clock 0x4 I2C_MASTER I2C mode with internal clock 0x5 RUNSTDBY Run in Standby 7 1 PINOUT Pin Usage 16 1 SDAHOLD SDA Hold Time 20 2 MEXTTOEN Master SCL Low Extend Timeout 22 1 SEXTTOEN Slave SCL Low Extend Timeout 23 1 SPEED Transfer Speed 24 2 SCLSM SCL Clock Stretch Mode 27 1 INACTOUT Inactive Time-Out 28 2 LOWTOUTEN SCL Low Timeout Enable 30 1 CTRLB I2CM Control B 0x04 32 SMEN Smart Mode Enable 8 1 QCEN Quick Command Enable 9 1 CMD Command 16 2 write-only ACKACT Acknowledge Action 18 1 DATA I2CM Data 0x28 8 DATA Data Value 0 8 DBGCTRL I2CM Debug Control 0x30 8 DBGSTOP Debug Mode 0 1 INTENCLR I2CM Interrupt Enable Clear 0x14 8 MB Master On Bus Interrupt Disable 0 1 SB Slave On Bus Interrupt Disable 1 1 ERROR Combined Error Interrupt Disable 7 1 INTENSET I2CM Interrupt Enable Set 0x16 8 MB Master On Bus Interrupt Enable 0 1 SB Slave On Bus Interrupt Enable 1 1 ERROR Combined Error Interrupt Enable 7 1 INTFLAG I2CM Interrupt Flag Status and Clear 0x18 8 MB Master On Bus Interrupt 0 1 SB Slave On Bus Interrupt 1 1 ERROR Combined Error Interrupt 7 1 STATUS I2CM Status 0x1A 16 BUSERR Bus Error 0 1 ARBLOST Arbitration Lost 1 1 RXNACK Received Not Acknowledge 2 1 read-only BUSSTATE Bus State 4 2 LOWTOUT SCL Low Timeout 6 1 CLKHOLD Clock Hold 7 1 read-only MEXTTOUT Master SCL Low Extend Timeout 8 1 SEXTTOUT Slave SCL Low Extend Timeout 9 1 LENERR Length Error 10 1 SYNCBUSY I2CM Syncbusy 0x1C 32 read-only SWRST Software Reset Synchronization Busy 0 1 read-only ENABLE SERCOM Enable Synchronization Busy 1 1 read-only SYSOP System Operation Synchronization Busy 2 1 read-only I2CS I2C Slave Mode I2CM SercomI2cs 0x0 ADDR I2CS Address 0x24 32 GENCEN General Call Address Enable 0 1 ADDR Address Value 1 10 TENBITEN Ten Bit Addressing Enable 15 1 ADDRMASK Address Mask 17 10 CTRLA I2CS Control A 0x00 32 SWRST Software Reset 0 1 ENABLE Enable 1 1 MODE Operating Mode 2 3 MODESelect USART_EXT_CLK USART mode with external clock 0x0 USART_INT_CLK USART mode with internal clock 0x1 SPI_SLAVE SPI mode with external clock 0x2 SPI_MASTER SPI mode with internal clock 0x3 I2C_SLAVE I2C mode with external clock 0x4 I2C_MASTER I2C mode with internal clock 0x5 RUNSTDBY Run during Standby 7 1 PINOUT Pin Usage 16 1 SDAHOLD SDA Hold Time 20 2 SEXTTOEN Slave SCL Low Extend Timeout 23 1 SPEED Transfer Speed 24 2 SCLSM SCL Clock Stretch Mode 27 1 LOWTOUTEN SCL Low Timeout Enable 30 1 CTRLB I2CS Control B 0x04 32 SMEN Smart Mode Enable 8 1 GCMD PMBus Group Command 9 1 AACKEN Automatic Address Acknowledge 10 1 AMODE Address Mode 14 2 CMD Command 16 2 write-only ACKACT Acknowledge Action 18 1 DATA I2CS Data 0x28 8 DATA Data Value 0 8 DBGCTRL I2CS Debug Control 0x30 8 DBGSTOP Debug Mode 0 1 INTENCLR I2CS Interrupt Enable Clear 0x14 8 PREC Stop Received Interrupt Disable 0 1 AMATCH Address Match Interrupt Disable 1 1 DRDY Data Interrupt Disable 2 1 ERROR Combined Error Interrupt Disable 7 1 INTENSET I2CS Interrupt Enable Set 0x16 8 PREC Stop Received Interrupt Enable 0 1 AMATCH Address Match Interrupt Enable 1 1 DRDY Data Interrupt Enable 2 1 ERROR Combined Error Interrupt Enable 7 1 INTFLAG I2CS Interrupt Flag Status and Clear 0x18 8 PREC Stop Received Interrupt 0 1 AMATCH Address Match Interrupt 1 1 DRDY Data Interrupt 2 1 ERROR Combined Error Interrupt 7 1 STATUS I2CS Status 0x1A 16 BUSERR Bus Error 0 1 COLL Transmit Collision 1 1 RXNACK Received Not Acknowledge 2 1 read-only DIR Read/Write Direction 3 1 read-only SR Repeated Start 4 1 read-only LOWTOUT SCL Low Timeout 6 1 CLKHOLD Clock Hold 7 1 read-only SEXTTOUT Slave SCL Low Extend Timeout 9 1 HS High Speed 10 1 SYNCBUSY I2CS Syncbusy 0x1C 32 read-only SWRST Software Reset Synchronization Busy 0 1 read-only ENABLE SERCOM Enable Synchronization Busy 1 1 read-only SPI SPI Mode I2CM SercomSpi 0x0 ADDR SPI Address 0x24 32 ADDR Address Value 0 8 ADDRMASK Address Mask 16 8 BAUD SPI Baud Rate 0x0C 8 BAUD Baud Rate Value 0 8 CTRLA SPI Control A 0x00 32 SWRST Software Reset 0 1 ENABLE Enable 1 1 MODE Operating Mode 2 3 MODESelect USART_EXT_CLK USART mode with external clock 0x0 USART_INT_CLK USART mode with internal clock 0x1 SPI_SLAVE SPI mode with external clock 0x2 SPI_MASTER SPI mode with internal clock 0x3 I2C_SLAVE I2C mode with external clock 0x4 I2C_MASTER I2C mode with internal clock 0x5 RUNSTDBY Run during Standby 7 1 IBON Immediate Buffer Overflow Notification 8 1 DOPO Data Out Pinout 16 2 DIPO Data In Pinout 20 2 FORM Frame Format 24 4 CPHA Clock Phase 28 1 CPOL Clock Polarity 29 1 DORD Data Order 30 1 CTRLB SPI Control B 0x04 32 CHSIZE Character Size 0 3 PLOADEN Data Preload Enable 6 1 SSDE Slave Select Low Detect Enable 9 1 MSSEN Master Slave Select Enable 13 1 AMODE Address Mode 14 2 RXEN Receiver Enable 17 1 DATA SPI Data 0x28 32 DATA Data Value 0 9 DBGCTRL SPI Debug Control 0x30 8 DBGSTOP Debug Mode 0 1 INTENCLR SPI Interrupt Enable Clear 0x14 8 DRE Data Register Empty Interrupt Disable 0 1 TXC Transmit Complete Interrupt Disable 1 1 RXC Receive Complete Interrupt Disable 2 1 SSL Slave Select Low Interrupt Disable 3 1 ERROR Combined Error Interrupt Disable 7 1 INTENSET SPI Interrupt Enable Set 0x16 8 DRE Data Register Empty Interrupt Enable 0 1 TXC Transmit Complete Interrupt Enable 1 1 RXC Receive Complete Interrupt Enable 2 1 SSL Slave Select Low Interrupt Enable 3 1 ERROR Combined Error Interrupt Enable 7 1 INTFLAG SPI Interrupt Flag Status and Clear 0x18 8 DRE Data Register Empty Interrupt 0 1 read-only TXC Transmit Complete Interrupt 1 1 RXC Receive Complete Interrupt 2 1 read-only SSL Slave Select Low Interrupt Flag 3 1 ERROR Combined Error Interrupt 7 1 STATUS SPI Status 0x1A 16 BUFOVF Buffer Overflow 2 1 SYNCBUSY SPI Syncbusy 0x1C 32 read-only SWRST Software Reset Synchronization Busy 0 1 read-only ENABLE SERCOM Enable Synchronization Busy 1 1 read-only CTRLB CTRLB Synchronization Busy 2 1 read-only USART USART Mode I2CM SercomUsart 0x0 BAUD USART Baud Rate DEFAULT_MODE 0x0C 16 BAUD Baud Rate Value 0 16 BAUD USART Baud Rate FRAC_MODE 0x0C 16 BAUD Baud Rate Value 0 13 FP Fractional Part 13 3 BAUD USART Baud Rate FRACFP_MODE 0x0C 16 BAUD Baud Rate Value 0 13 FP Fractional Part 13 3 BAUD USART Baud Rate USARTFP_MODE 0x0C 16 BAUD Baud Rate Value 0 16 CTRLA USART Control A 0x00 32 SWRST Software Reset 0 1 ENABLE Enable 1 1 MODE Operating Mode 2 3 MODESelect USART_EXT_CLK USART mode with external clock 0x0 USART_INT_CLK USART mode with internal clock 0x1 SPI_SLAVE SPI mode with external clock 0x2 SPI_MASTER SPI mode with internal clock 0x3 I2C_SLAVE I2C mode with external clock 0x4 I2C_MASTER I2C mode with internal clock 0x5 RUNSTDBY Run during Standby 7 1 IBON Immediate Buffer Overflow Notification 8 1 SAMPR Sample 13 3 TXPO Transmit Data Pinout 16 2 RXPO Receive Data Pinout 20 2 SAMPA Sample Adjustment 22 2 FORM Frame Format 24 4 CMODE Communication Mode 28 1 CPOL Clock Polarity 29 1 DORD Data Order 30 1 CTRLB USART Control B 0x04 32 CHSIZE Character Size 0 3 SBMODE Stop Bit Mode 6 1 COLDEN Collision Detection Enable 8 1 SFDE Start of Frame Detection Enable 9 1 ENC Encoding Format 10 1 PMODE Parity Mode 13 1 TXEN Transmitter Enable 16 1 RXEN Receiver Enable 17 1 DATA USART Data 0x28 16 DATA Data Value 0 9 DBGCTRL USART Debug Control 0x30 8 DBGSTOP Debug Mode 0 1 INTENCLR USART Interrupt Enable Clear 0x14 8 DRE Data Register Empty Interrupt Disable 0 1 TXC Transmit Complete Interrupt Disable 1 1 RXC Receive Complete Interrupt Disable 2 1 RXS Receive Start Interrupt Disable 3 1 CTSIC Clear To Send Input Change Interrupt Disable 4 1 RXBRK Break Received Interrupt Disable 5 1 ERROR Combined Error Interrupt Disable 7 1 INTENSET USART Interrupt Enable Set 0x16 8 DRE Data Register Empty Interrupt Enable 0 1 TXC Transmit Complete Interrupt Enable 1 1 RXC Receive Complete Interrupt Enable 2 1 RXS Receive Start Interrupt Enable 3 1 CTSIC Clear To Send Input Change Interrupt Enable 4 1 RXBRK Break Received Interrupt Enable 5 1 ERROR Combined Error Interrupt Enable 7 1 INTFLAG USART Interrupt Flag Status and Clear 0x18 8 DRE Data Register Empty Interrupt 0 1 read-only TXC Transmit Complete Interrupt 1 1 RXC Receive Complete Interrupt 2 1 read-only RXS Receive Start Interrupt 3 1 write-only CTSIC Clear To Send Input Change Interrupt 4 1 RXBRK Break Received Interrupt 5 1 ERROR Combined Error Interrupt 7 1 RXPL USART Receive Pulse Length 0x0E 8 RXPL Receive Pulse Length 0 8 STATUS USART Status 0x1A 16 PERR Parity Error 0 1 FERR Frame Error 1 1 BUFOVF Buffer Overflow 2 1 CTS Clear To Send 3 1 read-only ISF Inconsistent Sync Field 4 1 COLL Collision Detected 5 1 SYNCBUSY USART Syncbusy 0x1C 32 read-only SWRST Software Reset Synchronization Busy 0 1 read-only ENABLE SERCOM Enable Synchronization Busy 1 1 read-only CTRLB CTRLB Synchronization Busy 2 1 read-only SERCOM1 Serial Communication Interface 1 0x42000C00 SERCOM1 10 SERCOM2 Serial Communication Interface 2 0x42001000 SERCOM2 11 SERCOM3 Serial Communication Interface 3 0x42001400 SERCOM3 12 SERCOM4 Serial Communication Interface 4 0x42001800 SERCOM4 13 SERCOM5 Serial Communication Interface 5 0x42001C00 SERCOM5 14 SYSCTRL 2.0.1 System Control SYSCTRL SYSCTRL_ 0x40000800 0 0x80 registers SYSCTRL 1 BOD33 3.3V Brown-Out Detector (BOD33) Control 0x34 32 ENABLE Enable 1 1 HYST Hysteresis 2 1 ACTION BOD33 Action 3 2 ACTIONSelect NONE No action 0x0 RESET The BOD33 generates a reset 0x1 INTERRUPT The BOD33 generates an interrupt 0x2 RUNSTDBY Run in Standby 6 1 MODE Operation Mode 8 1 CEN Clock Enable 9 1 PSEL Prescaler Select 12 4 PSELSelect DIV2 Divide clock by 2 0x0 DIV4 Divide clock by 4 0x1 DIV8 Divide clock by 8 0x2 DIV16 Divide clock by 16 0x3 DIV32 Divide clock by 32 0x4 DIV64 Divide clock by 64 0x5 DIV128 Divide clock by 128 0x6 DIV256 Divide clock by 256 0x7 DIV512 Divide clock by 512 0x8 DIV1K Divide clock by 1024 0x9 DIV2K Divide clock by 2048 0xa DIV4K Divide clock by 4096 0xb DIV8K Divide clock by 8192 0xc DIV16K Divide clock by 16384 0xd DIV32K Divide clock by 32768 0xe DIV64K Divide clock by 65536 0xf LEVEL BOD33 Threshold Level 16 6 DFLLCTRL DFLL48M Control 0x24 16 0x0080 ENABLE DFLL Enable 1 1 MODE Operating Mode Selection 2 1 STABLE Stable DFLL Frequency 3 1 LLAW Lose Lock After Wake 4 1 USBCRM USB Clock Recovery Mode 5 1 RUNSTDBY Run in Standby 6 1 ONDEMAND On Demand Control 7 1 CCDIS Chill Cycle Disable 8 1 QLDIS Quick Lock Disable 9 1 BPLCKC Bypass Coarse Lock 10 1 WAITLOCK Wait Lock 11 1 DFLLMUL DFLL48M Multiplier 0x2C 32 MUL DFLL Multiply Factor 0 16 FSTEP Fine Maximum Step 16 10 CSTEP Coarse Maximum Step 26 6 DFLLSYNC DFLL48M Synchronization 0x30 8 READREQ Read Request 7 1 write-only DFLLVAL DFLL48M Value 0x28 32 FINE Fine Value 0 10 COARSE Coarse Value 10 6 DIFF Multiplication Ratio Difference 16 16 read-only DPLLCTRLA DPLL Control A 0x44 8 0x80 ENABLE DPLL Enable 1 1 RUNSTDBY Run in Standby 6 1 ONDEMAND On Demand Clock Activation 7 1 DPLLCTRLB DPLL Control B 0x4C 32 FILTER Proportional Integral Filter Selection 0 2 FILTERSelect DEFAULT Default filter mode 0x0 LBFILT Low bandwidth filter 0x1 HBFILT High bandwidth filter 0x2 HDFILT High damping filter 0x3 LPEN Low-Power Enable 2 1 WUF Wake Up Fast 3 1 REFCLK Reference Clock Selection 4 2 REFCLKSelect REF0 CLK_DPLL_REF0 clock reference 0x0 REF1 CLK_DPLL_REF1 clock reference 0x1 GCLK GCLK_DPLL clock reference 0x2 LTIME Lock Time 8 3 LTIMESelect 0x0 Default No time-out 0x0 0x4 8MS Time-out if no lock within 8 ms 0x4 0x5 9MS Time-out if no lock within 9 ms 0x5 0x6 10MS Time-out if no lock within 10 ms 0x6 0x7 11MS Time-out if no lock within 11 ms 0x7 LBYPASS Lock Bypass 12 1 DIV Clock Divider 16 11 DPLLRATIO DPLL Ratio Control 0x48 32 LDR Loop Divider Ratio 0 12 LDRFRAC Loop Divider Ratio Fractional Part 16 4 DPLLSTATUS DPLL Status 0x50 8 read-only LOCK DPLL Lock Status 0 1 read-only CLKRDY Output Clock Ready 1 1 read-only ENABLE DPLL Enable 2 1 read-only DIV Divider Enable 3 1 read-only INTENCLR Interrupt Enable Clear 0x00 32 XOSCRDY XOSC Ready Interrupt Enable 0 1 XOSC32KRDY XOSC32K Ready Interrupt Enable 1 1 OSC32KRDY OSC32K Ready Interrupt Enable 2 1 OSC8MRDY OSC8M Ready Interrupt Enable 3 1 DFLLRDY DFLL Ready Interrupt Enable 4 1 DFLLOOB DFLL Out Of Bounds Interrupt Enable 5 1 DFLLLCKF DFLL Lock Fine Interrupt Enable 6 1 DFLLLCKC DFLL Lock Coarse Interrupt Enable 7 1 DFLLRCS DFLL Reference Clock Stopped Interrupt Enable 8 1 BOD33RDY BOD33 Ready Interrupt Enable 9 1 BOD33DET BOD33 Detection Interrupt Enable 10 1 B33SRDY BOD33 Synchronization Ready Interrupt Enable 11 1 DPLLLCKR DPLL Lock Rise Interrupt Enable 15 1 DPLLLCKF DPLL Lock Fall Interrupt Enable 16 1 DPLLLTO DPLL Lock Timeout Interrupt Enable 17 1 INTENSET Interrupt Enable Set 0x04 32 XOSCRDY XOSC Ready Interrupt Enable 0 1 XOSC32KRDY XOSC32K Ready Interrupt Enable 1 1 OSC32KRDY OSC32K Ready Interrupt Enable 2 1 OSC8MRDY OSC8M Ready Interrupt Enable 3 1 DFLLRDY DFLL Ready Interrupt Enable 4 1 DFLLOOB DFLL Out Of Bounds Interrupt Enable 5 1 DFLLLCKF DFLL Lock Fine Interrupt Enable 6 1 DFLLLCKC DFLL Lock Coarse Interrupt Enable 7 1 DFLLRCS DFLL Reference Clock Stopped Interrupt Enable 8 1 BOD33RDY BOD33 Ready Interrupt Enable 9 1 BOD33DET BOD33 Detection Interrupt Enable 10 1 B33SRDY BOD33 Synchronization Ready Interrupt Enable 11 1 DPLLLCKR DPLL Lock Rise Interrupt Enable 15 1 DPLLLCKF DPLL Lock Fall Interrupt Enable 16 1 DPLLLTO DPLL Lock Timeout Interrupt Enable 17 1 INTFLAG Interrupt Flag Status and Clear 0x08 32 XOSCRDY XOSC Ready 0 1 XOSC32KRDY XOSC32K Ready 1 1 OSC32KRDY OSC32K Ready 2 1 OSC8MRDY OSC8M Ready 3 1 DFLLRDY DFLL Ready 4 1 DFLLOOB DFLL Out Of Bounds 5 1 DFLLLCKF DFLL Lock Fine 6 1 DFLLLCKC DFLL Lock Coarse 7 1 DFLLRCS DFLL Reference Clock Stopped 8 1 BOD33RDY BOD33 Ready 9 1 BOD33DET BOD33 Detection 10 1 B33SRDY BOD33 Synchronization Ready 11 1 DPLLLCKR DPLL Lock Rise 15 1 DPLLLCKF DPLL Lock Fall 16 1 DPLLLTO DPLL Lock Timeout 17 1 OSCULP32K 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control 0x1C 8 0x1F CALIB Oscillator Calibration 0 5 WRTLOCK Write Lock 7 1 OSC8M 8MHz Internal Oscillator (OSC8M) Control 0x20 32 0x87070382 ENABLE Oscillator Enable 1 1 RUNSTDBY Run in Standby 6 1 ONDEMAND On Demand Control 7 1 PRESC Oscillator Prescaler 8 2 PRESCSelect 0x0 1 0x0 0x1 2 0x1 0x2 4 0x2 0x3 8 0x3 CALIB Oscillator Calibration 16 12 FRANGE Oscillator Frequency Range 30 2 FRANGESelect 0x0 4 to 6MHz 0x0 0x1 6 to 8MHz 0x1 0x2 8 to 11MHz 0x2 0x3 11 to 15MHz 0x3 OSC32K 32kHz Internal Oscillator (OSC32K) Control 0x18 32 0x003F0080 ENABLE Oscillator Enable 1 1 EN32K 32kHz Output Enable 2 1 EN1K 1kHz Output Enable 3 1 RUNSTDBY Run in Standby 6 1 ONDEMAND On Demand Control 7 1 STARTUP Oscillator Start-Up Time 8 3 WRTLOCK Write Lock 12 1 CALIB Oscillator Calibration 16 7 PCLKSR Power and Clocks Status 0x0C 32 read-only XOSCRDY XOSC Ready 0 1 read-only XOSC32KRDY XOSC32K Ready 1 1 read-only OSC32KRDY OSC32K Ready 2 1 read-only OSC8MRDY OSC8M Ready 3 1 read-only DFLLRDY DFLL Ready 4 1 read-only DFLLOOB DFLL Out Of Bounds 5 1 read-only DFLLLCKF DFLL Lock Fine 6 1 read-only DFLLLCKC DFLL Lock Coarse 7 1 read-only DFLLRCS DFLL Reference Clock Stopped 8 1 read-only BOD33RDY BOD33 Ready 9 1 read-only BOD33DET BOD33 Detection 10 1 read-only B33SRDY BOD33 Synchronization Ready 11 1 read-only DPLLLCKR DPLL Lock Rise 15 1 read-only DPLLLCKF DPLL Lock Fall 16 1 read-only DPLLLTO DPLL Lock Timeout 17 1 read-only VREF Voltage References System (VREF) Control 0x40 32 TSEN Temperature Sensor Enable 1 1 BGOUTEN Bandgap Output Enable 2 1 CALIB Bandgap Voltage Generator Calibration 16 11 XOSC External Multipurpose Crystal Oscillator (XOSC) Control 0x10 16 0x0080 ENABLE Oscillator Enable 1 1 XTALEN Crystal Oscillator Enable 2 1 RUNSTDBY Run in Standby 6 1 ONDEMAND On Demand Control 7 1 GAIN Oscillator Gain 8 3 GAINSelect 0x0 2MHz 0x0 0x1 4MHz 0x1 0x2 8MHz 0x2 0x3 16MHz 0x3 0x4 30MHz 0x4 AMPGC Automatic Amplitude Gain Control 11 1 STARTUP Start-Up Time 12 4 XOSC32K 32kHz External Crystal Oscillator (XOSC32K) Control 0x14 16 0x0080 ENABLE Oscillator Enable 1 1 XTALEN Crystal Oscillator Enable 2 1 EN32K 32kHz Output Enable 3 1 EN1K 1kHz Output Enable 4 1 AAMPEN Automatic Amplitude Control Enable 5 1 RUNSTDBY Run in Standby 6 1 ONDEMAND On Demand Control 7 1 STARTUP Oscillator Start-Up Time 8 3 WRTLOCK Write Lock 12 1 TC3 1.2.1 Basic Timer Counter 3 TC TC_ 0x42002C00 0 0x040 registers TC3 18 COUNT8 8-bit Counter Mode TcCount8 0x0 2 0x1 CC%s COUNT8 Compare/Capture 0x18 8 CC Compare/Capture Value 0 8 COUNT COUNT8 Counter Value 0x10 8 COUNT Counter Value 0 8 PER COUNT8 Period Value 0x14 8 0xFF PER Period Value 0 8 CTRLA Control A 0x00 16 SWRST Software Reset 0 1 write-only ENABLE Enable 1 1 MODE TC Mode 2 2 MODESelect COUNT16 Counter in 16-bit mode 0x0 COUNT8 Counter in 8-bit mode 0x1 COUNT32 Counter in 32-bit mode 0x2 WAVEGEN Waveform Generation Operation 5 2 WAVEGENSelect NFRQ 0x0 MFRQ 0x1 NPWM 0x2 MPWM 0x3 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 Prescaler: GCLK_TC 0x0 DIV2 Prescaler: GCLK_TC/2 0x1 DIV4 Prescaler: GCLK_TC/4 0x2 DIV8 Prescaler: GCLK_TC/8 0x3 DIV16 Prescaler: GCLK_TC/16 0x4 DIV64 Prescaler: GCLK_TC/64 0x5 DIV256 Prescaler: GCLK_TC/256 0x6 DIV1024 Prescaler: GCLK_TC/1024 0x7 RUNSTDBY Run in Standby 11 1 PRESCSYNC Prescaler and Counter Synchronization 12 2 PRESCSYNCSelect GCLK Reload or reset the counter on next generic clock 0x0 PRESC Reload or reset the counter on next prescaler clock 0x1 RESYNC Reload or reset the counter on next generic clock. Reset the prescaler counter 0x2 CTRLBCLR Control B Clear 0x04 8 0x02 DIR Counter Direction 0 1 ONESHOT One-Shot 2 1 CMD Command 6 2 CMDSelect NONE No action 0x0 RETRIGGER Force a start, restart or retrigger 0x1 STOP Force a stop 0x2 CTRLBSET Control B Set 0x05 8 DIR Counter Direction 0 1 ONESHOT One-Shot 2 1 CMD Command 6 2 CMDSelect NONE No action 0x0 RETRIGGER Force a start, restart or retrigger 0x1 STOP Force a stop 0x2 CTRLC Control C 0x06 8 INVEN0 Output Waveform 0 Invert Enable 0 1 INVEN1 Output Waveform 1 Invert Enable 1 1 CPTEN0 Capture Channel 0 Enable 4 1 CPTEN1 Capture Channel 1 Enable 5 1 DBGCTRL Debug Control 0x08 8 DBGRUN Debug Run Mode 0 1 EVCTRL Event Control 0x0A 16 EVACT Event Action 0 3 EVACTSelect OFF Event action disabled 0x0 RETRIGGER Start, restart or retrigger TC on event 0x1 COUNT Count on event 0x2 START Start TC on event 0x3 PPW Period captured in CC0, pulse width in CC1 0x5 PWP Period captured in CC1, pulse width in CC0 0x6 TCINV TC Inverted Event Input 4 1 TCEI TC Event Input 5 1 OVFEO Overflow/Underflow Event Output Enable 8 1 MCEO0 Match or Capture Channel 0 Event Output Enable 12 1 MCEO1 Match or Capture Channel 1 Event Output Enable 13 1 INTENCLR Interrupt Enable Clear 0x0C 8 OVF Overflow Interrupt Enable 0 1 ERR Error Interrupt Enable 1 1 SYNCRDY Synchronization Ready Interrupt Enable 3 1 MC0 Match or Capture Channel 0 Interrupt Enable 4 1 MC1 Match or Capture Channel 1 Interrupt Enable 5 1 INTENSET Interrupt Enable Set 0x0D 8 OVF Overflow Interrupt Enable 0 1 ERR Error Interrupt Enable 1 1 SYNCRDY Synchronization Ready Interrupt Enable 3 1 MC0 Match or Capture Channel 0 Interrupt Enable 4 1 MC1 Match or Capture Channel 1 Interrupt Enable 5 1 INTFLAG Interrupt Flag Status and Clear 0x0E 8 OVF Overflow 0 1 ERR Error 1 1 SYNCRDY Synchronization Ready 3 1 MC0 Match or Capture Channel 0 4 1 MC1 Match or Capture Channel 1 5 1 READREQ Read Request 0x02 16 ADDR Address 0 5 RCONT Read Continuously 14 1 RREQ Read Request 15 1 STATUS Status 0x0F 8 read-only 0x08 STOP Stop 3 1 read-only SLAVE Slave 4 1 read-only SYNCBUSY Synchronization Busy 7 1 read-only COUNT16 16-bit Counter Mode COUNT8 TcCount16 0x0 2 0x2 CC%s COUNT16 Compare/Capture 0x18 16 CC Compare/Capture Value 0 16 COUNT COUNT16 Counter Value 0x10 16 COUNT Count Value 0 16 CTRLA Control A 0x00 16 SWRST Software Reset 0 1 write-only ENABLE Enable 1 1 MODE TC Mode 2 2 MODESelect COUNT16 Counter in 16-bit mode 0x0 COUNT8 Counter in 8-bit mode 0x1 COUNT32 Counter in 32-bit mode 0x2 WAVEGEN Waveform Generation Operation 5 2 WAVEGENSelect NFRQ 0x0 MFRQ 0x1 NPWM 0x2 MPWM 0x3 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 Prescaler: GCLK_TC 0x0 DIV2 Prescaler: GCLK_TC/2 0x1 DIV4 Prescaler: GCLK_TC/4 0x2 DIV8 Prescaler: GCLK_TC/8 0x3 DIV16 Prescaler: GCLK_TC/16 0x4 DIV64 Prescaler: GCLK_TC/64 0x5 DIV256 Prescaler: GCLK_TC/256 0x6 DIV1024 Prescaler: GCLK_TC/1024 0x7 RUNSTDBY Run in Standby 11 1 PRESCSYNC Prescaler and Counter Synchronization 12 2 PRESCSYNCSelect GCLK Reload or reset the counter on next generic clock 0x0 PRESC Reload or reset the counter on next prescaler clock 0x1 RESYNC Reload or reset the counter on next generic clock. Reset the prescaler counter 0x2 CTRLBCLR Control B Clear 0x04 8 0x02 DIR Counter Direction 0 1 ONESHOT One-Shot 2 1 CMD Command 6 2 CMDSelect NONE No action 0x0 RETRIGGER Force a start, restart or retrigger 0x1 STOP Force a stop 0x2 CTRLBSET Control B Set 0x05 8 DIR Counter Direction 0 1 ONESHOT One-Shot 2 1 CMD Command 6 2 CMDSelect NONE No action 0x0 RETRIGGER Force a start, restart or retrigger 0x1 STOP Force a stop 0x2 CTRLC Control C 0x06 8 INVEN0 Output Waveform 0 Invert Enable 0 1 INVEN1 Output Waveform 1 Invert Enable 1 1 CPTEN0 Capture Channel 0 Enable 4 1 CPTEN1 Capture Channel 1 Enable 5 1 DBGCTRL Debug Control 0x08 8 DBGRUN Debug Run Mode 0 1 EVCTRL Event Control 0x0A 16 EVACT Event Action 0 3 EVACTSelect OFF Event action disabled 0x0 RETRIGGER Start, restart or retrigger TC on event 0x1 COUNT Count on event 0x2 START Start TC on event 0x3 PPW Period captured in CC0, pulse width in CC1 0x5 PWP Period captured in CC1, pulse width in CC0 0x6 TCINV TC Inverted Event Input 4 1 TCEI TC Event Input 5 1 OVFEO Overflow/Underflow Event Output Enable 8 1 MCEO0 Match or Capture Channel 0 Event Output Enable 12 1 MCEO1 Match or Capture Channel 1 Event Output Enable 13 1 INTENCLR Interrupt Enable Clear 0x0C 8 OVF Overflow Interrupt Enable 0 1 ERR Error Interrupt Enable 1 1 SYNCRDY Synchronization Ready Interrupt Enable 3 1 MC0 Match or Capture Channel 0 Interrupt Enable 4 1 MC1 Match or Capture Channel 1 Interrupt Enable 5 1 INTENSET Interrupt Enable Set 0x0D 8 OVF Overflow Interrupt Enable 0 1 ERR Error Interrupt Enable 1 1 SYNCRDY Synchronization Ready Interrupt Enable 3 1 MC0 Match or Capture Channel 0 Interrupt Enable 4 1 MC1 Match or Capture Channel 1 Interrupt Enable 5 1 INTFLAG Interrupt Flag Status and Clear 0x0E 8 OVF Overflow 0 1 ERR Error 1 1 SYNCRDY Synchronization Ready 3 1 MC0 Match or Capture Channel 0 4 1 MC1 Match or Capture Channel 1 5 1 READREQ Read Request 0x02 16 ADDR Address 0 5 RCONT Read Continuously 14 1 RREQ Read Request 15 1 STATUS Status 0x0F 8 read-only 0x08 STOP Stop 3 1 read-only SLAVE Slave 4 1 read-only SYNCBUSY Synchronization Busy 7 1 read-only COUNT32 32-bit Counter Mode COUNT8 TcCount32 0x0 2 0x4 CC%s COUNT32 Compare/Capture 0x18 32 CC Compare/Capture Value 0 32 COUNT COUNT32 Counter Value 0x10 32 COUNT Count Value 0 32 CTRLA Control A 0x00 16 SWRST Software Reset 0 1 write-only ENABLE Enable 1 1 MODE TC Mode 2 2 MODESelect COUNT16 Counter in 16-bit mode 0x0 COUNT8 Counter in 8-bit mode 0x1 COUNT32 Counter in 32-bit mode 0x2 WAVEGEN Waveform Generation Operation 5 2 WAVEGENSelect NFRQ 0x0 MFRQ 0x1 NPWM 0x2 MPWM 0x3 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 Prescaler: GCLK_TC 0x0 DIV2 Prescaler: GCLK_TC/2 0x1 DIV4 Prescaler: GCLK_TC/4 0x2 DIV8 Prescaler: GCLK_TC/8 0x3 DIV16 Prescaler: GCLK_TC/16 0x4 DIV64 Prescaler: GCLK_TC/64 0x5 DIV256 Prescaler: GCLK_TC/256 0x6 DIV1024 Prescaler: GCLK_TC/1024 0x7 RUNSTDBY Run in Standby 11 1 PRESCSYNC Prescaler and Counter Synchronization 12 2 PRESCSYNCSelect GCLK Reload or reset the counter on next generic clock 0x0 PRESC Reload or reset the counter on next prescaler clock 0x1 RESYNC Reload or reset the counter on next generic clock. Reset the prescaler counter 0x2 CTRLBCLR Control B Clear 0x04 8 0x02 DIR Counter Direction 0 1 ONESHOT One-Shot 2 1 CMD Command 6 2 CMDSelect NONE No action 0x0 RETRIGGER Force a start, restart or retrigger 0x1 STOP Force a stop 0x2 CTRLBSET Control B Set 0x05 8 DIR Counter Direction 0 1 ONESHOT One-Shot 2 1 CMD Command 6 2 CMDSelect NONE No action 0x0 RETRIGGER Force a start, restart or retrigger 0x1 STOP Force a stop 0x2 CTRLC Control C 0x06 8 INVEN0 Output Waveform 0 Invert Enable 0 1 INVEN1 Output Waveform 1 Invert Enable 1 1 CPTEN0 Capture Channel 0 Enable 4 1 CPTEN1 Capture Channel 1 Enable 5 1 DBGCTRL Debug Control 0x08 8 DBGRUN Debug Run Mode 0 1 EVCTRL Event Control 0x0A 16 EVACT Event Action 0 3 EVACTSelect OFF Event action disabled 0x0 RETRIGGER Start, restart or retrigger TC on event 0x1 COUNT Count on event 0x2 START Start TC on event 0x3 PPW Period captured in CC0, pulse width in CC1 0x5 PWP Period captured in CC1, pulse width in CC0 0x6 TCINV TC Inverted Event Input 4 1 TCEI TC Event Input 5 1 OVFEO Overflow/Underflow Event Output Enable 8 1 MCEO0 Match or Capture Channel 0 Event Output Enable 12 1 MCEO1 Match or Capture Channel 1 Event Output Enable 13 1 INTENCLR Interrupt Enable Clear 0x0C 8 OVF Overflow Interrupt Enable 0 1 ERR Error Interrupt Enable 1 1 SYNCRDY Synchronization Ready Interrupt Enable 3 1 MC0 Match or Capture Channel 0 Interrupt Enable 4 1 MC1 Match or Capture Channel 1 Interrupt Enable 5 1 INTENSET Interrupt Enable Set 0x0D 8 OVF Overflow Interrupt Enable 0 1 ERR Error Interrupt Enable 1 1 SYNCRDY Synchronization Ready Interrupt Enable 3 1 MC0 Match or Capture Channel 0 Interrupt Enable 4 1 MC1 Match or Capture Channel 1 Interrupt Enable 5 1 INTFLAG Interrupt Flag Status and Clear 0x0E 8 OVF Overflow 0 1 ERR Error 1 1 SYNCRDY Synchronization Ready 3 1 MC0 Match or Capture Channel 0 4 1 MC1 Match or Capture Channel 1 5 1 READREQ Read Request 0x02 16 ADDR Address 0 5 RCONT Read Continuously 14 1 RREQ Read Request 15 1 STATUS Status 0x0F 8 read-only 0x08 STOP Stop 3 1 read-only SLAVE Slave 4 1 read-only SYNCBUSY Synchronization Busy 7 1 read-only TC4 Basic Timer Counter 4 0x42003000 TC4 19 TC5 Basic Timer Counter 5 0x42003400 TC5 20 TCC0 1.0.1 Timer Counter Control 0 TCC TCC_ 0x42002000 0 0x090 registers TCC0 15 4 0x4 CC%s Compare and Capture 0x44 32 CC Compare and Capture value 0 24 4 0x4 CCB%s Compare and Capture Buffer 0x70 32 CCB Compare and Capture buffer value 0 24 COUNT Count 0x34 32 COUNT Count Value 0 24 CTRLA Control A 0x00 32 SWRST Software Reset 0 1 ENABLE Enable 1 1 RESOLUTION Enhanced Resolution 5 2 RESOLUTIONSelect None 0x0 DITH4 0x1 DITH5 0x2 DITH6 0x3 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 0x0 DIV2 0x1 DIV4 0x2 DIV8 0x3 DIV16 0x4 DIV64 0x5 DIV256 0x6 DIV1024 0x7 RUNSTDBY Run in Standby 11 1 PRESCSYNC Prescaler and Counter Synchronization Selection 12 2 PRESCSYNCSelect GCLK 0x0 PRESC 0x1 RESYNC 0x2 ALOCK Auto Lock 14 1 MSYNC Master Synchronization 15 1 CPTEN0 Capture Channel 0 Enable 24 1 CPTEN1 Capture Channel 1 Enable 25 1 CPTEN2 Capture Channel 2 Enable 26 1 CPTEN3 Capture Channel 3 Enable 27 1 CTRLBCLR Control B Clear 0x04 8 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot 2 1 IDXCMD Ramp Index Command 3 2 IDXCMDSelect DISABLE 0x0 SET 0x1 CLEAR 0x2 HOLD 0x3 CMD TCC Command 5 3 CMDSelect NONE 0x0 RETRIGGER 0x1 STOP 0x2 UPDATE 0x3 READSYNC 0x4 CTRLBSET Control B Set 0x05 8 DIR Counter Direction 0 1 LUPD Lock update 1 1 ONESHOT One-Shot 2 1 IDXCMD Ramp Index Command 3 2 IDXCMDSelect DISABLE 0x0 SET 0x1 CLEAR 0x2 HOLD 0x3 CMD TCC Command 5 3 CMDSelect NONE 0x0 RETRIGGER 0x1 STOP 0x2 UPDATE 0x3 READSYNC 0x4 DBGCTRL Debug Control 0x1E 8 DBGRUN Debug Running Mode 0 1 FDDBD Fault Detection on Debug Break Detection 2 1 DRVCTRL Driver Configuration 0x18 32 NRE0 Non-Recoverable State 0 Output Enable 0 1 NRE1 Non-Recoverable State 1 Output Enable 1 1 NRE2 Non-Recoverable State 2 Output Enable 2 1 NRE3 Non-Recoverable State 3 Output Enable 3 1 NRE4 Non-Recoverable State 4 Output Enable 4 1 NRE5 Non-Recoverable State 5 Output Enable 5 1 NRE6 Non-Recoverable State 6 Output Enable 6 1 NRE7 Non-Recoverable State 7 Output Enable 7 1 NRV0 Non-Recoverable State 0 Output Value 8 1 NRV1 Non-Recoverable State 1 Output Value 9 1 NRV2 Non-Recoverable State 2 Output Value 10 1 NRV3 Non-Recoverable State 3 Output Value 11 1 NRV4 Non-Recoverable State 4 Output Value 12 1 NRV5 Non-Recoverable State 5 Output Value 13 1 NRV6 Non-Recoverable State 6 Output Value 14 1 NRV7 Non-Recoverable State 7 Output Value 15 1 INVEN0 Output Waveform 0 Inversion 16 1 INVEN1 Output Waveform 1 Inversion 17 1 INVEN2 Output Waveform 2 Inversion 18 1 INVEN3 Output Waveform 3 Inversion 19 1 INVEN4 Output Waveform 4 Inversion 20 1 INVEN5 Output Waveform 5 Inversion 21 1 INVEN6 Output Waveform 6 Inversion 22 1 INVEN7 Output Waveform 7 Inversion 23 1 FILTERVAL0 Non-Recoverable Fault Input 0 Filter Value 24 4 FILTERVAL1 Non-Recoverable Fault Input 1 Filter Value 28 4 EVCTRL Event Control 0x20 32 EVACT0 Timer/counter Input Event0 Action 0 3 EVACT0Select OFF 0x0 RETRIGGER 0x1 COUNTEV 0x2 START 0x3 INC 0x4 COUNT 0x5 FAULT 0x7 EVACT1 Timer/counter Input Event1 Action 3 3 EVACT1Select OFF 0x0 RETRIGGER 0x1 DIR 0x2 STOP 0x3 DEC 0x4 PPW 0x5 PWP 0x6 FAULT 0x7 CNTSEL Timer/counter Output Event Mode 6 2 CNTSELSelect START 0x0 END 0x1 BETWEEN 0x2 BOUNDARY 0x3 OVFEO Overflow/Underflow Output Event Enable 8 1 TRGEO Retrigger Output Event Enable 9 1 CNTEO Timer/counter Output Event Enable 10 1 TCINV0 Inverted Event 0 Input Enable 12 1 TCINV1 Inverted Event 1 Input Enable 13 1 TCEI0 Timer/counter Event 0 Input Enable 14 1 TCEI1 Timer/counter Event 1 Input Enable 15 1 MCEI0 Match or Capture Channel 0 Event Input Enable 16 1 MCEI1 Match or Capture Channel 1 Event Input Enable 17 1 MCEI2 Match or Capture Channel 2 Event Input Enable 18 1 MCEI3 Match or Capture Channel 3 Event Input Enable 19 1 MCEO0 Match or Capture Channel 0 Event Output Enable 24 1 MCEO1 Match or Capture Channel 1 Event Output Enable 25 1 MCEO2 Match or Capture Channel 2 Event Output Enable 26 1 MCEO3 Match or Capture Channel 3 Event Output Enable 27 1 FCTRLA Recoverable FaultA Configuration 0x0C 32 SRC FaultA Source 0 2 SRCSelect DISABLE 0x0 ENABLE 0x1 INVERT 0x2 ALTFAULT 0x3 KEEP FaultA Keeper 3 1 QUAL FaultA Qualification 4 1 BLANK FaultA Blanking Mode 5 2 BLANKSelect DISABLE 0x0 RISE 0x1 FALL 0x2 BOTH 0x3 RESTART FaultA Restart 7 1 HALT FaultA Halt Mode 8 2 HALTSelect DISABLE 0x0 HW 0x1 SW 0x2 NR 0x3 CHSEL FaultA Capture Channel 10 2 CHSELSelect CC0 0x0 CC1 0x1 CC2 0x2 CC3 0x3 CAPTURE FaultA Capture Action 12 3 CAPTURESelect DISABLE 0x0 CAPT 0x1 CAPTMIN 0x2 CAPTMAX 0x3 LOCMIN 0x4 LOCMAX 0x5 DERIV0 0x6 BLANKVAL FaultA Blanking Time 16 8 FILTERVAL FaultA Filter Value 24 4 FCTRLB Recoverable FaultB Configuration 0x10 32 SRC FaultB Source 0 2 SRCSelect DISABLE 0x0 ENABLE 0x1 INVERT 0x2 ALTFAULT 0x3 KEEP FaultB Keeper 3 1 QUAL FaultB Qualification 4 1 BLANK FaultB Blanking Mode 5 2 BLANKSelect DISABLE 0x0 RISE 0x1 FALL 0x2 BOTH 0x3 RESTART FaultB Restart 7 1 HALT FaultB Halt Mode 8 2 HALTSelect DISABLE 0x0 HW 0x1 SW 0x2 NR 0x3 CHSEL FaultB Capture Channel 10 2 CHSELSelect CC0 0x0 CC1 0x1 CC2 0x2 CC3 0x3 CAPTURE FaultB Capture Action 12 3 CAPTURESelect DISABLE 0x0 CAPT 0x1 CAPTMIN 0x2 CAPTMAX 0x3 LOCMIN 0x4 LOCMAX 0x5 DERIV0 0x6 BLANKVAL FaultB Blanking Time 16 8 FILTERVAL FaultB Filter Value 24 4 INTENCLR Interrupt Enable Clear 0x24 32 OVF Overflow Interrupt Enable 0 1 TRG Retrigger Interrupt Enable 1 1 CNT Counter Interrupt Enable 2 1 ERR Error Interrupt Enable 3 1 DFS Non-recoverable Debug Fault Interrupt Enable 11 1 FAULTA Recoverable FaultA Interrupt Enable 12 1 FAULTB Recoverable FaultB Interrupt Enable 13 1 FAULT0 Non-Recoverable Fault 0 Interrupt Enable 14 1 FAULT1 Non-Recoverable Fault 1 Interrupt Enable 15 1 MC0 Match or Capture Channel 0 Interrupt Enable 16 1 MC1 Match or Capture Channel 1 Interrupt Enable 17 1 MC2 Match or Capture Channel 2 Interrupt Enable 18 1 MC3 Match or Capture Channel 3 Interrupt Enable 19 1 INTENSET Interrupt Enable Set 0x28 32 OVF Overflow Interrupt Enable 0 1 TRG Retrigger Interrupt Enable 1 1 CNT Counter Interrupt Enable 2 1 ERR Error Interrupt Enable 3 1 DFS Non-Recoverable Debug Fault Interrupt Enable 11 1 FAULTA Recoverable FaultA Interrupt Enable 12 1 FAULTB Recoverable FaultB Interrupt Enable 13 1 FAULT0 Non-Recoverable Fault 0 Interrupt Enable 14 1 FAULT1 Non-Recoverable Fault 1 Interrupt Enabl 15 1 MC0 Match or Capture Channel 0 Interrupt Enable 16 1 MC1 Match or Capture Channel 1 Interrupt Enable 17 1 MC2 Match or Capture Channel 2 Interrupt Enable 18 1 MC3 Match or Capture Channel 3 Interrupt Enable 19 1 INTFLAG Interrupt Flag Status and Clear 0x2C 32 OVF Overflow 0 1 TRG Retrigger 1 1 CNT Counter 2 1 ERR Error 3 1 DFS Non-Recoverable Debug Fault 11 1 FAULTA Recoverable FaultA 12 1 FAULTB Recoverable FaultB 13 1 FAULT0 Non-Recoverable Fault 0 14 1 FAULT1 Non-Recoverable Fault 1 15 1 MC0 Match or Capture 0 16 1 MC1 Match or Capture 1 17 1 MC2 Match or Capture 2 18 1 MC3 Match or Capture 3 19 1 PATT Pattern 0x38 16 PGE0 Pattern Generator 0 Output Enable 0 1 PGE1 Pattern Generator 1 Output Enable 1 1 PGE2 Pattern Generator 2 Output Enable 2 1 PGE3 Pattern Generator 3 Output Enable 3 1 PGE4 Pattern Generator 4 Output Enable 4 1 PGE5 Pattern Generator 5 Output Enable 5 1 PGE6 Pattern Generator 6 Output Enable 6 1 PGE7 Pattern Generator 7 Output Enable 7 1 PGV0 Pattern Generator 0 Output Value 8 1 PGV1 Pattern Generator 1 Output Value 9 1 PGV2 Pattern Generator 2 Output Value 10 1 PGV3 Pattern Generator 3 Output Value 11 1 PGV4 Pattern Generator 4 Output Value 12 1 PGV5 Pattern Generator 5 Output Value 13 1 PGV6 Pattern Generator 6 Output Value 14 1 PGV7 Pattern Generator 7 Output Value 15 1 PATTB Pattern Buffer 0x64 16 PGEB0 Pattern Generator 0 Output Enable Buffer 0 1 PGEB1 Pattern Generator 1 Output Enable Buffer 1 1 PGEB2 Pattern Generator 2 Output Enable Buffer 2 1 PGEB3 Pattern Generator 3 Output Enable Buffer 3 1 PGEB4 Pattern Generator 4 Output Enable Buffer 4 1 PGEB5 Pattern Generator 5 Output Enable Buffer 5 1 PGEB6 Pattern Generator 6 Output Enable Buffer 6 1 PGEB7 Pattern Generator 7 Output Enable Buffer 7 1 PGVB0 Pattern Generator 0 Output Enable 8 1 PGVB1 Pattern Generator 1 Output Enable 9 1 PGVB2 Pattern Generator 2 Output Enable 10 1 PGVB3 Pattern Generator 3 Output Enable 11 1 PGVB4 Pattern Generator 4 Output Enable 12 1 PGVB5 Pattern Generator 5 Output Enable 13 1 PGVB6 Pattern Generator 6 Output Enable 14 1 PGVB7 Pattern Generator 7 Output Enable 15 1 PER Period 0x40 32 0xFFFFFFFF PER Period Value 0 24 PERB Period Buffer 0x6C 32 0xFFFFFFFF PERB Period Value 0 24 STATUS Status 0x30 32 0x00000001 STOP Stop 0 1 read-only IDX Ramp 1 1 read-only DFS Non-Recoverable Debug Fault State 3 1 PATTBV Pattern Buffer Valid 5 1 WAVEBV Wave Buffer Valid 6 1 PERBV Period Buffer Valid 7 1 FAULTAIN Recoverable FaultA Input 8 1 read-only FAULTBIN Recoverable FaultB Input 9 1 read-only FAULT0IN Non-Recoverable Fault0 Input 10 1 read-only FAULT1IN Non-Recoverable Fault1 Input 11 1 read-only FAULTA Recoverable FaultA State 12 1 FAULTB Recoverable FaultB State 13 1 FAULT0 Non-Recoverable Fault 0 State 14 1 FAULT1 Non-Recoverable Fault 1 State 15 1 CCBV0 Compare Channel 0 Buffer Valid 16 1 CCBV1 Compare Channel 1 Buffer Valid 17 1 CCBV2 Compare Channel 2 Buffer Valid 18 1 CCBV3 Compare Channel 3 Buffer Valid 19 1 CMP0 Compare Channel 0 Value 24 1 read-only CMP1 Compare Channel 1 Value 25 1 read-only CMP2 Compare Channel 2 Value 26 1 read-only CMP3 Compare Channel 3 Value 27 1 read-only SYNCBUSY Synchronization Busy 0x08 32 read-only SWRST Swrst Busy 0 1 ENABLE Enable Busy 1 1 CTRLB Ctrlb Busy 2 1 STATUS Status Busy 3 1 COUNT Count Busy 4 1 PATT Pattern Busy 5 1 WAVE Wave Busy 6 1 PER Period busy 7 1 CC0 Compare Channel Buffer 0 Busy 8 1 CC1 Compare Channel Buffer 1 Busy 9 1 CC2 Compare Channel Buffer 2 Busy 10 1 CC3 Compare Channel Buffer 3 Busy 11 1 PATTB Pattern Buffer Busy 16 1 WAVEB Wave Buffer Busy 17 1 PERB Period Buffer Busy 18 1 CCB0 Compare Channel Buffer 0 Busy 19 1 CCB1 Compare Channel Buffer 1 Busy 20 1 CCB2 Compare Channel Buffer 2 Busy 21 1 CCB3 Compare Channel Buffer 3 Busy 22 1 WAVE Waveform Control 0x3C 32 WAVEGEN Waveform Generation 0 3 WAVEGENSelect NFRQ 0x0 MFRQ 0x1 NPWM 0x2 DSCRITICAL 0x4 DSBOTTOM 0x5 DSBOTH 0x6 DSTOP 0x7 RAMP Ramp Mode 4 2 RAMPSelect RAMP1 0x0 RAMP2A 0x1 RAMP2 0x2 CIPEREN Circular period Enable 7 1 CICCEN0 Circular Channel 0 Enable 8 1 CICCEN1 Circular Channel 1 Enable 9 1 CICCEN2 Circular Channel 2 Enable 10 1 CICCEN3 Circular Channel 3 Enable 11 1 POL0 Channel 0 Polarity 16 1 POL1 Channel 1 Polarity 17 1 POL2 Channel 2 Polarity 18 1 POL3 Channel 3 Polarity 19 1 SWAP0 Swap DTI Output Pair 0 24 1 SWAP1 Swap DTI Output Pair 1 25 1 SWAP2 Swap DTI Output Pair 2 26 1 SWAP3 Swap DTI Output Pair 3 27 1 WAVEB Waveform Control Buffer 0x68 32 WAVEGENB Waveform Generation Buffer 0 3 WAVEGENBSelect NFRQ 0x0 MFRQ 0x1 NPWM 0x2 DSCRITICAL 0x4 DSBOTTOM 0x5 DSBOTH 0x6 DSTOP 0x7 RAMPB Ramp Mode Buffer 4 2 CIPERENB Circular Period Enable Buffer 7 1 CICCENB0 Circular Channel 0 Enable Buffer 8 1 CICCENB1 Circular Channel 1 Enable Buffer 9 1 CICCENB2 Circular Channel 2 Enable Buffer 10 1 CICCENB3 Circular Channel 3 Enable Buffer 11 1 POLB0 Channel 0 Polarity Buffer 16 1 POLB1 Channel 1 Polarity Buffer 17 1 POLB2 Channel 2 Polarity Buffer 18 1 POLB3 Channel 3 Polarity Buffer 19 1 SWAPB0 Swap DTI Output Pair 0 Buffer 24 1 SWAPB1 Swap DTI Output Pair 1 Buffer 25 1 SWAPB2 Swap DTI Output Pair 2 Buffer 26 1 SWAPB3 Swap DTI Output Pair 3 Buffer 27 1 WEXCTRL Waveform Extension Configuration 0x14 32 OTMX Output Matrix 0 2 DTIEN0 Dead-time Insertion Generator 0 Enable 8 1 DTIEN1 Dead-time Insertion Generator 1 Enable 9 1 DTIEN2 Dead-time Insertion Generator 2 Enable 10 1 DTIEN3 Dead-time Insertion Generator 3 Enable 11 1 DTLS Dead-time Low Side Outputs Value 16 8 DTHS Dead-time High Side Outputs Value 24 8 TCC1 Timer Counter Control 1 0x42002400 TCC1 16 TCC2 Timer Counter Control 2 0x42002800 TCC2 17 USB 1.0.1 Universal Serial Bus USB USB_ 0x41005000 0 0x1000 registers USB 7 DEVICE USB is Device UsbDevice 0x0 CTRLA Control A 0x000 8 SWRST Software Reset 0 1 ENABLE Enable 1 1 RUNSTDBY Run in Standby Mode 2 1 MODE Operating Mode 7 1 MODESelect DEVICE Device Mode 0x0 HOST Host Mode 0x1 DESCADD Descriptor Address 0x024 32 DESCADD Descriptor Address Value 0 32 CTRLB DEVICE Control B 0x008 16 0x0001 DETACH Detach 0 1 UPRSM Upstream Resume 1 1 SPDCONF Speed Configuration 2 2 SPDCONFSelect 0x0 FS : Full Speed 0x0 0x1 LS : Low Speed 0x1 0x2 HS : High Speed capable 0x2 0x3 HSTM: High Speed Test Mode (force high-speed mode for test mode) 0x3 NREPLY No Reply 4 1 TSTJ Test mode J 5 1 TSTK Test mode K 6 1 TSTPCKT Test packet mode 7 1 OPMODE2 Specific Operational Mode 8 1 GNAK Global NAK 9 1 LPMHDSK Link Power Management Handshake 10 2 LPMHDSKSelect NO No handshake. LPM is not supported 0x0 ACK ACK 0x1 NYET NYET 0x2 STALL STALL 0x3 DADD DEVICE Device Address 0x00A 8 DADD Device Address 0 7 ADDEN Device Address Enable 7 1 EPINTSMRY DEVICE End Point Interrupt Summary 0x020 16 read-only EPINT0 End Point 0 Interrupt 0 1 read-only EPINT1 End Point 1 Interrupt 1 1 read-only EPINT2 End Point 2 Interrupt 2 1 read-only EPINT3 End Point 3 Interrupt 3 1 read-only EPINT4 End Point 4 Interrupt 4 1 read-only EPINT5 End Point 5 Interrupt 5 1 read-only EPINT6 End Point 6 Interrupt 6 1 read-only EPINT7 End Point 7 Interrupt 7 1 read-only FNUM DEVICE Device Frame Number 0x010 16 read-only MFNUM Micro Frame Number 0 3 read-only FNUM Frame Number 3 11 read-only FNCERR Frame Number CRC Error 15 1 read-only INTENCLR DEVICE Device Interrupt Enable Clear 0x014 16 SUSPEND Suspend Interrupt Enable 0 1 MSOF Micro Start of Frame Interrupt Enable in High Speed Mode 1 1 SOF Start Of Frame Interrupt Enable 2 1 EORST End of Reset Interrupt Enable 3 1 WAKEUP Wake Up Interrupt Enable 4 1 EORSM End Of Resume Interrupt Enable 5 1 UPRSM Upstream Resume Interrupt Enable 6 1 RAMACER Ram Access Interrupt Enable 7 1 LPMNYET Link Power Management Not Yet Interrupt Enable 8 1 LPMSUSP Link Power Management Suspend Interrupt Enable 9 1 INTENSET DEVICE Device Interrupt Enable Set 0x018 16 SUSPEND Suspend Interrupt Enable 0 1 MSOF Micro Start of Frame Interrupt Enable in High Speed Mode 1 1 SOF Start Of Frame Interrupt Enable 2 1 EORST End of Reset Interrupt Enable 3 1 WAKEUP Wake Up Interrupt Enable 4 1 EORSM End Of Resume Interrupt Enable 5 1 UPRSM Upstream Resume Interrupt Enable 6 1 RAMACER Ram Access Interrupt Enable 7 1 LPMNYET Link Power Management Not Yet Interrupt Enable 8 1 LPMSUSP Link Power Management Suspend Interrupt Enable 9 1 INTFLAG DEVICE Device Interrupt Flag 0x01C 16 SUSPEND Suspend 0 1 MSOF Micro Start of Frame in High Speed Mode 1 1 SOF Start Of Frame 2 1 EORST End of Reset 3 1 WAKEUP Wake Up 4 1 EORSM End Of Resume 5 1 UPRSM Upstream Resume 6 1 RAMACER Ram Access 7 1 LPMNYET Link Power Management Not Yet 8 1 LPMSUSP Link Power Management Suspend 9 1 STATUS DEVICE Status 0x00C 8 read-only 0x40 SPEED Speed Status 2 2 read-only SPEEDSelect 0x0 Full-speed mode 0x0 0x1 High-speed mode 0x1 0x2 Low-speed mode 0x2 LINESTATE USB Line State Status 6 2 read-only LINESTATESelect 0x0 SE0/RESET 0x0 0x1 FS-J or LS-K State 0x1 0x2 FS-K or LS-J State 0x2 8 0x20 EPCFG%s DEVICE End Point Configuration 0x100 8 EPTYPE0 End Point Type0 0 3 EPTYPE1 End Point Type1 4 3 NYETDIS NYET Token Disable 7 1 8 0x20 EPINTENCLR%s DEVICE End Point Interrupt Clear Flag 0x108 8 TRCPT0 Transfer Complete 0 Interrupt Disable 0 1 TRCPT1 Transfer Complete 1 Interrupt Disable 1 1 TRFAIL0 Error Flow 0 Interrupt Disable 2 1 TRFAIL1 Error Flow 1 Interrupt Disable 3 1 RXSTP Received Setup Interrupt Disable 4 1 STALL0 Stall 0 In/Out Interrupt Disable 5 1 STALL1 Stall 1 In/Out Interrupt Disable 6 1 8 0x20 EPINTENSET%s DEVICE End Point Interrupt Set Flag 0x109 8 TRCPT0 Transfer Complete 0 Interrupt Enable 0 1 TRCPT1 Transfer Complete 1 Interrupt Enable 1 1 TRFAIL0 Error Flow 0 Interrupt Enable 2 1 TRFAIL1 Error Flow 1 Interrupt Enable 3 1 RXSTP Received Setup Interrupt Enable 4 1 STALL0 Stall 0 In/out Interrupt enable 5 1 STALL1 Stall 1 In/out Interrupt enable 6 1 8 0x20 EPINTFLAG%s DEVICE End Point Interrupt Flag 0x107 8 TRCPT0 Transfer Complete 0 0 1 TRCPT1 Transfer Complete 1 1 1 TRFAIL0 Error Flow 0 2 1 TRFAIL1 Error Flow 1 3 1 RXSTP Received Setup 4 1 STALL0 Stall 0 In/out 5 1 STALL1 Stall 1 In/out 6 1 8 0x20 EPSTATUS%s DEVICE End Point Pipe Status 0x106 8 read-only DTGLOUT Data Toggle Out 0 1 read-only DTGLIN Data Toggle In 1 1 read-only CURBK Current Bank 2 1 read-only STALLRQ0 Stall 0 Request 4 1 read-only STALLRQ1 Stall 1 Request 5 1 read-only BK0RDY Bank 0 ready 6 1 read-only BK1RDY Bank 1 ready 7 1 read-only 8 0x20 EPSTATUSCLR%s DEVICE End Point Pipe Status Clear 0x104 8 write-only DTGLOUT Data Toggle OUT Clear 0 1 write-only DTGLIN Data Toggle IN Clear 1 1 write-only CURBK Curren Bank Clear 2 1 write-only STALLRQ0 Stall 0 Request Clear 4 1 write-only STALLRQ1 Stall 1 Request Clear 5 1 write-only BK0RDY Bank 0 Ready Clear 6 1 write-only BK1RDY Bank 1 Ready Clear 7 1 write-only 8 0x20 EPSTATUSSET%s DEVICE End Point Pipe Status Set 0x105 8 write-only DTGLOUT Data Toggle OUT Set 0 1 write-only DTGLIN Data Toggle IN Set 1 1 write-only CURBK Current Bank Set 2 1 write-only STALLRQ0 Stall 0 Request Set 4 1 write-only STALLRQ1 Stall 1 Request Set 5 1 write-only BK0RDY Bank 0 Ready Set 6 1 write-only BK1RDY Bank 1 Ready Set 7 1 write-only FSMSTATUS Finite State Machine Status 0x00D 8 read-only 0x01 FSMSTATE Fine State Machine Status 0 6 read-only FSMSTATESelect 0x1 OFF (L3). It corresponds to the powered-off, disconnected, and disabled state 0x1 0x2 ON (L0). It corresponds to the Idle and Active states 0x2 0x4 SUSPEND (L2) 0x4 0x8 SLEEP (L1) 0x8 0x10 DNRESUME. Down Stream Resume. 0x10 0x20 UPRESUME. Up Stream Resume. 0x20 0x40 RESET. USB lines Reset. 0x40 PADCAL USB PAD Calibration 0x028 16 TRANSP USB Pad Transp calibration 0 5 TRANSN USB Pad Transn calibration 6 5 TRIM USB Pad Trim calibration 12 3 SYNCBUSY Synchronization Busy 0x002 8 read-only SWRST Software Reset Synchronization Busy 0 1 read-only ENABLE Enable Synchronization Busy 1 1 read-only HOST USB is Host DEVICE UsbHost 0x0 CTRLA Control A 0x000 8 SWRST Software Reset 0 1 ENABLE Enable 1 1 RUNSTDBY Run in Standby Mode 2 1 MODE Operating Mode 7 1 MODESelect DEVICE Device Mode 0x0 HOST Host Mode 0x1 DESCADD Descriptor Address 0x024 32 DESCADD Descriptor Address Value 0 32 FSMSTATUS Finite State Machine Status 0x00D 8 read-only 0x01 FSMSTATE Fine State Machine Status 0 6 read-only FSMSTATESelect 0x1 OFF (L3). It corresponds to the powered-off, disconnected, and disabled state 0x1 0x2 ON (L0). It corresponds to the Idle and Active states 0x2 0x4 SUSPEND (L2) 0x4 0x8 SLEEP (L1) 0x8 0x10 DNRESUME. Down Stream Resume. 0x10 0x20 UPRESUME. Up Stream Resume. 0x20 0x40 RESET. USB lines Reset. 0x40 CTRLB HOST Control B 0x008 16 RESUME Send USB Resume 1 1 SPDCONF Speed Configuration for Host 2 2 SPDCONFSelect 0x0 Normal mode:the host starts in full-speed mode and performs a high-speed reset to switch to the high speed mode if the downstream peripheralis high-speed capable. 0x0 0x1 reserved 0x1 0x2 reserved 0x2 0x3 Full-speed:the host remains in full-speed mode whatever is the peripheral speed capability. Releveant in UTMI mode only. 0x3 TSTJ Test mode J 5 1 TSTK Test mode K 6 1 SOFE Start of Frame Generation Enable 8 1 BUSRESET Send USB Reset 9 1 VBUSOK VBUS is OK 10 1 L1RESUME Send L1 Resume 11 1 FLENHIGH HOST Host Frame Length 0x012 8 read-only FLENHIGH Frame Length 0 8 read-only FNUM HOST Host Frame Number 0x010 16 MFNUM Micro Frame Number 0 3 FNUM Frame Number 3 11 HSOFC HOST Host Start Of Frame Control 0x00A 8 FLENC Frame Length Control 0 4 FLENCE Frame Length Control Enable 7 1 INTENCLR HOST Host Interrupt Enable Clear 0x014 16 HSOF Host Start Of Frame Interrupt Disable 2 1 RST BUS Reset Interrupt Disable 3 1 WAKEUP Wake Up Interrupt Disable 4 1 DNRSM DownStream to Device Interrupt Disable 5 1 UPRSM Upstream Resume from Device Interrupt Disable 6 1 RAMACER Ram Access Interrupt Disable 7 1 DCONN Device Connection Interrupt Disable 8 1 DDISC Device Disconnection Interrupt Disable 9 1 INTENSET HOST Host Interrupt Enable Set 0x018 16 HSOF Host Start Of Frame Interrupt Enable 2 1 RST Bus Reset Interrupt Enable 3 1 WAKEUP Wake Up Interrupt Enable 4 1 DNRSM DownStream to the Device Interrupt Enable 5 1 UPRSM Upstream Resume fromthe device Interrupt Enable 6 1 RAMACER Ram Access Interrupt Enable 7 1 DCONN Link Power Management Interrupt Enable 8 1 DDISC Device Disconnection Interrupt Enable 9 1 INTFLAG HOST Host Interrupt Flag 0x01C 16 HSOF Host Start Of Frame 2 1 RST Bus Reset 3 1 WAKEUP Wake Up 4 1 DNRSM Downstream 5 1 UPRSM Upstream Resume from the Device 6 1 RAMACER Ram Access 7 1 DCONN Device Connection 8 1 DDISC Device Disconnection 9 1 PINTSMRY HOST Pipe Interrupt Summary 0x020 16 read-only EPINT0 Pipe 0 Interrupt 0 1 read-only EPINT1 Pipe 1 Interrupt 1 1 read-only EPINT2 Pipe 2 Interrupt 2 1 read-only EPINT3 Pipe 3 Interrupt 3 1 read-only EPINT4 Pipe 4 Interrupt 4 1 read-only EPINT5 Pipe 5 Interrupt 5 1 read-only EPINT6 Pipe 6 Interrupt 6 1 read-only EPINT7 Pipe 7 Interrupt 7 1 read-only STATUS HOST Status 0x00C 8 SPEED Speed Status 2 2 LINESTATE USB Line State Status 6 2 read-only 8 0x20 BINTERVAL%s HOST Bus Access Period of Pipe 0x103 8 BITINTERVAL Bit Interval 0 8 8 0x20 PCFG%s HOST End Point Configuration 0x100 8 PTOKEN Pipe Token 0 2 BK Pipe Bank 2 1 PTYPE Pipe Type 3 3 8 0x20 PINTENCLR%s HOST Pipe Interrupt Flag Clear 0x108 8 TRCPT0 Transfer Complete 0 Disable 0 1 TRCPT1 Transfer Complete 1 Disable 1 1 TRFAIL Error Flow Interrupt Disable 2 1 PERR Pipe Error Interrupt Disable 3 1 TXSTP Transmit Setup Interrupt Disable 4 1 STALL Stall Inetrrupt Disable 5 1 8 0x20 PINTENSET%s HOST Pipe Interrupt Flag Set 0x109 8 TRCPT0 Transfer Complete 0 Interrupt Enable 0 1 TRCPT1 Transfer Complete 1 Interrupt Enable 1 1 TRFAIL Error Flow Interrupt Enable 2 1 PERR Pipe Error Interrupt Enable 3 1 TXSTP Transmit Setup Interrupt Enable 4 1 STALL Stall Interrupt Enable 5 1 8 0x20 PINTFLAG%s HOST Pipe Interrupt Flag 0x107 8 TRCPT0 Transfer Complete 0 Interrupt Flag 0 1 TRCPT1 Transfer Complete 1 Interrupt Flag 1 1 TRFAIL Error Flow Interrupt Flag 2 1 PERR Pipe Error Interrupt Flag 3 1 TXSTP Transmit Setup Interrupt Flag 4 1 STALL Stall Interrupt Flag 5 1 8 0x20 PSTATUS%s HOST End Point Pipe Status 0x106 8 read-only DTGL Data Toggle 0 1 read-only CURBK Current Bank 2 1 read-only PFREEZE Pipe Freeze 4 1 read-only BK0RDY Bank 0 ready 6 1 read-only BK1RDY Bank 1 ready 7 1 read-only 8 0x20 PSTATUSCLR%s HOST End Point Pipe Status Clear 0x104 8 write-only DTGL Data Toggle clear 0 1 read-only CURBK Curren Bank clear 2 1 write-only PFREEZE Pipe Freeze Clear 4 1 write-only BK0RDY Bank 0 Ready Clear 6 1 write-only BK1RDY Bank 1 Ready Clear 7 1 write-only 8 0x20 PSTATUSSET%s HOST End Point Pipe Status Set 0x105 8 write-only DTGL Data Toggle Set 0 1 write-only CURBK Current Bank Set 2 1 write-only PFREEZE Pipe Freeze Set 4 1 write-only BK0RDY Bank 0 Ready Set 6 1 write-only BK1RDY Bank 1 Ready Set 7 1 write-only PADCAL USB PAD Calibration 0x028 16 TRANSP USB Pad Transp calibration 0 5 TRANSN USB Pad Transn calibration 6 5 TRIM USB Pad Trim calibration 12 3 SYNCBUSY Synchronization Busy 0x002 8 read-only SWRST Software Reset Synchronization Busy 0 1 read-only ENABLE Enable Synchronization Busy 1 1 read-only WDT 2.0.0 Watchdog Timer WDT WDT_ 0x40001000 0 0x10 registers WDT 2 CLEAR Clear 0x8 8 write-only CLEAR Watchdog Clear 0 8 write-only CLEARSelect KEY Clear Key 0xa5 CONFIG Configuration 0x1 8 0xBB PER Time-Out Period 0 4 PERSelect 0x0 8 clock cycles 0x0 0x1 16 clock cycles 0x1 0x2 32 clock cycles 0x2 0x3 64 clock cycles 0x3 0x4 128 clock cycles 0x4 0x5 256 clock cycles 0x5 0x6 512 clock cycles 0x6 0x7 1024 clock cycles 0x7 0x8 2048 clock cycles 0x8 0x9 4096 clock cycles 0x9 0xA 8192 clock cycles 0xa 0xB 16384 clock cycles 0xb WINDOW Window Mode Time-Out Period 4 4 WINDOWSelect 0x0 8 clock cycles 0x0 0x1 16 clock cycles 0x1 0x2 32 clock cycles 0x2 0x3 64 clock cycles 0x3 0x4 128 clock cycles 0x4 0x5 256 clock cycles 0x5 0x6 512 clock cycles 0x6 0x7 1024 clock cycles 0x7 0x8 2048 clock cycles 0x8 0x9 4096 clock cycles 0x9 0xA 8192 clock cycles 0xa 0xB 16384 clock cycles 0xb CTRL Control 0x0 8 ENABLE Enable 1 1 WEN Watchdog Timer Window Mode Enable 2 1 ALWAYSON Always-On 7 1 EWCTRL Early Warning Interrupt Control 0x2 8 0x0B EWOFFSET Early Warning Interrupt Time Offset 0 4 EWOFFSETSelect 0x0 8 clock cycles 0x0 0x1 16 clock cycles 0x1 0x2 32 clock cycles 0x2 0x3 64 clock cycles 0x3 0x4 128 clock cycles 0x4 0x5 256 clock cycles 0x5 0x6 512 clock cycles 0x6 0x7 1024 clock cycles 0x7 0x8 2048 clock cycles 0x8 0x9 4096 clock cycles 0x9 0xA 8192 clock cycles 0xa 0xB 16384 clock cycles 0xb INTENCLR Interrupt Enable Clear 0x4 8 EW Early Warning Interrupt Enable 0 1 INTENSET Interrupt Enable Set 0x5 8 EW Early Warning Interrupt Enable 0 1 INTFLAG Interrupt Flag Status and Clear 0x6 8 EW Early Warning 0 1 STATUS Status 0x7 8 read-only SYNCBUSY Synchronization Busy 7 1 read-only