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	(version 20241229)
	(generator "pcbnew")
	(generator_version "9.0")
	(general
		(thickness 1.702)
		(legacy_teardrops no)
	)
	(paper "A4")
	(title_block
		(title "CLAWS Receiver and Power Distribution Board")
		(date "2026-01-07")
		(rev "V4.2.1")
		(comment 1 "As this is an iteration on previous designs (V3.x), revision number starts at 4.0")
		(comment 2 "V4.1 addresses the issues discovered when building V4.0 prototypes")
		(comment 3 "V4.2 reduces number of different components used, fix LDO startup problem")
		(comment 4 "V4.2.1 adds minor fixes incl. signal trace impedance fix (however only negligible effect)")
	)
	(layers
		(0 "F.Cu" signal)
		(4 "In1.Cu" signal)
		(6 "In2.Cu" signal)
		(2 "B.Cu" signal)
		(9 "F.Adhes" user "F.Adhesive")
		(11 "B.Adhes" user "B.Adhesive")
		(13 "F.Paste" user)
		(15 "B.Paste" user)
		(5 "F.SilkS" user "F.Silkscreen")
		(7 "B.SilkS" user "B.Silkscreen")
		(1 "F.Mask" user)
		(3 "B.Mask" user)
		(17 "Dwgs.User" user "User.Drawings")
		(19 "Cmts.User" user "User.Comments")
		(21 "Eco1.User" user "User.Eco1")
		(23 "Eco2.User" user "User.Eco2")
		(25 "Edge.Cuts" user)
		(27 "Margin" user)
		(31 "F.CrtYd" user "F.Courtyard")
		(29 "B.CrtYd" user "B.Courtyard")
		(35 "F.Fab" user)
		(33 "B.Fab" user)
		(39 "User.1" user)
		(41 "User.2" user)
		(43 "User.3" user)
		(45 "User.4" user)
		(47 "User.5" user)
		(49 "User.6" user)
		(51 "User.7" user)
		(53 "User.8" user)
		(55 "User.9" user)
	)
	(setup
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				(type "Top Silk Screen")
			)
			(layer "F.Paste"
				(type "Top Solder Paste")
			)
			(layer "F.Mask"
				(type "Top Solder Mask")
				(color "Green")
				(thickness 0.016)
			)
			(layer "F.Cu"
				(type "copper")
				(thickness 0.035)
			)
			(layer "dielectric 1"
				(type "prepreg")
				(color "FR4 natural")
				(thickness 0.1)
				(material "FR4")
				(epsilon_r 4.5)
				(loss_tangent 0.02)
			)
			(layer "In1.Cu"
				(type "copper")
				(thickness 0.035)
			)
			(layer "dielectric 2"
				(type "core")
				(thickness 1.33)
				(material "FR4")
				(epsilon_r 4.5)
				(loss_tangent 0.02)
			)
			(layer "In2.Cu"
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				(thickness 0.035)
			)
			(layer "dielectric 3"
				(type "prepreg")
				(thickness 0.1)
				(material "FR4")
				(epsilon_r 4.5)
				(loss_tangent 0.02)
			)
			(layer "B.Cu"
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			)
			(layer "B.Mask"
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				(color "Green")
				(thickness 0.016)
			)
			(layer "B.Paste"
				(type "Bottom Solder Paste")
			)
			(layer "B.SilkS"
				(type "Bottom Silk Screen")
			)
			(copper_finish "None")
			(dielectric_constraints no)
		)
		(pad_to_mask_clearance 0.1)
		(allow_soldermask_bridges_in_footprints yes)
		(tenting front back)
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			(mirror no)
			(drillshape 0)
			(scaleselection 1)
			(outputdirectory "plot")
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	)
	(net 0 "")
	(net 1 "VCC_REC")
	(net 2 "GND")
	(net 3 "VCM")
	(net 4 "VCLAMP")
	(net 5 "VEE_REC")
	(net 6 "/OUT-")
	(net 7 "/OUT+")
	(net 8 "VCC_SNS")
	(net 9 "VBIAS")
	(net 10 "/VCC_REC_EXT")
	(net 11 "/VEE_REC_EXT")
	(net 12 "/VCC_SNS_EXT")
	(net 13 "/VEE_REC_INT")
	(net 14 "/VCC_SNS_INT")
	(net 15 "/VBIAS_EXT")
	(net 16 "/VBIAS_INT")
	(net 17 "/VCC_REC_INT")
	(net 18 "/VCC_REC_UNF")
	(net 19 "/VEE_REC_UNF")
	(net 20 "/VCC_SNS_UNF")
	(net 21 "/VBIAS_UNF")
	(net 22 "/VCC_REC_UNREG")
	(net 23 "Net-(J1-In)")
	(net 24 "Net-(J2-In)")
	(net 25 "unconnected-(J3-Pin_7-Pad7)")
	(net 26 "unconnected-(J3-Pin_8-Pad8)")
	(net 27 "unconnected-(J8-Pin_7-Pad7)")
	(net 28 "unconnected-(J8-Pin_8-Pad8)")
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	(net 34 "Net-(R13-Pad1)")
	(net 35 "Net-(U1-IN-)")
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	(net 37 "/VEE_REC_UNREG")
	(net 38 "Net-(R10-Pad1)")
	(net 39 "Net-(R10-Pad2)")
	(net 40 "Net-(U2-VIN)")
	(net 41 "Net-(U3-VIN)")
	(net 42 "Net-(U2-GND)")
	(net 43 "Net-(U3-GND)")
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