#-----------------------------------------------------------
# Vivado v2016.2 (64-bit)
# SW Build 1577090 on Thu Jun  2 16:32:40 MDT 2016
# IP Build 1577682 on Fri Jun  3 12:00:54 MDT 2016
# Start of session at: Thu Dec 27 14:55:15 2018
# Process ID: 17196
# Current directory: C:/Users/53194/Desktop/pro9 10/project_789
# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent2716 C:\Users\53194\Desktop\pro9 10\project_789\project_78.xpr
# Log file: C:/Users/53194/Desktop/pro9 10/project_789/vivado.log
# Journal file: C:/Users/53194/Desktop/pro9 10/project_789\vivado.jou
#-----------------------------------------------------------
start_gui
open_project {C:/Users/53194/Desktop/pro9 10/project_789/project_78.xpr}
INFO: [Project 1-313] Project file moved from 'C:/Users/53194/Desktop/project_789' since last save.
Scanning sources...
Finished scanning sources
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'J:/Xilinx/Vivado/2016.2/data/ip'.
open_project: Time (s): cpu = 00:00:13 ; elapsed = 00:00:19 . Memory (MB): peak = 748.848 ; gain = 98.023
update_compile_order -fileset sources_1
set_property top top [get_filesets sim_1]
set_property top_lib xil_defaultlib [get_filesets sim_1]
launch_simulation
INFO: [USF-XSim-27] Simulation object is 'sim_1'
INFO: [USF-XSim-37] Inspecting design source files for 'top' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/pro9 10/project_789/project_78.sim/sim_1/behav'
"xvlog -m64 --relax -prj top_vlog.prj"
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/pro9 10/project_789/project_78.srcs/sources_1/new/SignalExtension.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module SignalExtension
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/pro9 10/project_789/project_78.srcs/sources_1/new/ShiftUnit.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ShiftUnit
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/pro9 10/project_789/project_78.srcs/sources_1/new/RegMA.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module RegMA
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/pro9 10/project_789/project_78.srcs/sources_1/new/RegisterFile.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module RegisterFile
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/pro9 10/project_789/project_78.srcs/sources_1/new/RegID.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module RegID
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/pro9 10/project_789/project_78.srcs/sources_1/new/RegFI.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module RegFI
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/pro9 10/project_789/project_78.srcs/sources_1/new/RegEX.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module RegEX
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/pro9 10/project_789/project_78.srcs/sources_1/new/ProgramCounter.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ProgramCounter
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/pro9 10/project_789/project_78.srcs/sources_1/new/Multiplexer4.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Multiplexer4
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/pro9 10/project_789/project_78.srcs/sources_1/new/Multiplexer.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Multiplexer
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/pro9 10/project_789/project_78.srcs/sources_1/new/InstructionMemory.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module InstructionMemory
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/pro9 10/project_789/project_78.srcs/sources_1/new/DataMemory.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module DataMemory
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/pro9 10/project_789/project_78.srcs/sources_1/new/ControlUnit.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ControlUnit
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/pro9 10/project_789/project_78.srcs/sources_1/new/ALUControl.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ALUControl
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/pro9 10/project_789/project_78.srcs/sources_1/new/ALU2.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ALU2
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/pro9 10/project_789/project_78.srcs/sources_1/new/Add1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Add1
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/pro9 10/project_789/project_78.srcs/sources_1/new/top.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module top
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/pro9 10/project_789/project_78.sim/sim_1/behav/glbl.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module glbl
INFO: [USF-XSim-69] 'compile' step finished in '4' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/53194/Desktop/pro9 10/project_789/project_78.sim/sim_1/behav'
Vivado Simulator 2016.2
Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved.
Running: J:/Xilinx/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto 4c388791a4e240948a5554cd0b3617d7 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot top_behav xil_defaultlib.top xil_defaultlib.glbl -log elaborate.log 
Using 2 slave threads.
Starting static elaboration
WARNING: [VRFC 10-278] actual bit length 32 differs from formal bit length 5 for port addr [C:/Users/53194/Desktop/pro9 10/project_789/project_78.srcs/sources_1/new/top.v:139]
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling module xil_defaultlib.ControlUnit
Compiling module xil_defaultlib.ProgramCounter
Compiling module xil_defaultlib.Add1
Compiling module xil_defaultlib.InstructionMemory
Compiling module xil_defaultlib.RegFI
Compiling module xil_defaultlib.RegisterFile
Compiling module xil_defaultlib.SignalExtension
Compiling module xil_defaultlib.RegID
Compiling module xil_defaultlib.ALUControl
Compiling module xil_defaultlib.ALU2
Compiling module xil_defaultlib.ShiftUnit
Compiling module xil_defaultlib.RegEX
Compiling module xil_defaultlib.Multiplexer4
Compiling module xil_defaultlib.Multiplexer
Compiling module xil_defaultlib.DataMemory
Compiling module xil_defaultlib.RegMA
Compiling module xil_defaultlib.top
Compiling module xil_defaultlib.glbl
Built simulation snapshot top_behav

****** Webtalk v2016.2 (64-bit)
  **** SW Build 1577090 on Thu Jun  2 16:32:40 MDT 2016
  **** IP Build 1577682 on Fri Jun  3 12:00:54 MDT 2016
    ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.

source C:/Users/53194/Desktop/pro9 -notrace
couldn't read file "C:/Users/53194/Desktop/pro9": no such file or directory
INFO: [Common 17-206] Exiting Webtalk at Thu Dec 27 14:57:51 2018...
run_program: Time (s): cpu = 00:00:02 ; elapsed = 00:00:10 . Memory (MB): peak = 800.676 ; gain = 39.980
INFO: [USF-XSim-69] 'elaborate' step finished in '9' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/53194/Desktop/pro9 10/project_789/project_78.sim/sim_1/behav'
INFO: [USF-XSim-98] *** Running xsim
   with args "top_behav -key {Behavioral:sim_1:Functional:top} -tclbatch {top.tcl} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Vivado Simulator 2016.2
Time resolution is 1 ps
source top.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
#   if { [llength [get_objects]] > 0} {
#     add_wave /
#     set_property needs_save false [current_wave_config]
#   } else {
#      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
#   }
# }
# run 1000ns
WARNING: File C:/Users/53194/Desktop/project_789/instruction.txt referenced on C:/Users/53194/Desktop/pro9 10/project_789/project_78.srcs/sources_1/new/InstructionMemory.v at line 40 cannot be opened for reading. Please ensure that this file is available in the current working directory.
INFO: [USF-XSim-96] XSim completed. Design snapshot 'top_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:07 ; elapsed = 00:00:18 . Memory (MB): peak = 800.676 ; gain = 39.980
close_sim
INFO: [Simtcl 6-16] Simulation closed
exit
INFO: [Common 17-206] Exiting Vivado at Thu Dec 27 23:28:36 2018...