#----------------------------------------------------------- # Vivado v2016.2 (64-bit) # SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016 # IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 # Start of session at: Sun Dec 23 16:11:48 2018 # Process ID: 3720 # Current directory: C:/Users/53194/Desktop/project_789 # Command line: vivado.exe -gui_launcher_event rodinguilauncherevent4660 C:\Users\53194\Desktop\project_789\project_78.xpr # Log file: C:/Users/53194/Desktop/project_789/vivado.log # Journal file: C:/Users/53194/Desktop/project_789\vivado.jou #----------------------------------------------------------- start_gui open_project C:/Users/53194/Desktop/project_789/project_78.xpr Scanning sources... Finished scanning sources INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'J:/Xilinx/Vivado/2016.2/data/ip'. open_project: Time (s): cpu = 00:00:12 ; elapsed = 00:00:26 . Memory (MB): peak = 807.289 ; gain = 116.023 update_compile_order -fileset sources_1 close [ open C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Sim_top.v w ] add_files C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Sim_top.v update_compile_order -fileset sources_1 set_property top Sim_top [get_filesets sim_1] set_property top_lib xil_defaultlib [get_filesets sim_1] set_property top top [get_filesets sim_1] set_property top_lib xil_defaultlib [get_filesets sim_1] launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'top' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj top_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SignalExtension.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module SignalExtension INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ShiftUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ShiftUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegisterFile.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegisterFile INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ProgramCounter.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ProgramCounter INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Multiplexer INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module InstructionMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module DataMemory INFO: [VRFC 10-2458] undeclared symbol out, assumed default net type wire [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v:44] INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ControlUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALUControl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALUControl INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Add1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Add1 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SimpleALU.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module SimpleALU INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module top INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl INFO: [USF-XSim-69] 'compile' step finished in '3' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' Vivado Simulator 2016.2 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: J:/Xilinx/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto 4c388791a4e240948a5554cd0b3617d7 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot top_behav xil_defaultlib.top xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration WARNING: [VRFC 10-278] actual bit length 32 differs from formal bit length 1 for port rdata1 [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:80] WARNING: [VRFC 10-278] actual bit length 4 differs from formal bit length 3 for port op [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:83] Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling module xil_defaultlib.ControlUnit Compiling module xil_defaultlib.ProgramCounter Compiling module xil_defaultlib.Add1 Compiling module xil_defaultlib.InstructionMemory Compiling module xil_defaultlib.RegisterFile Compiling module xil_defaultlib.SignalExtension Compiling module xil_defaultlib.ALUControl Compiling module xil_defaultlib.SimpleALU Compiling module xil_defaultlib.Multiplexer Compiling module xil_defaultlib.ShiftUnit Compiling module xil_defaultlib.DataMemory Compiling module xil_defaultlib.top Compiling module xil_defaultlib.glbl Built simulation snapshot top_behav ****** Webtalk v2016.2 (64-bit) **** SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016 **** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. source C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/xsim.dir/top_behav/webtalk/xsim_webtalk.tcl -notrace INFO: [Common 17-206] Exiting Webtalk at Sun Dec 23 16:26:25 2018... run_program: Time (s): cpu = 00:00:00 ; elapsed = 00:00:08 . Memory (MB): peak = 831.164 ; gain = 0.000 INFO: [USF-XSim-69] 'elaborate' step finished in '8' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' INFO: [USF-XSim-98] *** Running xsim with args "top_behav -key {Behavioral:sim_1:Functional:top} -tclbatch {top.tcl} -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature Vivado Simulator 2016.2 Time resolution is 1 ps source top.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns WARNING: File C:UsersY94Desktopproject_789instruction.txt referenced on C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v at line 37 cannot be opened for reading. Please ensure that this file is available in the current working directory. INFO: [USF-XSim-96] XSim completed. Design snapshot 'top_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:03 ; elapsed = 00:00:15 . Memory (MB): peak = 860.160 ; gain = 28.996 remove_files C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Sim_top.v set_property top top [current_fileset] update_compile_order -fileset sources_1 synth_design -rtl -name rtl_1 Command: synth_design -rtl -name rtl_1 Starting synth_design Using part: xc7z030sbg485-1 Top: top WARNING: [Synth 8-2306] macro LW redefined [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:21] WARNING: [Synth 8-2306] macro SW redefined [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:22] WARNING: [Synth 8-2306] macro ADD redefined [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:24] WARNING: [Synth 8-2306] macro SUB redefined [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:25] WARNING: [Synth 8-2306] macro ADDU redefined [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:26] WARNING: [Synth 8-2306] macro AND redefined [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:27] WARNING: [Synth 8-2306] macro OR redefined [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:28] WARNING: [Synth 8-2306] macro SLT redefined [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:29] WARNING: [Synth 8-2306] macro BEQ redefined [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:31] WARNING: [Synth 8-2306] macro J redefined [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:32] --------------------------------------------------------------------------------- Starting RTL Elaboration : Time (s): cpu = 00:01:48 ; elapsed = 00:16:28 . Memory (MB): peak = 898.977 ; gain = 691.887 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:34] INFO: [Synth 8-638] synthesizing module 'ControlUnit' [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v:36] INFO: [Synth 8-256] done synthesizing module 'ControlUnit' (1#1) [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v:36] WARNING: [Synth 8-350] instance 'CU' of module 'ControlUnit' requires 9 connections, but only 8 given [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:76] INFO: [Synth 8-638] synthesizing module 'ProgramCounter' [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ProgramCounter.v:23] INFO: [Synth 8-256] done synthesizing module 'ProgramCounter' (2#1) [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ProgramCounter.v:23] INFO: [Synth 8-638] synthesizing module 'Add1' [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Add1.v:23] INFO: [Synth 8-256] done synthesizing module 'Add1' (3#1) [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Add1.v:23] INFO: [Synth 8-638] synthesizing module 'InstructionMemory' [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v:23] CRITICAL WARNING: [Synth 8-4445] could not open $readmem data file 'C:UsersY94Desktopproject_789instruction.txt'; please make sure the file is added to project and has read permission, ignoring [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v:37] Warning: Trying to implement RAM in registers. Block RAM or DRAM implementation is not possible for one or more of the following reasons : 1: Unable to determine number of words or word size in RAM. 2: No valid read/write found for RAM. RAM dissolved into registers WARNING: [Synth 8-3848] Net bram in module/entity InstructionMemory does not have driver. [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v:32] WARNING: [Synth 8-3848] Net bram in module/entity InstructionMemory does not have driver. [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v:32] WARNING: [Synth 8-3848] Net bram in module/entity InstructionMemory does not have driver. [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v:32] WARNING: [Synth 8-3848] Net bram in module/entity InstructionMemory does not have driver. [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v:32] WARNING: [Synth 8-3848] Net bram in module/entity InstructionMemory does not have driver. [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v:32] WARNING: [Synth 8-3848] Net bram in module/entity InstructionMemory does not have driver. [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v:32] WARNING: [Synth 8-3848] Net bram in module/entity InstructionMemory does not have driver. [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v:32] WARNING: [Synth 8-3848] Net bram in module/entity InstructionMemory does not have driver. [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v:32] WARNING: [Synth 8-3848] Net bram in module/entity InstructionMemory does not have driver. [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v:32] WARNING: [Synth 8-3848] Net bram in module/entity InstructionMemory does not have driver. [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v:32] WARNING: [Synth 8-3848] Net bram in module/entity InstructionMemory does not have driver. [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v:32] WARNING: [Synth 8-3848] Net bram in module/entity InstructionMemory does not have driver. [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v:32] WARNING: [Synth 8-3848] Net bram in module/entity InstructionMemory does not have driver. [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v:32] WARNING: [Synth 8-3848] Net bram in module/entity InstructionMemory does not have driver. [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v:32] WARNING: [Synth 8-3848] Net bram in module/entity InstructionMemory does not have driver. [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v:32] WARNING: [Synth 8-3848] Net bram in module/entity InstructionMemory does not have driver. [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v:32] WARNING: [Synth 8-3848] Net bram in module/entity InstructionMemory does not have driver. [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v:32] WARNING: [Synth 8-3848] Net bram in module/entity InstructionMemory does not have driver. [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v:32] WARNING: [Synth 8-3848] Net bram in module/entity InstructionMemory does not have driver. [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v:32] WARNING: [Synth 8-3848] Net bram in module/entity InstructionMemory does not have driver. [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v:32] WARNING: [Synth 8-3848] Net bram in module/entity InstructionMemory does not have driver. [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v:32] WARNING: [Synth 8-3848] Net bram in module/entity InstructionMemory does not have driver. [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v:32] WARNING: [Synth 8-3848] Net bram in module/entity InstructionMemory does not have driver. [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v:32] WARNING: [Synth 8-3848] Net bram in module/entity InstructionMemory does not have driver. [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v:32] WARNING: [Synth 8-3848] Net bram in module/entity InstructionMemory does not have driver. [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v:32] WARNING: [Synth 8-3848] Net bram in module/entity InstructionMemory does not have driver. [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v:32] WARNING: [Synth 8-3848] Net bram in module/entity InstructionMemory does not have driver. [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v:32] WARNING: [Synth 8-3848] Net bram in module/entity InstructionMemory does not have driver. [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v:32] WARNING: [Synth 8-3848] Net bram in module/entity InstructionMemory does not have driver. [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v:32] WARNING: [Synth 8-3848] Net bram in module/entity InstructionMemory does not have driver. [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v:32] WARNING: [Synth 8-3848] Net bram in module/entity InstructionMemory does not have driver. [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v:32] WARNING: [Synth 8-3848] Net bram in module/entity InstructionMemory does not have driver. [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v:32] WARNING: [Synth 8-3848] Net bram in module/entity InstructionMemory does not have driver. [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v:32] WARNING: [Synth 8-3848] Net bram in module/entity InstructionMemory does not have driver. [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v:32] WARNING: [Synth 8-3848] Net bram in module/entity InstructionMemory does not have driver. [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v:32] WARNING: [Synth 8-3848] Net bram in module/entity InstructionMemory does not have driver. [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v:32] WARNING: [Synth 8-3848] Net bram in module/entity InstructionMemory does not have driver. [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v:32] WARNING: [Synth 8-3848] Net bram in module/entity InstructionMemory does not have driver. [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v:32] WARNING: [Synth 8-3848] Net bram in module/entity InstructionMemory does not have driver. [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v:32] WARNING: [Synth 8-3848] Net bram in module/entity InstructionMemory does not have driver. [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v:32] WARNING: [Synth 8-3848] Net bram in module/entity InstructionMemory does not have driver. [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v:32] WARNING: [Synth 8-3848] Net bram in module/entity InstructionMemory does not have driver. [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v:32] WARNING: [Synth 8-3848] Net bram in module/entity InstructionMemory does not have driver. [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v:32] WARNING: [Synth 8-3848] Net bram in module/entity InstructionMemory does not have driver. [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v:32] WARNING: [Synth 8-3848] Net bram in module/entity InstructionMemory does not have driver. [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v:32] WARNING: [Synth 8-3848] Net bram in module/entity InstructionMemory does not have driver. [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v:32] WARNING: [Synth 8-3848] Net bram in module/entity InstructionMemory does not have driver. [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v:32] WARNING: [Synth 8-3848] Net bram in module/entity InstructionMemory does not have driver. [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v:32] WARNING: [Synth 8-3848] Net bram in module/entity InstructionMemory does not have driver. [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v:32] WARNING: [Synth 8-3848] Net bram in module/entity InstructionMemory does not have driver. [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v:32] WARNING: [Synth 8-3848] Net bram in module/entity InstructionMemory does not have driver. [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v:32] WARNING: [Synth 8-3848] Net bram in module/entity InstructionMemory does not have driver. [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v:32] WARNING: [Synth 8-3848] Net bram in module/entity InstructionMemory does not have driver. [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v:32] WARNING: [Synth 8-3848] Net bram in module/entity InstructionMemory does not have driver. [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v:32] WARNING: [Synth 8-3848] Net bram in module/entity InstructionMemory does not have driver. [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v:32] WARNING: [Synth 8-3848] Net bram in module/entity InstructionMemory does not have driver. [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v:32] WARNING: [Synth 8-3848] Net bram in module/entity InstructionMemory does not have driver. [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v:32] WARNING: [Synth 8-3848] Net bram in module/entity InstructionMemory does not have driver. [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v:32] WARNING: [Synth 8-3848] Net bram in module/entity InstructionMemory does not have driver. [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v:32] WARNING: [Synth 8-3848] Net bram in module/entity InstructionMemory does not have driver. [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v:32] WARNING: [Synth 8-3848] Net bram in module/entity InstructionMemory does not have driver. [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v:32] WARNING: [Synth 8-3848] Net bram in module/entity InstructionMemory does not have driver. [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v:32] WARNING: [Synth 8-3848] Net bram in module/entity InstructionMemory does not have driver. [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v:32] WARNING: [Synth 8-3848] Net bram in module/entity InstructionMemory does not have driver. [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v:32] WARNING: [Synth 8-3848] Net bram in module/entity InstructionMemory does not have driver. [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v:32] WARNING: [Synth 8-3848] Net bram in module/entity InstructionMemory does not have driver. [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v:32] WARNING: [Synth 8-3848] Net bram in module/entity InstructionMemory does not have driver. [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v:32] WARNING: [Synth 8-3848] Net bram in module/entity InstructionMemory does not have driver. [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v:32] WARNING: [Synth 8-3848] Net bram in module/entity InstructionMemory does not have driver. [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v:32] WARNING: [Synth 8-3848] Net bram in module/entity InstructionMemory does not have driver. [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v:32] WARNING: [Synth 8-3848] Net bram in module/entity InstructionMemory does not have driver. [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v:32] WARNING: [Synth 8-3848] Net bram in module/entity InstructionMemory does not have driver. [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v:32] WARNING: [Synth 8-3848] Net bram in module/entity InstructionMemory does not have driver. [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v:32] WARNING: [Synth 8-3848] Net bram in module/entity InstructionMemory does not have driver. [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v:32] WARNING: [Synth 8-3848] Net bram in module/entity InstructionMemory does not have driver. [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v:32] WARNING: [Synth 8-3848] Net bram in module/entity InstructionMemory does not have driver. [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v:32] WARNING: [Synth 8-3848] Net bram in module/entity InstructionMemory does not have driver. [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v:32] WARNING: [Synth 8-3848] Net bram in module/entity InstructionMemory does not have driver. [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v:32] WARNING: [Synth 8-3848] Net bram in module/entity InstructionMemory does not have driver. [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v:32] WARNING: [Synth 8-3848] Net bram in module/entity InstructionMemory does not have driver. [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v:32] WARNING: [Synth 8-3848] Net bram in module/entity InstructionMemory does not have driver. [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v:32] WARNING: [Synth 8-3848] Net bram in module/entity InstructionMemory does not have driver. [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v:32] WARNING: [Synth 8-3848] Net bram in module/entity InstructionMemory does not have driver. [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v:32] WARNING: [Synth 8-3848] Net bram in module/entity InstructionMemory does not have driver. [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v:32] WARNING: [Synth 8-3848] Net bram in module/entity InstructionMemory does not have driver. [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v:32] WARNING: [Synth 8-3848] Net bram in module/entity InstructionMemory does not have driver. [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v:32] WARNING: [Synth 8-3848] Net bram in module/entity InstructionMemory does not have driver. [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v:32] WARNING: [Synth 8-3848] Net bram in module/entity InstructionMemory does not have driver. [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v:32] WARNING: [Synth 8-3848] Net bram in module/entity InstructionMemory does not have driver. [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v:32] WARNING: [Synth 8-3848] Net bram in module/entity InstructionMemory does not have driver. [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v:32] WARNING: [Synth 8-3848] Net bram in module/entity InstructionMemory does not have driver. [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v:32] WARNING: [Synth 8-3848] Net bram in module/entity InstructionMemory does not have driver. [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v:32] WARNING: [Synth 8-3848] Net bram in module/entity InstructionMemory does not have driver. [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v:32] WARNING: [Synth 8-3848] Net bram in module/entity InstructionMemory does not have driver. [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v:32] WARNING: [Synth 8-3848] Net bram in module/entity InstructionMemory does not have driver. [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v:32] WARNING: [Synth 8-3848] Net bram in module/entity InstructionMemory does not have driver. [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v:32] WARNING: [Synth 8-3848] Net bram in module/entity InstructionMemory does not have driver. [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v:32] WARNING: [Synth 8-3848] Net bram in module/entity InstructionMemory does not have driver. [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v:32] WARNING: [Synth 8-3848] Net bram in module/entity InstructionMemory does not have driver. [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v:32] WARNING: [Synth 8-3848] Net bram in module/entity InstructionMemory does not have driver. [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v:32] INFO: [Common 17-14] Message 'Synth 8-3848' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'InstructionMemory' (4#1) [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v:23] INFO: [Synth 8-638] synthesizing module 'RegisterFile' [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegisterFile.v:23] INFO: [Synth 8-256] done synthesizing module 'RegisterFile' (5#1) [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegisterFile.v:23] WARNING: [Synth 8-689] width (32) of port connection 'rdata1' does not match port width (1) of module 'RegisterFile' [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:80] WARNING: [Synth 8-689] width (32) of port connection 'rdata2' does not match port width (1) of module 'RegisterFile' [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:80] INFO: [Synth 8-638] synthesizing module 'SignalExtension' [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SignalExtension.v:23] INFO: [Synth 8-256] done synthesizing module 'SignalExtension' (6#1) [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SignalExtension.v:23] INFO: [Synth 8-638] synthesizing module 'ALUControl' [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALUControl.v:35] WARNING: [Synth 8-151] case item 32'b00000000000000000000000001100100 is unreachable [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALUControl.v:44] WARNING: [Synth 8-151] case item 32'b00000000000000000000000001100101 is unreachable [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALUControl.v:45] WARNING: [Synth 8-151] case item 32'b00000000000000000000000001101110 is unreachable [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALUControl.v:46] WARNING: [Synth 8-151] case item 32'b00000000000000000000000000001011 is unreachable [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALUControl.v:41] INFO: [Synth 8-155] case statement is not full and has no default [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALUControl.v:41] INFO: [Synth 8-256] done synthesizing module 'ALUControl' (7#1) [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALUControl.v:35] INFO: [Synth 8-638] synthesizing module 'SimpleALU' [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SimpleALU.v:23] INFO: [Synth 8-256] done synthesizing module 'SimpleALU' (8#1) [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SimpleALU.v:23] WARNING: [Synth 8-689] width (4) of port connection 'op' does not match port width (3) of module 'SimpleALU' [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:83] INFO: [Synth 8-638] synthesizing module 'Multiplexer' [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer.v:23] INFO: [Synth 8-256] done synthesizing module 'Multiplexer' (9#1) [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer.v:23] INFO: [Synth 8-638] synthesizing module 'ShiftUnit' [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ShiftUnit.v:23] INFO: [Synth 8-256] done synthesizing module 'ShiftUnit' (10#1) [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ShiftUnit.v:23] INFO: [Synth 8-638] synthesizing module 'DataMemory' [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v:23] INFO: [Synth 8-256] done synthesizing module 'DataMemory' (11#1) [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v:23] INFO: [Synth 8-256] done synthesizing module 'top' (12#1) [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:34] WARNING: [Synth 8-3331] design DataMemory has unconnected port rdata[31] WARNING: [Synth 8-3331] design DataMemory has unconnected port rdata[30] WARNING: [Synth 8-3331] design DataMemory has unconnected port rdata[29] WARNING: [Synth 8-3331] design DataMemory has unconnected port rdata[28] WARNING: [Synth 8-3331] design DataMemory has unconnected port rdata[27] WARNING: [Synth 8-3331] design DataMemory has unconnected port rdata[26] WARNING: [Synth 8-3331] design DataMemory has unconnected port rdata[25] WARNING: [Synth 8-3331] design DataMemory has unconnected port rdata[24] WARNING: [Synth 8-3331] design DataMemory has unconnected port rdata[23] WARNING: [Synth 8-3331] design DataMemory has unconnected port rdata[22] WARNING: [Synth 8-3331] design DataMemory has unconnected port rdata[21] WARNING: [Synth 8-3331] design DataMemory has unconnected port rdata[20] WARNING: [Synth 8-3331] design DataMemory has unconnected port rdata[19] WARNING: [Synth 8-3331] design DataMemory has unconnected port rdata[18] WARNING: [Synth 8-3331] design DataMemory has unconnected port rdata[17] WARNING: [Synth 8-3331] design DataMemory has unconnected port rdata[16] WARNING: [Synth 8-3331] design DataMemory has unconnected port rdata[15] WARNING: [Synth 8-3331] design DataMemory has unconnected port rdata[14] WARNING: [Synth 8-3331] design DataMemory has unconnected port rdata[13] WARNING: [Synth 8-3331] design DataMemory has unconnected port rdata[12] WARNING: [Synth 8-3331] design DataMemory has unconnected port rdata[11] WARNING: [Synth 8-3331] design DataMemory has unconnected port rdata[10] WARNING: [Synth 8-3331] design DataMemory has unconnected port rdata[9] WARNING: [Synth 8-3331] design DataMemory has unconnected port rdata[8] WARNING: [Synth 8-3331] design DataMemory has unconnected port rdata[7] WARNING: [Synth 8-3331] design DataMemory has unconnected port rdata[6] WARNING: [Synth 8-3331] design DataMemory has unconnected port rdata[5] WARNING: [Synth 8-3331] design DataMemory has unconnected port rdata[4] WARNING: [Synth 8-3331] design DataMemory has unconnected port rdata[3] WARNING: [Synth 8-3331] design DataMemory has unconnected port rdata[2] WARNING: [Synth 8-3331] design DataMemory has unconnected port rdata[1] WARNING: [Synth 8-3331] design DataMemory has unconnected port rdata[0] WARNING: [Synth 8-3331] design DataMemory has unconnected port rd WARNING: [Synth 8-3331] design DataMemory has unconnected port wr WARNING: [Synth 8-3331] design DataMemory has unconnected port addr[31] WARNING: [Synth 8-3331] design DataMemory has unconnected port addr[30] WARNING: [Synth 8-3331] design DataMemory has unconnected port addr[29] WARNING: [Synth 8-3331] design DataMemory has unconnected port addr[28] WARNING: [Synth 8-3331] design DataMemory has unconnected port addr[27] WARNING: [Synth 8-3331] design DataMemory has unconnected port addr[26] WARNING: [Synth 8-3331] design DataMemory has unconnected port addr[25] WARNING: [Synth 8-3331] design DataMemory has unconnected port addr[24] WARNING: [Synth 8-3331] design DataMemory has unconnected port addr[23] WARNING: [Synth 8-3331] design DataMemory has unconnected port addr[22] WARNING: [Synth 8-3331] design DataMemory has unconnected port addr[21] WARNING: [Synth 8-3331] design DataMemory has unconnected port addr[20] WARNING: [Synth 8-3331] design DataMemory has unconnected port addr[19] WARNING: [Synth 8-3331] design DataMemory has unconnected port addr[18] WARNING: [Synth 8-3331] design DataMemory has unconnected port addr[17] WARNING: [Synth 8-3331] design DataMemory has unconnected port addr[16] WARNING: [Synth 8-3331] design DataMemory has unconnected port addr[15] WARNING: [Synth 8-3331] design DataMemory has unconnected port addr[14] WARNING: [Synth 8-3331] design DataMemory has unconnected port addr[13] WARNING: [Synth 8-3331] design DataMemory has unconnected port addr[12] WARNING: [Synth 8-3331] design DataMemory has unconnected port addr[11] WARNING: [Synth 8-3331] design DataMemory has unconnected port addr[10] WARNING: [Synth 8-3331] design DataMemory has unconnected port addr[9] WARNING: [Synth 8-3331] design DataMemory has unconnected port addr[8] WARNING: [Synth 8-3331] design DataMemory has unconnected port addr[7] WARNING: [Synth 8-3331] design DataMemory has unconnected port addr[6] WARNING: [Synth 8-3331] design DataMemory has unconnected port addr[5] WARNING: [Synth 8-3331] design DataMemory has unconnected port addr[4] WARNING: [Synth 8-3331] design DataMemory has unconnected port addr[3] WARNING: [Synth 8-3331] design DataMemory has unconnected port addr[2] WARNING: [Synth 8-3331] design DataMemory has unconnected port addr[1] WARNING: [Synth 8-3331] design DataMemory has unconnected port addr[0] WARNING: [Synth 8-3331] design DataMemory has unconnected port wdata[31] WARNING: [Synth 8-3331] design DataMemory has unconnected port wdata[30] WARNING: [Synth 8-3331] design DataMemory has unconnected port wdata[29] WARNING: [Synth 8-3331] design DataMemory has unconnected port wdata[28] WARNING: [Synth 8-3331] design DataMemory has unconnected port wdata[27] WARNING: [Synth 8-3331] design DataMemory has unconnected port wdata[26] WARNING: [Synth 8-3331] design DataMemory has unconnected port wdata[25] WARNING: [Synth 8-3331] design DataMemory has unconnected port wdata[24] WARNING: [Synth 8-3331] design DataMemory has unconnected port wdata[23] WARNING: [Synth 8-3331] design DataMemory has unconnected port wdata[22] WARNING: [Synth 8-3331] design DataMemory has unconnected port wdata[21] WARNING: [Synth 8-3331] design DataMemory has unconnected port wdata[20] WARNING: [Synth 8-3331] design DataMemory has unconnected port wdata[19] WARNING: [Synth 8-3331] design DataMemory has unconnected port wdata[18] WARNING: [Synth 8-3331] design DataMemory has unconnected port wdata[17] WARNING: [Synth 8-3331] design DataMemory has unconnected port wdata[16] WARNING: [Synth 8-3331] design DataMemory has unconnected port wdata[15] WARNING: [Synth 8-3331] design DataMemory has unconnected port wdata[14] WARNING: [Synth 8-3331] design DataMemory has unconnected port wdata[13] WARNING: [Synth 8-3331] design DataMemory has unconnected port wdata[12] WARNING: [Synth 8-3331] design DataMemory has unconnected port wdata[11] WARNING: [Synth 8-3331] design DataMemory has unconnected port wdata[10] WARNING: [Synth 8-3331] design DataMemory has unconnected port wdata[9] WARNING: [Synth 8-3331] design DataMemory has unconnected port wdata[8] WARNING: [Synth 8-3331] design DataMemory has unconnected port wdata[7] WARNING: [Synth 8-3331] design DataMemory has unconnected port wdata[6] WARNING: [Synth 8-3331] design DataMemory has unconnected port wdata[5] WARNING: [Synth 8-3331] design DataMemory has unconnected port wdata[4] WARNING: [Synth 8-3331] design DataMemory has unconnected port wdata[3] WARNING: [Synth 8-3331] design DataMemory has unconnected port wdata[2] WARNING: [Synth 8-3331] design DataMemory has unconnected port wdata[1] WARNING: [Synth 8-3331] design DataMemory has unconnected port wdata[0] WARNING: [Synth 8-3331] design Multiplexer has unconnected port a[31] WARNING: [Synth 8-3331] design Multiplexer has unconnected port a[30] INFO: [Common 17-14] Message 'Synth 8-3331' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- Finished RTL Elaboration : Time (s): cpu = 00:01:49 ; elapsed = 00:16:29 . Memory (MB): peak = 928.160 ; gain = 721.070 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ WARNING: [Synth 8-3295] tying undriven pin RF:regwr to constant 0 [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:80] --------------------------------------------------------------------------------- Finished RTL Optimization Phase 1 : Time (s): cpu = 00:01:49 ; elapsed = 00:16:29 . Memory (MB): peak = 928.160 ; gain = 721.070 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z030sbg485-1 INFO: [Project 1-570] Preparing netlist for logic optimization Processing XDC Constraints Initializing timing engine Completed Processing XDC Constraints INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. RTL Elaboration Complete: : Time (s): cpu = 00:02:06 ; elapsed = 00:16:50 . Memory (MB): peak = 1289.617 ; gain = 1082.527 31 Infos, 219 Warnings, 1 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:28 . Memory (MB): peak = 1289.617 ; gain = 416.848 write_schematic C:/Users/53194/Desktop/project_789/schematic.sch C:/Users/53194/Desktop/project_789/schematic.sch close_design synth_design -rtl -name rtl_1 Command: synth_design -rtl -name rtl_1 Starting synth_design Using part: xc7z030sbg485-1 Top: top INFO: [Common 17-41] Interrupt caught. Command should exit soon. INFO: [Common 17-344] 'source' was cancelled 2 Infos, 0 Warnings, 0 Critical Warnings and 1 Errors encountered. synth_design failed INFO: [Common 17-344] 'synth_design' was cancelled close_sim INFO: [Simtcl 6-16] Simulation closed launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'top' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj top_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SignalExtension.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module SignalExtension INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ShiftUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ShiftUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegisterFile.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegisterFile INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ProgramCounter.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ProgramCounter INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Multiplexer INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module InstructionMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module DataMemory INFO: [VRFC 10-2458] undeclared symbol out, assumed default net type wire [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v:44] INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ControlUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALUControl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALUControl INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Add1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Add1 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SimpleALU.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module SimpleALU INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module top INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl INFO: [USF-XSim-69] 'compile' step finished in '1' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' Vivado Simulator 2016.2 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: J:/Xilinx/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto 4c388791a4e240948a5554cd0b3617d7 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot top_behav xil_defaultlib.top xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration WARNING: [VRFC 10-278] actual bit length 32 differs from formal bit length 1 for port rdata1 [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:80] WARNING: [VRFC 10-278] actual bit length 4 differs from formal bit length 3 for port op [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:83] Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling module xil_defaultlib.ControlUnit Compiling module xil_defaultlib.ProgramCounter Compiling module xil_defaultlib.Add1 Compiling module xil_defaultlib.InstructionMemory Compiling module xil_defaultlib.RegisterFile Compiling module xil_defaultlib.SignalExtension Compiling module xil_defaultlib.ALUControl Compiling module xil_defaultlib.SimpleALU Compiling module xil_defaultlib.Multiplexer Compiling module xil_defaultlib.ShiftUnit Compiling module xil_defaultlib.DataMemory Compiling module xil_defaultlib.top Compiling module xil_defaultlib.glbl Built simulation snapshot top_behav ****** Webtalk v2016.2 (64-bit) **** SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016 **** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. source C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/xsim.dir/top_behav/webtalk/xsim_webtalk.tcl -notrace INFO: [Common 17-206] Exiting Webtalk at Sun Dec 23 19:59:14 2018... INFO: [USF-XSim-69] 'elaborate' step finished in '4' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' INFO: [USF-XSim-98] *** Running xsim with args "top_behav -key {Behavioral:sim_1:Functional:top} -tclbatch {top.tcl} -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature Vivado Simulator 2016.2 Time resolution is 1 ps source top.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns WARNING: File C:UsersY94Desktopproject_789instruction.txt referenced on C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v at line 37 cannot be opened for reading. Please ensure that this file is available in the current working directory. INFO: [USF-XSim-96] XSim completed. Design snapshot 'top_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:03 ; elapsed = 00:00:09 . Memory (MB): peak = 1313.207 ; gain = 0.000 close_sim INFO: [Simtcl 6-16] Simulation closed close [ open C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALU2.v w ] add_files C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALU2.v update_compile_order -fileset sources_1 update_compile_order -fileset sources_1 launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'top' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj top_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALU2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALU2 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SignalExtension.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module SignalExtension INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ShiftUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ShiftUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegisterFile.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegisterFile INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ProgramCounter.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ProgramCounter INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Multiplexer INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module InstructionMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module DataMemory INFO: [VRFC 10-2458] undeclared symbol out, assumed default net type wire [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v:44] INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ControlUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALUControl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALUControl INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Add1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Add1 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module top INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl INFO: [USF-XSim-69] 'compile' step finished in '1' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' Vivado Simulator 2016.2 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: J:/Xilinx/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto 4c388791a4e240948a5554cd0b3617d7 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot top_behav xil_defaultlib.top xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration WARNING: [VRFC 10-278] actual bit length 32 differs from formal bit length 1 for port rdata1 [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:80] WARNING: [VRFC 10-278] actual bit length 4 differs from formal bit length 3 for port op [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:83] Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling module xil_defaultlib.ControlUnit Compiling module xil_defaultlib.ProgramCounter Compiling module xil_defaultlib.Add1 Compiling module xil_defaultlib.InstructionMemory Compiling module xil_defaultlib.RegisterFile Compiling module xil_defaultlib.SignalExtension Compiling module xil_defaultlib.ALUControl Compiling module xil_defaultlib.ALU2 Compiling module xil_defaultlib.Multiplexer Compiling module xil_defaultlib.ShiftUnit Compiling module xil_defaultlib.DataMemory Compiling module xil_defaultlib.top Compiling module xil_defaultlib.glbl Built simulation snapshot top_behav ****** Webtalk v2016.2 (64-bit) **** SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016 **** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. source C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/xsim.dir/top_behav/webtalk/xsim_webtalk.tcl -notrace INFO: [Common 17-206] Exiting Webtalk at Sun Dec 23 20:14:32 2018... INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' INFO: [USF-XSim-98] *** Running xsim with args "top_behav -key {Behavioral:sim_1:Functional:top} -tclbatch {top.tcl} -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature Vivado Simulator 2016.2 Time resolution is 1 ps source top.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns WARNING: File C:UsersY94Desktopproject_789instruction.txt referenced on C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v at line 37 cannot be opened for reading. Please ensure that this file is available in the current working directory. INFO: [USF-XSim-96] XSim completed. Design snapshot 'top_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:02 ; elapsed = 00:00:06 . Memory (MB): peak = 1313.207 ; gain = 0.000 close_sim INFO: [Simtcl 6-16] Simulation closed remove_files C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Sim_ALU.v remove_files C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Sim_ConnectRamAndReg.v remove_files C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Sim_Reg_group.v remove_files C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Sim_test.v remove_files C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/sim_ram.v remove_files C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALU.v remove_files C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/test.v remove_files {C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SimpleALU.v C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Sim_simpleALU.v} remove_files C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/instruction_coder.v remove_files C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ConnectRamAndReg.v remove_files C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ram.v remove_files C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/reg_group.v reset_run synth_1 launch_runs synth_1 INFO: [HDL 9-2216] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALUControl.v" into library work [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALUControl.v:1] [Sun Dec 23 20:19:14 2018] Launched synth_1... Run output will be captured here: C:/Users/53194/Desktop/project_789/project_78.runs/synth_1/runme.log add_files -norecurse C:/Users/53194/Desktop/project_789/instruction.txt reset_run synth_1 launch_runs synth_1 INFO: [HDL 9-2216] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v" into library work [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:1] [Sun Dec 23 20:27:01 2018] Launched synth_1... Run output will be captured here: C:/Users/53194/Desktop/project_789/project_78.runs/synth_1/runme.log launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'top' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj top_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALU2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALU2 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SignalExtension.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module SignalExtension INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ShiftUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ShiftUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegisterFile.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegisterFile INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ProgramCounter.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ProgramCounter INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Multiplexer INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module InstructionMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module DataMemory INFO: [VRFC 10-2458] undeclared symbol out, assumed default net type wire [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v:44] INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ControlUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALUControl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALUControl INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Add1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Add1 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module top INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl INFO: [USF-XSim-69] 'compile' step finished in '1' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' Vivado Simulator 2016.2 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: J:/Xilinx/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto 4c388791a4e240948a5554cd0b3617d7 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot top_behav xil_defaultlib.top xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling module xil_defaultlib.ControlUnit Compiling module xil_defaultlib.ProgramCounter Compiling module xil_defaultlib.Add1 Compiling module xil_defaultlib.InstructionMemory Compiling module xil_defaultlib.RegisterFile Compiling module xil_defaultlib.SignalExtension Compiling module xil_defaultlib.ALUControl Compiling module xil_defaultlib.ALU2 Compiling module xil_defaultlib.Multiplexer Compiling module xil_defaultlib.ShiftUnit Compiling module xil_defaultlib.DataMemory Compiling module xil_defaultlib.top Compiling module xil_defaultlib.glbl Built simulation snapshot top_behav ****** Webtalk v2016.2 (64-bit) **** SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016 **** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. source C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/xsim.dir/top_behav/webtalk/xsim_webtalk.tcl -notrace INFO: [Common 17-206] Exiting Webtalk at Sun Dec 23 20:30:25 2018... INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' INFO: [USF-XSim-98] *** Running xsim with args "top_behav -key {Behavioral:sim_1:Functional:top} -tclbatch {top.tcl} -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature Vivado Simulator 2016.2 Time resolution is 1 ps source top.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns WARNING: File C:UsersY94Desktopproject_789instruction.txt referenced on C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v at line 37 cannot be opened for reading. Please ensure that this file is available in the current working directory. INFO: [USF-XSim-96] XSim completed. Design snapshot 'top_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:02 ; elapsed = 00:00:07 . Memory (MB): peak = 1313.207 ; gain = 0.000 close_sim INFO: [Simtcl 6-16] Simulation closed reset_run synth_1 launch_runs synth_1 INFO: [HDL 9-2216] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v" into library work [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:1] [Sun Dec 23 20:31:05 2018] Launched synth_1... Run output will be captured here: C:/Users/53194/Desktop/project_789/project_78.runs/synth_1/runme.log reset_run synth_1 launch_runs synth_1 INFO: [HDL 9-2216] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALUControl.v" into library work [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALUControl.v:1] [Sun Dec 23 20:37:15 2018] Launched synth_1... Run output will be captured here: C:/Users/53194/Desktop/project_789/project_78.runs/synth_1/runme.log add_files -norecurse C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/test.v update_compile_order -fileset sources_1 set_property top test [get_filesets sim_1] set_property top_lib xil_defaultlib [get_filesets sim_1] launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'test' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj test_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/test.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module test INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl INFO: [USF-XSim-69] 'compile' step finished in '1' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' Vivado Simulator 2016.2 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: J:/Xilinx/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto 4c388791a4e240948a5554cd0b3617d7 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot test_behav xil_defaultlib.test xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling module xil_defaultlib.test Compiling module xil_defaultlib.glbl Built simulation snapshot test_behav ****** Webtalk v2016.2 (64-bit) **** SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016 **** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. source C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/xsim.dir/test_behav/webtalk/xsim_webtalk.tcl -notrace INFO: [Common 17-206] Exiting Webtalk at Sun Dec 23 20:55:38 2018... INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' INFO: [USF-XSim-98] *** Running xsim with args "test_behav -key {Behavioral:sim_1:Functional:test} -tclbatch {test.tcl} -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature Vivado Simulator 2016.2 Time resolution is 1 ps source test.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns WARNING: File instruction.txt referenced on C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/test.v at line 29 cannot be opened for reading. Please ensure that this file is available in the current working directory. INFO: [USF-XSim-96] XSim completed. Design snapshot 'test_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:01 ; elapsed = 00:00:06 . Memory (MB): peak = 1313.207 ; gain = 0.000 close_sim INFO: [Simtcl 6-16] Simulation closed set_property top test [current_fileset] update_compile_order -fileset sources_1 reset_run synth_1 launch_runs synth_1 INFO: [HDL 9-2216] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v" into library work [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v:1] [Sun Dec 23 20:56:06 2018] Launched synth_1... Run output will be captured here: C:/Users/53194/Desktop/project_789/project_78.runs/synth_1/runme.log add_files -norecurse C:/Users/53194/Desktop/project_789/instruction.txt WARNING: [filemgmt 56-12] File 'C:/Users/53194/Desktop/project_789/instruction.txt' cannot be added to the project because it already exists in the project, skipping this file reset_run synth_1 launch_runs synth_1 INFO: [HDL 9-2216] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/test.v" into library work [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/test.v:1] [Sun Dec 23 20:59:55 2018] Launched synth_1... Run output will be captured here: C:/Users/53194/Desktop/project_789/project_78.runs/synth_1/runme.log remove_files C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/test.v update_compile_order -fileset sources_1 update_compile_order -fileset sim_1 launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'top' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj top_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SignalExtension.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module SignalExtension INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ShiftUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ShiftUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegisterFile.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegisterFile INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ProgramCounter.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ProgramCounter INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Multiplexer INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module InstructionMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module DataMemory INFO: [VRFC 10-2458] undeclared symbol out, assumed default net type wire [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v:44] INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ControlUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALUControl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALUControl INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALU2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALU2 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Add1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Add1 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module top INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl INFO: [USF-XSim-69] 'compile' step finished in '1' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' Vivado Simulator 2016.2 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: J:/Xilinx/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto 4c388791a4e240948a5554cd0b3617d7 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot top_behav xil_defaultlib.top xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling module xil_defaultlib.ControlUnit Compiling module xil_defaultlib.ProgramCounter Compiling module xil_defaultlib.Add1 Compiling module xil_defaultlib.InstructionMemory Compiling module xil_defaultlib.RegisterFile Compiling module xil_defaultlib.SignalExtension Compiling module xil_defaultlib.ALUControl Compiling module xil_defaultlib.ALU2 Compiling module xil_defaultlib.Multiplexer Compiling module xil_defaultlib.ShiftUnit Compiling module xil_defaultlib.DataMemory Compiling module xil_defaultlib.top Compiling module xil_defaultlib.glbl Built simulation snapshot top_behav ****** Webtalk v2016.2 (64-bit) **** SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016 **** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. source C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/xsim.dir/top_behav/webtalk/xsim_webtalk.tcl -notrace INFO: [Common 17-206] Exiting Webtalk at Sun Dec 23 21:01:17 2018... INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' INFO: [USF-XSim-98] *** Running xsim with args "top_behav -key {Behavioral:sim_1:Functional:top} -tclbatch {top.tcl} -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature Vivado Simulator 2016.2 Time resolution is 1 ps source top.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns INFO: [USF-XSim-96] XSim completed. Design snapshot 'top_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:01 ; elapsed = 00:00:06 . Memory (MB): peak = 1313.207 ; gain = 0.000 close_sim INFO: [Simtcl 6-16] Simulation closed launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'top' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj top_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SignalExtension.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module SignalExtension INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ShiftUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ShiftUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegisterFile.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegisterFile INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ProgramCounter.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ProgramCounter INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Multiplexer INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module InstructionMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module DataMemory INFO: [VRFC 10-2458] undeclared symbol out, assumed default net type wire [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v:44] INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ControlUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALUControl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALUControl INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALU2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALU2 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Add1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Add1 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module top INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl INFO: [USF-XSim-69] 'compile' step finished in '1' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' Vivado Simulator 2016.2 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: J:/Xilinx/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto 4c388791a4e240948a5554cd0b3617d7 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot top_behav xil_defaultlib.top xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling module xil_defaultlib.ControlUnit Compiling module xil_defaultlib.ProgramCounter Compiling module xil_defaultlib.Add1 Compiling module xil_defaultlib.InstructionMemory Compiling module xil_defaultlib.RegisterFile Compiling module xil_defaultlib.SignalExtension Compiling module xil_defaultlib.ALUControl Compiling module xil_defaultlib.ALU2 Compiling module xil_defaultlib.Multiplexer Compiling module xil_defaultlib.ShiftUnit Compiling module xil_defaultlib.DataMemory Compiling module xil_defaultlib.top Compiling module xil_defaultlib.glbl Built simulation snapshot top_behav ****** Webtalk v2016.2 (64-bit) **** SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016 **** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. source C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/xsim.dir/top_behav/webtalk/xsim_webtalk.tcl -notrace INFO: [Common 17-206] Exiting Webtalk at Sun Dec 23 21:15:11 2018... INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' INFO: [USF-XSim-98] *** Running xsim with args "top_behav -key {Behavioral:sim_1:Functional:top} -tclbatch {top.tcl} -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature Vivado Simulator 2016.2 Time resolution is 1 ps source top.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns INFO: [USF-XSim-96] XSim completed. Design snapshot 'top_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:03 ; elapsed = 00:00:07 . Memory (MB): peak = 1313.207 ; gain = 0.000 close_sim INFO: [Simtcl 6-16] Simulation closed launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'top' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj top_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SignalExtension.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module SignalExtension INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ShiftUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ShiftUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegisterFile.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegisterFile INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ProgramCounter.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ProgramCounter INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Multiplexer INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module InstructionMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module DataMemory INFO: [VRFC 10-2458] undeclared symbol out, assumed default net type wire [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v:44] INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ControlUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALUControl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALUControl INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALU2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALU2 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Add1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Add1 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module top INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl INFO: [USF-XSim-69] 'compile' step finished in '1' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' Vivado Simulator 2016.2 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: J:/Xilinx/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto 4c388791a4e240948a5554cd0b3617d7 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot top_behav xil_defaultlib.top xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling module xil_defaultlib.ControlUnit Compiling module xil_defaultlib.ProgramCounter Compiling module xil_defaultlib.Add1 Compiling module xil_defaultlib.InstructionMemory Compiling module xil_defaultlib.RegisterFile Compiling module xil_defaultlib.SignalExtension Compiling module xil_defaultlib.ALUControl Compiling module xil_defaultlib.ALU2 Compiling module xil_defaultlib.Multiplexer Compiling module xil_defaultlib.ShiftUnit Compiling module xil_defaultlib.DataMemory Compiling module xil_defaultlib.top Compiling module xil_defaultlib.glbl Built simulation snapshot top_behav ****** Webtalk v2016.2 (64-bit) **** SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016 **** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. source C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/xsim.dir/top_behav/webtalk/xsim_webtalk.tcl -notrace INFO: [Common 17-206] Exiting Webtalk at Sun Dec 23 21:20:16 2018... INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' INFO: [USF-XSim-98] *** Running xsim with args "top_behav -key {Behavioral:sim_1:Functional:top} -tclbatch {top.tcl} -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature Vivado Simulator 2016.2 Time resolution is 1 ps source top.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns INFO: [USF-XSim-96] XSim completed. Design snapshot 'top_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:03 ; elapsed = 00:00:07 . Memory (MB): peak = 1313.207 ; gain = 0.000 close_sim INFO: [Simtcl 6-16] Simulation closed launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'top' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' INFO: [Common 17-41] Interrupt caught. Command should exit soon. "xvlog -m64 --relax -prj top_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SignalExtension.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module SignalExtension INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ShiftUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ShiftUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegisterFile.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegisterFile INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ProgramCounter.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ProgramCounter INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Multiplexer INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module InstructionMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module DataMemory INFO: [VRFC 10-2458] undeclared symbol out, assumed default net type wire [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v:44] INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ControlUnit ERROR: [VRFC 10-794] illegal character in binary number [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v:53] ERROR: [VRFC 10-1412] syntax error near 'b [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v:53] ERROR: [VRFC 10-1040] module ControlUnit ignored due to previous errors [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v:36] INFO: [Common 17-344] 'run_program' was cancelled INFO: [Vivado 12-4703] 'compile' step aborted INFO: [Common 17-344] 'launch_simulation' was cancelled launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'top' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj top_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SignalExtension.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module SignalExtension INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ShiftUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ShiftUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegisterFile.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegisterFile INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ProgramCounter.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ProgramCounter INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Multiplexer INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module InstructionMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module DataMemory INFO: [VRFC 10-2458] undeclared symbol out, assumed default net type wire [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v:44] INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ControlUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALUControl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALUControl INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALU2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALU2 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Add1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Add1 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module top INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl INFO: [USF-XSim-69] 'compile' step finished in '1' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' Vivado Simulator 2016.2 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: J:/Xilinx/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto 4c388791a4e240948a5554cd0b3617d7 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot top_behav xil_defaultlib.top xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling module xil_defaultlib.ControlUnit Compiling module xil_defaultlib.ProgramCounter Compiling module xil_defaultlib.Add1 Compiling module xil_defaultlib.InstructionMemory Compiling module xil_defaultlib.RegisterFile Compiling module xil_defaultlib.SignalExtension Compiling module xil_defaultlib.ALUControl Compiling module xil_defaultlib.ALU2 Compiling module xil_defaultlib.Multiplexer Compiling module xil_defaultlib.ShiftUnit Compiling module xil_defaultlib.DataMemory Compiling module xil_defaultlib.top Compiling module xil_defaultlib.glbl Built simulation snapshot top_behav ****** Webtalk v2016.2 (64-bit) **** SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016 **** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. source C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/xsim.dir/top_behav/webtalk/xsim_webtalk.tcl -notrace INFO: [Common 17-206] Exiting Webtalk at Sun Dec 23 21:26:56 2018... INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' INFO: [USF-XSim-98] *** Running xsim with args "top_behav -key {Behavioral:sim_1:Functional:top} -tclbatch {top.tcl} -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature Vivado Simulator 2016.2 Time resolution is 1 ps source top.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns INFO: [USF-XSim-96] XSim completed. Design snapshot 'top_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:01 ; elapsed = 00:00:06 . Memory (MB): peak = 1313.207 ; gain = 0.000 close_sim INFO: [Simtcl 6-16] Simulation closed launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'top' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj top_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SignalExtension.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module SignalExtension INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ShiftUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ShiftUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegisterFile.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegisterFile INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ProgramCounter.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ProgramCounter INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Multiplexer INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module InstructionMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module DataMemory INFO: [VRFC 10-2458] undeclared symbol out, assumed default net type wire [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v:44] INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ControlUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALUControl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALUControl INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALU2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALU2 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Add1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Add1 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module top INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl INFO: [USF-XSim-69] 'compile' step finished in '1' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' Vivado Simulator 2016.2 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: J:/Xilinx/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto 4c388791a4e240948a5554cd0b3617d7 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot top_behav xil_defaultlib.top xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling module xil_defaultlib.ControlUnit Compiling module xil_defaultlib.ProgramCounter Compiling module xil_defaultlib.Add1 Compiling module xil_defaultlib.InstructionMemory Compiling module xil_defaultlib.RegisterFile Compiling module xil_defaultlib.SignalExtension Compiling module xil_defaultlib.ALUControl Compiling module xil_defaultlib.ALU2 Compiling module xil_defaultlib.Multiplexer Compiling module xil_defaultlib.ShiftUnit Compiling module xil_defaultlib.DataMemory Compiling module xil_defaultlib.top Compiling module xil_defaultlib.glbl Built simulation snapshot top_behav ****** Webtalk v2016.2 (64-bit) **** SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016 **** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. source C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/xsim.dir/top_behav/webtalk/xsim_webtalk.tcl -notrace INFO: [Common 17-206] Exiting Webtalk at Sun Dec 23 21:36:54 2018... INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' INFO: [USF-XSim-98] *** Running xsim with args "top_behav -key {Behavioral:sim_1:Functional:top} -tclbatch {top.tcl} -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature Vivado Simulator 2016.2 Time resolution is 1 ps source top.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns INFO: [USF-XSim-96] XSim completed. Design snapshot 'top_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:02 ; elapsed = 00:00:08 . Memory (MB): peak = 1313.207 ; gain = 0.000 close_sim INFO: [Simtcl 6-16] Simulation closed launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'top' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj top_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SignalExtension.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module SignalExtension INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ShiftUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ShiftUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegisterFile.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegisterFile INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ProgramCounter.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ProgramCounter INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Multiplexer INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module InstructionMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module DataMemory INFO: [VRFC 10-2458] undeclared symbol out, assumed default net type wire [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v:44] INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ControlUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALUControl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALUControl INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALU2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALU2 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Add1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Add1 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module top INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl INFO: [USF-XSim-69] 'compile' step finished in '2' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' Vivado Simulator 2016.2 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: J:/Xilinx/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto 4c388791a4e240948a5554cd0b3617d7 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot top_behav xil_defaultlib.top xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling module xil_defaultlib.ControlUnit Compiling module xil_defaultlib.ProgramCounter Compiling module xil_defaultlib.Add1 Compiling module xil_defaultlib.InstructionMemory Compiling module xil_defaultlib.RegisterFile Compiling module xil_defaultlib.SignalExtension Compiling module xil_defaultlib.ALUControl Compiling module xil_defaultlib.ALU2 Compiling module xil_defaultlib.Multiplexer Compiling module xil_defaultlib.ShiftUnit Compiling module xil_defaultlib.DataMemory Compiling module xil_defaultlib.top Compiling module xil_defaultlib.glbl Built simulation snapshot top_behav ****** Webtalk v2016.2 (64-bit) **** SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016 **** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. source C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/xsim.dir/top_behav/webtalk/xsim_webtalk.tcl -notrace INFO: [Common 17-206] Exiting Webtalk at Sun Dec 23 21:38:12 2018... INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' INFO: [USF-XSim-98] *** Running xsim with args "top_behav -key {Behavioral:sim_1:Functional:top} -tclbatch {top.tcl} -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature Vivado Simulator 2016.2 Time resolution is 1 ps source top.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns INFO: [USF-XSim-96] XSim completed. Design snapshot 'top_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:03 ; elapsed = 00:00:08 . Memory (MB): peak = 1313.207 ; gain = 0.000 close_sim INFO: [Simtcl 6-16] Simulation closed launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'top' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj top_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SignalExtension.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module SignalExtension INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ShiftUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ShiftUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegisterFile.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegisterFile INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ProgramCounter.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ProgramCounter INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Multiplexer INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module InstructionMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module DataMemory INFO: [VRFC 10-2458] undeclared symbol out, assumed default net type wire [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v:44] INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ControlUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALUControl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALUControl INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALU2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALU2 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Add1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Add1 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module top INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl INFO: [USF-XSim-69] 'compile' step finished in '1' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' Vivado Simulator 2016.2 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: J:/Xilinx/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto 4c388791a4e240948a5554cd0b3617d7 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot top_behav xil_defaultlib.top xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling module xil_defaultlib.ControlUnit Compiling module xil_defaultlib.ProgramCounter Compiling module xil_defaultlib.Add1 Compiling module xil_defaultlib.InstructionMemory Compiling module xil_defaultlib.RegisterFile Compiling module xil_defaultlib.SignalExtension Compiling module xil_defaultlib.ALUControl Compiling module xil_defaultlib.ALU2 Compiling module xil_defaultlib.Multiplexer Compiling module xil_defaultlib.ShiftUnit Compiling module xil_defaultlib.DataMemory Compiling module xil_defaultlib.top Compiling module xil_defaultlib.glbl Built simulation snapshot top_behav ****** Webtalk v2016.2 (64-bit) **** SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016 **** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. source C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/xsim.dir/top_behav/webtalk/xsim_webtalk.tcl -notrace INFO: [Common 17-206] Exiting Webtalk at Sun Dec 23 21:39:59 2018... INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' INFO: [USF-XSim-98] *** Running xsim with args "top_behav -key {Behavioral:sim_1:Functional:top} -tclbatch {top.tcl} -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature Vivado Simulator 2016.2 Time resolution is 1 ps source top.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns INFO: [USF-XSim-96] XSim completed. Design snapshot 'top_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:03 ; elapsed = 00:00:08 . Memory (MB): peak = 1313.207 ; gain = 0.000 close_sim INFO: [Simtcl 6-16] Simulation closed launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'top' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj top_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SignalExtension.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module SignalExtension INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ShiftUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ShiftUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegisterFile.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegisterFile INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ProgramCounter.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ProgramCounter INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Multiplexer INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module InstructionMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module DataMemory INFO: [VRFC 10-2458] undeclared symbol out, assumed default net type wire [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v:44] INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ControlUnit ERROR: [VRFC 10-1532] use of undefined macro LW [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v:32] ERROR: [VRFC 10-1412] syntax error near ) [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v:32] ERROR: [VRFC 10-1532] use of undefined macro J [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v:33] ERROR: [VRFC 10-1412] syntax error near ) [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v:33] ERROR: [VRFC 10-1532] use of undefined macro R [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v:34] ERROR: [VRFC 10-1412] syntax error near ) [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v:34] ERROR: [VRFC 10-1532] use of undefined macro BEQ [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v:35] ERROR: [VRFC 10-1412] syntax error near ) [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v:35] ERROR: [VRFC 10-1412] syntax error near ) [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v:36] ERROR: [VRFC 10-1412] syntax error near ) [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v:37] ERROR: [VRFC 10-1532] use of undefined macro SW [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v:38] ERROR: [VRFC 10-1412] syntax error near ) [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v:38] ERROR: [VRFC 10-1412] syntax error near || [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v:39] ERROR: [VRFC 10-1040] module ControlUnit ignored due to previous errors [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v:21] INFO: [USF-XSim-69] 'compile' step finished in '1' seconds INFO: [USF-XSim-99] Step results log file:'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/xvlog.log' ERROR: [USF-XSim-62] 'compile' step failed with error(s). Please check the Tcl console output or 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/xvlog.log' file for more information. ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation. ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors. launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'top' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj top_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SignalExtension.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module SignalExtension INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ShiftUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ShiftUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegisterFile.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegisterFile INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ProgramCounter.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ProgramCounter INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Multiplexer INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module InstructionMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module DataMemory INFO: [VRFC 10-2458] undeclared symbol out, assumed default net type wire [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v:44] INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ControlUnit ERROR: [VRFC 10-1532] use of undefined macro LW [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v:32] ERROR: [VRFC 10-1412] syntax error near ) [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v:32] ERROR: [VRFC 10-1532] use of undefined macro J [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v:33] ERROR: [VRFC 10-1412] syntax error near ) [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v:33] ERROR: [VRFC 10-1532] use of undefined macro R [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v:34] ERROR: [VRFC 10-1412] syntax error near ) [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v:34] ERROR: [VRFC 10-1532] use of undefined macro BEQ [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v:35] ERROR: [VRFC 10-1412] syntax error near ) [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v:35] ERROR: [VRFC 10-1412] syntax error near ) [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v:36] ERROR: [VRFC 10-1412] syntax error near ) [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v:37] ERROR: [VRFC 10-1532] use of undefined macro SW [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v:38] ERROR: [VRFC 10-1412] syntax error near ) [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v:38] ERROR: [VRFC 10-1412] syntax error near || [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v:39] ERROR: [VRFC 10-1040] module ControlUnit ignored due to previous errors [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v:21] INFO: [USF-XSim-69] 'compile' step finished in '1' seconds INFO: [USF-XSim-99] Step results log file:'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/xvlog.log' ERROR: [USF-XSim-62] 'compile' step failed with error(s). Please check the Tcl console output or 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/xvlog.log' file for more information. ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation. ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors. launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'top' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj top_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SignalExtension.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module SignalExtension INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ShiftUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ShiftUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegisterFile.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegisterFile INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ProgramCounter.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ProgramCounter INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Multiplexer INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module InstructionMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module DataMemory INFO: [VRFC 10-2458] undeclared symbol out, assumed default net type wire [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v:44] INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ControlUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALUControl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALUControl INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALU2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALU2 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Add1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Add1 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module top INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl INFO: [USF-XSim-69] 'compile' step finished in '1' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' Vivado Simulator 2016.2 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: J:/Xilinx/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto 4c388791a4e240948a5554cd0b3617d7 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot top_behav xil_defaultlib.top xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling module xil_defaultlib.ControlUnit Compiling module xil_defaultlib.ProgramCounter Compiling module xil_defaultlib.Add1 Compiling module xil_defaultlib.InstructionMemory Compiling module xil_defaultlib.RegisterFile Compiling module xil_defaultlib.SignalExtension Compiling module xil_defaultlib.ALUControl Compiling module xil_defaultlib.ALU2 Compiling module xil_defaultlib.Multiplexer Compiling module xil_defaultlib.ShiftUnit Compiling module xil_defaultlib.DataMemory Compiling module xil_defaultlib.top Compiling module xil_defaultlib.glbl Built simulation snapshot top_behav ****** Webtalk v2016.2 (64-bit) **** SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016 **** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. source C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/xsim.dir/top_behav/webtalk/xsim_webtalk.tcl -notrace INFO: [Common 17-206] Exiting Webtalk at Sun Dec 23 21:49:00 2018... INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' INFO: [USF-XSim-98] *** Running xsim with args "top_behav -key {Behavioral:sim_1:Functional:top} -tclbatch {top.tcl} -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature Vivado Simulator 2016.2 Time resolution is 1 ps source top.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns INFO: [USF-XSim-96] XSim completed. Design snapshot 'top_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:01 ; elapsed = 00:00:06 . Memory (MB): peak = 1313.207 ; gain = 0.000 close_sim INFO: [Simtcl 6-16] Simulation closed launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'top' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj top_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SignalExtension.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module SignalExtension INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ShiftUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ShiftUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegisterFile.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegisterFile INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ProgramCounter.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ProgramCounter INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Multiplexer INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module InstructionMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module DataMemory INFO: [VRFC 10-2458] undeclared symbol out, assumed default net type wire [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v:44] INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ControlUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALUControl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALUControl INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALU2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALU2 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Add1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Add1 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module top INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl INFO: [USF-XSim-69] 'compile' step finished in '1' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' Vivado Simulator 2016.2 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: J:/Xilinx/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto 4c388791a4e240948a5554cd0b3617d7 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot top_behav xil_defaultlib.top xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling module xil_defaultlib.ControlUnit Compiling module xil_defaultlib.ProgramCounter Compiling module xil_defaultlib.Add1 Compiling module xil_defaultlib.InstructionMemory Compiling module xil_defaultlib.RegisterFile Compiling module xil_defaultlib.SignalExtension Compiling module xil_defaultlib.ALUControl Compiling module xil_defaultlib.ALU2 Compiling module xil_defaultlib.Multiplexer Compiling module xil_defaultlib.ShiftUnit Compiling module xil_defaultlib.DataMemory Compiling module xil_defaultlib.top Compiling module xil_defaultlib.glbl Built simulation snapshot top_behav ****** Webtalk v2016.2 (64-bit) **** SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016 **** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. source C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/xsim.dir/top_behav/webtalk/xsim_webtalk.tcl -notrace INFO: [Common 17-206] Exiting Webtalk at Sun Dec 23 22:14:36 2018... INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' INFO: [USF-XSim-98] *** Running xsim with args "top_behav -key {Behavioral:sim_1:Functional:top} -tclbatch {top.tcl} -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature Vivado Simulator 2016.2 Time resolution is 1 ps source top.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns INFO: [USF-XSim-96] XSim completed. Design snapshot 'top_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:02 ; elapsed = 00:00:07 . Memory (MB): peak = 1313.207 ; gain = 0.000 close_sim INFO: [Simtcl 6-16] Simulation closed launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'top' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj top_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SignalExtension.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module SignalExtension INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ShiftUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ShiftUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegisterFile.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegisterFile INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ProgramCounter.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ProgramCounter INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Multiplexer INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module InstructionMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module DataMemory INFO: [VRFC 10-2458] undeclared symbol out, assumed default net type wire [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v:44] INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ControlUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALUControl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALUControl INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALU2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALU2 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Add1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Add1 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module top INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl INFO: [USF-XSim-69] 'compile' step finished in '1' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' Vivado Simulator 2016.2 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: J:/Xilinx/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto 4c388791a4e240948a5554cd0b3617d7 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot top_behav xil_defaultlib.top xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling module xil_defaultlib.ControlUnit Compiling module xil_defaultlib.ProgramCounter Compiling module xil_defaultlib.Add1 Compiling module xil_defaultlib.InstructionMemory Compiling module xil_defaultlib.RegisterFile Compiling module xil_defaultlib.SignalExtension Compiling module xil_defaultlib.ALUControl Compiling module xil_defaultlib.ALU2 Compiling module xil_defaultlib.Multiplexer Compiling module xil_defaultlib.ShiftUnit Compiling module xil_defaultlib.DataMemory Compiling module xil_defaultlib.top Compiling module xil_defaultlib.glbl Built simulation snapshot top_behav ****** Webtalk v2016.2 (64-bit) **** SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016 **** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. source C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/xsim.dir/top_behav/webtalk/xsim_webtalk.tcl -notrace INFO: [Common 17-206] Exiting Webtalk at Sun Dec 23 22:16:53 2018... INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' INFO: [USF-XSim-98] *** Running xsim with args "top_behav -key {Behavioral:sim_1:Functional:top} -tclbatch {top.tcl} -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature Vivado Simulator 2016.2 Time resolution is 1 ps source top.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns INFO: [USF-XSim-96] XSim completed. Design snapshot 'top_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:03 ; elapsed = 00:00:08 . Memory (MB): peak = 1313.207 ; gain = 0.000 close_sim INFO: [Simtcl 6-16] Simulation closed launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'top' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj top_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SignalExtension.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module SignalExtension INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ShiftUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ShiftUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegisterFile.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegisterFile INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ProgramCounter.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ProgramCounter INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Multiplexer INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module InstructionMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module DataMemory INFO: [VRFC 10-2458] undeclared symbol out, assumed default net type wire [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v:44] INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ControlUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALUControl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALUControl INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALU2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALU2 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Add1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Add1 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module top INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl INFO: [USF-XSim-69] 'compile' step finished in '1' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' Vivado Simulator 2016.2 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: J:/Xilinx/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto 4c388791a4e240948a5554cd0b3617d7 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot top_behav xil_defaultlib.top xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling module xil_defaultlib.ControlUnit Compiling module xil_defaultlib.ProgramCounter Compiling module xil_defaultlib.Add1 Compiling module xil_defaultlib.InstructionMemory Compiling module xil_defaultlib.RegisterFile Compiling module xil_defaultlib.SignalExtension Compiling module xil_defaultlib.ALUControl Compiling module xil_defaultlib.ALU2 Compiling module xil_defaultlib.Multiplexer Compiling module xil_defaultlib.ShiftUnit Compiling module xil_defaultlib.DataMemory Compiling module xil_defaultlib.top Compiling module xil_defaultlib.glbl Built simulation snapshot top_behav ****** Webtalk v2016.2 (64-bit) **** SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016 **** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. source C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/xsim.dir/top_behav/webtalk/xsim_webtalk.tcl -notrace INFO: [Common 17-206] Exiting Webtalk at Sun Dec 23 22:18:35 2018... INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' INFO: [USF-XSim-98] *** Running xsim with args "top_behav -key {Behavioral:sim_1:Functional:top} -tclbatch {top.tcl} -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature Vivado Simulator 2016.2 Time resolution is 1 ps source top.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns INFO: [USF-XSim-96] XSim completed. Design snapshot 'top_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:02 ; elapsed = 00:00:07 . Memory (MB): peak = 1313.207 ; gain = 0.000 close_sim INFO: [Simtcl 6-16] Simulation closed launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'top' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj top_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SignalExtension.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module SignalExtension INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ShiftUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ShiftUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegisterFile.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegisterFile INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ProgramCounter.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ProgramCounter INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Multiplexer INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module InstructionMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module DataMemory INFO: [VRFC 10-2458] undeclared symbol out, assumed default net type wire [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v:44] INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ControlUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALUControl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALUControl INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALU2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALU2 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Add1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Add1 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module top INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl INFO: [USF-XSim-69] 'compile' step finished in '1' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' Vivado Simulator 2016.2 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: J:/Xilinx/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto 4c388791a4e240948a5554cd0b3617d7 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot top_behav xil_defaultlib.top xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling module xil_defaultlib.ControlUnit Compiling module xil_defaultlib.ProgramCounter Compiling module xil_defaultlib.Add1 Compiling module xil_defaultlib.InstructionMemory Compiling module xil_defaultlib.RegisterFile Compiling module xil_defaultlib.SignalExtension Compiling module xil_defaultlib.ALUControl Compiling module xil_defaultlib.ALU2 Compiling module xil_defaultlib.Multiplexer Compiling module xil_defaultlib.ShiftUnit Compiling module xil_defaultlib.DataMemory Compiling module xil_defaultlib.top Compiling module xil_defaultlib.glbl Built simulation snapshot top_behav ****** Webtalk v2016.2 (64-bit) **** SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016 **** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. source C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/xsim.dir/top_behav/webtalk/xsim_webtalk.tcl -notrace INFO: [Common 17-206] Exiting Webtalk at Sun Dec 23 22:19:54 2018... INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' INFO: [USF-XSim-98] *** Running xsim with args "top_behav -key {Behavioral:sim_1:Functional:top} -tclbatch {top.tcl} -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature Vivado Simulator 2016.2 Time resolution is 1 ps source top.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns INFO: [USF-XSim-96] XSim completed. Design snapshot 'top_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:02 ; elapsed = 00:00:07 . Memory (MB): peak = 1313.207 ; gain = 0.000 close_sim INFO: [Simtcl 6-16] Simulation closed close [ open C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Sim_multi.v w ] add_files C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Sim_multi.v update_compile_order -fileset sources_1 set_property top Sim_multi [get_filesets sim_1] set_property top_lib xil_defaultlib [get_filesets sim_1] launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'Sim_multi' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj Sim_multi_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Multiplexer INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Sim_multi.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Sim_multi INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl INFO: [USF-XSim-69] 'compile' step finished in '1' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' Vivado Simulator 2016.2 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: J:/Xilinx/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto 4c388791a4e240948a5554cd0b3617d7 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot Sim_multi_behav xil_defaultlib.Sim_multi xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling module xil_defaultlib.Multiplexer Compiling module xil_defaultlib.Sim_multi Compiling module xil_defaultlib.glbl Built simulation snapshot Sim_multi_behav ****** Webtalk v2016.2 (64-bit) **** SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016 **** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. source C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/xsim.dir/Sim_multi_behav/webtalk/xsim_webtalk.tcl -notrace INFO: [Common 17-206] Exiting Webtalk at Sun Dec 23 22:25:44 2018... INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' INFO: [USF-XSim-98] *** Running xsim with args "Sim_multi_behav -key {Behavioral:sim_1:Functional:Sim_multi} -tclbatch {Sim_multi.tcl} -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature Vivado Simulator 2016.2 Time resolution is 1 ps source Sim_multi.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns INFO: [USF-XSim-96] XSim completed. Design snapshot 'Sim_multi_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:01 ; elapsed = 00:00:06 . Memory (MB): peak = 1313.207 ; gain = 0.000 close_sim INFO: [Simtcl 6-16] Simulation closed launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'Sim_multi' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj Sim_multi_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Multiplexer INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Sim_multi.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Sim_multi INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl INFO: [USF-XSim-69] 'compile' step finished in '1' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' Vivado Simulator 2016.2 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: J:/Xilinx/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto 4c388791a4e240948a5554cd0b3617d7 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot Sim_multi_behav xil_defaultlib.Sim_multi xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling module xil_defaultlib.Multiplexer Compiling module xil_defaultlib.Sim_multi Compiling module xil_defaultlib.glbl Built simulation snapshot Sim_multi_behav ****** Webtalk v2016.2 (64-bit) **** SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016 **** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. source C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/xsim.dir/Sim_multi_behav/webtalk/xsim_webtalk.tcl -notrace INFO: [Common 17-206] Exiting Webtalk at Sun Dec 23 22:26:41 2018... INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' INFO: [USF-XSim-98] *** Running xsim with args "Sim_multi_behav -key {Behavioral:sim_1:Functional:Sim_multi} -tclbatch {Sim_multi.tcl} -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature Vivado Simulator 2016.2 Time resolution is 1 ps source Sim_multi.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns INFO: [USF-XSim-96] XSim completed. Design snapshot 'Sim_multi_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:02 ; elapsed = 00:00:07 . Memory (MB): peak = 1313.207 ; gain = 0.000 close_sim INFO: [Simtcl 6-16] Simulation closed set_property top top [get_filesets sim_1] set_property top_lib xil_defaultlib [get_filesets sim_1] launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'top' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj top_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SignalExtension.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module SignalExtension INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ShiftUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ShiftUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegisterFile.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegisterFile INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ProgramCounter.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ProgramCounter INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Multiplexer INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module InstructionMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module DataMemory INFO: [VRFC 10-2458] undeclared symbol out, assumed default net type wire [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v:44] INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ControlUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALUControl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALUControl INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALU2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALU2 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Add1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Add1 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module top INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl INFO: [USF-XSim-69] 'compile' step finished in '1' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' Vivado Simulator 2016.2 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: J:/Xilinx/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto 4c388791a4e240948a5554cd0b3617d7 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot top_behav xil_defaultlib.top xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling module xil_defaultlib.ControlUnit Compiling module xil_defaultlib.ProgramCounter Compiling module xil_defaultlib.Add1 Compiling module xil_defaultlib.InstructionMemory Compiling module xil_defaultlib.RegisterFile Compiling module xil_defaultlib.SignalExtension Compiling module xil_defaultlib.ALUControl Compiling module xil_defaultlib.ALU2 Compiling module xil_defaultlib.Multiplexer Compiling module xil_defaultlib.ShiftUnit Compiling module xil_defaultlib.DataMemory Compiling module xil_defaultlib.top Compiling module xil_defaultlib.glbl Built simulation snapshot top_behav ****** Webtalk v2016.2 (64-bit) **** SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016 **** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. source C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/xsim.dir/top_behav/webtalk/xsim_webtalk.tcl -notrace INFO: [Common 17-206] Exiting Webtalk at Sun Dec 23 22:27:10 2018... INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' INFO: [USF-XSim-98] *** Running xsim with args "top_behav -key {Behavioral:sim_1:Functional:top} -tclbatch {top.tcl} -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature Vivado Simulator 2016.2 Time resolution is 1 ps source top.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns INFO: [USF-XSim-96] XSim completed. Design snapshot 'top_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:01 ; elapsed = 00:00:06 . Memory (MB): peak = 1313.207 ; gain = 0.000 close_sim INFO: [Simtcl 6-16] Simulation closed launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'top' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj top_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SignalExtension.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module SignalExtension INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ShiftUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ShiftUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegisterFile.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegisterFile INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ProgramCounter.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ProgramCounter INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Multiplexer INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module InstructionMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module DataMemory INFO: [VRFC 10-2458] undeclared symbol out, assumed default net type wire [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v:44] INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ControlUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALUControl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALUControl INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALU2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALU2 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Add1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Add1 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module top INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl INFO: [USF-XSim-69] 'compile' step finished in '1' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' Vivado Simulator 2016.2 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: J:/Xilinx/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto 4c388791a4e240948a5554cd0b3617d7 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot top_behav xil_defaultlib.top xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling module xil_defaultlib.ControlUnit Compiling module xil_defaultlib.ProgramCounter Compiling module xil_defaultlib.Add1 Compiling module xil_defaultlib.InstructionMemory Compiling module xil_defaultlib.RegisterFile Compiling module xil_defaultlib.SignalExtension Compiling module xil_defaultlib.ALUControl Compiling module xil_defaultlib.ALU2 Compiling module xil_defaultlib.Multiplexer Compiling module xil_defaultlib.ShiftUnit Compiling module xil_defaultlib.DataMemory Compiling module xil_defaultlib.top Compiling module xil_defaultlib.glbl Built simulation snapshot top_behav ****** Webtalk v2016.2 (64-bit) **** SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016 **** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. source C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/xsim.dir/top_behav/webtalk/xsim_webtalk.tcl -notrace INFO: [Common 17-206] Exiting Webtalk at Sun Dec 23 22:46:15 2018... INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' INFO: [USF-XSim-98] *** Running xsim with args "top_behav -key {Behavioral:sim_1:Functional:top} -tclbatch {top.tcl} -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature Vivado Simulator 2016.2 Time resolution is 1 ps source top.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns INFO: [USF-XSim-96] XSim completed. Design snapshot 'top_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:01 ; elapsed = 00:00:06 . Memory (MB): peak = 1313.207 ; gain = 0.000 update_compile_order -fileset sources_1 update_compile_order -fileset sources_1 close_sim INFO: [Simtcl 6-16] Simulation closed launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'top' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj top_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ProgramCounter.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ProgramCounter INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SignalExtension.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module SignalExtension INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ShiftUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ShiftUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegisterFile.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegisterFile INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Multiplexer INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module InstructionMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module DataMemory INFO: [VRFC 10-2458] undeclared symbol out, assumed default net type wire [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v:44] INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ControlUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALUControl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALUControl INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALU2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALU2 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Add1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Add1 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module top INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl INFO: [USF-XSim-69] 'compile' step finished in '1' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' Vivado Simulator 2016.2 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: J:/Xilinx/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto 4c388791a4e240948a5554cd0b3617d7 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot top_behav xil_defaultlib.top xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling module xil_defaultlib.ControlUnit Compiling module xil_defaultlib.ProgramCounter Compiling module xil_defaultlib.Add1 Compiling module xil_defaultlib.InstructionMemory Compiling module xil_defaultlib.RegisterFile Compiling module xil_defaultlib.SignalExtension Compiling module xil_defaultlib.ALUControl Compiling module xil_defaultlib.ALU2 Compiling module xil_defaultlib.Multiplexer Compiling module xil_defaultlib.ShiftUnit Compiling module xil_defaultlib.DataMemory Compiling module xil_defaultlib.top Compiling module xil_defaultlib.glbl Built simulation snapshot top_behav ****** Webtalk v2016.2 (64-bit) **** SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016 **** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. source C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/xsim.dir/top_behav/webtalk/xsim_webtalk.tcl -notrace INFO: [Common 17-206] Exiting Webtalk at Sun Dec 23 22:58:42 2018... INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' INFO: [USF-XSim-98] *** Running xsim with args "top_behav -key {Behavioral:sim_1:Functional:top} -tclbatch {top.tcl} -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature Vivado Simulator 2016.2 Time resolution is 1 ps source top.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns INFO: [USF-XSim-96] XSim completed. Design snapshot 'top_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:03 ; elapsed = 00:00:08 . Memory (MB): peak = 1313.207 ; gain = 0.000 update_compile_order -fileset sources_1 update_compile_order -fileset sources_1 close_sim INFO: [Simtcl 6-16] Simulation closed launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'top' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj top_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ControlUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ProgramCounter.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ProgramCounter INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SignalExtension.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module SignalExtension INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ShiftUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ShiftUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegisterFile.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegisterFile INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Multiplexer INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module InstructionMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module DataMemory INFO: [VRFC 10-2458] undeclared symbol out, assumed default net type wire [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v:44] INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALUControl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALUControl INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALU2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALU2 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Add1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Add1 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module top INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl INFO: [USF-XSim-69] 'compile' step finished in '1' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' Vivado Simulator 2016.2 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: J:/Xilinx/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto 4c388791a4e240948a5554cd0b3617d7 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot top_behav xil_defaultlib.top xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling module xil_defaultlib.ControlUnit Compiling module xil_defaultlib.ProgramCounter Compiling module xil_defaultlib.Add1 Compiling module xil_defaultlib.InstructionMemory Compiling module xil_defaultlib.RegisterFile Compiling module xil_defaultlib.SignalExtension Compiling module xil_defaultlib.ALUControl Compiling module xil_defaultlib.ALU2 Compiling module xil_defaultlib.Multiplexer Compiling module xil_defaultlib.ShiftUnit Compiling module xil_defaultlib.DataMemory Compiling module xil_defaultlib.top Compiling module xil_defaultlib.glbl Built simulation snapshot top_behav ****** Webtalk v2016.2 (64-bit) **** SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016 **** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. source C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/xsim.dir/top_behav/webtalk/xsim_webtalk.tcl -notrace INFO: [Common 17-206] Exiting Webtalk at Sun Dec 23 23:14:56 2018... INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' INFO: [USF-XSim-98] *** Running xsim with args "top_behav -key {Behavioral:sim_1:Functional:top} -tclbatch {top.tcl} -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature Vivado Simulator 2016.2 Time resolution is 1 ps source top.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns INFO: [USF-XSim-96] XSim completed. Design snapshot 'top_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:03 ; elapsed = 00:00:08 . Memory (MB): peak = 1313.207 ; gain = 0.000 close_sim INFO: [Simtcl 6-16] Simulation closed launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'top' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj top_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ControlUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ProgramCounter.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ProgramCounter INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SignalExtension.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module SignalExtension INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ShiftUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ShiftUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegisterFile.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegisterFile INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Multiplexer INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module InstructionMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module DataMemory INFO: [VRFC 10-2458] undeclared symbol out, assumed default net type wire [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v:44] INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALUControl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALUControl INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALU2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALU2 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Add1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Add1 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module top INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl INFO: [USF-XSim-69] 'compile' step finished in '1' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' Vivado Simulator 2016.2 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: J:/Xilinx/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto 4c388791a4e240948a5554cd0b3617d7 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot top_behav xil_defaultlib.top xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration ERROR: [VRFC 10-529] concurrent assignment to a non-net pcin is not permitted [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:90] ERROR: [XSIM 43-3322] Static elaboration of top level Verilog design unit(s) in library work failed. INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds INFO: [USF-XSim-99] Step results log file:'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/elaborate.log' ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/elaborate.log' file for more information. ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation. ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors. launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'top' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj top_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ControlUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ProgramCounter.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ProgramCounter INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SignalExtension.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module SignalExtension INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ShiftUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ShiftUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegisterFile.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegisterFile INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Multiplexer INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module InstructionMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module DataMemory INFO: [VRFC 10-2458] undeclared symbol out, assumed default net type wire [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v:44] INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALUControl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALUControl INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALU2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALU2 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Add1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Add1 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module top INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl INFO: [USF-XSim-69] 'compile' step finished in '1' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' Vivado Simulator 2016.2 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: J:/Xilinx/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto 4c388791a4e240948a5554cd0b3617d7 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot top_behav xil_defaultlib.top xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration ERROR: [VRFC 10-529] concurrent assignment to a non-net pcin is not permitted [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:90] ERROR: [VRFC 10-1146] non-net variable cannot be connected to inout port c [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:90] ERROR: [XSIM 43-3322] Static elaboration of top level Verilog design unit(s) in library work failed. INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds INFO: [USF-XSim-99] Step results log file:'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/elaborate.log' ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/elaborate.log' file for more information. ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation. ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors. launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'top' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj top_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ControlUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ProgramCounter.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ProgramCounter INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SignalExtension.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module SignalExtension INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ShiftUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ShiftUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegisterFile.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegisterFile INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Multiplexer INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module InstructionMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module DataMemory INFO: [VRFC 10-2458] undeclared symbol out, assumed default net type wire [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v:44] INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALUControl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALUControl INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALU2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALU2 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Add1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Add1 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module top INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl INFO: [USF-XSim-69] 'compile' step finished in '1' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' Vivado Simulator 2016.2 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: J:/Xilinx/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto 4c388791a4e240948a5554cd0b3617d7 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot top_behav xil_defaultlib.top xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration ERROR: [VRFC 10-529] concurrent assignment to a non-net pcin is not permitted [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:90] ERROR: [XSIM 43-3322] Static elaboration of top level Verilog design unit(s) in library work failed. INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds INFO: [USF-XSim-99] Step results log file:'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/elaborate.log' ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/elaborate.log' file for more information. ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation. ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors. launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'top' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj top_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ControlUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ProgramCounter.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ProgramCounter INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SignalExtension.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module SignalExtension INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ShiftUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ShiftUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegisterFile.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegisterFile INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Multiplexer INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module InstructionMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module DataMemory INFO: [VRFC 10-2458] undeclared symbol out, assumed default net type wire [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v:44] INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALUControl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALUControl INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALU2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALU2 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Add1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Add1 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module top INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl INFO: [USF-XSim-69] 'compile' step finished in '1' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' Vivado Simulator 2016.2 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: J:/Xilinx/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto 4c388791a4e240948a5554cd0b3617d7 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot top_behav xil_defaultlib.top xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling module xil_defaultlib.ControlUnit Compiling module xil_defaultlib.ProgramCounter Compiling module xil_defaultlib.Add1 Compiling module xil_defaultlib.InstructionMemory Compiling module xil_defaultlib.RegisterFile Compiling module xil_defaultlib.SignalExtension Compiling module xil_defaultlib.ALUControl Compiling module xil_defaultlib.ALU2 Compiling module xil_defaultlib.Multiplexer Compiling module xil_defaultlib.ShiftUnit Compiling module xil_defaultlib.DataMemory Compiling module xil_defaultlib.top Compiling module xil_defaultlib.glbl Built simulation snapshot top_behav ****** Webtalk v2016.2 (64-bit) **** SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016 **** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. source C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/xsim.dir/top_behav/webtalk/xsim_webtalk.tcl -notrace INFO: [Common 17-206] Exiting Webtalk at Sun Dec 23 23:19:58 2018... INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' INFO: [USF-XSim-98] *** Running xsim with args "top_behav -key {Behavioral:sim_1:Functional:top} -tclbatch {top.tcl} -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature Vivado Simulator 2016.2 Time resolution is 1 ps source top.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns INFO: [USF-XSim-96] XSim completed. Design snapshot 'top_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:01 ; elapsed = 00:00:06 . Memory (MB): peak = 1313.207 ; gain = 0.000 close_sim INFO: [Simtcl 6-16] Simulation closed close [ open C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Sim_cpu.v w ] add_files C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Sim_cpu.v update_compile_order -fileset sources_1 update_compile_order -fileset sources_1 update_compile_order -fileset sources_1 launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'top' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' INFO: [Common 17-41] Interrupt caught. Command should exit soon. "xvlog -m64 --relax -prj top_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ControlUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ProgramCounter.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ProgramCounter INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SignalExtension.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module SignalExtension INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ShiftUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ShiftUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegisterFile.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegisterFile INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Multiplexer INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module InstructionMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module DataMemory INFO: [VRFC 10-2458] undeclared symbol out, assumed default net type wire [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v:44] INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALUControl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALUControl INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALU2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALU2 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Add1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Add1 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module top INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl INFO: [Common 17-344] 'run_program' was cancelled INFO: [Vivado 12-4703] 'compile' step aborted INFO: [Common 17-344] 'launch_simulation' was cancelled set_property top Sim_cpu [get_filesets sim_1] set_property top_lib xil_defaultlib [get_filesets sim_1] launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'Sim_cpu' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj Sim_cpu_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ControlUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ProgramCounter.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ProgramCounter INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SignalExtension.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module SignalExtension INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ShiftUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ShiftUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegisterFile.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegisterFile INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Multiplexer INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module InstructionMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module DataMemory INFO: [VRFC 10-2458] undeclared symbol out, assumed default net type wire [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v:44] INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALUControl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALUControl INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALU2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALU2 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Add1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Add1 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module top INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Sim_cpu.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Sim_cpu INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl INFO: [USF-XSim-69] 'compile' step finished in '2' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' Vivado Simulator 2016.2 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: J:/Xilinx/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto 4c388791a4e240948a5554cd0b3617d7 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot Sim_cpu_behav xil_defaultlib.Sim_cpu xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration ERROR: [VRFC 10-93] Out1 is not declared under prefix opCode [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Sim_cpu.v:30] ERROR: [XSIM 43-3322] Static elaboration of top level Verilog design unit(s) in library work failed. INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds INFO: [USF-XSim-99] Step results log file:'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/elaborate.log' ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/elaborate.log' file for more information. ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation. ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors. launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'Sim_cpu' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj Sim_cpu_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ControlUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ProgramCounter.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ProgramCounter INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SignalExtension.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module SignalExtension INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ShiftUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ShiftUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegisterFile.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegisterFile INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Multiplexer INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module InstructionMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module DataMemory INFO: [VRFC 10-2458] undeclared symbol out, assumed default net type wire [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v:44] INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALUControl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALUControl INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALU2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALU2 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Add1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Add1 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module top INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Sim_cpu.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Sim_cpu INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl INFO: [USF-XSim-69] 'compile' step finished in '2' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' Vivado Simulator 2016.2 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: J:/Xilinx/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto 4c388791a4e240948a5554cd0b3617d7 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot Sim_cpu_behav xil_defaultlib.Sim_cpu xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling module xil_defaultlib.ControlUnit Compiling module xil_defaultlib.ProgramCounter Compiling module xil_defaultlib.Add1 Compiling module xil_defaultlib.InstructionMemory Compiling module xil_defaultlib.RegisterFile Compiling module xil_defaultlib.SignalExtension Compiling module xil_defaultlib.ALUControl Compiling module xil_defaultlib.ALU2 Compiling module xil_defaultlib.Multiplexer Compiling module xil_defaultlib.ShiftUnit Compiling module xil_defaultlib.DataMemory Compiling module xil_defaultlib.top Compiling module xil_defaultlib.Sim_cpu Compiling module xil_defaultlib.glbl Built simulation snapshot Sim_cpu_behav ****** Webtalk v2016.2 (64-bit) **** SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016 **** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. source C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/xsim.dir/Sim_cpu_behav/webtalk/xsim_webtalk.tcl -notrace INFO: [Common 17-206] Exiting Webtalk at Sun Dec 23 23:26:40 2018... INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' INFO: [USF-XSim-98] *** Running xsim with args "Sim_cpu_behav -key {Behavioral:sim_1:Functional:Sim_cpu} -tclbatch {Sim_cpu.tcl} -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature Vivado Simulator 2016.2 Time resolution is 1 ps source Sim_cpu.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns INFO: [USF-XSim-96] XSim completed. Design snapshot 'Sim_cpu_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:01 ; elapsed = 00:00:07 . Memory (MB): peak = 1313.207 ; gain = 0.000 close_sim INFO: [Simtcl 6-16] Simulation closed launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'Sim_cpu' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj Sim_cpu_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ControlUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ProgramCounter.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ProgramCounter INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SignalExtension.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module SignalExtension INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ShiftUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ShiftUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegisterFile.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegisterFile INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Multiplexer INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module InstructionMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module DataMemory INFO: [VRFC 10-2458] undeclared symbol out, assumed default net type wire [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v:44] INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALUControl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALUControl INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALU2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALU2 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Add1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Add1 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module top INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Sim_cpu.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Sim_cpu INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl INFO: [USF-XSim-69] 'compile' step finished in '1' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' Vivado Simulator 2016.2 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: J:/Xilinx/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto 4c388791a4e240948a5554cd0b3617d7 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot Sim_cpu_behav xil_defaultlib.Sim_cpu xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling module xil_defaultlib.ControlUnit Compiling module xil_defaultlib.ProgramCounter Compiling module xil_defaultlib.Add1 Compiling module xil_defaultlib.InstructionMemory Compiling module xil_defaultlib.RegisterFile Compiling module xil_defaultlib.SignalExtension Compiling module xil_defaultlib.ALUControl Compiling module xil_defaultlib.ALU2 Compiling module xil_defaultlib.Multiplexer Compiling module xil_defaultlib.ShiftUnit Compiling module xil_defaultlib.DataMemory Compiling module xil_defaultlib.top Compiling module xil_defaultlib.Sim_cpu Compiling module xil_defaultlib.glbl Built simulation snapshot Sim_cpu_behav ****** Webtalk v2016.2 (64-bit) **** SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016 **** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. source C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/xsim.dir/Sim_cpu_behav/webtalk/xsim_webtalk.tcl -notrace INFO: [Common 17-206] Exiting Webtalk at Sun Dec 23 23:52:52 2018... INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' INFO: [USF-XSim-98] *** Running xsim with args "Sim_cpu_behav -key {Behavioral:sim_1:Functional:Sim_cpu} -tclbatch {Sim_cpu.tcl} -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature Vivado Simulator 2016.2 Time resolution is 1 ps source Sim_cpu.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns INFO: [USF-XSim-96] XSim completed. Design snapshot 'Sim_cpu_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:02 ; elapsed = 00:00:08 . Memory (MB): peak = 1313.207 ; gain = 0.000 close_sim INFO: [Simtcl 6-16] Simulation closed remove_files C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Sim_cpu.v update_compile_order -fileset sources_1 update_compile_order -fileset sim_1 update_compile_order -fileset sources_1 launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'top' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj top_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ControlUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ProgramCounter.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ProgramCounter INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SignalExtension.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module SignalExtension INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ShiftUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ShiftUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegisterFile.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegisterFile INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Multiplexer INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module InstructionMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module DataMemory INFO: [VRFC 10-2458] undeclared symbol out, assumed default net type wire [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v:44] INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALUControl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALUControl INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALU2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALU2 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Add1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Add1 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module top INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl INFO: [USF-XSim-69] 'compile' step finished in '1' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' Vivado Simulator 2016.2 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: J:/Xilinx/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto 4c388791a4e240948a5554cd0b3617d7 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot top_behav xil_defaultlib.top xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling module xil_defaultlib.ControlUnit Compiling module xil_defaultlib.ProgramCounter Compiling module xil_defaultlib.Add1 Compiling module xil_defaultlib.InstructionMemory Compiling module xil_defaultlib.RegisterFile Compiling module xil_defaultlib.SignalExtension Compiling module xil_defaultlib.ALUControl Compiling module xil_defaultlib.ALU2 Compiling module xil_defaultlib.Multiplexer Compiling module xil_defaultlib.ShiftUnit Compiling module xil_defaultlib.DataMemory Compiling module xil_defaultlib.top Compiling module xil_defaultlib.glbl Built simulation snapshot top_behav ****** Webtalk v2016.2 (64-bit) **** SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016 **** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. source C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/xsim.dir/top_behav/webtalk/xsim_webtalk.tcl -notrace INFO: [Common 17-206] Exiting Webtalk at Sun Dec 23 23:55:16 2018... INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' INFO: [USF-XSim-98] *** Running xsim with args "top_behav -key {Behavioral:sim_1:Functional:top} -tclbatch {top.tcl} -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature Vivado Simulator 2016.2 Time resolution is 1 ps source top.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns INFO: [USF-XSim-96] XSim completed. Design snapshot 'top_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:01 ; elapsed = 00:00:06 . Memory (MB): peak = 1313.207 ; gain = 0.000 close_sim INFO: [Simtcl 6-16] Simulation closed launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'top' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj top_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ControlUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ProgramCounter.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ProgramCounter INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SignalExtension.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module SignalExtension INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ShiftUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ShiftUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegisterFile.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegisterFile INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Multiplexer INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module InstructionMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module DataMemory INFO: [VRFC 10-2458] undeclared symbol out, assumed default net type wire [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v:44] INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALUControl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALUControl INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALU2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALU2 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Add1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Add1 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module top INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl INFO: [USF-XSim-69] 'compile' step finished in '1' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' Vivado Simulator 2016.2 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: J:/Xilinx/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto 4c388791a4e240948a5554cd0b3617d7 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot top_behav xil_defaultlib.top xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling module xil_defaultlib.ControlUnit Compiling module xil_defaultlib.ProgramCounter Compiling module xil_defaultlib.Add1 Compiling module xil_defaultlib.InstructionMemory Compiling module xil_defaultlib.RegisterFile Compiling module xil_defaultlib.SignalExtension Compiling module xil_defaultlib.ALUControl Compiling module xil_defaultlib.ALU2 Compiling module xil_defaultlib.Multiplexer Compiling module xil_defaultlib.ShiftUnit Compiling module xil_defaultlib.DataMemory Compiling module xil_defaultlib.top Compiling module xil_defaultlib.glbl Built simulation snapshot top_behav ****** Webtalk v2016.2 (64-bit) **** SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016 **** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. source C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/xsim.dir/top_behav/webtalk/xsim_webtalk.tcl -notrace INFO: [Common 17-206] Exiting Webtalk at Sun Dec 23 23:56:06 2018... INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' INFO: [USF-XSim-98] *** Running xsim with args "top_behav -key {Behavioral:sim_1:Functional:top} -tclbatch {top.tcl} -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature Vivado Simulator 2016.2 Time resolution is 1 ps source top.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns INFO: [USF-XSim-96] XSim completed. Design snapshot 'top_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:03 ; elapsed = 00:00:08 . Memory (MB): peak = 1313.207 ; gain = 0.000 close_sim INFO: [Simtcl 6-16] Simulation closed launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'top' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj top_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ControlUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ProgramCounter.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ProgramCounter INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SignalExtension.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module SignalExtension INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ShiftUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ShiftUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegisterFile.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegisterFile INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Multiplexer INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module InstructionMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module DataMemory INFO: [VRFC 10-2458] undeclared symbol out, assumed default net type wire [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v:44] INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALUControl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALUControl INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALU2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALU2 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Add1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Add1 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module top INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl INFO: [USF-XSim-69] 'compile' step finished in '1' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' Vivado Simulator 2016.2 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: J:/Xilinx/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto 4c388791a4e240948a5554cd0b3617d7 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot top_behav xil_defaultlib.top xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling module xil_defaultlib.ControlUnit Compiling module xil_defaultlib.ProgramCounter Compiling module xil_defaultlib.Add1 Compiling module xil_defaultlib.InstructionMemory Compiling module xil_defaultlib.RegisterFile Compiling module xil_defaultlib.SignalExtension Compiling module xil_defaultlib.ALUControl Compiling module xil_defaultlib.ALU2 Compiling module xil_defaultlib.Multiplexer Compiling module xil_defaultlib.ShiftUnit Compiling module xil_defaultlib.DataMemory Compiling module xil_defaultlib.top Compiling module xil_defaultlib.glbl Built simulation snapshot top_behav ****** Webtalk v2016.2 (64-bit) **** SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016 **** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. source C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/xsim.dir/top_behav/webtalk/xsim_webtalk.tcl -notrace INFO: [Common 17-206] Exiting Webtalk at Sun Dec 23 23:57:33 2018... INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' INFO: [USF-XSim-98] *** Running xsim with args "top_behav -key {Behavioral:sim_1:Functional:top} -tclbatch {top.tcl} -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature Vivado Simulator 2016.2 Time resolution is 1 ps source top.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns INFO: [USF-XSim-96] XSim completed. Design snapshot 'top_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:02 ; elapsed = 00:00:08 . Memory (MB): peak = 1313.207 ; gain = 0.000 close_sim INFO: [Simtcl 6-16] Simulation closed close_sim: Time (s): cpu = 00:00:02 ; elapsed = 00:00:05 . Memory (MB): peak = 1313.207 ; gain = 0.000 launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'top' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj top_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ControlUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ProgramCounter.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ProgramCounter INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SignalExtension.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module SignalExtension INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ShiftUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ShiftUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegisterFile.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegisterFile INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Multiplexer INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module InstructionMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module DataMemory INFO: [VRFC 10-2458] undeclared symbol out, assumed default net type wire [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v:44] INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALUControl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALUControl INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALU2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALU2 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Add1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Add1 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module top INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl INFO: [USF-XSim-69] 'compile' step finished in '1' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' Vivado Simulator 2016.2 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: J:/Xilinx/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto 4c388791a4e240948a5554cd0b3617d7 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot top_behav xil_defaultlib.top xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling module xil_defaultlib.ControlUnit Compiling module xil_defaultlib.ProgramCounter Compiling module xil_defaultlib.Add1 Compiling module xil_defaultlib.InstructionMemory Compiling module xil_defaultlib.RegisterFile Compiling module xil_defaultlib.SignalExtension Compiling module xil_defaultlib.ALUControl Compiling module xil_defaultlib.ALU2 Compiling module xil_defaultlib.Multiplexer Compiling module xil_defaultlib.ShiftUnit Compiling module xil_defaultlib.DataMemory Compiling module xil_defaultlib.top Compiling module xil_defaultlib.glbl Built simulation snapshot top_behav ****** Webtalk v2016.2 (64-bit) **** SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016 **** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. source C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/xsim.dir/top_behav/webtalk/xsim_webtalk.tcl -notrace INFO: [Common 17-206] Exiting Webtalk at Mon Dec 24 00:04:33 2018... INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' INFO: [USF-XSim-98] *** Running xsim with args "top_behav -key {Behavioral:sim_1:Functional:top} -tclbatch {top.tcl} -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature Vivado Simulator 2016.2 Time resolution is 1 ps source top.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns INFO: [USF-XSim-96] XSim completed. Design snapshot 'top_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:01 ; elapsed = 00:00:06 . Memory (MB): peak = 1313.207 ; gain = 0.000 close_sim INFO: [Simtcl 6-16] Simulation closed launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'top' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj top_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ControlUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ProgramCounter.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ProgramCounter INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SignalExtension.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module SignalExtension INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ShiftUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ShiftUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegisterFile.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegisterFile INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Multiplexer INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module InstructionMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module DataMemory INFO: [VRFC 10-2458] undeclared symbol out, assumed default net type wire [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v:44] INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALUControl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALUControl INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALU2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALU2 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Add1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Add1 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module top INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl INFO: [USF-XSim-69] 'compile' step finished in '1' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' Vivado Simulator 2016.2 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: J:/Xilinx/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto 4c388791a4e240948a5554cd0b3617d7 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot top_behav xil_defaultlib.top xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling module xil_defaultlib.ControlUnit Compiling module xil_defaultlib.ProgramCounter Compiling module xil_defaultlib.Add1 Compiling module xil_defaultlib.InstructionMemory Compiling module xil_defaultlib.RegisterFile Compiling module xil_defaultlib.SignalExtension Compiling module xil_defaultlib.ALUControl Compiling module xil_defaultlib.ALU2 Compiling module xil_defaultlib.Multiplexer Compiling module xil_defaultlib.ShiftUnit Compiling module xil_defaultlib.DataMemory Compiling module xil_defaultlib.top Compiling module xil_defaultlib.glbl Built simulation snapshot top_behav ****** Webtalk v2016.2 (64-bit) **** SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016 **** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. source C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/xsim.dir/top_behav/webtalk/xsim_webtalk.tcl -notrace INFO: [Common 17-206] Exiting Webtalk at Mon Dec 24 00:12:55 2018... INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' INFO: [USF-XSim-98] *** Running xsim with args "top_behav -key {Behavioral:sim_1:Functional:top} -tclbatch {top.tcl} -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature Vivado Simulator 2016.2 Time resolution is 1 ps source top.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns INFO: [USF-XSim-96] XSim completed. Design snapshot 'top_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:02 ; elapsed = 00:00:07 . Memory (MB): peak = 1313.207 ; gain = 0.000 close_sim INFO: [Simtcl 6-16] Simulation closed launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'top' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj top_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ControlUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ProgramCounter.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ProgramCounter INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SignalExtension.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module SignalExtension INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ShiftUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ShiftUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegisterFile.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegisterFile INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Multiplexer INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module InstructionMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module DataMemory INFO: [VRFC 10-2458] undeclared symbol out, assumed default net type wire [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v:44] INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALUControl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALUControl INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALU2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALU2 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Add1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Add1 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module top INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl INFO: [USF-XSim-69] 'compile' step finished in '1' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' Vivado Simulator 2016.2 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: J:/Xilinx/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto 4c388791a4e240948a5554cd0b3617d7 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot top_behav xil_defaultlib.top xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling module xil_defaultlib.ControlUnit Compiling module xil_defaultlib.ProgramCounter Compiling module xil_defaultlib.Add1 Compiling module xil_defaultlib.InstructionMemory Compiling module xil_defaultlib.RegisterFile Compiling module xil_defaultlib.SignalExtension Compiling module xil_defaultlib.ALUControl Compiling module xil_defaultlib.ALU2 Compiling module xil_defaultlib.Multiplexer Compiling module xil_defaultlib.ShiftUnit Compiling module xil_defaultlib.DataMemory Compiling module xil_defaultlib.top Compiling module xil_defaultlib.glbl Built simulation snapshot top_behav ****** Webtalk v2016.2 (64-bit) **** SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016 **** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. source C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/xsim.dir/top_behav/webtalk/xsim_webtalk.tcl -notrace INFO: [Common 17-206] Exiting Webtalk at Mon Dec 24 00:14:08 2018... INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' INFO: [USF-XSim-98] *** Running xsim with args "top_behav -key {Behavioral:sim_1:Functional:top} -tclbatch {top.tcl} -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature Vivado Simulator 2016.2 Time resolution is 1 ps source top.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns INFO: [USF-XSim-96] XSim completed. Design snapshot 'top_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:01 ; elapsed = 00:00:07 . Memory (MB): peak = 1313.207 ; gain = 0.000 close_sim INFO: [Simtcl 6-16] Simulation closed launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'top' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj top_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ControlUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ProgramCounter.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ProgramCounter INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SignalExtension.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module SignalExtension INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ShiftUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ShiftUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegisterFile.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegisterFile INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Multiplexer INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module InstructionMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module DataMemory INFO: [VRFC 10-2458] undeclared symbol out, assumed default net type wire [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v:44] INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALUControl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALUControl INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALU2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALU2 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Add1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Add1 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module top INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl INFO: [USF-XSim-69] 'compile' step finished in '1' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' Vivado Simulator 2016.2 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: J:/Xilinx/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto 4c388791a4e240948a5554cd0b3617d7 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot top_behav xil_defaultlib.top xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling module xil_defaultlib.ControlUnit Compiling module xil_defaultlib.ProgramCounter Compiling module xil_defaultlib.Add1 Compiling module xil_defaultlib.InstructionMemory Compiling module xil_defaultlib.RegisterFile Compiling module xil_defaultlib.SignalExtension Compiling module xil_defaultlib.ALUControl Compiling module xil_defaultlib.ALU2 Compiling module xil_defaultlib.Multiplexer Compiling module xil_defaultlib.ShiftUnit Compiling module xil_defaultlib.DataMemory Compiling module xil_defaultlib.top Compiling module xil_defaultlib.glbl Built simulation snapshot top_behav ****** Webtalk v2016.2 (64-bit) **** SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016 **** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. source C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/xsim.dir/top_behav/webtalk/xsim_webtalk.tcl -notrace INFO: [Common 17-206] Exiting Webtalk at Mon Dec 24 00:15:05 2018... INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' INFO: [USF-XSim-98] *** Running xsim with args "top_behav -key {Behavioral:sim_1:Functional:top} -tclbatch {top.tcl} -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature Vivado Simulator 2016.2 Time resolution is 1 ps source top.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns INFO: [USF-XSim-96] XSim completed. Design snapshot 'top_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:02 ; elapsed = 00:00:07 . Memory (MB): peak = 1313.207 ; gain = 0.000 close_sim INFO: [Simtcl 6-16] Simulation closed launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'top' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj top_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ControlUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ProgramCounter.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ProgramCounter INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SignalExtension.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module SignalExtension INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ShiftUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ShiftUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegisterFile.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegisterFile INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Multiplexer INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module InstructionMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module DataMemory INFO: [VRFC 10-2458] undeclared symbol out, assumed default net type wire [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v:44] INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALUControl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALUControl INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALU2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALU2 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Add1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Add1 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module top INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl INFO: [USF-XSim-69] 'compile' step finished in '1' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' Vivado Simulator 2016.2 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: J:/Xilinx/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto 4c388791a4e240948a5554cd0b3617d7 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot top_behav xil_defaultlib.top xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling module xil_defaultlib.ControlUnit Compiling module xil_defaultlib.ProgramCounter Compiling module xil_defaultlib.Add1 Compiling module xil_defaultlib.InstructionMemory Compiling module xil_defaultlib.RegisterFile Compiling module xil_defaultlib.SignalExtension Compiling module xil_defaultlib.ALUControl Compiling module xil_defaultlib.ALU2 Compiling module xil_defaultlib.Multiplexer Compiling module xil_defaultlib.ShiftUnit Compiling module xil_defaultlib.DataMemory Compiling module xil_defaultlib.top Compiling module xil_defaultlib.glbl Built simulation snapshot top_behav ****** Webtalk v2016.2 (64-bit) **** SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016 **** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. source C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/xsim.dir/top_behav/webtalk/xsim_webtalk.tcl -notrace INFO: [Common 17-206] Exiting Webtalk at Mon Dec 24 00:19:30 2018... INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' INFO: [USF-XSim-98] *** Running xsim with args "top_behav -key {Behavioral:sim_1:Functional:top} -tclbatch {top.tcl} -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature Vivado Simulator 2016.2 Time resolution is 1 ps source top.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns INFO: [USF-XSim-96] XSim completed. Design snapshot 'top_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:02 ; elapsed = 00:00:07 . Memory (MB): peak = 1313.207 ; gain = 0.000 close_sim INFO: [Simtcl 6-16] Simulation closed launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'top' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj top_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ControlUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ProgramCounter.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ProgramCounter INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SignalExtension.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module SignalExtension INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ShiftUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ShiftUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegisterFile.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegisterFile INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Multiplexer INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module InstructionMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module DataMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALUControl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALUControl INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALU2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALU2 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Add1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Add1 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module top INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl INFO: [USF-XSim-69] 'compile' step finished in '2' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' Vivado Simulator 2016.2 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: J:/Xilinx/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto 4c388791a4e240948a5554cd0b3617d7 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot top_behav xil_defaultlib.top xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling module xil_defaultlib.ControlUnit Compiling module xil_defaultlib.ProgramCounter Compiling module xil_defaultlib.Add1 Compiling module xil_defaultlib.InstructionMemory Compiling module xil_defaultlib.RegisterFile Compiling module xil_defaultlib.SignalExtension Compiling module xil_defaultlib.ALUControl Compiling module xil_defaultlib.ALU2 Compiling module xil_defaultlib.Multiplexer Compiling module xil_defaultlib.ShiftUnit Compiling module xil_defaultlib.DataMemory Compiling module xil_defaultlib.top Compiling module xil_defaultlib.glbl Built simulation snapshot top_behav ****** Webtalk v2016.2 (64-bit) **** SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016 **** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. source C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/xsim.dir/top_behav/webtalk/xsim_webtalk.tcl -notrace INFO: [Common 17-206] Exiting Webtalk at Mon Dec 24 02:40:19 2018... INFO: [USF-XSim-69] 'elaborate' step finished in '4' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' INFO: [USF-XSim-98] *** Running xsim with args "top_behav -key {Behavioral:sim_1:Functional:top} -tclbatch {top.tcl} -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature Vivado Simulator 2016.2 Time resolution is 1 ps source top.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns INFO: [USF-XSim-96] XSim completed. Design snapshot 'top_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:02 ; elapsed = 00:00:09 . Memory (MB): peak = 1313.207 ; gain = 0.000 close_sim INFO: [Simtcl 6-16] Simulation closed launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'top' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj top_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ControlUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ProgramCounter.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ProgramCounter INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SignalExtension.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module SignalExtension INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ShiftUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ShiftUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegisterFile.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegisterFile INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Multiplexer INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module InstructionMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module DataMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALUControl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALUControl INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALU2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALU2 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Add1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Add1 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module top INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl INFO: [USF-XSim-69] 'compile' step finished in '1' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' Vivado Simulator 2016.2 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: J:/Xilinx/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto 4c388791a4e240948a5554cd0b3617d7 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot top_behav xil_defaultlib.top xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling module xil_defaultlib.ControlUnit Compiling module xil_defaultlib.ProgramCounter Compiling module xil_defaultlib.Add1 Compiling module xil_defaultlib.InstructionMemory Compiling module xil_defaultlib.RegisterFile Compiling module xil_defaultlib.SignalExtension Compiling module xil_defaultlib.ALUControl Compiling module xil_defaultlib.ALU2 Compiling module xil_defaultlib.Multiplexer Compiling module xil_defaultlib.ShiftUnit Compiling module xil_defaultlib.DataMemory Compiling module xil_defaultlib.top Compiling module xil_defaultlib.glbl Built simulation snapshot top_behav ****** Webtalk v2016.2 (64-bit) **** SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016 **** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. source C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/xsim.dir/top_behav/webtalk/xsim_webtalk.tcl -notrace INFO: [Common 17-206] Exiting Webtalk at Mon Dec 24 02:55:20 2018... INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' INFO: [USF-XSim-98] *** Running xsim with args "top_behav -key {Behavioral:sim_1:Functional:top} -tclbatch {top.tcl} -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature Vivado Simulator 2016.2 Time resolution is 1 ps source top.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns INFO: [USF-XSim-96] XSim completed. Design snapshot 'top_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:01 ; elapsed = 00:00:06 . Memory (MB): peak = 1313.207 ; gain = 0.000 close_sim INFO: [Simtcl 6-16] Simulation closed launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'top' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj top_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ControlUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ProgramCounter.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ProgramCounter INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SignalExtension.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module SignalExtension INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ShiftUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ShiftUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegisterFile.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegisterFile INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Multiplexer INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module InstructionMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module DataMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALUControl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALUControl INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALU2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALU2 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Add1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Add1 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module top INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl INFO: [USF-XSim-69] 'compile' step finished in '1' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' Vivado Simulator 2016.2 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: J:/Xilinx/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto 4c388791a4e240948a5554cd0b3617d7 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot top_behav xil_defaultlib.top xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling module xil_defaultlib.ControlUnit Compiling module xil_defaultlib.ProgramCounter Compiling module xil_defaultlib.Add1 Compiling module xil_defaultlib.InstructionMemory Compiling module xil_defaultlib.RegisterFile Compiling module xil_defaultlib.SignalExtension Compiling module xil_defaultlib.ALUControl Compiling module xil_defaultlib.ALU2 Compiling module xil_defaultlib.Multiplexer Compiling module xil_defaultlib.ShiftUnit Compiling module xil_defaultlib.DataMemory Compiling module xil_defaultlib.top Compiling module xil_defaultlib.glbl Built simulation snapshot top_behav ****** Webtalk v2016.2 (64-bit) **** SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016 **** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. source C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/xsim.dir/top_behav/webtalk/xsim_webtalk.tcl -notrace INFO: [Common 17-206] Exiting Webtalk at Mon Dec 24 03:00:58 2018... INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' INFO: [USF-XSim-98] *** Running xsim with args "top_behav -key {Behavioral:sim_1:Functional:top} -tclbatch {top.tcl} -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature Vivado Simulator 2016.2 Time resolution is 1 ps source top.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns INFO: [USF-XSim-96] XSim completed. Design snapshot 'top_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:02 ; elapsed = 00:00:07 . Memory (MB): peak = 1313.207 ; gain = 0.000 close_sim INFO: [Simtcl 6-16] Simulation closed launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'top' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj top_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ControlUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ProgramCounter.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ProgramCounter INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SignalExtension.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module SignalExtension INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ShiftUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ShiftUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegisterFile.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegisterFile INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Multiplexer INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module InstructionMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module DataMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALUControl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALUControl INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALU2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALU2 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Add1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Add1 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module top INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl INFO: [USF-XSim-69] 'compile' step finished in '1' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' Vivado Simulator 2016.2 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: J:/Xilinx/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto 4c388791a4e240948a5554cd0b3617d7 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot top_behav xil_defaultlib.top xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling module xil_defaultlib.ControlUnit Compiling module xil_defaultlib.ProgramCounter Compiling module xil_defaultlib.Add1 Compiling module xil_defaultlib.InstructionMemory Compiling module xil_defaultlib.RegisterFile Compiling module xil_defaultlib.SignalExtension Compiling module xil_defaultlib.ALUControl Compiling module xil_defaultlib.ALU2 Compiling module xil_defaultlib.Multiplexer Compiling module xil_defaultlib.ShiftUnit Compiling module xil_defaultlib.DataMemory Compiling module xil_defaultlib.top Compiling module xil_defaultlib.glbl Built simulation snapshot top_behav ****** Webtalk v2016.2 (64-bit) **** SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016 **** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. source C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/xsim.dir/top_behav/webtalk/xsim_webtalk.tcl -notrace INFO: [Common 17-206] Exiting Webtalk at Mon Dec 24 03:35:58 2018... INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' INFO: [USF-XSim-98] *** Running xsim with args "top_behav -key {Behavioral:sim_1:Functional:top} -tclbatch {top.tcl} -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature Vivado Simulator 2016.2 Time resolution is 1 ps source top.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns INFO: [USF-XSim-96] XSim completed. Design snapshot 'top_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:01 ; elapsed = 00:00:06 . Memory (MB): peak = 1313.207 ; gain = 0.000 close_sim INFO: [Simtcl 6-16] Simulation closed launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'top' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj top_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ControlUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ProgramCounter.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ProgramCounter INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SignalExtension.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module SignalExtension INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ShiftUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ShiftUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegisterFile.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegisterFile INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Multiplexer INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module InstructionMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module DataMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALUControl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALUControl INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALU2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALU2 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Add1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Add1 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module top INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl INFO: [USF-XSim-69] 'compile' step finished in '1' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' Vivado Simulator 2016.2 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: J:/Xilinx/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto 4c388791a4e240948a5554cd0b3617d7 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot top_behav xil_defaultlib.top xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling module xil_defaultlib.ControlUnit Compiling module xil_defaultlib.ProgramCounter Compiling module xil_defaultlib.Add1 Compiling module xil_defaultlib.InstructionMemory Compiling module xil_defaultlib.RegisterFile Compiling module xil_defaultlib.SignalExtension Compiling module xil_defaultlib.ALUControl Compiling module xil_defaultlib.ALU2 Compiling module xil_defaultlib.Multiplexer Compiling module xil_defaultlib.ShiftUnit Compiling module xil_defaultlib.DataMemory Compiling module xil_defaultlib.top Compiling module xil_defaultlib.glbl Built simulation snapshot top_behav ****** Webtalk v2016.2 (64-bit) **** SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016 **** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. source C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/xsim.dir/top_behav/webtalk/xsim_webtalk.tcl -notrace INFO: [Common 17-206] Exiting Webtalk at Mon Dec 24 03:37:04 2018... INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' INFO: [USF-XSim-98] *** Running xsim with args "top_behav -key {Behavioral:sim_1:Functional:top} -tclbatch {top.tcl} -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature Vivado Simulator 2016.2 Time resolution is 1 ps source top.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns INFO: [USF-XSim-96] XSim completed. Design snapshot 'top_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:01 ; elapsed = 00:00:06 . Memory (MB): peak = 1313.207 ; gain = 0.000 close_sim INFO: [Simtcl 6-16] Simulation closed close [ open C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegFI.v w ] add_files C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegFI.v update_compile_order -fileset sources_1 remove_files C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Sim_multi.v close [ open C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegID.v w ] add_files C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegID.v update_compile_order -fileset sources_1 close [ open C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegEX.v w ] add_files C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegEX.v update_compile_order -fileset sources_1 close [ open C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegMA.v w ] add_files C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegMA.v update_compile_order -fileset sources_1 close [ open C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegWB.v w ] add_files C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegWB.v update_compile_order -fileset sources_1 update_compile_order -fileset sources_1 update_compile_order -fileset sources_1 update_compile_order -fileset sources_1 update_compile_order -fileset sources_1 update_compile_order -fileset sources_1 close [ open C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer4.v w ] add_files C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer4.v update_compile_order -fileset sources_1 update_compile_order -fileset sources_1 update_compile_order -fileset sources_1 update_compile_order -fileset sources_1 remove_files C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegWB.v file delete -force C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegWB.v update_compile_order -fileset sources_1 launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'top' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj top_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer4.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Multiplexer4 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegMA.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegMA INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegEX.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegEX INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALUControl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALUControl INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegisterFile.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegisterFile INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegID.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegID INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegFI.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegFI INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ControlUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ProgramCounter.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ProgramCounter INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SignalExtension.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module SignalExtension INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ShiftUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ShiftUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module InstructionMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module DataMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALU2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALU2 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Add1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Add1 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module top ERROR: [VRFC 10-46] pcin is already declared [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:85] INFO: [VRFC 10-2458] undeclared symbol flag, assumed default net type wire [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:87] INFO: [VRFC 10-2458] undeclared symbol dmout_2, assumed default net type wire [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:102] INFO: [VRFC 10-2458] undeclared symbol aluout_3, assumed default net type wire [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:102] INFO: [VRFC 10-2458] undeclared symbol rd_4, assumed default net type wire [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:102] INFO: [VRFC 10-2458] undeclared symbol rt_4, assumed default net type wire [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:102] ERROR: [VRFC 10-2071] flag is already implicitly declared on line 87 [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:110] ERROR: [VRFC 10-2071] aluout_3 is already implicitly declared on line 102 [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:123] ERROR: [VRFC 10-2071] dmout_2 is already implicitly declared on line 102 [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:124] ERROR: [VRFC 10-2071] rt_4 is already implicitly declared on line 102 [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:131] ERROR: [VRFC 10-2071] rd_4 is already implicitly declared on line 102 [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:132] ERROR: [VRFC 10-1040] module top ignored due to previous errors [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:37] INFO: [USF-XSim-69] 'compile' step finished in '1' seconds INFO: [USF-XSim-99] Step results log file:'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/xvlog.log' ERROR: [USF-XSim-62] 'compile' step failed with error(s). Please check the Tcl console output or 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/xvlog.log' file for more information. ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation. ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors. launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'top' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj top_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer4.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Multiplexer4 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegMA.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegMA INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegEX.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegEX INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALUControl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALUControl INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegisterFile.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegisterFile INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegID.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegID INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegFI.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegFI INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ControlUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ProgramCounter.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ProgramCounter INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SignalExtension.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module SignalExtension INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ShiftUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ShiftUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module InstructionMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module DataMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALU2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALU2 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Add1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Add1 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module top INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl INFO: [USF-XSim-69] 'compile' step finished in '1' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' Vivado Simulator 2016.2 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: J:/Xilinx/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto 4c388791a4e240948a5554cd0b3617d7 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot top_behav xil_defaultlib.top xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration ERROR: [VRFC 10-93] imm32_2 is not declared under prefix rt_2 [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:105] WARNING: [VRFC 10-278] actual bit length 26 differs from formal bit length 27 for port out26 [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:89] WARNING: [VRFC 10-278] actual bit length 32 differs from formal bit length 5 for port wreg [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:103] WARNING: [VRFC 10-278] actual bit length 32 differs from formal bit length 5 for port rs [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:105] WARNING: [VRFC 10-278] actual bit length 6 differs from formal bit length 32 for port a [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:118] WARNING: [VRFC 10-278] actual bit length 5 differs from formal bit length 32 for port wdata [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:131] ERROR: [XSIM 43-3322] Static elaboration of top level Verilog design unit(s) in library work failed. INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds INFO: [USF-XSim-99] Step results log file:'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/elaborate.log' ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/elaborate.log' file for more information. ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation. ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors. launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'top' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj top_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer4.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Multiplexer4 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegMA.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegMA INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegEX.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegEX INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALUControl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALUControl INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegisterFile.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegisterFile INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegID.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegID INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegFI.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegFI INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ControlUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ProgramCounter.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ProgramCounter INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SignalExtension.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module SignalExtension INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ShiftUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ShiftUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module InstructionMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module DataMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALU2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALU2 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Add1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Add1 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module top INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl INFO: [USF-XSim-69] 'compile' step finished in '1' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' Vivado Simulator 2016.2 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: J:/Xilinx/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto 4c388791a4e240948a5554cd0b3617d7 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot top_behav xil_defaultlib.top xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration WARNING: [VRFC 10-278] actual bit length 32 differs from formal bit length 5 for port wreg [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:103] WARNING: [VRFC 10-278] actual bit length 32 differs from formal bit length 5 for port rs [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:105] WARNING: [VRFC 10-278] actual bit length 5 differs from formal bit length 32 for port a [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:118] WARNING: [VRFC 10-278] actual bit length 5 differs from formal bit length 6 for port rt [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:122] WARNING: [VRFC 10-278] actual bit length 32 differs from formal bit length 5 for port addr [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:131] Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling module xil_defaultlib.ControlUnit Compiling module xil_defaultlib.ProgramCounter Compiling module xil_defaultlib.Add1 Compiling module xil_defaultlib.InstructionMemory Compiling module xil_defaultlib.RegFI Compiling module xil_defaultlib.RegisterFile Compiling module xil_defaultlib.SignalExtension Compiling module xil_defaultlib.RegID Compiling module xil_defaultlib.ALUControl Compiling module xil_defaultlib.ALU2 Compiling module xil_defaultlib.ShiftUnit Compiling module xil_defaultlib.RegEX Compiling module xil_defaultlib.Multiplexer4 Compiling module xil_defaultlib.DataMemory Compiling module xil_defaultlib.RegMA Compiling module xil_defaultlib.top Compiling module xil_defaultlib.glbl Built simulation snapshot top_behav ****** Webtalk v2016.2 (64-bit) **** SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016 **** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. source C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/xsim.dir/top_behav/webtalk/xsim_webtalk.tcl -notrace INFO: [Common 17-206] Exiting Webtalk at Mon Dec 24 05:41:00 2018... INFO: [USF-XSim-69] 'elaborate' step finished in '4' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' INFO: [USF-XSim-98] *** Running xsim with args "top_behav -key {Behavioral:sim_1:Functional:top} -tclbatch {top.tcl} -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature Vivado Simulator 2016.2 Time resolution is 1 ps source top.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns INFO: [USF-XSim-96] XSim completed. Design snapshot 'top_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:01 ; elapsed = 00:00:07 . Memory (MB): peak = 1313.207 ; gain = 0.000 close_sim INFO: [Simtcl 6-16] Simulation closed launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'top' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj top_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer4.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Multiplexer4 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegMA.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegMA INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegEX.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegEX INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALUControl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALUControl INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegisterFile.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegisterFile INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegID.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegID INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegFI.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegFI INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ControlUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ProgramCounter.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ProgramCounter INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SignalExtension.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module SignalExtension INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ShiftUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ShiftUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module InstructionMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module DataMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALU2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALU2 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Add1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Add1 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module top INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl INFO: [USF-XSim-69] 'compile' step finished in '2' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' Vivado Simulator 2016.2 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: J:/Xilinx/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto 4c388791a4e240948a5554cd0b3617d7 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot top_behav xil_defaultlib.top xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration WARNING: [VRFC 10-278] actual bit length 32 differs from formal bit length 5 for port wreg [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:103] WARNING: [VRFC 10-278] actual bit length 32 differs from formal bit length 5 for port rs [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:105] WARNING: [VRFC 10-278] actual bit length 5 differs from formal bit length 32 for port a [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:118] WARNING: [VRFC 10-278] actual bit length 5 differs from formal bit length 6 for port rt [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:122] WARNING: [VRFC 10-278] actual bit length 32 differs from formal bit length 5 for port addr [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:131] Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling module xil_defaultlib.ControlUnit Compiling module xil_defaultlib.ProgramCounter Compiling module xil_defaultlib.Add1 Compiling module xil_defaultlib.InstructionMemory Compiling module xil_defaultlib.RegFI Compiling module xil_defaultlib.RegisterFile Compiling module xil_defaultlib.SignalExtension Compiling module xil_defaultlib.RegID Compiling module xil_defaultlib.ALUControl Compiling module xil_defaultlib.ALU2 Compiling module xil_defaultlib.ShiftUnit Compiling module xil_defaultlib.RegEX Compiling module xil_defaultlib.Multiplexer4 Compiling module xil_defaultlib.DataMemory Compiling module xil_defaultlib.RegMA Compiling module xil_defaultlib.top Compiling module xil_defaultlib.glbl Built simulation snapshot top_behav ****** Webtalk v2016.2 (64-bit) **** SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016 **** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. source C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/xsim.dir/top_behav/webtalk/xsim_webtalk.tcl -notrace INFO: [Common 17-206] Exiting Webtalk at Mon Dec 24 05:42:59 2018... INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' INFO: [USF-XSim-98] *** Running xsim with args "top_behav -key {Behavioral:sim_1:Functional:top} -tclbatch {top.tcl} -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature Vivado Simulator 2016.2 Time resolution is 1 ps source top.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns INFO: [USF-XSim-96] XSim completed. Design snapshot 'top_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:02 ; elapsed = 00:00:07 . Memory (MB): peak = 1313.207 ; gain = 0.000 close_sim INFO: [Simtcl 6-16] Simulation closed launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'top' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj top_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer4.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Multiplexer4 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegMA.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegMA INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegEX.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegEX INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALUControl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALUControl INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegisterFile.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegisterFile INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegID.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegID INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegFI.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegFI INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ControlUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ProgramCounter.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ProgramCounter INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SignalExtension.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module SignalExtension INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ShiftUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ShiftUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module InstructionMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module DataMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALU2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALU2 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Add1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Add1 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module top INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl INFO: [USF-XSim-69] 'compile' step finished in '2' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' Vivado Simulator 2016.2 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: J:/Xilinx/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto 4c388791a4e240948a5554cd0b3617d7 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot top_behav xil_defaultlib.top xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration WARNING: [VRFC 10-278] actual bit length 32 differs from formal bit length 5 for port wreg [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:103] WARNING: [VRFC 10-278] actual bit length 32 differs from formal bit length 5 for port rs [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:105] WARNING: [VRFC 10-278] actual bit length 5 differs from formal bit length 32 for port a [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:118] WARNING: [VRFC 10-278] actual bit length 5 differs from formal bit length 6 for port rt [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:122] WARNING: [VRFC 10-278] actual bit length 32 differs from formal bit length 5 for port addr [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:131] Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling module xil_defaultlib.ControlUnit Compiling module xil_defaultlib.ProgramCounter Compiling module xil_defaultlib.Add1 Compiling module xil_defaultlib.InstructionMemory Compiling module xil_defaultlib.RegFI Compiling module xil_defaultlib.RegisterFile Compiling module xil_defaultlib.SignalExtension Compiling module xil_defaultlib.RegID Compiling module xil_defaultlib.ALUControl Compiling module xil_defaultlib.ALU2 Compiling module xil_defaultlib.ShiftUnit Compiling module xil_defaultlib.RegEX Compiling module xil_defaultlib.Multiplexer4 Compiling module xil_defaultlib.DataMemory Compiling module xil_defaultlib.RegMA Compiling module xil_defaultlib.top Compiling module xil_defaultlib.glbl Built simulation snapshot top_behav ****** Webtalk v2016.2 (64-bit) **** SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016 **** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. source C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/xsim.dir/top_behav/webtalk/xsim_webtalk.tcl -notrace INFO: [Common 17-206] Exiting Webtalk at Mon Dec 24 05:43:32 2018... INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' INFO: [USF-XSim-98] *** Running xsim with args "top_behav -key {Behavioral:sim_1:Functional:top} -tclbatch {top.tcl} -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature Vivado Simulator 2016.2 Time resolution is 1 ps source top.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns INFO: [USF-XSim-96] XSim completed. Design snapshot 'top_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:02 ; elapsed = 00:00:07 . Memory (MB): peak = 1313.207 ; gain = 0.000 close_sim INFO: [Simtcl 6-16] Simulation closed launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'top' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj top_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer4.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Multiplexer4 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegMA.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegMA INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegEX.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegEX INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALUControl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALUControl INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegisterFile.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegisterFile INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegID.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegID INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegFI.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegFI INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ControlUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ProgramCounter.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ProgramCounter INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SignalExtension.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module SignalExtension INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ShiftUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ShiftUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module InstructionMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module DataMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALU2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALU2 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Add1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Add1 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module top INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl INFO: [USF-XSim-69] 'compile' step finished in '1' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' Vivado Simulator 2016.2 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: J:/Xilinx/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto 4c388791a4e240948a5554cd0b3617d7 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot top_behav xil_defaultlib.top xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration ERROR: [VRFC 10-29] RegisterFile expects 7 arguments [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:103] WARNING: [VRFC 10-278] actual bit length 32 differs from formal bit length 1 for port clk [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:88] WARNING: [VRFC 10-278] actual bit length 1 differs from formal bit length 32 for port wdata [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:103] WARNING: [VRFC 10-278] actual bit length 32 differs from formal bit length 5 for port rs [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:105] WARNING: [VRFC 10-278] actual bit length 5 differs from formal bit length 32 for port a [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:118] WARNING: [VRFC 10-278] actual bit length 5 differs from formal bit length 6 for port rt [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:122] WARNING: [VRFC 10-278] actual bit length 32 differs from formal bit length 5 for port addr [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:131] ERROR: [XSIM 43-3322] Static elaboration of top level Verilog design unit(s) in library work failed. INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds INFO: [USF-XSim-99] Step results log file:'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/elaborate.log' ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/elaborate.log' file for more information. ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation. ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors. launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'top' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj top_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer4.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Multiplexer4 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegMA.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegMA INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegEX.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegEX INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALUControl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALUControl INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegisterFile.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegisterFile INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegID.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegID INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegFI.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegFI INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ControlUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ProgramCounter.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ProgramCounter INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SignalExtension.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module SignalExtension INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ShiftUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ShiftUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module InstructionMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module DataMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALU2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALU2 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Add1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Add1 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module top INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl INFO: [USF-XSim-69] 'compile' step finished in '1' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' Vivado Simulator 2016.2 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: J:/Xilinx/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto 4c388791a4e240948a5554cd0b3617d7 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot top_behav xil_defaultlib.top xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration WARNING: [VRFC 10-278] actual bit length 32 differs from formal bit length 5 for port wreg [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:103] WARNING: [VRFC 10-278] actual bit length 32 differs from formal bit length 5 for port rs [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:105] WARNING: [VRFC 10-278] actual bit length 5 differs from formal bit length 32 for port a [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:118] WARNING: [VRFC 10-278] actual bit length 5 differs from formal bit length 6 for port rt [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:122] WARNING: [VRFC 10-278] actual bit length 32 differs from formal bit length 5 for port addr [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:131] Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling module xil_defaultlib.ControlUnit Compiling module xil_defaultlib.ProgramCounter Compiling module xil_defaultlib.Add1 Compiling module xil_defaultlib.InstructionMemory Compiling module xil_defaultlib.RegFI Compiling module xil_defaultlib.RegisterFile Compiling module xil_defaultlib.SignalExtension Compiling module xil_defaultlib.RegID Compiling module xil_defaultlib.ALUControl Compiling module xil_defaultlib.ALU2 Compiling module xil_defaultlib.ShiftUnit Compiling module xil_defaultlib.RegEX Compiling module xil_defaultlib.Multiplexer4 Compiling module xil_defaultlib.DataMemory Compiling module xil_defaultlib.RegMA Compiling module xil_defaultlib.top Compiling module xil_defaultlib.glbl Built simulation snapshot top_behav ****** Webtalk v2016.2 (64-bit) **** SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016 **** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. source C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/xsim.dir/top_behav/webtalk/xsim_webtalk.tcl -notrace INFO: [Common 17-206] Exiting Webtalk at Mon Dec 24 05:47:04 2018... INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' INFO: [USF-XSim-98] *** Running xsim with args "top_behav -key {Behavioral:sim_1:Functional:top} -tclbatch {top.tcl} -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature Vivado Simulator 2016.2 Time resolution is 1 ps source top.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns INFO: [USF-XSim-96] XSim completed. Design snapshot 'top_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:01 ; elapsed = 00:00:06 . Memory (MB): peak = 1313.207 ; gain = 0.000 close_sim INFO: [Simtcl 6-16] Simulation closed update_compile_order -fileset sources_1 update_compile_order -fileset sources_1 update_compile_order -fileset sources_1 launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'top' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj top_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Multiplexer INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer4.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Multiplexer4 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegMA.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegMA INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegEX.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegEX INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALUControl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALUControl INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegisterFile.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegisterFile INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegID.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegID INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegFI.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegFI INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ControlUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ProgramCounter.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ProgramCounter INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SignalExtension.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module SignalExtension INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ShiftUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ShiftUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module InstructionMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module DataMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALU2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALU2 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Add1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Add1 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module top INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl INFO: [USF-XSim-69] 'compile' step finished in '1' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' Vivado Simulator 2016.2 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: J:/Xilinx/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto 4c388791a4e240948a5554cd0b3617d7 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot top_behav xil_defaultlib.top xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration WARNING: [VRFC 10-278] actual bit length 32 differs from formal bit length 5 for port wreg [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:103] WARNING: [VRFC 10-278] actual bit length 32 differs from formal bit length 5 for port rs [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:105] WARNING: [VRFC 10-278] actual bit length 5 differs from formal bit length 32 for port a [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:118] WARNING: [VRFC 10-278] actual bit length 5 differs from formal bit length 6 for port rt [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:122] WARNING: [VRFC 10-278] actual bit length 32 differs from formal bit length 5 for port addr [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:131] Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling module xil_defaultlib.ControlUnit Compiling module xil_defaultlib.ProgramCounter Compiling module xil_defaultlib.Add1 Compiling module xil_defaultlib.InstructionMemory Compiling module xil_defaultlib.RegFI Compiling module xil_defaultlib.RegisterFile Compiling module xil_defaultlib.SignalExtension Compiling module xil_defaultlib.RegID Compiling module xil_defaultlib.ALUControl Compiling module xil_defaultlib.ALU2 Compiling module xil_defaultlib.ShiftUnit Compiling module xil_defaultlib.RegEX Compiling module xil_defaultlib.Multiplexer4 Compiling module xil_defaultlib.Multiplexer Compiling module xil_defaultlib.DataMemory Compiling module xil_defaultlib.RegMA Compiling module xil_defaultlib.top Compiling module xil_defaultlib.glbl Built simulation snapshot top_behav ****** Webtalk v2016.2 (64-bit) **** SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016 **** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. source C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/xsim.dir/top_behav/webtalk/xsim_webtalk.tcl -notrace INFO: [Common 17-206] Exiting Webtalk at Mon Dec 24 05:58:47 2018... INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' INFO: [USF-XSim-98] *** Running xsim with args "top_behav -key {Behavioral:sim_1:Functional:top} -tclbatch {top.tcl} -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature Vivado Simulator 2016.2 Time resolution is 1 ps source top.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns INFO: [USF-XSim-96] XSim completed. Design snapshot 'top_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:01 ; elapsed = 00:00:06 . Memory (MB): peak = 1313.324 ; gain = 0.000 close_sim INFO: [Simtcl 6-16] Simulation closed launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'top' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj top_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Multiplexer INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer4.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Multiplexer4 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegMA.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegMA INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegEX.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegEX INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALUControl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALUControl INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegisterFile.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegisterFile INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegID.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegID INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegFI.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegFI INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ControlUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ProgramCounter.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ProgramCounter INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SignalExtension.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module SignalExtension INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ShiftUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ShiftUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module InstructionMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module DataMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALU2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALU2 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Add1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Add1 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module top INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl INFO: [USF-XSim-69] 'compile' step finished in '1' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' Vivado Simulator 2016.2 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: J:/Xilinx/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto 4c388791a4e240948a5554cd0b3617d7 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot top_behav xil_defaultlib.top xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration WARNING: [VRFC 10-278] actual bit length 32 differs from formal bit length 5 for port wreg [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:103] WARNING: [VRFC 10-278] actual bit length 32 differs from formal bit length 5 for port rs [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:105] WARNING: [VRFC 10-278] actual bit length 5 differs from formal bit length 32 for port a [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:118] WARNING: [VRFC 10-278] actual bit length 5 differs from formal bit length 6 for port rt [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:122] WARNING: [VRFC 10-278] actual bit length 32 differs from formal bit length 5 for port addr [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:131] Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling module xil_defaultlib.ControlUnit Compiling module xil_defaultlib.ProgramCounter Compiling module xil_defaultlib.Add1 Compiling module xil_defaultlib.InstructionMemory Compiling module xil_defaultlib.RegFI Compiling module xil_defaultlib.RegisterFile Compiling module xil_defaultlib.SignalExtension Compiling module xil_defaultlib.RegID Compiling module xil_defaultlib.ALUControl Compiling module xil_defaultlib.ALU2 Compiling module xil_defaultlib.ShiftUnit Compiling module xil_defaultlib.RegEX Compiling module xil_defaultlib.Multiplexer4 Compiling module xil_defaultlib.Multiplexer Compiling module xil_defaultlib.DataMemory Compiling module xil_defaultlib.RegMA Compiling module xil_defaultlib.top Compiling module xil_defaultlib.glbl Built simulation snapshot top_behav ****** Webtalk v2016.2 (64-bit) **** SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016 **** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. source C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/xsim.dir/top_behav/webtalk/xsim_webtalk.tcl -notrace INFO: [Common 17-206] Exiting Webtalk at Mon Dec 24 06:01:04 2018... INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' INFO: [USF-XSim-98] *** Running xsim with args "top_behav -key {Behavioral:sim_1:Functional:top} -tclbatch {top.tcl} -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature Vivado Simulator 2016.2 Time resolution is 1 ps source top.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns INFO: [USF-XSim-96] XSim completed. Design snapshot 'top_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:02 ; elapsed = 00:00:08 . Memory (MB): peak = 1313.324 ; gain = 0.000 close_sim INFO: [Simtcl 6-16] Simulation closed launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'top' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj top_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Multiplexer INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer4.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Multiplexer4 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegMA.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegMA INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegEX.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegEX INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALUControl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALUControl INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegisterFile.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegisterFile INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegID.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegID INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegFI.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegFI INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ControlUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ProgramCounter.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ProgramCounter INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SignalExtension.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module SignalExtension INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ShiftUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ShiftUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module InstructionMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module DataMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALU2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALU2 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Add1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Add1 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module top INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl INFO: [USF-XSim-69] 'compile' step finished in '2' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' Vivado Simulator 2016.2 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: J:/Xilinx/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto 4c388791a4e240948a5554cd0b3617d7 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot top_behav xil_defaultlib.top xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration WARNING: [VRFC 10-278] actual bit length 32 differs from formal bit length 5 for port wreg [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:103] WARNING: [VRFC 10-278] actual bit length 32 differs from formal bit length 5 for port rs [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:105] WARNING: [VRFC 10-278] actual bit length 5 differs from formal bit length 32 for port a [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:118] WARNING: [VRFC 10-278] actual bit length 5 differs from formal bit length 6 for port rt [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:122] WARNING: [VRFC 10-278] actual bit length 32 differs from formal bit length 5 for port addr [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:131] Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling module xil_defaultlib.ControlUnit Compiling module xil_defaultlib.ProgramCounter Compiling module xil_defaultlib.Add1 Compiling module xil_defaultlib.InstructionMemory Compiling module xil_defaultlib.RegFI Compiling module xil_defaultlib.RegisterFile Compiling module xil_defaultlib.SignalExtension Compiling module xil_defaultlib.RegID Compiling module xil_defaultlib.ALUControl Compiling module xil_defaultlib.ALU2 Compiling module xil_defaultlib.ShiftUnit Compiling module xil_defaultlib.RegEX Compiling module xil_defaultlib.Multiplexer4 Compiling module xil_defaultlib.Multiplexer Compiling module xil_defaultlib.DataMemory Compiling module xil_defaultlib.RegMA Compiling module xil_defaultlib.top Compiling module xil_defaultlib.glbl Built simulation snapshot top_behav ****** Webtalk v2016.2 (64-bit) **** SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016 **** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. source C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/xsim.dir/top_behav/webtalk/xsim_webtalk.tcl -notrace INFO: [Common 17-206] Exiting Webtalk at Mon Dec 24 06:01:59 2018... INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' INFO: [USF-XSim-98] *** Running xsim with args "top_behav -key {Behavioral:sim_1:Functional:top} -tclbatch {top.tcl} -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature Vivado Simulator 2016.2 Time resolution is 1 ps source top.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns INFO: [USF-XSim-96] XSim completed. Design snapshot 'top_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:02 ; elapsed = 00:00:08 . Memory (MB): peak = 1313.324 ; gain = 0.000 close_sim INFO: [Simtcl 6-16] Simulation closed launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'top' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj top_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Multiplexer INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer4.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Multiplexer4 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegMA.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegMA INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegEX.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegEX INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALUControl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALUControl INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegisterFile.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegisterFile INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegID.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegID INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegFI.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegFI INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ControlUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ProgramCounter.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ProgramCounter INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SignalExtension.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module SignalExtension INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ShiftUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ShiftUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module InstructionMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module DataMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALU2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALU2 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Add1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Add1 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module top INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl INFO: [USF-XSim-69] 'compile' step finished in '1' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' Vivado Simulator 2016.2 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: J:/Xilinx/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto 4c388791a4e240948a5554cd0b3617d7 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot top_behav xil_defaultlib.top xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration WARNING: [VRFC 10-278] actual bit length 32 differs from formal bit length 5 for port wreg [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:103] WARNING: [VRFC 10-278] actual bit length 32 differs from formal bit length 5 for port rs [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:105] WARNING: [VRFC 10-278] actual bit length 5 differs from formal bit length 32 for port a [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:118] WARNING: [VRFC 10-278] actual bit length 5 differs from formal bit length 6 for port rt [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:122] WARNING: [VRFC 10-278] actual bit length 32 differs from formal bit length 5 for port addr [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:131] Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling module xil_defaultlib.ControlUnit Compiling module xil_defaultlib.ProgramCounter Compiling module xil_defaultlib.Add1 Compiling module xil_defaultlib.InstructionMemory Compiling module xil_defaultlib.RegFI Compiling module xil_defaultlib.RegisterFile Compiling module xil_defaultlib.SignalExtension Compiling module xil_defaultlib.RegID Compiling module xil_defaultlib.ALUControl Compiling module xil_defaultlib.ALU2 Compiling module xil_defaultlib.ShiftUnit Compiling module xil_defaultlib.RegEX Compiling module xil_defaultlib.Multiplexer4 Compiling module xil_defaultlib.Multiplexer Compiling module xil_defaultlib.DataMemory Compiling module xil_defaultlib.RegMA Compiling module xil_defaultlib.top Compiling module xil_defaultlib.glbl Built simulation snapshot top_behav ****** Webtalk v2016.2 (64-bit) **** SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016 **** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. source C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/xsim.dir/top_behav/webtalk/xsim_webtalk.tcl -notrace INFO: [Common 17-206] Exiting Webtalk at Mon Dec 24 06:02:35 2018... INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' INFO: [USF-XSim-98] *** Running xsim with args "top_behav -key {Behavioral:sim_1:Functional:top} -tclbatch {top.tcl} -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature Vivado Simulator 2016.2 Time resolution is 1 ps source top.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns INFO: [USF-XSim-96] XSim completed. Design snapshot 'top_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:03 ; elapsed = 00:00:08 . Memory (MB): peak = 1320.301 ; gain = 6.977 update_compile_order -fileset sources_1 close_sim INFO: [Simtcl 6-16] Simulation closed launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'top' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj top_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer4.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Multiplexer4 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegMA.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegMA INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegEX.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegEX INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALUControl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALUControl INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegisterFile.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegisterFile INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegID.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegID INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegFI.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegFI INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ControlUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ProgramCounter.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ProgramCounter INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SignalExtension.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module SignalExtension INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ShiftUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ShiftUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module InstructionMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module DataMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALU2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALU2 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Add1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Add1 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module top INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl INFO: [USF-XSim-69] 'compile' step finished in '1' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' Vivado Simulator 2016.2 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: J:/Xilinx/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto 4c388791a4e240948a5554cd0b3617d7 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot top_behav xil_defaultlib.top xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration WARNING: [VRFC 10-278] actual bit length 32 differs from formal bit length 1 for port clk [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:88] WARNING: [VRFC 10-278] actual bit length 32 differs from formal bit length 5 for port wreg [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:103] WARNING: [VRFC 10-278] actual bit length 32 differs from formal bit length 5 for port rs [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:105] WARNING: [VRFC 10-278] actual bit length 5 differs from formal bit length 32 for port a [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:118] WARNING: [VRFC 10-278] actual bit length 5 differs from formal bit length 6 for port rt [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:122] WARNING: [VRFC 10-278] actual bit length 32 differs from formal bit length 5 for port addr [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:131] Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling module xil_defaultlib.ControlUnit Compiling module xil_defaultlib.ProgramCounter Compiling module xil_defaultlib.Add1 Compiling module xil_defaultlib.InstructionMemory Compiling module xil_defaultlib.RegFI Compiling module xil_defaultlib.RegisterFile Compiling module xil_defaultlib.SignalExtension Compiling module xil_defaultlib.RegID Compiling module xil_defaultlib.ALUControl Compiling module xil_defaultlib.ALU2 Compiling module xil_defaultlib.ShiftUnit Compiling module xil_defaultlib.RegEX Compiling module xil_defaultlib.Multiplexer4 Compiling module xil_defaultlib.DataMemory Compiling module xil_defaultlib.RegMA Compiling module xil_defaultlib.top Compiling module xil_defaultlib.glbl Built simulation snapshot top_behav ****** Webtalk v2016.2 (64-bit) **** SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016 **** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. source C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/xsim.dir/top_behav/webtalk/xsim_webtalk.tcl -notrace INFO: [Common 17-206] Exiting Webtalk at Mon Dec 24 06:04:53 2018... INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' INFO: [USF-XSim-98] *** Running xsim with args "top_behav -key {Behavioral:sim_1:Functional:top} -tclbatch {top.tcl} -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature Vivado Simulator 2016.2 Time resolution is 1 ps source top.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns INFO: [USF-XSim-96] XSim completed. Design snapshot 'top_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:02 ; elapsed = 00:00:07 . Memory (MB): peak = 1320.914 ; gain = 0.000 close_sim INFO: [Simtcl 6-16] Simulation closed launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'top' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj top_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer4.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Multiplexer4 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegMA.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegMA INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegEX.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegEX INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALUControl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALUControl INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegisterFile.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegisterFile INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegID.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegID INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegFI.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegFI INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ControlUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ProgramCounter.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ProgramCounter INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SignalExtension.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module SignalExtension INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ShiftUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ShiftUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module InstructionMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module DataMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALU2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALU2 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Add1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Add1 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module top INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl INFO: [USF-XSim-69] 'compile' step finished in '1' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' Vivado Simulator 2016.2 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: J:/Xilinx/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto 4c388791a4e240948a5554cd0b3617d7 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot top_behav xil_defaultlib.top xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration WARNING: [VRFC 10-278] actual bit length 32 differs from formal bit length 5 for port wreg [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:103] WARNING: [VRFC 10-278] actual bit length 32 differs from formal bit length 5 for port rs [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:105] WARNING: [VRFC 10-278] actual bit length 5 differs from formal bit length 32 for port a [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:118] WARNING: [VRFC 10-278] actual bit length 5 differs from formal bit length 6 for port rt [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:122] WARNING: [VRFC 10-278] actual bit length 32 differs from formal bit length 5 for port addr [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:131] Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling module xil_defaultlib.ControlUnit Compiling module xil_defaultlib.ProgramCounter Compiling module xil_defaultlib.Add1 Compiling module xil_defaultlib.InstructionMemory Compiling module xil_defaultlib.RegFI Compiling module xil_defaultlib.RegisterFile Compiling module xil_defaultlib.SignalExtension Compiling module xil_defaultlib.RegID Compiling module xil_defaultlib.ALUControl Compiling module xil_defaultlib.ALU2 Compiling module xil_defaultlib.ShiftUnit Compiling module xil_defaultlib.RegEX Compiling module xil_defaultlib.Multiplexer4 Compiling module xil_defaultlib.DataMemory Compiling module xil_defaultlib.RegMA Compiling module xil_defaultlib.top Compiling module xil_defaultlib.glbl Built simulation snapshot top_behav ****** Webtalk v2016.2 (64-bit) **** SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016 **** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. source C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/xsim.dir/top_behav/webtalk/xsim_webtalk.tcl -notrace INFO: [Common 17-206] Exiting Webtalk at Mon Dec 24 06:05:47 2018... INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' INFO: [USF-XSim-98] *** Running xsim with args "top_behav -key {Behavioral:sim_1:Functional:top} -tclbatch {top.tcl} -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature Vivado Simulator 2016.2 Time resolution is 1 ps source top.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns INFO: [USF-XSim-96] XSim completed. Design snapshot 'top_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:02 ; elapsed = 00:00:08 . Memory (MB): peak = 1320.914 ; gain = 0.000 close_sim INFO: [Simtcl 6-16] Simulation closed launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'top' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj top_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer4.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Multiplexer4 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegMA.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegMA INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegEX.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegEX INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALUControl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALUControl INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegisterFile.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegisterFile INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegID.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegID INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegFI.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegFI INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ControlUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ProgramCounter.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ProgramCounter INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SignalExtension.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module SignalExtension INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ShiftUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ShiftUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module InstructionMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module DataMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALU2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALU2 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Add1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Add1 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module top INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl INFO: [USF-XSim-69] 'compile' step finished in '1' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' Vivado Simulator 2016.2 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: J:/Xilinx/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto 4c388791a4e240948a5554cd0b3617d7 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot top_behav xil_defaultlib.top xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration WARNING: [VRFC 10-278] actual bit length 32 differs from formal bit length 5 for port rs [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:105] WARNING: [VRFC 10-278] actual bit length 5 differs from formal bit length 32 for port a [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:118] WARNING: [VRFC 10-278] actual bit length 5 differs from formal bit length 6 for port rt [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:122] WARNING: [VRFC 10-278] actual bit length 32 differs from formal bit length 5 for port addr [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:131] Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling module xil_defaultlib.ControlUnit Compiling module xil_defaultlib.ProgramCounter Compiling module xil_defaultlib.Add1 Compiling module xil_defaultlib.InstructionMemory Compiling module xil_defaultlib.RegFI Compiling module xil_defaultlib.RegisterFile Compiling module xil_defaultlib.SignalExtension Compiling module xil_defaultlib.RegID Compiling module xil_defaultlib.ALUControl Compiling module xil_defaultlib.ALU2 Compiling module xil_defaultlib.ShiftUnit Compiling module xil_defaultlib.RegEX Compiling module xil_defaultlib.Multiplexer4 Compiling module xil_defaultlib.DataMemory Compiling module xil_defaultlib.RegMA Compiling module xil_defaultlib.top Compiling module xil_defaultlib.glbl Built simulation snapshot top_behav ****** Webtalk v2016.2 (64-bit) **** SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016 **** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. source C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/xsim.dir/top_behav/webtalk/xsim_webtalk.tcl -notrace INFO: [Common 17-206] Exiting Webtalk at Mon Dec 24 06:07:54 2018... INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' INFO: [USF-XSim-98] *** Running xsim with args "top_behav -key {Behavioral:sim_1:Functional:top} -tclbatch {top.tcl} -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature Vivado Simulator 2016.2 Time resolution is 1 ps source top.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns INFO: [USF-XSim-96] XSim completed. Design snapshot 'top_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:03 ; elapsed = 00:00:08 . Memory (MB): peak = 1321.109 ; gain = 0.000 close_sim INFO: [Simtcl 6-16] Simulation closed launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'top' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj top_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer4.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Multiplexer4 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegMA.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegMA INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegEX.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegEX INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALUControl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALUControl INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegisterFile.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegisterFile INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegID.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegID INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegFI.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegFI INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ControlUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ProgramCounter.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ProgramCounter INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SignalExtension.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module SignalExtension INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ShiftUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ShiftUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module InstructionMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module DataMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALU2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALU2 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Add1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Add1 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module top INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl INFO: [USF-XSim-69] 'compile' step finished in '1' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' Vivado Simulator 2016.2 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: J:/Xilinx/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto 4c388791a4e240948a5554cd0b3617d7 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot top_behav xil_defaultlib.top xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration WARNING: [VRFC 10-278] actual bit length 5 differs from formal bit length 32 for port Rs [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:105] WARNING: [VRFC 10-278] actual bit length 5 differs from formal bit length 32 for port a [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:118] WARNING: [VRFC 10-278] actual bit length 5 differs from formal bit length 6 for port rt [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:122] WARNING: [VRFC 10-278] actual bit length 32 differs from formal bit length 5 for port addr [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:131] Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling module xil_defaultlib.ControlUnit Compiling module xil_defaultlib.ProgramCounter Compiling module xil_defaultlib.Add1 Compiling module xil_defaultlib.InstructionMemory Compiling module xil_defaultlib.RegFI Compiling module xil_defaultlib.RegisterFile Compiling module xil_defaultlib.SignalExtension Compiling module xil_defaultlib.RegID Compiling module xil_defaultlib.ALUControl Compiling module xil_defaultlib.ALU2 Compiling module xil_defaultlib.ShiftUnit Compiling module xil_defaultlib.RegEX Compiling module xil_defaultlib.Multiplexer4 Compiling module xil_defaultlib.DataMemory Compiling module xil_defaultlib.RegMA Compiling module xil_defaultlib.top Compiling module xil_defaultlib.glbl Built simulation snapshot top_behav ****** Webtalk v2016.2 (64-bit) **** SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016 **** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. source C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/xsim.dir/top_behav/webtalk/xsim_webtalk.tcl -notrace INFO: [Common 17-206] Exiting Webtalk at Mon Dec 24 06:10:51 2018... INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' INFO: [USF-XSim-98] *** Running xsim with args "top_behav -key {Behavioral:sim_1:Functional:top} -tclbatch {top.tcl} -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature Vivado Simulator 2016.2 Time resolution is 1 ps source top.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns INFO: [USF-XSim-96] XSim completed. Design snapshot 'top_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:02 ; elapsed = 00:00:08 . Memory (MB): peak = 1326.348 ; gain = 0.000 close_sim INFO: [Simtcl 6-16] Simulation closed launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'top' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj top_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer4.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Multiplexer4 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegMA.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegMA INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegEX.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegEX INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALUControl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALUControl INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegisterFile.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegisterFile INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegID.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegID INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegFI.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegFI INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ControlUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ProgramCounter.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ProgramCounter INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SignalExtension.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module SignalExtension INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ShiftUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ShiftUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module InstructionMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module DataMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALU2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALU2 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Add1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Add1 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module top INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl INFO: [USF-XSim-69] 'compile' step finished in '1' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' Vivado Simulator 2016.2 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: J:/Xilinx/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto 4c388791a4e240948a5554cd0b3617d7 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot top_behav xil_defaultlib.top xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration WARNING: [VRFC 10-278] actual bit length 32 differs from formal bit length 5 for port addr [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:131] Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling module xil_defaultlib.ControlUnit Compiling module xil_defaultlib.ProgramCounter Compiling module xil_defaultlib.Add1 Compiling module xil_defaultlib.InstructionMemory Compiling module xil_defaultlib.RegFI Compiling module xil_defaultlib.RegisterFile Compiling module xil_defaultlib.SignalExtension Compiling module xil_defaultlib.RegID Compiling module xil_defaultlib.ALUControl Compiling module xil_defaultlib.ALU2 Compiling module xil_defaultlib.ShiftUnit Compiling module xil_defaultlib.RegEX Compiling module xil_defaultlib.Multiplexer4 Compiling module xil_defaultlib.DataMemory Compiling module xil_defaultlib.RegMA Compiling module xil_defaultlib.top Compiling module xil_defaultlib.glbl Built simulation snapshot top_behav ****** Webtalk v2016.2 (64-bit) **** SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016 **** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. source C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/xsim.dir/top_behav/webtalk/xsim_webtalk.tcl -notrace INFO: [Common 17-206] Exiting Webtalk at Mon Dec 24 06:15:38 2018... INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' INFO: [USF-XSim-98] *** Running xsim with args "top_behav -key {Behavioral:sim_1:Functional:top} -tclbatch {top.tcl} -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature Vivado Simulator 2016.2 Time resolution is 1 ps source top.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns INFO: [USF-XSim-96] XSim completed. Design snapshot 'top_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:02 ; elapsed = 00:00:08 . Memory (MB): peak = 1344.523 ; gain = 0.000 close_sim INFO: [Simtcl 6-16] Simulation closed launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'top' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj top_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer4.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Multiplexer4 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegMA.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegMA INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegEX.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegEX INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALUControl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALUControl INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegisterFile.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegisterFile INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegID.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegID INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegFI.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegFI INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ControlUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ProgramCounter.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ProgramCounter INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SignalExtension.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module SignalExtension INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ShiftUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ShiftUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module InstructionMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module DataMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALU2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALU2 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Add1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Add1 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module top INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl INFO: [USF-XSim-69] 'compile' step finished in '1' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' Vivado Simulator 2016.2 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: J:/Xilinx/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto 4c388791a4e240948a5554cd0b3617d7 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot top_behav xil_defaultlib.top xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration WARNING: [VRFC 10-278] actual bit length 32 differs from formal bit length 5 for port addr [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:131] Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling module xil_defaultlib.ControlUnit Compiling module xil_defaultlib.ProgramCounter Compiling module xil_defaultlib.Add1 Compiling module xil_defaultlib.InstructionMemory Compiling module xil_defaultlib.RegFI Compiling module xil_defaultlib.RegisterFile Compiling module xil_defaultlib.SignalExtension Compiling module xil_defaultlib.RegID Compiling module xil_defaultlib.ALUControl Compiling module xil_defaultlib.ALU2 Compiling module xil_defaultlib.ShiftUnit Compiling module xil_defaultlib.RegEX Compiling module xil_defaultlib.Multiplexer4 Compiling module xil_defaultlib.DataMemory Compiling module xil_defaultlib.RegMA Compiling module xil_defaultlib.top Compiling module xil_defaultlib.glbl Built simulation snapshot top_behav ****** Webtalk v2016.2 (64-bit) **** SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016 **** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. source C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/xsim.dir/top_behav/webtalk/xsim_webtalk.tcl -notrace INFO: [Common 17-206] Exiting Webtalk at Mon Dec 24 06:20:41 2018... INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' INFO: [USF-XSim-98] *** Running xsim with args "top_behav -key {Behavioral:sim_1:Functional:top} -tclbatch {top.tcl} -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature Vivado Simulator 2016.2 Time resolution is 1 ps source top.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns INFO: [USF-XSim-96] XSim completed. Design snapshot 'top_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:03 ; elapsed = 00:00:08 . Memory (MB): peak = 1344.523 ; gain = 0.000 close_sim INFO: [Simtcl 6-16] Simulation closed launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'top' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj top_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer4.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Multiplexer4 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegMA.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegMA INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegEX.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegEX INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALUControl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALUControl INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegisterFile.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegisterFile INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegID.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegID INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegFI.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegFI INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ControlUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ProgramCounter.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ProgramCounter INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SignalExtension.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module SignalExtension INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ShiftUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ShiftUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module InstructionMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module DataMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALU2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALU2 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Add1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Add1 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module top INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl INFO: [USF-XSim-69] 'compile' step finished in '1' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' Vivado Simulator 2016.2 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: J:/Xilinx/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto 4c388791a4e240948a5554cd0b3617d7 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot top_behav xil_defaultlib.top xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration WARNING: [VRFC 10-278] actual bit length 32 differs from formal bit length 5 for port addr [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:131] Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling module xil_defaultlib.ControlUnit Compiling module xil_defaultlib.ProgramCounter Compiling module xil_defaultlib.Add1 Compiling module xil_defaultlib.InstructionMemory Compiling module xil_defaultlib.RegFI Compiling module xil_defaultlib.RegisterFile Compiling module xil_defaultlib.SignalExtension Compiling module xil_defaultlib.RegID Compiling module xil_defaultlib.ALUControl Compiling module xil_defaultlib.ALU2 Compiling module xil_defaultlib.ShiftUnit Compiling module xil_defaultlib.RegEX Compiling module xil_defaultlib.Multiplexer4 Compiling module xil_defaultlib.DataMemory Compiling module xil_defaultlib.RegMA Compiling module xil_defaultlib.top Compiling module xil_defaultlib.glbl Built simulation snapshot top_behav ****** Webtalk v2016.2 (64-bit) **** SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016 **** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. source C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/xsim.dir/top_behav/webtalk/xsim_webtalk.tcl -notrace INFO: [Common 17-206] Exiting Webtalk at Mon Dec 24 06:23:28 2018... INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' INFO: [USF-XSim-98] *** Running xsim with args "top_behav -key {Behavioral:sim_1:Functional:top} -tclbatch {top.tcl} -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature Vivado Simulator 2016.2 Time resolution is 1 ps source top.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns INFO: [USF-XSim-96] XSim completed. Design snapshot 'top_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:02 ; elapsed = 00:00:08 . Memory (MB): peak = 1346.113 ; gain = 0.000 update_compile_order -fileset sources_1 close_sim INFO: [Simtcl 6-16] Simulation closed launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'top' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj top_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Multiplexer INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer4.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Multiplexer4 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegMA.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegMA INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegEX.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegEX INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALUControl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALUControl INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegisterFile.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegisterFile INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegID.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegID INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegFI.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegFI INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ControlUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ProgramCounter.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ProgramCounter INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SignalExtension.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module SignalExtension INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ShiftUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ShiftUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module InstructionMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module DataMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALU2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALU2 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Add1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Add1 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module top INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl INFO: [USF-XSim-69] 'compile' step finished in '1' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' Vivado Simulator 2016.2 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: J:/Xilinx/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto 4c388791a4e240948a5554cd0b3617d7 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot top_behav xil_defaultlib.top xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration WARNING: [VRFC 10-278] actual bit length 32 differs from formal bit length 5 for port addr [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:131] Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling module xil_defaultlib.ControlUnit Compiling module xil_defaultlib.ProgramCounter Compiling module xil_defaultlib.Add1 Compiling module xil_defaultlib.InstructionMemory Compiling module xil_defaultlib.RegFI Compiling module xil_defaultlib.RegisterFile Compiling module xil_defaultlib.SignalExtension Compiling module xil_defaultlib.RegID Compiling module xil_defaultlib.ALUControl Compiling module xil_defaultlib.ALU2 Compiling module xil_defaultlib.ShiftUnit Compiling module xil_defaultlib.RegEX Compiling module xil_defaultlib.Multiplexer4 Compiling module xil_defaultlib.Multiplexer Compiling module xil_defaultlib.DataMemory Compiling module xil_defaultlib.RegMA Compiling module xil_defaultlib.top Compiling module xil_defaultlib.glbl Built simulation snapshot top_behav ****** Webtalk v2016.2 (64-bit) **** SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016 **** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. source C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/xsim.dir/top_behav/webtalk/xsim_webtalk.tcl -notrace INFO: [Common 17-206] Exiting Webtalk at Mon Dec 24 06:25:53 2018... INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' INFO: [USF-XSim-98] *** Running xsim with args "top_behav -key {Behavioral:sim_1:Functional:top} -tclbatch {top.tcl} -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature Vivado Simulator 2016.2 Time resolution is 1 ps source top.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns INFO: [USF-XSim-96] XSim completed. Design snapshot 'top_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:02 ; elapsed = 00:00:08 . Memory (MB): peak = 1346.113 ; gain = 0.000 update_compile_order -fileset sources_1 close_sim INFO: [Simtcl 6-16] Simulation closed launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'top' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj top_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer4.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Multiplexer4 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegMA.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegMA INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegEX.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegEX INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALUControl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALUControl INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegisterFile.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegisterFile INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegID.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegID INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegFI.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegFI INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ControlUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ProgramCounter.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ProgramCounter INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SignalExtension.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module SignalExtension INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ShiftUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ShiftUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module InstructionMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module DataMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALU2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALU2 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Add1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Add1 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module top INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl INFO: [USF-XSim-69] 'compile' step finished in '1' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' Vivado Simulator 2016.2 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: J:/Xilinx/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto 4c388791a4e240948a5554cd0b3617d7 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot top_behav xil_defaultlib.top xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration WARNING: [VRFC 10-278] actual bit length 32 differs from formal bit length 5 for port addr [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:132] Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling module xil_defaultlib.ControlUnit Compiling module xil_defaultlib.ProgramCounter Compiling module xil_defaultlib.Add1 Compiling module xil_defaultlib.InstructionMemory Compiling module xil_defaultlib.RegFI Compiling module xil_defaultlib.RegisterFile Compiling module xil_defaultlib.SignalExtension Compiling module xil_defaultlib.RegID Compiling module xil_defaultlib.ALUControl Compiling module xil_defaultlib.ALU2 Compiling module xil_defaultlib.ShiftUnit Compiling module xil_defaultlib.RegEX Compiling module xil_defaultlib.Multiplexer4 Compiling module xil_defaultlib.DataMemory Compiling module xil_defaultlib.RegMA Compiling module xil_defaultlib.top Compiling module xil_defaultlib.glbl Built simulation snapshot top_behav ****** Webtalk v2016.2 (64-bit) **** SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016 **** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. source C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/xsim.dir/top_behav/webtalk/xsim_webtalk.tcl -notrace INFO: [Common 17-206] Exiting Webtalk at Mon Dec 24 06:32:57 2018... INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' INFO: [USF-XSim-98] *** Running xsim with args "top_behav -key {Behavioral:sim_1:Functional:top} -tclbatch {top.tcl} -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature Vivado Simulator 2016.2 Time resolution is 1 ps source top.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns INFO: [USF-XSim-96] XSim completed. Design snapshot 'top_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:03 ; elapsed = 00:00:09 . Memory (MB): peak = 1346.113 ; gain = 0.000 close_sim INFO: [Simtcl 6-16] Simulation closed launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'top' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj top_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer4.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Multiplexer4 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegMA.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegMA INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegEX.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegEX INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALUControl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALUControl INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegisterFile.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegisterFile INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegID.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegID INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegFI.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegFI INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ControlUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ProgramCounter.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ProgramCounter INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SignalExtension.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module SignalExtension INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ShiftUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ShiftUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module InstructionMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module DataMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALU2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALU2 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Add1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Add1 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module top INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl INFO: [USF-XSim-69] 'compile' step finished in '1' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' Vivado Simulator 2016.2 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: J:/Xilinx/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto 4c388791a4e240948a5554cd0b3617d7 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot top_behav xil_defaultlib.top xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration WARNING: [VRFC 10-278] actual bit length 32 differs from formal bit length 5 for port addr [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:133] Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling module xil_defaultlib.ControlUnit Compiling module xil_defaultlib.ProgramCounter Compiling module xil_defaultlib.Add1 Compiling module xil_defaultlib.InstructionMemory Compiling module xil_defaultlib.RegFI Compiling module xil_defaultlib.RegisterFile Compiling module xil_defaultlib.SignalExtension Compiling module xil_defaultlib.RegID Compiling module xil_defaultlib.ALUControl Compiling module xil_defaultlib.ALU2 Compiling module xil_defaultlib.ShiftUnit Compiling module xil_defaultlib.RegEX Compiling module xil_defaultlib.Multiplexer4 Compiling module xil_defaultlib.DataMemory Compiling module xil_defaultlib.RegMA Compiling module xil_defaultlib.top Compiling module xil_defaultlib.glbl Built simulation snapshot top_behav ****** Webtalk v2016.2 (64-bit) **** SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016 **** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. source C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/xsim.dir/top_behav/webtalk/xsim_webtalk.tcl -notrace INFO: [Common 17-206] Exiting Webtalk at Mon Dec 24 06:45:06 2018... INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' INFO: [USF-XSim-98] *** Running xsim with args "top_behav -key {Behavioral:sim_1:Functional:top} -tclbatch {top.tcl} -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature Vivado Simulator 2016.2 Time resolution is 1 ps source top.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns INFO: [USF-XSim-96] XSim completed. Design snapshot 'top_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:03 ; elapsed = 00:00:08 . Memory (MB): peak = 1346.113 ; gain = 0.000 close_sim INFO: [Simtcl 6-16] Simulation closed launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'top' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj top_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer4.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Multiplexer4 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegMA.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegMA INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegEX.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegEX INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALUControl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALUControl INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegisterFile.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegisterFile INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegID.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegID INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegFI.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegFI INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ControlUnit ERROR: [VRFC 10-394] cannot access memory opcode directly [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v:57] ERROR: [VRFC 10-394] cannot access memory opcode directly [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v:58] ERROR: [VRFC 10-394] cannot access memory opcode directly [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v:59] ERROR: [VRFC 10-394] cannot access memory opcode directly [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v:60] ERROR: [VRFC 10-394] cannot access memory opcode directly [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v:61] ERROR: [VRFC 10-394] cannot access memory opcode directly [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v:62] ERROR: [VRFC 10-394] cannot access memory opcode directly [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v:63] ERROR: [VRFC 10-1040] module ControlUnit ignored due to previous errors [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v:36] INFO: [USF-XSim-69] 'compile' step finished in '1' seconds INFO: [USF-XSim-99] Step results log file:'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/xvlog.log' ERROR: [USF-XSim-62] 'compile' step failed with error(s). Please check the Tcl console output or 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/xvlog.log' file for more information. ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation. ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors. launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'top' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj top_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer4.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Multiplexer4 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegMA.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegMA INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegEX.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegEX INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALUControl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALUControl INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegisterFile.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegisterFile INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegID.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegID INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegFI.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegFI INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ControlUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ProgramCounter.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ProgramCounter INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SignalExtension.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module SignalExtension INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ShiftUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ShiftUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module InstructionMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module DataMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALU2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALU2 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Add1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Add1 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module top INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl INFO: [USF-XSim-69] 'compile' step finished in '1' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' Vivado Simulator 2016.2 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: J:/Xilinx/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto 4c388791a4e240948a5554cd0b3617d7 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot top_behav xil_defaultlib.top xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration WARNING: [VRFC 10-278] actual bit length 32 differs from formal bit length 5 for port addr [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:140] Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling module xil_defaultlib.ControlUnit Compiling module xil_defaultlib.ProgramCounter Compiling module xil_defaultlib.Add1 Compiling module xil_defaultlib.InstructionMemory Compiling module xil_defaultlib.RegFI Compiling module xil_defaultlib.RegisterFile Compiling module xil_defaultlib.SignalExtension Compiling module xil_defaultlib.RegID Compiling module xil_defaultlib.ALUControl Compiling module xil_defaultlib.ALU2 Compiling module xil_defaultlib.ShiftUnit Compiling module xil_defaultlib.RegEX Compiling module xil_defaultlib.Multiplexer4 Compiling module xil_defaultlib.DataMemory Compiling module xil_defaultlib.RegMA Compiling module xil_defaultlib.top Compiling module xil_defaultlib.glbl Built simulation snapshot top_behav ****** Webtalk v2016.2 (64-bit) **** SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016 **** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. source C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/xsim.dir/top_behav/webtalk/xsim_webtalk.tcl -notrace INFO: [Common 17-206] Exiting Webtalk at Mon Dec 24 16:20:19 2018... INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' INFO: [USF-XSim-98] *** Running xsim with args "top_behav -key {Behavioral:sim_1:Functional:top} -tclbatch {top.tcl} -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature Vivado Simulator 2016.2 Time resolution is 1 ps source top.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns INFO: [USF-XSim-96] XSim completed. Design snapshot 'top_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:01 ; elapsed = 00:00:07 . Memory (MB): peak = 1354.344 ; gain = 1.414 close_sim INFO: [Simtcl 6-16] Simulation closed launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'top' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj top_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer4.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Multiplexer4 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegMA.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegMA INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegEX.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegEX INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALUControl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALUControl INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegisterFile.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegisterFile INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegID.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegID INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegFI.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegFI INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ControlUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ProgramCounter.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ProgramCounter INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SignalExtension.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module SignalExtension INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ShiftUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ShiftUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module InstructionMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module DataMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALU2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALU2 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Add1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Add1 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module top INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl INFO: [USF-XSim-69] 'compile' step finished in '2' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' Vivado Simulator 2016.2 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: J:/Xilinx/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto 4c388791a4e240948a5554cd0b3617d7 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot top_behav xil_defaultlib.top xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration WARNING: [VRFC 10-278] actual bit length 32 differs from formal bit length 5 for port addr [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:140] Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling module xil_defaultlib.ControlUnit Compiling module xil_defaultlib.ProgramCounter Compiling module xil_defaultlib.Add1 Compiling module xil_defaultlib.InstructionMemory Compiling module xil_defaultlib.RegFI Compiling module xil_defaultlib.RegisterFile Compiling module xil_defaultlib.SignalExtension Compiling module xil_defaultlib.RegID Compiling module xil_defaultlib.ALUControl Compiling module xil_defaultlib.ALU2 Compiling module xil_defaultlib.ShiftUnit Compiling module xil_defaultlib.RegEX Compiling module xil_defaultlib.Multiplexer4 Compiling module xil_defaultlib.DataMemory Compiling module xil_defaultlib.RegMA Compiling module xil_defaultlib.top Compiling module xil_defaultlib.glbl Built simulation snapshot top_behav ****** Webtalk v2016.2 (64-bit) **** SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016 **** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. source C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/xsim.dir/top_behav/webtalk/xsim_webtalk.tcl -notrace INFO: [Common 17-206] Exiting Webtalk at Mon Dec 24 16:48:44 2018... INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' INFO: [USF-XSim-98] *** Running xsim with args "top_behav -key {Behavioral:sim_1:Functional:top} -tclbatch {top.tcl} -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature Vivado Simulator 2016.2 Time resolution is 1 ps source top.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns INFO: [USF-XSim-96] XSim completed. Design snapshot 'top_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:03 ; elapsed = 00:00:09 . Memory (MB): peak = 1390.645 ; gain = 0.000 close_sim INFO: [Simtcl 6-16] Simulation closed launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'top' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj top_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer4.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Multiplexer4 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegMA.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegMA INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegEX.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegEX INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALUControl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALUControl INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegisterFile.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegisterFile INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegID.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegID INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegFI.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegFI INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ControlUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ProgramCounter.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ProgramCounter INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SignalExtension.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module SignalExtension INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ShiftUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ShiftUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module InstructionMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module DataMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALU2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALU2 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Add1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Add1 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module top INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl INFO: [USF-XSim-69] 'compile' step finished in '1' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' Vivado Simulator 2016.2 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: J:/Xilinx/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto 4c388791a4e240948a5554cd0b3617d7 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot top_behav xil_defaultlib.top xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration WARNING: [VRFC 10-278] actual bit length 32 differs from formal bit length 5 for port addr [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:140] Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling module xil_defaultlib.ControlUnit Compiling module xil_defaultlib.ProgramCounter Compiling module xil_defaultlib.Add1 Compiling module xil_defaultlib.InstructionMemory Compiling module xil_defaultlib.RegFI Compiling module xil_defaultlib.RegisterFile Compiling module xil_defaultlib.SignalExtension Compiling module xil_defaultlib.RegID Compiling module xil_defaultlib.ALUControl Compiling module xil_defaultlib.ALU2 Compiling module xil_defaultlib.ShiftUnit Compiling module xil_defaultlib.RegEX Compiling module xil_defaultlib.Multiplexer4 Compiling module xil_defaultlib.DataMemory Compiling module xil_defaultlib.RegMA Compiling module xil_defaultlib.top Compiling module xil_defaultlib.glbl Built simulation snapshot top_behav ****** Webtalk v2016.2 (64-bit) **** SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016 **** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. source C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/xsim.dir/top_behav/webtalk/xsim_webtalk.tcl -notrace INFO: [Common 17-206] Exiting Webtalk at Mon Dec 24 16:54:17 2018... INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' INFO: [USF-XSim-98] *** Running xsim with args "top_behav -key {Behavioral:sim_1:Functional:top} -tclbatch {top.tcl} -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature Vivado Simulator 2016.2 Time resolution is 1 ps source top.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns INFO: [USF-XSim-96] XSim completed. Design snapshot 'top_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:02 ; elapsed = 00:00:08 . Memory (MB): peak = 1390.645 ; gain = 0.000 close_sim INFO: [Simtcl 6-16] Simulation closed launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'top' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj top_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer4.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Multiplexer4 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegMA.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegMA INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegEX.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegEX INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALUControl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALUControl INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegisterFile.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegisterFile INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegID.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegID INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegFI.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegFI INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ControlUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ProgramCounter.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ProgramCounter INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SignalExtension.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module SignalExtension INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ShiftUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ShiftUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module InstructionMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module DataMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALU2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALU2 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Add1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Add1 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module top INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl INFO: [USF-XSim-69] 'compile' step finished in '1' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' Vivado Simulator 2016.2 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: J:/Xilinx/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto 4c388791a4e240948a5554cd0b3617d7 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot top_behav xil_defaultlib.top xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration WARNING: [VRFC 10-278] actual bit length 32 differs from formal bit length 5 for port addr [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:140] Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling module xil_defaultlib.ControlUnit Compiling module xil_defaultlib.ProgramCounter Compiling module xil_defaultlib.Add1 Compiling module xil_defaultlib.InstructionMemory Compiling module xil_defaultlib.RegFI Compiling module xil_defaultlib.RegisterFile Compiling module xil_defaultlib.SignalExtension Compiling module xil_defaultlib.RegID Compiling module xil_defaultlib.ALUControl Compiling module xil_defaultlib.ALU2 Compiling module xil_defaultlib.ShiftUnit Compiling module xil_defaultlib.RegEX Compiling module xil_defaultlib.Multiplexer4 Compiling module xil_defaultlib.DataMemory Compiling module xil_defaultlib.RegMA Compiling module xil_defaultlib.top Compiling module xil_defaultlib.glbl Built simulation snapshot top_behav ****** Webtalk v2016.2 (64-bit) **** SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016 **** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. source C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/xsim.dir/top_behav/webtalk/xsim_webtalk.tcl -notrace INFO: [Common 17-206] Exiting Webtalk at Mon Dec 24 17:15:53 2018... INFO: [USF-XSim-69] 'elaborate' step finished in '4' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' INFO: [USF-XSim-98] *** Running xsim with args "top_behav -key {Behavioral:sim_1:Functional:top} -tclbatch {top.tcl} -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature Vivado Simulator 2016.2 Time resolution is 1 ps source top.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns INFO: [USF-XSim-96] XSim completed. Design snapshot 'top_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:03 ; elapsed = 00:00:08 . Memory (MB): peak = 1390.645 ; gain = 0.000 close_sim INFO: [Simtcl 6-16] Simulation closed close_sim: Time (s): cpu = 00:00:00 ; elapsed = 00:00:07 . Memory (MB): peak = 1390.645 ; gain = 0.000 launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'top' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj top_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer4.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Multiplexer4 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegMA.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegMA INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegEX.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegEX INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALUControl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALUControl INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegisterFile.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegisterFile INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegID.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegID INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegFI.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegFI INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ControlUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ProgramCounter.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ProgramCounter INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SignalExtension.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module SignalExtension INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ShiftUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ShiftUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module InstructionMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module DataMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALU2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALU2 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Add1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Add1 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module top INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl INFO: [USF-XSim-69] 'compile' step finished in '2' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' Vivado Simulator 2016.2 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: J:/Xilinx/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto 4c388791a4e240948a5554cd0b3617d7 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot top_behav xil_defaultlib.top xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration WARNING: [VRFC 10-278] actual bit length 32 differs from formal bit length 5 for port addr [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:140] Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling module xil_defaultlib.ControlUnit Compiling module xil_defaultlib.ProgramCounter Compiling module xil_defaultlib.Add1 Compiling module xil_defaultlib.InstructionMemory Compiling module xil_defaultlib.RegFI Compiling module xil_defaultlib.RegisterFile Compiling module xil_defaultlib.SignalExtension Compiling module xil_defaultlib.RegID Compiling module xil_defaultlib.ALUControl Compiling module xil_defaultlib.ALU2 Compiling module xil_defaultlib.ShiftUnit Compiling module xil_defaultlib.RegEX Compiling module xil_defaultlib.Multiplexer4 Compiling module xil_defaultlib.DataMemory Compiling module xil_defaultlib.RegMA Compiling module xil_defaultlib.top Compiling module xil_defaultlib.glbl Built simulation snapshot top_behav ****** Webtalk v2016.2 (64-bit) **** SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016 **** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. source C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/xsim.dir/top_behav/webtalk/xsim_webtalk.tcl -notrace INFO: [Common 17-206] Exiting Webtalk at Mon Dec 24 21:22:20 2018... run_program: Time (s): cpu = 00:00:00 ; elapsed = 00:00:07 . Memory (MB): peak = 1390.645 ; gain = 0.000 INFO: [USF-XSim-69] 'elaborate' step finished in '8' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' INFO: [USF-XSim-98] *** Running xsim with args "top_behav -key {Behavioral:sim_1:Functional:top} -tclbatch {top.tcl} -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature Vivado Simulator 2016.2 Time resolution is 1 ps source top.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns INFO: [USF-XSim-96] XSim completed. Design snapshot 'top_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:03 ; elapsed = 00:00:15 . Memory (MB): peak = 1390.645 ; gain = 0.000 close_sim INFO: [Simtcl 6-16] Simulation closed launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'top' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj top_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer4.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Multiplexer4 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegMA.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegMA INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegEX.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegEX INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALUControl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALUControl INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegisterFile.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegisterFile INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegID.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegID INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegFI.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegFI INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ControlUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ProgramCounter.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ProgramCounter INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SignalExtension.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module SignalExtension INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ShiftUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ShiftUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module InstructionMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module DataMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALU2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALU2 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Add1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Add1 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module top INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl INFO: [USF-XSim-69] 'compile' step finished in '1' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' Vivado Simulator 2016.2 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: J:/Xilinx/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto 4c388791a4e240948a5554cd0b3617d7 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot top_behav xil_defaultlib.top xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration WARNING: [VRFC 10-278] actual bit length 32 differs from formal bit length 5 for port addr [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:140] Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling module xil_defaultlib.ControlUnit Compiling module xil_defaultlib.ProgramCounter Compiling module xil_defaultlib.Add1 Compiling module xil_defaultlib.InstructionMemory Compiling module xil_defaultlib.RegFI Compiling module xil_defaultlib.RegisterFile Compiling module xil_defaultlib.SignalExtension Compiling module xil_defaultlib.RegID Compiling module xil_defaultlib.ALUControl Compiling module xil_defaultlib.ALU2 Compiling module xil_defaultlib.ShiftUnit Compiling module xil_defaultlib.RegEX Compiling module xil_defaultlib.Multiplexer4 Compiling module xil_defaultlib.DataMemory Compiling module xil_defaultlib.RegMA Compiling module xil_defaultlib.top Compiling module xil_defaultlib.glbl Built simulation snapshot top_behav ****** Webtalk v2016.2 (64-bit) **** SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016 **** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. source C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/xsim.dir/top_behav/webtalk/xsim_webtalk.tcl -notrace INFO: [Common 17-206] Exiting Webtalk at Mon Dec 24 21:23:51 2018... INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' INFO: [USF-XSim-98] *** Running xsim with args "top_behav -key {Behavioral:sim_1:Functional:top} -tclbatch {top.tcl} -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature Vivado Simulator 2016.2 Time resolution is 1 ps source top.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns INFO: [USF-XSim-96] XSim completed. Design snapshot 'top_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:02 ; elapsed = 00:00:08 . Memory (MB): peak = 1390.645 ; gain = 0.000 close_sim INFO: [Simtcl 6-16] Simulation closed launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'top' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj top_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer4.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Multiplexer4 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegMA.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegMA INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegEX.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegEX INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALUControl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALUControl INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegisterFile.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegisterFile INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegID.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegID INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegFI.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegFI INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ControlUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ProgramCounter.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ProgramCounter INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SignalExtension.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module SignalExtension INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ShiftUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ShiftUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module InstructionMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module DataMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALU2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALU2 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Add1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Add1 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module top INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl INFO: [USF-XSim-69] 'compile' step finished in '1' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' Vivado Simulator 2016.2 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: J:/Xilinx/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto 4c388791a4e240948a5554cd0b3617d7 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot top_behav xil_defaultlib.top xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration WARNING: [VRFC 10-278] actual bit length 32 differs from formal bit length 5 for port addr [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:140] Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling module xil_defaultlib.ControlUnit Compiling module xil_defaultlib.ProgramCounter Compiling module xil_defaultlib.Add1 Compiling module xil_defaultlib.InstructionMemory Compiling module xil_defaultlib.RegFI Compiling module xil_defaultlib.RegisterFile Compiling module xil_defaultlib.SignalExtension Compiling module xil_defaultlib.RegID Compiling module xil_defaultlib.ALUControl Compiling module xil_defaultlib.ALU2 Compiling module xil_defaultlib.ShiftUnit Compiling module xil_defaultlib.RegEX Compiling module xil_defaultlib.Multiplexer4 Compiling module xil_defaultlib.DataMemory Compiling module xil_defaultlib.RegMA Compiling module xil_defaultlib.top Compiling module xil_defaultlib.glbl Built simulation snapshot top_behav ****** Webtalk v2016.2 (64-bit) **** SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016 **** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. source C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/xsim.dir/top_behav/webtalk/xsim_webtalk.tcl -notrace INFO: [Common 17-206] Exiting Webtalk at Mon Dec 24 21:25:40 2018... INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' INFO: [USF-XSim-98] *** Running xsim with args "top_behav -key {Behavioral:sim_1:Functional:top} -tclbatch {top.tcl} -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature Vivado Simulator 2016.2 Time resolution is 1 ps source top.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns INFO: [USF-XSim-96] XSim completed. Design snapshot 'top_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:02 ; elapsed = 00:00:08 . Memory (MB): peak = 1390.645 ; gain = 0.000 close_sim INFO: [Simtcl 6-16] Simulation closed launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'top' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj top_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer4.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Multiplexer4 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegMA.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegMA INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegEX.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegEX ERROR: [VRFC 10-2068] ansi port flag cannot be redeclared in the header [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegEX.v:35] ERROR: [VRFC 10-1040] module RegEX ignored due to previous errors [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegEX.v:23] INFO: [USF-XSim-69] 'compile' step finished in '1' seconds INFO: [USF-XSim-99] Step results log file:'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/xvlog.log' ERROR: [USF-XSim-62] 'compile' step failed with error(s). Please check the Tcl console output or 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/xvlog.log' file for more information. ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation. ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors. update_compile_order -fileset sources_1 launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'top' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj top_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer4.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Multiplexer4 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegMA.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegMA INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALUControl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALUControl INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegisterFile.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegisterFile INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegID.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegID INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegFI.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegFI INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ControlUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ProgramCounter.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ProgramCounter INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SignalExtension.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module SignalExtension INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ShiftUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ShiftUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module InstructionMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module DataMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALU2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALU2 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Add1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Add1 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module top INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl INFO: [USF-XSim-69] 'compile' step finished in '1' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' Vivado Simulator 2016.2 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: J:/Xilinx/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto 4c388791a4e240948a5554cd0b3617d7 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot top_behav xil_defaultlib.top xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration ERROR: [VRFC 10-2063] Module not found while processing module instance [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:128] ERROR: [VRFC 10-2063] Module not found while processing module instance [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:137] ERROR: [VRFC 10-2063] Module not found while processing module instance [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:140] ERROR: [VRFC 10-2063] Module not found while processing module instance [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:141] ERROR: [XSIM 43-3322] Static elaboration of top level Verilog design unit(s) in library work failed. INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds INFO: [USF-XSim-99] Step results log file:'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/elaborate.log' ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/elaborate.log' file for more information. ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation. ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors. update_compile_order -fileset sources_1 launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'top' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj top_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegEX.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegEX INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer4.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Multiplexer4 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegMA.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegMA INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALUControl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALUControl INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegisterFile.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegisterFile INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegID.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegID INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegFI.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegFI INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ControlUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ProgramCounter.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ProgramCounter INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SignalExtension.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module SignalExtension INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ShiftUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ShiftUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module InstructionMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module DataMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALU2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALU2 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Add1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Add1 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module top INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl INFO: [USF-XSim-69] 'compile' step finished in '1' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' Vivado Simulator 2016.2 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: J:/Xilinx/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto 4c388791a4e240948a5554cd0b3617d7 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot top_behav xil_defaultlib.top xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration WARNING: [VRFC 10-278] actual bit length 32 differs from formal bit length 5 for port addr [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:140] Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling module xil_defaultlib.ControlUnit Compiling module xil_defaultlib.ProgramCounter Compiling module xil_defaultlib.Add1 Compiling module xil_defaultlib.InstructionMemory Compiling module xil_defaultlib.RegFI Compiling module xil_defaultlib.RegisterFile Compiling module xil_defaultlib.SignalExtension Compiling module xil_defaultlib.RegID Compiling module xil_defaultlib.ALUControl Compiling module xil_defaultlib.ALU2 Compiling module xil_defaultlib.ShiftUnit Compiling module xil_defaultlib.RegEX Compiling module xil_defaultlib.Multiplexer4 Compiling module xil_defaultlib.DataMemory Compiling module xil_defaultlib.RegMA Compiling module xil_defaultlib.top Compiling module xil_defaultlib.glbl Built simulation snapshot top_behav ****** Webtalk v2016.2 (64-bit) **** SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016 **** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. source C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/xsim.dir/top_behav/webtalk/xsim_webtalk.tcl -notrace INFO: [Common 17-206] Exiting Webtalk at Mon Dec 24 22:04:32 2018... INFO: [USF-XSim-69] 'elaborate' step finished in '4' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' INFO: [USF-XSim-98] *** Running xsim with args "top_behav -key {Behavioral:sim_1:Functional:top} -tclbatch {top.tcl} -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature Vivado Simulator 2016.2 Time resolution is 1 ps source top.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns INFO: [USF-XSim-96] XSim completed. Design snapshot 'top_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:01 ; elapsed = 00:00:07 . Memory (MB): peak = 1396.879 ; gain = 0.000 close_sim INFO: [Simtcl 6-16] Simulation closed launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'top' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj top_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegEX.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegEX INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer4.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Multiplexer4 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegMA.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegMA INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALUControl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALUControl INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegisterFile.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegisterFile INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegID.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegID INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegFI.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegFI INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ControlUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ProgramCounter.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ProgramCounter INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SignalExtension.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module SignalExtension INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ShiftUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ShiftUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module InstructionMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module DataMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALU2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALU2 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Add1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Add1 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module top ERROR: [VRFC 10-46] opcode_3 is already declared [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:137] ERROR: [VRFC 10-1040] module top ignored due to previous errors [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:37] INFO: [USF-XSim-69] 'compile' step finished in '1' seconds INFO: [USF-XSim-99] Step results log file:'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/xvlog.log' ERROR: [USF-XSim-62] 'compile' step failed with error(s). Please check the Tcl console output or 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/xvlog.log' file for more information. ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation. ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors. launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'top' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj top_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegEX.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegEX INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer4.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Multiplexer4 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegMA.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegMA INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALUControl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALUControl INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegisterFile.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegisterFile INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegID.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegID INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegFI.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegFI INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ControlUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ProgramCounter.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ProgramCounter INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SignalExtension.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module SignalExtension INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ShiftUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ShiftUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module InstructionMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module DataMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALU2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALU2 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Add1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Add1 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module top INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl INFO: [USF-XSim-69] 'compile' step finished in '1' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' Vivado Simulator 2016.2 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: J:/Xilinx/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto 4c388791a4e240948a5554cd0b3617d7 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot top_behav xil_defaultlib.top xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration WARNING: [VRFC 10-278] actual bit length 32 differs from formal bit length 5 for port addr [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:142] Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling module xil_defaultlib.ControlUnit Compiling module xil_defaultlib.ProgramCounter Compiling module xil_defaultlib.Add1 Compiling module xil_defaultlib.InstructionMemory Compiling module xil_defaultlib.RegFI Compiling module xil_defaultlib.RegisterFile Compiling module xil_defaultlib.SignalExtension Compiling module xil_defaultlib.RegID Compiling module xil_defaultlib.ALUControl Compiling module xil_defaultlib.ALU2 Compiling module xil_defaultlib.ShiftUnit Compiling module xil_defaultlib.RegEX Compiling module xil_defaultlib.Multiplexer4 Compiling module xil_defaultlib.DataMemory Compiling module xil_defaultlib.RegMA Compiling module xil_defaultlib.top Compiling module xil_defaultlib.glbl Built simulation snapshot top_behav ****** Webtalk v2016.2 (64-bit) **** SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016 **** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. source C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/xsim.dir/top_behav/webtalk/xsim_webtalk.tcl -notrace INFO: [Common 17-206] Exiting Webtalk at Mon Dec 24 22:25:43 2018... INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' INFO: [USF-XSim-98] *** Running xsim with args "top_behav -key {Behavioral:sim_1:Functional:top} -tclbatch {top.tcl} -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature Vivado Simulator 2016.2 Time resolution is 1 ps source top.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns INFO: [USF-XSim-96] XSim completed. Design snapshot 'top_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:01 ; elapsed = 00:00:07 . Memory (MB): peak = 1404.559 ; gain = 0.000 close_sim INFO: [Simtcl 6-16] Simulation closed launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'top' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj top_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegEX.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegEX INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer4.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Multiplexer4 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegMA.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegMA INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALUControl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALUControl INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegisterFile.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegisterFile INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegID.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegID INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegFI.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegFI INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ControlUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ProgramCounter.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ProgramCounter INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SignalExtension.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module SignalExtension INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ShiftUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ShiftUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module InstructionMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module DataMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALU2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALU2 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Add1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Add1 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module top INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl INFO: [USF-XSim-69] 'compile' step finished in '1' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' Vivado Simulator 2016.2 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: J:/Xilinx/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto 4c388791a4e240948a5554cd0b3617d7 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot top_behav xil_defaultlib.top xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration WARNING: [VRFC 10-278] actual bit length 32 differs from formal bit length 5 for port addr [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:141] Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling module xil_defaultlib.ControlUnit Compiling module xil_defaultlib.ProgramCounter Compiling module xil_defaultlib.Add1 Compiling module xil_defaultlib.InstructionMemory Compiling module xil_defaultlib.RegFI Compiling module xil_defaultlib.RegisterFile Compiling module xil_defaultlib.SignalExtension Compiling module xil_defaultlib.RegID Compiling module xil_defaultlib.ALUControl Compiling module xil_defaultlib.ALU2 Compiling module xil_defaultlib.ShiftUnit Compiling module xil_defaultlib.RegEX Compiling module xil_defaultlib.Multiplexer4 Compiling module xil_defaultlib.DataMemory Compiling module xil_defaultlib.RegMA Compiling module xil_defaultlib.top Compiling module xil_defaultlib.glbl Built simulation snapshot top_behav ****** Webtalk v2016.2 (64-bit) **** SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016 **** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. source C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/xsim.dir/top_behav/webtalk/xsim_webtalk.tcl -notrace INFO: [Common 17-206] Exiting Webtalk at Mon Dec 24 22:31:45 2018... INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' INFO: [USF-XSim-98] *** Running xsim with args "top_behav -key {Behavioral:sim_1:Functional:top} -tclbatch {top.tcl} -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature Vivado Simulator 2016.2 Time resolution is 1 ps source top.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns INFO: [USF-XSim-96] XSim completed. Design snapshot 'top_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:02 ; elapsed = 00:00:08 . Memory (MB): peak = 1404.559 ; gain = 0.000 close_sim INFO: [Simtcl 6-16] Simulation closed launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'top' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj top_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegEX.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegEX INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer4.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Multiplexer4 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegMA.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegMA INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALUControl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALUControl INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegisterFile.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegisterFile INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegID.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegID INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegFI.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegFI INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ControlUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ProgramCounter.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ProgramCounter INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SignalExtension.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module SignalExtension INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ShiftUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ShiftUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module InstructionMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module DataMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALU2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALU2 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Add1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Add1 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module top INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl INFO: [USF-XSim-69] 'compile' step finished in '1' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' Vivado Simulator 2016.2 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: J:/Xilinx/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto 4c388791a4e240948a5554cd0b3617d7 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot top_behav xil_defaultlib.top xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration WARNING: [VRFC 10-278] actual bit length 32 differs from formal bit length 5 for port addr [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:141] Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling module xil_defaultlib.ControlUnit Compiling module xil_defaultlib.ProgramCounter Compiling module xil_defaultlib.Add1 Compiling module xil_defaultlib.InstructionMemory Compiling module xil_defaultlib.RegFI Compiling module xil_defaultlib.RegisterFile Compiling module xil_defaultlib.SignalExtension Compiling module xil_defaultlib.RegID Compiling module xil_defaultlib.ALUControl Compiling module xil_defaultlib.ALU2 Compiling module xil_defaultlib.ShiftUnit Compiling module xil_defaultlib.RegEX Compiling module xil_defaultlib.Multiplexer4 Compiling module xil_defaultlib.DataMemory Compiling module xil_defaultlib.RegMA Compiling module xil_defaultlib.top Compiling module xil_defaultlib.glbl Built simulation snapshot top_behav ****** Webtalk v2016.2 (64-bit) **** SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016 **** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. source C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/xsim.dir/top_behav/webtalk/xsim_webtalk.tcl -notrace INFO: [Common 17-206] Exiting Webtalk at Mon Dec 24 22:40:06 2018... INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' INFO: [USF-XSim-98] *** Running xsim with args "top_behav -key {Behavioral:sim_1:Functional:top} -tclbatch {top.tcl} -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature Vivado Simulator 2016.2 Time resolution is 1 ps source top.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns INFO: [USF-XSim-96] XSim completed. Design snapshot 'top_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:02 ; elapsed = 00:00:08 . Memory (MB): peak = 1404.559 ; gain = 0.000 close_sim INFO: [Simtcl 6-16] Simulation closed launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'top' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj top_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegEX.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegEX INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer4.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Multiplexer4 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegMA.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegMA INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALUControl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALUControl INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegisterFile.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegisterFile INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegID.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegID INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegFI.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegFI INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ControlUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ProgramCounter.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ProgramCounter INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SignalExtension.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module SignalExtension INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ShiftUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ShiftUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module InstructionMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module DataMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALU2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALU2 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Add1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Add1 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module top INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl INFO: [USF-XSim-69] 'compile' step finished in '1' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' Vivado Simulator 2016.2 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: J:/Xilinx/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto 4c388791a4e240948a5554cd0b3617d7 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot top_behav xil_defaultlib.top xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration WARNING: [VRFC 10-278] actual bit length 32 differs from formal bit length 5 for port addr [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:141] Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling module xil_defaultlib.ControlUnit Compiling module xil_defaultlib.ProgramCounter Compiling module xil_defaultlib.Add1 Compiling module xil_defaultlib.InstructionMemory Compiling module xil_defaultlib.RegFI Compiling module xil_defaultlib.RegisterFile Compiling module xil_defaultlib.SignalExtension Compiling module xil_defaultlib.RegID Compiling module xil_defaultlib.ALUControl Compiling module xil_defaultlib.ALU2 Compiling module xil_defaultlib.ShiftUnit Compiling module xil_defaultlib.RegEX Compiling module xil_defaultlib.Multiplexer4 Compiling module xil_defaultlib.DataMemory Compiling module xil_defaultlib.RegMA Compiling module xil_defaultlib.top Compiling module xil_defaultlib.glbl Built simulation snapshot top_behav ****** Webtalk v2016.2 (64-bit) **** SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016 **** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. source C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/xsim.dir/top_behav/webtalk/xsim_webtalk.tcl -notrace INFO: [Common 17-206] Exiting Webtalk at Mon Dec 24 22:40:56 2018... INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' INFO: [USF-XSim-98] *** Running xsim with args "top_behav -key {Behavioral:sim_1:Functional:top} -tclbatch {top.tcl} -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature Vivado Simulator 2016.2 Time resolution is 1 ps source top.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns INFO: [USF-XSim-96] XSim completed. Design snapshot 'top_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:02 ; elapsed = 00:00:08 . Memory (MB): peak = 1404.559 ; gain = 0.000 close_sim INFO: [Simtcl 6-16] Simulation closed launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'top' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj top_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegEX.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegEX INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer4.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Multiplexer4 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegMA.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegMA INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALUControl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALUControl INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegisterFile.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegisterFile INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegID.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegID INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegFI.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegFI INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ControlUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ProgramCounter.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ProgramCounter INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SignalExtension.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module SignalExtension INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ShiftUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ShiftUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module InstructionMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module DataMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALU2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALU2 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Add1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Add1 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module top INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl INFO: [USF-XSim-69] 'compile' step finished in '1' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' Vivado Simulator 2016.2 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: J:/Xilinx/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto 4c388791a4e240948a5554cd0b3617d7 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot top_behav xil_defaultlib.top xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration WARNING: [VRFC 10-278] actual bit length 32 differs from formal bit length 5 for port addr [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:141] Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling module xil_defaultlib.ControlUnit Compiling module xil_defaultlib.ProgramCounter Compiling module xil_defaultlib.Add1 Compiling module xil_defaultlib.InstructionMemory Compiling module xil_defaultlib.RegFI Compiling module xil_defaultlib.RegisterFile Compiling module xil_defaultlib.SignalExtension Compiling module xil_defaultlib.RegID Compiling module xil_defaultlib.ALUControl Compiling module xil_defaultlib.ALU2 Compiling module xil_defaultlib.ShiftUnit Compiling module xil_defaultlib.RegEX Compiling module xil_defaultlib.Multiplexer4 Compiling module xil_defaultlib.DataMemory Compiling module xil_defaultlib.RegMA Compiling module xil_defaultlib.top Compiling module xil_defaultlib.glbl Built simulation snapshot top_behav ****** Webtalk v2016.2 (64-bit) **** SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016 **** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. source C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/xsim.dir/top_behav/webtalk/xsim_webtalk.tcl -notrace INFO: [Common 17-206] Exiting Webtalk at Mon Dec 24 22:42:09 2018... INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' INFO: [USF-XSim-98] *** Running xsim with args "top_behav -key {Behavioral:sim_1:Functional:top} -tclbatch {top.tcl} -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature Vivado Simulator 2016.2 Time resolution is 1 ps source top.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns INFO: [USF-XSim-96] XSim completed. Design snapshot 'top_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:02 ; elapsed = 00:00:08 . Memory (MB): peak = 1404.559 ; gain = 0.000 close_sim INFO: [Simtcl 6-16] Simulation closed launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'top' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj top_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegEX.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegEX INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer4.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Multiplexer4 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegMA.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegMA INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALUControl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALUControl INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegisterFile.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegisterFile INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegID.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegID INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegFI.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegFI INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ControlUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ProgramCounter.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ProgramCounter INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SignalExtension.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module SignalExtension INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ShiftUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ShiftUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module InstructionMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module DataMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALU2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALU2 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Add1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Add1 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module top INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl INFO: [USF-XSim-69] 'compile' step finished in '1' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' Vivado Simulator 2016.2 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: J:/Xilinx/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto 4c388791a4e240948a5554cd0b3617d7 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot top_behav xil_defaultlib.top xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration WARNING: [VRFC 10-278] actual bit length 32 differs from formal bit length 5 for port addr [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:141] Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling module xil_defaultlib.ControlUnit Compiling module xil_defaultlib.ProgramCounter Compiling module xil_defaultlib.Add1 Compiling module xil_defaultlib.InstructionMemory Compiling module xil_defaultlib.RegFI Compiling module xil_defaultlib.RegisterFile Compiling module xil_defaultlib.SignalExtension Compiling module xil_defaultlib.RegID Compiling module xil_defaultlib.ALUControl Compiling module xil_defaultlib.ALU2 Compiling module xil_defaultlib.ShiftUnit Compiling module xil_defaultlib.RegEX Compiling module xil_defaultlib.Multiplexer4 Compiling module xil_defaultlib.DataMemory Compiling module xil_defaultlib.RegMA Compiling module xil_defaultlib.top Compiling module xil_defaultlib.glbl Built simulation snapshot top_behav ****** Webtalk v2016.2 (64-bit) **** SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016 **** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. source C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/xsim.dir/top_behav/webtalk/xsim_webtalk.tcl -notrace INFO: [Common 17-206] Exiting Webtalk at Mon Dec 24 22:55:13 2018... INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' INFO: [USF-XSim-98] *** Running xsim with args "top_behav -key {Behavioral:sim_1:Functional:top} -tclbatch {top.tcl} -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature Vivado Simulator 2016.2 Time resolution is 1 ps source top.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns INFO: [USF-XSim-96] XSim completed. Design snapshot 'top_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:03 ; elapsed = 00:00:08 . Memory (MB): peak = 1404.559 ; gain = 0.000 close_sim INFO: [Simtcl 6-16] Simulation closed launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'top' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj top_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegEX.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegEX INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer4.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Multiplexer4 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegMA.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegMA INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALUControl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALUControl INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegisterFile.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegisterFile INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegID.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegID INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegFI.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegFI INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ControlUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ProgramCounter.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ProgramCounter INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SignalExtension.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module SignalExtension INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ShiftUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ShiftUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module InstructionMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module DataMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALU2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALU2 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Add1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Add1 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module top INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl INFO: [USF-XSim-69] 'compile' step finished in '1' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' Vivado Simulator 2016.2 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: J:/Xilinx/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto 4c388791a4e240948a5554cd0b3617d7 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot top_behav xil_defaultlib.top xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration WARNING: [VRFC 10-278] actual bit length 32 differs from formal bit length 5 for port addr [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:142] Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling module xil_defaultlib.ControlUnit Compiling module xil_defaultlib.ProgramCounter Compiling module xil_defaultlib.Add1 Compiling module xil_defaultlib.InstructionMemory Compiling module xil_defaultlib.RegFI Compiling module xil_defaultlib.RegisterFile Compiling module xil_defaultlib.SignalExtension Compiling module xil_defaultlib.RegID Compiling module xil_defaultlib.ALUControl Compiling module xil_defaultlib.ALU2 Compiling module xil_defaultlib.ShiftUnit Compiling module xil_defaultlib.RegEX Compiling module xil_defaultlib.Multiplexer4 Compiling module xil_defaultlib.DataMemory Compiling module xil_defaultlib.RegMA Compiling module xil_defaultlib.top Compiling module xil_defaultlib.glbl Built simulation snapshot top_behav ****** Webtalk v2016.2 (64-bit) **** SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016 **** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. source C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/xsim.dir/top_behav/webtalk/xsim_webtalk.tcl -notrace INFO: [Common 17-206] Exiting Webtalk at Mon Dec 24 23:02:23 2018... INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' INFO: [USF-XSim-98] *** Running xsim with args "top_behav -key {Behavioral:sim_1:Functional:top} -tclbatch {top.tcl} -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature Vivado Simulator 2016.2 Time resolution is 1 ps source top.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns INFO: [USF-XSim-96] XSim completed. Design snapshot 'top_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:03 ; elapsed = 00:00:08 . Memory (MB): peak = 1404.559 ; gain = 0.000 close_sim INFO: [Simtcl 6-16] Simulation closed launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'top' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj top_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegEX.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegEX INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer4.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Multiplexer4 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegMA.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegMA INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALUControl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALUControl INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegisterFile.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegisterFile INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegID.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegID INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegFI.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegFI INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ControlUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ProgramCounter.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ProgramCounter INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SignalExtension.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module SignalExtension INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ShiftUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ShiftUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module InstructionMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module DataMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALU2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALU2 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Add1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Add1 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module top INFO: [VRFC 10-2458] undeclared symbol pci, assumed default net type wire [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:88] INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl INFO: [USF-XSim-69] 'compile' step finished in '1' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' Vivado Simulator 2016.2 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: J:/Xilinx/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto 4c388791a4e240948a5554cd0b3617d7 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot top_behav xil_defaultlib.top xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration WARNING: [VRFC 10-278] actual bit length 1 differs from formal bit length 32 for port addrin [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:88] WARNING: [VRFC 10-278] actual bit length 32 differs from formal bit length 5 for port addr [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:141] Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling module xil_defaultlib.ControlUnit Compiling module xil_defaultlib.ProgramCounter Compiling module xil_defaultlib.Add1 Compiling module xil_defaultlib.InstructionMemory Compiling module xil_defaultlib.RegFI Compiling module xil_defaultlib.RegisterFile Compiling module xil_defaultlib.SignalExtension Compiling module xil_defaultlib.RegID Compiling module xil_defaultlib.ALUControl Compiling module xil_defaultlib.ALU2 Compiling module xil_defaultlib.ShiftUnit Compiling module xil_defaultlib.RegEX Compiling module xil_defaultlib.Multiplexer4 Compiling module xil_defaultlib.DataMemory Compiling module xil_defaultlib.RegMA Compiling module xil_defaultlib.top Compiling module xil_defaultlib.glbl Built simulation snapshot top_behav ****** Webtalk v2016.2 (64-bit) **** SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016 **** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. source C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/xsim.dir/top_behav/webtalk/xsim_webtalk.tcl -notrace INFO: [Common 17-206] Exiting Webtalk at Mon Dec 24 23:07:34 2018... INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' INFO: [USF-XSim-98] *** Running xsim with args "top_behav -key {Behavioral:sim_1:Functional:top} -tclbatch {top.tcl} -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature Vivado Simulator 2016.2 Time resolution is 1 ps source top.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns INFO: [USF-XSim-96] XSim completed. Design snapshot 'top_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:02 ; elapsed = 00:00:08 . Memory (MB): peak = 1404.559 ; gain = 0.000 close_sim INFO: [Simtcl 6-16] Simulation closed launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'top' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj top_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegEX.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegEX INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer4.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Multiplexer4 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegMA.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegMA INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALUControl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALUControl INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegisterFile.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegisterFile INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegID.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegID INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegFI.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegFI INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ControlUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ProgramCounter.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ProgramCounter INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SignalExtension.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module SignalExtension INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ShiftUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ShiftUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module InstructionMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module DataMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALU2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALU2 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Add1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Add1 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module top INFO: [VRFC 10-2458] undeclared symbol pci, assumed default net type wire [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:88] INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl INFO: [USF-XSim-69] 'compile' step finished in '1' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' Vivado Simulator 2016.2 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: J:/Xilinx/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto 4c388791a4e240948a5554cd0b3617d7 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot top_behav xil_defaultlib.top xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration WARNING: [VRFC 10-278] actual bit length 1 differs from formal bit length 32 for port addrin [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:88] WARNING: [VRFC 10-278] actual bit length 32 differs from formal bit length 5 for port addr [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:141] Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling module xil_defaultlib.ControlUnit Compiling module xil_defaultlib.ProgramCounter Compiling module xil_defaultlib.Add1 Compiling module xil_defaultlib.InstructionMemory Compiling module xil_defaultlib.RegFI Compiling module xil_defaultlib.RegisterFile Compiling module xil_defaultlib.SignalExtension Compiling module xil_defaultlib.RegID Compiling module xil_defaultlib.ALUControl Compiling module xil_defaultlib.ALU2 Compiling module xil_defaultlib.ShiftUnit Compiling module xil_defaultlib.RegEX Compiling module xil_defaultlib.Multiplexer4 Compiling module xil_defaultlib.DataMemory Compiling module xil_defaultlib.RegMA Compiling module xil_defaultlib.top Compiling module xil_defaultlib.glbl Built simulation snapshot top_behav ****** Webtalk v2016.2 (64-bit) **** SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016 **** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. source C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/xsim.dir/top_behav/webtalk/xsim_webtalk.tcl -notrace INFO: [Common 17-206] Exiting Webtalk at Mon Dec 24 23:08:21 2018... INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' INFO: [USF-XSim-98] *** Running xsim with args "top_behav -key {Behavioral:sim_1:Functional:top} -tclbatch {top.tcl} -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature Vivado Simulator 2016.2 Time resolution is 1 ps source top.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns INFO: [USF-XSim-96] XSim completed. Design snapshot 'top_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:02 ; elapsed = 00:00:08 . Memory (MB): peak = 1404.559 ; gain = 0.000 close_sim INFO: [Simtcl 6-16] Simulation closed launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'top' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj top_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegEX.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegEX INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer4.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Multiplexer4 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegMA.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegMA INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALUControl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALUControl INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegisterFile.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegisterFile INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegID.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegID INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegFI.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegFI INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ControlUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ProgramCounter.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ProgramCounter INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SignalExtension.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module SignalExtension INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ShiftUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ShiftUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module InstructionMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module DataMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALU2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALU2 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Add1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Add1 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module top INFO: [VRFC 10-2458] undeclared symbol pci, assumed default net type wire [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:88] INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl INFO: [USF-XSim-69] 'compile' step finished in '1' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' Vivado Simulator 2016.2 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: J:/Xilinx/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto 4c388791a4e240948a5554cd0b3617d7 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot top_behav xil_defaultlib.top xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration WARNING: [VRFC 10-278] actual bit length 1 differs from formal bit length 32 for port addrin [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:88] WARNING: [VRFC 10-278] actual bit length 32 differs from formal bit length 5 for port addr [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:141] Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling module xil_defaultlib.ControlUnit Compiling module xil_defaultlib.ProgramCounter Compiling module xil_defaultlib.Add1 Compiling module xil_defaultlib.InstructionMemory Compiling module xil_defaultlib.RegFI Compiling module xil_defaultlib.RegisterFile Compiling module xil_defaultlib.SignalExtension Compiling module xil_defaultlib.RegID Compiling module xil_defaultlib.ALUControl Compiling module xil_defaultlib.ALU2 Compiling module xil_defaultlib.ShiftUnit Compiling module xil_defaultlib.RegEX Compiling module xil_defaultlib.Multiplexer4 Compiling module xil_defaultlib.DataMemory Compiling module xil_defaultlib.RegMA Compiling module xil_defaultlib.top Compiling module xil_defaultlib.glbl Built simulation snapshot top_behav ****** Webtalk v2016.2 (64-bit) **** SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016 **** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. source C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/xsim.dir/top_behav/webtalk/xsim_webtalk.tcl -notrace INFO: [Common 17-206] Exiting Webtalk at Mon Dec 24 23:10:11 2018... INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' INFO: [USF-XSim-98] *** Running xsim with args "top_behav -key {Behavioral:sim_1:Functional:top} -tclbatch {top.tcl} -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature Vivado Simulator 2016.2 Time resolution is 1 ps source top.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns INFO: [USF-XSim-96] XSim completed. Design snapshot 'top_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:03 ; elapsed = 00:00:08 . Memory (MB): peak = 1404.559 ; gain = 0.000 close_sim INFO: [Simtcl 6-16] Simulation closed launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'top' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj top_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegEX.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegEX INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer4.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Multiplexer4 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegMA.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegMA INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALUControl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALUControl INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegisterFile.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegisterFile INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegID.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegID INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegFI.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegFI INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ControlUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ProgramCounter.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ProgramCounter INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SignalExtension.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module SignalExtension INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ShiftUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ShiftUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module InstructionMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module DataMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALU2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALU2 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Add1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Add1 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module top INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl INFO: [USF-XSim-69] 'compile' step finished in '1' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' Vivado Simulator 2016.2 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: J:/Xilinx/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto 4c388791a4e240948a5554cd0b3617d7 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot top_behav xil_defaultlib.top xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration WARNING: [VRFC 10-278] actual bit length 32 differs from formal bit length 5 for port addr [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:143] Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling module xil_defaultlib.ControlUnit Compiling module xil_defaultlib.ProgramCounter Compiling module xil_defaultlib.Add1 Compiling module xil_defaultlib.InstructionMemory Compiling module xil_defaultlib.RegFI Compiling module xil_defaultlib.RegisterFile Compiling module xil_defaultlib.SignalExtension Compiling module xil_defaultlib.RegID Compiling module xil_defaultlib.ALUControl Compiling module xil_defaultlib.ALU2 Compiling module xil_defaultlib.ShiftUnit Compiling module xil_defaultlib.RegEX Compiling module xil_defaultlib.Multiplexer4 Compiling module xil_defaultlib.DataMemory Compiling module xil_defaultlib.RegMA Compiling module xil_defaultlib.top Compiling module xil_defaultlib.glbl Built simulation snapshot top_behav ****** Webtalk v2016.2 (64-bit) **** SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016 **** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. source C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/xsim.dir/top_behav/webtalk/xsim_webtalk.tcl -notrace INFO: [Common 17-206] Exiting Webtalk at Mon Dec 24 23:11:14 2018... INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' INFO: [USF-XSim-98] *** Running xsim with args "top_behav -key {Behavioral:sim_1:Functional:top} -tclbatch {top.tcl} -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature Vivado Simulator 2016.2 Time resolution is 1 ps source top.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns INFO: [USF-XSim-96] XSim completed. Design snapshot 'top_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:02 ; elapsed = 00:00:08 . Memory (MB): peak = 1404.559 ; gain = 0.000 close_sim INFO: [Simtcl 6-16] Simulation closed launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'top' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj top_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegEX.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegEX INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer4.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Multiplexer4 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegMA.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegMA INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALUControl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALUControl INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegisterFile.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegisterFile INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegID.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegID INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegFI.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegFI INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ControlUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ProgramCounter.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ProgramCounter INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SignalExtension.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module SignalExtension INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ShiftUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ShiftUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module InstructionMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module DataMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALU2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALU2 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Add1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Add1 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module top INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl INFO: [USF-XSim-69] 'compile' step finished in '1' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' Vivado Simulator 2016.2 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: J:/Xilinx/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto 4c388791a4e240948a5554cd0b3617d7 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot top_behav xil_defaultlib.top xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration WARNING: [VRFC 10-278] actual bit length 32 differs from formal bit length 5 for port addr [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:143] Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling module xil_defaultlib.ControlUnit Compiling module xil_defaultlib.ProgramCounter Compiling module xil_defaultlib.Add1 Compiling module xil_defaultlib.InstructionMemory Compiling module xil_defaultlib.RegFI Compiling module xil_defaultlib.RegisterFile Compiling module xil_defaultlib.SignalExtension Compiling module xil_defaultlib.RegID Compiling module xil_defaultlib.ALUControl Compiling module xil_defaultlib.ALU2 Compiling module xil_defaultlib.ShiftUnit Compiling module xil_defaultlib.RegEX Compiling module xil_defaultlib.Multiplexer4 Compiling module xil_defaultlib.DataMemory Compiling module xil_defaultlib.RegMA Compiling module xil_defaultlib.top Compiling module xil_defaultlib.glbl Built simulation snapshot top_behav ****** Webtalk v2016.2 (64-bit) **** SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016 **** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. source C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/xsim.dir/top_behav/webtalk/xsim_webtalk.tcl -notrace INFO: [Common 17-206] Exiting Webtalk at Mon Dec 24 23:15:17 2018... INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' INFO: [USF-XSim-98] *** Running xsim with args "top_behav -key {Behavioral:sim_1:Functional:top} -tclbatch {top.tcl} -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature Vivado Simulator 2016.2 Time resolution is 1 ps source top.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns INFO: [USF-XSim-96] XSim completed. Design snapshot 'top_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:03 ; elapsed = 00:00:08 . Memory (MB): peak = 1404.559 ; gain = 0.000 close_sim INFO: [Simtcl 6-16] Simulation closed launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'top' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj top_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegEX.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegEX INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer4.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Multiplexer4 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegMA.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegMA INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALUControl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALUControl INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegisterFile.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegisterFile INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegID.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegID INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegFI.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegFI INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ControlUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ProgramCounter.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ProgramCounter INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SignalExtension.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module SignalExtension INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ShiftUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ShiftUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module InstructionMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module DataMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALU2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALU2 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Add1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Add1 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module top INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl INFO: [USF-XSim-69] 'compile' step finished in '1' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' Vivado Simulator 2016.2 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: J:/Xilinx/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto 4c388791a4e240948a5554cd0b3617d7 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot top_behav xil_defaultlib.top xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration WARNING: [VRFC 10-278] actual bit length 32 differs from formal bit length 5 for port addr [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:143] Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling module xil_defaultlib.ControlUnit Compiling module xil_defaultlib.ProgramCounter Compiling module xil_defaultlib.Add1 Compiling module xil_defaultlib.InstructionMemory Compiling module xil_defaultlib.RegFI Compiling module xil_defaultlib.RegisterFile Compiling module xil_defaultlib.SignalExtension Compiling module xil_defaultlib.RegID Compiling module xil_defaultlib.ALUControl Compiling module xil_defaultlib.ALU2 Compiling module xil_defaultlib.ShiftUnit Compiling module xil_defaultlib.RegEX Compiling module xil_defaultlib.Multiplexer4 Compiling module xil_defaultlib.DataMemory Compiling module xil_defaultlib.RegMA Compiling module xil_defaultlib.top Compiling module xil_defaultlib.glbl Built simulation snapshot top_behav ****** Webtalk v2016.2 (64-bit) **** SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016 **** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. source C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/xsim.dir/top_behav/webtalk/xsim_webtalk.tcl -notrace INFO: [Common 17-206] Exiting Webtalk at Mon Dec 24 23:16:01 2018... INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' INFO: [USF-XSim-98] *** Running xsim with args "top_behav -key {Behavioral:sim_1:Functional:top} -tclbatch {top.tcl} -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature Vivado Simulator 2016.2 Time resolution is 1 ps source top.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns INFO: [USF-XSim-96] XSim completed. Design snapshot 'top_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:03 ; elapsed = 00:00:08 . Memory (MB): peak = 1404.559 ; gain = 0.000 close_sim INFO: [Simtcl 6-16] Simulation closed launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'top' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj top_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegEX.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegEX INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer4.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Multiplexer4 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegMA.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegMA INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALUControl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALUControl INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegisterFile.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegisterFile INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegID.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegID INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegFI.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegFI INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ControlUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ProgramCounter.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ProgramCounter INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SignalExtension.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module SignalExtension INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ShiftUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ShiftUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module InstructionMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module DataMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALU2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALU2 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Add1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Add1 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module top INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl INFO: [USF-XSim-69] 'compile' step finished in '2' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' Vivado Simulator 2016.2 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: J:/Xilinx/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto 4c388791a4e240948a5554cd0b3617d7 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot top_behav xil_defaultlib.top xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration WARNING: [VRFC 10-278] actual bit length 32 differs from formal bit length 5 for port addr [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:143] Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling module xil_defaultlib.ControlUnit Compiling module xil_defaultlib.ProgramCounter Compiling module xil_defaultlib.Add1 Compiling module xil_defaultlib.InstructionMemory Compiling module xil_defaultlib.RegFI Compiling module xil_defaultlib.RegisterFile Compiling module xil_defaultlib.SignalExtension Compiling module xil_defaultlib.RegID Compiling module xil_defaultlib.ALUControl Compiling module xil_defaultlib.ALU2 Compiling module xil_defaultlib.ShiftUnit Compiling module xil_defaultlib.RegEX Compiling module xil_defaultlib.Multiplexer4 Compiling module xil_defaultlib.DataMemory Compiling module xil_defaultlib.RegMA Compiling module xil_defaultlib.top Compiling module xil_defaultlib.glbl Built simulation snapshot top_behav ****** Webtalk v2016.2 (64-bit) **** SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016 **** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. source C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/xsim.dir/top_behav/webtalk/xsim_webtalk.tcl -notrace INFO: [Common 17-206] Exiting Webtalk at Mon Dec 24 23:23:53 2018... INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' INFO: [USF-XSim-98] *** Running xsim with args "top_behav -key {Behavioral:sim_1:Functional:top} -tclbatch {top.tcl} -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature Vivado Simulator 2016.2 Time resolution is 1 ps source top.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns INFO: [USF-XSim-96] XSim completed. Design snapshot 'top_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:02 ; elapsed = 00:00:08 . Memory (MB): peak = 1410.078 ; gain = 0.000 close_sim INFO: [Simtcl 6-16] Simulation closed close_sim: Time (s): cpu = 00:00:00 ; elapsed = 00:00:05 . Memory (MB): peak = 1410.078 ; gain = 0.000 launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'top' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj top_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegEX.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegEX INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer4.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Multiplexer4 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegMA.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegMA INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALUControl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALUControl INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegisterFile.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegisterFile INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegID.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegID INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegFI.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegFI INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ControlUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ProgramCounter.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ProgramCounter INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SignalExtension.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module SignalExtension INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ShiftUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ShiftUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module InstructionMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module DataMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALU2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALU2 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Add1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Add1 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module top INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl INFO: [USF-XSim-69] 'compile' step finished in '2' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' Vivado Simulator 2016.2 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: J:/Xilinx/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto 4c388791a4e240948a5554cd0b3617d7 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot top_behav xil_defaultlib.top xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration WARNING: [VRFC 10-278] actual bit length 32 differs from formal bit length 5 for port addr [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:143] Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling module xil_defaultlib.ControlUnit Compiling module xil_defaultlib.ProgramCounter Compiling module xil_defaultlib.Add1 Compiling module xil_defaultlib.InstructionMemory Compiling module xil_defaultlib.RegFI Compiling module xil_defaultlib.RegisterFile Compiling module xil_defaultlib.SignalExtension Compiling module xil_defaultlib.RegID Compiling module xil_defaultlib.ALUControl Compiling module xil_defaultlib.ALU2 Compiling module xil_defaultlib.ShiftUnit Compiling module xil_defaultlib.RegEX Compiling module xil_defaultlib.Multiplexer4 Compiling module xil_defaultlib.DataMemory Compiling module xil_defaultlib.RegMA Compiling module xil_defaultlib.top Compiling module xil_defaultlib.glbl Built simulation snapshot top_behav ****** Webtalk v2016.2 (64-bit) **** SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016 **** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. source C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/xsim.dir/top_behav/webtalk/xsim_webtalk.tcl -notrace INFO: [Common 17-206] Exiting Webtalk at Mon Dec 24 23:41:06 2018... run_program: Time (s): cpu = 00:00:00 ; elapsed = 00:00:06 . Memory (MB): peak = 1410.078 ; gain = 0.000 INFO: [USF-XSim-69] 'elaborate' step finished in '6' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' INFO: [USF-XSim-98] *** Running xsim with args "top_behav -key {Behavioral:sim_1:Functional:top} -tclbatch {top.tcl} -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature Vivado Simulator 2016.2 Time resolution is 1 ps source top.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns xsim: Time (s): cpu = 00:00:04 ; elapsed = 00:00:07 . Memory (MB): peak = 1410.078 ; gain = 0.000 INFO: [USF-XSim-96] XSim completed. Design snapshot 'top_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:06 ; elapsed = 00:00:16 . Memory (MB): peak = 1410.078 ; gain = 0.000 update_compile_order -fileset sources_1 close_sim INFO: [Simtcl 6-16] Simulation closed close_sim: Time (s): cpu = 00:00:00 ; elapsed = 00:00:05 . Memory (MB): peak = 1410.078 ; gain = 0.000 launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'top' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj top_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Multiplexer INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegEX.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegEX INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer4.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Multiplexer4 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegMA.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegMA INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALUControl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALUControl INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegisterFile.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegisterFile INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegID.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegID INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegFI.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegFI INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ControlUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ProgramCounter.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ProgramCounter INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SignalExtension.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module SignalExtension INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ShiftUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ShiftUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module InstructionMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module DataMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALU2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALU2 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Add1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Add1 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module top INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl INFO: [USF-XSim-69] 'compile' step finished in '2' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' Vivado Simulator 2016.2 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: J:/Xilinx/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto 4c388791a4e240948a5554cd0b3617d7 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot top_behav xil_defaultlib.top xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration WARNING: [VRFC 10-278] actual bit length 32 differs from formal bit length 5 for port addr [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:144] Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling module xil_defaultlib.ControlUnit Compiling module xil_defaultlib.ProgramCounter Compiling module xil_defaultlib.Add1 Compiling module xil_defaultlib.InstructionMemory Compiling module xil_defaultlib.RegFI Compiling module xil_defaultlib.RegisterFile Compiling module xil_defaultlib.SignalExtension Compiling module xil_defaultlib.RegID Compiling module xil_defaultlib.ALUControl Compiling module xil_defaultlib.ALU2 Compiling module xil_defaultlib.ShiftUnit Compiling module xil_defaultlib.RegEX Compiling module xil_defaultlib.Multiplexer4 Compiling module xil_defaultlib.Multiplexer Compiling module xil_defaultlib.DataMemory Compiling module xil_defaultlib.RegMA Compiling module xil_defaultlib.top Compiling module xil_defaultlib.glbl Built simulation snapshot top_behav ****** Webtalk v2016.2 (64-bit) **** SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016 **** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. source C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/xsim.dir/top_behav/webtalk/xsim_webtalk.tcl -notrace INFO: [Common 17-206] Exiting Webtalk at Mon Dec 24 23:46:18 2018... run_program: Time (s): cpu = 00:00:00 ; elapsed = 00:00:06 . Memory (MB): peak = 1410.078 ; gain = 0.000 INFO: [USF-XSim-69] 'elaborate' step finished in '6' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' INFO: [USF-XSim-98] *** Running xsim with args "top_behav -key {Behavioral:sim_1:Functional:top} -tclbatch {top.tcl} -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature Vivado Simulator 2016.2 Time resolution is 1 ps source top.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns INFO: [USF-XSim-96] XSim completed. Design snapshot 'top_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:04 ; elapsed = 00:00:14 . Memory (MB): peak = 1410.078 ; gain = 0.000 close_sim INFO: [Simtcl 6-16] Simulation closed close_sim: Time (s): cpu = 00:00:00 ; elapsed = 00:00:05 . Memory (MB): peak = 1410.078 ; gain = 0.000 launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'top' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj top_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Multiplexer INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegEX.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegEX INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer4.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Multiplexer4 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegMA.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegMA INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALUControl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALUControl INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegisterFile.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegisterFile INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegID.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegID INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegFI.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegFI INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ControlUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ProgramCounter.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ProgramCounter INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SignalExtension.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module SignalExtension INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ShiftUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ShiftUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module InstructionMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module DataMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALU2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALU2 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Add1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Add1 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module top INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl INFO: [USF-XSim-69] 'compile' step finished in '2' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' Vivado Simulator 2016.2 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: J:/Xilinx/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto 4c388791a4e240948a5554cd0b3617d7 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot top_behav xil_defaultlib.top xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration WARNING: [VRFC 10-278] actual bit length 32 differs from formal bit length 5 for port addr [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:144] Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling module xil_defaultlib.ControlUnit Compiling module xil_defaultlib.ProgramCounter Compiling module xil_defaultlib.Add1 Compiling module xil_defaultlib.InstructionMemory Compiling module xil_defaultlib.RegFI Compiling module xil_defaultlib.RegisterFile Compiling module xil_defaultlib.SignalExtension Compiling module xil_defaultlib.RegID Compiling module xil_defaultlib.ALUControl Compiling module xil_defaultlib.ALU2 Compiling module xil_defaultlib.ShiftUnit Compiling module xil_defaultlib.RegEX Compiling module xil_defaultlib.Multiplexer4 Compiling module xil_defaultlib.Multiplexer Compiling module xil_defaultlib.DataMemory Compiling module xil_defaultlib.RegMA Compiling module xil_defaultlib.top Compiling module xil_defaultlib.glbl Built simulation snapshot top_behav ****** Webtalk v2016.2 (64-bit) **** SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016 **** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. source C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/xsim.dir/top_behav/webtalk/xsim_webtalk.tcl -notrace INFO: [Common 17-206] Exiting Webtalk at Mon Dec 24 23:49:12 2018... run_program: Time (s): cpu = 00:00:00 ; elapsed = 00:00:06 . Memory (MB): peak = 1410.078 ; gain = 0.000 INFO: [USF-XSim-69] 'elaborate' step finished in '6' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' INFO: [USF-XSim-98] *** Running xsim with args "top_behav -key {Behavioral:sim_1:Functional:top} -tclbatch {top.tcl} -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature Vivado Simulator 2016.2 Time resolution is 1 ps source top.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns INFO: [USF-XSim-96] XSim completed. Design snapshot 'top_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:04 ; elapsed = 00:00:14 . Memory (MB): peak = 1410.078 ; gain = 0.000 close_sim INFO: [Simtcl 6-16] Simulation closed close_sim: Time (s): cpu = 00:00:00 ; elapsed = 00:00:05 . Memory (MB): peak = 1410.078 ; gain = 0.000 launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'top' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj top_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Multiplexer INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegEX.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegEX INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer4.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Multiplexer4 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegMA.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegMA INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALUControl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALUControl INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegisterFile.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegisterFile INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegID.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegID INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegFI.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegFI INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ControlUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ProgramCounter.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ProgramCounter INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SignalExtension.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module SignalExtension INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ShiftUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ShiftUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module InstructionMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module DataMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALU2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALU2 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Add1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Add1 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module top INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl INFO: [USF-XSim-69] 'compile' step finished in '3' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' Vivado Simulator 2016.2 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: J:/Xilinx/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto 4c388791a4e240948a5554cd0b3617d7 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot top_behav xil_defaultlib.top xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration WARNING: [VRFC 10-278] actual bit length 32 differs from formal bit length 5 for port addr [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:144] Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling module xil_defaultlib.ControlUnit Compiling module xil_defaultlib.ProgramCounter Compiling module xil_defaultlib.Add1 Compiling module xil_defaultlib.InstructionMemory Compiling module xil_defaultlib.RegFI Compiling module xil_defaultlib.RegisterFile Compiling module xil_defaultlib.SignalExtension Compiling module xil_defaultlib.RegID Compiling module xil_defaultlib.ALUControl Compiling module xil_defaultlib.ALU2 Compiling module xil_defaultlib.ShiftUnit Compiling module xil_defaultlib.RegEX Compiling module xil_defaultlib.Multiplexer4 Compiling module xil_defaultlib.Multiplexer Compiling module xil_defaultlib.DataMemory Compiling module xil_defaultlib.RegMA Compiling module xil_defaultlib.top Compiling module xil_defaultlib.glbl Built simulation snapshot top_behav ****** Webtalk v2016.2 (64-bit) **** SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016 **** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. source C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/xsim.dir/top_behav/webtalk/xsim_webtalk.tcl -notrace INFO: [Common 17-206] Exiting Webtalk at Mon Dec 24 23:52:20 2018... run_program: Time (s): cpu = 00:00:00 ; elapsed = 00:00:06 . Memory (MB): peak = 1410.078 ; gain = 0.000 INFO: [USF-XSim-69] 'elaborate' step finished in '6' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' INFO: [USF-XSim-98] *** Running xsim with args "top_behav -key {Behavioral:sim_1:Functional:top} -tclbatch {top.tcl} -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature Vivado Simulator 2016.2 Time resolution is 1 ps source top.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns INFO: [USF-XSim-96] XSim completed. Design snapshot 'top_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:04 ; elapsed = 00:00:15 . Memory (MB): peak = 1410.078 ; gain = 0.000 close_sim INFO: [Simtcl 6-16] Simulation closed launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'top' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj top_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Multiplexer INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegEX.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegEX INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer4.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Multiplexer4 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegMA.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegMA INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALUControl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALUControl INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegisterFile.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegisterFile INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegID.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegID INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegFI.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegFI INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ControlUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ProgramCounter.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ProgramCounter INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SignalExtension.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module SignalExtension INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ShiftUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ShiftUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module InstructionMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module DataMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALU2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALU2 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Add1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Add1 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module top INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl INFO: [USF-XSim-69] 'compile' step finished in '3' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' Vivado Simulator 2016.2 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: J:/Xilinx/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto 4c388791a4e240948a5554cd0b3617d7 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot top_behav xil_defaultlib.top xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration WARNING: [VRFC 10-278] actual bit length 32 differs from formal bit length 5 for port addr [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:144] Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling module xil_defaultlib.ControlUnit Compiling module xil_defaultlib.ProgramCounter Compiling module xil_defaultlib.Add1 Compiling module xil_defaultlib.InstructionMemory Compiling module xil_defaultlib.RegFI Compiling module xil_defaultlib.RegisterFile Compiling module xil_defaultlib.SignalExtension Compiling module xil_defaultlib.RegID Compiling module xil_defaultlib.ALUControl Compiling module xil_defaultlib.ALU2 Compiling module xil_defaultlib.ShiftUnit Compiling module xil_defaultlib.RegEX Compiling module xil_defaultlib.Multiplexer4 Compiling module xil_defaultlib.Multiplexer Compiling module xil_defaultlib.DataMemory Compiling module xil_defaultlib.RegMA Compiling module xil_defaultlib.top Compiling module xil_defaultlib.glbl Built simulation snapshot top_behav ****** Webtalk v2016.2 (64-bit) **** SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016 **** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. source C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/xsim.dir/top_behav/webtalk/xsim_webtalk.tcl -notrace INFO: [Common 17-206] Exiting Webtalk at Mon Dec 24 23:54:26 2018... run_program: Time (s): cpu = 00:00:00 ; elapsed = 00:00:06 . Memory (MB): peak = 1410.078 ; gain = 0.000 INFO: [USF-XSim-69] 'elaborate' step finished in '6' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' INFO: [USF-XSim-98] *** Running xsim with args "top_behav -key {Behavioral:sim_1:Functional:top} -tclbatch {top.tcl} -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature Vivado Simulator 2016.2 Time resolution is 1 ps source top.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns INFO: [USF-XSim-96] XSim completed. Design snapshot 'top_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:04 ; elapsed = 00:00:14 . Memory (MB): peak = 1410.078 ; gain = 0.000 close_sim INFO: [Simtcl 6-16] Simulation closed close_sim: Time (s): cpu = 00:00:01 ; elapsed = 00:00:05 . Memory (MB): peak = 1410.078 ; gain = 0.000 launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'top' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj top_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Multiplexer INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegEX.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegEX INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer4.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Multiplexer4 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegMA.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegMA INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALUControl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALUControl INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegisterFile.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegisterFile INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegID.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegID INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegFI.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegFI INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ControlUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ProgramCounter.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ProgramCounter INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SignalExtension.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module SignalExtension INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ShiftUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ShiftUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module InstructionMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module DataMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALU2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALU2 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Add1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Add1 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module top INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl INFO: [USF-XSim-69] 'compile' step finished in '2' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' Vivado Simulator 2016.2 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: J:/Xilinx/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto 4c388791a4e240948a5554cd0b3617d7 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot top_behav xil_defaultlib.top xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration WARNING: [VRFC 10-278] actual bit length 32 differs from formal bit length 5 for port addr [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:144] Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling module xil_defaultlib.ControlUnit Compiling module xil_defaultlib.ProgramCounter Compiling module xil_defaultlib.Add1 Compiling module xil_defaultlib.InstructionMemory Compiling module xil_defaultlib.RegFI Compiling module xil_defaultlib.RegisterFile Compiling module xil_defaultlib.SignalExtension Compiling module xil_defaultlib.RegID Compiling module xil_defaultlib.ALUControl Compiling module xil_defaultlib.ALU2 Compiling module xil_defaultlib.ShiftUnit Compiling module xil_defaultlib.RegEX Compiling module xil_defaultlib.Multiplexer4 Compiling module xil_defaultlib.Multiplexer Compiling module xil_defaultlib.DataMemory Compiling module xil_defaultlib.RegMA Compiling module xil_defaultlib.top Compiling module xil_defaultlib.glbl Built simulation snapshot top_behav ****** Webtalk v2016.2 (64-bit) **** SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016 **** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. source C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/xsim.dir/top_behav/webtalk/xsim_webtalk.tcl -notrace INFO: [Common 17-206] Exiting Webtalk at Tue Dec 25 00:02:19 2018... run_program: Time (s): cpu = 00:00:00 ; elapsed = 00:00:07 . Memory (MB): peak = 1410.078 ; gain = 0.000 INFO: [USF-XSim-69] 'elaborate' step finished in '7' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' INFO: [USF-XSim-98] *** Running xsim with args "top_behav -key {Behavioral:sim_1:Functional:top} -tclbatch {top.tcl} -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature Vivado Simulator 2016.2 Time resolution is 1 ps source top.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns xsim: Time (s): cpu = 00:00:03 ; elapsed = 00:00:05 . Memory (MB): peak = 1410.078 ; gain = 0.000 INFO: [USF-XSim-96] XSim completed. Design snapshot 'top_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:05 ; elapsed = 00:00:16 . Memory (MB): peak = 1410.078 ; gain = 0.000 close_sim INFO: [Simtcl 6-16] Simulation closed launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'top' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj top_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Multiplexer INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegEX.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegEX INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer4.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Multiplexer4 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegMA.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegMA INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALUControl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALUControl INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegisterFile.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegisterFile INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegID.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegID INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegFI.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegFI INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ControlUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ProgramCounter.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ProgramCounter INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SignalExtension.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module SignalExtension INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ShiftUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ShiftUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module InstructionMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module DataMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALU2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALU2 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Add1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Add1 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module top INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl INFO: [USF-XSim-69] 'compile' step finished in '2' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' Vivado Simulator 2016.2 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: J:/Xilinx/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto 4c388791a4e240948a5554cd0b3617d7 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot top_behav xil_defaultlib.top xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration WARNING: [VRFC 10-278] actual bit length 32 differs from formal bit length 5 for port addr [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:144] Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling module xil_defaultlib.ControlUnit Compiling module xil_defaultlib.ProgramCounter Compiling module xil_defaultlib.Add1 Compiling module xil_defaultlib.InstructionMemory Compiling module xil_defaultlib.RegFI Compiling module xil_defaultlib.RegisterFile Compiling module xil_defaultlib.SignalExtension Compiling module xil_defaultlib.RegID Compiling module xil_defaultlib.ALUControl Compiling module xil_defaultlib.ALU2 Compiling module xil_defaultlib.ShiftUnit Compiling module xil_defaultlib.RegEX Compiling module xil_defaultlib.Multiplexer4 Compiling module xil_defaultlib.Multiplexer Compiling module xil_defaultlib.DataMemory Compiling module xil_defaultlib.RegMA Compiling module xil_defaultlib.top Compiling module xil_defaultlib.glbl Built simulation snapshot top_behav ****** Webtalk v2016.2 (64-bit) **** SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016 **** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. source C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/xsim.dir/top_behav/webtalk/xsim_webtalk.tcl -notrace INFO: [Common 17-206] Exiting Webtalk at Tue Dec 25 00:04:38 2018... run_program: Time (s): cpu = 00:00:01 ; elapsed = 00:00:05 . Memory (MB): peak = 1410.078 ; gain = 0.000 INFO: [USF-XSim-69] 'elaborate' step finished in '6' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' INFO: [USF-XSim-98] *** Running xsim with args "top_behav -key {Behavioral:sim_1:Functional:top} -tclbatch {top.tcl} -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature Vivado Simulator 2016.2 Time resolution is 1 ps source top.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns INFO: [USF-XSim-96] XSim completed. Design snapshot 'top_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:03 ; elapsed = 00:00:13 . Memory (MB): peak = 1410.078 ; gain = 0.000 close_sim INFO: [Simtcl 6-16] Simulation closed close_sim: Time (s): cpu = 00:00:01 ; elapsed = 00:00:05 . Memory (MB): peak = 1410.078 ; gain = 0.000 launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'top' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj top_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Multiplexer INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegEX.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegEX INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer4.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Multiplexer4 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegMA.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegMA INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALUControl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALUControl INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegisterFile.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegisterFile INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegID.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegID INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegFI.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegFI INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ControlUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ProgramCounter.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ProgramCounter INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SignalExtension.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module SignalExtension INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ShiftUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ShiftUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module InstructionMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module DataMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALU2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALU2 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Add1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Add1 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module top INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl INFO: [USF-XSim-69] 'compile' step finished in '2' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' Vivado Simulator 2016.2 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: J:/Xilinx/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto 4c388791a4e240948a5554cd0b3617d7 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot top_behav xil_defaultlib.top xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration WARNING: [VRFC 10-278] actual bit length 32 differs from formal bit length 5 for port addr [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:144] Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling module xil_defaultlib.ControlUnit Compiling module xil_defaultlib.ProgramCounter Compiling module xil_defaultlib.Add1 Compiling module xil_defaultlib.InstructionMemory Compiling module xil_defaultlib.RegFI Compiling module xil_defaultlib.RegisterFile Compiling module xil_defaultlib.SignalExtension Compiling module xil_defaultlib.RegID Compiling module xil_defaultlib.ALUControl Compiling module xil_defaultlib.ALU2 Compiling module xil_defaultlib.ShiftUnit Compiling module xil_defaultlib.RegEX Compiling module xil_defaultlib.Multiplexer4 Compiling module xil_defaultlib.Multiplexer Compiling module xil_defaultlib.DataMemory Compiling module xil_defaultlib.RegMA Compiling module xil_defaultlib.top Compiling module xil_defaultlib.glbl Built simulation snapshot top_behav ****** Webtalk v2016.2 (64-bit) **** SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016 **** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. source C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/xsim.dir/top_behav/webtalk/xsim_webtalk.tcl -notrace INFO: [Common 17-206] Exiting Webtalk at Tue Dec 25 00:31:24 2018... run_program: Time (s): cpu = 00:00:00 ; elapsed = 00:00:06 . Memory (MB): peak = 1410.078 ; gain = 0.000 INFO: [USF-XSim-69] 'elaborate' step finished in '6' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' INFO: [USF-XSim-98] *** Running xsim with args "top_behav -key {Behavioral:sim_1:Functional:top} -tclbatch {top.tcl} -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature Vivado Simulator 2016.2 Time resolution is 1 ps source top.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns INFO: [USF-XSim-96] XSim completed. Design snapshot 'top_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:04 ; elapsed = 00:00:14 . Memory (MB): peak = 1410.078 ; gain = 0.000 close_sim INFO: [Simtcl 6-16] Simulation closed close_sim: Time (s): cpu = 00:00:00 ; elapsed = 00:00:05 . Memory (MB): peak = 1410.078 ; gain = 0.000 launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'top' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj top_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Multiplexer INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegEX.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegEX INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer4.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Multiplexer4 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegMA.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegMA INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALUControl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALUControl INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegisterFile.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegisterFile INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegID.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegID INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegFI.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegFI INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ControlUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ProgramCounter.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ProgramCounter INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SignalExtension.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module SignalExtension INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ShiftUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ShiftUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module InstructionMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module DataMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALU2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALU2 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Add1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Add1 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module top INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl INFO: [USF-XSim-69] 'compile' step finished in '2' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' Vivado Simulator 2016.2 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: J:/Xilinx/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto 4c388791a4e240948a5554cd0b3617d7 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot top_behav xil_defaultlib.top xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration WARNING: [VRFC 10-278] actual bit length 32 differs from formal bit length 5 for port addr [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:144] Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling module xil_defaultlib.ControlUnit Compiling module xil_defaultlib.ProgramCounter Compiling module xil_defaultlib.Add1 Compiling module xil_defaultlib.InstructionMemory Compiling module xil_defaultlib.RegFI Compiling module xil_defaultlib.RegisterFile Compiling module xil_defaultlib.SignalExtension Compiling module xil_defaultlib.RegID Compiling module xil_defaultlib.ALUControl Compiling module xil_defaultlib.ALU2 Compiling module xil_defaultlib.ShiftUnit Compiling module xil_defaultlib.RegEX Compiling module xil_defaultlib.Multiplexer4 Compiling module xil_defaultlib.Multiplexer Compiling module xil_defaultlib.DataMemory Compiling module xil_defaultlib.RegMA Compiling module xil_defaultlib.top Compiling module xil_defaultlib.glbl Built simulation snapshot top_behav ****** Webtalk v2016.2 (64-bit) **** SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016 **** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. source C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/xsim.dir/top_behav/webtalk/xsim_webtalk.tcl -notrace INFO: [Common 17-206] Exiting Webtalk at Tue Dec 25 00:33:07 2018... run_program: Time (s): cpu = 00:00:00 ; elapsed = 00:00:06 . Memory (MB): peak = 1410.078 ; gain = 0.000 INFO: [USF-XSim-69] 'elaborate' step finished in '6' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' INFO: [USF-XSim-98] *** Running xsim with args "top_behav -key {Behavioral:sim_1:Functional:top} -tclbatch {top.tcl} -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature Vivado Simulator 2016.2 Time resolution is 1 ps source top.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns INFO: [USF-XSim-96] XSim completed. Design snapshot 'top_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:04 ; elapsed = 00:00:14 . Memory (MB): peak = 1410.078 ; gain = 0.000 close_sim INFO: [Simtcl 6-16] Simulation closed close_sim: Time (s): cpu = 00:00:01 ; elapsed = 00:00:05 . Memory (MB): peak = 1419.152 ; gain = 9.074 launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'top' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj top_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Multiplexer INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegEX.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegEX INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer4.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Multiplexer4 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegMA.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegMA INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALUControl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALUControl INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegisterFile.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegisterFile INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegID.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegID INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegFI.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegFI INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ControlUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ProgramCounter.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ProgramCounter INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SignalExtension.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module SignalExtension INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ShiftUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ShiftUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module InstructionMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module DataMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALU2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALU2 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Add1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Add1 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module top INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl INFO: [USF-XSim-69] 'compile' step finished in '2' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' Vivado Simulator 2016.2 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: J:/Xilinx/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto 4c388791a4e240948a5554cd0b3617d7 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot top_behav xil_defaultlib.top xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration WARNING: [VRFC 10-278] actual bit length 32 differs from formal bit length 5 for port addr [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:144] Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling module xil_defaultlib.ControlUnit Compiling module xil_defaultlib.ProgramCounter Compiling module xil_defaultlib.Add1 Compiling module xil_defaultlib.InstructionMemory Compiling module xil_defaultlib.RegFI Compiling module xil_defaultlib.RegisterFile Compiling module xil_defaultlib.SignalExtension Compiling module xil_defaultlib.RegID Compiling module xil_defaultlib.ALUControl Compiling module xil_defaultlib.ALU2 Compiling module xil_defaultlib.ShiftUnit Compiling module xil_defaultlib.RegEX Compiling module xil_defaultlib.Multiplexer4 Compiling module xil_defaultlib.Multiplexer Compiling module xil_defaultlib.DataMemory Compiling module xil_defaultlib.RegMA Compiling module xil_defaultlib.top Compiling module xil_defaultlib.glbl Built simulation snapshot top_behav ****** Webtalk v2016.2 (64-bit) **** SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016 **** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. source C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/xsim.dir/top_behav/webtalk/xsim_webtalk.tcl -notrace INFO: [Common 17-206] Exiting Webtalk at Tue Dec 25 01:56:09 2018... run_program: Time (s): cpu = 00:00:00 ; elapsed = 00:00:06 . Memory (MB): peak = 1419.152 ; gain = 0.000 INFO: [USF-XSim-69] 'elaborate' step finished in '6' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' INFO: [USF-XSim-98] *** Running xsim with args "top_behav -key {Behavioral:sim_1:Functional:top} -tclbatch {top.tcl} -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature Vivado Simulator 2016.2 Time resolution is 1 ps source top.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns INFO: [USF-XSim-96] XSim completed. Design snapshot 'top_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:05 ; elapsed = 00:00:14 . Memory (MB): peak = 1419.152 ; gain = 0.000 close_sim INFO: [Simtcl 6-16] Simulation closed close_sim: Time (s): cpu = 00:00:00 ; elapsed = 00:00:05 . Memory (MB): peak = 1419.508 ; gain = 0.000 launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'top' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj top_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Multiplexer INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegEX.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegEX INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer4.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Multiplexer4 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegMA.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegMA INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALUControl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALUControl INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegisterFile.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegisterFile INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegID.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegID INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegFI.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegFI INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ControlUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ProgramCounter.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ProgramCounter INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SignalExtension.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module SignalExtension INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ShiftUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ShiftUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module InstructionMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module DataMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALU2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALU2 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Add1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Add1 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module top INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl INFO: [USF-XSim-69] 'compile' step finished in '2' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' Vivado Simulator 2016.2 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: J:/Xilinx/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto 4c388791a4e240948a5554cd0b3617d7 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot top_behav xil_defaultlib.top xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration WARNING: [VRFC 10-278] actual bit length 32 differs from formal bit length 5 for port addr [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:139] Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling module xil_defaultlib.ControlUnit Compiling module xil_defaultlib.ProgramCounter Compiling module xil_defaultlib.Add1 Compiling module xil_defaultlib.InstructionMemory Compiling module xil_defaultlib.RegFI Compiling module xil_defaultlib.RegisterFile Compiling module xil_defaultlib.SignalExtension Compiling module xil_defaultlib.RegID Compiling module xil_defaultlib.ALUControl Compiling module xil_defaultlib.ALU2 Compiling module xil_defaultlib.ShiftUnit Compiling module xil_defaultlib.RegEX Compiling module xil_defaultlib.Multiplexer4 Compiling module xil_defaultlib.Multiplexer Compiling module xil_defaultlib.DataMemory Compiling module xil_defaultlib.RegMA Compiling module xil_defaultlib.top Compiling module xil_defaultlib.glbl Built simulation snapshot top_behav ****** Webtalk v2016.2 (64-bit) **** SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016 **** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. source C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/xsim.dir/top_behav/webtalk/xsim_webtalk.tcl -notrace INFO: [Common 17-206] Exiting Webtalk at Tue Dec 25 02:01:22 2018... run_program: Time (s): cpu = 00:00:01 ; elapsed = 00:00:06 . Memory (MB): peak = 1419.508 ; gain = 0.000 INFO: [USF-XSim-69] 'elaborate' step finished in '7' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' INFO: [USF-XSim-98] *** Running xsim with args "top_behav -key {Behavioral:sim_1:Functional:top} -tclbatch {top.tcl} -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature Vivado Simulator 2016.2 Time resolution is 1 ps source top.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns xsim: Time (s): cpu = 00:00:04 ; elapsed = 00:00:06 . Memory (MB): peak = 1419.508 ; gain = 0.000 INFO: [USF-XSim-96] XSim completed. Design snapshot 'top_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:05 ; elapsed = 00:00:16 . Memory (MB): peak = 1419.508 ; gain = 0.000 close_sim INFO: [Simtcl 6-16] Simulation closed close_sim: Time (s): cpu = 00:00:01 ; elapsed = 00:00:08 . Memory (MB): peak = 1419.508 ; gain = 0.000 launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'top' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj top_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Multiplexer INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegEX.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegEX INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer4.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Multiplexer4 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegMA.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegMA INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALUControl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALUControl INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegisterFile.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegisterFile INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegID.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegID INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegFI.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegFI INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ControlUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ProgramCounter.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ProgramCounter INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SignalExtension.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module SignalExtension INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ShiftUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ShiftUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module InstructionMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module DataMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALU2.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALU2 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Add1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Add1 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module top INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl INFO: [USF-XSim-69] 'compile' step finished in '3' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' Vivado Simulator 2016.2 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: J:/Xilinx/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto 4c388791a4e240948a5554cd0b3617d7 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot top_behav xil_defaultlib.top xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration WARNING: [VRFC 10-278] actual bit length 32 differs from formal bit length 5 for port addr [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:139] Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling module xil_defaultlib.ControlUnit Compiling module xil_defaultlib.ProgramCounter Compiling module xil_defaultlib.Add1 Compiling module xil_defaultlib.InstructionMemory Compiling module xil_defaultlib.RegFI Compiling module xil_defaultlib.RegisterFile Compiling module xil_defaultlib.SignalExtension Compiling module xil_defaultlib.RegID Compiling module xil_defaultlib.ALUControl Compiling module xil_defaultlib.ALU2 Compiling module xil_defaultlib.ShiftUnit Compiling module xil_defaultlib.RegEX Compiling module xil_defaultlib.Multiplexer4 Compiling module xil_defaultlib.Multiplexer Compiling module xil_defaultlib.DataMemory Compiling module xil_defaultlib.RegMA Compiling module xil_defaultlib.top Compiling module xil_defaultlib.glbl Built simulation snapshot top_behav ****** Webtalk v2016.2 (64-bit) **** SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016 **** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. source C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/xsim.dir/top_behav/webtalk/xsim_webtalk.tcl -notrace INFO: [Common 17-206] Exiting Webtalk at Tue Dec 25 02:25:21 2018... run_program: Time (s): cpu = 00:00:01 ; elapsed = 00:00:08 . Memory (MB): peak = 1419.508 ; gain = 0.000 INFO: [USF-XSim-69] 'elaborate' step finished in '9' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' INFO: [USF-XSim-98] *** Running xsim with args "top_behav -key {Behavioral:sim_1:Functional:top} -tclbatch {top.tcl} -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature Vivado Simulator 2016.2 Time resolution is 1 ps source top.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns INFO: [USF-XSim-96] XSim completed. Design snapshot 'top_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:04 ; elapsed = 00:00:17 . Memory (MB): peak = 1419.508 ; gain = 0.000 close_sim INFO: [Simtcl 6-16] Simulation closed close_sim: Time (s): cpu = 00:00:02 ; elapsed = 00:00:08 . Memory (MB): peak = 1419.508 ; gain = 0.000 synth_design -rtl -name rtl_1 Command: synth_design -rtl -name rtl_1 Starting synth_design Using part: xc7z030sbg485-1 Top: top CRITICAL WARNING: [Synth 8-2490] overwriting previous definition of module AND2 [J:/Xilinx/Vivado/2016.2/scripts/rt/data/unisim_comp.v:14] CRITICAL WARNING: [Synth 8-2490] overwriting previous definition of module AND2B1 [J:/Xilinx/Vivado/2016.2/scripts/rt/data/unisim_comp.v:25] CRITICAL WARNING: [Synth 8-2490] overwriting previous definition of module AND2B1L [J:/Xilinx/Vivado/2016.2/scripts/rt/data/unisim_comp.v:36] CRITICAL WARNING: [Synth 8-2490] overwriting previous definition of module AND2B2 [J:/Xilinx/Vivado/2016.2/scripts/rt/data/unisim_comp.v:49] CRITICAL WARNING: [Synth 8-2490] overwriting previous definition of module AND3 [J:/Xilinx/Vivado/2016.2/scripts/rt/data/unisim_comp.v:60] CRITICAL WARNING: [Synth 8-2490] overwriting previous definition of module AND3B1 [J:/Xilinx/Vivado/2016.2/scripts/rt/data/unisim_comp.v:72] CRITICAL WARNING: [Synth 8-2490] overwriting previous definition of module AND3B2 [J:/Xilinx/Vivado/2016.2/scripts/rt/data/unisim_comp.v:84] CRITICAL WARNING: [Synth 8-2490] overwriting previous definition of module AND3B3 [J:/Xilinx/Vivado/2016.2/scripts/rt/data/unisim_comp.v:96] CRITICAL WARNING: [Synth 8-2490] overwriting previous definition of module AND4 [J:/Xilinx/Vivado/2016.2/scripts/rt/data/unisim_comp.v:108] CRITICAL WARNING: [Synth 8-2490] overwriting previous definition of module AND4B1 [J:/Xilinx/Vivado/2016.2/scripts/rt/data/unisim_comp.v:121] CRITICAL WARNING: [Synth 8-2490] overwriting previous definition of module AND4B2 [J:/Xilinx/Vivado/2016.2/scripts/rt/data/unisim_comp.v:134] CRITICAL WARNING: [Synth 8-2490] overwriting previous definition of module AND4B3 [J:/Xilinx/Vivado/2016.2/scripts/rt/data/unisim_comp.v:147] CRITICAL WARNING: [Synth 8-2490] overwriting previous definition of module AND4B4 [J:/Xilinx/Vivado/2016.2/scripts/rt/data/unisim_comp.v:160] CRITICAL WARNING: [Synth 8-2490] overwriting previous definition of module AND5 [J:/Xilinx/Vivado/2016.2/scripts/rt/data/unisim_comp.v:173] CRITICAL WARNING: [Synth 8-2490] overwriting previous definition of module AND5B1 [J:/Xilinx/Vivado/2016.2/scripts/rt/data/unisim_comp.v:187] CRITICAL WARNING: [Synth 8-2490] overwriting previous definition of module AND5B2 [J:/Xilinx/Vivado/2016.2/scripts/rt/data/unisim_comp.v:201] CRITICAL WARNING: [Synth 8-2490] overwriting previous definition of module AND5B3 [J:/Xilinx/Vivado/2016.2/scripts/rt/data/unisim_comp.v:215] CRITICAL WARNING: [Synth 8-2490] overwriting previous definition of module AND5B4 [J:/Xilinx/Vivado/2016.2/scripts/rt/data/unisim_comp.v:229] CRITICAL WARNING: [Synth 8-2490] overwriting previous definition of module AND5B5 [J:/Xilinx/Vivado/2016.2/scripts/rt/data/unisim_comp.v:243] CRITICAL WARNING: [Synth 8-2490] overwriting previous definition of module AUTOBUF [J:/Xilinx/Vivado/2016.2/scripts/rt/data/unisim_comp.v:257] CRITICAL WARNING: [Synth 8-2490] overwriting previous definition of module BIBUF [J:/Xilinx/Vivado/2016.2/scripts/rt/data/unisim_comp.v:268] CRITICAL WARNING: [Synth 8-2490] overwriting previous definition of module BITSLICE_CONTROL [J:/Xilinx/Vivado/2016.2/scripts/rt/data/unisim_comp.v:278] CRITICAL WARNING: [Synth 8-2490] overwriting previous definition of module BSCANE2 [J:/Xilinx/Vivado/2016.2/scripts/rt/data/unisim_comp.v:422] CRITICAL WARNING: [Synth 8-2490] overwriting previous definition of module BSCAN_SPARTAN3 [J:/Xilinx/Vivado/2016.2/scripts/rt/data/unisim_comp.v:452] CRITICAL WARNING: [Synth 8-2490] overwriting previous definition of module BSCAN_SPARTAN3A [J:/Xilinx/Vivado/2016.2/scripts/rt/data/unisim_comp.v:471] CRITICAL WARNING: [Synth 8-2490] overwriting previous definition of module BSCAN_SPARTAN6 [J:/Xilinx/Vivado/2016.2/scripts/rt/data/unisim_comp.v:492] CRITICAL WARNING: [Synth 8-2490] overwriting previous definition of module BSCAN_VIRTEX4 [J:/Xilinx/Vivado/2016.2/scripts/rt/data/unisim_comp.v:512] CRITICAL WARNING: [Synth 8-2490] overwriting previous definition of module BSCAN_VIRTEX5 [J:/Xilinx/Vivado/2016.2/scripts/rt/data/unisim_comp.v:529] CRITICAL WARNING: [Synth 8-2490] overwriting previous definition of module BSCAN_VIRTEX6 [J:/Xilinx/Vivado/2016.2/scripts/rt/data/unisim_comp.v:546] CRITICAL WARNING: [Synth 8-2490] overwriting previous definition of module BUF [J:/Xilinx/Vivado/2016.2/scripts/rt/data/unisim_comp.v:567] CRITICAL WARNING: [Synth 8-2490] overwriting previous definition of module BUFCE_LEAF [J:/Xilinx/Vivado/2016.2/scripts/rt/data/unisim_comp.v:577] CRITICAL WARNING: [Synth 8-2490] overwriting previous definition of module BUFCE_ROW [J:/Xilinx/Vivado/2016.2/scripts/rt/data/unisim_comp.v:592] CRITICAL WARNING: [Synth 8-2490] overwriting previous definition of module BUFG [J:/Xilinx/Vivado/2016.2/scripts/rt/data/unisim_comp.v:607] CRITICAL WARNING: [Synth 8-2490] overwriting previous definition of module BUFGCE [J:/Xilinx/Vivado/2016.2/scripts/rt/data/unisim_comp.v:617] CRITICAL WARNING: [Synth 8-2490] overwriting previous definition of module BUFGCE_1 [J:/Xilinx/Vivado/2016.2/scripts/rt/data/unisim_comp.v:632] CRITICAL WARNING: [Synth 8-2490] overwriting previous definition of module BUFGCE_DIV [J:/Xilinx/Vivado/2016.2/scripts/rt/data/unisim_comp.v:643] CRITICAL WARNING: [Synth 8-2490] overwriting previous definition of module BUFGCTRL [J:/Xilinx/Vivado/2016.2/scripts/rt/data/unisim_comp.v:661] CRITICAL WARNING: [Synth 8-2490] overwriting previous definition of module BUFGMUX [J:/Xilinx/Vivado/2016.2/scripts/rt/data/unisim_comp.v:696] CRITICAL WARNING: [Synth 8-2490] overwriting previous definition of module BUFGMUX_1 [J:/Xilinx/Vivado/2016.2/scripts/rt/data/unisim_comp.v:709] CRITICAL WARNING: [Synth 8-2490] overwriting previous definition of module BUFGMUX_CTRL [J:/Xilinx/Vivado/2016.2/scripts/rt/data/unisim_comp.v:722] CRITICAL WARNING: [Synth 8-2490] overwriting previous definition of module BUFGMUX_VIRTEX4 [J:/Xilinx/Vivado/2016.2/scripts/rt/data/unisim_comp.v:736] CRITICAL WARNING: [Synth 8-2490] overwriting previous definition of module BUFGP [J:/Xilinx/Vivado/2016.2/scripts/rt/data/unisim_comp.v:750] CRITICAL WARNING: [Synth 8-2490] overwriting previous definition of module BUFG_GT [J:/Xilinx/Vivado/2016.2/scripts/rt/data/unisim_comp.v:760] CRITICAL WARNING: [Synth 8-2490] overwriting previous definition of module BUFG_GT_SYNC [J:/Xilinx/Vivado/2016.2/scripts/rt/data/unisim_comp.v:780] CRITICAL WARNING: [Synth 8-2490] overwriting previous definition of module BUFG_PS [J:/Xilinx/Vivado/2016.2/scripts/rt/data/unisim_comp.v:796] CRITICAL WARNING: [Synth 8-2490] overwriting previous definition of module BUFH [J:/Xilinx/Vivado/2016.2/scripts/rt/data/unisim_comp.v:806] CRITICAL WARNING: [Synth 8-2490] overwriting previous definition of module BUFHCE [J:/Xilinx/Vivado/2016.2/scripts/rt/data/unisim_comp.v:816] CRITICAL WARNING: [Synth 8-2490] overwriting previous definition of module BUFIO [J:/Xilinx/Vivado/2016.2/scripts/rt/data/unisim_comp.v:831] CRITICAL WARNING: [Synth 8-2490] overwriting previous definition of module BUFIO2 [J:/Xilinx/Vivado/2016.2/scripts/rt/data/unisim_comp.v:841] CRITICAL WARNING: [Synth 8-2490] overwriting previous definition of module BUFMR [J:/Xilinx/Vivado/2016.2/scripts/rt/data/unisim_comp.v:859] CRITICAL WARNING: [Synth 8-2490] overwriting previous definition of module BUFMRCE [J:/Xilinx/Vivado/2016.2/scripts/rt/data/unisim_comp.v:869] CRITICAL WARNING: [Synth 8-2490] overwriting previous definition of module BUFR [J:/Xilinx/Vivado/2016.2/scripts/rt/data/unisim_comp.v:884] CRITICAL WARNING: [Synth 8-2490] overwriting previous definition of module CAPTUREE2 [J:/Xilinx/Vivado/2016.2/scripts/rt/data/unisim_comp.v:900] CRITICAL WARNING: [Synth 8-2490] overwriting previous definition of module CAPTURE_SPARTAN3 [J:/Xilinx/Vivado/2016.2/scripts/rt/data/unisim_comp.v:911] CRITICAL WARNING: [Synth 8-2490] overwriting previous definition of module CAPTURE_SPARTAN3A [J:/Xilinx/Vivado/2016.2/scripts/rt/data/unisim_comp.v:921] CRITICAL WARNING: [Synth 8-2490] overwriting previous definition of module CAPTURE_VIRTEX4 [J:/Xilinx/Vivado/2016.2/scripts/rt/data/unisim_comp.v:931] CRITICAL WARNING: [Synth 8-2490] overwriting previous definition of module CAPTURE_VIRTEX5 [J:/Xilinx/Vivado/2016.2/scripts/rt/data/unisim_comp.v:941] CRITICAL WARNING: [Synth 8-2490] overwriting previous definition of module CAPTURE_VIRTEX6 [J:/Xilinx/Vivado/2016.2/scripts/rt/data/unisim_comp.v:951] CRITICAL WARNING: [Synth 8-2490] overwriting previous definition of module CARRY4 [J:/Xilinx/Vivado/2016.2/scripts/rt/data/unisim_comp.v:961] CRITICAL WARNING: [Synth 8-2490] overwriting previous definition of module CARRY8 [J:/Xilinx/Vivado/2016.2/scripts/rt/data/unisim_comp.v:979] CRITICAL WARNING: [Synth 8-2490] overwriting previous definition of module CFGLUT5 [J:/Xilinx/Vivado/2016.2/scripts/rt/data/unisim_comp.v:998] CRITICAL WARNING: [Synth 8-2490] overwriting previous definition of module CMAC [J:/Xilinx/Vivado/2016.2/scripts/rt/data/unisim_comp.v:1028] CRITICAL WARNING: [Synth 8-2490] overwriting previous definition of module CMACE4 [J:/Xilinx/Vivado/2016.2/scripts/rt/data/unisim_comp.v:1838] CRITICAL WARNING: [Synth 8-2490] overwriting previous definition of module DCIRESET [J:/Xilinx/Vivado/2016.2/scripts/rt/data/unisim_comp.v:2755] CRITICAL WARNING: [Synth 8-2490] overwriting previous definition of module DCM [J:/Xilinx/Vivado/2016.2/scripts/rt/data/unisim_comp.v:2765] CRITICAL WARNING: [Synth 8-2490] overwriting previous definition of module DCM_ADV [J:/Xilinx/Vivado/2016.2/scripts/rt/data/unisim_comp.v:2811] CRITICAL WARNING: [Synth 8-2490] overwriting previous definition of module DCM_BASE [J:/Xilinx/Vivado/2016.2/scripts/rt/data/unisim_comp.v:2882] CRITICAL WARNING: [Synth 8-2490] overwriting previous definition of module DCM_PS [J:/Xilinx/Vivado/2016.2/scripts/rt/data/unisim_comp.v:2930] CRITICAL WARNING: [Synth 8-2490] overwriting previous definition of module DCM_SP [J:/Xilinx/Vivado/2016.2/scripts/rt/data/unisim_comp.v:2988] CRITICAL WARNING: [Synth 8-2490] overwriting previous definition of module DNA_PORT [J:/Xilinx/Vivado/2016.2/scripts/rt/data/unisim_comp.v:3033] CRITICAL WARNING: [Synth 8-2490] overwriting previous definition of module DNA_PORTE2 [J:/Xilinx/Vivado/2016.2/scripts/rt/data/unisim_comp.v:3047] CRITICAL WARNING: [Synth 8-2490] overwriting previous definition of module DPHY_DIFFINBUF [J:/Xilinx/Vivado/2016.2/scripts/rt/data/unisim_comp.v:3064] CRITICAL WARNING: [Synth 8-2490] overwriting previous definition of module DSP48 [J:/Xilinx/Vivado/2016.2/scripts/rt/data/unisim_comp.v:3086] CRITICAL WARNING: [Synth 8-2490] overwriting previous definition of module DSP48A [J:/Xilinx/Vivado/2016.2/scripts/rt/data/unisim_comp.v:3159] CRITICAL WARNING: [Synth 8-2490] overwriting previous definition of module DSP48A1 [J:/Xilinx/Vivado/2016.2/scripts/rt/data/unisim_comp.v:3233] CRITICAL WARNING: [Synth 8-2490] overwriting previous definition of module DSP48E [J:/Xilinx/Vivado/2016.2/scripts/rt/data/unisim_comp.v:3312] CRITICAL WARNING: [Synth 8-2490] overwriting previous definition of module DSP48E1 [J:/Xilinx/Vivado/2016.2/scripts/rt/data/unisim_comp.v:3429] CRITICAL WARNING: [Synth 8-2490] overwriting previous definition of module DSP48E2 [J:/Xilinx/Vivado/2016.2/scripts/rt/data/unisim_comp.v:3563] CRITICAL WARNING: [Synth 8-2490] overwriting previous definition of module EFUSE_USR [J:/Xilinx/Vivado/2016.2/scripts/rt/data/unisim_comp.v:3715] CRITICAL WARNING: [Synth 8-2490] overwriting previous definition of module FD [J:/Xilinx/Vivado/2016.2/scripts/rt/data/unisim_comp.v:3724] CRITICAL WARNING: [Synth 8-2490] overwriting previous definition of module FDC [J:/Xilinx/Vivado/2016.2/scripts/rt/data/unisim_comp.v:3736] CRITICAL WARNING: [Synth 8-2490] overwriting previous definition of module FDCE [J:/Xilinx/Vivado/2016.2/scripts/rt/data/unisim_comp.v:3749] CRITICAL WARNING: [Synth 8-2490] overwriting previous definition of module FDCE_1 [J:/Xilinx/Vivado/2016.2/scripts/rt/data/unisim_comp.v:3769] CRITICAL WARNING: [Synth 8-2490] overwriting previous definition of module FDCP [J:/Xilinx/Vivado/2016.2/scripts/rt/data/unisim_comp.v:3783] CRITICAL WARNING: [Synth 8-2490] overwriting previous definition of module FDCPE [J:/Xilinx/Vivado/2016.2/scripts/rt/data/unisim_comp.v:3800] CRITICAL WARNING: [Synth 8-2490] overwriting previous definition of module FDCPE_1 [J:/Xilinx/Vivado/2016.2/scripts/rt/data/unisim_comp.v:3818] CRITICAL WARNING: [Synth 8-2490] overwriting previous definition of module FDCP_1 [J:/Xilinx/Vivado/2016.2/scripts/rt/data/unisim_comp.v:3836] CRITICAL WARNING: [Synth 8-2490] overwriting previous definition of module FDC_1 [J:/Xilinx/Vivado/2016.2/scripts/rt/data/unisim_comp.v:3853] CRITICAL WARNING: [Synth 8-2490] overwriting previous definition of module FDE [J:/Xilinx/Vivado/2016.2/scripts/rt/data/unisim_comp.v:3866] CRITICAL WARNING: [Synth 8-2490] overwriting previous definition of module FDE_1 [J:/Xilinx/Vivado/2016.2/scripts/rt/data/unisim_comp.v:3879] CRITICAL WARNING: [Synth 8-2490] overwriting previous definition of module FDP [J:/Xilinx/Vivado/2016.2/scripts/rt/data/unisim_comp.v:3892] CRITICAL WARNING: [Synth 8-2490] overwriting previous definition of module FDPE [J:/Xilinx/Vivado/2016.2/scripts/rt/data/unisim_comp.v:3905] CRITICAL WARNING: [Synth 8-2490] overwriting previous definition of module FDPE_1 [J:/Xilinx/Vivado/2016.2/scripts/rt/data/unisim_comp.v:3925] CRITICAL WARNING: [Synth 8-2490] overwriting previous definition of module FDP_1 [J:/Xilinx/Vivado/2016.2/scripts/rt/data/unisim_comp.v:3939] CRITICAL WARNING: [Synth 8-2490] overwriting previous definition of module FDR [J:/Xilinx/Vivado/2016.2/scripts/rt/data/unisim_comp.v:3952] CRITICAL WARNING: [Synth 8-2490] overwriting previous definition of module FDRE [J:/Xilinx/Vivado/2016.2/scripts/rt/data/unisim_comp.v:3965] CRITICAL WARNING: [Synth 8-2490] overwriting previous definition of module FDRE_1 [J:/Xilinx/Vivado/2016.2/scripts/rt/data/unisim_comp.v:3985] CRITICAL WARNING: [Synth 8-2490] overwriting previous definition of module FDRS [J:/Xilinx/Vivado/2016.2/scripts/rt/data/unisim_comp.v:3999] CRITICAL WARNING: [Synth 8-2490] overwriting previous definition of module FDRSE [J:/Xilinx/Vivado/2016.2/scripts/rt/data/unisim_comp.v:4017] CRITICAL WARNING: [Synth 8-2490] overwriting previous definition of module FDRSE_1 [J:/Xilinx/Vivado/2016.2/scripts/rt/data/unisim_comp.v:4037] INFO: [Common 17-14] Message 'Synth 8-2490' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- Starting RTL Elaboration : Time (s): cpu = 01:11:22 ; elapsed = 34:19:04 . Memory (MB): peak = 1419.508 ; gain = 1212.418 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:37] INFO: [Synth 8-638] synthesizing module 'ControlUnit' [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v:36] INFO: [Synth 8-256] done synthesizing module 'ControlUnit' (1#1) [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v:36] INFO: [Synth 8-638] synthesizing module 'ProgramCounter' [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ProgramCounter.v:23] INFO: [Synth 8-256] done synthesizing module 'ProgramCounter' (2#1) [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ProgramCounter.v:23] INFO: [Synth 8-638] synthesizing module 'Add1' [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Add1.v:23] INFO: [Synth 8-256] done synthesizing module 'Add1' (3#1) [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Add1.v:23] INFO: [Synth 8-638] synthesizing module 'InstructionMemory' [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v:23] INFO: [Synth 8-3876] $readmem data file 'C:/Users/53194/Desktop/project_789/instruction.txt' is read successfully [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v:40] WARNING: [Synth 8-3936] Found unconnected internal register 'in_reg' and it is trimmed from '32' to '26' bits. [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v:46] INFO: [Synth 8-256] done synthesizing module 'InstructionMemory' (4#1) [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v:23] INFO: [Synth 8-638] synthesizing module 'RegFI' [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegFI.v:23] INFO: [Synth 8-256] done synthesizing module 'RegFI' (5#1) [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegFI.v:23] INFO: [Synth 8-638] synthesizing module 'RegisterFile' [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegisterFile.v:22] INFO: [Synth 8-256] done synthesizing module 'RegisterFile' (6#1) [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegisterFile.v:22] INFO: [Synth 8-638] synthesizing module 'SignalExtension' [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SignalExtension.v:23] INFO: [Synth 8-256] done synthesizing module 'SignalExtension' (7#1) [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SignalExtension.v:23] INFO: [Synth 8-638] synthesizing module 'RegID' [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegID.v:23] INFO: [Synth 8-256] done synthesizing module 'RegID' (8#1) [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegID.v:23] INFO: [Synth 8-638] synthesizing module 'ALUControl' [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALUControl.v:37] INFO: [Synth 8-256] done synthesizing module 'ALUControl' (9#1) [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALUControl.v:37] INFO: [Synth 8-638] synthesizing module 'ALU2' [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALU2.v:21] INFO: [Synth 8-226] default block is never used [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALU2.v:29] INFO: [Synth 8-256] done synthesizing module 'ALU2' (10#1) [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALU2.v:21] INFO: [Synth 8-638] synthesizing module 'ShiftUnit' [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ShiftUnit.v:23] INFO: [Synth 8-256] done synthesizing module 'ShiftUnit' (11#1) [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ShiftUnit.v:23] INFO: [Synth 8-638] synthesizing module 'RegEX' [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegEX.v:23] INFO: [Synth 8-256] done synthesizing module 'RegEX' (12#1) [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegEX.v:23] INFO: [Synth 8-638] synthesizing module 'Multiplexer4' [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer4.v:23] INFO: [Synth 8-256] done synthesizing module 'Multiplexer4' (13#1) [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer4.v:23] INFO: [Synth 8-638] synthesizing module 'Multiplexer' [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer.v:23] INFO: [Synth 8-256] done synthesizing module 'Multiplexer' (14#1) [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer.v:23] INFO: [Synth 8-638] synthesizing module 'DataMemory' [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v:23] INFO: [Synth 8-256] done synthesizing module 'DataMemory' (15#1) [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v:23] WARNING: [Synth 8-689] width (32) of port connection 'addr' does not match port width (5) of module 'DataMemory' [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:139] INFO: [Synth 8-638] synthesizing module 'RegMA' [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegMA.v:23] INFO: [Synth 8-256] done synthesizing module 'RegMA' (16#1) [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegMA.v:23] INFO: [Synth 8-256] done synthesizing module 'top' (17#1) [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:37] WARNING: [Synth 8-3331] design RegEX has unconnected port rt[31] WARNING: [Synth 8-3331] design RegEX has unconnected port rt[30] WARNING: [Synth 8-3331] design RegEX has unconnected port rt[29] WARNING: [Synth 8-3331] design RegEX has unconnected port rt[28] WARNING: [Synth 8-3331] design RegEX has unconnected port rt[27] WARNING: [Synth 8-3331] design RegEX has unconnected port rt[26] WARNING: [Synth 8-3331] design RegEX has unconnected port rt[25] WARNING: [Synth 8-3331] design RegEX has unconnected port rt[24] WARNING: [Synth 8-3331] design RegEX has unconnected port rt[23] WARNING: [Synth 8-3331] design RegEX has unconnected port rt[22] WARNING: [Synth 8-3331] design RegEX has unconnected port rt[21] WARNING: [Synth 8-3331] design RegEX has unconnected port rt[20] WARNING: [Synth 8-3331] design RegEX has unconnected port rt[19] WARNING: [Synth 8-3331] design RegEX has unconnected port rt[18] WARNING: [Synth 8-3331] design RegEX has unconnected port rt[17] WARNING: [Synth 8-3331] design RegEX has unconnected port rt[16] WARNING: [Synth 8-3331] design RegEX has unconnected port rt[15] WARNING: [Synth 8-3331] design RegEX has unconnected port rt[14] WARNING: [Synth 8-3331] design RegEX has unconnected port rt[13] WARNING: [Synth 8-3331] design RegEX has unconnected port rt[12] WARNING: [Synth 8-3331] design RegEX has unconnected port rt[11] WARNING: [Synth 8-3331] design RegEX has unconnected port rt[10] WARNING: [Synth 8-3331] design RegEX has unconnected port rt[9] WARNING: [Synth 8-3331] design RegEX has unconnected port rt[8] WARNING: [Synth 8-3331] design RegEX has unconnected port rt[7] WARNING: [Synth 8-3331] design RegEX has unconnected port rt[6] WARNING: [Synth 8-3331] design InstructionMemory has unconnected port pc[31] WARNING: [Synth 8-3331] design InstructionMemory has unconnected port pc[30] WARNING: [Synth 8-3331] design InstructionMemory has unconnected port pc[29] WARNING: [Synth 8-3331] design InstructionMemory has unconnected port pc[28] WARNING: [Synth 8-3331] design InstructionMemory has unconnected port pc[27] WARNING: [Synth 8-3331] design InstructionMemory has unconnected port pc[26] WARNING: [Synth 8-3331] design InstructionMemory has unconnected port pc[25] WARNING: [Synth 8-3331] design InstructionMemory has unconnected port pc[24] WARNING: [Synth 8-3331] design InstructionMemory has unconnected port pc[23] WARNING: [Synth 8-3331] design InstructionMemory has unconnected port pc[22] WARNING: [Synth 8-3331] design InstructionMemory has unconnected port pc[21] WARNING: [Synth 8-3331] design InstructionMemory has unconnected port pc[20] WARNING: [Synth 8-3331] design InstructionMemory has unconnected port pc[19] WARNING: [Synth 8-3331] design InstructionMemory has unconnected port pc[18] WARNING: [Synth 8-3331] design InstructionMemory has unconnected port pc[17] WARNING: [Synth 8-3331] design InstructionMemory has unconnected port pc[16] WARNING: [Synth 8-3331] design InstructionMemory has unconnected port pc[15] WARNING: [Synth 8-3331] design InstructionMemory has unconnected port pc[14] WARNING: [Synth 8-3331] design InstructionMemory has unconnected port pc[13] WARNING: [Synth 8-3331] design InstructionMemory has unconnected port pc[12] WARNING: [Synth 8-3331] design InstructionMemory has unconnected port pc[11] WARNING: [Synth 8-3331] design InstructionMemory has unconnected port pc[10] WARNING: [Synth 8-3331] design InstructionMemory has unconnected port pc[9] WARNING: [Synth 8-3331] design InstructionMemory has unconnected port pc[8] WARNING: [Synth 8-3331] design InstructionMemory has unconnected port pc[7] WARNING: [Synth 8-3331] design InstructionMemory has unconnected port pc[6] WARNING: [Synth 8-3331] design InstructionMemory has unconnected port pc[1] WARNING: [Synth 8-3331] design InstructionMemory has unconnected port pc[0] --------------------------------------------------------------------------------- Finished RTL Elaboration : Time (s): cpu = 01:11:24 ; elapsed = 34:19:07 . Memory (MB): peak = 1419.508 ; gain = 1212.418 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Finished RTL Optimization Phase 1 : Time (s): cpu = 01:11:25 ; elapsed = 34:19:08 . Memory (MB): peak = 1419.508 ; gain = 1212.418 --------------------------------------------------------------------------------- INFO: [Project 1-570] Preparing netlist for logic optimization Processing XDC Constraints Initializing timing engine Completed Processing XDC Constraints INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. RTL Elaboration Complete: : Time (s): cpu = 01:11:39 ; elapsed = 34:19:21 . Memory (MB): peak = 1534.602 ; gain = 1327.512 40 Infos, 56 Warnings, 100 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:25 ; elapsed = 00:00:28 . Memory (MB): peak = 1534.602 ; gain = 115.094 close_design set_property is_enabled false [get_files C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v] update_compile_order -fileset sources_1 update_compile_order -fileset sim_1 update_compile_order -fileset sources_1 set_property is_enabled true [get_files C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v] update_compile_order -fileset sources_1 update_compile_order -fileset sim_1 update_compile_order -fileset sources_1 add_files -norecurse C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/instruction_coder.v update_compile_order -fileset sources_1 add_files -norecurse {C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/reg_group.v C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Sim_simpleALU.v C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ConnectRamAndReg.v C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ram.v} update_compile_order -fileset sources_1 add_files -norecurse C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALU2.v WARNING: [filemgmt 56-12] File 'C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALU2.v' cannot be added to the project because it already exists in the project, skipping this file add_files -norecurse C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SimpleALU.v update_compile_order -fileset sources_1 remove_files C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Sim_simpleALU.v set_property top instruction_coder [get_filesets sim_1] set_property top_lib xil_defaultlib [get_filesets sim_1] set_property top ConnectRamAndReg [current_fileset] update_compile_order -fileset sources_1 synth_design -rtl -name rtl_1 Command: synth_design -rtl -name rtl_1 Starting synth_design Using part: xc7z030sbg485-1 Top: ConnectRamAndReg --------------------------------------------------------------------------------- Starting RTL Elaboration : Time (s): cpu = 01:12:40 ; elapsed = 34:28:54 . Memory (MB): peak = 1534.602 ; gain = 1327.512 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'ConnectRamAndReg' [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ConnectRamAndReg.v:23] INFO: [Synth 8-638] synthesizing module 'ram' [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ram.v:23] INFO: [Synth 8-256] done synthesizing module 'ram' (1#1) [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ram.v:23] INFO: [Synth 8-638] synthesizing module 'reg_group' [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/reg_group.v:23] WARNING: [Synth 8-324] index 10 out of range [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/reg_group.v:39] WARNING: [Synth 8-324] index 11 out of range [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/reg_group.v:39] WARNING: [Synth 8-324] index 12 out of range [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/reg_group.v:39] WARNING: [Synth 8-324] index 13 out of range [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/reg_group.v:39] WARNING: [Synth 8-324] index 14 out of range [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/reg_group.v:39] WARNING: [Synth 8-324] index 15 out of range [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/reg_group.v:39] WARNING: [Synth 8-5788] Register dataout_reg in module reg_group is has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/reg_group.v:45] INFO: [Synth 8-256] done synthesizing module 'reg_group' (2#1) [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/reg_group.v:23] INFO: [Synth 8-256] done synthesizing module 'ConnectRamAndReg' (3#1) [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ConnectRamAndReg.v:23] --------------------------------------------------------------------------------- Finished RTL Elaboration : Time (s): cpu = 01:12:41 ; elapsed = 34:28:56 . Memory (MB): peak = 1534.602 ; gain = 1327.512 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Finished RTL Optimization Phase 1 : Time (s): cpu = 01:12:41 ; elapsed = 34:28:57 . Memory (MB): peak = 1534.602 ; gain = 1327.512 --------------------------------------------------------------------------------- INFO: [Project 1-570] Preparing netlist for logic optimization Processing XDC Constraints Initializing timing engine Completed Processing XDC Constraints INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. RTL Elaboration Complete: : Time (s): cpu = 01:12:57 ; elapsed = 34:29:05 . Memory (MB): peak = 1567.352 ; gain = 1360.262 9 Infos, 7 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:25 ; elapsed = 00:00:19 . Memory (MB): peak = 1567.352 ; gain = 32.750 close_design set_property top instruction_coder [current_fileset] update_compile_order -fileset sources_1 synth_design -rtl -name rtl_1 Command: synth_design -rtl -name rtl_1 Starting synth_design Using part: xc7z030sbg485-1 Top: instruction_coder --------------------------------------------------------------------------------- Starting RTL Elaboration : Time (s): cpu = 01:13:33 ; elapsed = 34:33:34 . Memory (MB): peak = 1567.352 ; gain = 1360.262 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'instruction_coder' [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/instruction_coder.v:23] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/instruction_coder.v:34] INFO: [Synth 8-638] synthesizing module 'ConnectRamAndReg' [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ConnectRamAndReg.v:23] INFO: [Synth 8-638] synthesizing module 'ram' [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ram.v:23] INFO: [Synth 8-256] done synthesizing module 'ram' (1#1) [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ram.v:23] INFO: [Synth 8-638] synthesizing module 'reg_group' [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/reg_group.v:23] WARNING: [Synth 8-324] index 10 out of range [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/reg_group.v:39] WARNING: [Synth 8-324] index 11 out of range [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/reg_group.v:39] WARNING: [Synth 8-324] index 12 out of range [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/reg_group.v:39] WARNING: [Synth 8-324] index 13 out of range [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/reg_group.v:39] WARNING: [Synth 8-324] index 14 out of range [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/reg_group.v:39] WARNING: [Synth 8-324] index 15 out of range [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/reg_group.v:39] WARNING: [Synth 8-5788] Register dataout_reg in module reg_group is has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/reg_group.v:45] INFO: [Synth 8-256] done synthesizing module 'reg_group' (2#1) [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/reg_group.v:23] INFO: [Synth 8-256] done synthesizing module 'ConnectRamAndReg' (3#1) [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ConnectRamAndReg.v:23] WARNING: [Synth 8-689] width (3) of port connection 'en' does not match port width (1) of module 'ConnectRamAndReg' [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/instruction_coder.v:34] WARNING: [Synth 8-689] width (4) of port connection 'op' does not match port width (3) of module 'ConnectRamAndReg' [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/instruction_coder.v:34] WARNING: [Synth 8-350] instance 'storage' of module 'ConnectRamAndReg' requires 7 connections, but only 6 given [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/instruction_coder.v:34] INFO: [Synth 8-638] synthesizing module 'SimpleALU' [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SimpleALU.v:23] INFO: [Synth 8-256] done synthesizing module 'SimpleALU' (4#1) [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SimpleALU.v:23] ERROR: [Synth 8-685] variable 'calculationout' should not be used in output port connection [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/instruction_coder.v:39] ERROR: [Synth 8-285] failed synthesizing module 'instruction_coder' [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/instruction_coder.v:23] --------------------------------------------------------------------------------- Finished RTL Elaboration : Time (s): cpu = 01:13:35 ; elapsed = 34:33:35 . Memory (MB): peak = 1567.352 ; gain = 1360.262 --------------------------------------------------------------------------------- RTL Elaboration failed 9 Infos, 11 Warnings, 0 Critical Warnings and 3 Errors encountered. synth_design failed ERROR: [Vivado_Tcl 4-5] Elaboration failed - please see the console for details add_files -norecurse C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Sim_simpleALU.v update_compile_order -fileset sources_1 synth_design -rtl -name rtl_1 Command: synth_design -rtl -name rtl_1 Starting synth_design Using part: xc7z030sbg485-1 Top: instruction_coder --------------------------------------------------------------------------------- Starting RTL Elaboration : Time (s): cpu = 01:14:01 ; elapsed = 34:35:23 . Memory (MB): peak = 1567.352 ; gain = 1360.262 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'instruction_coder' [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/instruction_coder.v:23] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/instruction_coder.v:34] INFO: [Synth 8-638] synthesizing module 'ConnectRamAndReg' [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ConnectRamAndReg.v:23] INFO: [Synth 8-638] synthesizing module 'ram' [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ram.v:23] INFO: [Synth 8-256] done synthesizing module 'ram' (1#1) [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ram.v:23] INFO: [Synth 8-638] synthesizing module 'reg_group' [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/reg_group.v:23] WARNING: [Synth 8-324] index 10 out of range [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/reg_group.v:39] WARNING: [Synth 8-324] index 11 out of range [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/reg_group.v:39] WARNING: [Synth 8-324] index 12 out of range [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/reg_group.v:39] WARNING: [Synth 8-324] index 13 out of range [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/reg_group.v:39] WARNING: [Synth 8-324] index 14 out of range [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/reg_group.v:39] WARNING: [Synth 8-324] index 15 out of range [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/reg_group.v:39] WARNING: [Synth 8-5788] Register dataout_reg in module reg_group is has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/reg_group.v:45] INFO: [Synth 8-256] done synthesizing module 'reg_group' (2#1) [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/reg_group.v:23] INFO: [Synth 8-256] done synthesizing module 'ConnectRamAndReg' (3#1) [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ConnectRamAndReg.v:23] WARNING: [Synth 8-689] width (3) of port connection 'en' does not match port width (1) of module 'ConnectRamAndReg' [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/instruction_coder.v:34] WARNING: [Synth 8-689] width (4) of port connection 'op' does not match port width (3) of module 'ConnectRamAndReg' [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/instruction_coder.v:34] WARNING: [Synth 8-350] instance 'storage' of module 'ConnectRamAndReg' requires 7 connections, but only 6 given [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/instruction_coder.v:34] INFO: [Synth 8-638] synthesizing module 'SimpleALU' [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SimpleALU.v:23] INFO: [Synth 8-256] done synthesizing module 'SimpleALU' (4#1) [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SimpleALU.v:23] WARNING: [Synth 8-3848] Net out in module/entity instruction_coder does not have driver. [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/instruction_coder.v:27] WARNING: [Synth 8-3848] Net storageout in module/entity instruction_coder does not have driver. [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/instruction_coder.v:33] INFO: [Synth 8-256] done synthesizing module 'instruction_coder' (5#1) [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/instruction_coder.v:23] WARNING: [Synth 8-3331] design instruction_coder has unconnected port out[3] WARNING: [Synth 8-3331] design instruction_coder has unconnected port out[2] WARNING: [Synth 8-3331] design instruction_coder has unconnected port out[1] WARNING: [Synth 8-3331] design instruction_coder has unconnected port out[0] --------------------------------------------------------------------------------- Finished RTL Elaboration : Time (s): cpu = 01:14:02 ; elapsed = 34:35:25 . Memory (MB): peak = 1567.352 ; gain = 1360.262 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ WARNING: [Synth 8-3295] tying undriven pin storage:in[3] to constant 0 [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/instruction_coder.v:34] WARNING: [Synth 8-3295] tying undriven pin storage:in[2] to constant 0 [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/instruction_coder.v:34] WARNING: [Synth 8-3295] tying undriven pin storage:in[1] to constant 0 [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/instruction_coder.v:34] WARNING: [Synth 8-3295] tying undriven pin storage:in[0] to constant 0 [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/instruction_coder.v:34] --------------------------------------------------------------------------------- Finished RTL Optimization Phase 1 : Time (s): cpu = 01:14:03 ; elapsed = 34:35:25 . Memory (MB): peak = 1567.352 ; gain = 1360.262 --------------------------------------------------------------------------------- INFO: [Project 1-570] Preparing netlist for logic optimization Processing XDC Constraints Initializing timing engine Completed Processing XDC Constraints INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. RTL Elaboration Complete: : Time (s): cpu = 01:14:16 ; elapsed = 34:35:32 . Memory (MB): peak = 1567.352 ; gain = 1360.262 13 Infos, 21 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:23 ; elapsed = 00:00:16 . Memory (MB): peak = 1567.352 ; gain = 0.000 close_design launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'instruction_coder' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj instruction_coder_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/reg_group.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module reg_group INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ram.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ram INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SimpleALU.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module SimpleALU INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ConnectRamAndReg.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ConnectRamAndReg INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/instruction_coder.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module instruction_coder INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl INFO: [USF-XSim-69] 'compile' step finished in '2' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' INFO: [Common 17-41] Interrupt caught. Command should exit soon. Vivado Simulator 2016.2 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: J:/Xilinx/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto 4c388791a4e240948a5554cd0b3617d7 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot instruction_coder_behav xil_defaultlib.instruction_coder xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration WARNING: [VRFC 10-278] actual bit length 3 differs from formal bit length 1 for port en [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/instruction_coder.v:34] Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling module xil_defaultlib.ram Compiling module xil_defaultlib.reg_group Compiling module xil_defaultlib.ConnectRamAndReg Compiling module xil_defaultlib.SimpleALU Compiling module xil_defaultlib.instruction_coder Compiling module xil_defaultlib.glbl Built simulation snapshot instruction_coder_behav INFO: [Common 17-344] 'run_program' was cancelled INFO: [Vivado 12-4704] 'elaborate' step aborted launch_simulation: Time (s): cpu = 00:00:00 ; elapsed = 00:00:07 . Memory (MB): peak = 1567.352 ; gain = 0.000 INFO: [Common 17-344] 'launch_simulation' was cancelled launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'instruction_coder' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj instruction_coder_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/reg_group.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module reg_group INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ram.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ram INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SimpleALU.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module SimpleALU INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ConnectRamAndReg.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ConnectRamAndReg INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/instruction_coder.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module instruction_coder INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl INFO: [USF-XSim-69] 'compile' step finished in '2' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' Vivado Simulator 2016.2 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: J:/Xilinx/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto 4c388791a4e240948a5554cd0b3617d7 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot instruction_coder_behav xil_defaultlib.instruction_coder xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration WARNING: [VRFC 10-278] actual bit length 3 differs from formal bit length 1 for port en [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/instruction_coder.v:34] Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling module xil_defaultlib.ram Compiling module xil_defaultlib.reg_group Compiling module xil_defaultlib.ConnectRamAndReg Compiling module xil_defaultlib.SimpleALU Compiling module xil_defaultlib.instruction_coder Compiling module xil_defaultlib.glbl Built simulation snapshot instruction_coder_behav ****** Webtalk v2016.2 (64-bit) **** SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016 **** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. source C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/xsim.dir/instruction_coder_behav/webtalk/xsim_webtalk.tcl -notrace INFO: [Common 17-206] Exiting Webtalk at Tue Dec 25 02:55:28 2018... run_program: Time (s): cpu = 00:00:00 ; elapsed = 00:00:06 . Memory (MB): peak = 1567.352 ; gain = 0.000 INFO: [USF-XSim-69] 'elaborate' step finished in '6' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' INFO: [USF-XSim-98] *** Running xsim with args "instruction_coder_behav -key {Behavioral:sim_1:Functional:instruction_coder} -tclbatch {instruction_coder.tcl} -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature Vivado Simulator 2016.2 Time resolution is 1 ps source instruction_coder.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns INFO: [USF-XSim-96] XSim completed. Design snapshot 'instruction_coder_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:02 ; elapsed = 00:00:11 . Memory (MB): peak = 1567.352 ; gain = 0.000 close_sim INFO: [Simtcl 6-16] Simulation closed close_sim: Time (s): cpu = 00:00:02 ; elapsed = 00:00:08 . Memory (MB): peak = 1567.352 ; gain = 0.000 add_files -norecurse {C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Sim_ALU.v C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Sim_ConnectRamAndReg.v} update_compile_order -fileset sources_1 close [ open C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Sim_ins.v w ] add_files C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Sim_ins.v update_compile_order -fileset sources_1 exit INFO: [Common 17-206] Exiting Vivado at Tue Dec 25 03:04:22 2018...