#----------------------------------------------------------- # Vivado v2016.2 (64-bit) # SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016 # IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 # Start of session at: Sat Dec 01 21:45:48 2018 # Process ID: 5152 # Current directory: C:/Users/53194/Desktop/project_789 # Command line: vivado.exe -gui_launcher_event rodinguilauncherevent17604 C:\Users\53194\Desktop\project_789\project_78.xpr # Log file: C:/Users/53194/Desktop/project_789/vivado.log # Journal file: C:/Users/53194/Desktop/project_789\vivado.jou #-----------------------------------------------------------start_gui oopen_project C:/Users/53194/Desktop/project_789/project_78.xprSScanning sources...FFinished scanning sourcesIINFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specifiedIINFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'J:/Xilinx/Vivado/2016.2/data/ip'.oopen_project: Time (s): cpu = 00:00:36 ; elapsed = 00:00:34 . Memory (MB): peak = 806.098 ; gain = 185.035uupdate_compile_order -fileset sources_1launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'sim_ram' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj sim_ram_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ram.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ram INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/sim_ram.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module sim_ram INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl INFO: [USF-XSim-69] 'compile' step finished in '5' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' Vivado Simulator 2016.2 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: J:/Xilinx/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto 4c388791a4e240948a5554cd0b3617d7 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot sim_ram_behav xil_defaultlib.sim_ram xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling module xil_defaultlib.ram Compiling module xil_defaultlib.sim_ram Compiling module xil_defaultlib.glbl Built simulation snapshot sim_ram_behav ****** Webtalk v2016.2 (64-bit) **** SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016 **** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. source C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/xsim.dir/sim_ram_behav/webtalk/xsim_webtalk.tcl -notrace INFO: [Common 17-206] Exiting Webtalk at Sat Dec 01 22:13:15 2018... run_program: Time (s): cpu = 00:00:02 ; elapsed = 00:00:16 . Memory (MB): peak = 875.840 ; gain = 0.000 INFO: [USF-XSim-69] 'elaborate' step finished in '17' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' INFO: [USF-XSim-98] *** Running xsim with args "sim_ram_behav -key {Behavioral:sim_1:Functional:sim_ram} -tclbatch {sim_ram.tcl} -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature Vivado Simulator 2016.2 Time resolution is 1 ps source sim_ram.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns INFO: [USF-XSim-96] XSim completed. Design snapshot 'sim_ram_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:09 ; elapsed = 00:00:27 . Memory (MB): peak = 875.840 ; gain = 0.000 close_sim INFO: [Simtcl 6-16] Simulation closed close_sim: Time (s): cpu = 00:00:00 ; elapsed = 00:00:06 . Memory (MB): peak = 875.840 ; gain = 0.000 launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'sim_ram' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj sim_ram_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ram.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ram INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/sim_ram.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module sim_ram INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl INFO: [USF-XSim-69] 'compile' step finished in '1' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' Vivado Simulator 2016.2 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: J:/Xilinx/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto 4c388791a4e240948a5554cd0b3617d7 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot sim_ram_behav xil_defaultlib.sim_ram xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling module xil_defaultlib.ram Compiling module xil_defaultlib.sim_ram Compiling module xil_defaultlib.glbl Built simulation snapshot sim_ram_behav ****** Webtalk v2016.2 (64-bit) **** SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016 **** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. source C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/xsim.dir/sim_ram_behav/webtalk/xsim_webtalk.tcl -notrace INFO: [Common 17-206] Exiting Webtalk at Sat Dec 01 22:15:09 2018... run_program: Time (s): cpu = 00:00:01 ; elapsed = 00:00:05 . Memory (MB): peak = 875.840 ; gain = 0.000 INFO: [USF-XSim-69] 'elaborate' step finished in '5' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' INFO: [USF-XSim-98] *** Running xsim with args "sim_ram_behav -key {Behavioral:sim_1:Functional:sim_ram} -tclbatch {sim_ram.tcl} -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature Vivado Simulator 2016.2 Time resolution is 1 ps source sim_ram.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns INFO: [USF-XSim-96] XSim completed. Design snapshot 'sim_ram_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:08 ; elapsed = 00:00:12 . Memory (MB): peak = 875.840 ; gain = 0.000 add_bp {C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ram.v} 52 remove_bps -file {C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ram.v} -line 52 add_bp {C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ram.v} 53 remove_bps -file {C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ram.v} -line 53 close_sim INFO: [Simtcl 6-16] Simulation closed launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'sim_ram' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj sim_ram_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ram.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ram INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/sim_ram.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module sim_ram INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl INFO: [USF-XSim-69] 'compile' step finished in '1' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' Vivado Simulator 2016.2 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: J:/Xilinx/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto 4c388791a4e240948a5554cd0b3617d7 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot sim_ram_behav xil_defaultlib.sim_ram xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling module xil_defaultlib.ram Compiling module xil_defaultlib.sim_ram Compiling module xil_defaultlib.glbl Built simulation snapshot sim_ram_behav ****** Webtalk v2016.2 (64-bit) **** SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016 **** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. source C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/xsim.dir/sim_ram_behav/webtalk/xsim_webtalk.tcl -notrace INFO: [Common 17-206] Exiting Webtalk at Sat Dec 01 22:19:42 2018... INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' INFO: [USF-XSim-98] *** Running xsim with args "sim_ram_behav -key {Behavioral:sim_1:Functional:sim_ram} -tclbatch {sim_ram.tcl} -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature Vivado Simulator 2016.2 Time resolution is 1 ps source sim_ram.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns INFO: [USF-XSim-96] XSim completed. Design snapshot 'sim_ram_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:02 ; elapsed = 00:00:06 . Memory (MB): peak = 875.840 ; gain = 0.000 close_sim INFO: [Simtcl 6-16] Simulation closed launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'sim_ram' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj sim_ram_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ram.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ram INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/sim_ram.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module sim_ram INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl INFO: [USF-XSim-69] 'compile' step finished in '1' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' Vivado Simulator 2016.2 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: J:/Xilinx/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto 4c388791a4e240948a5554cd0b3617d7 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot sim_ram_behav xil_defaultlib.sim_ram xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling module xil_defaultlib.ram Compiling module xil_defaultlib.sim_ram Compiling module xil_defaultlib.glbl Built simulation snapshot sim_ram_behav ****** Webtalk v2016.2 (64-bit) **** SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016 **** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. source C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/xsim.dir/sim_ram_behav/webtalk/xsim_webtalk.tcl -notrace INFO: [Common 17-206] Exiting Webtalk at Sat Dec 01 22:22:45 2018... INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' INFO: [USF-XSim-98] *** Running xsim with args "sim_ram_behav -key {Behavioral:sim_1:Functional:sim_ram} -tclbatch {sim_ram.tcl} -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature Vivado Simulator 2016.2 Time resolution is 1 ps source sim_ram.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns INFO: [USF-XSim-96] XSim completed. Design snapshot 'sim_ram_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:02 ; elapsed = 00:00:06 . Memory (MB): peak = 875.840 ; gain = 0.000 update_compile_order -fileset sources_1 close_sim INFO: [Simtcl 6-16] Simulation closed launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'sim_ram' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj sim_ram_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/sim_ram.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module sim_ram INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl INFO: [USF-XSim-69] 'compile' step finished in '1' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' Vivado Simulator 2016.2 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: J:/Xilinx/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto 4c388791a4e240948a5554cd0b3617d7 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot sim_ram_behav xil_defaultlib.sim_ram xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration ERROR: [VRFC 10-2063] Module not found while processing module instance [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/sim_ram.v:31] ERROR: [XSIM 43-3322] Static elaboration of top level Verilog design unit(s) in library work failed. INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds INFO: [USF-XSim-99] Step results log file:'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/elaborate.log' ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/elaborate.log' file for more information. ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation. ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors. update_compile_order -fileset sources_1 launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'sim_ram' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj sim_ram_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ram.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ram INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/sim_ram.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module sim_ram INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl INFO: [USF-XSim-69] 'compile' step finished in '1' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' Vivado Simulator 2016.2 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: J:/Xilinx/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto 4c388791a4e240948a5554cd0b3617d7 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot sim_ram_behav xil_defaultlib.sim_ram xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration WARNING: [VRFC 10-1783] select index 9 into bram is out of bounds [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ram.v:59] Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling module xil_defaultlib.ram Compiling module xil_defaultlib.sim_ram Compiling module xil_defaultlib.glbl Built simulation snapshot sim_ram_behav ****** Webtalk v2016.2 (64-bit) **** SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016 **** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. source C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/xsim.dir/sim_ram_behav/webtalk/xsim_webtalk.tcl -notrace INFO: [Common 17-206] Exiting Webtalk at Sat Dec 01 22:26:33 2018... INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' INFO: [USF-XSim-98] *** Running xsim with args "sim_ram_behav -key {Behavioral:sim_1:Functional:sim_ram} -tclbatch {sim_ram.tcl} -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature Vivado Simulator 2016.2 Time resolution is 1 ps source sim_ram.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns INFO: [USF-XSim-96] XSim completed. Design snapshot 'sim_ram_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:01 ; elapsed = 00:00:05 . Memory (MB): peak = 875.840 ; gain = 0.000 close_sim INFO: [Simtcl 6-16] Simulation closed launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'sim_ram' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj sim_ram_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ram.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ram INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/sim_ram.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module sim_ram INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl INFO: [USF-XSim-69] 'compile' step finished in '1' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' Vivado Simulator 2016.2 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: J:/Xilinx/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto 4c388791a4e240948a5554cd0b3617d7 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot sim_ram_behav xil_defaultlib.sim_ram xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration WARNING: [VRFC 10-1783] select index 9 into bram is out of bounds [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ram.v:53] Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling module xil_defaultlib.ram Compiling module xil_defaultlib.sim_ram Compiling module xil_defaultlib.glbl Built simulation snapshot sim_ram_behav ****** Webtalk v2016.2 (64-bit) **** SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016 **** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. source C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/xsim.dir/sim_ram_behav/webtalk/xsim_webtalk.tcl -notrace INFO: [Common 17-206] Exiting Webtalk at Sat Dec 01 22:27:01 2018... INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' INFO: [USF-XSim-98] *** Running xsim with args "sim_ram_behav -key {Behavioral:sim_1:Functional:sim_ram} -tclbatch {sim_ram.tcl} -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature Vivado Simulator 2016.2 Time resolution is 1 ps source sim_ram.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns INFO: [USF-XSim-96] XSim completed. Design snapshot 'sim_ram_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:02 ; elapsed = 00:00:06 . Memory (MB): peak = 875.840 ; gain = 0.000 close_sim INFO: [Simtcl 6-16] Simulation closed launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'sim_ram' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj sim_ram_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ram.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ram INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/sim_ram.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module sim_ram INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl INFO: [USF-XSim-69] 'compile' step finished in '1' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' Vivado Simulator 2016.2 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: J:/Xilinx/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto 4c388791a4e240948a5554cd0b3617d7 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot sim_ram_behav xil_defaultlib.sim_ram xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration WARNING: [VRFC 10-1783] select index 9 into bram is out of bounds [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ram.v:59] Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling module xil_defaultlib.ram Compiling module xil_defaultlib.sim_ram Compiling module xil_defaultlib.glbl Built simulation snapshot sim_ram_behav ****** Webtalk v2016.2 (64-bit) **** SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016 **** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. source C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/xsim.dir/sim_ram_behav/webtalk/xsim_webtalk.tcl -notrace INFO: [Common 17-206] Exiting Webtalk at Sat Dec 01 22:32:27 2018... INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' INFO: [USF-XSim-98] *** Running xsim with args "sim_ram_behav -key {Behavioral:sim_1:Functional:sim_ram} -tclbatch {sim_ram.tcl} -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature Vivado Simulator 2016.2 Time resolution is 1 ps source sim_ram.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns INFO: [USF-XSim-96] XSim completed. Design snapshot 'sim_ram_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:02 ; elapsed = 00:00:06 . Memory (MB): peak = 875.840 ; gain = 0.000 close_sim INFO: [Simtcl 6-16] Simulation closed launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'sim_ram' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj sim_ram_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ram.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ram INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/sim_ram.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module sim_ram INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl INFO: [USF-XSim-69] 'compile' step finished in '1' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' Vivado Simulator 2016.2 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: J:/Xilinx/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto 4c388791a4e240948a5554cd0b3617d7 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot sim_ram_behav xil_defaultlib.sim_ram xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration WARNING: [VRFC 10-1783] select index 9 into bram is out of bounds [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ram.v:59] Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling module xil_defaultlib.ram Compiling module xil_defaultlib.sim_ram Compiling module xil_defaultlib.glbl Built simulation snapshot sim_ram_behav ****** Webtalk v2016.2 (64-bit) **** SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016 **** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. source C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/xsim.dir/sim_ram_behav/webtalk/xsim_webtalk.tcl -notrace INFO: [Common 17-206] Exiting Webtalk at Sat Dec 01 22:33:15 2018... INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' INFO: [USF-XSim-98] *** Running xsim with args "sim_ram_behav -key {Behavioral:sim_1:Functional:sim_ram} -tclbatch {sim_ram.tcl} -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature Vivado Simulator 2016.2 Time resolution is 1 ps source sim_ram.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns INFO: [USF-XSim-96] XSim completed. Design snapshot 'sim_ram_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:02 ; elapsed = 00:00:06 . Memory (MB): peak = 875.840 ; gain = 0.000 close_sim INFO: [Simtcl 6-16] Simulation closed launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'sim_ram' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj sim_ram_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ram.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ram INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/sim_ram.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module sim_ram INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl INFO: [USF-XSim-69] 'compile' step finished in '1' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' Vivado Simulator 2016.2 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: J:/Xilinx/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto 4c388791a4e240948a5554cd0b3617d7 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot sim_ram_behav xil_defaultlib.sim_ram xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration WARNING: [VRFC 10-1783] select index 9 into bram is out of bounds [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ram.v:59] Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling module xil_defaultlib.ram Compiling module xil_defaultlib.sim_ram Compiling module xil_defaultlib.glbl Built simulation snapshot sim_ram_behav ****** Webtalk v2016.2 (64-bit) **** SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016 **** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. source C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/xsim.dir/sim_ram_behav/webtalk/xsim_webtalk.tcl -notrace INFO: [Common 17-206] Exiting Webtalk at Sat Dec 01 22:33:51 2018... INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' INFO: [USF-XSim-98] *** Running xsim with args "sim_ram_behav -key {Behavioral:sim_1:Functional:sim_ram} -tclbatch {sim_ram.tcl} -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature Vivado Simulator 2016.2 Time resolution is 1 ps source sim_ram.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns INFO: [USF-XSim-96] XSim completed. Design snapshot 'sim_ram_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:01 ; elapsed = 00:00:06 . Memory (MB): peak = 875.840 ; gain = 0.000 close_sim INFO: [Simtcl 6-16] Simulation closed launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'sim_ram' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj sim_ram_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ram.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ram INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/sim_ram.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module sim_ram INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl INFO: [USF-XSim-69] 'compile' step finished in '1' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' Vivado Simulator 2016.2 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: J:/Xilinx/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto 4c388791a4e240948a5554cd0b3617d7 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot sim_ram_behav xil_defaultlib.sim_ram xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration WARNING: [VRFC 10-1783] select index 9 into bram is out of bounds [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ram.v:42] WARNING: [VRFC 10-1783] select index 9 into bram is out of bounds [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ram.v:60] Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling module xil_defaultlib.ram Compiling module xil_defaultlib.sim_ram Compiling module xil_defaultlib.glbl Built simulation snapshot sim_ram_behav ****** Webtalk v2016.2 (64-bit) **** SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016 **** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. source C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/xsim.dir/sim_ram_behav/webtalk/xsim_webtalk.tcl -notrace INFO: [Common 17-206] Exiting Webtalk at Sat Dec 01 22:34:44 2018... INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' INFO: [USF-XSim-98] *** Running xsim with args "sim_ram_behav -key {Behavioral:sim_1:Functional:sim_ram} -tclbatch {sim_ram.tcl} -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature Vivado Simulator 2016.2 Time resolution is 1 ps source sim_ram.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns INFO: [USF-XSim-96] XSim completed. Design snapshot 'sim_ram_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:02 ; elapsed = 00:00:06 . Memory (MB): peak = 875.840 ; gain = 0.000 close_sim INFO: [Simtcl 6-16] Simulation closed close [ open C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Sim_test.v w ] add_files C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Sim_test.v update_compile_order -fileset sources_1 set_property top Sim_test [get_filesets sim_1] set_property top_lib xil_defaultlib [get_filesets sim_1] launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'Sim_test' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj Sim_test_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Sim_test.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Sim_test INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl INFO: [USF-XSim-69] 'compile' step finished in '1' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' Vivado Simulator 2016.2 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: J:/Xilinx/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto 4c388791a4e240948a5554cd0b3617d7 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot Sim_test_behav xil_defaultlib.Sim_test xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling module xil_defaultlib.Sim_test Compiling module xil_defaultlib.glbl Built simulation snapshot Sim_test_behav ****** Webtalk v2016.2 (64-bit) **** SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016 **** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. source C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/xsim.dir/Sim_test_behav/webtalk/xsim_webtalk.tcl -notrace INFO: [Common 17-206] Exiting Webtalk at Sat Dec 01 22:40:50 2018... INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' INFO: [USF-XSim-98] *** Running xsim with args "Sim_test_behav -key {Behavioral:sim_1:Functional:Sim_test} -tclbatch {Sim_test.tcl} -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature Vivado Simulator 2016.2 Time resolution is 1 ps source Sim_test.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } WARNING: [Simtcl 6-168] No object found for the given pattern. WARNING: [Add_Wave-1] No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console. # run 1000ns INFO: [USF-XSim-96] XSim completed. Design snapshot 'Sim_test_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:01 ; elapsed = 00:00:06 . Memory (MB): peak = 875.840 ; gain = 0.000 close_sim INFO: [Simtcl 6-16] Simulation closed launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'Sim_test' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj Sim_test_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/test.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module test INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Sim_test.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Sim_test INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl INFO: [USF-XSim-69] 'compile' step finished in '1' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' Vivado Simulator 2016.2 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: J:/Xilinx/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto 4c388791a4e240948a5554cd0b3617d7 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot Sim_test_behav xil_defaultlib.Sim_test xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling module xil_defaultlib.test Compiling module xil_defaultlib.Sim_test Compiling module xil_defaultlib.glbl Built simulation snapshot Sim_test_behav ****** Webtalk v2016.2 (64-bit) **** SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016 **** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. source C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/xsim.dir/Sim_test_behav/webtalk/xsim_webtalk.tcl -notrace INFO: [Common 17-206] Exiting Webtalk at Sat Dec 01 22:41:29 2018... INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' INFO: [USF-XSim-98] *** Running xsim with args "Sim_test_behav -key {Behavioral:sim_1:Functional:Sim_test} -tclbatch {Sim_test.tcl} -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature Vivado Simulator 2016.2 Time resolution is 1 ps source Sim_test.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns INFO: [USF-XSim-96] XSim completed. Design snapshot 'Sim_test_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:01 ; elapsed = 00:00:05 . Memory (MB): peak = 875.840 ; gain = 0.000 close_sim INFO: [Simtcl 6-16] Simulation closed launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'Sim_test' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj Sim_test_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/test.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module test INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Sim_test.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Sim_test INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl INFO: [USF-XSim-69] 'compile' step finished in '1' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' Vivado Simulator 2016.2 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: J:/Xilinx/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto 4c388791a4e240948a5554cd0b3617d7 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot Sim_test_behav xil_defaultlib.Sim_test xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration WARNING: [VRFC 10-1783] select index 9 into bram is out of bounds [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/test.v:31] WARNING: [VRFC 10-1783] select index 9 into bram is out of bounds [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/test.v:33] Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling module xil_defaultlib.test Compiling module xil_defaultlib.Sim_test Compiling module xil_defaultlib.glbl Built simulation snapshot Sim_test_behav ****** Webtalk v2016.2 (64-bit) **** SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016 **** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. source C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/xsim.dir/Sim_test_behav/webtalk/xsim_webtalk.tcl -notrace INFO: [Common 17-206] Exiting Webtalk at Sat Dec 01 22:43:47 2018... INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' INFO: [USF-XSim-98] *** Running xsim with args "Sim_test_behav -key {Behavioral:sim_1:Functional:Sim_test} -tclbatch {Sim_test.tcl} -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature Vivado Simulator 2016.2 Time resolution is 1 ps source Sim_test.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns INFO: [USF-XSim-96] XSim completed. Design snapshot 'Sim_test_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:02 ; elapsed = 00:00:06 . Memory (MB): peak = 875.840 ; gain = 0.000 close_sim INFO: [Simtcl 6-16] Simulation closed launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'Sim_test' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj Sim_test_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/test.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module test INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Sim_test.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Sim_test INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl INFO: [USF-XSim-69] 'compile' step finished in '1' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' Vivado Simulator 2016.2 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: J:/Xilinx/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto 4c388791a4e240948a5554cd0b3617d7 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot Sim_test_behav xil_defaultlib.Sim_test xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling module xil_defaultlib.test Compiling module xil_defaultlib.Sim_test Compiling module xil_defaultlib.glbl Built simulation snapshot Sim_test_behav ****** Webtalk v2016.2 (64-bit) **** SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016 **** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. source C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/xsim.dir/Sim_test_behav/webtalk/xsim_webtalk.tcl -notrace INFO: [Common 17-206] Exiting Webtalk at Sat Dec 01 22:45:10 2018... INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' INFO: [USF-XSim-98] *** Running xsim with args "Sim_test_behav -key {Behavioral:sim_1:Functional:Sim_test} -tclbatch {Sim_test.tcl} -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature Vivado Simulator 2016.2 Time resolution is 1 ps source Sim_test.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns INFO: [USF-XSim-96] XSim completed. Design snapshot 'Sim_test_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:02 ; elapsed = 00:00:06 . Memory (MB): peak = 875.840 ; gain = 0.000 close_sim INFO: [Simtcl 6-16] Simulation closed launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'Sim_test' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj Sim_test_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/test.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module test INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Sim_test.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Sim_test INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl INFO: [USF-XSim-69] 'compile' step finished in '1' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' Vivado Simulator 2016.2 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: J:/Xilinx/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto 4c388791a4e240948a5554cd0b3617d7 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot Sim_test_behav xil_defaultlib.Sim_test xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration WARNING: [VRFC 10-1783] select index 9 into bram is out of bounds [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/test.v:31] WARNING: [VRFC 10-1783] select index 9 into bram is out of bounds [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/test.v:33] Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling module xil_defaultlib.test Compiling module xil_defaultlib.Sim_test Compiling module xil_defaultlib.glbl Built simulation snapshot Sim_test_behav ****** Webtalk v2016.2 (64-bit) **** SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016 **** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. source C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/xsim.dir/Sim_test_behav/webtalk/xsim_webtalk.tcl -notrace INFO: [Common 17-206] Exiting Webtalk at Sat Dec 01 22:45:50 2018... INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' INFO: [USF-XSim-98] *** Running xsim with args "Sim_test_behav -key {Behavioral:sim_1:Functional:Sim_test} -tclbatch {Sim_test.tcl} -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature Vivado Simulator 2016.2 Time resolution is 1 ps source Sim_test.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns INFO: [USF-XSim-96] XSim completed. Design snapshot 'Sim_test_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:02 ; elapsed = 00:00:06 . Memory (MB): peak = 875.840 ; gain = 0.000 close_sim INFO: [Simtcl 6-16] Simulation closed launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'Sim_test' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj Sim_test_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/test.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module test INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Sim_test.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Sim_test INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl INFO: [USF-XSim-69] 'compile' step finished in '1' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' Vivado Simulator 2016.2 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: J:/Xilinx/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto 4c388791a4e240948a5554cd0b3617d7 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot Sim_test_behav xil_defaultlib.Sim_test xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration WARNING: [VRFC 10-1783] select index 9 into bram is out of bounds [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/test.v:31] WARNING: [VRFC 10-1783] select index 9 into bram is out of bounds [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/test.v:32] Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling module xil_defaultlib.test Compiling module xil_defaultlib.Sim_test Compiling module xil_defaultlib.glbl Built simulation snapshot Sim_test_behav ****** Webtalk v2016.2 (64-bit) **** SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016 **** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. source C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/xsim.dir/Sim_test_behav/webtalk/xsim_webtalk.tcl -notrace INFO: [Common 17-206] Exiting Webtalk at Sat Dec 01 22:46:31 2018... INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' INFO: [USF-XSim-98] *** Running xsim with args "Sim_test_behav -key {Behavioral:sim_1:Functional:Sim_test} -tclbatch {Sim_test.tcl} -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature Vivado Simulator 2016.2 Time resolution is 1 ps source Sim_test.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns INFO: [USF-XSim-96] XSim completed. Design snapshot 'Sim_test_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:01 ; elapsed = 00:00:06 . Memory (MB): peak = 875.840 ; gain = 0.000 close_sim INFO: [Simtcl 6-16] Simulation closed close_sim: Time (s): cpu = 00:00:01 ; elapsed = 00:00:05 . Memory (MB): peak = 875.840 ; gain = 0.000 launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'Sim_test' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj Sim_test_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/test.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module test INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Sim_test.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Sim_test INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl INFO: [USF-XSim-69] 'compile' step finished in '2' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' Vivado Simulator 2016.2 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: J:/Xilinx/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto 4c388791a4e240948a5554cd0b3617d7 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot Sim_test_behav xil_defaultlib.Sim_test xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling module xil_defaultlib.test Compiling module xil_defaultlib.Sim_test Compiling module xil_defaultlib.glbl Built simulation snapshot Sim_test_behav ****** Webtalk v2016.2 (64-bit) **** SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016 **** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. source C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/xsim.dir/Sim_test_behav/webtalk/xsim_webtalk.tcl -notrace INFO: [Common 17-206] Exiting Webtalk at Sat Dec 01 22:51:16 2018... run_program: Time (s): cpu = 00:00:01 ; elapsed = 00:00:05 . Memory (MB): peak = 875.840 ; gain = 0.000 INFO: [USF-XSim-69] 'elaborate' step finished in '5' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' INFO: [USF-XSim-98] *** Running xsim with args "Sim_test_behav -key {Behavioral:sim_1:Functional:Sim_test} -tclbatch {Sim_test.tcl} -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature Vivado Simulator 2016.2 Time resolution is 1 ps source Sim_test.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns INFO: [USF-XSim-96] XSim completed. Design snapshot 'Sim_test_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:03 ; elapsed = 00:00:11 . Memory (MB): peak = 875.840 ; gain = 0.000 close_sim INFO: [Simtcl 6-16] Simulation closed close_sim: Time (s): cpu = 00:00:00 ; elapsed = 00:00:06 . Memory (MB): peak = 875.840 ; gain = 0.000 launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'Sim_test' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj Sim_test_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/test.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module test INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Sim_test.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Sim_test INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl INFO: [USF-XSim-69] 'compile' step finished in '3' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' Vivado Simulator 2016.2 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: J:/Xilinx/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto 4c388791a4e240948a5554cd0b3617d7 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot Sim_test_behav xil_defaultlib.Sim_test xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration WARNING: [VRFC 10-1783] select index 9 into bram is out of bounds [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/test.v:31] WARNING: [VRFC 10-1783] select index 9 into bram is out of bounds [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/test.v:33] Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling module xil_defaultlib.test Compiling module xil_defaultlib.Sim_test Compiling module xil_defaultlib.glbl Built simulation snapshot Sim_test_behav ****** Webtalk v2016.2 (64-bit) **** SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016 **** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. source C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/xsim.dir/Sim_test_behav/webtalk/xsim_webtalk.tcl -notrace INFO: [Common 17-206] Exiting Webtalk at Sat Dec 01 22:53:33 2018... run_program: Time (s): cpu = 00:00:00 ; elapsed = 00:00:05 . Memory (MB): peak = 875.840 ; gain = 0.000 INFO: [USF-XSim-69] 'elaborate' step finished in '5' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' INFO: [USF-XSim-98] *** Running xsim with args "Sim_test_behav -key {Behavioral:sim_1:Functional:Sim_test} -tclbatch {Sim_test.tcl} -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature Vivado Simulator 2016.2 Time resolution is 1 ps source Sim_test.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns INFO: [USF-XSim-96] XSim completed. Design snapshot 'Sim_test_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:04 ; elapsed = 00:00:12 . Memory (MB): peak = 875.840 ; gain = 0.000 close_sim INFO: [Simtcl 6-16] Simulation closed close_sim: Time (s): cpu = 00:00:02 ; elapsed = 00:00:06 . Memory (MB): peak = 875.840 ; gain = 0.000 set_property top Sim_Reg_group [get_filesets sim_1] set_property top_lib xil_defaultlib [get_filesets sim_1] launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'Sim_Reg_group' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj Sim_Reg_group_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/reg_group.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module reg_group INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Sim_Reg_group.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Sim_Reg_group INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl INFO: [USF-XSim-69] 'compile' step finished in '1' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' Vivado Simulator 2016.2 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: J:/Xilinx/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto 4c388791a4e240948a5554cd0b3617d7 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot Sim_Reg_group_behav xil_defaultlib.Sim_Reg_group xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling module xil_defaultlib.reg_group Compiling module xil_defaultlib.Sim_Reg_group Compiling module xil_defaultlib.glbl Built simulation snapshot Sim_Reg_group_behav ****** Webtalk v2016.2 (64-bit) **** SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016 **** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. source C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/xsim.dir/Sim_Reg_group_behav/webtalk/xsim_webtalk.tcl -notrace INFO: [Common 17-206] Exiting Webtalk at Sat Dec 01 22:56:34 2018... INFO: [USF-XSim-69] 'elaborate' step finished in '4' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' INFO: [USF-XSim-98] *** Running xsim with args "Sim_Reg_group_behav -key {Behavioral:sim_1:Functional:Sim_Reg_group} -tclbatch {Sim_Reg_group.tcl} -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature Vivado Simulator 2016.2 Time resolution is 1 ps source Sim_Reg_group.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns INFO: [USF-XSim-96] XSim completed. Design snapshot 'Sim_Reg_group_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:02 ; elapsed = 00:00:08 . Memory (MB): peak = 875.840 ; gain = 0.000 close_sim INFO: [Simtcl 6-16] Simulation closed close_sim: Time (s): cpu = 00:00:01 ; elapsed = 00:00:08 . Memory (MB): peak = 875.840 ; gain = 0.000 exit INFO: [Common 17-206] Exiting Vivado at Sat Dec 01 23:05:46 2018...